Config.in.arm 23 KB

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  1. # arm cpu features
  2. config BR2_ARM_CPU_HAS_NEON
  3. bool
  4. # for some cores, NEON support is optional
  5. config BR2_ARM_CPU_MAYBE_HAS_NEON
  6. bool
  7. # for some cores, VFPv2 is optional
  8. config BR2_ARM_CPU_MAYBE_HAS_VFPV2
  9. bool
  10. config BR2_ARM_CPU_HAS_VFPV2
  11. bool
  12. # for some cores, VFPv3 is optional
  13. config BR2_ARM_CPU_MAYBE_HAS_VFPV3
  14. bool
  15. select BR2_ARM_CPU_MAYBE_HAS_VFPV2
  16. config BR2_ARM_CPU_HAS_VFPV3
  17. bool
  18. select BR2_ARM_CPU_HAS_VFPV2
  19. # for some cores, VFPv4 is optional
  20. config BR2_ARM_CPU_MAYBE_HAS_VFPV4
  21. bool
  22. select BR2_ARM_CPU_MAYBE_HAS_VFPV3
  23. config BR2_ARM_CPU_HAS_VFPV4
  24. bool
  25. select BR2_ARM_CPU_HAS_VFPV3
  26. config BR2_ARM_CPU_HAS_FP_ARMV8
  27. bool
  28. select BR2_ARM_CPU_HAS_VFPV4
  29. config BR2_ARM_CPU_HAS_ARM
  30. bool
  31. config BR2_ARM_CPU_HAS_THUMB
  32. bool
  33. config BR2_ARM_CPU_HAS_THUMB2
  34. bool
  35. config BR2_ARM_CPU_ARMV4
  36. bool
  37. config BR2_ARM_CPU_ARMV5
  38. bool
  39. config BR2_ARM_CPU_ARMV6
  40. bool
  41. config BR2_ARM_CPU_ARMV7A
  42. bool
  43. config BR2_ARM_CPU_ARMV7M
  44. bool
  45. config BR2_ARM_CPU_ARMV8A
  46. bool
  47. choice
  48. prompt "Target Architecture Variant"
  49. default BR2_cortex_a53 if BR2_ARCH_IS_64
  50. default BR2_arm926t
  51. help
  52. Specific CPU variant to use
  53. if !BR2_ARCH_IS_64
  54. comment "armv4 cores"
  55. config BR2_arm920t
  56. bool "arm920t"
  57. select BR2_ARM_CPU_HAS_ARM
  58. select BR2_ARM_CPU_HAS_THUMB
  59. select BR2_ARM_CPU_ARMV4
  60. select BR2_ARCH_HAS_MMU_OPTIONAL
  61. config BR2_arm922t
  62. bool "arm922t"
  63. select BR2_ARM_CPU_HAS_ARM
  64. select BR2_ARM_CPU_HAS_THUMB
  65. select BR2_ARM_CPU_ARMV4
  66. select BR2_ARCH_HAS_MMU_OPTIONAL
  67. config BR2_fa526
  68. bool "fa526/626"
  69. select BR2_ARM_CPU_HAS_ARM
  70. select BR2_ARM_CPU_ARMV4
  71. select BR2_ARCH_HAS_MMU_OPTIONAL
  72. config BR2_strongarm
  73. bool "strongarm sa110/sa1100"
  74. select BR2_ARM_CPU_HAS_ARM
  75. select BR2_ARM_CPU_ARMV4
  76. select BR2_ARCH_HAS_MMU_OPTIONAL
  77. comment "armv5 cores"
  78. config BR2_arm926t
  79. bool "arm926t"
  80. select BR2_ARM_CPU_HAS_ARM
  81. select BR2_ARM_CPU_MAYBE_HAS_VFPV2
  82. select BR2_ARM_CPU_HAS_THUMB
  83. select BR2_ARM_CPU_ARMV5
  84. select BR2_ARCH_HAS_MMU_OPTIONAL
  85. config BR2_iwmmxt
  86. bool "iwmmxt"
  87. select BR2_ARM_CPU_HAS_ARM
  88. select BR2_ARM_CPU_ARMV5
  89. select BR2_ARCH_HAS_MMU_OPTIONAL
  90. config BR2_xscale
  91. bool "xscale"
  92. select BR2_ARM_CPU_HAS_ARM
  93. select BR2_ARM_CPU_HAS_THUMB
  94. select BR2_ARM_CPU_ARMV5
  95. select BR2_ARCH_HAS_MMU_OPTIONAL
  96. comment "armv6 cores"
  97. config BR2_arm1136j_s
  98. bool "arm1136j-s"
  99. select BR2_ARM_CPU_HAS_ARM
  100. select BR2_ARM_CPU_HAS_THUMB
  101. select BR2_ARM_CPU_ARMV6
  102. select BR2_ARCH_HAS_MMU_OPTIONAL
  103. config BR2_arm1136jf_s
  104. bool "arm1136jf-s"
  105. select BR2_ARM_CPU_HAS_ARM
  106. select BR2_ARM_CPU_HAS_VFPV2
  107. select BR2_ARM_CPU_HAS_THUMB
  108. select BR2_ARM_CPU_ARMV6
  109. select BR2_ARCH_HAS_MMU_OPTIONAL
  110. config BR2_arm1176jz_s
  111. bool "arm1176jz-s"
  112. select BR2_ARM_CPU_HAS_ARM
  113. select BR2_ARM_CPU_HAS_THUMB
  114. select BR2_ARM_CPU_ARMV6
  115. select BR2_ARCH_HAS_MMU_OPTIONAL
  116. config BR2_arm1176jzf_s
  117. bool "arm1176jzf-s"
  118. select BR2_ARM_CPU_HAS_ARM
  119. select BR2_ARM_CPU_HAS_VFPV2
  120. select BR2_ARM_CPU_HAS_THUMB
  121. select BR2_ARM_CPU_ARMV6
  122. select BR2_ARCH_HAS_MMU_OPTIONAL
  123. config BR2_arm11mpcore
  124. bool "mpcore"
  125. select BR2_ARM_CPU_HAS_ARM
  126. select BR2_ARM_CPU_MAYBE_HAS_VFPV2
  127. select BR2_ARM_CPU_HAS_THUMB
  128. select BR2_ARM_CPU_ARMV6
  129. select BR2_ARCH_HAS_MMU_OPTIONAL
  130. comment "armv7a cores"
  131. config BR2_cortex_a5
  132. bool "cortex-A5"
  133. select BR2_ARM_CPU_HAS_ARM
  134. select BR2_ARM_CPU_MAYBE_HAS_NEON
  135. select BR2_ARM_CPU_MAYBE_HAS_VFPV4
  136. select BR2_ARM_CPU_HAS_THUMB2
  137. select BR2_ARM_CPU_ARMV7A
  138. select BR2_ARCH_HAS_MMU_OPTIONAL
  139. config BR2_cortex_a7
  140. bool "cortex-A7"
  141. select BR2_ARM_CPU_HAS_ARM
  142. select BR2_ARM_CPU_HAS_NEON
  143. select BR2_ARM_CPU_HAS_VFPV4
  144. select BR2_ARM_CPU_HAS_THUMB2
  145. select BR2_ARM_CPU_ARMV7A
  146. select BR2_ARCH_HAS_MMU_OPTIONAL
  147. config BR2_cortex_a8
  148. bool "cortex-A8"
  149. select BR2_ARM_CPU_HAS_ARM
  150. select BR2_ARM_CPU_HAS_NEON
  151. select BR2_ARM_CPU_HAS_VFPV3
  152. select BR2_ARM_CPU_HAS_THUMB2
  153. select BR2_ARM_CPU_ARMV7A
  154. select BR2_ARCH_HAS_MMU_OPTIONAL
  155. config BR2_cortex_a9
  156. bool "cortex-A9"
  157. select BR2_ARM_CPU_HAS_ARM
  158. select BR2_ARM_CPU_MAYBE_HAS_NEON
  159. select BR2_ARM_CPU_MAYBE_HAS_VFPV3
  160. select BR2_ARM_CPU_HAS_THUMB2
  161. select BR2_ARM_CPU_ARMV7A
  162. select BR2_ARCH_HAS_MMU_OPTIONAL
  163. config BR2_cortex_a12
  164. bool "cortex-A12"
  165. select BR2_ARM_CPU_HAS_ARM
  166. select BR2_ARM_CPU_HAS_NEON
  167. select BR2_ARM_CPU_HAS_VFPV4
  168. select BR2_ARM_CPU_HAS_THUMB2
  169. select BR2_ARM_CPU_ARMV7A
  170. select BR2_ARCH_HAS_MMU_OPTIONAL
  171. config BR2_cortex_a15
  172. bool "cortex-A15"
  173. select BR2_ARM_CPU_HAS_ARM
  174. select BR2_ARM_CPU_HAS_NEON
  175. select BR2_ARM_CPU_HAS_VFPV4
  176. select BR2_ARM_CPU_HAS_THUMB2
  177. select BR2_ARM_CPU_ARMV7A
  178. select BR2_ARCH_HAS_MMU_OPTIONAL
  179. config BR2_cortex_a15_a7
  180. bool "cortex-A15/A7 big.LITTLE"
  181. select BR2_ARM_CPU_HAS_ARM
  182. select BR2_ARM_CPU_HAS_NEON
  183. select BR2_ARM_CPU_HAS_VFPV4
  184. select BR2_ARM_CPU_HAS_THUMB2
  185. select BR2_ARM_CPU_ARMV7A
  186. select BR2_ARCH_HAS_MMU_OPTIONAL
  187. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  188. config BR2_cortex_a17
  189. bool "cortex-A17"
  190. select BR2_ARM_CPU_HAS_ARM
  191. select BR2_ARM_CPU_HAS_NEON
  192. select BR2_ARM_CPU_HAS_VFPV4
  193. select BR2_ARM_CPU_HAS_THUMB2
  194. select BR2_ARM_CPU_ARMV7A
  195. select BR2_ARCH_HAS_MMU_OPTIONAL
  196. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  197. config BR2_cortex_a17_a7
  198. bool "cortex-A17/A7 big.LITTLE"
  199. select BR2_ARM_CPU_HAS_ARM
  200. select BR2_ARM_CPU_HAS_NEON
  201. select BR2_ARM_CPU_HAS_VFPV4
  202. select BR2_ARM_CPU_HAS_THUMB2
  203. select BR2_ARM_CPU_ARMV7A
  204. select BR2_ARCH_HAS_MMU_OPTIONAL
  205. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  206. config BR2_pj4
  207. bool "pj4"
  208. select BR2_ARM_CPU_HAS_ARM
  209. select BR2_ARM_CPU_HAS_VFPV3
  210. select BR2_ARM_CPU_ARMV7A
  211. select BR2_ARCH_HAS_MMU_OPTIONAL
  212. comment "armv7m cores"
  213. config BR2_cortex_m3
  214. bool "cortex-M3"
  215. select BR2_ARM_CPU_HAS_THUMB2
  216. select BR2_ARM_CPU_ARMV7M
  217. config BR2_cortex_m4
  218. bool "cortex-M4"
  219. select BR2_ARM_CPU_HAS_THUMB2
  220. select BR2_ARM_CPU_ARMV7M
  221. endif # !BR2_ARCH_IS_64
  222. comment "armv8 cores"
  223. config BR2_cortex_a32
  224. bool "cortex-A32"
  225. depends on !BR2_ARCH_IS_64
  226. select BR2_ARM_CPU_HAS_ARM
  227. select BR2_ARM_CPU_HAS_NEON
  228. select BR2_ARM_CPU_HAS_THUMB2
  229. select BR2_ARM_CPU_HAS_FP_ARMV8
  230. select BR2_ARM_CPU_ARMV8A
  231. select BR2_ARCH_HAS_MMU_OPTIONAL
  232. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  233. config BR2_cortex_a35
  234. bool "cortex-A35"
  235. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  236. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  237. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  238. select BR2_ARM_CPU_HAS_FP_ARMV8
  239. select BR2_ARM_CPU_ARMV8A
  240. select BR2_ARCH_HAS_MMU_OPTIONAL
  241. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  242. config BR2_cortex_a53
  243. bool "cortex-A53"
  244. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  245. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  246. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  247. select BR2_ARM_CPU_HAS_FP_ARMV8
  248. select BR2_ARM_CPU_ARMV8A
  249. select BR2_ARCH_HAS_MMU_OPTIONAL
  250. config BR2_cortex_a57
  251. bool "cortex-A57"
  252. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  253. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  254. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  255. select BR2_ARM_CPU_HAS_FP_ARMV8
  256. select BR2_ARM_CPU_ARMV8A
  257. select BR2_ARCH_HAS_MMU_OPTIONAL
  258. config BR2_cortex_a57_a53
  259. bool "cortex-A57/A53 big.LITTLE"
  260. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  261. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  262. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  263. select BR2_ARM_CPU_HAS_FP_ARMV8
  264. select BR2_ARM_CPU_ARMV8A
  265. select BR2_ARCH_HAS_MMU_OPTIONAL
  266. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  267. config BR2_cortex_a72
  268. bool "cortex-A72"
  269. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  270. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  271. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  272. select BR2_ARM_CPU_HAS_FP_ARMV8
  273. select BR2_ARM_CPU_ARMV8A
  274. select BR2_ARCH_HAS_MMU_OPTIONAL
  275. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  276. config BR2_cortex_a72_a53
  277. bool "cortex-A72/A53 big.LITTLE"
  278. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  279. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  280. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  281. select BR2_ARM_CPU_HAS_FP_ARMV8
  282. select BR2_ARM_CPU_ARMV8A
  283. select BR2_ARCH_HAS_MMU_OPTIONAL
  284. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  285. config BR2_cortex_a73
  286. bool "cortex-A73"
  287. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  288. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  289. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  290. select BR2_ARM_CPU_HAS_FP_ARMV8
  291. select BR2_ARM_CPU_ARMV8A
  292. select BR2_ARCH_HAS_MMU_OPTIONAL
  293. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  294. config BR2_cortex_a73_a35
  295. bool "cortex-A73/A35 big.LITTLE"
  296. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  297. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  298. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  299. select BR2_ARM_CPU_HAS_FP_ARMV8
  300. select BR2_ARM_CPU_ARMV8A
  301. select BR2_ARCH_HAS_MMU_OPTIONAL
  302. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  303. config BR2_cortex_a73_a53
  304. bool "cortex-A73/A53 big.LITTLE"
  305. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  306. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  307. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  308. select BR2_ARM_CPU_HAS_FP_ARMV8
  309. select BR2_ARM_CPU_ARMV8A
  310. select BR2_ARCH_HAS_MMU_OPTIONAL
  311. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  312. config BR2_exynos_m1
  313. bool "exynos-m1"
  314. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  315. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  316. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  317. select BR2_ARM_CPU_HAS_FP_ARMV8
  318. select BR2_ARM_CPU_ARMV8A
  319. select BR2_ARCH_HAS_MMU_OPTIONAL
  320. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  321. config BR2_falkor
  322. bool "falkor"
  323. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  324. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  325. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  326. select BR2_ARM_CPU_HAS_FP_ARMV8
  327. select BR2_ARM_CPU_ARMV8A
  328. select BR2_ARCH_HAS_MMU_OPTIONAL
  329. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  330. config BR2_qdf24xx
  331. bool "qdf24xx"
  332. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  333. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  334. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  335. select BR2_ARM_CPU_HAS_FP_ARMV8
  336. select BR2_ARM_CPU_ARMV8A
  337. select BR2_ARCH_HAS_MMU_OPTIONAL
  338. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  339. if BR2_ARCH_IS_64
  340. config BR2_thunderx
  341. bool "thunderx"
  342. select BR2_ARM_CPU_HAS_FP_ARMV8
  343. select BR2_ARM_CPU_ARMV8A
  344. select BR2_ARCH_HAS_MMU_OPTIONAL
  345. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  346. config BR2_thunderxt81
  347. bool "thunderxt81"
  348. select BR2_ARM_CPU_HAS_FP_ARMV8
  349. select BR2_ARM_CPU_ARMV8A
  350. select BR2_ARCH_HAS_MMU_OPTIONAL
  351. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  352. config BR2_thunderxt83
  353. bool "thunderxt83"
  354. select BR2_ARM_CPU_HAS_FP_ARMV8
  355. select BR2_ARM_CPU_ARMV8A
  356. select BR2_ARCH_HAS_MMU_OPTIONAL
  357. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  358. config BR2_thunderxt88
  359. bool "thunderxt88"
  360. select BR2_ARM_CPU_HAS_FP_ARMV8
  361. select BR2_ARM_CPU_ARMV8A
  362. select BR2_ARCH_HAS_MMU_OPTIONAL
  363. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  364. config BR2_thunderxt88p1
  365. bool "thunderxt88p1"
  366. select BR2_ARM_CPU_HAS_FP_ARMV8
  367. select BR2_ARM_CPU_ARMV8A
  368. select BR2_ARCH_HAS_MMU_OPTIONAL
  369. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  370. endif # BR2_ARCH_IS_64
  371. config BR2_xgene1
  372. bool "xgene1"
  373. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  374. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  375. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  376. select BR2_ARM_CPU_HAS_FP_ARMV8
  377. select BR2_ARM_CPU_ARMV8A
  378. select BR2_ARCH_HAS_MMU_OPTIONAL
  379. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  380. if BR2_ARCH_IS_64
  381. comment "armv8.1a cores"
  382. config BR2_thunderx2t99
  383. bool "thunderx2t99"
  384. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  385. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  386. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  387. select BR2_ARM_CPU_HAS_FP_ARMV8
  388. select BR2_ARM_CPU_ARMV8A
  389. select BR2_ARCH_HAS_MMU_OPTIONAL
  390. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  391. config BR2_thunderx2t99p1
  392. bool "thunderx2t99p1"
  393. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  394. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  395. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  396. select BR2_ARM_CPU_HAS_FP_ARMV8
  397. select BR2_ARM_CPU_ARMV8A
  398. select BR2_ARCH_HAS_MMU_OPTIONAL
  399. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  400. config BR2_vulcan
  401. bool "vulcan"
  402. select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
  403. select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
  404. select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
  405. select BR2_ARM_CPU_HAS_FP_ARMV8
  406. select BR2_ARM_CPU_ARMV8A
  407. select BR2_ARCH_HAS_MMU_OPTIONAL
  408. select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  409. endif # BR2_ARCH_IS_64
  410. endchoice
  411. config BR2_ARM_ENABLE_NEON
  412. bool "Enable NEON SIMD extension support"
  413. depends on BR2_ARM_CPU_MAYBE_HAS_NEON
  414. select BR2_ARM_CPU_HAS_NEON
  415. help
  416. For some CPU cores, the NEON SIMD extension is optional.
  417. Select this option if you are certain your particular
  418. implementation has NEON support and you want to use it.
  419. config BR2_ARM_ENABLE_VFP
  420. bool "Enable VFP extension support"
  421. depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2
  422. select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
  423. select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
  424. select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
  425. help
  426. For some CPU cores, the VFP extension is optional. Select
  427. this option if you are certain your particular
  428. implementation has VFP support and you want to use it.
  429. choice
  430. prompt "Target ABI"
  431. default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_VFPV2
  432. default BR2_ARM_EABI
  433. depends on BR2_arm || BR2_armeb
  434. help
  435. Application Binary Interface to use. The Application Binary
  436. Interface describes the calling conventions (how arguments
  437. are passed to functions, how the return value is passed, how
  438. system calls are made, etc.).
  439. config BR2_ARM_EABI
  440. bool "EABI"
  441. help
  442. The EABI is currently the standard ARM ABI, which is used in
  443. most projects. It supports both the 'soft' floating point
  444. model (in which floating point instructions are emulated in
  445. software) and the 'softfp' floating point model (in which
  446. floating point instructions are executed using an hardware
  447. floating point unit, but floating point arguments to
  448. functions are passed in integer registers).
  449. The 'softfp' floating point model is link-compatible with
  450. the 'soft' floating point model, i.e you can link a library
  451. built 'soft' with some other code built 'softfp'.
  452. However, passing the floating point arguments in integer
  453. registers is a bit inefficient, so if your ARM processor has
  454. a floating point unit, and you don't have pre-compiled
  455. 'soft' or 'softfp' code, using the EABIhf ABI will provide
  456. better floating point performances.
  457. If your processor does not have a floating point unit, then
  458. you must use this ABI.
  459. config BR2_ARM_EABIHF
  460. bool "EABIhf"
  461. depends on BR2_ARM_CPU_HAS_VFPV2
  462. help
  463. The EABIhf is an extension of EABI which supports the 'hard'
  464. floating point model. This model uses the floating point
  465. unit to execute floating point instructions, and passes
  466. floating point arguments in floating point registers.
  467. It is more efficient than EABI for floating point related
  468. workload. However, it does not allow to link against code
  469. that has been pre-built for the 'soft' or 'softfp' floating
  470. point models.
  471. If your processor has a floating point unit, and you don't
  472. depend on existing pre-compiled code, this option is most
  473. likely the best choice.
  474. endchoice
  475. choice
  476. prompt "Floating point strategy"
  477. default BR2_ARM_FPU_FP_ARMV8 if BR2_ARM_CPU_HAS_FP_ARMV8
  478. default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
  479. default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
  480. default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
  481. default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2
  482. config BR2_ARM_SOFT_FLOAT
  483. bool "Soft float"
  484. depends on BR2_ARM_EABI
  485. select BR2_SOFT_FLOAT
  486. help
  487. This option allows to use software emulated floating
  488. point. It should be used for ARM cores that do not include a
  489. Vector Floating Point unit, such as ARMv5 cores (ARM926 for
  490. example) or certain ARMv6 cores.
  491. config BR2_ARM_FPU_VFPV2
  492. bool "VFPv2"
  493. depends on BR2_ARM_CPU_HAS_VFPV2
  494. help
  495. This option allows to use the VFPv2 floating point unit, as
  496. available in some ARMv5 processors (ARM926EJ-S) and some
  497. ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
  498. MPCore).
  499. Note that this option is also safe to use for newer cores
  500. such as Cortex-A, because the VFPv3 and VFPv4 units are
  501. backward compatible with VFPv2.
  502. config BR2_ARM_FPU_VFPV3
  503. bool "VFPv3"
  504. depends on BR2_ARM_CPU_HAS_VFPV3
  505. help
  506. This option allows to use the VFPv3 floating point unit, as
  507. available in some ARMv7 processors (Cortex-A{8, 9}). This
  508. option requires a VFPv3 unit that has 32 double-precision
  509. registers, which is not necessarily the case in all SOCs
  510. based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16
  511. instead, which is guaranteed to work on all Cortex-A{8, 9}.
  512. Note that this option is also safe to use for newer cores
  513. that have a VFPv4 unit, because VFPv4 is backward compatible
  514. with VFPv3. They must of course also have 32
  515. double-precision registers.
  516. config BR2_ARM_FPU_VFPV3D16
  517. bool "VFPv3-D16"
  518. depends on BR2_ARM_CPU_HAS_VFPV3
  519. help
  520. This option allows to use the VFPv3 floating point unit, as
  521. available in some ARMv7 processors (Cortex-A{8, 9}). This
  522. option requires a VFPv3 unit that has 16 double-precision
  523. registers, which is generally the case in all SOCs based on
  524. Cortex-A{8, 9}, even though VFPv3 is technically optional on
  525. Cortex-A9. This is the safest option for those cores.
  526. Note that this option is also safe to use for newer cores
  527. such that have a VFPv4 unit, because the VFPv4 is backward
  528. compatible with VFPv3.
  529. config BR2_ARM_FPU_VFPV4
  530. bool "VFPv4"
  531. depends on BR2_ARM_CPU_HAS_VFPV4
  532. help
  533. This option allows to use the VFPv4 floating point unit, as
  534. available in some ARMv7 processors (Cortex-A{5, 7, 12,
  535. 15}). This option requires a VFPv4 unit that has 32
  536. double-precision registers, which is not necessarily the
  537. case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're
  538. unsure, you should probably use VFPv4-D16 instead.
  539. Note that if you want binary code that works on all ARMv7
  540. cores, including the earlier Cortex-A{8, 9}, you should
  541. instead select VFPv3.
  542. config BR2_ARM_FPU_VFPV4D16
  543. bool "VFPv4-D16"
  544. depends on BR2_ARM_CPU_HAS_VFPV4
  545. help
  546. This option allows to use the VFPv4 floating point unit, as
  547. available in some ARMv7 processors (Cortex-A{5, 7, 12,
  548. 15}). This option requires a VFPv4 unit that has 16
  549. double-precision registers, which is always available on
  550. Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and
  551. Cortex-A7.
  552. Note that if you want binary code that works on all ARMv7
  553. cores, including the earlier Cortex-A{8, 9}, you should
  554. instead select VFPv3-D16.
  555. config BR2_ARM_FPU_NEON
  556. bool "NEON"
  557. depends on BR2_ARM_CPU_HAS_NEON
  558. help
  559. This option allows to use the NEON SIMD unit, as available
  560. in some ARMv7 processors, as a floating-point unit. It
  561. should however be noted that using NEON for floating point
  562. operations doesn't provide a complete compatibility with the
  563. IEEE 754.
  564. config BR2_ARM_FPU_NEON_VFPV4
  565. bool "NEON/VFPv4"
  566. depends on BR2_ARM_CPU_HAS_VFPV4
  567. depends on BR2_ARM_CPU_HAS_NEON
  568. help
  569. This option allows to use both the VFPv4 and the NEON SIMD
  570. units for floating point operations. Note that some ARMv7
  571. cores do not necessarily have VFPv4 and/or NEON support, for
  572. example on Cortex-A5 and Cortex-A7, support for VFPv4 and
  573. NEON is optional.
  574. config BR2_ARM_FPU_FP_ARMV8
  575. bool "FP-ARMv8"
  576. depends on BR2_ARM_CPU_HAS_FP_ARMV8
  577. help
  578. This option allows to use the ARMv8 floating point unit.
  579. config BR2_ARM_FPU_NEON_FP_ARMV8
  580. bool "NEON/FP-ARMv8"
  581. depends on BR2_ARM_CPU_HAS_FP_ARMV8
  582. depends on BR2_ARM_CPU_HAS_NEON
  583. help
  584. This option allows to use both the ARMv8 floating point unit
  585. and the NEON SIMD unit for floating point operations.
  586. endchoice
  587. choice
  588. prompt "ARM instruction set"
  589. depends on BR2_arm || BR2_armeb
  590. config BR2_ARM_INSTRUCTIONS_ARM
  591. bool "ARM"
  592. depends on BR2_ARM_CPU_HAS_ARM
  593. help
  594. This option instructs the compiler to generate regular ARM
  595. instructions, that are all 32 bits wide.
  596. config BR2_ARM_INSTRUCTIONS_THUMB
  597. bool "Thumb"
  598. depends on BR2_ARM_CPU_HAS_THUMB
  599. # Thumb-1 and VFP are not compatible
  600. depends on BR2_ARM_SOFT_FLOAT
  601. help
  602. This option instructions the compiler to generate Thumb
  603. instructions, which allows to mix 16 bits instructions and
  604. 32 bits instructions. This generally provides a much smaller
  605. compiled binary size.
  606. comment "Thumb1 is not compatible with VFP"
  607. depends on BR2_ARM_CPU_HAS_THUMB
  608. depends on !BR2_ARM_SOFT_FLOAT
  609. config BR2_ARM_INSTRUCTIONS_THUMB2
  610. bool "Thumb2"
  611. depends on BR2_ARM_CPU_HAS_THUMB2
  612. help
  613. This option instructions the compiler to generate Thumb2
  614. instructions, which allows to mix 16 bits instructions and
  615. 32 bits instructions. This generally provides a much smaller
  616. compiled binary size.
  617. endchoice
  618. config BR2_ARCH
  619. default "arm" if BR2_arm
  620. default "armeb" if BR2_armeb
  621. default "aarch64" if BR2_aarch64
  622. default "aarch64_be" if BR2_aarch64_be
  623. config BR2_ENDIAN
  624. default "LITTLE" if (BR2_arm || BR2_aarch64)
  625. default "BIG" if (BR2_armeb || BR2_aarch64_be)
  626. config BR2_GCC_TARGET_CPU
  627. # armv4
  628. default "arm920t" if BR2_arm920t
  629. default "arm922t" if BR2_arm922t
  630. default "fa526" if BR2_fa526
  631. default "strongarm" if BR2_strongarm
  632. # armv5
  633. default "arm926ej-s" if BR2_arm926t
  634. default "iwmmxt" if BR2_iwmmxt
  635. default "xscale" if BR2_xscale
  636. # armv6
  637. default "arm1136j-s" if BR2_arm1136j_s
  638. default "arm1136jf-s" if BR2_arm1136jf_s
  639. default "arm1176jz-s" if BR2_arm1176jz_s
  640. default "arm1176jzf-s" if BR2_arm1176jzf_s
  641. default "mpcore" if BR2_arm11mpcore && BR2_ARM_CPU_HAS_VFPV2
  642. default "mpcorenovfp" if BR2_arm11mpcore
  643. # armv7a
  644. default "cortex-a5" if BR2_cortex_a5
  645. default "cortex-a7" if BR2_cortex_a7
  646. default "cortex-a8" if BR2_cortex_a8
  647. default "cortex-a9" if BR2_cortex_a9
  648. default "cortex-a12" if BR2_cortex_a12
  649. default "cortex-a15" if BR2_cortex_a15
  650. default "cortex-a15.cortex-a7" if BR2_cortex_a15_a7
  651. default "cortex-a17" if BR2_cortex_a17
  652. default "cortex-a17.cortex-a7" if BR2_cortex_a17_a7
  653. default "marvell-pj4" if BR2_pj4
  654. # armv7m
  655. default "cortex-m3" if BR2_cortex_m3
  656. default "cortex-m4" if BR2_cortex_m4
  657. # armv8a
  658. default "cortex-a32" if BR2_cortex_a32
  659. default "cortex-a35" if BR2_cortex_a35
  660. default "cortex-a53" if BR2_cortex_a53
  661. default "cortex-a57" if BR2_cortex_a57
  662. default "cortex-a57.cortex-a53" if BR2_cortex_a57_a53
  663. default "cortex-a72" if BR2_cortex_a72
  664. default "cortex-a72.cortex-a53" if BR2_cortex_a72_a53
  665. default "cortex-a73" if BR2_cortex_a73
  666. default "cortex-a73.cortex-a35" if BR2_cortex_a73_a35
  667. default "cortex-a73.cortex-a53" if BR2_cortex_a73_a53
  668. default "exynos-m1" if BR2_exynos_m1
  669. default "falkor" if BR2_falkor
  670. default "qdf24xx" if BR2_qdf24xx
  671. default "thunderx" if BR2_thunderx
  672. default "thunderxt81" if BR2_thunderxt81
  673. default "thunderxt83" if BR2_thunderxt83
  674. default "thunderxt88" if BR2_thunderxt88
  675. default "thunderxt88p1" if BR2_thunderxt88p1
  676. default "xgene1" if BR2_xgene1
  677. # armv8.1a
  678. default "thunderx2t99" if BR2_thunderx2t99
  679. default "thunderx2t99p1" if BR2_thunderx2t99p1
  680. default "vulcan" if BR2_vulcan
  681. config BR2_GCC_TARGET_ABI
  682. default "aapcs-linux" if BR2_arm || BR2_armeb
  683. default "lp64" if BR2_aarch64 || BR2_aarch64_be
  684. config BR2_GCC_TARGET_FPU
  685. default "vfp" if BR2_ARM_FPU_VFPV2
  686. default "vfpv3" if BR2_ARM_FPU_VFPV3
  687. default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
  688. default "vfpv4" if BR2_ARM_FPU_VFPV4
  689. default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
  690. default "neon" if BR2_ARM_FPU_NEON
  691. default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
  692. default "fp-armv8" if BR2_ARM_FPU_FP_ARMV8
  693. default "neon-fp-armv8" if BR2_ARM_FPU_NEON_FP_ARMV8
  694. depends on BR2_arm || BR2_armeb
  695. config BR2_GCC_TARGET_FLOAT_ABI
  696. default "soft" if BR2_ARM_SOFT_FLOAT
  697. default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
  698. default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
  699. config BR2_GCC_TARGET_MODE
  700. default "arm" if BR2_ARM_INSTRUCTIONS_ARM
  701. default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2
  702. config BR2_READELF_ARCH_NAME
  703. default "ARM" if BR2_arm || BR2_armeb
  704. default "AArch64" if BR2_aarch64 || BR2_aarch64_be