Config.in 11 KB

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  1. menu "Target options"
  2. config BR2_ARCH_IS_64
  3. bool
  4. config BR2_KERNEL_64_USERLAND_32
  5. bool
  6. config BR2_SOFT_FLOAT
  7. bool
  8. config BR2_ARCH_HAS_MMU_MANDATORY
  9. bool
  10. config BR2_ARCH_HAS_MMU_OPTIONAL
  11. bool
  12. config BR2_ARCH_HAS_FDPIC_SUPPORT
  13. bool
  14. choice
  15. prompt "Target Architecture"
  16. default BR2_i386
  17. help
  18. Select the target architecture family to build for.
  19. config BR2_arcle
  20. bool "ARC (little endian)"
  21. select BR2_ARCH_HAS_MMU_MANDATORY
  22. help
  23. Synopsys' DesignWare ARC Processor Cores are a family of
  24. 32-bit CPUs that can be used from deeply embedded to high
  25. performance host applications. Little endian.
  26. config BR2_arceb
  27. bool "ARC (big endian)"
  28. select BR2_ARCH_HAS_MMU_MANDATORY
  29. help
  30. Synopsys' DesignWare ARC Processor Cores are a family of
  31. 32-bit CPUs that can be used from deeply embedded to high
  32. performance host applications. Big endian.
  33. config BR2_arm
  34. bool "ARM (little endian)"
  35. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  36. help
  37. ARM is a 32-bit reduced instruction set computer (RISC)
  38. instruction set architecture (ISA) developed by ARM Holdings.
  39. Little endian.
  40. http://www.arm.com/
  41. http://en.wikipedia.org/wiki/ARM
  42. config BR2_armeb
  43. bool "ARM (big endian)"
  44. # MMU support is set by the subarchitecture file, arch/Config.in.arm
  45. help
  46. ARM is a 32-bit reduced instruction set computer (RISC)
  47. instruction set architecture (ISA) developed by ARM Holdings.
  48. Big endian.
  49. http://www.arm.com/
  50. http://en.wikipedia.org/wiki/ARM
  51. config BR2_aarch64
  52. bool "AArch64 (little endian)"
  53. select BR2_ARCH_IS_64
  54. select BR2_ARCH_HAS_MMU_MANDATORY
  55. help
  56. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  57. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  58. http://en.wikipedia.org/wiki/ARM
  59. config BR2_aarch64_be
  60. bool "AArch64 (big endian)"
  61. select BR2_ARCH_IS_64
  62. select BR2_ARCH_HAS_MMU_MANDATORY
  63. help
  64. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  65. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  66. http://en.wikipedia.org/wiki/ARM
  67. config BR2_csky
  68. bool "csky"
  69. select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  70. select BR2_ARCH_HAS_MMU_MANDATORY
  71. help
  72. csky is processor IP from china.
  73. http://www.c-sky.com/
  74. http://www.github.com/c-sky
  75. config BR2_i386
  76. bool "i386"
  77. select BR2_ARCH_HAS_MMU_MANDATORY
  78. help
  79. Intel i386 architecture compatible microprocessor
  80. http://en.wikipedia.org/wiki/I386
  81. config BR2_m68k
  82. bool "m68k"
  83. # MMU support is set by the subarchitecture file, arch/Config.in.m68k
  84. help
  85. Motorola 68000 family microprocessor
  86. http://en.wikipedia.org/wiki/M68k
  87. config BR2_microblazeel
  88. bool "Microblaze AXI (little endian)"
  89. select BR2_ARCH_HAS_MMU_MANDATORY
  90. help
  91. Soft processor core designed for Xilinx FPGAs from Xilinx. AXI
  92. bus based architecture (little endian)
  93. http://www.xilinx.com
  94. http://en.wikipedia.org/wiki/Microblaze
  95. config BR2_microblazebe
  96. bool "Microblaze non-AXI (big endian)"
  97. select BR2_ARCH_HAS_MMU_MANDATORY
  98. help
  99. Soft processor core designed for Xilinx FPGAs from Xilinx. PLB
  100. bus based architecture (non-AXI, big endian)
  101. http://www.xilinx.com
  102. http://en.wikipedia.org/wiki/Microblaze
  103. config BR2_mips
  104. bool "MIPS (big endian)"
  105. select BR2_ARCH_HAS_MMU_MANDATORY
  106. help
  107. MIPS is a RISC microprocessor from MIPS Technologies. Big
  108. endian.
  109. http://www.mips.com/
  110. http://en.wikipedia.org/wiki/MIPS_Technologies
  111. config BR2_mipsel
  112. bool "MIPS (little endian)"
  113. select BR2_ARCH_HAS_MMU_MANDATORY
  114. help
  115. MIPS is a RISC microprocessor from MIPS Technologies. Little
  116. endian.
  117. http://www.mips.com/
  118. http://en.wikipedia.org/wiki/MIPS_Technologies
  119. config BR2_mips64
  120. bool "MIPS64 (big endian)"
  121. select BR2_ARCH_IS_64
  122. select BR2_ARCH_HAS_MMU_MANDATORY
  123. help
  124. MIPS is a RISC microprocessor from MIPS Technologies. Big
  125. endian.
  126. http://www.mips.com/
  127. http://en.wikipedia.org/wiki/MIPS_Technologies
  128. config BR2_mips64el
  129. bool "MIPS64 (little endian)"
  130. select BR2_ARCH_IS_64
  131. select BR2_ARCH_HAS_MMU_MANDATORY
  132. help
  133. MIPS is a RISC microprocessor from MIPS Technologies. Little
  134. endian.
  135. http://www.mips.com/
  136. http://en.wikipedia.org/wiki/MIPS_Technologies
  137. config BR2_nios2
  138. bool "Nios II"
  139. select BR2_ARCH_HAS_MMU_MANDATORY
  140. help
  141. Nios II is a soft core processor from Altera Corporation.
  142. http://www.altera.com/
  143. http://en.wikipedia.org/wiki/Nios_II
  144. config BR2_or1k
  145. bool "OpenRISC"
  146. select BR2_ARCH_HAS_MMU_MANDATORY
  147. help
  148. OpenRISC is a free and open processor for embedded system.
  149. http://openrisc.io
  150. config BR2_powerpc
  151. bool "PowerPC"
  152. select BR2_ARCH_HAS_MMU_MANDATORY
  153. help
  154. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  155. alliance. Big endian.
  156. http://www.power.org/
  157. http://en.wikipedia.org/wiki/Powerpc
  158. config BR2_powerpc64
  159. bool "PowerPC64 (big endian)"
  160. select BR2_ARCH_IS_64
  161. select BR2_ARCH_HAS_MMU_MANDATORY
  162. help
  163. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  164. alliance. Big endian.
  165. http://www.power.org/
  166. http://en.wikipedia.org/wiki/Powerpc
  167. config BR2_powerpc64le
  168. bool "PowerPC64 (little endian)"
  169. select BR2_ARCH_IS_64
  170. select BR2_ARCH_HAS_MMU_MANDATORY
  171. help
  172. PowerPC is a RISC architecture created by Apple-IBM-Motorola
  173. alliance. Little endian.
  174. http://www.power.org/
  175. http://en.wikipedia.org/wiki/Powerpc
  176. config BR2_sh
  177. bool "SuperH"
  178. select BR2_ARCH_HAS_MMU_OPTIONAL
  179. help
  180. SuperH (or SH) is a 32-bit reduced instruction set computer
  181. (RISC) instruction set architecture (ISA) developed by
  182. Hitachi.
  183. http://www.hitachi.com/
  184. http://en.wikipedia.org/wiki/SuperH
  185. config BR2_sparc
  186. bool "SPARC"
  187. select BR2_ARCH_HAS_MMU_MANDATORY
  188. help
  189. SPARC (from Scalable Processor Architecture) is a RISC
  190. instruction set architecture (ISA) developed by Sun
  191. Microsystems.
  192. http://www.oracle.com/sun
  193. http://en.wikipedia.org/wiki/Sparc
  194. config BR2_sparc64
  195. bool "SPARC64"
  196. select BR2_ARCH_IS_64
  197. select BR2_ARCH_HAS_MMU_MANDATORY
  198. help
  199. SPARC (from Scalable Processor Architecture) is a RISC
  200. instruction set architecture (ISA) developed by Sun
  201. Microsystems.
  202. http://www.oracle.com/sun
  203. http://en.wikipedia.org/wiki/Sparc
  204. config BR2_x86_64
  205. bool "x86_64"
  206. select BR2_ARCH_IS_64
  207. select BR2_ARCH_HAS_MMU_MANDATORY
  208. help
  209. x86-64 is an extension of the x86 instruction set (Intel i386
  210. architecture compatible microprocessor).
  211. http://en.wikipedia.org/wiki/X86_64
  212. config BR2_xtensa
  213. bool "Xtensa"
  214. # MMU support is set by the subarchitecture file, arch/Config.in.xtensa
  215. help
  216. Xtensa is a Tensilica processor IP architecture.
  217. http://en.wikipedia.org/wiki/Xtensa
  218. http://www.tensilica.com/
  219. endchoice
  220. # For some architectures or specific cores, our internal toolchain
  221. # backend is not suitable (like, missing support in upstream gcc, or
  222. # no ChipCo fork exists...)
  223. config BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  224. bool
  225. config BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT
  226. bool
  227. default y if !BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  228. # The following symbols are selected by the individual
  229. # Config.in.$ARCH files
  230. config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
  231. bool
  232. config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  233. bool
  234. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
  235. config BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  236. bool
  237. select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
  238. config BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  239. bool
  240. select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
  241. config BR2_ARCH_NEEDS_GCC_AT_LEAST_7
  242. bool
  243. select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
  244. # The following string values are defined by the individual
  245. # Config.in.$ARCH files
  246. config BR2_ARCH
  247. string
  248. config BR2_ENDIAN
  249. string
  250. config BR2_GCC_TARGET_ARCH
  251. string
  252. config BR2_GCC_TARGET_ABI
  253. string
  254. config BR2_GCC_TARGET_NAN
  255. string
  256. config BR2_GCC_TARGET_FP32_MODE
  257. string
  258. config BR2_GCC_TARGET_CPU
  259. string
  260. config BR2_GCC_TARGET_CPU_REVISION
  261. string
  262. # The value of this option will be passed as --with-fpu=<value> when
  263. # building gcc (internal backend) or -mfpu=<value> in the toolchain
  264. # wrapper (external toolchain)
  265. config BR2_GCC_TARGET_FPU
  266. string
  267. # The value of this option will be passed as --with-float=<value> when
  268. # building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
  269. # wrapper (external toolchain)
  270. config BR2_GCC_TARGET_FLOAT_ABI
  271. string
  272. # The value of this option will be passed as --with-mode=<value> when
  273. # building gcc (internal backend) or -m<value> in the toolchain
  274. # wrapper (external toolchain)
  275. config BR2_GCC_TARGET_MODE
  276. string
  277. # Must be selected by binary formats that support shared libraries.
  278. config BR2_BINFMT_SUPPORTS_SHARED
  279. bool
  280. # Must match the name of the architecture from readelf point of view,
  281. # i.e the "Machine:" field of readelf output. See get_machine_name()
  282. # in binutils/readelf.c for the list of possible values.
  283. config BR2_READELF_ARCH_NAME
  284. string
  285. # Set up target binary format
  286. choice
  287. prompt "Target Binary Format"
  288. default BR2_BINFMT_ELF if BR2_USE_MMU
  289. default BR2_BINFMT_FDPIC if BR2_ARCH_HAS_FDPIC_SUPPORT
  290. default BR2_BINFMT_FLAT
  291. config BR2_BINFMT_ELF
  292. bool "ELF"
  293. depends on BR2_USE_MMU
  294. select BR2_BINFMT_SUPPORTS_SHARED
  295. help
  296. ELF (Executable and Linkable Format) is a format for libraries
  297. and executables used across different architectures and
  298. operating systems.
  299. config BR2_BINFMT_FDPIC
  300. bool "FDPIC"
  301. depends on BR2_ARCH_HAS_FDPIC_SUPPORT
  302. select BR2_BINFMT_SUPPORTS_SHARED
  303. help
  304. ELF FDPIC binaries are based on ELF, but allow the individual
  305. load segments of a binary to be located in memory
  306. independently of each other. This makes this format ideal for
  307. use in environments where no MMU is available.
  308. config BR2_BINFMT_FLAT
  309. bool "FLAT"
  310. depends on !BR2_USE_MMU
  311. help
  312. FLAT binary is a relatively simple and lightweight executable
  313. format based on the original a.out format. It is widely used
  314. in environment where no MMU is available.
  315. endchoice
  316. # Set up flat binary type
  317. choice
  318. prompt "FLAT Binary type"
  319. default BR2_BINFMT_FLAT_ONE
  320. depends on BR2_BINFMT_FLAT
  321. config BR2_BINFMT_FLAT_ONE
  322. bool "One memory region"
  323. help
  324. All segments are linked into one memory region.
  325. config BR2_BINFMT_FLAT_SHARED
  326. bool "Shared binary"
  327. depends on BR2_m68k
  328. # Even though this really generates shared binaries, there is no libdl
  329. # and dlopen() cannot be used. So packages that require shared
  330. # libraries cannot be built. Therefore, we don't select
  331. # BR2_BINFMT_SUPPORTS_SHARED and therefore force BR2_STATIC_LIBS.
  332. # Although this adds -static to the compilation, that's not a problem
  333. # because the -mid-shared-library option overrides it.
  334. help
  335. Allow to load and link indiviual FLAT binaries at run time.
  336. endchoice
  337. if BR2_arcle || BR2_arceb
  338. source "arch/Config.in.arc"
  339. endif
  340. if BR2_arm || BR2_armeb || BR2_aarch64 || BR2_aarch64_be
  341. source "arch/Config.in.arm"
  342. endif
  343. if BR2_csky
  344. source "arch/Config.in.csky"
  345. endif
  346. if BR2_m68k
  347. source "arch/Config.in.m68k"
  348. endif
  349. if BR2_microblazeel || BR2_microblazebe
  350. source "arch/Config.in.microblaze"
  351. endif
  352. if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
  353. source "arch/Config.in.mips"
  354. endif
  355. if BR2_nios2
  356. source "arch/Config.in.nios2"
  357. endif
  358. if BR2_or1k
  359. source "arch/Config.in.or1k"
  360. endif
  361. if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
  362. source "arch/Config.in.powerpc"
  363. endif
  364. if BR2_sh
  365. source "arch/Config.in.sh"
  366. endif
  367. if BR2_sparc || BR2_sparc64
  368. source "arch/Config.in.sparc"
  369. endif
  370. if BR2_i386 || BR2_x86_64
  371. source "arch/Config.in.x86"
  372. endif
  373. if BR2_xtensa
  374. source "arch/Config.in.xtensa"
  375. endif
  376. endmenu # Target options