Config.in.arm 14 KB

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  1. # arm cpu features
  2. config BR2_ARM_CPU_HAS_NEON
  3. bool
  4. # for some cores, NEON support is optional
  5. config BR2_ARM_CPU_MAYBE_HAS_NEON
  6. bool
  7. # for some cores, VFPv2 is optional
  8. config BR2_ARM_CPU_MAYBE_HAS_VFPV2
  9. bool
  10. config BR2_ARM_CPU_HAS_VFPV2
  11. bool
  12. # for some cores, VFPv3 is optional
  13. config BR2_ARM_CPU_MAYBE_HAS_VFPV3
  14. bool
  15. select BR2_ARM_CPU_MAYBE_HAS_VFPV2
  16. config BR2_ARM_CPU_HAS_VFPV3
  17. bool
  18. select BR2_ARM_CPU_HAS_VFPV2
  19. # for some cores, VFPv4 is optional
  20. config BR2_ARM_CPU_MAYBE_HAS_VFPV4
  21. bool
  22. select BR2_ARM_CPU_MAYBE_HAS_VFPV3
  23. config BR2_ARM_CPU_HAS_VFPV4
  24. bool
  25. select BR2_ARM_CPU_HAS_VFPV3
  26. config BR2_ARM_CPU_HAS_ARM
  27. bool
  28. config BR2_ARM_CPU_HAS_THUMB
  29. bool
  30. config BR2_ARM_CPU_HAS_THUMB2
  31. bool
  32. config BR2_ARM_CPU_ARMV4
  33. bool
  34. config BR2_ARM_CPU_ARMV5
  35. bool
  36. config BR2_ARM_CPU_ARMV6
  37. bool
  38. config BR2_ARM_CPU_ARMV7A
  39. bool
  40. config BR2_ARM_CPU_ARMV7M
  41. bool
  42. choice
  43. prompt "Target Architecture Variant"
  44. depends on BR2_arm || BR2_armeb
  45. default BR2_arm926t
  46. help
  47. Specific CPU variant to use
  48. config BR2_arm920t
  49. bool "arm920t"
  50. select BR2_ARM_CPU_HAS_ARM
  51. select BR2_ARM_CPU_HAS_THUMB
  52. select BR2_ARM_CPU_ARMV4
  53. select BR2_ARCH_HAS_MMU_OPTIONAL
  54. config BR2_arm922t
  55. bool "arm922t"
  56. select BR2_ARM_CPU_HAS_ARM
  57. select BR2_ARM_CPU_HAS_THUMB
  58. select BR2_ARM_CPU_ARMV4
  59. select BR2_ARCH_HAS_MMU_OPTIONAL
  60. config BR2_arm926t
  61. bool "arm926t"
  62. select BR2_ARM_CPU_HAS_ARM
  63. select BR2_ARM_CPU_MAYBE_HAS_VFPV2
  64. select BR2_ARM_CPU_HAS_THUMB
  65. select BR2_ARM_CPU_ARMV5
  66. select BR2_ARCH_HAS_MMU_OPTIONAL
  67. config BR2_arm1136j_s
  68. bool "arm1136j-s"
  69. select BR2_ARM_CPU_HAS_ARM
  70. select BR2_ARM_CPU_HAS_THUMB
  71. select BR2_ARM_CPU_ARMV6
  72. select BR2_ARCH_HAS_MMU_OPTIONAL
  73. config BR2_arm1136jf_s
  74. bool "arm1136jf-s"
  75. select BR2_ARM_CPU_HAS_ARM
  76. select BR2_ARM_CPU_HAS_VFPV2
  77. select BR2_ARM_CPU_HAS_THUMB
  78. select BR2_ARM_CPU_ARMV6
  79. select BR2_ARCH_HAS_MMU_OPTIONAL
  80. config BR2_arm1176jz_s
  81. bool "arm1176jz-s"
  82. select BR2_ARM_CPU_HAS_ARM
  83. select BR2_ARM_CPU_HAS_THUMB
  84. select BR2_ARM_CPU_ARMV6
  85. select BR2_ARCH_HAS_MMU_OPTIONAL
  86. config BR2_arm1176jzf_s
  87. bool "arm1176jzf-s"
  88. select BR2_ARM_CPU_HAS_ARM
  89. select BR2_ARM_CPU_HAS_VFPV2
  90. select BR2_ARM_CPU_HAS_THUMB
  91. select BR2_ARM_CPU_ARMV6
  92. select BR2_ARCH_HAS_MMU_OPTIONAL
  93. config BR2_arm11mpcore
  94. bool "mpcore"
  95. select BR2_ARM_CPU_HAS_ARM
  96. select BR2_ARM_CPU_MAYBE_HAS_VFPV2
  97. select BR2_ARM_CPU_HAS_THUMB
  98. select BR2_ARM_CPU_ARMV6
  99. select BR2_ARCH_HAS_MMU_OPTIONAL
  100. config BR2_cortex_a5
  101. bool "cortex-A5"
  102. select BR2_ARM_CPU_HAS_ARM
  103. select BR2_ARM_CPU_MAYBE_HAS_NEON
  104. select BR2_ARM_CPU_MAYBE_HAS_VFPV4
  105. select BR2_ARM_CPU_HAS_THUMB2
  106. select BR2_ARM_CPU_ARMV7A
  107. select BR2_ARCH_HAS_MMU_OPTIONAL
  108. config BR2_cortex_a7
  109. bool "cortex-A7"
  110. select BR2_ARM_CPU_HAS_ARM
  111. select BR2_ARM_CPU_HAS_NEON
  112. select BR2_ARM_CPU_HAS_VFPV4
  113. select BR2_ARM_CPU_HAS_THUMB2
  114. select BR2_ARM_CPU_ARMV7A
  115. select BR2_ARCH_HAS_MMU_OPTIONAL
  116. config BR2_cortex_a8
  117. bool "cortex-A8"
  118. select BR2_ARM_CPU_HAS_ARM
  119. select BR2_ARM_CPU_HAS_NEON
  120. select BR2_ARM_CPU_HAS_VFPV3
  121. select BR2_ARM_CPU_HAS_THUMB2
  122. select BR2_ARM_CPU_ARMV7A
  123. select BR2_ARCH_HAS_MMU_OPTIONAL
  124. config BR2_cortex_a9
  125. bool "cortex-A9"
  126. select BR2_ARM_CPU_HAS_ARM
  127. select BR2_ARM_CPU_MAYBE_HAS_NEON
  128. select BR2_ARM_CPU_MAYBE_HAS_VFPV3
  129. select BR2_ARM_CPU_HAS_THUMB2
  130. select BR2_ARM_CPU_ARMV7A
  131. select BR2_ARCH_HAS_MMU_OPTIONAL
  132. config BR2_cortex_a12
  133. bool "cortex-A12"
  134. select BR2_ARM_CPU_HAS_ARM
  135. select BR2_ARM_CPU_HAS_NEON
  136. select BR2_ARM_CPU_HAS_VFPV4
  137. select BR2_ARM_CPU_HAS_THUMB2
  138. select BR2_ARM_CPU_ARMV7A
  139. select BR2_ARCH_HAS_MMU_OPTIONAL
  140. config BR2_cortex_a15
  141. bool "cortex-A15"
  142. select BR2_ARM_CPU_HAS_ARM
  143. select BR2_ARM_CPU_HAS_NEON
  144. select BR2_ARM_CPU_HAS_VFPV4
  145. select BR2_ARM_CPU_HAS_THUMB2
  146. select BR2_ARM_CPU_ARMV7A
  147. select BR2_ARCH_HAS_MMU_OPTIONAL
  148. config BR2_cortex_a17
  149. bool "cortex-A17"
  150. select BR2_ARM_CPU_HAS_ARM
  151. select BR2_ARM_CPU_HAS_NEON
  152. select BR2_ARM_CPU_HAS_VFPV4
  153. select BR2_ARM_CPU_HAS_THUMB2
  154. select BR2_ARM_CPU_ARMV7A
  155. select BR2_ARCH_HAS_MMU_OPTIONAL
  156. config BR2_cortex_m3
  157. bool "cortex-M3"
  158. select BR2_ARM_CPU_HAS_THUMB2
  159. select BR2_ARM_CPU_ARMV7M
  160. config BR2_cortex_m4
  161. bool "cortex-M4"
  162. select BR2_ARM_CPU_HAS_THUMB2
  163. select BR2_ARM_CPU_ARMV7M
  164. config BR2_fa526
  165. bool "fa526/626"
  166. select BR2_ARM_CPU_HAS_ARM
  167. select BR2_ARM_CPU_ARMV4
  168. select BR2_ARCH_HAS_MMU_OPTIONAL
  169. config BR2_pj4
  170. bool "pj4"
  171. select BR2_ARM_CPU_HAS_ARM
  172. select BR2_ARM_CPU_HAS_VFPV3
  173. select BR2_ARM_CPU_ARMV7A
  174. select BR2_ARCH_HAS_MMU_OPTIONAL
  175. config BR2_strongarm
  176. bool "strongarm sa110/sa1100"
  177. select BR2_ARM_CPU_HAS_ARM
  178. select BR2_ARM_CPU_ARMV4
  179. select BR2_ARCH_HAS_MMU_OPTIONAL
  180. config BR2_xscale
  181. bool "xscale"
  182. select BR2_ARM_CPU_HAS_ARM
  183. select BR2_ARM_CPU_HAS_THUMB
  184. select BR2_ARM_CPU_ARMV5
  185. select BR2_ARCH_HAS_MMU_OPTIONAL
  186. config BR2_iwmmxt
  187. bool "iwmmxt"
  188. select BR2_ARM_CPU_HAS_ARM
  189. select BR2_ARM_CPU_ARMV5
  190. select BR2_ARCH_HAS_MMU_OPTIONAL
  191. endchoice
  192. config BR2_ARM_ENABLE_NEON
  193. bool "Enable NEON SIMD extension support"
  194. depends on BR2_ARM_CPU_MAYBE_HAS_NEON
  195. select BR2_ARM_CPU_HAS_NEON
  196. help
  197. For some CPU cores, the NEON SIMD extension is optional.
  198. Select this option if you are certain your particular
  199. implementation has NEON support and you want to use it.
  200. config BR2_ARM_ENABLE_VFP
  201. bool "Enable VFP extension support"
  202. depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2
  203. select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
  204. select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
  205. select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
  206. help
  207. For some CPU cores, the VFP extension is optional. Select
  208. this option if you are certain your particular
  209. implementation has VFP support and you want to use it.
  210. choice
  211. prompt "Target ABI"
  212. depends on BR2_arm || BR2_armeb
  213. default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_VFPV2
  214. default BR2_ARM_EABI
  215. help
  216. Application Binary Interface to use. The Application Binary
  217. Interface describes the calling conventions (how arguments
  218. are passed to functions, how the return value is passed, how
  219. system calls are made, etc.).
  220. config BR2_ARM_EABI
  221. bool "EABI"
  222. help
  223. The EABI is currently the standard ARM ABI, which is used in
  224. most projects. It supports both the 'soft' floating point
  225. model (in which floating point instructions are emulated in
  226. software) and the 'softfp' floating point model (in which
  227. floating point instructions are executed using an hardware
  228. floating point unit, but floating point arguments to
  229. functions are passed in integer registers).
  230. The 'softfp' floating point model is link-compatible with
  231. the 'soft' floating point model, i.e you can link a library
  232. built 'soft' with some other code built 'softfp'.
  233. However, passing the floating point arguments in integer
  234. registers is a bit inefficient, so if your ARM processor has
  235. a floating point unit, and you don't have pre-compiled
  236. 'soft' or 'softfp' code, using the EABIhf ABI will provide
  237. better floating point performances.
  238. If your processor does not have a floating point unit, then
  239. you must use this ABI.
  240. config BR2_ARM_EABIHF
  241. bool "EABIhf"
  242. depends on BR2_ARM_CPU_HAS_VFPV2
  243. help
  244. The EABIhf is an extension of EABI which supports the 'hard'
  245. floating point model. This model uses the floating point
  246. unit to execute floating point instructions, and passes
  247. floating point arguments in floating point registers.
  248. It is more efficient than EABI for floating point related
  249. workload. However, it does not allow to link against code
  250. that has been pre-built for the 'soft' or 'softfp' floating
  251. point models.
  252. If your processor has a floating point unit, and you don't
  253. depend on existing pre-compiled code, this option is most
  254. likely the best choice.
  255. endchoice
  256. choice
  257. prompt "Floating point strategy"
  258. depends on BR2_ARM_EABI || BR2_ARM_EABIHF
  259. default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
  260. default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
  261. default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
  262. default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2
  263. config BR2_ARM_SOFT_FLOAT
  264. bool "Soft float"
  265. depends on BR2_ARM_EABI
  266. select BR2_SOFT_FLOAT
  267. help
  268. This option allows to use software emulated floating
  269. point. It should be used for ARM cores that do not include a
  270. Vector Floating Point unit, such as ARMv5 cores (ARM926 for
  271. example) or certain ARMv6 cores.
  272. config BR2_ARM_FPU_VFPV2
  273. bool "VFPv2"
  274. depends on BR2_ARM_CPU_HAS_VFPV2
  275. help
  276. This option allows to use the VFPv2 floating point unit, as
  277. available in some ARMv5 processors (ARM926EJ-S) and some
  278. ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
  279. MPCore).
  280. Note that this option is also safe to use for newer cores
  281. such as Cortex-A, because the VFPv3 and VFPv4 units are
  282. backward compatible with VFPv2.
  283. config BR2_ARM_FPU_VFPV3
  284. bool "VFPv3"
  285. depends on BR2_ARM_CPU_HAS_VFPV3
  286. help
  287. This option allows to use the VFPv3 floating point unit, as
  288. available in some ARMv7 processors (Cortex-A{8, 9}). This
  289. option requires a VFPv3 unit that has 32 double-precision
  290. registers, which is not necessarily the case in all SOCs
  291. based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16
  292. instead, which is guaranteed to work on all Cortex-A{8, 9}.
  293. Note that this option is also safe to use for newer cores
  294. that have a VFPv4 unit, because VFPv4 is backward compatible
  295. with VFPv3. They must of course also have 32
  296. double-precision registers.
  297. config BR2_ARM_FPU_VFPV3D16
  298. bool "VFPv3-D16"
  299. depends on BR2_ARM_CPU_HAS_VFPV3
  300. help
  301. This option allows to use the VFPv3 floating point unit, as
  302. available in some ARMv7 processors (Cortex-A{8, 9}). This
  303. option requires a VFPv3 unit that has 16 double-precision
  304. registers, which is generally the case in all SOCs based on
  305. Cortex-A{8, 9}, even though VFPv3 is technically optional on
  306. Cortex-A9. This is the safest option for those cores.
  307. Note that this option is also safe to use for newer cores
  308. such that have a VFPv4 unit, because the VFPv4 is backward
  309. compatible with VFPv3.
  310. config BR2_ARM_FPU_VFPV4
  311. bool "VFPv4"
  312. depends on BR2_ARM_CPU_HAS_VFPV4
  313. help
  314. This option allows to use the VFPv4 floating point unit, as
  315. available in some ARMv7 processors (Cortex-A{5, 7, 12,
  316. 15}). This option requires a VFPv4 unit that has 32
  317. double-precision registers, which is not necessarily the
  318. case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're
  319. unsure, you should probably use VFPv4-D16 instead.
  320. Note that if you want binary code that works on all ARMv7
  321. cores, including the earlier Cortex-A{8, 9}, you should
  322. instead select VFPv3.
  323. config BR2_ARM_FPU_VFPV4D16
  324. bool "VFPv4-D16"
  325. depends on BR2_ARM_CPU_HAS_VFPV4
  326. help
  327. This option allows to use the VFPv4 floating point unit, as
  328. available in some ARMv7 processors (Cortex-A{5, 7, 12,
  329. 15}). This option requires a VFPv4 unit that has 16
  330. double-precision registers, which is always available on
  331. Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and
  332. Cortex-A7.
  333. Note that if you want binary code that works on all ARMv7
  334. cores, including the earlier Cortex-A{8, 9}, you should
  335. instead select VFPv3-D16.
  336. config BR2_ARM_FPU_NEON
  337. bool "NEON"
  338. depends on BR2_ARM_CPU_HAS_NEON
  339. help
  340. This option allows to use the NEON SIMD unit, as available
  341. in some ARMv7 processors, as a floating-point unit. It
  342. should however be noted that using NEON for floating point
  343. operations doesn't provide a complete compatibility with the
  344. IEEE 754.
  345. config BR2_ARM_FPU_NEON_VFPV4
  346. bool "NEON/VFPv4"
  347. depends on BR2_ARM_CPU_HAS_VFPV4
  348. depends on BR2_ARM_CPU_HAS_NEON
  349. help
  350. This option allows to use both the VFPv4 and the NEON SIMD
  351. units for floating point operations. Note that some ARMv7
  352. cores do not necessarily have VFPv4 and/or NEON support, for
  353. example on Cortex-A5 and Cortex-A7, support for VFPv4 and
  354. NEON is optional.
  355. endchoice
  356. choice
  357. prompt "ARM instruction set"
  358. config BR2_ARM_INSTRUCTIONS_ARM
  359. bool "ARM"
  360. depends on BR2_ARM_CPU_HAS_ARM
  361. help
  362. This option instructs the compiler to generate regular ARM
  363. instructions, that are all 32 bits wide.
  364. config BR2_ARM_INSTRUCTIONS_THUMB
  365. bool "Thumb"
  366. depends on BR2_ARM_CPU_HAS_THUMB
  367. # Thumb-1 and VFP are not compatible
  368. depends on BR2_ARM_SOFT_FLOAT
  369. help
  370. This option instructions the compiler to generate Thumb
  371. instructions, which allows to mix 16 bits instructions and
  372. 32 bits instructions. This generally provides a much smaller
  373. compiled binary size.
  374. comment "Thumb1 is not compatible with VFP"
  375. depends on BR2_ARM_CPU_HAS_THUMB
  376. depends on !BR2_ARM_SOFT_FLOAT
  377. config BR2_ARM_INSTRUCTIONS_THUMB2
  378. bool "Thumb2"
  379. depends on BR2_ARM_CPU_HAS_THUMB2
  380. help
  381. This option instructions the compiler to generate Thumb2
  382. instructions, which allows to mix 16 bits instructions and
  383. 32 bits instructions. This generally provides a much smaller
  384. compiled binary size.
  385. endchoice
  386. config BR2_ARCH
  387. default "arm" if BR2_arm
  388. default "armeb" if BR2_armeb
  389. config BR2_ENDIAN
  390. default "LITTLE" if BR2_arm
  391. default "BIG" if BR2_armeb
  392. config BR2_GCC_TARGET_CPU
  393. default "arm920t" if BR2_arm920t
  394. default "arm922t" if BR2_arm922t
  395. default "arm926ej-s" if BR2_arm926t
  396. default "arm1136j-s" if BR2_arm1136j_s
  397. default "arm1136jf-s" if BR2_arm1136jf_s
  398. default "arm1176jz-s" if BR2_arm1176jz_s
  399. default "arm1176jzf-s" if BR2_arm1176jzf_s
  400. default "mpcore" if BR2_arm11mpcore && BR2_ARM_CPU_HAS_VFPV2
  401. default "mpcorenovfp" if BR2_arm11mpcore
  402. default "cortex-a5" if BR2_cortex_a5
  403. default "cortex-a7" if BR2_cortex_a7
  404. default "cortex-a8" if BR2_cortex_a8
  405. default "cortex-a9" if BR2_cortex_a9
  406. default "cortex-a12" if BR2_cortex_a12
  407. default "cortex-a15" if BR2_cortex_a15
  408. default "cortex-a17" if BR2_cortex_a17
  409. default "cortex-m3" if BR2_cortex_m3
  410. default "cortex-m4" if BR2_cortex_m4
  411. default "fa526" if BR2_fa526
  412. default "marvell-pj4" if BR2_pj4
  413. default "strongarm" if BR2_strongarm
  414. default "xscale" if BR2_xscale
  415. default "iwmmxt" if BR2_iwmmxt
  416. config BR2_GCC_TARGET_ABI
  417. default "aapcs-linux"
  418. config BR2_GCC_TARGET_FPU
  419. default "vfp" if BR2_ARM_FPU_VFPV2
  420. default "vfpv3" if BR2_ARM_FPU_VFPV3
  421. default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
  422. default "vfpv4" if BR2_ARM_FPU_VFPV4
  423. default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
  424. default "neon" if BR2_ARM_FPU_NEON
  425. default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
  426. config BR2_GCC_TARGET_FLOAT_ABI
  427. default "soft" if BR2_ARM_SOFT_FLOAT
  428. default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
  429. default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
  430. config BR2_GCC_TARGET_MODE
  431. default "arm" if BR2_ARM_INSTRUCTIONS_ARM
  432. default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2