Config.in 7.8 KB

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  1. config BR2_ARCH_IS_64
  2. bool
  3. config BR2_SOFT_FLOAT
  4. bool
  5. choice
  6. prompt "Target Architecture"
  7. default BR2_i386
  8. help
  9. Select the target architecture family to build for.
  10. config BR2_arcle
  11. bool "ARC (little endian)"
  12. help
  13. Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
  14. that can be used from deeply embedded to high performance host
  15. applications. Little endian.
  16. config BR2_arceb
  17. bool "ARC (big endian)"
  18. help
  19. Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
  20. that can be used from deeply embedded to high performance host
  21. applications. Big endian.
  22. config BR2_arm
  23. bool "ARM (little endian)"
  24. help
  25. ARM is a 32-bit reduced instruction set computer (RISC) instruction
  26. set architecture (ISA) developed by ARM Holdings. Little endian.
  27. http://www.arm.com/
  28. http://en.wikipedia.org/wiki/ARM
  29. config BR2_armeb
  30. bool "ARM (big endian)"
  31. help
  32. ARM is a 32-bit reduced instruction set computer (RISC) instruction
  33. set architecture (ISA) developed by ARM Holdings. Big endian.
  34. http://www.arm.com/
  35. http://en.wikipedia.org/wiki/ARM
  36. config BR2_aarch64
  37. bool "AArch64"
  38. select BR2_ARCH_IS_64
  39. help
  40. Aarch64 is a 64-bit architecture developed by ARM Holdings.
  41. http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  42. http://en.wikipedia.org/wiki/ARM
  43. config BR2_avr32
  44. bool "AVR32"
  45. select BR2_SOFT_FLOAT
  46. help
  47. The AVR32 is a 32-bit RISC microprocessor architecture designed by
  48. Atmel.
  49. http://www.atmel.com/
  50. http://en.wikipedia.org/wiki/Avr32
  51. config BR2_bfin
  52. bool "Blackfin"
  53. help
  54. The Blackfin is a family of 16 or 32-bit microprocessors developed,
  55. manufactured and marketed by Analog Devices.
  56. http://www.analog.com/
  57. http://en.wikipedia.org/wiki/Blackfin
  58. config BR2_i386
  59. bool "i386"
  60. help
  61. Intel i386 architecture compatible microprocessor
  62. http://en.wikipedia.org/wiki/I386
  63. config BR2_m68k
  64. bool "m68k"
  65. depends on BROKEN # ice in uclibc / inet_ntoa_r
  66. help
  67. Motorola 68000 family microprocessor
  68. http://en.wikipedia.org/wiki/M68k
  69. config BR2_microblazeel
  70. bool "Microblaze AXI (little endian)"
  71. help
  72. Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus
  73. based architecture (little endian)
  74. http://www.xilinx.com
  75. http://en.wikipedia.org/wiki/Microblaze
  76. config BR2_microblazebe
  77. bool "Microblaze non-AXI (big endian)"
  78. help
  79. Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus
  80. based architecture (non-AXI, big endian)
  81. http://www.xilinx.com
  82. http://en.wikipedia.org/wiki/Microblaze
  83. config BR2_mips
  84. bool "MIPS (big endian)"
  85. help
  86. MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
  87. http://www.mips.com/
  88. http://en.wikipedia.org/wiki/MIPS_Technologies
  89. config BR2_mipsel
  90. bool "MIPS (little endian)"
  91. help
  92. MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
  93. http://www.mips.com/
  94. http://en.wikipedia.org/wiki/MIPS_Technologies
  95. config BR2_mips64
  96. bool "MIPS64 (big endian)"
  97. select BR2_ARCH_IS_64
  98. help
  99. MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
  100. http://www.mips.com/
  101. http://en.wikipedia.org/wiki/MIPS_Technologies
  102. config BR2_mips64el
  103. bool "MIPS64 (little endian)"
  104. select BR2_ARCH_IS_64
  105. help
  106. MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
  107. http://www.mips.com/
  108. http://en.wikipedia.org/wiki/MIPS_Technologies
  109. config BR2_powerpc
  110. bool "PowerPC"
  111. help
  112. PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
  113. http://www.power.org/
  114. http://en.wikipedia.org/wiki/Powerpc
  115. config BR2_sh
  116. bool "SuperH"
  117. help
  118. SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)
  119. instruction set architecture (ISA) developed by Hitachi.
  120. http://www.hitachi.com/
  121. http://en.wikipedia.org/wiki/SuperH
  122. config BR2_sh64
  123. bool "SuperH64"
  124. help
  125. SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC)
  126. instruction set architecture (ISA) developed by Hitachi.
  127. http://www.hitachi.com/
  128. http://en.wikipedia.org/wiki/SuperH
  129. config BR2_sparc
  130. bool "SPARC"
  131. help
  132. SPARC (from Scalable Processor Architecture) is a RISC instruction
  133. set architecture (ISA) developed by Sun Microsystems.
  134. http://www.oracle.com/sun
  135. http://en.wikipedia.org/wiki/Sparc
  136. config BR2_x86_64
  137. bool "x86_64"
  138. select BR2_ARCH_IS_64
  139. help
  140. x86-64 is an extension of the x86 instruction set (Intel i386
  141. architecture compatible microprocessor).
  142. http://en.wikipedia.org/wiki/X86_64
  143. config BR2_xtensa
  144. bool "Xtensa"
  145. help
  146. Xtensa is a Tensilica processor IP architecture.
  147. http://en.wikipedia.org/wiki/Xtensa
  148. http://www.tensilica.com/
  149. endchoice
  150. # The following string values are defined by the individual
  151. # Config.in.$ARCH files
  152. config BR2_ARCH
  153. string
  154. config BR2_ENDIAN
  155. string
  156. config BR2_GCC_TARGET_TUNE
  157. string
  158. config BR2_GCC_TARGET_ARCH
  159. string
  160. config BR2_GCC_TARGET_ABI
  161. string
  162. config BR2_GCC_TARGET_CPU
  163. string
  164. config BR2_GCC_TARGET_CPU_REVISION
  165. string
  166. # The value of this option will be passed as --with-fpu=<value> when
  167. # building gcc (internal backend) or -mfpu=<value> in the toolchain
  168. # wrapper (external toolchain)
  169. config BR2_GCC_TARGET_FPU
  170. string
  171. # The value of this option will be passed as --with-float=<value> when
  172. # building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
  173. # wrapper (external toolchain)
  174. config BR2_GCC_TARGET_FLOAT_ABI
  175. string
  176. # The value of this option will be passed as --with-mode=<value> when
  177. # building gcc (internal backend) or -m<value> in the toolchain
  178. # wrapper (external toolchain)
  179. config BR2_GCC_TARGET_MODE
  180. string
  181. # Set up target binary format
  182. choice
  183. prompt "Target Binary Format"
  184. depends on BR2_bfin || BR2_m68k
  185. default BR2_BINFMT_FDPIC
  186. config BR2_BINFMT_ELF
  187. bool "ELF"
  188. depends on !BR2_bfin && !BR2_m68k
  189. help
  190. ELF (Executable and Linkable Format) is a format for libraries and
  191. executables used across different architectures and operating
  192. systems.
  193. config BR2_BINFMT_FDPIC
  194. bool "FDPIC"
  195. depends on BR2_bfin || BR2_m68k
  196. help
  197. ELF FDPIC binaries are based on ELF, but allow the individual load
  198. segments of a binary to be located in memory independently of each
  199. other. This makes this format ideal for use in environments where no
  200. MMU is available.
  201. config BR2_BINFMT_FLAT
  202. bool "FLAT"
  203. depends on BR2_bfin || BR2_m68k
  204. select BR2_PREFER_STATIC_LIB
  205. help
  206. FLAT binary is a relatively simple and lightweight executable format
  207. based on the original a.out format. It is widely used in environment
  208. where no MMU is available.
  209. endchoice
  210. # Set up flat binary type
  211. choice
  212. prompt "FLAT Binary type"
  213. depends on BR2_BINFMT_FLAT
  214. default BR2_BINFMT_FLAT_ONE
  215. config BR2_BINFMT_FLAT_ONE
  216. bool "One memory region"
  217. help
  218. All segments are linked into one memory region.
  219. config BR2_BINFMT_FLAT_SEP_DATA
  220. bool "Separate data and code region"
  221. depends on BR2_bfin || BR2_m68k
  222. help
  223. Allow for the data and text segments to be separated and placed in
  224. different regions of memory.
  225. config BR2_BINFMT_FLAT_SHARED
  226. bool "Shared binary"
  227. depends on BR2_bfin || BR2_m68k
  228. help
  229. Allow to load and link indiviual FLAT binaries at run time.
  230. endchoice
  231. if BR2_arcle || BR2_arceb
  232. source "arch/Config.in.arc"
  233. endif
  234. if BR2_arm || BR2_armeb
  235. source "arch/Config.in.arm"
  236. endif
  237. if BR2_aarch64
  238. source "arch/Config.in.aarch64"
  239. endif
  240. if BR2_avr32
  241. source "arch/Config.in.avr32"
  242. endif
  243. if BR2_bfin
  244. source "arch/Config.in.bfin"
  245. endif
  246. if BR2_m68k
  247. source "arch/Config.in.m68k"
  248. endif
  249. if BR2_microblazeel || BR2_microblazebe
  250. source "arch/Config.in.microblaze"
  251. endif
  252. if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
  253. source "arch/Config.in.mips"
  254. endif
  255. if BR2_powerpc
  256. source "arch/Config.in.powerpc"
  257. endif
  258. if BR2_sh || BR2_sh64
  259. source "arch/Config.in.sh"
  260. endif
  261. if BR2_sparc
  262. source "arch/Config.in.sparc"
  263. endif
  264. if BR2_i386 || BR2_x86_64
  265. source "arch/Config.in.x86"
  266. endif
  267. if BR2_xtensa
  268. source "arch/Config.in.xtensa"
  269. endif