0001-DTS-for-QMTech-Zynq-starter-kit.patch 7.6 KB

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  1. From 22d955122ac0f7ac74ab74aadebf6b8edaf0bbbd Mon Sep 17 00:00:00 2001
  2. From: Julien Olivain <juju@cotds.org>
  3. Date: Sun, 15 Dec 2019 18:45:40 +0100
  4. Subject: [PATCH] DTS for QMTech Zynq starter kit
  5. Signed-off-by: Martin Chabot <martin.chabot@gmail.com>
  6. Signed-off-by: Julien Olivain <juju@cotds.org>
  7. ---
  8. arch/arm/boot/dts/zynq-qmtech.dts | 397 ++++++++++++++++++++++++++++++
  9. 1 file changed, 397 insertions(+)
  10. create mode 100644 arch/arm/boot/dts/zynq-qmtech.dts
  11. diff --git a/arch/arm/boot/dts/zynq-qmtech.dts b/arch/arm/boot/dts/zynq-qmtech.dts
  12. new file mode 100644
  13. index 000000000000..c6081dc0080e
  14. --- /dev/null
  15. +++ b/arch/arm/boot/dts/zynq-qmtech.dts
  16. @@ -0,0 +1,397 @@
  17. +// SPDX-License-Identifier: GPL-2.0+
  18. +/*
  19. + * Copyright (C) 2011 - 2015 Xilinx
  20. + * Copyright (C) 2012 National Instruments Corp.
  21. + * Copyright (C) 2019 Martin Chabot <martin.chabot@gmail.com>
  22. + */
  23. +
  24. +/* Derived from:
  25. + * https://github.com/Xilinx/linux-xlnx/blob/xilinx-v2019.2.01/arch/arm/boot/dts/zynq-zc702.dts
  26. + */
  27. +
  28. +/dts-v1/;
  29. +#include "zynq-7000.dtsi"
  30. +
  31. +/ {
  32. + model = "QMTECH XC7Z010 Starter Kit";
  33. + compatible = "xlnx,zynq-qmtech", "xlnx,zynq-zc702", "xlnx,zynq-7000";
  34. +
  35. + aliases {
  36. + ethernet0 = &gem0;
  37. + i2c0 = &i2c0;
  38. + serial0 = &uart1;
  39. + spi0 = &qspi;
  40. + mmc0 = &sdhci0;
  41. + };
  42. +
  43. + memory@0 {
  44. + device_type = "memory";
  45. + reg = <0x0 0x20000000>;
  46. + };
  47. +
  48. + chosen {
  49. + bootargs = "";
  50. + stdout-path = "serial0:115200n8";
  51. + };
  52. +
  53. + leds {
  54. + compatible = "gpio-leds";
  55. +
  56. + ds23 {
  57. + label = "ds23";
  58. + gpios = <&gpio0 10 0>;
  59. + linux,default-trigger = "heartbeat";
  60. + };
  61. + };
  62. +
  63. +};
  64. +
  65. +&amba {
  66. + ocm: sram@fffc0000 {
  67. + compatible = "mmio-sram";
  68. + reg = <0xfffc0000 0x10000>;
  69. + };
  70. +};
  71. +
  72. +&clkc {
  73. + ps-clk-frequency = <33333333>;
  74. +};
  75. +
  76. +&gem0 {
  77. + status = "okay";
  78. + phy-mode = "rgmii-id";
  79. + phy-handle = <&ethernet_phy>;
  80. +
  81. + ethernet_phy: ethernet-phy@0 {
  82. + reg = <0>;
  83. + device_type = "ethernet-phy";
  84. + };
  85. +};
  86. +
  87. +&gpio0 {
  88. + pinctrl-names = "default";
  89. + pinctrl-0 = <&pinctrl_gpio0_default>;
  90. +};
  91. +
  92. +&i2c0 {
  93. + status = "disabled";
  94. + clock-frequency = <400000>;
  95. + pinctrl-names = "default", "gpio";
  96. + pinctrl-0 = <&pinctrl_i2c0_default>;
  97. + pinctrl-1 = <&pinctrl_i2c0_gpio>;
  98. + scl-gpios = <&gpio0 50 0>;
  99. + sda-gpios = <&gpio0 51 0>;
  100. +
  101. + i2c-mux@74 {
  102. + compatible = "nxp,pca9548";
  103. + #address-cells = <1>;
  104. + #size-cells = <0>;
  105. + reg = <0x74>;
  106. +
  107. + i2c@0 {
  108. + #address-cells = <1>;
  109. + #size-cells = <0>;
  110. + reg = <0>;
  111. + si570: clock-generator@5d {
  112. + #clock-cells = <0>;
  113. + compatible = "silabs,si570";
  114. + temperature-stability = <50>;
  115. + reg = <0x5d>;
  116. + factory-fout = <156250000>;
  117. + clock-frequency = <148500000>;
  118. + };
  119. + };
  120. +
  121. + i2c@1 {
  122. + #address-cells = <1>;
  123. + #size-cells = <0>;
  124. + reg = <1>;
  125. + adv7511: hdmi-tx@39 {
  126. + compatible = "adi,adv7511";
  127. + reg = <0x39>;
  128. + adi,input-depth = <8>;
  129. + adi,input-colorspace = "yuv422";
  130. + adi,input-clock = "1x";
  131. + adi,input-style = <3>;
  132. + adi,input-justification = "right";
  133. + };
  134. + };
  135. +
  136. + i2c@2 {
  137. + #address-cells = <1>;
  138. + #size-cells = <0>;
  139. + reg = <2>;
  140. + eeprom@54 {
  141. + compatible = "atmel,24c08";
  142. + reg = <0x54>;
  143. + };
  144. + };
  145. +
  146. + i2c@3 {
  147. + #address-cells = <1>;
  148. + #size-cells = <0>;
  149. + reg = <3>;
  150. + gpio@21 {
  151. + compatible = "ti,tca6416";
  152. + reg = <0x21>;
  153. + gpio-controller;
  154. + #gpio-cells = <2>;
  155. + };
  156. + };
  157. +
  158. + i2c@4 {
  159. + #address-cells = <1>;
  160. + #size-cells = <0>;
  161. + reg = <4>;
  162. + rtc@51 {
  163. + compatible = "nxp,pcf8563";
  164. + reg = <0x51>;
  165. + };
  166. + };
  167. +
  168. + i2c@7 {
  169. + #address-cells = <1>;
  170. + #size-cells = <0>;
  171. + reg = <7>;
  172. + hwmon@52 {
  173. + compatible = "ti,ucd9248";
  174. + reg = <52>;
  175. + };
  176. + hwmon@53 {
  177. + compatible = "ti,ucd9248";
  178. + reg = <53>;
  179. + };
  180. + hwmon@54 {
  181. + compatible = "ti,ucd9248";
  182. + reg = <54>;
  183. + };
  184. + };
  185. + };
  186. +};
  187. +
  188. +&pinctrl0 {
  189. + pinctrl_can0_default: can0-default {
  190. + mux {
  191. + function = "can0";
  192. + groups = "can0_9_grp";
  193. + };
  194. +
  195. + conf {
  196. + groups = "can0_9_grp";
  197. + slew-rate = <0>;
  198. + io-standard = <1>;
  199. + };
  200. +
  201. + conf-rx {
  202. + pins = "MIO46";
  203. + bias-high-impedance;
  204. + };
  205. +
  206. + conf-tx {
  207. + pins = "MIO47";
  208. + bias-disable;
  209. + };
  210. + };
  211. +
  212. + pinctrl_gem0_default: gem0-default {
  213. + mux {
  214. + function = "ethernet0";
  215. + groups = "ethernet0_0_grp";
  216. + };
  217. +
  218. + conf {
  219. + groups = "ethernet0_0_grp";
  220. + slew-rate = <0>;
  221. + io-standard = <4>;
  222. + };
  223. +
  224. + conf-rx {
  225. + pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
  226. + bias-high-impedance;
  227. + low-power-disable;
  228. + };
  229. +
  230. + conf-tx {
  231. + pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
  232. + bias-disable;
  233. + low-power-enable;
  234. + };
  235. +
  236. + mux-mdio {
  237. + function = "mdio0";
  238. + groups = "mdio0_0_grp";
  239. + };
  240. +
  241. + conf-mdio {
  242. + groups = "mdio0_0_grp";
  243. + slew-rate = <0>;
  244. + io-standard = <1>;
  245. + bias-disable;
  246. + };
  247. + };
  248. +
  249. + pinctrl_gpio0_default: gpio0-default {
  250. + mux {
  251. + function = "gpio0";
  252. + groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
  253. + "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
  254. + "gpio0_13_grp", "gpio0_14_grp";
  255. + };
  256. +
  257. + conf {
  258. + groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
  259. + "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
  260. + "gpio0_13_grp", "gpio0_14_grp";
  261. + slew-rate = <0>;
  262. + io-standard = <1>;
  263. + };
  264. +
  265. + conf-pull-up {
  266. + pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
  267. + bias-pull-up;
  268. + };
  269. +
  270. + conf-pull-none {
  271. + pins = "MIO7", "MIO8";
  272. + bias-disable;
  273. + };
  274. + };
  275. +
  276. + pinctrl_i2c0_default: i2c0-default {
  277. + mux {
  278. + groups = "i2c0_10_grp";
  279. + function = "i2c0";
  280. + };
  281. +
  282. + conf {
  283. + groups = "i2c0_10_grp";
  284. + bias-pull-up;
  285. + slew-rate = <0>;
  286. + io-standard = <1>;
  287. + };
  288. + };
  289. +
  290. + pinctrl_i2c0_gpio: i2c0-gpio {
  291. + mux {
  292. + groups = "gpio0_50_grp", "gpio0_51_grp";
  293. + function = "gpio0";
  294. + };
  295. +
  296. + conf {
  297. + groups = "gpio0_50_grp", "gpio0_51_grp";
  298. + slew-rate = <0>;
  299. + io-standard = <1>;
  300. + };
  301. + };
  302. +
  303. + pinctrl_sdhci0_default: sdhci0-default {
  304. + mux {
  305. + groups = "sdio0_2_grp";
  306. + function = "sdio0";
  307. + };
  308. +
  309. + conf {
  310. + groups = "sdio0_2_grp";
  311. + slew-rate = <0>;
  312. + io-standard = <1>;
  313. + bias-disable;
  314. + };
  315. +
  316. + mux-cd {
  317. + groups = "gpio0_0_grp";
  318. + function = "sdio0_cd";
  319. + };
  320. +
  321. + conf-cd {
  322. + groups = "gpio0_0_grp";
  323. + bias-high-impedance;
  324. + bias-pull-up;
  325. + slew-rate = <0>;
  326. + io-standard = <1>;
  327. + };
  328. +
  329. + mux-wp {
  330. + groups = "gpio0_15_grp";
  331. + function = "sdio0_wp";
  332. + };
  333. +
  334. + conf-wp {
  335. + groups = "gpio0_15_grp";
  336. + bias-high-impedance;
  337. + bias-pull-up;
  338. + slew-rate = <0>;
  339. + io-standard = <1>;
  340. + };
  341. + };
  342. +
  343. + pinctrl_uart1_default: uart1-default {
  344. + mux {
  345. + groups = "uart1_10_grp";
  346. + function = "uart1";
  347. + };
  348. +
  349. + conf {
  350. + groups = "uart1_10_grp";
  351. + slew-rate = <0>;
  352. + io-standard = <1>;
  353. + };
  354. +
  355. + conf-rx {
  356. + pins = "MIO25";
  357. + bias-high-impedance;
  358. + };
  359. +
  360. + conf-tx {
  361. + pins = "MIO24";
  362. + bias-disable;
  363. + };
  364. + };
  365. +};
  366. +
  367. +&qspi {
  368. + u-boot,dm-pre-reloc;
  369. + status = "disabled";
  370. + is-dual = <0>;
  371. + num-cs = <1>;
  372. + flash@0 {
  373. + compatible = "n25q128a11";
  374. + reg = <0x0>;
  375. + spi-tx-bus-width = <1>;
  376. + spi-rx-bus-width = <4>;
  377. + spi-max-frequency = <50000000>;
  378. + #address-cells = <1>;
  379. + #size-cells = <1>;
  380. + partition@qspi-fsbl-uboot {
  381. + label = "qspi-fsbl-uboot";
  382. + reg = <0x0 0x100000>;
  383. + };
  384. + partition@qspi-linux {
  385. + label = "qspi-linux";
  386. + reg = <0x100000 0x500000>;
  387. + };
  388. + partition@qspi-device-tree {
  389. + label = "qspi-device-tree";
  390. + reg = <0x600000 0x20000>;
  391. + };
  392. + partition@qspi-rootfs {
  393. + label = "qspi-rootfs";
  394. + reg = <0x620000 0x5E0000>;
  395. + };
  396. + partition@qspi-bitstream {
  397. + label = "qspi-bitstream";
  398. + reg = <0xC00000 0x400000>;
  399. + };
  400. + };
  401. +};
  402. +
  403. +&sdhci0 {
  404. + u-boot,dm-pre-reloc;
  405. + status = "okay";
  406. +};
  407. +
  408. +&uart1 {
  409. + u-boot,dm-pre-reloc;
  410. + status = "okay";
  411. + pinctrl-names = "default";
  412. + pinctrl-0 = <&pinctrl_uart1_default>;
  413. +};
  414. --
  415. 2.23.0