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@@ -28,24 +28,25 @@ config BR2_arcle
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bool "ARC (little endian)"
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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- Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
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- that can be used from deeply embedded to high performance host
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- applications. Little endian.
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+ Synopsys' DesignWare ARC Processor Cores are a family of
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+ 32-bit CPUs that can be used from deeply embedded to high
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+ performance host applications. Little endian.
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config BR2_arceb
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bool "ARC (big endian)"
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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- Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
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- that can be used from deeply embedded to high performance host
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- applications. Big endian.
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+ Synopsys' DesignWare ARC Processor Cores are a family of
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+ 32-bit CPUs that can be used from deeply embedded to high
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+ performance host applications. Big endian.
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config BR2_arm
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bool "ARM (little endian)"
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# MMU support is set by the subarchitecture file, arch/Config.in.arm
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help
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- ARM is a 32-bit reduced instruction set computer (RISC) instruction
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- set architecture (ISA) developed by ARM Holdings. Little endian.
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+ ARM is a 32-bit reduced instruction set computer (RISC)
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+ instruction set architecture (ISA) developed by ARM Holdings.
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+ Little endian.
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http://www.arm.com/
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http://en.wikipedia.org/wiki/ARM
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@@ -53,8 +54,9 @@ config BR2_armeb
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bool "ARM (big endian)"
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# MMU support is set by the subarchitecture file, arch/Config.in.arm
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help
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- ARM is a 32-bit reduced instruction set computer (RISC) instruction
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- set architecture (ISA) developed by ARM Holdings. Big endian.
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+ ARM is a 32-bit reduced instruction set computer (RISC)
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+ instruction set architecture (ISA) developed by ARM Holdings.
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+ Big endian.
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http://www.arm.com/
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http://en.wikipedia.org/wiki/ARM
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@@ -81,8 +83,8 @@ config BR2_bfin
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select BR2_ARCH_HAS_FDPIC_SUPPORT
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select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
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help
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- The Blackfin is a family of 16 or 32-bit microprocessors developed,
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- manufactured and marketed by Analog Devices.
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+ The Blackfin is a family of 16 or 32-bit microprocessors
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+ developed, manufactured and marketed by Analog Devices.
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http://www.analog.com/
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http://en.wikipedia.org/wiki/Blackfin
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@@ -113,8 +115,8 @@ config BR2_microblazeel
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bool "Microblaze AXI (little endian)"
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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- Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus
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- based architecture (little endian)
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+ Soft processor core designed for Xilinx FPGAs from Xilinx. AXI
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+ bus based architecture (little endian)
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http://www.xilinx.com
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http://en.wikipedia.org/wiki/Microblaze
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@@ -122,8 +124,8 @@ config BR2_microblazebe
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bool "Microblaze non-AXI (big endian)"
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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- Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus
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- based architecture (non-AXI, big endian)
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+ Soft processor core designed for Xilinx FPGAs from Xilinx. PLB
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+ bus based architecture (non-AXI, big endian)
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http://www.xilinx.com
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http://en.wikipedia.org/wiki/Microblaze
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@@ -131,7 +133,8 @@ config BR2_mips
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bool "MIPS (big endian)"
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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- MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
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+ MIPS is a RISC microprocessor from MIPS Technologies. Big
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+ endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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@@ -139,7 +142,8 @@ config BR2_mipsel
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bool "MIPS (little endian)"
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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- MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
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+ MIPS is a RISC microprocessor from MIPS Technologies. Little
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+ endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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@@ -148,7 +152,8 @@ config BR2_mips64
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select BR2_ARCH_IS_64
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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- MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
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+ MIPS is a RISC microprocessor from MIPS Technologies. Big
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+ endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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@@ -157,7 +162,8 @@ config BR2_mips64el
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select BR2_ARCH_IS_64
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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- MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
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+ MIPS is a RISC microprocessor from MIPS Technologies. Little
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+ endian.
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http://www.mips.com/
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http://en.wikipedia.org/wiki/MIPS_Technologies
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@@ -180,8 +186,8 @@ config BR2_powerpc
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bool "PowerPC"
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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- PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
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- Big endian.
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+ PowerPC is a RISC architecture created by Apple-IBM-Motorola
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+ alliance. Big endian.
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http://www.power.org/
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http://en.wikipedia.org/wiki/Powerpc
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@@ -190,8 +196,8 @@ config BR2_powerpc64
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select BR2_ARCH_IS_64
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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- PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
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- Big endian.
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+ PowerPC is a RISC architecture created by Apple-IBM-Motorola
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+ alliance. Big endian.
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http://www.power.org/
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http://en.wikipedia.org/wiki/Powerpc
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@@ -200,8 +206,8 @@ config BR2_powerpc64le
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select BR2_ARCH_IS_64
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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- PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
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- Little endian.
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+ PowerPC is a RISC architecture created by Apple-IBM-Motorola
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+ alliance. Little endian.
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http://www.power.org/
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http://en.wikipedia.org/wiki/Powerpc
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@@ -209,8 +215,9 @@ config BR2_sh
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bool "SuperH"
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select BR2_ARCH_HAS_MMU_OPTIONAL
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help
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- SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)
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- instruction set architecture (ISA) developed by Hitachi.
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+ SuperH (or SH) is a 32-bit reduced instruction set computer
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+ (RISC) instruction set architecture (ISA) developed by
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+ Hitachi.
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http://www.hitachi.com/
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http://en.wikipedia.org/wiki/SuperH
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@@ -218,8 +225,9 @@ config BR2_sparc
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bool "SPARC"
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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- SPARC (from Scalable Processor Architecture) is a RISC instruction
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- set architecture (ISA) developed by Sun Microsystems.
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+ SPARC (from Scalable Processor Architecture) is a RISC
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+ instruction set architecture (ISA) developed by Sun
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+ Microsystems.
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http://www.oracle.com/sun
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http://en.wikipedia.org/wiki/Sparc
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@@ -228,8 +236,9 @@ config BR2_sparc64
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select BR2_ARCH_IS_64
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select BR2_ARCH_HAS_MMU_MANDATORY
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help
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- SPARC (from Scalable Processor Architecture) is a RISC instruction
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- set architecture (ISA) developed by Sun Microsystems.
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+ SPARC (from Scalable Processor Architecture) is a RISC
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+ instruction set architecture (ISA) developed by Sun
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+ Microsystems.
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http://www.oracle.com/sun
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http://en.wikipedia.org/wiki/Sparc
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@@ -349,27 +358,27 @@ config BR2_BINFMT_ELF
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depends on BR2_USE_MMU
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select BR2_BINFMT_SUPPORTS_SHARED
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help
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- ELF (Executable and Linkable Format) is a format for libraries and
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- executables used across different architectures and operating
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- systems.
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+ ELF (Executable and Linkable Format) is a format for libraries
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+ and executables used across different architectures and
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+ operating systems.
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config BR2_BINFMT_FDPIC
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bool "FDPIC"
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depends on BR2_ARCH_HAS_FDPIC_SUPPORT
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select BR2_BINFMT_SUPPORTS_SHARED
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help
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- ELF FDPIC binaries are based on ELF, but allow the individual load
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- segments of a binary to be located in memory independently of each
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- other. This makes this format ideal for use in environments where no
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- MMU is available.
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+ ELF FDPIC binaries are based on ELF, but allow the individual
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+ load segments of a binary to be located in memory
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+ independently of each other. This makes this format ideal for
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+ use in environments where no MMU is available.
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config BR2_BINFMT_FLAT
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bool "FLAT"
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depends on !BR2_USE_MMU
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help
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- FLAT binary is a relatively simple and lightweight executable format
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- based on the original a.out format. It is widely used in environment
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- where no MMU is available.
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+ FLAT binary is a relatively simple and lightweight executable
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+ format based on the original a.out format. It is widely used
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+ in environment where no MMU is available.
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endchoice
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@@ -393,8 +402,8 @@ config BR2_BINFMT_FLAT_SEP_DATA
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# absolute jump" or "error: value -yyyyy out of range".
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depends on BR2_bfin
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help
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- Allow for the data and text segments to be separated and placed in
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- different regions of memory.
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+ Allow for the data and text segments to be separated and
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+ placed in different regions of memory.
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config BR2_BINFMT_FLAT_SHARED
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bool "Shared binary"
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