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arch: remove BR2_ARCH_HAS_ATOMICS option

Now that BR2_ARCH_HAS_ATOMICS is no longer used anywhere, we can
remove it from arch/Config.in*, as well as from the documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
Thomas Petazzoni vor 8 Jahren
Ursprung
Commit
4a3f597a0e

+ 0 - 4
arch/Config.in

@@ -284,10 +284,6 @@ config BR2_GCC_TARGET_FLOAT_ABI
 config BR2_GCC_TARGET_MODE
 	string
 
-# If the architecture has atomic operations, select this:
-config BR2_ARCH_HAS_ATOMICS
-	bool
-
 # Must be selected by binary formats that support shared libraries.
 config BR2_BINFMT_SUPPORTS_SHARED
 	bool

+ 0 - 3
arch/Config.in.aarch64

@@ -5,6 +5,3 @@ config BR2_ARCH
 config BR2_ENDIAN
 	default "LITTLE" if BR2_aarch64
 	default "BIG"	 if BR2_aarch64_be
-
-config BR2_ARCH_HAS_ATOMICS
-	default y

+ 0 - 3
arch/Config.in.arc

@@ -21,9 +21,6 @@ config BR2_ARC_ATOMIC_EXT
 	bool "Atomic extension (LLOCK/SCOND instructions)"
 	default y if BR2_arc770d || BR2_archs38
 
-config BR2_ARCH_HAS_ATOMICS
-	default y if BR2_ARC_ATOMIC_EXT
-
 config BR2_ARCH
 	default "arc"	if BR2_arcle
 	default "arceb"	if BR2_arceb

+ 0 - 3
arch/Config.in.arm

@@ -426,9 +426,6 @@ config BR2_ENDIAN
 	default "LITTLE" if BR2_arm
 	default "BIG"	 if BR2_armeb
 
-config BR2_ARCH_HAS_ATOMICS
-	default y
-
 config BR2_GCC_TARGET_CPU
 	default "arm920t"	if BR2_arm920t
 	default "arm922t"	if BR2_arm922t

+ 0 - 3
arch/Config.in.bfin

@@ -68,9 +68,6 @@ config BR2_ARCH
 config BR2_ENDIAN
 	default "LITTLE"
 
-config BR2_ARCH_HAS_ATOMICS
-	default y
-
 config BR2_GCC_TARGET_CPU
 	default bf606		if BR2_bf606
 	default bf607		if BR2_bf607

+ 0 - 3
arch/Config.in.m68k

@@ -4,9 +4,6 @@ config BR2_ARCH
 config BR2_ENDIAN
 	default "BIG"
 
-config BR2_ARCH_HAS_ATOMICS
-	default y
-
 config BR2_GCC_TARGET_ARCH
 	default "68000"		if BR2_m68k_68000
 	default "68010"		if BR2_m68k_68010

+ 0 - 3
arch/Config.in.microblaze

@@ -9,6 +9,3 @@ config BR2_ENDIAN
 config BR2_microblaze
 	bool
 	default y if BR2_microblazeel || BR2_microblazebe
-
-config BR2_ARCH_HAS_ATOMICS
-	default y

+ 0 - 3
arch/Config.in.mips

@@ -67,9 +67,6 @@ config BR2_ENDIAN
 	default "LITTLE"	if BR2_mipsel || BR2_mips64el
 	default "BIG" 	    	if BR2_mips || BR2_mips64
 
-config BR2_ARCH_HAS_ATOMICS
-	default y
-
 config BR2_GCC_TARGET_ARCH
 	default "mips32"	if BR2_mips_32
 	default "mips32r2"	if BR2_mips_32r2

+ 0 - 3
arch/Config.in.nios2

@@ -3,6 +3,3 @@ config BR2_ARCH
 
 config BR2_ENDIAN
 	default "LITTLE"
-
-config BR2_ARCH_HAS_ATOMICS
-	default y

+ 0 - 3
arch/Config.in.powerpc

@@ -164,9 +164,6 @@ config BR2_ENDIAN
 	default "BIG"    if BR2_powerpc || BR2_powerpc64
 	default "LITTLE" if BR2_powerpc64le
 
-config BR2_ARCH_HAS_ATOMICS
-	default y
-
 config BR2_GCC_TARGET_CPU
 	default "401"		if BR2_powerpc_401
 	default "403"		if BR2_powerpc_403

+ 0 - 3
arch/Config.in.sh

@@ -28,6 +28,3 @@ config BR2_ARCH
 config BR2_ENDIAN
 	default "LITTLE"	if BR2_sh4 || BR2_sh4a || BR2_sh64
 	default "BIG"		if BR2_sh2a || BR2_sh4eb || BR2_sh4aeb
-
-config BR2_ARCH_HAS_ATOMICS
-	default y

+ 0 - 3
arch/Config.in.x86

@@ -245,9 +245,6 @@ config BR2_ARCH
 config BR2_ENDIAN
 	default "LITTLE"
 
-config BR2_ARCH_HAS_ATOMICS
-	default y if !BR2_x86_i386
-
 config BR2_GCC_TARGET_ARCH
 	default "i386"		if BR2_x86_i386
 	default "i486"		if BR2_x86_i486

+ 0 - 3
arch/Config.in.xtensa

@@ -54,6 +54,3 @@ config BR2_ENDIAN
 
 config BR2_ARCH
 	default "xtensa"	if BR2_xtensa
-
-config BR2_ARCH_HAS_ATOMICS
-	default y

+ 0 - 5
docs/manual/adding-packages-directory.txt

@@ -274,11 +274,6 @@ use in the comment.
 ** Dependency symbol: +BR2_USE_MMU+
 ** Comment string: no comment to be added
 
-* Atomic instructions (whereby the architecture has instructions to
-  perform some operations atomically, like LOCKCMPXCHG on x86)
-** Dependency symbol: +BR2_ARCH_HAS_ATOMICS+
-** Comment string: no comment to be added
-
 * Gcc +__sync_*+ built-ins used for atomic operations. They are
   available in variants operating on 1 byte, 2 bytes, 4 bytes and 8
   bytes. Since different architectures support atomic operations on