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@@ -13,22 +13,22 @@
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-- --
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-- Licensed under the the Creative Common BY-NC-ND : --
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-- You are free to: --
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--- Share — copy and redistribute the material in any medium or format --
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+-- Share, copy and redistribute the material in any medium or format --
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-- --
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-- The licensor cannot revoke these freedoms as long as you follow the --
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-- license terms. --
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-- --
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-- Under the following terms: --
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-- --
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--- Attribution — You must give appropriate credit, provide a link to --
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+-- Attribution - You must give appropriate credit, provide a link to --
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-- the license, and indicate if changes were made. You --
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-- may do so in any reasonable manner, but not in any way --
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-- that suggests the licensor endorses you or your use. --
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--- NonCommercial — You may not use the material for commercial purposes. --
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--- NoDerivatives — If you remix, transform, or build upon the material, --
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+-- NonCommercial - You may not use the material for commercial purposes. --
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+-- NoDerivatives - If you remix, transform, or build upon the material, --
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-- you may not distribute the modified material. --
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-- --
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--- No additional restrictions — You may not apply legal terms or --
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+-- No additional restrictions - You may not apply legal terms or --
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-- technological measures that legally --
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-- restrict others from doing anything the --
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-- license permits. --
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@@ -74,7 +74,7 @@ use IEEE.NUMERIC_STD.ALL;
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entity WonderMadeleine is
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port(
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- D_BUS: inout std_logic_vector( 7 downto 0); -- Lower part of the 16 bit Data bus
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+ D_BUS: inout std_logic_vector( 7 downto 0); -- 16 bit Data bus
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A_BUS_H: in std_logic_vector(19 downto 16); -- High part of 20 bit Address bus
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A_BUS_L: in std_logic_vector( 3 downto 0); -- Low part of 20 bit Address bus
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@@ -111,8 +111,8 @@ architecture Behavioral of WonderMadeleine is
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component GpioRegs is
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port(
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sel: in std_logic;
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- nRD: in std_logic;
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- nWR: in std_logic;
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+ nRD: in std_logic;
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+ nWR: in std_logic;
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regNum: in std_logic;
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data: inout std_logic_vector(7 downto 0);
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clock: in std_logic;
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@@ -124,8 +124,8 @@ architecture Behavioral of WonderMadeleine is
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component EepromRegs
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port(
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sel: in std_logic;
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- nRD: in std_logic;
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- nWR: in std_logic;
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+ nRD: in std_logic;
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+ nWR: in std_logic;
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regNum: in std_logic_vector(2 downto 0);
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data: inout std_logic_vector(7 downto 0);
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clock: in std_logic;
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@@ -140,15 +140,16 @@ architecture Behavioral of WonderMadeleine is
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component RtcRegs
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port(
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sel: in std_logic;
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- nRD: in std_logic;
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- nWR: in std_logic;
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+ nRD: in std_logic;
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+ nWR: in std_logic;
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regNum: in std_logic;
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data: inout std_logic_vector(7 downto 0);
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clock: in std_logic;
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-- RTC PINs
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SDA: inout std_logic;
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CLK: out std_logic;
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- CS: out std_logic
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+ CS: out std_logic;
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+ nINT: out std_logic
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);
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end component;
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@@ -172,7 +173,7 @@ begin
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-- Instantiates all needed components
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gpioInst: GpioRegs port map(gpioRegSel, nRd, nWR, ioRegNum(0), D_BUS, SYS_CLK, GPIO);
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eepromInst: EepromRegs port map(eepromRegSel, nRd, nWR, ioRegNum(2 downto 0), D_BUS, SYS_CLK, EEP_CS, EEP_CK, EEP_DI, EEP_DO);
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- rtcInst: RtcRegs port map(rtcRegSel, nRd, nWR, ioRegNum(0), D_BUS, SYS_CLK, RTC_DATA, RTC_CLK, RTC_CS);
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+ rtcInst: RtcRegs port map(rtcRegSel, nRd, nWR, ioRegNum(0), D_BUS, SYS_CLK, RTC_DATA, RTC_CLK, RTC_CS, nINT);
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nINT <= 'Z';
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nMBC <= rMBC;
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@@ -180,18 +181,14 @@ begin
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d_latches: process (nSEL, nIO, nRD, nWR, D_BUS, writeD, readD)
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begin
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if (nSEL='0' and nIO = '0' and nRD = '0' and nWR = '1') then
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- if (nIO = '0') then
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- D_BUS <= writeD;
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- else
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- D_BUS <= "ZZZZZZZZ";
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- end if;
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+ D_BUS <= writeD;
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readD <= D_BUS;
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elsif (nSEL='0' and nIO = '0' and nRD = '1' and nWR = '0') then
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D_BUS <= "ZZZZZZZZ";
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readD <= D_BUS;
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else
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D_BUS <= "ZZZZZZZZ";
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- readD <= "11111111";
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+ readD <= D_BUS;
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end if;
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end process;
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@@ -211,7 +208,7 @@ begin
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eepromRegSel <= '0';
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rtcRegSel <= '0';
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gpioRegSel <= '0';
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- elsif (nSEL = '0' and validRange = '1') then
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+ elsif (nSEL = '0' and validRange = '1') then
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if(nIO = '0') then
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nSRAM_CS <= '1'; nROM_CS <= '1';
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if (falling_edge(nRWTop) and nRD = '0' and nWR = '1') then
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@@ -220,15 +217,15 @@ begin
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when X"C1" => writeD <= regC1; eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '0';
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when X"C2" => writeD <= regC2; eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '0';
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when X"C3" => writeD <= regC3; eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '0';
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- when X"C4" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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- when X"C5" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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- when X"C6" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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- when X"C7" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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- when X"C8" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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- when X"CA" => eepromRegSel <= '0'; rtcRegSel <= '1'; gpioRegSel <= '0';
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- when X"CB" => eepromRegSel <= '0'; rtcRegSel <= '1'; gpioRegSel <= '0';
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+ when X"C4" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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+ when X"C5" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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+ when X"C6" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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+ when X"C7" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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+ when X"C8" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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+ when X"CA" => eepromRegSel <= '0'; rtcRegSel <= '1'; gpioRegSel <= '0';
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+ when X"CB" => eepromRegSel <= '0'; rtcRegSel <= '1'; gpioRegSel <= '0';
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when X"CC" => eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '1';
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- when X"CD" => eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '1';
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+ when X"CD" => eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '1';
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when others => writeD <= X"FF"; eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '0';
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end case;
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elsif (falling_edge(nRWTop) and nRD = '1' and nWR = '0') then
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@@ -237,15 +234,15 @@ begin
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when X"C1" => regC1 <= readD; eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '0';
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when X"C2" => regC2 <= readD; eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '0';
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when X"C3" => regC3 <= readD; eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '0';
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- when X"C4" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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- when X"C5" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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- when X"C6" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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- when X"C7" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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- when X"C8" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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- when X"CA" => eepromRegSel <= '0'; rtcRegSel <= '1'; gpioRegSel <= '0';
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- when X"CB" => eepromRegSel <= '0'; rtcRegSel <= '1'; gpioRegSel <= '0';
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+ when X"C4" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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+ when X"C5" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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+ when X"C6" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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+ when X"C7" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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+ when X"C8" => eepromRegSel <= '1'; rtcRegSel <= '0'; gpioRegSel <= '0';
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+ when X"CA" => eepromRegSel <= '0'; rtcRegSel <= '1'; gpioRegSel <= '0';
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+ when X"CB" => eepromRegSel <= '0'; rtcRegSel <= '1'; gpioRegSel <= '0';
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when X"CC" => eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '1';
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- when X"CD" => eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '1';
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+ when X"CD" => eepromRegSel <= '0'; rtcRegSel <= '0'; gpioRegSel <= '1';
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when others => null;
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end case;
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end if;
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@@ -283,7 +280,7 @@ begin
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when X"2" => validRange := '1'; EXT_A <= regC2;
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when X"3" => validRange := '1'; EXT_A <= regC3;
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when others => validRange := '1'; EXT_A(7 downto 4) <= regC0(3 downto 0);
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- EXT_A(3 downto 0) <= A_BUS_H;
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+ EXT_A(3 downto 0) <= A_BUS_H;
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end case;
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end process;
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