xrp_kernel_dsp_interface.h 4.1 KB

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  1. /*
  2. * Data structures and constants for generic XRP interface between
  3. * linux and DSP
  4. *
  5. * Copyright (c) 2015 - 2019 Cadence Design Systems, Inc.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining
  8. * a copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation the rights to use, copy, modify, merge, publish,
  11. * distribute, sublicense, and/or sell copies of the Software, and to
  12. * permit persons to whom the Software is furnished to do so, subject to
  13. * the following conditions:
  14. *
  15. * The above copyright notice and this permission notice shall be included
  16. * in all copies or substantial portions of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21. * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
  22. * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. * Alternatively you can use and distribute this file under the terms of
  27. * the GNU General Public License version 2 or later.
  28. */
  29. #ifndef _XRP_KERNEL_DSP_INTERFACE_H
  30. #define _XRP_KERNEL_DSP_INTERFACE_H
  31. #ifndef XRP_DSP_COMM_BASE_MAGIC
  32. #define XRP_DSP_COMM_BASE_MAGIC 0x20161006
  33. #endif
  34. enum {
  35. XRP_DSP_SYNC_IDLE = 0,
  36. XRP_DSP_SYNC_HOST_TO_DSP = 0x1,
  37. XRP_DSP_SYNC_DSP_TO_HOST = 0x3,
  38. XRP_DSP_SYNC_START = 0x101,
  39. XRP_DSP_SYNC_DSP_READY_V1 = 0x203,
  40. XRP_DSP_SYNC_DSP_READY_V2 = 0x303,
  41. };
  42. enum {
  43. XRP_DSP_SYNC_TYPE_ACCEPT = 0x80000000,
  44. XRP_DSP_SYNC_TYPE_MASK = 0x00ffffff,
  45. XRP_DSP_SYNC_TYPE_LAST = 0,
  46. XRP_DSP_SYNC_TYPE_HW_SPEC_DATA = 1,
  47. XRP_DSP_SYNC_TYPE_HW_QUEUES = 2,
  48. XRP_DSP_SYNC_TYPE_HW_DEBUG_INFO =3,
  49. };
  50. struct xrp_dsp_tlv {
  51. __u32 type;
  52. __u32 length;
  53. __u32 value[0];
  54. };
  55. struct xrp_dsp_sync_v1 {
  56. __u32 sync;
  57. __u32 hw_sync_data[0];
  58. };
  59. struct xrp_dsp_sync_v2 {
  60. __u32 sync;
  61. __u32 reserved[3];
  62. struct xrp_dsp_tlv hw_sync_data[0];
  63. };
  64. enum log_level{
  65. FW_DEBUG_LOG_MODE_QUIET, /* disabel FW log printf */
  66. FW_DEBUG_LOG_MODE_ERR, /* enable FW log printf with error level */
  67. FW_DEBUG_LOG_MODE_WRN, /* enable FW log printf with warning level */
  68. FW_DEBUG_LOG_MODE_INF, /* enable FW log printf with info level*/
  69. FW_DEBUG_LOG_MODE_DBG, /* enable FW log printf with debug level*/
  70. FW_DEBUG_LOG_MODE_TRACE, /* enable FW log printf with trace level*/
  71. };
  72. struct xrp_dsp_debug_info{
  73. __u32 panic_addr;
  74. __u32 log_level;
  75. __u32 profile_addr;
  76. };
  77. enum {
  78. XRP_DSP_BUFFER_FLAG_READ = 0x1,
  79. XRP_DSP_BUFFER_FLAG_WRITE = 0x2,
  80. };
  81. struct xrp_dsp_buffer {
  82. /*
  83. * When submitted to DSP: types of access allowed
  84. * When returned to host: actual access performed
  85. */
  86. __u32 flags;
  87. __u32 size;
  88. __u32 addr;
  89. };
  90. enum {
  91. XRP_DSP_CMD_FLAG_REQUEST_VALID = 0x00000001,
  92. XRP_DSP_CMD_FLAG_RESPONSE_VALID = 0x00000002,
  93. XRP_DSP_CMD_FLAG_REQUEST_NSID = 0x00000004,
  94. XRP_DSP_CMD_FLAG_RESPONSE_DELIVERY_FAIL = 0x00000008,
  95. };
  96. enum {
  97. XRP_DSP_REPORT_INVALID = 0,
  98. XRP_DSP_REPORT_WORKING = 0x1,
  99. XRP_DSP_REPORT_OVERWIRTE = 0x3,
  100. };
  101. #define XRP_DSP_REPORT_TO_HOST_FLAG (0x10000000)
  102. #define XRP_DSP_CMD_INLINE_DATA_SIZE 16
  103. #define XRP_DSP_CMD_INLINE_BUFFER_COUNT 1
  104. #define XRP_DSP_CMD_NAMESPACE_ID_SIZE 16
  105. #define XRP_DSP_CMD_STRIDE 128
  106. struct xrp_dsp_cmd {
  107. __u32 flags;
  108. __u32 in_data_size;
  109. __u32 out_data_size;
  110. __u32 buffer_size;
  111. union {
  112. __u32 in_data_addr;
  113. __u8 in_data[XRP_DSP_CMD_INLINE_DATA_SIZE];
  114. };
  115. union {
  116. __u32 out_data_addr;
  117. __u8 out_data[XRP_DSP_CMD_INLINE_DATA_SIZE];
  118. };
  119. union {
  120. __u32 buffer_addr;
  121. struct xrp_dsp_buffer buffer_data[XRP_DSP_CMD_INLINE_BUFFER_COUNT];
  122. __u8 buffer_alignment[XRP_DSP_CMD_INLINE_DATA_SIZE];
  123. };
  124. __u8 nsid[XRP_DSP_CMD_NAMESPACE_ID_SIZE];
  125. /*************DSP report channel***************************************/
  126. __u32 report_id;
  127. __u32 report_paylad_size;
  128. __u32 report_buffer_size;
  129. __u32 report_status;
  130. union {
  131. __u32 report_addr;
  132. __u8 report_data[XRP_DSP_CMD_INLINE_DATA_SIZE];
  133. };
  134. __u32 cmd_flag;
  135. };
  136. #endif