cdns,xrp-hw-simple.txt 2.0 KB

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  1. Bindings for the Cadence Xtensa Remote Processing Simple HW-specific driver.
  2. This binding is an extension of the cdns,xrp binding. All properties of
  3. that binding are in effect.
  4. Required properties:
  5. - compatible: shall be "cdns,xrp-hw-simple".
  6. - reg: register locations of the DSP MMIO block, DSP communication area and
  7. DSP shared memory area.
  8. Optional properties:
  9. - device-irq: 3 32-bit cells:
  10. - first: offset of the 32-bit device IRQ MMIO register from the DSP MMIO
  11. block start as seen by the device;
  12. - second: register bit index that controls IRQ;
  13. - third: DSP IRQ number (normal core IRQ number, not external IRQ number)
  14. controlled by this register/bit.
  15. - device-irq-host-offset: offset of the 32-bit device IRQ MMIO register from
  16. the DSP MMIO block start as seen by the host. If omitted device-irq cell 0
  17. is used;
  18. - device-irq-mode: 0 for none (polling), 1 for level, 2 for edge, 3 for
  19. software-assisted (by LUA script in the XTSC) edge.
  20. - host-irq: 2 32-bit cells:
  21. - first: offset of the 32-bit device IRQ MMIO register from the DSP MMIO
  22. block start;
  23. - second: register bit index that controls IRQ.
  24. - host-irq-mode: 0 for none (polling), 1 for level, 2 for edge.
  25. - interrupts: host IRQ number controlled by this register/bit.
  26. Example:
  27. xrp@0 {
  28. #address-cells = <1>;
  29. #size-cells = <1>;
  30. compatible = "cdns,xrp-hw-simple";
  31. reg = <0xfd001000 0x00000200 /* DSP MMIO */
  32. 0xf0000000 0x00001000 /* DSP communication area */
  33. 0xf0001000 0x00fff000>; /* DSP shared memory */
  34. device-irq = <0 1 5>; /* offset, bit#, IRQ# */
  35. device-irq-host-offset = <0>;
  36. device-irq-mode = <1>;
  37. host-irq = <0xfffff000 0>; /* offset, bit# */
  38. host-irq-mode = <2>;
  39. interrupts = <15 0>;
  40. firmware-name = "xrp0.elf";
  41. ranges = <0x00000000 0x00000000 0x10000000
  42. 0x3ffc0000 0xc0000000 0x00020000
  43. 0x3ffe0000 0xc0020000 0x00020000
  44. 0x50000000 0x50000000 0x01000000
  45. 0x60000000 0x60000000 0x20000000
  46. 0xf0000000 0xf0000000 0x0d000000>;
  47. dsp@0 {
  48. };
  49. };