dts_FM_95P_VI_V2_SP1.txt 26 KB

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  1. /dts-v1/;
  2. / {
  3. model = "T-HEAD Light FM c910 soc";
  4. compatible = "thead,light_fm_c910_soc";
  5. #address-cells = <2>;
  6. #size-cells = <2>;
  7. memory@0 {
  8. device_type = "memory";
  9. /*
  10. * Total memory size: 8GB in HAPS system:
  11. * 0x0 00000000 - 0x1 80000000: 6GB reserved for Linux system
  12. * 0x1 80000000 - 0x0 80000000: 2GB reserved for Media system
  13. */
  14. reg = <0x0 0x00000000 0x0 0x60000000>;
  15. };
  16. reserved-memory {
  17. #address-cells = <2>;
  18. #size-cells = <2>;
  19. ranges;
  20. media-buffer@c0000000 {
  21. compatible = "shared-dma-pool";
  22. reg = <0x0 0xc0000000 0x0 0x40000000>;
  23. reusable;
  24. status = "okay";
  25. };
  26. isp_reserved: isp@40000000 {
  27. no-map;
  28. reg = <0 0x40000000 0 0x10000000>;
  29. status = "okay";
  30. };
  31. };
  32. cpus {
  33. #address-cells = <1>;
  34. #size-cells = <0>;
  35. timebase-frequency = <3000000>;
  36. cpu@0 {
  37. device_type = "cpu";
  38. reg = <0>;
  39. status = "okay";
  40. compatible = "riscv";
  41. riscv,isa = "rv64imafdcvsu";
  42. mmu-type = "riscv,sv39";
  43. cpu0_intc: interrupt-controller {
  44. #interrupt-cells = <1>;
  45. compatible = "riscv,cpu-intc";
  46. interrupt-controller;
  47. };
  48. };
  49. cpu@1 {
  50. device_type = "cpu";
  51. reg = <1>;
  52. status = "disabled";
  53. compatible = "riscv";
  54. riscv,isa = "rv64imafdcvsu";
  55. mmu-type = "riscv,sv39";
  56. cpu1_intc: interrupt-controller {
  57. #interrupt-cells = <1>;
  58. compatible = "riscv,cpu-intc";
  59. interrupt-controller;
  60. };
  61. };
  62. cpu@2 {
  63. device_type = "cpu";
  64. reg = <2>;
  65. status = "disabled";
  66. compatible = "riscv";
  67. riscv,isa = "rv64imafdcvsu";
  68. mmu-type = "riscv,sv39";
  69. cpu2_intc: interrupt-controller {
  70. #interrupt-cells = <1>;
  71. compatible = "riscv,cpu-intc";
  72. interrupt-controller;
  73. };
  74. };
  75. cpu@3 {
  76. device_type = "cpu";
  77. reg = <3>;
  78. status = "disabled";
  79. compatible = "riscv";
  80. riscv,isa = "rv64imafdcvsu";
  81. mmu-type = "riscv,sv39";
  82. cpu3_intc: interrupt-controller {
  83. #interrupt-cells = <1>;
  84. compatible = "riscv,cpu-intc";
  85. interrupt-controller;
  86. };
  87. };
  88. };
  89. soc {
  90. compatible = "simple-bus";
  91. #address-cells = <2>;
  92. #size-cells = <2>;
  93. ranges;
  94. intc: interrupt-controller@ffd8000000 {
  95. #interrupt-cells = <1>;
  96. compatible = "riscv,plic0";
  97. interrupt-controller;
  98. interrupts-extended = <
  99. &cpu0_intc 0xffffffff &cpu0_intc 9
  100. &cpu1_intc 0xffffffff &cpu1_intc 9
  101. &cpu2_intc 0xffffffff &cpu2_intc 9
  102. &cpu3_intc 0xffffffff &cpu3_intc 9
  103. >;
  104. reg = <0xff 0xd8000000 0x0 0x04000000>;
  105. reg-names = "control";
  106. riscv,max-priority = <7>;
  107. riscv,ndev = <240>;
  108. };
  109. clocks {
  110. compatible = "simple-bus";
  111. #address-cells = <1>;
  112. #size-cells = <0>;
  113. dummy_clock_apb: apb-clock@0 {
  114. compatible = "fixed-clock";
  115. reg = <0>; /* Not address, just for index */
  116. clock-frequency = <50000000>;
  117. clock-output-names = "dummy_clock_apb";
  118. #clock-cells = <0>;
  119. };
  120. dummy_clock_ref: ref-clock@1 {
  121. compatible = "fixed-clock";
  122. reg = <1>; /* Not address, just for index */
  123. clock-frequency = <50000000>;
  124. clock-output-names = "dummy_clock_ref";
  125. #clock-cells = <0>;
  126. };
  127. dummy_clock_suspend: suspend-clock@2 {
  128. compatible = "fixed-clock";
  129. reg = <2>; /* Not address, just for index */
  130. clock-frequency = <50000000>;
  131. clock-output-names = "dummy_clock_suspend";
  132. #clock-cells = <0>;
  133. };
  134. dummy_clock_rtc: rtc-clock@3 {
  135. compatible = "fixed-clock";
  136. reg = <3>; /* Not address, just for index */
  137. clock-frequency = <32768>;
  138. clock-output-names = "dummy_clock_rtc";
  139. #clock-cells = <0>;
  140. };
  141. dummy_clock_ahb: ahb-clock@4 {
  142. compatible = "fixed-clock";
  143. reg = <4>; /* Not address, just for index */
  144. clock-frequency = <50000000>;
  145. clock-output-names = "dummy_clock_ahb";
  146. #clock-cells = <0>;
  147. };
  148. dummy_clock_npu: npu-clock@5 {
  149. compatible = "fixed-clock";
  150. reg = <5>; /* Not address, just for index */
  151. clock-frequency = <24000000>;
  152. clock-output-names = "dummy_clock_npu";
  153. #clock-cells = <0>;
  154. };
  155. };
  156. gpio0: gpio@ffec005000 {
  157. compatible = "snps,dw-apb-gpio";
  158. reg = <0xff 0xec005000 0x0 0x1000>;
  159. #address-cells = <1>;
  160. #size-cells = <0>;
  161. gpio0_porta: gpio0-controller@0 {
  162. compatible = "snps,dw-apb-gpio-port";
  163. gpio-controller;
  164. #gpio-cells = <2>;
  165. snps,nr-gpios = <32>;
  166. reg = <0>;
  167. interrupt-controller;
  168. #interrupt-cells = <2>;
  169. interrupt-parent = <&intc>;
  170. interrupts = <56>;
  171. };
  172. };
  173. gpio1: gpio@ffec006000 {
  174. compatible = "snps,dw-apb-gpio";
  175. reg = <0xff 0xec006000 0x0 0x1000>;
  176. #address-cells = <1>;
  177. #size-cells = <0>;
  178. gpio1_porta: gpio1-controller@0 {
  179. compatible = "snps,dw-apb-gpio-port";
  180. gpio-controller;
  181. #gpio-cells = <2>;
  182. snps,nr-gpios = <32>;
  183. reg = <0>;
  184. interrupt-controller;
  185. #interrupt-cells = <2>;
  186. interrupt-parent = <&intc>;
  187. interrupts = <57>;
  188. };
  189. };
  190. gpio2: gpio@ffe7f34000 {
  191. compatible = "snps,dw-apb-gpio";
  192. reg = <0xff 0xe7f34000 0x0 0x1000>;
  193. #address-cells = <1>;
  194. #size-cells = <0>;
  195. gpio2_porta: gpio2-controller@0 {
  196. compatible = "snps,dw-apb-gpio-port";
  197. gpio-controller;
  198. #gpio-cells = <2>;
  199. snps,nr-gpios = <32>;
  200. reg = <0>;
  201. interrupt-controller;
  202. #interrupt-cells = <2>;
  203. interrupt-parent = <&intc>;
  204. interrupts = <58>;
  205. };
  206. };
  207. gpio3: gpio@ffe7f38000 {
  208. compatible = "snps,dw-apb-gpio";
  209. reg = <0xff 0xe7f38000 0x0 0x1000>;
  210. #address-cells = <1>;
  211. #size-cells = <0>;
  212. gpio3_porta: gpio3-controller@0 {
  213. compatible = "snps,dw-apb-gpio-port";
  214. gpio-controller;
  215. #gpio-cells = <2>;
  216. snps,nr-gpios = <32>;
  217. reg = <0>;
  218. interrupt-controller;
  219. #interrupt-cells = <2>;
  220. interrupt-parent = <&intc>;
  221. interrupts = <59>;
  222. };
  223. };
  224. timer0: timer@ffefc32000 {
  225. compatible = "snps,dw-apb-timer";
  226. reg = <0xff 0xefc32000 0x0 0x14>;
  227. clocks = <&dummy_clock_apb>;
  228. clock-names = "timer";
  229. clock-frequency = <50000000>;
  230. interrupts = <16>;
  231. interrupt-parent = <&intc>;
  232. status = "okay";
  233. };
  234. timer1: timer@ffefc32014 {
  235. compatible = "snps,dw-apb-timer";
  236. reg = <0xff 0xefc32014 0x0 0x14>;
  237. clocks = <&dummy_clock_apb>;
  238. clock-names = "timer";
  239. clock-frequency = <50000000>;
  240. interrupts = <17>;
  241. interrupt-parent = <&intc>;
  242. status = "okay";
  243. };
  244. timer2: timer@ffefc32028 {
  245. compatible = "snps,dw-apb-timer";
  246. reg = <0xff 0xefc32028 0x0 0x14>;
  247. clocks = <&dummy_clock_apb>;
  248. clock-names = "timer";
  249. clock-frequency = <50000000>;
  250. interrupts = <18>;
  251. interrupt-parent = <&intc>;
  252. status = "disabled";
  253. };
  254. timer3: timer@ffefc3203c {
  255. compatible = "snps,dw-apb-timer";
  256. reg = <0xff 0xefc3203c 0x0 0x14>;
  257. clocks = <&dummy_clock_apb>;
  258. clock-names = "timer";
  259. clock-frequency = <50000000>;
  260. interrupts = <19>;
  261. interrupt-parent = <&intc>;
  262. status = "disabled";
  263. };
  264. timer4: timer@ffffc33000 {
  265. compatible = "snps,dw-apb-timer";
  266. reg = <0xff 0xffc33000 0x0 0x14>;
  267. clocks = <&dummy_clock_apb>;
  268. clock-names = "timer";
  269. clock-frequency = <50000000>;
  270. interrupts = <20>;
  271. interrupt-parent = <&intc>;
  272. status = "disabled";
  273. };
  274. timer5: timer@ffffc33014 {
  275. compatible = "snps,dw-apb-timer";
  276. reg = <0xff 0xffc33014 0x0 0x14>;
  277. clocks = <&dummy_clock_apb>;
  278. clock-names = "timer";
  279. clock-frequency = <50000000>;
  280. interrupts = <21>;
  281. interrupt-parent = <&intc>;
  282. status = "disabled";
  283. };
  284. timer6: timer@ffffc33028 {
  285. compatible = "snps,dw-apb-timer";
  286. reg = <0xff 0xffc33028 0x0 0x14>;
  287. clocks = <&dummy_clock_apb>;
  288. clock-names = "timer";
  289. clock-frequency = <50000000>;
  290. interrupts = <22>;
  291. interrupt-parent = <&intc>;
  292. status = "disabled";
  293. };
  294. timer7: timer@ffffc3303c {
  295. compatible = "snps,dw-apb-timer";
  296. reg = <0xff 0xffc3303c 0x0 0x14>;
  297. clocks = <&dummy_clock_apb>;
  298. clock-names = "timer";
  299. clock-frequency = <50000000>;
  300. interrupts = <23>;
  301. interrupt-parent = <&intc>;
  302. status = "disabled";
  303. };
  304. // keys: gpio-keys@100 {
  305. // compatible = "gpio-keys";
  306. // reg = <0x0 0x100 0x0 0x0>;
  307. //
  308. // key0 {
  309. // label = "key0";
  310. // gpios = <&gpio1_porta 7 1>; /* GPIO_ACTIVE_LOW: 1 */
  311. // linux,code = <59>; /* KEY_F1: 59 */
  312. // status = "okay";
  313. // };
  314. // };
  315. //
  316. // leds: gpio-leds@200 {
  317. // compatible = "gpio-leds";
  318. // reg = <0x0 0x200 0x0 0x0>;
  319. //
  320. // led0 {
  321. // label = "led0";
  322. // gpios = <&gpio1_porta 8 0>; /* GPIO_ACTIVE_HIGH: 0 */
  323. // default-state = "off";
  324. // };
  325. // };
  326. uart0: serial@ffe7014000 { /* Normal serial, for C910 log */
  327. compatible = "snps,dw-apb-uart";
  328. reg = <0xff 0xe7014000 0x0 0x4000>;
  329. interrupt-parent = <&intc>;
  330. interrupts = <36>;
  331. clocks = <&dummy_clock_apb>;
  332. clock-names = "baudclk";
  333. reg-shift = <2>;
  334. reg-io-width = <4>;
  335. hw-flow-control = "unsupport";
  336. status = "okay";
  337. };
  338. uart1: serial@ffe7f00000 { /* Normal serial, for C902 log */
  339. compatible = "snps,dw-apb-uart";
  340. reg = <0xff 0xe7f00000 0x0 0x4000>;
  341. interrupt-parent = <&intc>;
  342. interrupts = <37>;
  343. clocks = <&dummy_clock_apb>;
  344. clock-names = "baudclk";
  345. reg-shift = <2>;
  346. reg-io-width = <4>;
  347. hw-flow-control = "unsupport";
  348. status = "okay";
  349. };
  350. uart2: serial@ffec010000 { /* IRDA supported serial, not in 85P bit */
  351. compatible = "snps,dw-apb-uart";
  352. reg = <0xff 0xec010000 0x0 0x4000>;
  353. interrupt-parent = <&intc>;
  354. interrupts = <38>;
  355. clocks = <&dummy_clock_apb>;
  356. clock-names = "baudclk";
  357. reg-shift = <2>;
  358. reg-io-width = <4>;
  359. hw-flow-control = "unsupport";
  360. status = "disabled";
  361. };
  362. uart3: serial@ffe7f04000 { /* IRDA supported serial, not in 85P bit */
  363. compatible = "snps,dw-apb-uart";
  364. reg = <0xff 0xe7f04000 0x0 0x4000>;
  365. interrupt-parent = <&intc>;
  366. interrupts = <39>;
  367. clocks = <&dummy_clock_apb>;
  368. clock-names = "baudclk";
  369. reg-shift = <2>;
  370. reg-io-width = <4>;
  371. hw-flow-control = "unsupport";
  372. status = "disabled";
  373. };
  374. uart4: serial@fff7f08000 { /* High Speed with Flow Ctrol serial */
  375. compatible = "snps,dw-apb-uart";
  376. reg = <0xff 0xf7f08000 0x0 0x4000>;
  377. interrupt-parent = <&intc>;
  378. interrupts = <40>;
  379. clocks = <&dummy_clock_apb>;
  380. clock-names = "baudclk";
  381. reg-shift = <2>;
  382. reg-io-width = <4>;
  383. hw-flow-control = "support";
  384. status = "okay";
  385. };
  386. uart5: serial@fff7f0c000 { /* Normal serial, for external SE, not in 85P bit */
  387. compatible = "snps,dw-apb-uart";
  388. reg = <0xff 0xf7f0c000 0x0 0x4000>;
  389. interrupt-parent = <&intc>;
  390. interrupts = <41>;
  391. clocks = <&dummy_clock_apb>;
  392. clock-names = "baudclk";
  393. reg-shift = <2>;
  394. reg-io-width = <4>;
  395. hw-flow-control = "unsupport";
  396. status = "disabled";
  397. };
  398. i2c0: i2c@ffe7f20000 {
  399. compatible = "snps,designware-i2c";
  400. reg = <0xff 0xe7f20000 0x0 0x4000>;
  401. interrupt-parent = <&intc>;
  402. interrupts = <44>;
  403. clocks = <&dummy_clock_apb>;
  404. clock-frequency = <100000>;
  405. #address-cells = <1>;
  406. #size-cells = <0>;
  407. eeprom@50 {
  408. compatible = "atmel,24c32";
  409. reg = <0x50>;
  410. pagesize = <32>;
  411. };
  412. };
  413. i2c2: i2c@ffec00c000{
  414. compatible = "snps,designware-i2c";
  415. reg = <0xff 0xec00c000 0x0 0x4000>;
  416. interrupt-parent = <&intc>;
  417. interrupts = <46>;
  418. clocks = <&dummy_clock_apb>;
  419. clock-frequency = <100000>;
  420. #address-cells = <1>;
  421. #size-cells = <0>;
  422. //status = "disabled";
  423. };
  424. i2c3: i2c@123321{
  425. compatible = "snps,designware-i2c";
  426. reg = <0xff 0xec014000 0x0 0x4000>;
  427. //reg = <0xff 0xec00c000 0x0 0x4000>;
  428. interrupt-parent = <&intc>;
  429. //interrupts = <46>;
  430. clocks = <&dummy_clock_apb>;
  431. clock-frequency = <100000>;
  432. #address-cells = <1>;
  433. #size-cells = <0>;
  434. ov2775_0: ov2775_mipi@20 {
  435. compatible = "ovti,ov2775";
  436. //reg = <0x20>;
  437. reg = <0x10>;
  438. pinctrl-names = "default";
  439. clocks = <&dummy_clock_apb>;
  440. clock-names = "csi_mclk";
  441. //assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
  442. //assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
  443. assigned-clock-rates = <24000000>;
  444. csi_id = <0>;
  445. //pwn-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
  446. //rst-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
  447. mclk = <24000000>;
  448. mclk_source = <0>;
  449. status = "okay";
  450. port {
  451. ov2775_mipi_0_ep: endpoint {
  452. data-lanes = <1 2 3 4>;
  453. clock-lanes = <0>;
  454. max-pixel-frequency = /bits/ 64 <266000000>;
  455. //remote-endpoint = <&mipi_csi0_ep>;
  456. };
  457. };
  458. };
  459. };
  460. spi0: spi@ffe700c000 {
  461. compatible = "snps,dw-apb-ssi";
  462. reg = <0xff 0xe700c000 0x0 0x1000>;
  463. interrupt-parent = <&intc>;
  464. interrupts = <54>;
  465. clocks = <&dummy_clock_apb>;
  466. num-cs = <2>;
  467. cs-gpios = <&gpio2_porta 15 0>, // GPIO_ACTIVE_HIGH: 0
  468. <&gpio2_porta 23 0>; // GPIO_ACTIVE_LOW: 1
  469. #address-cells = <1>;
  470. #size-cells = <0>;
  471. spi_norflash@0 {
  472. #address-cells = <1>;
  473. #size-cells = <1>;
  474. compatible = "winbond,w25q64", "jedec,spi-nor";
  475. reg = <0>;
  476. spi-max-frequency = <8000000>;
  477. w25q,fast-read;
  478. };
  479. spidev@1 {
  480. compatible = "spidev";
  481. #address-cells = <1>;
  482. #size-cells = <1>;
  483. reg = <1>;
  484. spi-max-frequency = <12500000>;
  485. };
  486. };
  487. qspi0: spi@ffea000000 {
  488. compatible = "snps,dw-apb-ssi-quad";
  489. reg = <0xff 0xea000000 0x0 0x1000>;
  490. interrupt-parent = <&intc>;
  491. interrupts = <52>;
  492. clocks = <&dummy_clock_apb>;
  493. num-cs = <2>;
  494. cs-gpios = <&gpio2_porta 3 0>, // GPIO_ACTIVE_HIGH: 0
  495. <&gpio2_porta 26 0>;
  496. status = "disabled";
  497. #address-cells = <1>;
  498. #size-cells = <0>;
  499. spi-flash@0 {
  500. #address-cells = <1>;
  501. #size-cells = <1>;
  502. compatible = "spi-nand";
  503. spi-max-frequency = <10000000>;
  504. spi-tx-bus-width = <4>;
  505. spi-rx-bus-width = <4>;
  506. reg = <0>;
  507. partition@0 {
  508. label = "ubi1";
  509. reg = <0x00000000 0x08000000>;
  510. };
  511. };
  512. spidev@1 {
  513. compatible = "spidev";
  514. #address-cells = <1>;
  515. #size-cells = <1>;
  516. reg = <1>;
  517. spi-max-frequency = <6250000>;
  518. };
  519. };
  520. watchdog0: watchdog@ffefc30000 {
  521. compatible = "snps,dw-wdt";
  522. reg = <0xff 0xefc30000 0x0 0x1000>;
  523. interrupt-parent = <&intc>;
  524. interrupts = <24>;
  525. clocks = <&dummy_clock_apb>;
  526. clock-names = "baudclk";
  527. status = "okay";
  528. };
  529. watchdog1: watchdog@ffefc31000 {
  530. compatible = "snps,dw-wdt";
  531. reg = <0xff 0xefc31000 0x0 0x1000>;
  532. interrupt-parent = <&intc>;
  533. interrupts = <25>;
  534. clocks = <&dummy_clock_apb>;
  535. clock-names = "baudclk";
  536. status = "okay";
  537. };
  538. rtc: rtc@fffff40000 {
  539. compatible = "apm,xgene-rtc";
  540. reg = <0xff 0xfff40000 0x0 0x1000>;
  541. interrupt-parent = <&intc>;
  542. interrupts = <74>;
  543. clocks = <&dummy_clock_rtc>;
  544. clock-names = "rtc";
  545. status = "okay";
  546. };
  547. usb: dwc3@ffe7040000 {
  548. compatible = "snps,dwc3";
  549. reg = <0xff 0xe7040000 0x0 0x10000>;
  550. interrupt-parent = <&intc>;
  551. interrupts = <68>;
  552. clocks = <&dummy_clock_ref>, <&dummy_clock_apb>, <&dummy_clock_suspend>;
  553. clock-names = "ref", "bus_early", "suspend";
  554. reg-shift = <2>;
  555. reg-io-width = <4>;
  556. maximum-speed = "super-speed";
  557. dr_mode = "peripheral";
  558. snps,usb3_lpm_capable;
  559. snps,dis_u3_susphy_quirk;
  560. status = "disabled";
  561. };
  562. pmu: pmu@0 {
  563. compatible = "riscv,c910_pmu";
  564. reg = <0 0 0 0>; /* Not address, just for index */
  565. };
  566. dmac0: dmac@ffefc00000 {
  567. compatible = "snps,axi-dma-1.01a";
  568. reg = <0xff 0xefc00000 0x0 0x1000>;
  569. interrupt-parent = <&intc>;
  570. interrupts = <27>;
  571. clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
  572. clock-names = "core-clk", "cfgr-clk";
  573. dma-channels = <4>;
  574. snps,block-size = <65536 65536 65536 65536>;
  575. snps,priority = <0 1 2 3>;
  576. snps,dma-masters = <1>;
  577. snps,data-width = <4>;
  578. snps,axi-max-burst-len = <16>;
  579. status = "disabled";
  580. };
  581. dmac1: tee_dmac@ffff340000 {
  582. compatible = "snps,axi-dma-1.01a";
  583. reg = <0xff 0xff340000 0x0 0x1000>;
  584. interrupt-parent = <&intc>;
  585. interrupts = <150>;
  586. clocks = <&dummy_clock_apb>, <&dummy_clock_apb>;
  587. clock-names = "core-clk", "cfgr-clk";
  588. dma-channels = <4>;
  589. snps,block-size = <65536 65536 65536 65536>;
  590. snps,priority = <0 1 2 3>;
  591. snps,dma-masters = <1>;
  592. snps,data-width = <4>;
  593. snps,axi-max-burst-len = <16>;
  594. status = "disabled";
  595. };
  596. gmac: ethernet@ffe7070000 {
  597. compatible = "snps,dwmac";
  598. reg = <0xff 0xe7070000 0x0 0x2000>;
  599. interrupt-parent = <&intc>;
  600. interrupts = <66>;
  601. interrupt-names = "macirq";
  602. clocks = <&dummy_clock_apb>;
  603. clock-names = "stmmaceth";
  604. snps,pbl = <32>;
  605. snps,fixed-burst;
  606. max-speed = <100>;
  607. phy-mode = "mii";
  608. phy-handle = <&phy_88E1111>;
  609. mdio0 {
  610. #address-cells = <1>;
  611. #size-cells = <0>;
  612. compatible = "snps,dwmac-mdio";
  613. phy_88E1111: ethernet-phy@0 {
  614. reg = <0x0 0x0>;
  615. };
  616. };
  617. };
  618. emmc: sdhci@ffe7080000 {
  619. compatible = "snps,dwcmshc-sdhci";
  620. reg = <0xff 0xe7080000 0x0 0x10000>;
  621. interrupt-parent = <&intc>;
  622. interrupts = <62>;
  623. interrupt-names = "sdhciirq";
  624. clocks = <&dummy_clock_ahb>;
  625. clock-names = "core";
  626. max-frequency = <50000000>;
  627. non-removable;
  628. no-sdio;
  629. no-sd;
  630. bus-width = <8>;
  631. status = "disabled";
  632. };
  633. sdhci0: sd@ffe7090000 {
  634. compatible = "snps,dwcmshc-sdhci";
  635. reg = <0xff 0xe7090000 0x0 0x10000>;
  636. interrupt-parent = <&intc>;
  637. interrupts = <64>;
  638. interrupt-names = "sdhci0irq";
  639. clocks = <&dummy_clock_ahb>;
  640. clock-names = "core";
  641. max-frequency = <50000000>;
  642. no-1-8-v;
  643. bus-width = <4>;
  644. status = "disabled";
  645. };
  646. hwspinlock: hwspinlock@ffefc10000 {
  647. compatible = "light,hwspinlock";
  648. reg = <0xff 0xefc10000 0x0 0x10000>;
  649. };
  650. npu: vha@fffc800000 {
  651. compatible = "img,ax3386-nna";
  652. reg = <0xff 0xfc800000 0x0 0x100000>;
  653. interrupt-parent = <&intc>;
  654. interrupts = <113>;
  655. interrupt-names = "npuirq";
  656. clocks = <&dummy_clock_npu>;
  657. clock-names = "dummy_clock_npu";
  658. vha_clk_rate = <24000000>;
  659. ldo_vha-supply = <&npu>;
  660. dma-mask = <0xf 0xffffffff>;
  661. status = "disabled";
  662. };
  663. vdec: vdec@ffecc00000 {
  664. compatible = "platform-vc8000d";
  665. reg = <0xff 0xecc00000 0x0 0x1000>;
  666. interrupt-parent = <&intc>;
  667. interrupts = <131>;
  668. status = "disabled";
  669. };
  670. venc: venc@ffecc10000 {
  671. compatible = "platform-vc8000e";
  672. reg = <0xff 0xecc10000 0x0 0x1000>;
  673. interrupt-parent = <&intc>;
  674. interrupts = <133>;
  675. status = "disabled";
  676. };
  677. // from https://github.com/iwave-git-imx8mm-8mn/kernel_iwg34m/blob/62c0186302d2c4754e06722b3c38f6c4557b91f4/arch/arm64/boot/dts/freescale/imx8mp.dtsi
  678. aliases {
  679. csi0 = &v4l2_mipi_csi_0;
  680. };
  681. v4l2_mipi_csi_0: mipi_csi@ff000000 {
  682. compatible = "thead,light-mipi-csi";
  683. //reg = < 0xff 0xe4000000 0x0 0x10000>;
  684. reg = < 0x00 0xff000000 0x0 0x10000>;
  685. interrupt-parent = <&intc>;
  686. interrupts = <199>;
  687. clock-frequency = <24000000>;
  688. bus-width = <4>;
  689. no-reset-control;
  690. status = "okay";
  691. port@0 {
  692. endpoint {
  693. remote-endpoint = <&ov2775_mipi_0_ep>;
  694. data-lanes = <4>;
  695. csis-hs-settle = <16>;
  696. };
  697. };
  698. };
  699. v4l2_isp_0: v4l2_isp@ffe4100000 {
  700. compatible = "fsl,imx8mp-isp";
  701. reg = <0xff 0xe4100000 0x0 0x10000>;
  702. interrupt-parent = <&intc>;
  703. interrupts = <117>;
  704. memory-region = <&isp_reserved>;
  705. clock-names = "core", "axi", "ahb";
  706. //clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>;
  707. //clock-names = "isp_root";
  708. //assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP_SRC>;
  709. //assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
  710. //assigned-clock-rates = <500000000>;
  711. //power-domains = <&ispdwp_pd>;
  712. id = <0>;
  713. status = "okay";
  714. };
  715. v4l2_dewarp: dwe@ffe4130000 {
  716. compatible = "fsl,imx8mp-dwe";
  717. reg = <0xff 0xe4130000 0x0 0x10000>;
  718. interrupt-parent = <&intc>;
  719. interrupts = <98>;
  720. //clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
  721. // <&clk IMX8MP_CLK_MEDIA_AXI>,
  722. // <&clk IMX8MP_CLK_MEDIA_APB>;
  723. clock-names = "core", "axi", "ahb";
  724. //assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
  725. // <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
  726. //assigned-clock-rates = <500000000>, <200000000>;
  727. //power-domains = <&ispdwp_pd>;
  728. id = <0>;
  729. status = "okay";
  730. };
  731. isp0: isp@ffe4100000 {
  732. compatible = "thead,light-isp";
  733. reg = <0xff 0xe4100000 0x0 0x10000>;
  734. interrupt-parent = <&intc>;
  735. interrupts = <117>,<118>;
  736. status = "okay";
  737. };
  738. isp1: isp@ffe4110000 {
  739. compatible = "thead,light-isp";
  740. reg = <0xff 0xe4110000 0x0 0x10000>;
  741. interrupt-parent = <&intc>;
  742. interrupts = <120>,<121>;
  743. status = "okay";
  744. };
  745. isp_ry0: isp_ry@ffe4120000 {
  746. compatible = "thead,light-isp_ry";
  747. reg = <0xff 0xe4120000 0x0 0x10000>;
  748. interrupt-parent = <&intc>;
  749. interrupts = <123>,<124>;
  750. status = "okay";
  751. };
  752. dewarp: dewarp@ffe4130000 {
  753. compatible = "thead,light-dewarp";
  754. reg = <0xff 0xe4130000 0x0 0x10000>;
  755. interrupt-parent = <&intc>;
  756. interrupts = <98>,<99>;
  757. status = "okay";
  758. };
  759. dec400_isp0: dec400@ffe4060000 {
  760. compatible = "thead,dec400";
  761. reg = <0xff 0xe4060000 0x0 0x8000>;
  762. status = "okay";
  763. };
  764. dec400_isp1: dec400@ffe4068000 {
  765. compatible = "thead,dec400";
  766. reg = <0xff 0xe4068000 0x0 0x8000>;
  767. status = "okay";
  768. };
  769. //isp-ry
  770. dec400_isp2: dec400@ffe4070000 {
  771. compatible = "thead,dec400";
  772. reg = <0xff 0xe4070000 0x0 0x8000>;
  773. status = "okay";
  774. };
  775. bm_visys: bm_visys@ffe4040000 {
  776. compatible = "thead,light-bm-visys";
  777. reg = <0xff 0xe4040000 0x0 0x10000>;
  778. status = "okay";
  779. };
  780. bm_csi0: csi@ffe4000000{
  781. compatible = "thead,light-bm-csi";
  782. reg = < 0xff 0xe4000000 0x0 0x10000>;
  783. interrupt-parent = <&intc>;
  784. interrupts = <128>;
  785. dphyglueiftester = <0x180>;
  786. status = "okay";
  787. //status = "disabled";
  788. };
  789. bm_csi1: csi@ffe4020000{
  790. compatible = "thead,light-bm-csi";
  791. reg = < 0xff 0xe4020000 0x0 0x10000>;
  792. interrupt-parent = <&intc>;
  793. interrupts = <127>;
  794. dphyglueiftester = <0x184>;
  795. status = "okay";
  796. //status = "disabled";
  797. };
  798. bm_isp0: bm_isp@ffe4100000 {
  799. compatible = "thead,light-bm-isp";
  800. reg = <0xff 0xe4100000 0x0 0x10000>;
  801. status = "okay";
  802. };
  803. bm_isp1: bm_isp@ffe4110000 {
  804. compatible = "thead,light-bm-isp";
  805. reg = <0xff 0xe4110000 0x0 0x10000>;
  806. //status = "okay";
  807. status = "disabled";
  808. };
  809. //isp-ry
  810. bm_isp2: bm_isp@ffe4120000 {
  811. compatible = "thead,light-bm-isp";
  812. reg = <0xff 0xe4120000 0x0 0x10000>;
  813. //status = "okay";
  814. status = "disabled";
  815. };
  816. vi_pre: vi_pre@ffe4030000 {
  817. compatible = "thead,vi_pre";
  818. reg = <0xff 0xe4030000 0x0 0x1000>;
  819. status = "okay";
  820. };
  821. xtensa_dsp: dsp@01{
  822. compatible = "thead,dsp-hw-common";
  823. reg = <0xff 0xef040000 0x0 0x001000 >; /*DSP_SYSREG(0x0000-0xFFF) */
  824. };
  825. xtensa_dsp0: dsp@0 {
  826. compatible = "cdns,xrp-hw-simple";
  827. reg = <0xff 0xe4040190 0x0 0x000010 /* host irq DSP->CPU INT Register */
  828. 0xff 0xe40401e0 0x0 0x000010 /* device irq CPU->DSP INT Register */
  829. 0xff 0xef048000 0x0 0x008000 /*DSP_APB(0x0000-0xFFF) */
  830. 0x00 0x90000000 0x0 0x00001000 /* DSP communication area */
  831. 0x0 0x90001000 0x0 0x00fff000>; /* DSP shared memory */
  832. dsp = <0>;
  833. dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/
  834. dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/
  835. device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */
  836. device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/
  837. device-irq-mode = <1>; /*level trigger*/
  838. host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */
  839. host-irq-mode = <1>; /*level trigger */
  840. host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/
  841. interrupt-parent = <&intc>;
  842. interrupts = <156>;
  843. firmware-name = "xrp0.elf";
  844. ranges = <0x00 0x70000000 0x00 0x70000000 0x00 0x40000000
  845. 0x00 0xfa000000 0xff 0xe0000000 0x00 0x00180000
  846. 0x00 0xe0180000 0xff 0xe0180000 0x00 0x00040000
  847. 0x00 0xffc00000 0xff 0xe4000000 0x00 0x00200000 >; /* VISYS_R */
  848. dsp@0 {
  849. ranges = <0x00 0x70000000 0x00 0x70000000 0x00 0x40000000
  850. 0x00 0xfa000000 0xff 0xe0000000 0x00 0x00180000
  851. 0x00 0xe0180000 0xff 0xe0180000 0x00 0x00040000
  852. 0x00 0xffc00000 0xff 0xe4000000 0x00 0x00200000 >; /* VISYS_R */
  853. };
  854. };
  855. xtensa_dsp1: dsp@1 {
  856. compatible = "cdns,xrp-hw-simple";
  857. reg = <0xff 0xe40401a0 0x0 0x000010 /* host irq DSP->CPU INT Register */
  858. 0xff 0xe40401d0 0x0 0x000010 /* device irq CPU->DSP INT Register */
  859. 0xff 0xef050000 0x0 0x008000 /*DSP_APB(0x0000-0xFFF) */
  860. 0x00 0xa0000000 0x0 0x00001000 /* DSP communication area */
  861. 0x0 0xa0001000 0x0 0x00fff000>; /* DSP shared memory */
  862. dsp = <1>;
  863. dspsys-rst-bit = <8>; /*bit# in DSP_SYSREG*/
  864. dspsys-bus-offset = <0x90>; /*in DSP_SYSREG*/
  865. device-irq = <0x4 1 24>; /*0xff 0xe40401e4 offset to clear DSP I]RQ, bit#, IRQ# */
  866. device-irq-host-offset = <0x8>; /*0xff 0xe40401e8 offset to trigger DSP IRQ*/
  867. device-irq-mode = <1>; /*level trigger*/
  868. host-irq = <0x4 1>; /*0xff 0xe4040194 offset to clear, bit# */
  869. host-irq-mode = <1>; /*level trigger */
  870. host-irq-offset = <0x8>; /* 0xff 0xe4040198 offset to trigger ,device side*/
  871. interrupt-parent = <&intc>;
  872. interrupts = <157>;
  873. firmware-name = "xrp1.elf";
  874. status = "disabled";
  875. ranges = <0x00 0x70000000 0x00 0x70000000 0x00 0x40000000
  876. 0x00 0xfa000000 0xff 0xe0000000 0x00 0x00180000
  877. 0x00 0xe0180000 0xff 0xe01C0000 0x00 0x00040000
  878. 0x00 0xffc00000 0xff 0xe4000000 0x00 0x00200000 >; /* VISYS_R */
  879. dsp@0 {
  880. ranges = <0x00 0x70000000 0x00 0x70000000 0x00 0x40000000
  881. 0x00 0xfa000000 0xff 0xe0000000 0x00 0x00180000
  882. 0x00 0xe0180000 0xff 0xe01C0000 0x00 0x00040000
  883. 0x00 0xffc00000 0xff 0xe4000000 0x00 0x00200000 >; /* VISYS_R */
  884. };
  885. };
  886. pmp: pmp@ffdc020000 {
  887. compatible = "pmp";
  888. reg = <0xff 0xdc020000 0x0 0x1000>;
  889. };
  890. mrvbr: mrvbr@ffff019050{
  891. compatible = "mrvbr";
  892. reg = <0xff 0xff019050 0x0 0x1000>;
  893. };
  894. mrmr: mrmr@ffff015004 {
  895. compatible = "mrmr";
  896. reg = <0xff 0xff015004 0x0 0x1000>;
  897. };
  898. };
  899. chosen {
  900. bootargs = "console=ttyS0,115200 crashkernel=256M-:128M sram=0xffe0000000,0x180000";
  901. linux,initrd-start = <0x0 0x2000000>;
  902. linux,initrd-end = <0x0 0x0>;
  903. //bootargs = "console=ttyS0,115200 crashkernel=256M-:128M sram=0xffe0000000,0x180000 rdinit=/sbin/init root=/dev/nfs rw nfsroot=172.16.150.200:/home/share.dir/nfs/lucz/nfs_root,v3,tcp,nolock ip=172.16.150.233::172.16.150.254:255.255.255.0 rootwait";
  904. //bootargs = "console=ttyS0,115200 crashkernel=256M-:128M sram=0xffe0000000,0x180000 rdinit=/sbin/init root=/dev/nfs rw nfsroot=172.16.150.200:/home/share.dir/nfs/lucz/nfs_root,v3,tcp,nolock ip=172.18.80.233::172.18.80.254:255.255.255.0 rootwait";
  905. stdout-path = "/soc/serial@fff7014000:115200";
  906. };
  907. };