vc8000_vcmd_driver.c 166 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2014 - 2021 VERISILICON
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (C) 2014 - 2021 VERISILICON
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program; if not, write to the Free Software Foundation,
  43. * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  44. *
  45. *****************************************************************************
  46. *
  47. * Note: This software is released under dual MIT and GPL licenses. A
  48. * recipient may use this file under the terms of either the MIT license or
  49. * GPL License. If you wish to use only one license not the other, you can
  50. * indicate your decision by deleting one of the above license notices in your
  51. * version of this file.
  52. *
  53. *****************************************************************************/
  54. #include <linux/kernel.h>
  55. #include <linux/module.h>
  56. /* needed for __init,__exit directives */
  57. #include <linux/init.h>
  58. /* needed for remap_page_range
  59. SetPageReserved
  60. ClearPageReserved
  61. */
  62. #include <linux/mm.h>
  63. /* obviously, for kmalloc */
  64. #include <linux/slab.h>
  65. /* for struct file_operations, register_chrdev() */
  66. #include <linux/fs.h>
  67. /* standard error codes */
  68. #include <linux/errno.h>
  69. #include <linux/ioctl.h>
  70. #include <linux/kernel.h>
  71. #include <linux/module.h>
  72. #include <linux/cdev.h>
  73. #include <linux/moduleparam.h>
  74. /* request_irq(), free_irq() */
  75. #include <linux/interrupt.h>
  76. #include <linux/sched.h>
  77. #include <linux/semaphore.h>
  78. #include <linux/spinlock.h>
  79. /* needed for virt_to_phys() */
  80. #include <asm/io.h>
  81. #include <linux/pci.h>
  82. #include <linux/uaccess.h>
  83. #include <linux/ioport.h>
  84. #include <asm/irq.h>
  85. #include <linux/version.h>
  86. #include <linux/vmalloc.h>
  87. #include <linux/timer.h>
  88. #include <linux/delay.h>
  89. #include <linux/clk.h>
  90. #include <linux/pm_runtime.h>
  91. #include <linux/debugfs.h>
  92. /* our own stuff */
  93. #include <linux/platform_device.h>
  94. #include <linux/of.h>
  95. #include "vcmdswhwregisters.h"
  96. #include "bidirect_list.h"
  97. #include "vc8000_driver.h"
  98. /*------------------------------------------------------------------------
  99. *****************************VCMD CONFIGURATION BY CUSTOMER********************************
  100. -------------------------------------------------------------------------*/
  101. //video encoder vcmd configuration
  102. #define VCMD_ENC_IO_ADDR_0 0x90000 /*customer specify according to own platform*/
  103. #define VCMD_ENC_IO_SIZE_0 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  104. #define VCMD_ENC_INT_PIN_0 -1
  105. #define VCMD_ENC_MODULE_TYPE_0 0
  106. #define VCMD_ENC_MODULE_MAIN_ADDR_0 0x1000 /*customer specify according to own platform*/
  107. #define VCMD_ENC_MODULE_DEC400_ADDR_0 0X2000 //0X6000 /*0xffff means no such kind of submodule*/
  108. #define VCMD_ENC_MODULE_L2CACHE_ADDR_0 0XFFFF
  109. #define VCMD_ENC_MODULE_MMU0_ADDR_0 0X4000 //0X2000
  110. #define VCMD_ENC_MODULE_MMU1_ADDR_0 0XFFFF //0X4000
  111. #define VCMD_ENC_MODULE_AXIFE0_ADDR_0 0XFFFF //0X3000
  112. #define VCMD_ENC_MODULE_AXIFE1_ADDR_0 0XFFFF //0X5000
  113. #define VCMD_ENC_IO_ADDR_1 0x91000 /*customer specify according to own platform*/
  114. #define VCMD_ENC_IO_SIZE_1 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  115. #define VCMD_ENC_INT_PIN_1 -1
  116. #define VCMD_ENC_MODULE_TYPE_1 0
  117. #define VCMD_ENC_MODULE_MAIN_ADDR_1 0x0000 /*customer specify according to own platform*/
  118. #define VCMD_ENC_MODULE_DEC400_ADDR_1 0XFFFF /*0xffff means no such kind of submodule*/
  119. #define VCMD_ENC_MODULE_L2CACHE_ADDR_1 0XFFFF
  120. #define VCMD_ENC_MODULE_MMU_ADDR_1 0XFFFF
  121. #define VCMD_ENC_IO_ADDR_2 0x92000 /*customer specify according to own platform*/
  122. #define VCMD_ENC_IO_SIZE_2 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  123. #define VCMD_ENC_INT_PIN_2 -1
  124. #define VCMD_ENC_MODULE_TYPE_2 0
  125. #define VCMD_ENC_MODULE_MAIN_ADDR_2 0x0000 /*customer specify according to own platform*/
  126. #define VCMD_ENC_MODULE_DEC400_ADDR_2 0XFFFF /*0xffff means no such kind of submodule*/
  127. #define VCMD_ENC_MODULE_L2CACHE_ADDR_2 0XFFFF
  128. #define VCMD_ENC_MODULE_MMU_ADDR_2 0XFFFF
  129. #define VCMD_ENC_IO_ADDR_3 0x93000 /*customer specify according to own platform*/
  130. #define VCMD_ENC_IO_SIZE_3 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  131. #define VCMD_ENC_INT_PIN_3 -1
  132. #define VCMD_ENC_MODULE_TYPE_3 0
  133. #define VCMD_ENC_MODULE_MAIN_ADDR_3 0x0000 /*customer specify according to own platform*/
  134. #define VCMD_ENC_MODULE_DEC400_ADDR_3 0XFFFF /*0xffff means no such kind of submodule*/
  135. #define VCMD_ENC_MODULE_L2CACHE_ADDR_3 0XFFFF
  136. #define VCMD_ENC_MODULE_MMU_ADDR_3 0XFFFF
  137. //video encoder cutree/IM vcmd configuration
  138. #define VCMD_IM_IO_ADDR_0 0x94000 //0xA0000 /*customer specify according to own platform*/
  139. #define VCMD_IM_IO_SIZE_0 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  140. #define VCMD_IM_INT_PIN_0 -1
  141. #define VCMD_IM_MODULE_TYPE_0 1
  142. #define VCMD_IM_MODULE_MAIN_ADDR_0 0x1000 /*customer specify according to own platform*/
  143. #define VCMD_IM_MODULE_DEC400_ADDR_0 0XFFFF /*0xffff means no such kind of submodule*/
  144. #define VCMD_IM_MODULE_L2CACHE_ADDR_0 0XFFFF
  145. #define VCMD_IM_MODULE_MMU0_ADDR_0 0XFFFF //0X2000
  146. #define VCMD_IM_MODULE_MMU1_ADDR_0 0XFFFF
  147. #define VCMD_IM_MODULE_AXIFE0_ADDR_0 0XFFFF //0X3000
  148. #define VCMD_IM_MODULE_AXIFE1_ADDR_0 0XFFFF //0XFFFF
  149. #define VCMD_IM_IO_ADDR_1 0xa1000 /*customer specify according to own platform*/
  150. #define VCMD_IM_IO_SIZE_1 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  151. #define VCMD_IM_INT_PIN_1 -1
  152. #define VCMD_IM_MODULE_TYPE_1 1
  153. #define VCMD_IM_MODULE_MAIN_ADDR_1 0x0000 /*customer specify according to own platform*/
  154. #define VCMD_IM_MODULE_DEC400_ADDR_1 0XFFFF /*0xffff means no such kind of submodule*/
  155. #define VCMD_IM_MODULE_L2CACHE_ADDR_1 0XFFFF
  156. #define VCMD_IM_MODULE_MMU_ADDR_1 0XFFFF
  157. #define VCMD_IM_IO_ADDR_2 0xa2000 /*customer specify according to own platform*/
  158. #define VCMD_IM_IO_SIZE_2 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  159. #define VCMD_IM_INT_PIN_2 -1
  160. #define VCMD_IM_MODULE_TYPE_2 1
  161. #define VCMD_IM_MODULE_MAIN_ADDR_2 0x0000 /*customer specify according to own platform*/
  162. #define VCMD_IM_MODULE_DEC400_ADDR_2 0XFFFF /*0xffff means no such kind of submodule*/
  163. #define VCMD_IM_MODULE_L2CACHE_ADDR_2 0XFFFF
  164. #define VCMD_IM_MODULE_MMU_ADDR_2 0XFFFF
  165. #define VCMD_IM_IO_ADDR_3 0xa3000 /*customer specify according to own platform*/
  166. #define VCMD_IM_IO_SIZE_3 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  167. #define VCMD_IM_INT_PIN_3 -1
  168. #define VCMD_IM_MODULE_TYPE_3 1
  169. #define VCMD_IM_MODULE_MAIN_ADDR_3 0x0000 /*customer specify according to own platform*/
  170. #define VCMD_IM_MODULE_DEC400_ADDR_3 0XFFFF /*0xffff means no such kind of submodule*/
  171. #define VCMD_IM_MODULE_L2CACHE_ADDR_3 0XFFFF
  172. #define VCMD_IM_MODULE_MMU_ADDR_3 0XFFFF
  173. //video decoder vcmd configuration
  174. #define VCMD_DEC_IO_ADDR_0 0xb0000 /*customer specify according to own platform*/
  175. #define VCMD_DEC_IO_SIZE_0 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  176. #define VCMD_DEC_INT_PIN_0 -1
  177. #define VCMD_DEC_MODULE_TYPE_0 2
  178. #define VCMD_DEC_MODULE_MAIN_ADDR_0 0x0000 /*customer specify according to own platform*/
  179. #define VCMD_DEC_MODULE_DEC400_ADDR_0 0XFFFF /*0xffff means no such kind of submodule*/
  180. #define VCMD_DEC_MODULE_L2CACHE_ADDR_0 0XFFFF
  181. #define VCMD_DEC_MODULE_MMU_ADDR_0 0XFFFF
  182. #define VCMD_DEC_IO_ADDR_1 0xb1000 /*customer specify according to own platform*/
  183. #define VCMD_DEC_IO_SIZE_1 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  184. #define VCMD_DEC_INT_PIN_1 -1
  185. #define VCMD_DEC_MODULE_TYPE_1 2
  186. #define VCMD_DEC_MODULE_MAIN_ADDR_1 0x0000 /*customer specify according to own platform*/
  187. #define VCMD_DEC_MODULE_DEC400_ADDR_1 0XFFFF /*0xffff means no such kind of submodule*/
  188. #define VCMD_DEC_MODULE_L2CACHE_ADDR_1 0XFFFF
  189. #define VCMD_DEC_MODULE_MMU_ADDR_1 0XFFFF
  190. #define VCMD_DEC_IO_ADDR_2 0xb2000 /*customer specify according to own platform*/
  191. #define VCMD_DEC_IO_SIZE_2 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  192. #define VCMD_DEC_INT_PIN_2 -1
  193. #define VCMD_DEC_MODULE_TYPE_2 2
  194. #define VCMD_DEC_MODULE_MAIN_ADDR_2 0x0000 /*customer specify according to own platform*/
  195. #define VCMD_DEC_MODULE_DEC400_ADDR_2 0XFFFF /*0xffff means no such kind of submodule*/
  196. #define VCMD_DEC_MODULE_L2CACHE_ADDR_2 0XFFFF
  197. #define VCMD_DEC_MODULE_MMU_ADDR_2 0XFFFF
  198. #define VCMD_DEC_IO_ADDR_3 0xb3000 /*customer specify according to own platform*/
  199. #define VCMD_DEC_IO_SIZE_3 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  200. #define VCMD_DEC_INT_PIN_3 -1
  201. #define VCMD_DEC_MODULE_TYPE_3 2
  202. #define VCMD_DEC_MODULE_MAIN_ADDR_3 0x0000 /*customer specify according to own platform*/
  203. #define VCMD_DEC_MODULE_DEC400_ADDR_3 0XFFFF /*0xffff means no such kind of submodule*/
  204. #define VCMD_DEC_MODULE_L2CACHE_ADDR_3 0XFFFF
  205. #define VCMD_DEC_MODULE_MMU_ADDR_3 0XFFFF
  206. //JPEG encoder vcmd configuration
  207. #define VCMD_JPEGE_IO_ADDR_0 0x90000 /*customer specify according to own platform*/
  208. #define VCMD_JPEGE_IO_SIZE_0 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  209. #define VCMD_JPEGE_INT_PIN_0 -1
  210. #define VCMD_JPEGE_MODULE_TYPE_0 3
  211. #define VCMD_JPEGE_MODULE_MAIN_ADDR_0 0x1000 /*customer specify according to own platform*/
  212. #define VCMD_JPEGE_MODULE_DEC400_ADDR_0 0XFFFF //0X4000 /*0xffff means no such kind of submodule*/
  213. #define VCMD_JPEGE_MODULE_L2CACHE_ADDR_0 0XFFFF
  214. #define VCMD_JPEGE_MODULE_MMU0_ADDR_0 0XFFFF //0X2000
  215. #define VCMD_JPEGE_MODULE_MMU1_ADDR_0 0XFFFF
  216. #define VCMD_JPEGE_MODULE_AXIFE0_ADDR_0 0XFFFF //0X3000
  217. #define VCMD_JPEGE_MODULE_AXIFE1_ADDR_0 0XFFFF
  218. #define VCMD_JPEGE_IO_ADDR_1 0xC1000 /*customer specify according to own platform*/
  219. #define VCMD_JPEGE_IO_SIZE_1 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  220. #define VCMD_JPEGE_INT_PIN_1 -1
  221. #define VCMD_JPEGE_MODULE_TYPE_1 3
  222. #define VCMD_JPEGE_MODULE_MAIN_ADDR_1 0x0000 /*customer specify according to own platform*/
  223. #define VCMD_JPEGE_MODULE_DEC400_ADDR_1 0XFFFF /*0xffff means no such kind of submodule*/
  224. #define VCMD_JPEGE_MODULE_L2CACHE_ADDR_1 0XFFFF
  225. #define VCMD_JPEGE_MODULE_MMU_ADDR_1 0XFFFF
  226. #define VCMD_JPEGE_IO_ADDR_2 0xC2000 /*customer specify according to own platform*/
  227. #define VCMD_JPEGE_IO_SIZE_2 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  228. #define VCMD_JPEGE_INT_PIN_2 -1
  229. #define VCMD_JPEGE_MODULE_TYPE_2 3
  230. #define VCMD_JPEGE_MODULE_MAIN_ADDR_2 0x0000 /*customer specify according to own platform*/
  231. #define VCMD_JPEGE_MODULE_DEC400_ADDR_2 0XFFFF /*0xffff means no such kind of submodule*/
  232. #define VCMD_JPEGE_MODULE_L2CACHE_ADDR_2 0XFFFF
  233. #define VCMD_JPEGE_MODULE_MMU_ADDR_2 0XFFFF
  234. #define VCMD_JPEGE_IO_ADDR_3 0xC3000 /*customer specify according to own platform*/
  235. #define VCMD_JPEGE_IO_SIZE_3 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  236. #define VCMD_JPEGE_INT_PIN_3 -1
  237. #define VCMD_JPEGE_MODULE_TYPE_3 3
  238. #define VCMD_JPEGE_MODULE_MAIN_ADDR_3 0x0000 /*customer specify according to own platform*/
  239. #define VCMD_JPEGE_MODULE_DEC400_ADDR_3 0XFFFF /*0xffff means no such kind of submodule*/
  240. #define VCMD_JPEGE_MODULE_L2CACHE_ADDR_3 0XFFFF
  241. #define VCMD_JPEGE_MODULE_MMU_ADDR_3 0XFFFF
  242. //JPEG decoder vcmd configuration
  243. #define VCMD_JPEGD_IO_ADDR_0 0xD0000 /*customer specify according to own platform*/
  244. #define VCMD_JPEGD_IO_SIZE_0 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  245. #define VCMD_JPEGD_INT_PIN_0 -1
  246. #define VCMD_JPEGD_MODULE_TYPE_0 4
  247. #define VCMD_JPEGD_MODULE_MAIN_ADDR_0 0x0000 /*customer specify according to own platform*/
  248. #define VCMD_JPEGD_MODULE_DEC400_ADDR_0 0XFFFF /*0xffff means no such kind of submodule*/
  249. #define VCMD_JPEGD_MODULE_L2CACHE_ADDR_0 0XFFFF
  250. #define VCMD_JPEGD_MODULE_MMU_ADDR_0 0XFFFF
  251. #define VCMD_JPEGD_IO_ADDR_1 0xD1000 /*customer specify according to own platform*/
  252. #define VCMD_JPEGD_IO_SIZE_1 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  253. #define VCMD_JPEGD_INT_PIN_1 -1
  254. #define VCMD_JPEGD_MODULE_TYPE_1 4
  255. #define VCMD_JPEGD_MODULE_MAIN_ADDR_1 0x0000 /*customer specify according to own platform*/
  256. #define VCMD_JPEGD_MODULE_DEC400_ADDR_1 0XFFFF /*0xffff means no such kind of submodule*/
  257. #define VCMD_JPEGD_MODULE_L2CACHE_ADDR_1 0XFFFF
  258. #define VCMD_JPEGD_MODULE_MMU_ADDR_1 0XFFFF
  259. #define VCMD_JPEGD_IO_ADDR_2 0xD2000 /*customer specify according to own platform*/
  260. #define VCMD_JPEGD_IO_SIZE_2 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  261. #define VCMD_JPEGD_INT_PIN_2 -1
  262. #define VCMD_JPEGD_MODULE_TYPE_2 4
  263. #define VCMD_JPEGD_MODULE_MAIN_ADDR_2 0x0000 /*customer specify according to own platform*/
  264. #define VCMD_JPEGD_MODULE_DEC400_ADDR_2 0XFFFF /*0xffff means no such kind of submodule*/
  265. #define VCMD_JPEGD_MODULE_L2CACHE_ADDR_2 0XFFFF
  266. #define VCMD_JPEGD_MODULE_MMU_ADDR_2 0XFFFF
  267. #define VCMD_JPEGD_IO_ADDR_3 0xD3000 /*customer specify according to own platform*/
  268. #define VCMD_JPEGD_IO_SIZE_3 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  269. #define VCMD_JPEGD_INT_PIN_3 -1
  270. #define VCMD_JPEGD_MODULE_TYPE_3 4
  271. #define VCMD_JPEGD_MODULE_MAIN_ADDR_3 0x0000 /*customer specify according to own platform*/
  272. #define VCMD_JPEGD_MODULE_DEC400_ADDR_3 0XFFFF /*0xffff means no such kind of submodule*/
  273. #define VCMD_JPEGD_MODULE_L2CACHE_ADDR_3 0XFFFF
  274. #define VCMD_JPEGD_MODULE_MMU_ADDR_3 0XFFFF
  275. struct vcmd_config
  276. {
  277. unsigned long vcmd_base_addr;
  278. u32 vcmd_iosize;
  279. int vcmd_irq;
  280. u32 sub_module_type; /*input vc8000e=0,IM=1,vc8000d=2,jpege=3, jpegd=4*/
  281. u16 submodule_main_addr; // in byte
  282. u16 submodule_dec400_addr;//if submodule addr == 0xffff, this submodule does not exist.// in byte
  283. u16 submodule_L2Cache_addr; // in byte
  284. u16 submodule_MMU_addr[2]; // in byte
  285. u16 submodule_axife_addr[2]; // in byte
  286. };
  287. #define NETINT
  288. //#define MAGVII
  289. //#define OYB_VCEJ
  290. //#define OYB_VCE
  291. /*for all vcmds, the core info should be listed here for subsequent use*/
  292. static struct vcmd_config vcmd_core_array[]= {
  293. #if defined(NETINT) || defined(OYB_VCE)
  294. //encoder configuration
  295. {VCMD_ENC_IO_ADDR_0,
  296. VCMD_ENC_IO_SIZE_0,
  297. VCMD_ENC_INT_PIN_0,
  298. VCMD_ENC_MODULE_TYPE_0,
  299. VCMD_ENC_MODULE_MAIN_ADDR_0,
  300. VCMD_ENC_MODULE_DEC400_ADDR_0,
  301. VCMD_ENC_MODULE_L2CACHE_ADDR_0,
  302. {VCMD_ENC_MODULE_MMU0_ADDR_0,
  303. VCMD_ENC_MODULE_MMU1_ADDR_0},
  304. {VCMD_ENC_MODULE_AXIFE0_ADDR_0,
  305. VCMD_ENC_MODULE_AXIFE1_ADDR_0}},
  306. #endif
  307. #if 0
  308. {VCMD_ENC_IO_ADDR_1,
  309. VCMD_ENC_IO_SIZE_1,
  310. VCMD_ENC_INT_PIN_1,
  311. VCMD_ENC_MODULE_TYPE_1,
  312. VCMD_ENC_MODULE_MAIN_ADDR_1,
  313. VCMD_ENC_MODULE_DEC400_ADDR_1,
  314. VCMD_ENC_MODULE_L2CACHE_ADDR_1,
  315. VCMD_ENC_MODULE_MMU_ADDR_1},
  316. {VCMD_ENC_IO_ADDR_2,
  317. VCMD_ENC_IO_SIZE_2,
  318. VCMD_ENC_INT_PIN_2,
  319. VCMD_ENC_MODULE_TYPE_2,
  320. VCMD_ENC_MODULE_MAIN_ADDR_2,
  321. VCMD_ENC_MODULE_DEC400_ADDR_2,
  322. VCMD_ENC_MODULE_L2CACHE_ADDR_2,
  323. VCMD_ENC_MODULE_MMU_ADDR_2},
  324. {VCMD_ENC_IO_ADDR_3,
  325. VCMD_ENC_IO_SIZE_3,
  326. VCMD_ENC_INT_PIN_3,
  327. VCMD_ENC_MODULE_TYPE_3,
  328. VCMD_ENC_MODULE_MAIN_ADDR_3,
  329. VCMD_ENC_MODULE_DEC400_ADDR_3,
  330. VCMD_ENC_MODULE_L2CACHE_ADDR_3,
  331. VCMD_ENC_MODULE_MMU_ADDR_3},
  332. #endif
  333. //cutree/IM configuration
  334. #if defined(NETINT) || defined(OYB_VCE)
  335. {VCMD_IM_IO_ADDR_0,
  336. VCMD_IM_IO_SIZE_0,
  337. VCMD_IM_INT_PIN_0,
  338. VCMD_IM_MODULE_TYPE_0,
  339. VCMD_IM_MODULE_MAIN_ADDR_0,
  340. VCMD_IM_MODULE_DEC400_ADDR_0,
  341. VCMD_IM_MODULE_L2CACHE_ADDR_0,
  342. {VCMD_IM_MODULE_MMU0_ADDR_0,
  343. VCMD_IM_MODULE_MMU1_ADDR_0},
  344. {VCMD_IM_MODULE_AXIFE0_ADDR_0,
  345. VCMD_IM_MODULE_AXIFE1_ADDR_0}},
  346. #endif
  347. #if 0
  348. {VCMD_IM_IO_ADDR_1,
  349. VCMD_IM_IO_SIZE_1,
  350. VCMD_IM_INT_PIN_1,
  351. VCMD_IM_MODULE_TYPE_1,
  352. VCMD_IM_MODULE_MAIN_ADDR_1,
  353. VCMD_IM_MODULE_DEC400_ADDR_1,
  354. VCMD_IM_MODULE_L2CACHE_ADDR_1,
  355. VCMD_IM_MODULE_MMU_ADDR_1},
  356. {VCMD_IM_IO_ADDR_2,
  357. VCMD_IM_IO_SIZE_2,
  358. VCMD_IM_INT_PIN_2,
  359. VCMD_IM_MODULE_TYPE_2,
  360. VCMD_IM_MODULE_MAIN_ADDR_2,
  361. VCMD_IM_MODULE_DEC400_ADDR_2,
  362. VCMD_IM_MODULE_L2CACHE_ADDR_2,
  363. VCMD_IM_MODULE_MMU_ADDR_2},
  364. {VCMD_IM_IO_ADDR_3,
  365. VCMD_IM_IO_SIZE_3,
  366. VCMD_IM_INT_PIN_3,
  367. VCMD_IM_MODULE_TYPE_3,
  368. VCMD_IM_MODULE_MAIN_ADDR_3,
  369. VCMD_IM_MODULE_DEC400_ADDR_3,
  370. VCMD_IM_MODULE_L2CACHE_ADDR_3,
  371. VCMD_IM_MODULE_MMU_ADDR_3},
  372. //decoder configuration
  373. {VCMD_DEC_IO_ADDR_0,
  374. VCMD_DEC_IO_SIZE_0,
  375. VCMD_DEC_INT_PIN_0,
  376. VCMD_DEC_MODULE_TYPE_0,
  377. VCMD_DEC_MODULE_MAIN_ADDR_0,
  378. VCMD_DEC_MODULE_DEC400_ADDR_0,
  379. VCMD_DEC_MODULE_L2CACHE_ADDR_0,
  380. VCMD_DEC_MODULE_MMU_ADDR_0},
  381. {VCMD_DEC_IO_ADDR_1,
  382. VCMD_DEC_IO_SIZE_1,
  383. VCMD_DEC_INT_PIN_1,
  384. VCMD_DEC_MODULE_TYPE_1,
  385. VCMD_DEC_MODULE_MAIN_ADDR_1,
  386. VCMD_DEC_MODULE_DEC400_ADDR_1,
  387. VCMD_DEC_MODULE_L2CACHE_ADDR_1,
  388. VCMD_DEC_MODULE_MMU_ADDR_1},
  389. {VCMD_DEC_IO_ADDR_2,
  390. VCMD_DEC_IO_SIZE_2,
  391. VCMD_DEC_INT_PIN_2,
  392. VCMD_DEC_MODULE_TYPE_2,
  393. VCMD_DEC_MODULE_MAIN_ADDR_2,
  394. VCMD_DEC_MODULE_DEC400_ADDR_2,
  395. VCMD_DEC_MODULE_L2CACHE_ADDR_2,
  396. VCMD_DEC_MODULE_MMU_ADDR_2},
  397. {VCMD_DEC_IO_ADDR_3,
  398. VCMD_DEC_IO_SIZE_3,
  399. VCMD_DEC_INT_PIN_3,
  400. VCMD_DEC_MODULE_TYPE_3,
  401. VCMD_DEC_MODULE_MAIN_ADDR_3,
  402. VCMD_DEC_MODULE_DEC400_ADDR_3,
  403. VCMD_DEC_MODULE_L2CACHE_ADDR_3,
  404. VCMD_DEC_MODULE_MMU_ADDR_3},
  405. #endif
  406. #if defined(MAGVII) || defined(OYB_VCEJ)
  407. //JPEG encoder configuration
  408. {VCMD_JPEGE_IO_ADDR_0,
  409. VCMD_JPEGE_IO_SIZE_0,
  410. VCMD_JPEGE_INT_PIN_0,
  411. VCMD_JPEGE_MODULE_TYPE_0,
  412. VCMD_JPEGE_MODULE_MAIN_ADDR_0,
  413. VCMD_JPEGE_MODULE_DEC400_ADDR_0,
  414. VCMD_JPEGE_MODULE_L2CACHE_ADDR_0,
  415. {VCMD_JPEGE_MODULE_MMU0_ADDR_0,
  416. VCMD_JPEGE_MODULE_MMU1_ADDR_0},
  417. {VCMD_JPEGE_MODULE_AXIFE0_ADDR_0,
  418. VCMD_JPEGE_MODULE_AXIFE1_ADDR_0}},
  419. #endif
  420. #if 0
  421. {VCMD_JPEGE_IO_ADDR_1,
  422. VCMD_JPEGE_IO_SIZE_1,
  423. VCMD_JPEGE_INT_PIN_1,
  424. VCMD_JPEGE_MODULE_TYPE_1,
  425. VCMD_JPEGE_MODULE_MAIN_ADDR_1,
  426. VCMD_JPEGE_MODULE_DEC400_ADDR_1,
  427. VCMD_JPEGE_MODULE_L2CACHE_ADDR_1,
  428. VCMD_JPEGE_MODULE_MMU_ADDR_1},
  429. {VCMD_JPEGE_IO_ADDR_2,
  430. VCMD_JPEGE_IO_SIZE_2,
  431. VCMD_JPEGE_INT_PIN_2,
  432. VCMD_JPEGE_MODULE_TYPE_2,
  433. VCMD_JPEGE_MODULE_MAIN_ADDR_2,
  434. VCMD_JPEGE_MODULE_DEC400_ADDR_2,
  435. VCMD_JPEGE_MODULE_L2CACHE_ADDR_2,
  436. VCMD_JPEGE_MODULE_MMU_ADDR_2},
  437. {VCMD_JPEGE_IO_ADDR_3,
  438. VCMD_JPEGE_IO_SIZE_3,
  439. VCMD_JPEGE_INT_PIN_3,
  440. VCMD_JPEGE_MODULE_TYPE_3,
  441. VCMD_JPEGE_MODULE_MAIN_ADDR_3,
  442. VCMD_JPEGE_MODULE_DEC400_ADDR_3,
  443. VCMD_JPEGE_MODULE_L2CACHE_ADDR_3,
  444. VCMD_JPEGE_MODULE_MMU_ADDR_3},
  445. //JPEG decoder configuration
  446. {VCMD_JPEGD_IO_ADDR_0,
  447. VCMD_JPEGD_IO_SIZE_0,
  448. VCMD_JPEGD_INT_PIN_0,
  449. VCMD_JPEGD_MODULE_TYPE_0,
  450. VCMD_JPEGD_MODULE_MAIN_ADDR_0,
  451. VCMD_JPEGD_MODULE_DEC400_ADDR_0,
  452. VCMD_JPEGD_MODULE_L2CACHE_ADDR_0,
  453. VCMD_JPEGD_MODULE_MMU_ADDR_0},
  454. {VCMD_JPEGD_IO_ADDR_1,
  455. VCMD_JPEGD_IO_SIZE_1,
  456. VCMD_JPEGD_INT_PIN_1,
  457. VCMD_JPEGD_MODULE_TYPE_1,
  458. VCMD_JPEGD_MODULE_MAIN_ADDR_1,
  459. VCMD_JPEGD_MODULE_DEC400_ADDR_1,
  460. VCMD_JPEGD_MODULE_L2CACHE_ADDR_1,
  461. VCMD_JPEGD_MODULE_MMU_ADDR_1},
  462. {VCMD_JPEGD_IO_ADDR_2,
  463. VCMD_JPEGD_IO_SIZE_2,
  464. VCMD_JPEGD_INT_PIN_2,
  465. VCMD_JPEGD_MODULE_TYPE_2,
  466. VCMD_JPEGD_MODULE_MAIN_ADDR_2,
  467. VCMD_JPEGD_MODULE_DEC400_ADDR_2,
  468. VCMD_JPEGD_MODULE_L2CACHE_ADDR_2,
  469. VCMD_JPEGD_MODULE_MMU_ADDR_2},
  470. {VCMD_JPEGD_IO_ADDR_3,
  471. VCMD_JPEGD_IO_SIZE_3,
  472. VCMD_JPEGD_INT_PIN_3,
  473. VCMD_JPEGD_MODULE_TYPE_3,
  474. VCMD_JPEGD_MODULE_MAIN_ADDR_3,
  475. VCMD_JPEGD_MODULE_DEC400_ADDR_3,
  476. VCMD_JPEGD_MODULE_L2CACHE_ADDR_3,
  477. VCMD_JPEGD_MODULE_MMU_ADDR_3},
  478. #endif
  479. };
  480. /*these size need to be modified according to hw config.*/
  481. #define VCMD_ENCODER_REGISTER_SIZE (479 * 4)
  482. #define VCMD_DECODER_REGISTER_SIZE (512 * 4)
  483. #define VCMD_IM_REGISTER_SIZE (479 * 4)
  484. #define VCMD_JPEG_ENCODER_REGISTER_SIZE (479 * 4)
  485. #define VCMD_JPEG_DECODER_REGISTER_SIZE (512 * 4)
  486. #define MAX_VCMD_NUMBER (MAX_VCMD_TYPE*MAX_SAME_MODULE_TYPE_CORE_NUMBER) //
  487. #define HW_WORK_STATE_PEND 3
  488. #define MAX_CMDBUF_INT_NUMBER 1
  489. #define INT_MIN_SUM_OF_IMAGE_SIZE (4096*2160*MAX_SAME_MODULE_TYPE_CORE_NUMBER*MAX_CMDBUF_INT_NUMBER)
  490. #define MAX_PROCESS_CORE_NUMBER 4*8
  491. #define PROCESS_MAX_SUM_OF_IMAGE_SIZE (4096*2160*MAX_SAME_MODULE_TYPE_CORE_NUMBER*MAX_PROCESS_CORE_NUMBER)
  492. #define MAX_SAME_MODULE_TYPE_CORE_NUMBER 4
  493. #define VC8000E_MAX_CONFIG_LEN 32
  494. #define VC8000E_PM_TIMEOUT 100 /* ms */
  495. static size_t base_ddr_addr = 0; /*pcie address need to substract this value then can be put to register*/
  496. #ifdef HANTROAXIFE_SUPPORT
  497. #define AXIFE_SIZE (64*4)
  498. volatile u8* axife_hwregs[MAX_VCMD_NUMBER][2];
  499. #endif
  500. #ifdef HANTROMMU_SUPPORT
  501. #define MMU_SIZE (228*4)
  502. extern unsigned int mmu_enable;
  503. extern unsigned long gBaseDDRHw;
  504. static volatile u8* mmu_hwregs[MAX_VCMD_NUMBER][2];
  505. #else
  506. static unsigned int mmu_enable = 0;
  507. #endif
  508. /********variables declaration related with race condition**********/
  509. #define CMDBUF_MAX_SIZE (512*4*4)
  510. #define CMDBUF_POOL_TOTAL_SIZE (2*1024*1024) //approximately=128x(320x240)=128x2k=128x8kbyte=1Mbytes
  511. #define TOTAL_DISCRETE_CMDBUF_NUM (CMDBUF_POOL_TOTAL_SIZE/CMDBUF_MAX_SIZE)
  512. #define CMDBUF_VCMD_REGISTER_TOTAL_SIZE 9*1024*1024-CMDBUF_POOL_TOTAL_SIZE*2
  513. #define VCMD_REGISTER_SIZE (128*4)
  514. #ifndef DYNAMIC_MALLOC_VCMDNODE
  515. static struct cmdbuf_obj *g_cmdbuf_obj_pool;
  516. static struct bi_list_node *g_cmdbuf_node_pool;
  517. #endif
  518. struct noncache_mem
  519. {
  520. u32 *virtualAddress;
  521. dma_addr_t busAddress;
  522. unsigned int mmu_bus_address; /* buffer physical address in MMU*/
  523. u32 size;
  524. u16 cmdbuf_id;
  525. };
  526. struct process_manager_obj
  527. {
  528. struct file *filp;
  529. u32 total_exe_time;
  530. u32 pm_count;
  531. spinlock_t spinlock;
  532. wait_queue_head_t wait_queue;
  533. } ;
  534. struct cmdbuf_obj
  535. {
  536. u32 module_type; //current CMDBUF type: input vc8000e=0,IM=1,vc8000d=2,jpege=3, jpegd=4
  537. u32 priority; //current CMDBUFpriority: normal=0, high=1
  538. u32 executing_time; //current CMDBUFexecuting_time=encoded_image_size*(rdoLevel+1)*(rdoq+1);
  539. u32 cmdbuf_size; //current CMDBUF size
  540. u32 *cmdbuf_virtualAddress; //current CMDBUF start virtual address.
  541. size_t cmdbuf_busAddress; //current CMDBUF start physical address.
  542. unsigned int mmu_cmdbuf_busAddress; //current CMDBUF start mmu mapping address.
  543. u32 *status_virtualAddress; //current status CMDBUF start virtual address.
  544. size_t status_busAddress; //current status CMDBUF start physical address.
  545. unsigned int mmu_status_busAddress; //current status CMDBUF start mmu mapping address.
  546. u32 status_size; //current status CMDBUF size
  547. u32 executing_status; //current CMDBUF executing status.
  548. struct file *filp; //file pointer in the same process.
  549. u16 core_id; //which vcmd core is used.
  550. u16 cmdbuf_id; //used to manage CMDBUF in driver.It is a handle to identify cmdbuf.also is an interrupt vector.position in pool,same as status position.
  551. u8 cmdbuf_data_loaded; //0 means sw has not copied data into this CMDBUF; 1 means sw has copied data into this CMDBUF
  552. u8 cmdbuf_data_linked; //0 :not linked, 1:linked.into a vcmd core list.
  553. u8 cmdbuf_run_done; //if 0,waiting for CMDBUF finish; if 1, op code in CMDBUF has finished one by one. HANTRO_VCMD_IOCH_WAIT_CMDBUF will check this variable.
  554. u8 cmdbuf_need_remove; // if 0, not need to remove CMDBUF; 1 CMDBUF can be removed if it is not the last CMDBUF;
  555. u8 has_end_cmdbuf; //if 1, the last opcode is end opCode.
  556. u8 no_normal_int_cmdbuf; //if 1, JMP will not send normal interrupt.
  557. struct process_manager_obj* process_manager_obj;
  558. };
  559. struct hantrovcmd_dev
  560. {
  561. struct vcmd_config vcmd_core_cfg; //config of each core,such as base addr, irq,etc
  562. u32 core_id; //vcmd core id for driver and sw internal use
  563. u32 sw_cmdbuf_rdy_num;
  564. spinlock_t* spinlock;
  565. wait_queue_head_t * wait_queue;
  566. wait_queue_head_t * wait_abort_queue;
  567. bi_list list_manager;
  568. volatile u8 *hwregs;/* IO mem base */
  569. u32 reg_mirror[ASIC_VCMD_SWREG_AMOUNT];
  570. u32 duration_without_int; //number of cmdbufs without interrupt.
  571. volatile u8 working_state;
  572. u32 total_exe_time;
  573. u16 status_cmdbuf_id;//used for analyse configuration in cwl.
  574. u32 hw_version_id; /*megvii 0x43421001, later 0x43421102*/
  575. u32 *vcmd_reg_mem_virtualAddress;//start virtual address of vcmd registers memory of CMDBUF.
  576. size_t vcmd_reg_mem_busAddress; //start physical address of vcmd registers memory of CMDBUF.
  577. unsigned int mmu_vcmd_reg_mem_busAddress; //start mmu mapping address of vcmd registers memory of CMDBUF.
  578. u32 vcmd_reg_mem_size; // size of vcmd registers memory of CMDBUF.
  579. struct platform_device *pdev;
  580. struct clk *cclk;
  581. struct clk *aclk;
  582. struct clk *pclk;
  583. char config_buf[VC8000E_MAX_CONFIG_LEN];
  584. int has_power_domains;
  585. } ;
  586. /*
  587. * Ioctl definitions
  588. */
  589. #define VCMD_HW_ID 0x4342
  590. static struct noncache_mem vcmd_buf_mem_pool;
  591. static struct noncache_mem vcmd_status_buf_mem_pool;
  592. static struct noncache_mem vcmd_registers_mem_pool;
  593. static u16 cmdbuf_used[TOTAL_DISCRETE_CMDBUF_NUM];
  594. static u16 cmdbuf_used_pos;
  595. static u16 cmdbuf_used_residual;
  596. static struct hantrovcmd_dev* vcmd_manager[MAX_VCMD_TYPE][MAX_VCMD_NUMBER];
  597. static bi_list_node* global_cmdbuf_node[TOTAL_DISCRETE_CMDBUF_NUM];
  598. static bi_list global_process_manager;
  599. static u16 vcmd_position[MAX_VCMD_TYPE];
  600. static int vcmd_type_core_num[MAX_VCMD_TYPE];
  601. #define EXECUTING_CMDBUF_ID_ADDR 26
  602. #define VCMD_EXE_CMDBUF_COUNT 3
  603. #define WORKING_STATE_IDLE 0
  604. #define WORKING_STATE_WORKING 1
  605. #define CMDBUF_EXE_STATUS_OK 0
  606. #define CMDBUF_EXE_STATUS_CMDERR 1
  607. #define CMDBUF_EXE_STATUS_BUSERR 2
  608. struct semaphore vcmd_reserve_cmdbuf_sem[MAX_VCMD_TYPE]; //for reserve
  609. //#define VCMD_DEBUG_INTERNAL
  610. /***************************TYPE AND FUNCTION DECLARATION****************/
  611. /* here's all the must remember stuff */
  612. static int vcmd_reserve_IO(void);
  613. static void vcmd_release_IO(void);
  614. static void vcmd_reset_asic(struct hantrovcmd_dev * dev);
  615. static void vcmd_reset_current_asic(struct hantrovcmd_dev * dev);
  616. static int allocate_cmdbuf(struct noncache_mem* new_cmdbuf_addr,struct noncache_mem* new_status_cmdbuf_addr);
  617. static void vcmd_link_cmdbuf(struct hantrovcmd_dev *dev,bi_list_node* last_linked_cmdbuf_node);
  618. static void vcmd_start(struct hantrovcmd_dev *dev,bi_list_node* first_linked_cmdbuf_node);
  619. static void create_kernel_process_manager(void);
  620. static void vcmd_reset(void);
  621. #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18))
  622. static irqreturn_t hantrovcmd_isr(int irq, void *dev_id, struct pt_regs *regs);
  623. #else
  624. static irqreturn_t hantrovcmd_isr(int irq, void *dev_id);
  625. #endif
  626. #ifdef VCMD_DEBUG_INTERNAL
  627. static void printk_vcmd_register_debug(const void *hwregs, char* info);
  628. #endif
  629. /*********************local variable declaration*****************/
  630. static unsigned long vcmd_sram_base = 0;
  631. static unsigned int vcmd_sram_size = 0;
  632. /* and this is our MAJOR; use 0 for dynamic allocation (recommended)*/
  633. static int hantrovcmd_major = 0;
  634. static int hantrovcmd_minor = 0; /* dynamic allocation */
  635. static struct cdev hantrovcmd_cdev;
  636. static dev_t hantrovcmd_devt;
  637. static struct class *hantrovcmd_class;
  638. static int total_vcmd_core_num = 0;
  639. /* dynamic allocation*/
  640. static struct hantrovcmd_dev* hantrovcmd_data = NULL;
  641. static struct dentry *root_debugfs_dir = NULL;
  642. static int software_triger_abort=0;
  643. //#define IRQ_SIMULATION
  644. #ifdef IRQ_SIMULATION
  645. struct timer_manager
  646. {
  647. u32 core_id; //vcmd core id for driver and sw internal use
  648. u32 timer_id;
  649. struct timer_list *timer;
  650. } ;
  651. static struct timer_list timer[10000];
  652. struct timer_manager timer_reserve[10000];
  653. #if 0
  654. static struct timer_list timer0;
  655. static struct timer_list timer1;
  656. #endif
  657. #endif
  658. //hw_queue can be used for reserve cmdbuf memory
  659. DECLARE_WAIT_QUEUE_HEAD(vcmd_cmdbuf_memory_wait);
  660. DEFINE_SPINLOCK(vcmd_cmdbuf_alloc_lock);
  661. DEFINE_SPINLOCK(vcmd_process_manager_lock);
  662. static spinlock_t owner_lock_vcmd[MAX_VCMD_NUMBER];
  663. static wait_queue_head_t wait_queue_vcmd[MAX_VCMD_NUMBER];
  664. static wait_queue_head_t abort_queue_vcmd[MAX_VCMD_NUMBER];
  665. #if 0
  666. /*allocate non-cacheable DMA memory*/
  667. #define DRIVER_NAME_HANTRO_NON_CACH_MEM "non_cach_memory"
  668. static struct platform_device *noncachable_mem_dev = NULL;
  669. static const struct platform_device_info hantro_platform_info = {
  670. .name = DRIVER_NAME_HANTRO_NON_CACH_MEM,
  671. .id = -1,
  672. .dma_mask = DMA_BIT_MASK(32),
  673. };
  674. static int hantro_noncachable_mem_probe(struct platform_device *pdev)
  675. {
  676. struct device *dev = &pdev->dev;
  677. vcmd_buf_mem_pool.virtualAddress = dma_alloc_coherent(dev,CMDBUF_POOL_TOTAL_SIZE,&vcmd_buf_mem_pool.busAddress, GFP_KERNEL | GFP_DMA);
  678. vcmd_buf_mem_pool.size = CMDBUF_POOL_TOTAL_SIZE;
  679. vcmd_status_buf_mem_pool.virtualAddress = dma_alloc_coherent(dev,CMDBUF_POOL_TOTAL_SIZE,&vcmd_status_buf_mem_pool.busAddress, GFP_KERNEL | GFP_DMA);
  680. vcmd_status_buf_mem_pool.size = CMDBUF_POOL_TOTAL_SIZE;
  681. return 0;
  682. }
  683. static int hantro_noncachable_mem_remove(struct platform_device *pdev)
  684. {
  685. struct device *dev = &pdev->dev;
  686. dma_free_coherent(dev,vcmd_buf_mem_pool.size,vcmd_buf_mem_pool.virtualAddress,vcmd_buf_mem_pool.busAddress);
  687. dma_free_coherent(dev,vcmd_status_buf_mem_pool.size,vcmd_status_buf_mem_pool.virtualAddress,vcmd_status_buf_mem_pool.busAddress);
  688. return 0;
  689. }
  690. static const struct platform_device_id hantro_noncachable_mem_platform_ids[]={
  691. {
  692. .name = DRIVER_NAME_HANTRO_NON_CACH_MEM,
  693. },
  694. {/* sentinel */},
  695. };
  696. static const struct of_device_id hantro_of_match[]={
  697. {
  698. .compatible = "thead,light-vc8000e",
  699. },
  700. {/* sentinel */},
  701. };
  702. static struct platform_driver hantro_noncachable_mem_platform_driver = {
  703. .probe = hantro_noncachable_mem_probe,
  704. .remove = hantro_noncachable_mem_remove,
  705. .driver ={
  706. .name = DRIVER_NAME_HANTRO_NON_CACH_MEM,
  707. .owner = THIS_MODULE,
  708. .of_match_table = hantro_of_match,
  709. },
  710. .id_table = hantro_noncachable_mem_platform_ids,
  711. };
  712. static void init_vcmd_non_cachable_memory_allocate(void)
  713. {
  714. /*create device: This will create a {struct platform_device}, It has a member dev, which is a {struct device} */
  715. noncachable_mem_dev = platform_device_register_full(&hantro_platform_info);
  716. /*when this function is called, the .probe callback is invoked.*/
  717. platform_driver_register(&hantro_noncachable_mem_platform_driver);
  718. }
  719. static void release_vcmd_non_cachable_memory(void)
  720. {
  721. /* when this fucntion is called, .remove callback will be invoked. use it to clean up all resources allocated in .probe.*/
  722. platform_driver_unregister(&hantro_noncachable_mem_platform_driver);
  723. /*destroy the device*/
  724. platform_device_unregister(noncachable_mem_dev);
  725. }
  726. #endif
  727. /**********************************************************************************************************\
  728. *cmdbuf object management
  729. \***********************************************************************************************************/
  730. static struct cmdbuf_obj* create_cmdbuf_obj(void)
  731. {
  732. struct cmdbuf_obj* cmdbuf_obj=NULL;
  733. cmdbuf_obj=vmalloc(sizeof(struct cmdbuf_obj));
  734. if(cmdbuf_obj==NULL)
  735. {
  736. PDEBUG ("%s\n","vmalloc for cmdbuf_obj fail!");
  737. return cmdbuf_obj;
  738. }
  739. memset(cmdbuf_obj,0,sizeof(struct cmdbuf_obj));
  740. return cmdbuf_obj;
  741. }
  742. static void free_cmdbuf_obj(struct cmdbuf_obj* cmdbuf_obj)
  743. {
  744. #ifdef DYNAMIC_MALLOC_VCMDNODE
  745. if(cmdbuf_obj==NULL)
  746. {
  747. PDEBUG ("%s\n","remove_cmdbuf_obj NULL");
  748. return;
  749. }
  750. //free current cmdbuf_obj
  751. vfree(cmdbuf_obj);
  752. return;
  753. #endif
  754. }
  755. static struct cmdbuf_obj *create_vcmd_cmdbuf_obj(u16 cmdbuf_id)
  756. {
  757. struct cmdbuf_obj *cmdbuf_obj = NULL;
  758. #ifdef DYNAMIC_MALLOC_VCMDNODE
  759. cmdbuf_obj = create_cmdbuf_obj();
  760. #else
  761. cmdbuf_obj = g_cmdbuf_obj_pool + cmdbuf_id;
  762. if (cmdbuf_obj)
  763. memset(cmdbuf_obj, 0, sizeof(struct cmdbuf_obj));
  764. #endif
  765. return cmdbuf_obj;
  766. }
  767. static bi_list_node *bi_list_create_vcmd_node(u16 cmdbuf_id)
  768. {
  769. bi_list_node *node = NULL;
  770. #ifdef DYNAMIC_MALLOC_VCMDNODE
  771. node = bi_list_create_node();
  772. #else
  773. node = g_cmdbuf_node_pool + cmdbuf_id;
  774. if (node)
  775. memset(node, 0, sizeof(bi_list_node));
  776. #endif
  777. return node;
  778. }
  779. static void free_cmdbuf_mem(u16 cmdbuf_id )
  780. {
  781. unsigned long flags;
  782. spin_lock_irqsave(&vcmd_cmdbuf_alloc_lock, flags);
  783. cmdbuf_used[cmdbuf_id]=0;
  784. cmdbuf_used_residual +=1;
  785. spin_unlock_irqrestore(&vcmd_cmdbuf_alloc_lock, flags);
  786. wake_up_interruptible_all(&vcmd_cmdbuf_memory_wait);
  787. }
  788. static bi_list_node* create_cmdbuf_node(void)
  789. {
  790. bi_list_node* current_node=NULL;
  791. struct cmdbuf_obj* cmdbuf_obj=NULL;
  792. struct noncache_mem new_cmdbuf_addr;
  793. struct noncache_mem new_status_cmdbuf_addr;
  794. if(wait_event_interruptible(vcmd_cmdbuf_memory_wait, allocate_cmdbuf(&new_cmdbuf_addr,&new_status_cmdbuf_addr)) )
  795. return NULL;
  796. cmdbuf_obj = create_vcmd_cmdbuf_obj(new_cmdbuf_addr.cmdbuf_id);
  797. if(cmdbuf_obj==NULL)
  798. {
  799. PDEBUG ("%s\n","create_vcmd_cmdbuf_obj fail!");
  800. free_cmdbuf_mem(new_cmdbuf_addr.cmdbuf_id);
  801. return NULL;
  802. }
  803. cmdbuf_obj->cmdbuf_busAddress = new_cmdbuf_addr.busAddress;
  804. cmdbuf_obj->mmu_cmdbuf_busAddress = new_cmdbuf_addr.mmu_bus_address;
  805. cmdbuf_obj->cmdbuf_virtualAddress = new_cmdbuf_addr.virtualAddress;
  806. cmdbuf_obj->cmdbuf_size = new_cmdbuf_addr.size;
  807. cmdbuf_obj->cmdbuf_id = new_cmdbuf_addr.cmdbuf_id;
  808. cmdbuf_obj->status_busAddress = new_status_cmdbuf_addr.busAddress;
  809. cmdbuf_obj->mmu_status_busAddress = new_status_cmdbuf_addr.mmu_bus_address;
  810. cmdbuf_obj->status_virtualAddress = new_status_cmdbuf_addr.virtualAddress;
  811. cmdbuf_obj->status_size = new_status_cmdbuf_addr.size;
  812. current_node=bi_list_create_vcmd_node(cmdbuf_obj->cmdbuf_id);
  813. if(current_node==NULL)
  814. {
  815. PDEBUG ("%s\n","bi_list_create_vcmd_node fail!");
  816. free_cmdbuf_mem(new_cmdbuf_addr.cmdbuf_id);
  817. free_cmdbuf_obj(cmdbuf_obj);
  818. return NULL;
  819. }
  820. current_node->data = (void*)cmdbuf_obj;
  821. current_node->next = NULL;
  822. current_node->previous = NULL;
  823. return current_node;
  824. }
  825. static void free_cmdbuf_node(bi_list_node* cmdbuf_node)
  826. {
  827. struct cmdbuf_obj* cmdbuf_obj=NULL;
  828. if(cmdbuf_node==NULL)
  829. {
  830. PDEBUG ("%s\n","remove_cmdbuf_node NULL");
  831. return;
  832. }
  833. cmdbuf_obj = (struct cmdbuf_obj*)cmdbuf_node->data;
  834. //free cmdbuf mem in pool
  835. free_cmdbuf_mem(cmdbuf_obj->cmdbuf_id);
  836. //free struct cmdbuf_obj
  837. free_cmdbuf_obj(cmdbuf_obj);
  838. #ifdef DYNAMIC_MALLOC_VCMDNODE
  839. //free current cmdbuf_node entity.
  840. bi_list_free_node(cmdbuf_node);
  841. #endif
  842. return;
  843. }
  844. //just remove, not free the node.
  845. static bi_list_node* remove_cmdbuf_node_from_list(bi_list* list,bi_list_node* cmdbuf_node)
  846. {
  847. if(cmdbuf_node==NULL)
  848. {
  849. PDEBUG ("%s\n","remove_cmdbuf_node_from_list NULL");
  850. return NULL;
  851. }
  852. if(cmdbuf_node->next)
  853. {
  854. bi_list_remove_node(list,cmdbuf_node);
  855. return cmdbuf_node;
  856. }
  857. else
  858. {
  859. //the last one, should not be removed.
  860. return NULL;
  861. }
  862. }
  863. //calculate executing_time of each vcmd
  864. static u32 calculate_executing_time_after_node(bi_list_node* exe_cmdbuf_node)
  865. {
  866. u32 time_run_all=0;
  867. struct cmdbuf_obj* cmdbuf_obj_temp=NULL;
  868. while(1)
  869. {
  870. if(exe_cmdbuf_node==NULL)
  871. break;
  872. cmdbuf_obj_temp=(struct cmdbuf_obj* )exe_cmdbuf_node->data;
  873. time_run_all += cmdbuf_obj_temp->executing_time;
  874. exe_cmdbuf_node = exe_cmdbuf_node->next;
  875. }
  876. return time_run_all;
  877. }
  878. static u32 calculate_executing_time_after_node_high_priority(bi_list_node* exe_cmdbuf_node)
  879. {
  880. u32 time_run_all=0;
  881. struct cmdbuf_obj* cmdbuf_obj_temp=NULL;
  882. if(exe_cmdbuf_node==NULL)
  883. return time_run_all;
  884. cmdbuf_obj_temp=(struct cmdbuf_obj* )exe_cmdbuf_node->data;
  885. time_run_all += cmdbuf_obj_temp->executing_time;
  886. exe_cmdbuf_node = exe_cmdbuf_node->next;
  887. while(1)
  888. {
  889. if(exe_cmdbuf_node==NULL)
  890. break;
  891. cmdbuf_obj_temp=(struct cmdbuf_obj* )exe_cmdbuf_node->data;
  892. if(cmdbuf_obj_temp->priority==CMDBUF_PRIORITY_NORMAL)
  893. break;
  894. time_run_all += cmdbuf_obj_temp->executing_time;
  895. exe_cmdbuf_node = exe_cmdbuf_node->next;
  896. }
  897. return time_run_all;
  898. }
  899. /**********************************************************************************************************\
  900. *cmdbuf pool management
  901. \***********************************************************************************************************/
  902. static int allocate_cmdbuf(struct noncache_mem* new_cmdbuf_addr,struct noncache_mem* new_status_cmdbuf_addr)
  903. {
  904. unsigned long flags;
  905. spin_lock_irqsave(&vcmd_cmdbuf_alloc_lock, flags);
  906. if(cmdbuf_used_residual==0)
  907. {
  908. spin_unlock_irqrestore(&vcmd_cmdbuf_alloc_lock, flags);
  909. //no empty cmdbuf
  910. return 0;
  911. }
  912. //there is one cmdbuf at least
  913. while(1)
  914. {
  915. if(cmdbuf_used[cmdbuf_used_pos]==0&&(global_cmdbuf_node[cmdbuf_used_pos]==NULL ))
  916. {
  917. cmdbuf_used[cmdbuf_used_pos]=1;
  918. cmdbuf_used_residual -=1;
  919. new_cmdbuf_addr->virtualAddress=vcmd_buf_mem_pool.virtualAddress + cmdbuf_used_pos*CMDBUF_MAX_SIZE/4;
  920. new_cmdbuf_addr->busAddress=vcmd_buf_mem_pool.busAddress + cmdbuf_used_pos*CMDBUF_MAX_SIZE;
  921. new_cmdbuf_addr->mmu_bus_address=vcmd_buf_mem_pool.mmu_bus_address + cmdbuf_used_pos*CMDBUF_MAX_SIZE;
  922. new_cmdbuf_addr->size=CMDBUF_MAX_SIZE;
  923. new_cmdbuf_addr->cmdbuf_id = cmdbuf_used_pos;
  924. new_status_cmdbuf_addr->virtualAddress=vcmd_status_buf_mem_pool.virtualAddress + cmdbuf_used_pos*CMDBUF_MAX_SIZE/4;
  925. new_status_cmdbuf_addr->busAddress=vcmd_status_buf_mem_pool.busAddress + cmdbuf_used_pos*CMDBUF_MAX_SIZE;
  926. new_status_cmdbuf_addr->mmu_bus_address=vcmd_status_buf_mem_pool.mmu_bus_address + cmdbuf_used_pos*CMDBUF_MAX_SIZE;
  927. new_status_cmdbuf_addr->size=CMDBUF_MAX_SIZE;
  928. new_status_cmdbuf_addr->cmdbuf_id = cmdbuf_used_pos;
  929. cmdbuf_used_pos++;
  930. if(cmdbuf_used_pos>=TOTAL_DISCRETE_CMDBUF_NUM)
  931. cmdbuf_used_pos=0;
  932. spin_unlock_irqrestore(&vcmd_cmdbuf_alloc_lock, flags);
  933. return 1;
  934. }
  935. else
  936. {
  937. cmdbuf_used_pos++;
  938. if(cmdbuf_used_pos>=TOTAL_DISCRETE_CMDBUF_NUM)
  939. cmdbuf_used_pos=0;
  940. }
  941. }
  942. return 0;
  943. }
  944. static bi_list_node* get_cmdbuf_node_in_list_by_addr(size_t cmdbuf_addr,bi_list* list)
  945. {
  946. bi_list_node* new_cmdbuf_node=NULL;
  947. struct cmdbuf_obj* cmdbuf_obj=NULL;
  948. new_cmdbuf_node=list->head;
  949. while(1)
  950. {
  951. if(new_cmdbuf_node==NULL)
  952. return NULL;
  953. cmdbuf_obj=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  954. if(((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr) <=cmdbuf_addr)&&(((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr+cmdbuf_obj->cmdbuf_size) >cmdbuf_addr)) )
  955. {
  956. return new_cmdbuf_node;
  957. }
  958. new_cmdbuf_node=new_cmdbuf_node->next;
  959. }
  960. return NULL;
  961. }
  962. static int wait_abort_rdy(struct hantrovcmd_dev*dev)
  963. {
  964. return dev->working_state == WORKING_STATE_IDLE;
  965. }
  966. static int select_vcmd(bi_list_node* new_cmdbuf_node)
  967. {
  968. struct cmdbuf_obj* cmdbuf_obj=NULL;
  969. bi_list_node* curr_cmdbuf_node=NULL;
  970. bi_list* list=NULL;
  971. struct hantrovcmd_dev*dev=NULL;
  972. struct hantrovcmd_dev*smallest_dev=NULL;
  973. u32 executing_time=0xffff;
  974. int counter=0;
  975. unsigned long flags=0;
  976. u32 hw_rdy_cmdbuf_num=0;
  977. size_t exe_cmdbuf_addr=0;
  978. struct cmdbuf_obj* cmdbuf_obj_temp=NULL;
  979. u32 cmdbuf_id=0;
  980. cmdbuf_obj=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  981. //there is an empty vcmd to be used
  982. while(1)
  983. {
  984. dev = vcmd_manager[cmdbuf_obj->module_type][vcmd_position[cmdbuf_obj->module_type]];
  985. list=&dev->list_manager;
  986. spin_lock_irqsave(dev->spinlock, flags);
  987. if( list->tail==NULL)
  988. {
  989. bi_list_insert_node_tail(list,new_cmdbuf_node);
  990. spin_unlock_irqrestore(dev->spinlock, flags);
  991. vcmd_position[cmdbuf_obj->module_type]++;
  992. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  993. vcmd_position[cmdbuf_obj->module_type]=0;
  994. cmdbuf_obj->core_id = dev->core_id;
  995. return 0;
  996. }
  997. else
  998. {
  999. spin_unlock_irqrestore(dev->spinlock, flags);
  1000. vcmd_position[cmdbuf_obj->module_type]++;
  1001. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1002. vcmd_position[cmdbuf_obj->module_type]=0;
  1003. counter++;
  1004. }
  1005. if(counter>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1006. break;
  1007. }
  1008. //there is a vcmd which tail node -> cmdbuf_run_done == 1. It means this vcmd has nothing to do, so we select it.
  1009. counter =0;
  1010. while(1)
  1011. {
  1012. dev = vcmd_manager[cmdbuf_obj->module_type][vcmd_position[cmdbuf_obj->module_type]];
  1013. list=&dev->list_manager;
  1014. spin_lock_irqsave(dev->spinlock, flags);
  1015. curr_cmdbuf_node = list->tail;
  1016. if(curr_cmdbuf_node == NULL)
  1017. {
  1018. bi_list_insert_node_tail(list,new_cmdbuf_node);
  1019. spin_unlock_irqrestore(dev->spinlock, flags);
  1020. vcmd_position[cmdbuf_obj->module_type]++;
  1021. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1022. vcmd_position[cmdbuf_obj->module_type]=0;
  1023. cmdbuf_obj->core_id = dev->core_id;
  1024. return 0;
  1025. }
  1026. cmdbuf_obj_temp =(struct cmdbuf_obj*) curr_cmdbuf_node->data;
  1027. if(cmdbuf_obj_temp->cmdbuf_run_done ==1)
  1028. {
  1029. bi_list_insert_node_tail(list,new_cmdbuf_node);
  1030. spin_unlock_irqrestore(dev->spinlock, flags);
  1031. vcmd_position[cmdbuf_obj->module_type]++;
  1032. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1033. vcmd_position[cmdbuf_obj->module_type]=0;
  1034. cmdbuf_obj->core_id = dev->core_id;
  1035. return 0;
  1036. }
  1037. else
  1038. {
  1039. spin_unlock_irqrestore(dev->spinlock, flags);
  1040. vcmd_position[cmdbuf_obj->module_type]++;
  1041. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1042. vcmd_position[cmdbuf_obj->module_type]=0;
  1043. counter++;
  1044. }
  1045. if(counter>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1046. break;
  1047. }
  1048. //another case, tail = executing node, and vcmd=pend state (finish but not generate interrupt)
  1049. counter =0;
  1050. while(1)
  1051. {
  1052. dev = vcmd_manager[cmdbuf_obj->module_type][vcmd_position[cmdbuf_obj->module_type]];
  1053. list=&dev->list_manager;
  1054. //read executing cmdbuf address
  1055. if(dev->hw_version_id <= HW_ID_1_0_C )
  1056. hw_rdy_cmdbuf_num = vcmd_get_register_value((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_EXE_CMDBUF_COUNT);
  1057. else
  1058. {
  1059. hw_rdy_cmdbuf_num = *(dev->vcmd_reg_mem_virtualAddress+VCMD_EXE_CMDBUF_COUNT);
  1060. if(hw_rdy_cmdbuf_num!=dev->sw_cmdbuf_rdy_num)
  1061. hw_rdy_cmdbuf_num += 1;
  1062. }
  1063. spin_lock_irqsave(dev->spinlock, flags);
  1064. curr_cmdbuf_node = list->tail;
  1065. if(curr_cmdbuf_node == NULL)
  1066. {
  1067. bi_list_insert_node_tail(list,new_cmdbuf_node);
  1068. spin_unlock_irqrestore(dev->spinlock, flags);
  1069. vcmd_position[cmdbuf_obj->module_type]++;
  1070. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1071. vcmd_position[cmdbuf_obj->module_type]=0;
  1072. cmdbuf_obj->core_id = dev->core_id;
  1073. return 0;
  1074. }
  1075. if((dev->sw_cmdbuf_rdy_num ==hw_rdy_cmdbuf_num))
  1076. {
  1077. bi_list_insert_node_tail(list,new_cmdbuf_node);
  1078. spin_unlock_irqrestore(dev->spinlock, flags);
  1079. vcmd_position[cmdbuf_obj->module_type]++;
  1080. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1081. vcmd_position[cmdbuf_obj->module_type]=0;
  1082. cmdbuf_obj->core_id = dev->core_id;
  1083. return 0;
  1084. }
  1085. else
  1086. {
  1087. spin_unlock_irqrestore(dev->spinlock, flags);
  1088. vcmd_position[cmdbuf_obj->module_type]++;
  1089. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1090. vcmd_position[cmdbuf_obj->module_type]=0;
  1091. counter++;
  1092. }
  1093. if(counter>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1094. break;
  1095. }
  1096. //there is no idle vcmd,if low priority,calculate exe time, select the least one.
  1097. // or if high priority, calculate the exe time, select the least one and abort it.
  1098. if(cmdbuf_obj->priority==CMDBUF_PRIORITY_NORMAL)
  1099. {
  1100. counter =0;
  1101. //calculate total execute time of all devices
  1102. while(1)
  1103. {
  1104. dev = vcmd_manager[cmdbuf_obj->module_type][vcmd_position[cmdbuf_obj->module_type]];
  1105. //read executing cmdbuf address
  1106. if(dev->hw_version_id <= HW_ID_1_0_C )
  1107. {
  1108. exe_cmdbuf_addr = VCMDGetAddrRegisterValue((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR);
  1109. list=&dev->list_manager;
  1110. spin_lock_irqsave(dev->spinlock, flags);
  1111. //get the executing cmdbuf node.
  1112. curr_cmdbuf_node=get_cmdbuf_node_in_list_by_addr(exe_cmdbuf_addr,list);
  1113. //calculate total execute time of this device
  1114. dev->total_exe_time=calculate_executing_time_after_node(curr_cmdbuf_node);
  1115. spin_unlock_irqrestore(dev->spinlock, flags);
  1116. }
  1117. else
  1118. {
  1119. //cmdbuf_id = vcmd_get_register_value((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_CMDBUF_EXECUTING_ID);
  1120. cmdbuf_id = *(dev->vcmd_reg_mem_virtualAddress+EXECUTING_CMDBUF_ID_ADDR+1);
  1121. spin_lock_irqsave(dev->spinlock, flags);
  1122. if(cmdbuf_id>=TOTAL_DISCRETE_CMDBUF_NUM||cmdbuf_id == 0)
  1123. {
  1124. pr_err("cmdbuf_id greater than the ceiling !!\n");
  1125. spin_unlock_irqrestore(dev->spinlock, flags);
  1126. return -1;
  1127. }
  1128. //get the executing cmdbuf node.
  1129. curr_cmdbuf_node=global_cmdbuf_node[cmdbuf_id];
  1130. if(curr_cmdbuf_node==NULL)
  1131. {
  1132. list=&dev->list_manager;
  1133. curr_cmdbuf_node = list->head;
  1134. while(1)
  1135. {
  1136. if(curr_cmdbuf_node == NULL)
  1137. break;
  1138. cmdbuf_obj_temp =(struct cmdbuf_obj*) curr_cmdbuf_node->data;
  1139. if(cmdbuf_obj_temp->cmdbuf_data_linked&&cmdbuf_obj_temp->cmdbuf_run_done==0)
  1140. break;
  1141. curr_cmdbuf_node = curr_cmdbuf_node->next;
  1142. }
  1143. }
  1144. //calculate total execute time of this device
  1145. dev->total_exe_time=calculate_executing_time_after_node(curr_cmdbuf_node);
  1146. spin_unlock_irqrestore(dev->spinlock, flags);
  1147. }
  1148. vcmd_position[cmdbuf_obj->module_type]++;
  1149. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1150. vcmd_position[cmdbuf_obj->module_type]=0;
  1151. counter++;
  1152. if(counter>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1153. break;
  1154. }
  1155. //find the device with the least total_exe_time.
  1156. counter =0;
  1157. executing_time=0xffffffff;
  1158. while(1)
  1159. {
  1160. dev = vcmd_manager[cmdbuf_obj->module_type][vcmd_position[cmdbuf_obj->module_type]];
  1161. if(dev->total_exe_time <= executing_time)
  1162. {
  1163. executing_time = dev->total_exe_time;
  1164. smallest_dev = dev;
  1165. }
  1166. vcmd_position[cmdbuf_obj->module_type]++;
  1167. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1168. vcmd_position[cmdbuf_obj->module_type]=0;
  1169. counter++;
  1170. if(counter>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1171. break;
  1172. }
  1173. //insert list
  1174. list = &smallest_dev->list_manager;
  1175. spin_lock_irqsave(smallest_dev->spinlock, flags);
  1176. bi_list_insert_node_tail(list,new_cmdbuf_node);
  1177. spin_unlock_irqrestore(smallest_dev->spinlock, flags);
  1178. cmdbuf_obj->core_id = smallest_dev->core_id;
  1179. return 0;
  1180. }
  1181. else
  1182. {
  1183. //CMDBUF_PRIORITY_HIGH
  1184. counter =0;
  1185. //calculate total execute time of all devices
  1186. while(1)
  1187. {
  1188. dev = vcmd_manager[cmdbuf_obj->module_type][vcmd_position[cmdbuf_obj->module_type]];
  1189. if(dev->hw_version_id <= HW_ID_1_0_C )
  1190. {
  1191. //read executing cmdbuf address
  1192. exe_cmdbuf_addr = VCMDGetAddrRegisterValue((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR);
  1193. list=&dev->list_manager;
  1194. spin_lock_irqsave(dev->spinlock, flags);
  1195. //get the executing cmdbuf node.
  1196. curr_cmdbuf_node=get_cmdbuf_node_in_list_by_addr(exe_cmdbuf_addr,list);
  1197. //calculate total execute time of this device
  1198. dev->total_exe_time=calculate_executing_time_after_node_high_priority(curr_cmdbuf_node);
  1199. spin_unlock_irqrestore(dev->spinlock, flags);
  1200. }
  1201. else
  1202. {
  1203. //cmdbuf_id = vcmd_get_register_value((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_CMDBUF_EXECUTING_ID);
  1204. cmdbuf_id = *(dev->vcmd_reg_mem_virtualAddress+EXECUTING_CMDBUF_ID_ADDR);
  1205. spin_lock_irqsave(dev->spinlock, flags);
  1206. if(cmdbuf_id>=TOTAL_DISCRETE_CMDBUF_NUM||cmdbuf_id == 0)
  1207. {
  1208. pr_err("cmdbuf_id greater than the ceiling !!\n");
  1209. spin_unlock_irqrestore(dev->spinlock, flags);
  1210. return -1;
  1211. }
  1212. //get the executing cmdbuf node.
  1213. curr_cmdbuf_node=global_cmdbuf_node[cmdbuf_id];
  1214. if(curr_cmdbuf_node==NULL)
  1215. {
  1216. list=&dev->list_manager;
  1217. curr_cmdbuf_node = list->head;
  1218. while(1)
  1219. {
  1220. if(curr_cmdbuf_node == NULL)
  1221. break;
  1222. cmdbuf_obj_temp =(struct cmdbuf_obj*) curr_cmdbuf_node->data;
  1223. if(cmdbuf_obj_temp->cmdbuf_data_linked&&cmdbuf_obj_temp->cmdbuf_run_done==0)
  1224. break;
  1225. curr_cmdbuf_node = curr_cmdbuf_node->next;
  1226. }
  1227. }
  1228. //calculate total execute time of this device
  1229. dev->total_exe_time=calculate_executing_time_after_node(curr_cmdbuf_node);
  1230. spin_unlock_irqrestore(dev->spinlock, flags);
  1231. }
  1232. vcmd_position[cmdbuf_obj->module_type]++;
  1233. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1234. vcmd_position[cmdbuf_obj->module_type]=0;
  1235. counter++;
  1236. if(counter>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1237. break;
  1238. }
  1239. //find the smallest device.
  1240. counter =0;
  1241. executing_time=0xffffffff;
  1242. while(1)
  1243. {
  1244. dev = vcmd_manager[cmdbuf_obj->module_type][vcmd_position[cmdbuf_obj->module_type]];
  1245. if(dev->total_exe_time <= executing_time)
  1246. {
  1247. executing_time = dev->total_exe_time;
  1248. smallest_dev = dev;
  1249. }
  1250. vcmd_position[cmdbuf_obj->module_type]++;
  1251. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1252. vcmd_position[cmdbuf_obj->module_type]=0;
  1253. counter++;
  1254. if(counter>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1255. break;
  1256. }
  1257. //abort the vcmd and wait
  1258. vcmd_write_register_value((const void *)smallest_dev->hwregs,smallest_dev->reg_mirror,HWIF_VCMD_START_TRIGGER,0);
  1259. software_triger_abort = 1;
  1260. if(wait_event_interruptible(*smallest_dev->wait_abort_queue, wait_abort_rdy(smallest_dev)) )
  1261. {
  1262. software_triger_abort = 0;
  1263. return -ERESTARTSYS;
  1264. }
  1265. software_triger_abort = 0;
  1266. //need to select inserting position again because hw maybe have run to the next node.
  1267. //CMDBUF_PRIORITY_HIGH
  1268. spin_lock_irqsave(smallest_dev->spinlock, flags);
  1269. curr_cmdbuf_node = smallest_dev->list_manager.head;
  1270. while(1)
  1271. {
  1272. //if list is empty or tail,insert to tail
  1273. if(curr_cmdbuf_node == NULL)
  1274. break;
  1275. cmdbuf_obj_temp= (struct cmdbuf_obj*)curr_cmdbuf_node->data;
  1276. //if find the first node which priority is normal, insert node prior to the node
  1277. if((cmdbuf_obj_temp->priority==CMDBUF_PRIORITY_NORMAL) && (cmdbuf_obj_temp->cmdbuf_run_done==0))
  1278. break;
  1279. curr_cmdbuf_node = curr_cmdbuf_node->next;
  1280. }
  1281. bi_list_insert_node_before(list,curr_cmdbuf_node,new_cmdbuf_node);
  1282. cmdbuf_obj->core_id = smallest_dev->core_id;
  1283. spin_unlock_irqrestore(smallest_dev->spinlock, flags);
  1284. return 0;
  1285. }
  1286. return 0;
  1287. }
  1288. static int wait_process_resource_rdy(struct process_manager_obj* process_manager_obj )
  1289. {
  1290. return process_manager_obj->total_exe_time<=PROCESS_MAX_SUM_OF_IMAGE_SIZE;
  1291. }
  1292. static long reserve_cmdbuf(struct file *filp,struct exchange_parameter* input_para)
  1293. {
  1294. bi_list_node* new_cmdbuf_node=NULL;
  1295. struct cmdbuf_obj* cmdbuf_obj=NULL;
  1296. bi_list_node* process_manager_node=NULL;
  1297. struct process_manager_obj* process_manager_obj=NULL;
  1298. unsigned long flags;
  1299. input_para->cmdbuf_id = 0;
  1300. if(input_para->cmdbuf_size>CMDBUF_MAX_SIZE)
  1301. {
  1302. return -1;
  1303. }
  1304. spin_lock_irqsave(&vcmd_process_manager_lock, flags);
  1305. process_manager_node = global_process_manager.head;
  1306. while(1)
  1307. {
  1308. if(process_manager_node == NULL)
  1309. {
  1310. //should not happen
  1311. pr_err("hantrovcmd: ERROR process_manager_node !!\n");
  1312. spin_unlock_irqrestore(&vcmd_process_manager_lock, flags);
  1313. return -1;
  1314. }
  1315. process_manager_obj = (struct process_manager_obj*)process_manager_node->data;
  1316. if (filp==process_manager_obj->filp)
  1317. {
  1318. break;
  1319. }
  1320. process_manager_node = process_manager_node->next;
  1321. }
  1322. spin_unlock_irqrestore(&vcmd_process_manager_lock, flags);
  1323. spin_lock_irqsave(&process_manager_obj->spinlock, flags);
  1324. process_manager_obj->total_exe_time += input_para->executing_time;
  1325. spin_unlock_irqrestore(&process_manager_obj->spinlock, flags);
  1326. if(wait_event_interruptible(process_manager_obj->wait_queue, wait_process_resource_rdy(process_manager_obj)))
  1327. return -1;
  1328. new_cmdbuf_node=create_cmdbuf_node();
  1329. if(new_cmdbuf_node==NULL)
  1330. return -1;
  1331. cmdbuf_obj = (struct cmdbuf_obj* )new_cmdbuf_node->data;
  1332. cmdbuf_obj->module_type = input_para->module_type;
  1333. cmdbuf_obj->priority = input_para->priority;
  1334. cmdbuf_obj->executing_time = input_para->executing_time;
  1335. cmdbuf_obj->cmdbuf_size = CMDBUF_MAX_SIZE;
  1336. input_para->cmdbuf_size =CMDBUF_MAX_SIZE;
  1337. cmdbuf_obj->filp = filp;
  1338. cmdbuf_obj->process_manager_obj =process_manager_obj;
  1339. input_para->cmdbuf_id=cmdbuf_obj->cmdbuf_id;
  1340. global_cmdbuf_node[input_para->cmdbuf_id] = new_cmdbuf_node;
  1341. return 0;
  1342. }
  1343. static long release_cmdbuf(struct file *filp,u16 cmdbuf_id)
  1344. {
  1345. struct cmdbuf_obj* cmdbuf_obj=NULL;
  1346. bi_list_node* last_cmdbuf_node=NULL;
  1347. bi_list_node* new_cmdbuf_node=NULL;
  1348. bi_list* list=NULL;
  1349. u32 module_type;
  1350. unsigned long flags;
  1351. struct hantrovcmd_dev* dev=NULL;
  1352. /*get cmdbuf object according to cmdbuf_id*/
  1353. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  1354. if(new_cmdbuf_node==NULL)
  1355. {
  1356. //should not happen
  1357. pr_err("hantrovcmd: ERROR cmdbuf_id !!\n");
  1358. return -1;
  1359. }
  1360. cmdbuf_obj=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  1361. if(cmdbuf_obj->filp!=filp)
  1362. {
  1363. //should not happen
  1364. pr_err("hantrovcmd: ERROR cmdbuf_id !!\n");
  1365. return -1;
  1366. }
  1367. module_type = cmdbuf_obj->module_type;
  1368. //TODO
  1369. if (down_interruptible(&vcmd_reserve_cmdbuf_sem[module_type]))
  1370. return -ERESTARTSYS;
  1371. dev = &hantrovcmd_data[cmdbuf_obj->core_id];
  1372. //spin_lock_irqsave(dev->spinlock, flags);
  1373. list=&dev->list_manager;
  1374. cmdbuf_obj->cmdbuf_need_remove=1;
  1375. last_cmdbuf_node = new_cmdbuf_node->previous;
  1376. while(1)
  1377. {
  1378. //remove current node
  1379. cmdbuf_obj=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  1380. if(cmdbuf_obj->cmdbuf_need_remove==1)
  1381. {
  1382. new_cmdbuf_node=remove_cmdbuf_node_from_list(list,new_cmdbuf_node);
  1383. if(new_cmdbuf_node)
  1384. {
  1385. //free node
  1386. global_cmdbuf_node[cmdbuf_obj->cmdbuf_id] = NULL;
  1387. if(cmdbuf_obj->process_manager_obj)
  1388. {
  1389. spin_lock_irqsave(&cmdbuf_obj->process_manager_obj->spinlock, flags);
  1390. cmdbuf_obj->process_manager_obj->total_exe_time -= cmdbuf_obj->executing_time;
  1391. spin_unlock_irqrestore(&cmdbuf_obj->process_manager_obj->spinlock, flags);
  1392. wake_up_interruptible_all(&cmdbuf_obj->process_manager_obj->wait_queue);
  1393. }
  1394. free_cmdbuf_node(new_cmdbuf_node);
  1395. }
  1396. }
  1397. if(last_cmdbuf_node==NULL)
  1398. break;
  1399. new_cmdbuf_node=last_cmdbuf_node;
  1400. last_cmdbuf_node=new_cmdbuf_node->previous;
  1401. }
  1402. //spin_unlock_irqrestore(dev->spinlock, flags);
  1403. up(&vcmd_reserve_cmdbuf_sem[module_type]);
  1404. return 0;
  1405. }
  1406. static long release_cmdbuf_node(bi_list* list,bi_list_node*cmdbuf_node)
  1407. {
  1408. bi_list_node* new_cmdbuf_node=NULL;
  1409. struct cmdbuf_obj* cmdbuf_obj=NULL;
  1410. /*get cmdbuf object according to cmdbuf_id*/
  1411. new_cmdbuf_node=cmdbuf_node;
  1412. if(new_cmdbuf_node==NULL)
  1413. return -1;
  1414. //remove node from list
  1415. new_cmdbuf_node=remove_cmdbuf_node_from_list(list,new_cmdbuf_node);
  1416. if(new_cmdbuf_node)
  1417. {
  1418. //free node
  1419. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  1420. global_cmdbuf_node[cmdbuf_obj->cmdbuf_id] = NULL;
  1421. free_cmdbuf_node(new_cmdbuf_node);
  1422. return 0;
  1423. }
  1424. return 1;
  1425. }
  1426. static long release_cmdbuf_node_cleanup(bi_list* list)
  1427. {
  1428. bi_list_node* new_cmdbuf_node=NULL;
  1429. struct cmdbuf_obj* cmdbuf_obj=NULL;
  1430. while(1)
  1431. {
  1432. new_cmdbuf_node=list->head;
  1433. if(new_cmdbuf_node==NULL)
  1434. return 0;
  1435. //remove node from list
  1436. bi_list_remove_node(list,new_cmdbuf_node);
  1437. //free node
  1438. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  1439. global_cmdbuf_node[cmdbuf_obj->cmdbuf_id] = NULL;
  1440. free_cmdbuf_node(new_cmdbuf_node);
  1441. }
  1442. return 0;
  1443. }
  1444. static bi_list_node* find_last_linked_cmdbuf(bi_list_node* current_node)
  1445. {
  1446. bi_list_node* new_cmdbuf_node=current_node;
  1447. bi_list_node* last_cmdbuf_node;
  1448. struct cmdbuf_obj* cmdbuf_obj=NULL;
  1449. if(current_node==NULL)
  1450. return NULL;
  1451. last_cmdbuf_node = new_cmdbuf_node;
  1452. new_cmdbuf_node = new_cmdbuf_node->previous;
  1453. while(1)
  1454. {
  1455. if(new_cmdbuf_node==NULL)
  1456. return last_cmdbuf_node;
  1457. cmdbuf_obj=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  1458. if(cmdbuf_obj->cmdbuf_data_linked)
  1459. {
  1460. return new_cmdbuf_node;
  1461. }
  1462. last_cmdbuf_node = new_cmdbuf_node;
  1463. new_cmdbuf_node = new_cmdbuf_node->previous;
  1464. }
  1465. return NULL;
  1466. }
  1467. static long link_and_run_cmdbuf(struct file *filp,struct exchange_parameter* input_para)
  1468. {
  1469. struct cmdbuf_obj* cmdbuf_obj=NULL;
  1470. bi_list_node* new_cmdbuf_node=NULL;
  1471. bi_list_node* last_cmdbuf_node;
  1472. u32* jmp_addr=NULL;
  1473. u32 opCode;
  1474. u32 tempOpcode;
  1475. u32 record_last_cmdbuf_rdy_num;
  1476. struct hantrovcmd_dev* dev=NULL;
  1477. unsigned long flags;
  1478. int return_value;
  1479. u16 cmdbuf_id=input_para->cmdbuf_id;
  1480. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  1481. if(new_cmdbuf_node==NULL)
  1482. {
  1483. //should not happen
  1484. pr_err("hantrovcmd: ERROR cmdbuf_id !!\n");
  1485. return -1;
  1486. }
  1487. cmdbuf_obj=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  1488. if(cmdbuf_obj->filp!=filp)
  1489. {
  1490. //should not happen
  1491. pr_err("hantrovcmd: ERROR cmdbuf_id !!\n");
  1492. return -1;
  1493. }
  1494. cmdbuf_obj->cmdbuf_data_loaded=1;
  1495. cmdbuf_obj->cmdbuf_size=input_para->cmdbuf_size;
  1496. #ifdef VCMD_DEBUG_INTERNAL
  1497. {
  1498. u32 i;
  1499. pr_info("vcmd link, current cmdbuf content\n");
  1500. for(i=0;i<cmdbuf_obj->cmdbuf_size/4;i++)
  1501. {
  1502. pr_info("current cmdbuf data %d =0x%x\n",i,*(cmdbuf_obj->cmdbuf_virtualAddress+i));
  1503. }
  1504. }
  1505. #endif
  1506. //test nop and end opcode, then assign value.
  1507. cmdbuf_obj->has_end_cmdbuf=0; //0: has jmp opcode,1 has end code
  1508. cmdbuf_obj->no_normal_int_cmdbuf=0; //0: interrupt when JMP,1 not interrupt when JMP
  1509. jmp_addr = cmdbuf_obj->cmdbuf_virtualAddress + (cmdbuf_obj->cmdbuf_size/4);
  1510. opCode=tempOpcode = *(jmp_addr-4);
  1511. opCode >>=27;
  1512. opCode <<=27;
  1513. //we can't identify END opcode or JMP opcode, so we don't support END opcode in control sw and driver.
  1514. if(opCode == OPCODE_JMP)
  1515. {
  1516. //jmp
  1517. opCode=tempOpcode;
  1518. opCode &=0x02000000;
  1519. if(opCode == JMP_IE_1)
  1520. {
  1521. cmdbuf_obj->no_normal_int_cmdbuf=0;
  1522. }
  1523. else
  1524. {
  1525. cmdbuf_obj->no_normal_int_cmdbuf=1;
  1526. }
  1527. }
  1528. else
  1529. {
  1530. //not support other opcode
  1531. return -1;
  1532. }
  1533. if (down_interruptible(&vcmd_reserve_cmdbuf_sem[cmdbuf_obj->module_type]))
  1534. return -ERESTARTSYS;
  1535. return_value=select_vcmd(new_cmdbuf_node);
  1536. if(return_value)
  1537. return return_value;
  1538. dev = &hantrovcmd_data[cmdbuf_obj->core_id];
  1539. input_para->core_id = cmdbuf_obj->core_id;
  1540. PDEBUG("Allocate cmd buffer [%d] to core [%d]\n", cmdbuf_id, input_para->core_id);
  1541. //set ddr address for vcmd registers copy.
  1542. if(dev->hw_version_id > HW_ID_1_0_C )
  1543. {
  1544. //read vcmd executing register into ddr memory.
  1545. //now core id is got and output ddr address of vcmd register can be filled in.
  1546. //each core has its own fixed output ddr address of vcmd registers.
  1547. jmp_addr = cmdbuf_obj->cmdbuf_virtualAddress;
  1548. if (mmu_enable) {
  1549. *(jmp_addr + 2) = 0;
  1550. *(jmp_addr+1) = (u32)((dev->mmu_vcmd_reg_mem_busAddress + (EXECUTING_CMDBUF_ID_ADDR+1)*4));
  1551. } else {
  1552. if(sizeof(size_t) == 8) {
  1553. *(jmp_addr + 2) = (u32)((u64)(dev->vcmd_reg_mem_busAddress + (EXECUTING_CMDBUF_ID_ADDR+1)*4)>>32);
  1554. } else {
  1555. *(jmp_addr + 2) = 0;
  1556. }
  1557. *(jmp_addr+1) = (u32)((dev->vcmd_reg_mem_busAddress + (EXECUTING_CMDBUF_ID_ADDR+1)*4));
  1558. }
  1559. jmp_addr = cmdbuf_obj->cmdbuf_virtualAddress + (cmdbuf_obj->cmdbuf_size/4);
  1560. //read vcmd all registers into ddr memory.
  1561. //now core id is got and output ddr address of vcmd registers can be filled in.
  1562. //each core has its own fixed output ddr address of vcmd registers.
  1563. if (mmu_enable) {
  1564. if(sizeof(size_t) == 8) {
  1565. *(jmp_addr-6) = 0;
  1566. }
  1567. *(jmp_addr-7) = (u32)(dev->mmu_vcmd_reg_mem_busAddress);
  1568. } else {
  1569. if(sizeof(size_t) == 8) {
  1570. *(jmp_addr-6) = (u32)((u64)dev->vcmd_reg_mem_busAddress>>32);
  1571. } else {
  1572. *(jmp_addr-6) = 0;
  1573. }
  1574. *(jmp_addr-7) = (u32)(dev->vcmd_reg_mem_busAddress);
  1575. }
  1576. }
  1577. //start to link and/or run
  1578. spin_lock_irqsave(dev->spinlock, flags);
  1579. last_cmdbuf_node = find_last_linked_cmdbuf(new_cmdbuf_node);
  1580. record_last_cmdbuf_rdy_num=dev->sw_cmdbuf_rdy_num;
  1581. vcmd_link_cmdbuf(dev,last_cmdbuf_node);
  1582. if(dev->working_state==WORKING_STATE_IDLE)
  1583. {
  1584. //run
  1585. while (last_cmdbuf_node &&
  1586. ((struct cmdbuf_obj*)last_cmdbuf_node->data)->cmdbuf_run_done)
  1587. last_cmdbuf_node = last_cmdbuf_node->next;
  1588. if (last_cmdbuf_node && last_cmdbuf_node->data) {
  1589. PDEBUG("vcmd start for cmdbuf id %d, cmdbuf_run_done = %d\n",
  1590. ((struct cmdbuf_obj*)last_cmdbuf_node->data)->cmdbuf_id,
  1591. ((struct cmdbuf_obj*)last_cmdbuf_node->data)->cmdbuf_run_done);
  1592. }
  1593. vcmd_start(dev,last_cmdbuf_node);
  1594. }
  1595. else
  1596. {
  1597. //just update cmdbuf ready number
  1598. if(record_last_cmdbuf_rdy_num!=dev->sw_cmdbuf_rdy_num)
  1599. vcmd_write_register_value((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_RDY_CMDBUF_COUNT,dev->sw_cmdbuf_rdy_num);
  1600. }
  1601. spin_unlock_irqrestore(dev->spinlock, flags);
  1602. up(&vcmd_reserve_cmdbuf_sem[cmdbuf_obj->module_type]);
  1603. return 0;
  1604. }
  1605. /******************************************************************************/
  1606. static int check_cmdbuf_irq(struct hantrovcmd_dev* dev,struct cmdbuf_obj* cmdbuf_obj,u32 *irq_status_ret)
  1607. {
  1608. int rdy = 0;
  1609. unsigned long flags;
  1610. spin_lock_irqsave(dev->spinlock, flags);
  1611. if(cmdbuf_obj->cmdbuf_run_done)
  1612. {
  1613. rdy = 1;
  1614. *irq_status_ret=cmdbuf_obj->executing_status;//need to decide how to assign this variable
  1615. }
  1616. spin_unlock_irqrestore(dev->spinlock, flags);
  1617. return rdy;
  1618. }
  1619. #ifdef IRQ_SIMULATION
  1620. static void get_random_bytes(void *buf, int nbytes);
  1621. #if 0
  1622. void hantrovcmd_trigger_irq_0(struct timer_list* timer)
  1623. {
  1624. PDEBUG("trigger core 0 irq\n");
  1625. del_timer(timer);
  1626. hantrovcmd_isr(0,(void *)&hantrovcmd_data[0]);
  1627. }
  1628. void hantrovcmd_trigger_irq_1(struct timer_list* timer)
  1629. {
  1630. PDEBUG("trigger core 1 irq\n");
  1631. del_timer(timer);
  1632. hantrovcmd_isr(0,(void *)&hantrovcmd_data[1]);
  1633. }
  1634. #else
  1635. static void hantrovcmd_trigger_irq(struct timer_list *timer)
  1636. {
  1637. u32 timer_id=0;
  1638. u32 core_id=0;
  1639. u32 i;
  1640. for(i=0;i<10000;i++)
  1641. {
  1642. if(timer_reserve[i].timer==timer)
  1643. {
  1644. timer_id=timer_reserve[i].timer_id;
  1645. core_id = timer_reserve[i].core_id;
  1646. break;
  1647. }
  1648. }
  1649. PDEBUG("trigger core 0 irq\n");
  1650. hantrovcmd_isr(core_id,(void *)&hantrovcmd_data[core_id]);
  1651. del_timer(timer);
  1652. timer_reserve[timer_id].timer=NULL;
  1653. }
  1654. #endif
  1655. #endif
  1656. static unsigned int wait_cmdbuf_ready(struct file *filp,u16 cmdbuf_id,u32 *irq_status_ret)
  1657. {
  1658. struct cmdbuf_obj* cmdbuf_obj=NULL;
  1659. bi_list_node* new_cmdbuf_node=NULL;
  1660. struct hantrovcmd_dev* dev=NULL;
  1661. PDEBUG("wait_cmdbuf_ready\n");
  1662. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  1663. if(new_cmdbuf_node==NULL)
  1664. {
  1665. //should not happen
  1666. pr_err("hantrovcmd: ERROR cmdbuf_id !!\n");
  1667. return -1;
  1668. }
  1669. cmdbuf_obj=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  1670. if(cmdbuf_obj->filp!=filp)
  1671. {
  1672. //should not happen
  1673. pr_err("hantrovcmd: ERROR cmdbuf_id !!\n");
  1674. return -1;
  1675. }
  1676. dev = &hantrovcmd_data[cmdbuf_obj->core_id];
  1677. #ifdef IRQ_SIMULATION
  1678. {
  1679. u32 random_num;
  1680. //get_random_bytes(&random_num, sizeof(u32));
  1681. random_num = (u32)((u64)100*cmdbuf_obj->executing_time/(4096*2160)+50);
  1682. PDEBUG("random_num=%d\n",random_num);
  1683. #if 0
  1684. /*init a timer to trigger irq*/
  1685. if (cmdbuf_obj->core_id==0)
  1686. {
  1687. //init_timer(&timer0);
  1688. //timer0.function = hantrovcmd_trigger_irq_0;
  1689. timer_setup(&timer0,hantrovcmd_trigger_irq_0,0);
  1690. timer0.expires = jiffies + random_num*HZ/10; //the expires time is 1s
  1691. add_timer(&timer0);
  1692. }
  1693. if (cmdbuf_obj->core_id==1)
  1694. {
  1695. //init_timer(&timer1);
  1696. //timer1.function = hantrovcmd_trigger_irq_1;
  1697. timer_setup(&timer1,hantrovcmd_trigger_irq_1,0);
  1698. timer1.expires = jiffies + random_num*HZ/10; //the expires time is 1s
  1699. add_timer(&timer1);
  1700. }
  1701. #else
  1702. {
  1703. u32 i;
  1704. struct timer_list *temp_timer=NULL;
  1705. for(i=0;i<10000;i++)
  1706. {
  1707. if(timer_reserve[i].timer==NULL)
  1708. {
  1709. timer_reserve[i].timer_id=i;
  1710. timer_reserve[i].core_id=cmdbuf_obj->core_id;
  1711. temp_timer=timer_reserve[i].timer =&timer[i] ;
  1712. break;
  1713. }
  1714. }
  1715. //if (cmdbuf_obj->core_id==0)
  1716. {
  1717. //init_timer(&timer0);
  1718. //timer0.function = hantrovcmd_trigger_irq_0;
  1719. timer_setup(temp_timer,hantrovcmd_trigger_irq,0);
  1720. temp_timer->expires = jiffies + random_num*HZ/10; //the expires time is 1s
  1721. add_timer(temp_timer);
  1722. }
  1723. }
  1724. #endif
  1725. }
  1726. #endif
  1727. if(wait_event_interruptible(*dev->wait_queue, check_cmdbuf_irq(dev,cmdbuf_obj,irq_status_ret)))
  1728. {
  1729. PDEBUG("vcmd_wait_queue_0 interrupted\n");
  1730. //abort the vcmd
  1731. vcmd_write_register_value((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_START_TRIGGER,0);
  1732. return -ERESTARTSYS;
  1733. }
  1734. return 0;
  1735. }
  1736. static long hantrovcmd_ioctl(struct file *filp,
  1737. unsigned int cmd, unsigned long arg)
  1738. {
  1739. int err = 0;
  1740. struct device *dev = &hantrovcmd_data->pdev->dev;
  1741. struct process_manager_obj* process_manager_obj=NULL;
  1742. PDEBUG("ioctl cmd 0x%08x\n", cmd);
  1743. /*
  1744. * extract the type and number bitfields, and don't encode
  1745. * wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok()
  1746. */
  1747. if(_IOC_TYPE(cmd) != HANTRO_IOC_MAGIC
  1748. #ifdef HANTROMMU_SUPPORT
  1749. && _IOC_TYPE(cmd) != HANTRO_IOC_MMU
  1750. #endif
  1751. )
  1752. return -ENOTTY;
  1753. if((_IOC_TYPE(cmd) == HANTRO_IOC_MAGIC &&
  1754. _IOC_NR(cmd) > HANTRO_IOC_MAXNR)
  1755. #ifdef HANTROMMU_SUPPORT
  1756. ||(_IOC_TYPE(cmd) == HANTRO_IOC_MMU &&
  1757. _IOC_NR(cmd) > HANTRO_IOC_MMU_MAXNR)
  1758. #endif
  1759. )
  1760. return -ENOTTY;
  1761. /*
  1762. * the direction is a bitmask, and VERIFY_WRITE catches R/W
  1763. * transfers. `Type' is user-oriented, while
  1764. * access_ok is kernel-oriented, so the concept of "read" and
  1765. * "write" is reversed
  1766. */
  1767. if(_IOC_DIR(cmd) & _IOC_READ)
  1768. #if KERNEL_VERSION(5,0,0) <= LINUX_VERSION_CODE
  1769. err = !access_ok((void *) arg, _IOC_SIZE(cmd));
  1770. #else
  1771. err = !access_ok(VERIFY_WRITE, (void *) arg, _IOC_SIZE(cmd));
  1772. #endif
  1773. else if(_IOC_DIR(cmd) & _IOC_WRITE)
  1774. #if KERNEL_VERSION(5,0,0) <= LINUX_VERSION_CODE
  1775. err = !access_ok((void *) arg, _IOC_SIZE(cmd));
  1776. #else
  1777. err = !access_ok(VERIFY_READ, (void *) arg, _IOC_SIZE(cmd));
  1778. #endif
  1779. if(err)
  1780. return -EFAULT;
  1781. process_manager_obj = (struct process_manager_obj*)filp->private_data;
  1782. switch (cmd)
  1783. {
  1784. case HANTRO_IOCH_GET_VCMD_ENABLE:
  1785. {
  1786. __put_user(1, (unsigned long *) arg);
  1787. break;
  1788. }
  1789. case HANTRO_IOCH_GET_CMDBUF_PARAMETER:
  1790. {
  1791. struct cmdbuf_mem_parameter local_cmdbuf_mem_data;
  1792. PDEBUG(" VCMD GET_CMDBUF_PARAMETER\n");
  1793. local_cmdbuf_mem_data.cmdbuf_unit_size = CMDBUF_MAX_SIZE;
  1794. local_cmdbuf_mem_data.status_cmdbuf_unit_size = CMDBUF_MAX_SIZE;
  1795. local_cmdbuf_mem_data.cmdbuf_total_size = CMDBUF_POOL_TOTAL_SIZE;
  1796. local_cmdbuf_mem_data.status_cmdbuf_total_size = CMDBUF_POOL_TOTAL_SIZE;
  1797. local_cmdbuf_mem_data.phy_status_cmdbuf_addr = vcmd_status_buf_mem_pool.busAddress;
  1798. local_cmdbuf_mem_data.phy_cmdbuf_addr = vcmd_buf_mem_pool.busAddress;
  1799. if (mmu_enable) {
  1800. local_cmdbuf_mem_data.mmu_phy_status_cmdbuf_addr = vcmd_status_buf_mem_pool.mmu_bus_address;
  1801. local_cmdbuf_mem_data.mmu_phy_cmdbuf_addr = vcmd_buf_mem_pool.mmu_bus_address;
  1802. } else {
  1803. local_cmdbuf_mem_data.mmu_phy_status_cmdbuf_addr = 0;
  1804. local_cmdbuf_mem_data.mmu_phy_cmdbuf_addr = 0;
  1805. }
  1806. local_cmdbuf_mem_data.base_ddr_addr = base_ddr_addr;
  1807. copy_to_user((struct cmdbuf_mem_parameter*)arg,&local_cmdbuf_mem_data,sizeof(struct cmdbuf_mem_parameter));
  1808. break;
  1809. }
  1810. case HANTRO_IOCH_GET_VCMD_PARAMETER:
  1811. {
  1812. struct config_parameter input_para;
  1813. PDEBUG(" VCMD get vcmd config parameter \n");
  1814. copy_from_user(&input_para,(struct config_parameter*)arg,sizeof(struct config_parameter));
  1815. if(vcmd_type_core_num[input_para.module_type])
  1816. {
  1817. input_para.submodule_main_addr = vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_main_addr;
  1818. input_para.submodule_dec400_addr = vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_dec400_addr;
  1819. input_para.submodule_L2Cache_addr = vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_L2Cache_addr;
  1820. input_para.submodule_MMU_addr[0] = vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_MMU_addr[0];
  1821. input_para.submodule_MMU_addr[1] = vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_MMU_addr[1];
  1822. input_para.submodule_axife_addr[0] = vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_axife_addr[0];
  1823. input_para.submodule_axife_addr[1] = vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_axife_addr[1];
  1824. input_para.config_status_cmdbuf_id = vcmd_manager[input_para.module_type][0]->status_cmdbuf_id;
  1825. input_para.vcmd_hw_version_id = vcmd_manager[input_para.module_type][0]->hw_version_id;
  1826. input_para.vcmd_core_num = vcmd_type_core_num[input_para.module_type];
  1827. }
  1828. else
  1829. {
  1830. input_para.submodule_main_addr = 0xffff;
  1831. input_para.submodule_dec400_addr = 0xffff;
  1832. input_para.submodule_L2Cache_addr = 0xffff;
  1833. input_para.submodule_MMU_addr[0] = 0xffff;
  1834. input_para.submodule_MMU_addr[1] = 0xffff;
  1835. input_para.submodule_axife_addr[0] = 0xffff;
  1836. input_para.submodule_axife_addr[1] = 0xffff;
  1837. input_para.config_status_cmdbuf_id = 0;
  1838. input_para.vcmd_core_num = 0;
  1839. input_para.vcmd_hw_version_id =HW_ID_1_0_C;
  1840. }
  1841. copy_to_user((struct config_parameter*)arg,&input_para,sizeof(struct config_parameter));
  1842. break;
  1843. }
  1844. case HANTRO_IOCH_RESERVE_CMDBUF:
  1845. {
  1846. int ret;
  1847. struct exchange_parameter input_para;
  1848. copy_from_user(&input_para,(struct exchange_parameter*)arg,sizeof(struct exchange_parameter));
  1849. ret = reserve_cmdbuf(filp,&input_para);
  1850. if (ret == 0)
  1851. copy_to_user((struct exchange_parameter*)arg,&input_para,sizeof(struct exchange_parameter));
  1852. PDEBUG(" VCMD Reserve CMDBUF %d\n", input_para.cmdbuf_id);
  1853. return ret;
  1854. }
  1855. case HANTRO_IOCH_LINK_RUN_CMDBUF:
  1856. {
  1857. struct exchange_parameter input_para;
  1858. long retVal;
  1859. copy_from_user(&input_para,(struct exchange_parameter*)arg,sizeof(struct exchange_parameter));
  1860. PDEBUG("VCMD link and run cmdbuf\n");
  1861. pm_runtime_resume_and_get(dev);
  1862. if (process_manager_obj)
  1863. process_manager_obj->pm_count++;
  1864. retVal = link_and_run_cmdbuf(filp,&input_para);
  1865. copy_to_user((struct exchange_parameter*)arg,&input_para,sizeof(struct exchange_parameter));
  1866. return retVal;
  1867. break;
  1868. }
  1869. case HANTRO_IOCH_WAIT_CMDBUF:
  1870. {
  1871. u16 cmdbuf_id;
  1872. unsigned int tmp;
  1873. u32 irq_status_ret=0;
  1874. __get_user(cmdbuf_id, (u16*)arg);
  1875. /*high 16 bits are core id, low 16 bits are cmdbuf_id*/
  1876. PDEBUG("VCMD wait for CMDBUF finishing. \n");
  1877. //TODO
  1878. tmp = wait_cmdbuf_ready(filp,cmdbuf_id,&irq_status_ret);
  1879. cmdbuf_id=(u16)irq_status_ret;
  1880. if (tmp==0)
  1881. {
  1882. __put_user(cmdbuf_id, (u16 *)arg);
  1883. return tmp;//return core_id
  1884. }
  1885. else
  1886. {
  1887. return -1;
  1888. }
  1889. break;
  1890. }
  1891. case HANTRO_IOCH_RELEASE_CMDBUF:
  1892. {
  1893. u16 cmdbuf_id;
  1894. __get_user(cmdbuf_id, (u16*)arg);
  1895. /*16 bits are cmdbuf_id*/
  1896. PDEBUG("VCMD release CMDBUF\n");
  1897. pm_runtime_mark_last_busy(dev);
  1898. pm_runtime_put_autosuspend(dev);
  1899. if (process_manager_obj)
  1900. process_manager_obj->pm_count--;
  1901. release_cmdbuf(filp,cmdbuf_id);
  1902. return 0;
  1903. break;
  1904. }
  1905. case HANTRO_IOCH_POLLING_CMDBUF:
  1906. {
  1907. u16 core_id;
  1908. __get_user(core_id, (u16*)arg);
  1909. /*16 bits are cmdbuf_id*/
  1910. if(core_id>=total_vcmd_core_num)
  1911. return -1;
  1912. hantrovcmd_isr(core_id,&hantrovcmd_data[core_id]);
  1913. return 0;
  1914. break;
  1915. }
  1916. default:
  1917. {
  1918. #ifdef HANTROMMU_SUPPORT
  1919. if(_IOC_TYPE(cmd) == HANTRO_IOC_MMU)
  1920. {
  1921. pm_runtime_resume_and_get(dev);
  1922. long retval = MMUIoctl(cmd, filp, arg, mmu_hwregs);
  1923. pm_runtime_mark_last_busy(dev);
  1924. pm_runtime_put_autosuspend(dev);
  1925. return retval;
  1926. }
  1927. #endif
  1928. }
  1929. }
  1930. return 0;
  1931. }
  1932. /**********************************************************************************************************\
  1933. *process manager object management
  1934. \***********************************************************************************************************/
  1935. static struct process_manager_obj* create_process_manager_obj(void)
  1936. {
  1937. struct process_manager_obj* process_manager_obj=NULL;
  1938. process_manager_obj=vmalloc(sizeof(struct process_manager_obj));
  1939. if(process_manager_obj==NULL)
  1940. {
  1941. PDEBUG ("%s\n","vmalloc for process_manager_obj fail!");
  1942. return process_manager_obj;
  1943. }
  1944. memset(process_manager_obj,0,sizeof(struct process_manager_obj));
  1945. return process_manager_obj;
  1946. }
  1947. static void free_process_manager_obj( struct process_manager_obj* process_manager_obj)
  1948. {
  1949. if(process_manager_obj==NULL)
  1950. {
  1951. PDEBUG ("%s\n","free_process_manager_obj NULL");
  1952. return;
  1953. }
  1954. //free current cmdbuf_obj
  1955. vfree(process_manager_obj);
  1956. return;
  1957. }
  1958. static bi_list_node* create_process_manager_node(void)
  1959. {
  1960. bi_list_node* current_node=NULL;
  1961. struct process_manager_obj* process_manager_obj=NULL;
  1962. process_manager_obj=create_process_manager_obj();
  1963. if(process_manager_obj==NULL)
  1964. {
  1965. PDEBUG ("%s\n","create_process_manager_obj fail!");
  1966. return NULL;
  1967. }
  1968. process_manager_obj->total_exe_time = 0;
  1969. process_manager_obj->pm_count = 0;
  1970. spin_lock_init(&process_manager_obj->spinlock);
  1971. init_waitqueue_head(&process_manager_obj->wait_queue);
  1972. current_node=bi_list_create_node();
  1973. if(current_node==NULL)
  1974. {
  1975. PDEBUG ("%s\n","bi_list_create_node fail!");
  1976. free_process_manager_obj(process_manager_obj);
  1977. return NULL;
  1978. }
  1979. current_node->data = (void*)process_manager_obj;
  1980. return current_node;
  1981. }
  1982. static void free_process_manager_node(bi_list_node* process_node)
  1983. {
  1984. struct process_manager_obj* process_manager_obj=NULL;
  1985. if(process_node==NULL)
  1986. {
  1987. PDEBUG ("%s\n","free_process_manager_node NULL");
  1988. return;
  1989. }
  1990. process_manager_obj = (struct process_manager_obj*)process_node->data;
  1991. //free struct process_manager_obj
  1992. free_process_manager_obj (process_manager_obj);
  1993. //free current process_manager_obj entity.
  1994. bi_list_free_node(process_node);
  1995. return;
  1996. }
  1997. static long release_process_node_cleanup(bi_list* list)
  1998. {
  1999. bi_list_node* new_process_node=NULL;
  2000. while(1)
  2001. {
  2002. new_process_node=list->head;
  2003. if(new_process_node==NULL)
  2004. break;
  2005. //remove node from list
  2006. bi_list_remove_node(list,new_process_node);
  2007. //remove node from list
  2008. free_process_manager_node(new_process_node);
  2009. }
  2010. return 0;
  2011. }
  2012. static void create_kernel_process_manager(void)
  2013. {
  2014. bi_list_node* process_manager_node;
  2015. struct process_manager_obj* process_manager_obj=NULL;
  2016. process_manager_node = create_process_manager_node();
  2017. process_manager_obj = (struct process_manager_obj*)process_manager_node->data;
  2018. process_manager_obj->filp = NULL;
  2019. bi_list_insert_node_tail(&global_process_manager,process_manager_node);
  2020. }
  2021. /* Update the last JMP cmd in cmdbuf_ojb in order to jump to next_cmdbuf_obj. */
  2022. static void cmdbuf_update_jmp_cmd(int hw_version_id,
  2023. struct cmdbuf_obj *cmdbuf_obj,
  2024. struct cmdbuf_obj *next_cmdbuf_obj,
  2025. int jmp_IE_1) {
  2026. u32 *jmp_addr;
  2027. u32 operation_code;
  2028. if(!cmdbuf_obj)
  2029. return;
  2030. if(cmdbuf_obj->has_end_cmdbuf==0)
  2031. {
  2032. //need to link, current cmdbuf link to next cmdbuf
  2033. jmp_addr = cmdbuf_obj->cmdbuf_virtualAddress + (cmdbuf_obj->cmdbuf_size/4);
  2034. if (!next_cmdbuf_obj) {
  2035. operation_code = *(jmp_addr-4);
  2036. operation_code >>=16;
  2037. operation_code <<=16;
  2038. *(jmp_addr-4)=(u32)(operation_code & ~JMP_RDY_1);
  2039. } else {
  2040. if(hw_version_id > HW_ID_1_0_C )
  2041. {
  2042. //set next cmdbuf id
  2043. *(jmp_addr-1) = next_cmdbuf_obj->cmdbuf_id;
  2044. }
  2045. if (mmu_enable) {
  2046. if(sizeof(size_t) == 8) {
  2047. *(jmp_addr-2)=(u32)((u64)(next_cmdbuf_obj->mmu_cmdbuf_busAddress)>>32);
  2048. } else {
  2049. *(jmp_addr-2)=0;
  2050. }
  2051. *(jmp_addr-3)=(u32)(next_cmdbuf_obj->mmu_cmdbuf_busAddress);
  2052. } else {
  2053. if(sizeof(size_t) == 8) {
  2054. *(jmp_addr-2)=(u32)((u64)(next_cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr)>>32);
  2055. } else {
  2056. *(jmp_addr-2)=0;
  2057. }
  2058. *(jmp_addr-3)=(u32)(next_cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr);
  2059. }
  2060. operation_code = *(jmp_addr-4);
  2061. operation_code >>=16;
  2062. operation_code <<=16;
  2063. *(jmp_addr-4)=(u32)(operation_code |JMP_RDY_1|jmp_IE_1|((next_cmdbuf_obj->cmdbuf_size+7)/8));
  2064. }
  2065. #ifdef VCMD_DEBUG_INTERNAL
  2066. {
  2067. u32 i;
  2068. pr_info("vcmd link, last cmdbuf content\n");
  2069. for(i=cmdbuf_obj->cmdbuf_size/4 -8;i<cmdbuf_obj->cmdbuf_size/4;i++)
  2070. {
  2071. pr_info("current linked cmdbuf data %d =0x%x\n",i,*(cmdbuf_obj->cmdbuf_virtualAddress+i));
  2072. }
  2073. }
  2074. #endif
  2075. }
  2076. }
  2077. /* delink given cmd buffer (cmdbuf_node) and remove it from list.
  2078. Also modify the last JMP of buf P to point to cmdbuf N.
  2079. Used when a process is terminated but there are pending cmd bufs in vmcd list.
  2080. E.g.,
  2081. before:
  2082. L->L->...->P->X->N-> ... ->L
  2083. ^ ^ ^
  2084. head cmdbuf_node tail
  2085. end:
  2086. L->L->...->P->N-> ... ->L
  2087. ^ ^
  2088. head tail
  2089. Return: pointer to N or NULL if N doesn't exist.
  2090. */
  2091. void vcmd_delink_rm_cmdbuf(struct hantrovcmd_dev *dev, bi_list_node* cmdbuf_node)
  2092. {
  2093. bi_list *list = &dev->list_manager;
  2094. struct cmdbuf_obj* cmdbuf_obj = (struct cmdbuf_obj*)cmdbuf_node->data;
  2095. bi_list_node* prev = cmdbuf_node->previous;
  2096. bi_list_node* next = cmdbuf_node->next;
  2097. PDEBUG("Delink and remove cmdbuf [%d] from vcmd list.\n", cmdbuf_obj->cmdbuf_id);
  2098. if (prev) {
  2099. PDEBUG("prev cmdbuf [%d].\n", ((struct cmdbuf_obj*)prev->data)->cmdbuf_id);
  2100. } else {
  2101. PDEBUG("NO prev cmdbuf.\n");
  2102. }
  2103. if (next) {
  2104. PDEBUG("next cmdbuf [%d].\n", ((struct cmdbuf_obj*)next->data)->cmdbuf_id);
  2105. } else {
  2106. PDEBUG("NO next cmdbuf.\n");
  2107. }
  2108. bi_list_remove_node(list, cmdbuf_node);
  2109. global_cmdbuf_node[cmdbuf_obj->cmdbuf_id] = NULL;
  2110. free_cmdbuf_node(cmdbuf_node);
  2111. cmdbuf_update_jmp_cmd(dev->hw_version_id, prev ? prev->data : NULL, next ? next->data : NULL,
  2112. dev->duration_without_int > INT_MIN_SUM_OF_IMAGE_SIZE);
  2113. }
  2114. static int hantrovcmd_open(struct inode *inode, struct file *filp)
  2115. {
  2116. int result = 0;
  2117. struct hantrovcmd_dev *dev = hantrovcmd_data;
  2118. bi_list_node* process_manager_node;
  2119. unsigned long flags;
  2120. struct process_manager_obj* process_manager_obj=NULL;
  2121. filp->private_data = NULL;
  2122. process_manager_node = create_process_manager_node();
  2123. if(process_manager_node== NULL)
  2124. return -1;
  2125. process_manager_obj = (struct process_manager_obj*)process_manager_node->data;
  2126. process_manager_obj->filp = filp;
  2127. spin_lock_irqsave(&vcmd_process_manager_lock, flags);
  2128. bi_list_insert_node_tail(&global_process_manager,process_manager_node);
  2129. spin_unlock_irqrestore(&vcmd_process_manager_lock, flags);
  2130. filp->private_data = process_manager_node->data;
  2131. PDEBUG("dev opened\n");
  2132. return result;
  2133. }
  2134. static int hantrovcmd_release(struct inode *inode, struct file *filp)
  2135. {
  2136. struct hantrovcmd_dev *dev = hantrovcmd_data;
  2137. u32 core_id = 0;
  2138. u32 release_cmdbuf_num=0;
  2139. bi_list_node* new_cmdbuf_node=NULL;
  2140. struct cmdbuf_obj* cmdbuf_obj_temp=NULL;
  2141. bi_list_node* process_manager_node;
  2142. struct process_manager_obj* process_manager_obj=NULL;
  2143. int vcmd_aborted = 0; // vcmd is aborted in this function
  2144. struct cmdbuf_obj* restart_cmdbuf = NULL;
  2145. unsigned long flags;
  2146. long retVal=0;
  2147. PDEBUG("dev closed for process %p\n", (void *)filp);
  2148. if (down_interruptible(&vcmd_reserve_cmdbuf_sem[dev->vcmd_core_cfg.sub_module_type]))
  2149. return -ERESTARTSYS;
  2150. for (core_id = 0;core_id < total_vcmd_core_num; core_id++)
  2151. {
  2152. if((&dev[core_id])==NULL)
  2153. continue;
  2154. spin_lock_irqsave(dev[core_id].spinlock, flags);
  2155. new_cmdbuf_node=dev[core_id].list_manager.head;
  2156. while(1)
  2157. {
  2158. if(new_cmdbuf_node==NULL)
  2159. break;
  2160. cmdbuf_obj_temp=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  2161. if (dev[core_id].hwregs && (cmdbuf_obj_temp->filp == filp))
  2162. {
  2163. if(cmdbuf_obj_temp->cmdbuf_run_done)
  2164. {
  2165. cmdbuf_obj_temp->cmdbuf_need_remove=1;
  2166. retVal=release_cmdbuf_node(&dev[core_id].list_manager,new_cmdbuf_node);
  2167. if(retVal==1)
  2168. cmdbuf_obj_temp->process_manager_obj = NULL;
  2169. }
  2170. else if(cmdbuf_obj_temp->cmdbuf_data_linked==0)
  2171. {
  2172. cmdbuf_obj_temp->cmdbuf_data_linked = 1;
  2173. cmdbuf_obj_temp->cmdbuf_run_done=1;
  2174. cmdbuf_obj_temp->cmdbuf_need_remove=1;
  2175. retVal=release_cmdbuf_node(&dev[core_id].list_manager,new_cmdbuf_node);
  2176. if(retVal==1)
  2177. cmdbuf_obj_temp->process_manager_obj = NULL;
  2178. }
  2179. else if(cmdbuf_obj_temp->cmdbuf_data_linked==1 && dev[core_id].working_state==WORKING_STATE_IDLE)
  2180. {
  2181. vcmd_delink_rm_cmdbuf(&dev[core_id], new_cmdbuf_node);
  2182. if(restart_cmdbuf == cmdbuf_obj_temp)
  2183. restart_cmdbuf = new_cmdbuf_node->next ? new_cmdbuf_node->next->data : NULL;
  2184. }
  2185. else if(cmdbuf_obj_temp->cmdbuf_data_linked==1 && dev[core_id].working_state==WORKING_STATE_WORKING)
  2186. {
  2187. bi_list_node* last_cmdbuf_node = NULL;
  2188. bi_list_node* done_cmdbuf_node = NULL;
  2189. int abort_cmdbuf_id;
  2190. int loop_count = 0;
  2191. //abort the vcmd and wait
  2192. PDEBUG("Abort due to linked cmdbuf %d of current process.\n", cmdbuf_obj_temp->cmdbuf_id);
  2193. #ifdef VCMD_DEBUG_INTERNAL
  2194. printk_vcmd_register_debug((const void *)dev[core_id].hwregs, "Before trigger to 0");
  2195. #endif
  2196. // disable abort interrupt
  2197. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_START_TRIGGER,0);
  2198. vcmd_aborted = 1;
  2199. software_triger_abort = 1;
  2200. #ifdef VCMD_DEBUG_INTERNAL
  2201. printk_vcmd_register_debug((const void *)dev[core_id].hwregs,"After trigger to 0");
  2202. #endif
  2203. // wait vcmd core aborted and vcmd enters IDLE mode.
  2204. while (vcmd_get_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_WORK_STATE)) {
  2205. loop_count++;
  2206. if (!(loop_count % 10)) {
  2207. u32 irq_status = vcmd_read_reg((const void *)dev[core_id].hwregs, VCMD_REGISTER_INT_STATUS_OFFSET);
  2208. pr_err("hantrovcmd: expected idle state, but irq status = 0x%0x\n", irq_status);
  2209. pr_err("hantrovcmd: vcmd current status is %d\n", vcmd_get_register_value((const void *)dev[core_id].hwregs, dev[core_id].reg_mirror, HWIF_VCMD_WORK_STATE));
  2210. }
  2211. mdelay(10); // wait 10ms
  2212. if (loop_count > 100) { // too long
  2213. pr_err("hantrovcmd: too long before vcmd core to IDLE state\n");
  2214. process_manager_obj = (struct process_manager_obj*)filp->private_data;
  2215. if (process_manager_obj)
  2216. {
  2217. while(process_manager_obj->pm_count > 0)
  2218. {
  2219. pm_runtime_mark_last_busy(&dev[0].pdev->dev);
  2220. pm_runtime_put_autosuspend(&dev[0].pdev->dev);
  2221. process_manager_obj->pm_count--;
  2222. }
  2223. }
  2224. spin_unlock_irqrestore(dev[core_id].spinlock, flags);
  2225. up(&vcmd_reserve_cmdbuf_sem[dev->vcmd_core_cfg.sub_module_type]);
  2226. return -ERESTARTSYS;
  2227. }
  2228. }
  2229. dev[core_id].working_state = WORKING_STATE_IDLE;
  2230. // clear interrupt & restore abort_e
  2231. if (vcmd_get_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_IRQ_ABORT)) {
  2232. PDEBUG("Abort interrupt triggered, now clear it to avoid abort int...\n");
  2233. vcmd_write_reg((const void *)dev[core_id].hwregs, VCMD_REGISTER_INT_STATUS_OFFSET, 0x1<<4);
  2234. PDEBUG("Now irq status = 0x%0x.\n", vcmd_read_reg((const void *)dev[core_id].hwregs, VCMD_REGISTER_INT_STATUS_OFFSET));
  2235. }
  2236. abort_cmdbuf_id = vcmd_get_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_CMDBUF_EXECUTING_ID);
  2237. PDEBUG("Abort when executing cmd buf %d.\n", abort_cmdbuf_id);
  2238. dev[core_id].sw_cmdbuf_rdy_num = 0;
  2239. dev[core_id].duration_without_int = 0;
  2240. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_EXE_CMDBUF_COUNT,0);
  2241. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_RDY_CMDBUF_COUNT,0);
  2242. /* Mark cmdbuf_run_done to 1 for all the cmd buf executed. */
  2243. done_cmdbuf_node = dev[core_id].list_manager.head;
  2244. while (done_cmdbuf_node) {
  2245. if (!((struct cmdbuf_obj*)done_cmdbuf_node->data)->cmdbuf_run_done) {
  2246. ((struct cmdbuf_obj*)done_cmdbuf_node->data)->cmdbuf_run_done = 1;
  2247. ((struct cmdbuf_obj*)done_cmdbuf_node->data)->cmdbuf_data_linked = 0;
  2248. PDEBUG("Set cmdbuf [%d] cmdbuf_run_done to 1.\n", ((struct cmdbuf_obj*)done_cmdbuf_node->data)->cmdbuf_id);
  2249. }
  2250. if (((struct cmdbuf_obj*)done_cmdbuf_node->data)->cmdbuf_id == abort_cmdbuf_id)
  2251. break;
  2252. done_cmdbuf_node = done_cmdbuf_node->next;
  2253. }
  2254. if (cmdbuf_obj_temp->cmdbuf_run_done) {
  2255. /* current cmdbuf is in fact has been executed, but due to interrupt is not triggered, the status is not updated.
  2256. Just delink and remove it from the list. */
  2257. if (done_cmdbuf_node && done_cmdbuf_node->data) {
  2258. PDEBUG("done_cmdbuf_node is cmdbuf [%d].\n", ((struct cmdbuf_obj*)done_cmdbuf_node->data)->cmdbuf_id);
  2259. }
  2260. done_cmdbuf_node = done_cmdbuf_node->next;
  2261. if (done_cmdbuf_node)
  2262. restart_cmdbuf = (struct cmdbuf_obj*)done_cmdbuf_node->data;
  2263. if (restart_cmdbuf) {
  2264. PDEBUG("Set restart cmdbuf [%d] via if.\n", restart_cmdbuf->cmdbuf_id);
  2265. }
  2266. } else {
  2267. last_cmdbuf_node = new_cmdbuf_node;
  2268. /* cmd buf num from aborted cmd buf to current cmdbuf_obj_temp */
  2269. if (cmdbuf_obj_temp->cmdbuf_id != abort_cmdbuf_id) {
  2270. last_cmdbuf_node = new_cmdbuf_node->previous;
  2271. while (last_cmdbuf_node &&
  2272. ((struct cmdbuf_obj*)last_cmdbuf_node->data)->cmdbuf_id != abort_cmdbuf_id) {
  2273. restart_cmdbuf = (struct cmdbuf_obj*)last_cmdbuf_node->data;
  2274. last_cmdbuf_node = last_cmdbuf_node->previous;
  2275. dev[core_id].sw_cmdbuf_rdy_num++;
  2276. dev[core_id].duration_without_int += restart_cmdbuf->executing_time;
  2277. PDEBUG("Keep valid cmdbuf [%d] in the list.\n", restart_cmdbuf->cmdbuf_id);
  2278. }
  2279. }
  2280. if (restart_cmdbuf) {
  2281. PDEBUG("Set restart cmdbuf [%d] via else.\n", restart_cmdbuf->cmdbuf_id);
  2282. }
  2283. }
  2284. // remove first linked cmdbuf from list
  2285. vcmd_delink_rm_cmdbuf(&dev[core_id], new_cmdbuf_node);
  2286. }
  2287. software_triger_abort = 0;
  2288. release_cmdbuf_num++;
  2289. PDEBUG("release reserved cmdbuf\n");
  2290. }
  2291. else if (vcmd_aborted && !cmdbuf_obj_temp->cmdbuf_run_done) {
  2292. /* VCMD is aborted, need to re-calculate the duration_without_int */
  2293. if (!restart_cmdbuf)
  2294. restart_cmdbuf = cmdbuf_obj_temp; /* first cmdbuf to be restarted */
  2295. dev[core_id].duration_without_int += cmdbuf_obj_temp->executing_time;
  2296. dev[core_id].sw_cmdbuf_rdy_num++;
  2297. }
  2298. new_cmdbuf_node = new_cmdbuf_node->next;
  2299. }
  2300. if (restart_cmdbuf && restart_cmdbuf->core_id == core_id) {
  2301. u32 irq_status1, irq_status2;
  2302. PDEBUG("Restart from cmdbuf [%d] after aborting.\n", restart_cmdbuf->cmdbuf_id);
  2303. irq_status1 = vcmd_read_reg((const void *)dev[core_id].hwregs, VCMD_REGISTER_INT_STATUS_OFFSET);
  2304. vcmd_write_reg((const void *)dev[core_id].hwregs, VCMD_REGISTER_INT_STATUS_OFFSET, irq_status1);
  2305. irq_status2 = vcmd_read_reg((const void *)dev[core_id].hwregs, VCMD_REGISTER_INT_STATUS_OFFSET);
  2306. PDEBUG("Clear irq status from 0x%0x -> 0x%0x\n", irq_status1, irq_status2);
  2307. if (mmu_enable) {
  2308. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR,
  2309. (u32)(restart_cmdbuf->mmu_cmdbuf_busAddress));
  2310. if(sizeof(size_t) == 8) {
  2311. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR_MSB,(u32)((u64)(restart_cmdbuf->mmu_cmdbuf_busAddress)>>32));
  2312. } else {
  2313. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR_MSB, 0);
  2314. }
  2315. } else {
  2316. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR,(u32)(restart_cmdbuf->cmdbuf_busAddress-base_ddr_addr));
  2317. if(sizeof(size_t) == 8) {
  2318. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR_MSB,(u32)((u64)(restart_cmdbuf->cmdbuf_busAddress-base_ddr_addr)>>32));
  2319. } else {
  2320. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR_MSB, 0);
  2321. }
  2322. }
  2323. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_EXE_CMDBUF_COUNT,0);
  2324. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_EXE_CMDBUF_LENGTH,(u32)((restart_cmdbuf->cmdbuf_size+7)/8));
  2325. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_CMDBUF_EXECUTING_ID,restart_cmdbuf->cmdbuf_id);
  2326. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_RDY_CMDBUF_COUNT,dev->sw_cmdbuf_rdy_num);
  2327. #ifdef VCMD_DEBUG_INTERNAL
  2328. printk_vcmd_register_debug((const void *)dev[core_id].hwregs, "before restart");
  2329. #endif
  2330. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_START_TRIGGER,1);
  2331. PDEBUG("Restart from cmdbuf [%d] dev register sw_cmdbuf_rdy_num is %d \n", restart_cmdbuf->cmdbuf_id,
  2332. vcmd_get_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_RDY_CMDBUF_COUNT));
  2333. PDEBUG("Restart from cmdbuf [%d] after aborting: start trigger = %d.\n", restart_cmdbuf->cmdbuf_id,
  2334. vcmd_get_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_START_TRIGGER));
  2335. PDEBUG("dev state from %d -> WORKING.\n", dev[core_id].working_state);
  2336. dev[core_id].working_state = WORKING_STATE_WORKING;
  2337. #ifdef VCMD_DEBUG_INTERNAL
  2338. printk_vcmd_register_debug((const void *)dev[core_id].hwregs, "after restart");
  2339. #endif
  2340. } else {
  2341. PDEBUG("No more command buffer to be restarted!\n");
  2342. }
  2343. spin_unlock_irqrestore(dev[core_id].spinlock, flags);
  2344. // VCMD aborted but not restarted, nedd to wake up
  2345. if (vcmd_aborted && !restart_cmdbuf)
  2346. wake_up_interruptible_all(dev[core_id].wait_queue);
  2347. }
  2348. if(release_cmdbuf_num)
  2349. wake_up_interruptible_all(&vcmd_cmdbuf_memory_wait);
  2350. spin_lock_irqsave(&vcmd_process_manager_lock, flags);
  2351. process_manager_node = global_process_manager.head;
  2352. while(1)
  2353. {
  2354. if(process_manager_node == NULL)
  2355. break;
  2356. process_manager_obj = (struct process_manager_obj*)process_manager_node->data;
  2357. if(process_manager_obj->filp == filp)
  2358. break;
  2359. process_manager_node = process_manager_node->next;
  2360. }
  2361. if (process_manager_obj)
  2362. {
  2363. while(process_manager_obj->pm_count > 0)
  2364. {
  2365. pm_runtime_mark_last_busy(&dev[0].pdev->dev);
  2366. pm_runtime_put_autosuspend(&dev[0].pdev->dev);
  2367. process_manager_obj->pm_count--;
  2368. }
  2369. }
  2370. //remove node from list
  2371. bi_list_remove_node(&global_process_manager,process_manager_node);
  2372. spin_unlock_irqrestore(&vcmd_process_manager_lock, flags);
  2373. free_process_manager_node(process_manager_node);
  2374. up(&vcmd_reserve_cmdbuf_sem[dev->vcmd_core_cfg.sub_module_type]);
  2375. return 0;
  2376. }
  2377. /* VFS methods */
  2378. static struct file_operations hantrovcmd_fops = {
  2379. .owner= THIS_MODULE,
  2380. .open = hantrovcmd_open,
  2381. .release = hantrovcmd_release,
  2382. .unlocked_ioctl = hantrovcmd_ioctl,
  2383. .fasync = NULL,
  2384. };
  2385. static u32 vcmd_release_AXIFE_IO(void)
  2386. {
  2387. #ifdef HANTROAXIFE_SUPPORT
  2388. int i=0, j=0;
  2389. for(i=0; i<total_vcmd_core_num; i++)
  2390. {
  2391. for(j=0; j<2; j++)
  2392. {
  2393. if(axife_hwregs[i][j] != NULL)
  2394. {
  2395. iounmap(axife_hwregs[i][j]);
  2396. release_mem_region(vcmd_core_array[i].vcmd_base_addr
  2397. +vcmd_core_array[i].submodule_axife_addr[j], AXIFE_SIZE);
  2398. axife_hwregs[i][j] = NULL;
  2399. }
  2400. }
  2401. }
  2402. #endif
  2403. return 0;
  2404. }
  2405. static u32 vcmd_release_MMU_IO(void)
  2406. {
  2407. #ifdef HANTROMMU_SUPPORT
  2408. int i=0, j=0;
  2409. for(i=0; i<total_vcmd_core_num; i++)
  2410. {
  2411. for(j=0; j<2; j++)
  2412. {
  2413. if(mmu_hwregs[i][j] != NULL)
  2414. {
  2415. iounmap(mmu_hwregs[i][j]);
  2416. release_mem_region(vcmd_core_array[i].vcmd_base_addr
  2417. +vcmd_core_array[i].submodule_MMU_addr[j], MMU_SIZE);
  2418. mmu_hwregs[i][j] = NULL;
  2419. }
  2420. }
  2421. }
  2422. #endif
  2423. return 0;
  2424. }
  2425. static u32 ConfigAXIFE(u32 mode)
  2426. {
  2427. #ifdef HANTROAXIFE_SUPPORT
  2428. u32 i = 0;
  2429. u8 sub_module_type = 0;
  2430. for(i=0; i<total_vcmd_core_num; i++)
  2431. {
  2432. sub_module_type = vcmd_core_array[i].sub_module_type;
  2433. pr_info("ConfigAXIFE: sub_module_type is %d\n", sub_module_type);
  2434. if(vcmd_core_array[i].submodule_axife_addr[0] != 0xffff)
  2435. {
  2436. if(!request_mem_region(vcmd_core_array[i].vcmd_base_addr+vcmd_core_array[i].submodule_axife_addr[0], AXIFE_SIZE, "vc8000"))
  2437. {
  2438. pr_info("failed to request_mem_region for axife_hwregs[%d][0]\n", i);
  2439. return -EBUSY;
  2440. }
  2441. #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,17,0))
  2442. axife_hwregs[i][0] = (volatile u8*)ioremap_nocache(vcmd_core_array[i].vcmd_base_addr
  2443. +vcmd_core_array[i].submodule_axife_addr[0], AXIFE_SIZE);
  2444. #else
  2445. axife_hwregs[i][0] = (volatile u8*)ioremap(vcmd_core_array[i].vcmd_base_addr
  2446. +vcmd_core_array[i].submodule_axife_addr[0], AXIFE_SIZE);
  2447. #endif
  2448. if (axife_hwregs[i][0] != NULL)
  2449. {
  2450. PDEBUG("ConfigAXIFE: axife_hwregs[%d][0]=%p\n", i, axife_hwregs[i][0]);
  2451. AXIFEEnable(axife_hwregs[i][0], mode);
  2452. }
  2453. }
  2454. if(vcmd_core_array[i].submodule_axife_addr[1] != 0xffff)
  2455. {
  2456. if(!request_mem_region(vcmd_core_array[i].vcmd_base_addr+vcmd_core_array[i].submodule_axife_addr[1], AXIFE_SIZE, "vc8000"))
  2457. {
  2458. pr_info("failed to request_mem_region for axife_hwregs[%d][0]\n", i);
  2459. return -EBUSY;
  2460. }
  2461. #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,17,0))
  2462. axife_hwregs[i][1] = (volatile u8*)ioremap_nocache(vcmd_core_array[i].vcmd_base_addr
  2463. +vcmd_core_array[i].submodule_axife_addr[1], AXIFE_SIZE);
  2464. #else
  2465. axife_hwregs[i][1] = (volatile u8*)ioremap(vcmd_core_array[i].vcmd_base_addr
  2466. +vcmd_core_array[i].submodule_axife_addr[1], AXIFE_SIZE);
  2467. #endif
  2468. if (axife_hwregs[i][1] != NULL)
  2469. {
  2470. PDEBUG("ConfigAXIFE: axife_hwregs[%d][1]=%p\n", i, axife_hwregs[i][1]);
  2471. AXIFEEnable(axife_hwregs[i][1] , mode);
  2472. }
  2473. }
  2474. }
  2475. #endif
  2476. return 0;
  2477. }
  2478. static u32 ConfigMMU(void)
  2479. {
  2480. #ifdef HANTROMMU_SUPPORT
  2481. u32 i = 0;
  2482. enum MMUStatus mmu_status = MMU_STATUS_FALSE;
  2483. u8 sub_module_type = 0;
  2484. /* MMU only initial once for the vcmd core no matter how many MMU we have */
  2485. for(i = 0; i < total_vcmd_core_num; i++)
  2486. {
  2487. sub_module_type = vcmd_core_array[i].sub_module_type;
  2488. pr_info("ConfigMMU, MMUInit: sub_module_type is %d\n", sub_module_type);
  2489. if(vcmd_core_array[i].submodule_MMU_addr[0] != 0xffff)
  2490. {
  2491. if(!request_mem_region(vcmd_core_array[i].vcmd_base_addr+vcmd_core_array[i].submodule_MMU_addr[0], MMU_SIZE, "vc8000"))
  2492. {
  2493. pr_info("failed to request_mem_region for mmu_hwregs[%d][0]\n", i);
  2494. return -EBUSY;
  2495. }
  2496. #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,17,0))
  2497. mmu_hwregs[i][0] = (volatile u8*)ioremap_nocache(vcmd_core_array[i].vcmd_base_addr
  2498. +vcmd_core_array[i].submodule_MMU_addr[0], MMU_SIZE);
  2499. #else
  2500. mmu_hwregs[i][0] = (volatile u8*)ioremap(vcmd_core_array[i].vcmd_base_addr
  2501. +vcmd_core_array[i].submodule_MMU_addr[0], MMU_SIZE);
  2502. #endif
  2503. if (mmu_hwregs[i][0] != NULL)
  2504. {
  2505. mmu_status = MMUInit(mmu_hwregs[i][0]);
  2506. if(mmu_status == MMU_STATUS_NOT_FOUND)
  2507. {
  2508. pr_info("MMU does not exist!\n");
  2509. return -1;
  2510. }
  2511. else if(mmu_status != MMU_STATUS_OK)
  2512. {
  2513. return -2;
  2514. }
  2515. else
  2516. pr_info("MMU detected!\n");
  2517. PDEBUG("mmu_hwregs[%d][0]=%p\n", i, mmu_hwregs[i][0]);
  2518. }
  2519. }
  2520. if(vcmd_core_array[i].submodule_MMU_addr[1] != 0xffff)
  2521. {
  2522. if(!request_mem_region(vcmd_core_array[i].vcmd_base_addr+vcmd_core_array[i].submodule_MMU_addr[1], MMU_SIZE, "vc8000"))
  2523. {
  2524. pr_info("failed to request_mem_region for mmu_hwregs[%d][0]\n", i);
  2525. return -EBUSY;
  2526. }
  2527. #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,17,0))
  2528. mmu_hwregs[i][1] = (volatile u8*)ioremap_nocache(vcmd_core_array[i].vcmd_base_addr
  2529. +vcmd_core_array[i].submodule_MMU_addr[1], MMU_SIZE);
  2530. #else
  2531. mmu_hwregs[i][1] = (volatile u8*)ioremap(vcmd_core_array[i].vcmd_base_addr
  2532. +vcmd_core_array[i].submodule_MMU_addr[1], MMU_SIZE);
  2533. #endif
  2534. PDEBUG("mmu_hwregs[%d][1]=%p\n", i, mmu_hwregs[i][1]);
  2535. }
  2536. }
  2537. mmu_status = MMUEnable(mmu_hwregs);
  2538. PDEBUG("mmu_enable is %d\n", mmu_enable);
  2539. if (mmu_status != MMU_STATUS_OK)
  2540. {
  2541. pr_info("MMUEnable: MMU enable failed\n");
  2542. return -3;
  2543. }
  2544. #endif
  2545. return 0;
  2546. }
  2547. static u32 MMU_Kernel_map(void)
  2548. {
  2549. #ifdef HANTROMMU_SUPPORT
  2550. struct kernel_addr_desc addr;
  2551. if (mmu_enable) {
  2552. addr.bus_address = vcmd_buf_mem_pool.busAddress - gBaseDDRHw;
  2553. addr.size = vcmd_buf_mem_pool.size;
  2554. if(MMUKernelMemNodeMap(&addr) != MMU_STATUS_OK) {
  2555. return -1;
  2556. }
  2557. vcmd_buf_mem_pool.mmu_bus_address = addr.mmu_bus_address;
  2558. pr_info("MMU_Kernel_map: vcmd_buf_mem_pool.mmu_bus_address=0x%llx.\n",(long long unsigned int)vcmd_buf_mem_pool.mmu_bus_address);
  2559. }
  2560. if (mmu_enable) {
  2561. addr.bus_address = vcmd_status_buf_mem_pool.busAddress - gBaseDDRHw;
  2562. addr.size = vcmd_status_buf_mem_pool.size;
  2563. if(MMUKernelMemNodeMap(&addr) != MMU_STATUS_OK) {
  2564. return -1;
  2565. }
  2566. vcmd_status_buf_mem_pool.mmu_bus_address = addr.mmu_bus_address;
  2567. pr_info("MMU_Kernel_map: vcmd_status_buf_mem_pool.mmu_bus_address=0x%llx.\n",(long long unsigned int)vcmd_status_buf_mem_pool.mmu_bus_address);
  2568. }
  2569. if (mmu_enable) {
  2570. addr.bus_address = vcmd_registers_mem_pool.busAddress - gBaseDDRHw;
  2571. addr.size = vcmd_registers_mem_pool.size;
  2572. if(MMUKernelMemNodeMap(&addr) != MMU_STATUS_OK) {
  2573. return -1;
  2574. }
  2575. vcmd_registers_mem_pool.mmu_bus_address = addr.mmu_bus_address;
  2576. pr_info("MMU_Kernel_map: vcmd_registers_mem_pool.mmu_bus_address=0x%llx.\n",(long long unsigned int)vcmd_registers_mem_pool.mmu_bus_address);
  2577. }
  2578. #endif
  2579. return 0;
  2580. }
  2581. static u32 vcmd_pool_release(struct platform_device *pdev)
  2582. {
  2583. //iounmap((void *) vcmd_buf_mem_pool.virtualAddress);
  2584. //release_mem_region(vcmd_buf_mem_pool.busAddress, vcmd_buf_mem_pool.size);
  2585. //iounmap((void *) vcmd_status_buf_mem_pool.virtualAddress);
  2586. //release_mem_region(vcmd_status_buf_mem_pool.busAddress, vcmd_status_buf_mem_pool.size);
  2587. //iounmap((void *) vcmd_registers_mem_pool.virtualAddress);
  2588. //release_mem_region(vcmd_registers_mem_pool.busAddress, vcmd_registers_mem_pool.size);
  2589. dma_free_coherent(&pdev->dev, CMDBUF_POOL_TOTAL_SIZE*2 + CMDBUF_VCMD_REGISTER_TOTAL_SIZE,
  2590. vcmd_buf_mem_pool.virtualAddress, vcmd_buf_mem_pool.busAddress);
  2591. return 0;
  2592. }
  2593. static u32 MMU_Kernel_unmap(void)
  2594. {
  2595. #ifdef HANTROMMU_SUPPORT
  2596. struct kernel_addr_desc addr;
  2597. if (vcmd_buf_mem_pool.virtualAddress) {
  2598. if (mmu_enable) {
  2599. addr.bus_address = vcmd_buf_mem_pool.busAddress - gBaseDDRHw;
  2600. addr.size = vcmd_buf_mem_pool.size;
  2601. MMUKernelMemNodeUnmap(&addr);
  2602. }
  2603. }
  2604. if (vcmd_status_buf_mem_pool.virtualAddress) {
  2605. if (mmu_enable) {
  2606. addr.bus_address = vcmd_status_buf_mem_pool.busAddress - gBaseDDRHw;
  2607. addr.size = vcmd_status_buf_mem_pool.size;
  2608. MMUKernelMemNodeUnmap(&addr);
  2609. }
  2610. }
  2611. if (vcmd_registers_mem_pool.virtualAddress) {
  2612. if (mmu_enable) {
  2613. addr.bus_address = vcmd_registers_mem_pool.busAddress - gBaseDDRHw;
  2614. addr.size = vcmd_registers_mem_pool.size;
  2615. MMUKernelMemNodeUnmap(&addr);
  2616. }
  2617. }
  2618. #endif
  2619. return 0;
  2620. }
  2621. static void vcmd_link_cmdbuf(struct hantrovcmd_dev *dev,bi_list_node* last_linked_cmdbuf_node)
  2622. {
  2623. bi_list_node* new_cmdbuf_node=NULL;
  2624. bi_list_node* next_cmdbuf_node=NULL;
  2625. struct cmdbuf_obj* cmdbuf_obj=NULL;
  2626. struct cmdbuf_obj* next_cmdbuf_obj=NULL;
  2627. u32 * jmp_addr=NULL;
  2628. u32 operation_code;
  2629. new_cmdbuf_node = last_linked_cmdbuf_node;
  2630. //for the first cmdbuf.
  2631. if(new_cmdbuf_node!=NULL)
  2632. {
  2633. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  2634. if((cmdbuf_obj->cmdbuf_data_linked==0) )
  2635. {
  2636. dev->sw_cmdbuf_rdy_num ++;
  2637. cmdbuf_obj->cmdbuf_data_linked=1;
  2638. dev->duration_without_int = 0;
  2639. if(cmdbuf_obj->has_end_cmdbuf==0)
  2640. {
  2641. if(cmdbuf_obj->no_normal_int_cmdbuf==1)
  2642. {
  2643. dev->duration_without_int = cmdbuf_obj->executing_time;
  2644. //maybe nop is modified, so write back.
  2645. if(dev->duration_without_int>=INT_MIN_SUM_OF_IMAGE_SIZE)
  2646. {
  2647. jmp_addr = cmdbuf_obj->cmdbuf_virtualAddress + (cmdbuf_obj->cmdbuf_size/4);
  2648. operation_code = *(jmp_addr-4);
  2649. operation_code = JMP_IE_1|operation_code;
  2650. *(jmp_addr-4) = operation_code;
  2651. dev->duration_without_int = 0;
  2652. }
  2653. }
  2654. }
  2655. }
  2656. }
  2657. while(1)
  2658. {
  2659. if(new_cmdbuf_node==NULL)
  2660. break;
  2661. if(new_cmdbuf_node->next==NULL)
  2662. break;
  2663. next_cmdbuf_node = new_cmdbuf_node->next;
  2664. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  2665. next_cmdbuf_obj = (struct cmdbuf_obj*)next_cmdbuf_node->data;
  2666. if(cmdbuf_obj->has_end_cmdbuf==0 && !next_cmdbuf_obj->cmdbuf_run_done)
  2667. {
  2668. //need to link, current cmdbuf link to next cmdbuf
  2669. jmp_addr = cmdbuf_obj->cmdbuf_virtualAddress + (cmdbuf_obj->cmdbuf_size/4);
  2670. if(dev->hw_version_id > HW_ID_1_0_C )
  2671. {
  2672. //set next cmdbuf id
  2673. *(jmp_addr-1) = next_cmdbuf_obj->cmdbuf_id;
  2674. }
  2675. if (mmu_enable) {
  2676. if(sizeof(size_t) == 8) {
  2677. *(jmp_addr-2)=(u32)((u64)(next_cmdbuf_obj->mmu_cmdbuf_busAddress)>>32);
  2678. } else {
  2679. *(jmp_addr-2)=0;
  2680. }
  2681. *(jmp_addr-3)=(u32)(next_cmdbuf_obj->mmu_cmdbuf_busAddress);
  2682. pr_debug("vcmd_link_cmdbuf: next_cmdbuf_obj->mmu_cmdbuf_busAddress=0x%08x\n", next_cmdbuf_obj->mmu_cmdbuf_busAddress);
  2683. } else {
  2684. if(sizeof(size_t) == 8) {
  2685. *(jmp_addr-2)=(u32)((u64)(next_cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr)>>32);
  2686. } else {
  2687. *(jmp_addr-2)=0;
  2688. }
  2689. *(jmp_addr-3)=(u32)(next_cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr);
  2690. }
  2691. operation_code = *(jmp_addr-4);
  2692. operation_code >>=16;
  2693. operation_code <<=16;
  2694. *(jmp_addr-4)=(u32)(operation_code |JMP_RDY_1|((next_cmdbuf_obj->cmdbuf_size+7)/8));
  2695. next_cmdbuf_obj->cmdbuf_data_linked = 1;
  2696. dev->sw_cmdbuf_rdy_num ++;
  2697. //modify nop code of next cmdbuf
  2698. if(next_cmdbuf_obj->has_end_cmdbuf==0)
  2699. {
  2700. if(next_cmdbuf_obj->no_normal_int_cmdbuf==1)
  2701. {
  2702. dev->duration_without_int +=next_cmdbuf_obj->executing_time;
  2703. //maybe we see the modified nop before abort, so need to write back.
  2704. if(dev->duration_without_int>=INT_MIN_SUM_OF_IMAGE_SIZE)
  2705. {
  2706. jmp_addr = next_cmdbuf_obj->cmdbuf_virtualAddress + (next_cmdbuf_obj->cmdbuf_size/4);
  2707. operation_code = *(jmp_addr-4);
  2708. operation_code = JMP_IE_1|operation_code;
  2709. *(jmp_addr-4) = operation_code;
  2710. dev->duration_without_int = 0;
  2711. }
  2712. }
  2713. }
  2714. else
  2715. {
  2716. dev->duration_without_int = 0;
  2717. }
  2718. #ifdef VCMD_DEBUG_INTERNAL
  2719. {
  2720. u32 i;
  2721. pr_info("vcmd link, last cmdbuf content\n");
  2722. for(i=cmdbuf_obj->cmdbuf_size/4 -8;i<cmdbuf_obj->cmdbuf_size/4;i++)
  2723. {
  2724. pr_info("current linked cmdbuf data %d =0x%x\n",i,*(cmdbuf_obj->cmdbuf_virtualAddress+i));
  2725. }
  2726. }
  2727. #endif
  2728. }
  2729. new_cmdbuf_node = new_cmdbuf_node->next;
  2730. }
  2731. return;
  2732. }
  2733. /* delink all the cmd buffers from the cmdbuf in front of last_linked_cmdbuf_node
  2734. to head of the list. All the cmd bufs marked as X will be delinked.
  2735. E.g.,
  2736. X->X->...->X->L->L-> ... ->L
  2737. ^ ^ ^
  2738. head last_linked_cmdbuf_node tail
  2739. */
  2740. static void vcmd_delink_cmdbuf(struct hantrovcmd_dev *dev,bi_list_node* last_linked_cmdbuf_node)
  2741. {
  2742. bi_list_node* new_cmdbuf_node=NULL;
  2743. struct cmdbuf_obj* cmdbuf_obj=NULL;
  2744. new_cmdbuf_node = last_linked_cmdbuf_node;
  2745. while(1)
  2746. {
  2747. if(new_cmdbuf_node==NULL)
  2748. break;
  2749. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  2750. if(cmdbuf_obj->cmdbuf_data_linked)
  2751. {
  2752. cmdbuf_obj->cmdbuf_data_linked = 0;
  2753. }
  2754. else
  2755. break;
  2756. new_cmdbuf_node = new_cmdbuf_node->next;
  2757. }
  2758. dev->sw_cmdbuf_rdy_num=0;
  2759. }
  2760. static void ConfigAIIXFE_MMU_BYVCMD(struct hantrovcmd_dev **device)
  2761. {
  2762. #ifdef HANTROVCMD_ENABLE_IP_SUPPORT
  2763. u32 i = 0;
  2764. u64 address = 0;
  2765. u32 mirror_index, register_index, register_value;
  2766. u32 write_command = 0;
  2767. if(!device) return;
  2768. struct hantrovcmd_dev *dev = *device;
  2769. mirror_index = VCMD_REGISTER_INDEX_SW_INIT_CMD0;
  2770. write_command = OPCODE_WREG|(1<<26)|(1<<16);
  2771. #ifdef HANTROAXIFE_SUPPORT
  2772. //enable AXIFE by VCMD
  2773. for(i=0; i<2; i++)
  2774. {
  2775. if(dev->vcmd_core_cfg.submodule_axife_addr[i] != 0xffff)
  2776. {
  2777. register_index = AXI_REG10_SW_FRONTEND_EN;
  2778. register_value = 0x02;
  2779. dev->reg_mirror[mirror_index++] = write_command|(dev->vcmd_core_cfg.submodule_axife_addr[i]+register_index);
  2780. dev->reg_mirror[mirror_index++] = register_value;
  2781. register_index = AXI_REG11_SW_WORK_MODE;
  2782. register_value = 0x00;
  2783. dev->reg_mirror[mirror_index++] = write_command|(dev->vcmd_core_cfg.submodule_axife_addr[i]+register_index);
  2784. dev->reg_mirror[mirror_index++] = register_value;
  2785. }
  2786. }
  2787. #endif
  2788. #ifdef HANTROMMU_SUPPORT
  2789. //enable MMU by VCMD
  2790. address = GetMMUAddress();
  2791. pr_info("ConfigAIIXFE_MMU_BYVCMD: address = 0x%llx", address);
  2792. for(i=0; i<2; i++)
  2793. {
  2794. if(dev->vcmd_core_cfg.submodule_MMU_addr[i] != 0xffff)
  2795. {
  2796. register_index = MMU_REG_ADDRESS;
  2797. register_value = address;
  2798. dev->reg_mirror[mirror_index++] = write_command|(dev->vcmd_core_cfg.submodule_MMU_addr[i]+register_index);
  2799. dev->reg_mirror[mirror_index++] = register_value;
  2800. register_index = MMU_REG_PAGE_TABLE_ID;
  2801. register_value = 0x10000;
  2802. dev->reg_mirror[mirror_index++] = write_command|(dev->vcmd_core_cfg.submodule_MMU_addr[i]+register_index);
  2803. dev->reg_mirror[mirror_index++] = register_value;
  2804. register_index = MMU_REG_PAGE_TABLE_ID;
  2805. register_value = 0x00000;
  2806. dev->reg_mirror[mirror_index++] = write_command|(dev->vcmd_core_cfg.submodule_MMU_addr[i]+register_index);
  2807. dev->reg_mirror[mirror_index++] = register_value;
  2808. register_index = MMU_REG_CONTROL;
  2809. register_value = 1;
  2810. dev->reg_mirror[mirror_index++] = write_command|(dev->vcmd_core_cfg.submodule_MMU_addr[i]+register_index);
  2811. dev->reg_mirror[mirror_index++] = register_value;
  2812. }
  2813. }
  2814. #endif
  2815. //END command
  2816. dev->reg_mirror[mirror_index++] = OPCODE_END;
  2817. dev->reg_mirror[mirror_index] = 0x00;
  2818. for(i=0; i<mirror_index-VCMD_REGISTER_INDEX_SW_INIT_CMD0; i++)
  2819. {
  2820. register_index = (i + VCMD_REGISTER_INDEX_SW_INIT_CMD0) * 4;
  2821. vcmd_write_reg((const void *)dev->hwregs, register_index, dev->reg_mirror[i+VCMD_REGISTER_INDEX_SW_INIT_CMD0]);
  2822. }
  2823. #endif
  2824. }
  2825. static void vcmd_start(struct hantrovcmd_dev *dev,bi_list_node* first_linked_cmdbuf_node)
  2826. {
  2827. struct cmdbuf_obj* cmdbuf_obj = NULL;
  2828. if(dev->working_state == WORKING_STATE_IDLE)
  2829. {
  2830. if((first_linked_cmdbuf_node!=NULL) && dev->sw_cmdbuf_rdy_num)
  2831. {
  2832. cmdbuf_obj = (struct cmdbuf_obj*)first_linked_cmdbuf_node->data;
  2833. #ifdef VCMD_DEBUG_INTERNAL
  2834. printk_vcmd_register_debug((const void *)dev->hwregs, "vcmd_start enters");
  2835. #endif
  2836. //0x40
  2837. #ifdef HANTROVCMD_ENABLE_IP_SUPPORT
  2838. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_INIT_MODE,1); //when start vcmd, first vcmd is init mode
  2839. #endif
  2840. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_AXI_CLK_GATE_DISABLE,0);
  2841. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_MASTER_OUT_CLK_GATE_DISABLE,1);//this bit should be set 1 only when need to reset dec400
  2842. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_CORE_CLK_GATE_DISABLE,0);
  2843. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_ABORT_MODE,0);
  2844. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_RESET_CORE,0);
  2845. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_RESET_ALL,0);
  2846. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_START_TRIGGER,0);
  2847. //0x48
  2848. if(dev->hw_version_id <= HW_ID_1_0_C)
  2849. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_INTCMD_EN,0xffff);
  2850. else
  2851. {
  2852. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_JMPP_EN,1);
  2853. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_JMPD_EN,1);
  2854. }
  2855. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_RESET_EN,1);
  2856. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_ABORT_EN,1);
  2857. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_CMDERR_EN,1);
  2858. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_TIMEOUT_EN,1);
  2859. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_BUSERR_EN,1);
  2860. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_ENDCMD_EN,1);
  2861. //0x4c
  2862. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_TIMEOUT_EN,1);
  2863. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_TIMEOUT_CYCLES,0x1dcd6500);
  2864. if (mmu_enable) {
  2865. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR,(u32)(cmdbuf_obj->mmu_cmdbuf_busAddress));
  2866. pr_debug("cmdbuf_obj->mmu_cmdbuf_busAddress=0x%08x\n", (u32)cmdbuf_obj->mmu_cmdbuf_busAddress);
  2867. if(sizeof(size_t) == 8) {
  2868. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR_MSB,(u32)((u64)(cmdbuf_obj->mmu_cmdbuf_busAddress)>>32));
  2869. } else {
  2870. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR_MSB, 0);
  2871. }
  2872. } else {
  2873. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR,(u32)(cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr));
  2874. if(sizeof(size_t) == 8) {
  2875. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR_MSB,(u32)((u64)(cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr)>>32));
  2876. } else {
  2877. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR_MSB, 0);
  2878. }
  2879. }
  2880. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_EXE_CMDBUF_LENGTH,(u32)((cmdbuf_obj->cmdbuf_size+7)/8));
  2881. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_RDY_CMDBUF_COUNT,dev->sw_cmdbuf_rdy_num);
  2882. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_MAX_BURST_LEN,0x10);
  2883. if(dev->hw_version_id > HW_ID_1_0_C )
  2884. {
  2885. vcmd_write_register_value((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_CMDBUF_EXECUTING_ID,(u32)cmdbuf_obj->cmdbuf_id);
  2886. }
  2887. vcmd_write_reg((const void *)dev->hwregs,0x44,vcmd_read_reg((const void *)dev->hwregs,0x44));
  2888. vcmd_write_reg((const void *)dev->hwregs,0x40,dev->reg_mirror[0x40/4]);
  2889. vcmd_write_reg((const void *)dev->hwregs,0x48,dev->reg_mirror[0x48/4]);
  2890. vcmd_write_reg((const void *)dev->hwregs,0x4c,dev->reg_mirror[0x4c/4]);
  2891. vcmd_write_reg((const void *)dev->hwregs,0x50,dev->reg_mirror[0x50/4]);
  2892. vcmd_write_reg((const void *)dev->hwregs,0x54,dev->reg_mirror[0x54/4]);
  2893. vcmd_write_reg((const void *)dev->hwregs,0x58,dev->reg_mirror[0x58/4]);
  2894. vcmd_write_reg((const void *)dev->hwregs,0x5c,dev->reg_mirror[0x5c/4]);
  2895. vcmd_write_reg((const void *)dev->hwregs,0x60,dev->reg_mirror[0x60/4]);
  2896. vcmd_write_reg((const void *)dev->hwregs,0x64,0xffffffff);//not interrupt cpu
  2897. dev->working_state = WORKING_STATE_WORKING;
  2898. ConfigAIIXFE_MMU_BYVCMD(&dev);
  2899. //start
  2900. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_MASTER_OUT_CLK_GATE_DISABLE,1);//this bit should be set 1 only when need to reset dec400
  2901. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_START_TRIGGER,1);
  2902. PDEBUG("To write vcmd register 16:0x%x\n",dev->reg_mirror[0x40/4]);
  2903. vcmd_write_reg((const void *)dev->hwregs,0x40,dev->reg_mirror[0x40/4]);
  2904. #ifdef VCMD_DEBUG_INTERNAL
  2905. printk_vcmd_register_debug(dev->hwregs, "vcmd_start exits ");
  2906. #endif
  2907. }
  2908. }
  2909. }
  2910. static void create_read_all_registers_cmdbuf(struct exchange_parameter* input_para)
  2911. {
  2912. u32 register_range[]={VCMD_ENCODER_REGISTER_SIZE,
  2913. VCMD_IM_REGISTER_SIZE,
  2914. VCMD_DECODER_REGISTER_SIZE,
  2915. VCMD_JPEG_ENCODER_REGISTER_SIZE,
  2916. VCMD_JPEG_DECODER_REGISTER_SIZE};
  2917. u32 counter_cmdbuf_size=0;
  2918. u32 * set_base_addr=vcmd_buf_mem_pool.virtualAddress + input_para->cmdbuf_id*CMDBUF_MAX_SIZE/4;
  2919. //u32 *status_base_virt_addr=vcmd_status_buf_mem_pool.virtualAddress + input_para->cmdbuf_id*CMDBUF_MAX_SIZE/4+(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_main_addr/2/4+0);
  2920. ptr_t status_base_phy_addr=vcmd_status_buf_mem_pool.busAddress + input_para->cmdbuf_id*CMDBUF_MAX_SIZE+(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_main_addr/2+0);
  2921. u32 map_status_base_phy_addr=vcmd_status_buf_mem_pool.mmu_bus_address + input_para->cmdbuf_id*CMDBUF_MAX_SIZE+(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_main_addr/2+0);
  2922. u32 offset_inc=0;
  2923. u32 offset_inc_dec400=0;
  2924. if(vcmd_manager[input_para->module_type][0]->hw_version_id>HW_ID_1_0_C)
  2925. {
  2926. pr_info("vc8000_vcmd_driver:create cmdbuf data when hw_version_id = 0x%x\n",vcmd_manager[input_para->module_type][0]->hw_version_id);
  2927. //read vcmd executing cmdbuf id registers to ddr for balancing core load.
  2928. *(set_base_addr+0) = (OPCODE_RREG) |(1<<16) |(EXECUTING_CMDBUF_ID_ADDR*4);
  2929. counter_cmdbuf_size += 4;
  2930. *(set_base_addr+1) = (u32)0; //will be changed in link stage
  2931. counter_cmdbuf_size += 4;
  2932. *(set_base_addr+2) = (u32)0; //will be changed in link stage
  2933. counter_cmdbuf_size += 4;
  2934. //alignment
  2935. *(set_base_addr+3) = 0;
  2936. counter_cmdbuf_size += 4;
  2937. //read main IP all registers
  2938. *(set_base_addr+4) = (OPCODE_RREG) |((register_range[input_para->module_type]/4)<<16) |(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_main_addr+0);
  2939. counter_cmdbuf_size += 4;
  2940. if (mmu_enable) {
  2941. *(set_base_addr+5) = map_status_base_phy_addr;
  2942. } else {
  2943. *(set_base_addr+5) = (u32)(status_base_phy_addr-base_ddr_addr);
  2944. }
  2945. counter_cmdbuf_size += 4;
  2946. if (mmu_enable) {
  2947. *(set_base_addr+6) = 0;
  2948. } else {
  2949. if(sizeof(size_t) == 8) {
  2950. *(set_base_addr+6) = (u32)((u64)(status_base_phy_addr-base_ddr_addr)>>32);
  2951. } else {
  2952. *(set_base_addr+6) = 0;
  2953. }
  2954. }
  2955. counter_cmdbuf_size += 4;
  2956. //alignment
  2957. *(set_base_addr+7) = 0;
  2958. counter_cmdbuf_size += 4;
  2959. if(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_L2Cache_addr != 0xffff)
  2960. {
  2961. //read L2 cache register
  2962. offset_inc = 4;
  2963. status_base_phy_addr=vcmd_status_buf_mem_pool.busAddress + input_para->cmdbuf_id*CMDBUF_MAX_SIZE+(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_L2Cache_addr/2+0);
  2964. map_status_base_phy_addr=vcmd_status_buf_mem_pool.mmu_bus_address + input_para->cmdbuf_id*CMDBUF_MAX_SIZE+(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_L2Cache_addr/2+0);
  2965. //read L2cache IP first register
  2966. *(set_base_addr+8) = (OPCODE_RREG) |(1<<16) |(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_L2Cache_addr+0);
  2967. counter_cmdbuf_size += 4;
  2968. if (mmu_enable) {
  2969. *(set_base_addr+9) = map_status_base_phy_addr;
  2970. } else {
  2971. *(set_base_addr+9) = (u32)(status_base_phy_addr-base_ddr_addr);
  2972. }
  2973. counter_cmdbuf_size += 4;
  2974. if (mmu_enable) {
  2975. *(set_base_addr+10) = 0;
  2976. } else {
  2977. if(sizeof(size_t) == 8) {
  2978. *(set_base_addr+10) = (u32)((u64)(status_base_phy_addr-base_ddr_addr)>>32);
  2979. } else {
  2980. *(set_base_addr+10) = 0;
  2981. }
  2982. }
  2983. counter_cmdbuf_size += 4;
  2984. //alignment
  2985. *(set_base_addr+11) = 0;
  2986. counter_cmdbuf_size += 4;
  2987. }
  2988. if(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_dec400_addr != 0xffff)
  2989. {
  2990. //read dec400 register
  2991. offset_inc_dec400 = 4;
  2992. status_base_phy_addr=vcmd_status_buf_mem_pool.busAddress + input_para->cmdbuf_id*CMDBUF_MAX_SIZE+(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_dec400_addr/2+0);
  2993. map_status_base_phy_addr=vcmd_status_buf_mem_pool.mmu_bus_address + input_para->cmdbuf_id*CMDBUF_MAX_SIZE+(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_dec400_addr/2+0);
  2994. //read DEC400 IP first register
  2995. *(set_base_addr+8+offset_inc) = (OPCODE_RREG) |(0x2b<<16) |(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_dec400_addr+0);
  2996. counter_cmdbuf_size += 4;
  2997. if (mmu_enable)
  2998. {
  2999. *(set_base_addr+9+offset_inc) = map_status_base_phy_addr;
  3000. }
  3001. else
  3002. {
  3003. *(set_base_addr+9+offset_inc) = (u32)(status_base_phy_addr-base_ddr_addr);
  3004. }
  3005. counter_cmdbuf_size += 4;
  3006. if (mmu_enable)
  3007. {
  3008. *(set_base_addr+10+offset_inc) = 0;
  3009. }
  3010. else
  3011. {
  3012. if(sizeof(size_t) == 8)
  3013. {
  3014. *(set_base_addr+10+offset_inc) = (u32)((u64)(status_base_phy_addr-base_ddr_addr)>>32);
  3015. }
  3016. else
  3017. {
  3018. *(set_base_addr+10+offset_inc) = 0;
  3019. }
  3020. }
  3021. counter_cmdbuf_size += 4;
  3022. //alignment
  3023. *(set_base_addr+11+offset_inc) = 0;
  3024. counter_cmdbuf_size += 4;
  3025. }
  3026. #if 0
  3027. //INT code, interrupt immediately
  3028. *(set_base_addr+4) = (OPCODE_INT) |0 |input_para->cmdbuf_id;
  3029. counter_cmdbuf_size += 4;
  3030. //alignment
  3031. *(set_base_addr+5) = 0;
  3032. counter_cmdbuf_size += 4;
  3033. #endif
  3034. //read vcmd registers to ddr
  3035. *(set_base_addr+8+offset_inc + offset_inc_dec400) = (OPCODE_RREG) |(27<<16) |(0);
  3036. counter_cmdbuf_size += 4;
  3037. *(set_base_addr+9+offset_inc + offset_inc_dec400) = (u32)0; //will be changed in link stage
  3038. counter_cmdbuf_size += 4;
  3039. *(set_base_addr+10+offset_inc + offset_inc_dec400) = (u32)0; //will be changed in link stage
  3040. counter_cmdbuf_size += 4;
  3041. //alignment
  3042. *(set_base_addr+11+offset_inc + offset_inc_dec400) = 0;
  3043. counter_cmdbuf_size += 4;
  3044. //JMP RDY = 0
  3045. *(set_base_addr +12+offset_inc + offset_inc_dec400)= (OPCODE_JMP_RDY0) |0 |JMP_IE_1|0;
  3046. counter_cmdbuf_size += 4;
  3047. *(set_base_addr +13+offset_inc + offset_inc_dec400) = 0;
  3048. counter_cmdbuf_size += 4;
  3049. *(set_base_addr +14+offset_inc + offset_inc_dec400) = 0;
  3050. counter_cmdbuf_size += 4;
  3051. *(set_base_addr +15+offset_inc + offset_inc_dec400) = input_para->cmdbuf_id;
  3052. //don't add the last alignment DWORD in order to identify END command or JMP command.
  3053. //counter_cmdbuf_size += 4;
  3054. input_para->cmdbuf_size=(16+offset_inc + offset_inc_dec400)*4;
  3055. }
  3056. else
  3057. {
  3058. pr_info("vc8000_vcmd_driver:create cmdbuf data when hw_version_id = 0x%x\n",vcmd_manager[input_para->module_type][0]->hw_version_id);
  3059. //read all registers
  3060. *(set_base_addr+0) = (OPCODE_RREG) |((register_range[input_para->module_type]/4)<<16) |(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_main_addr+0);
  3061. counter_cmdbuf_size += 4;
  3062. if (mmu_enable) {
  3063. *(set_base_addr+1) = map_status_base_phy_addr;
  3064. } else {
  3065. *(set_base_addr+1) = (u32)(status_base_phy_addr-base_ddr_addr);
  3066. }
  3067. counter_cmdbuf_size += 4;
  3068. if (mmu_enable) {
  3069. *(set_base_addr+2) = 0;
  3070. } else {
  3071. if(sizeof(size_t) == 8) {
  3072. *(set_base_addr+2) = (u32)((u64)(status_base_phy_addr-base_ddr_addr)>>32);
  3073. } else {
  3074. *(set_base_addr+2) = 0;
  3075. }
  3076. }
  3077. counter_cmdbuf_size += 4;
  3078. //alignment
  3079. *(set_base_addr+3) = 0;
  3080. counter_cmdbuf_size += 4;
  3081. #if 0
  3082. //INT code, interrupt immediately
  3083. *(set_base_addr+4) = (OPCODE_INT) |0 |input_para->cmdbuf_id;
  3084. counter_cmdbuf_size += 4;
  3085. //alignment
  3086. *(set_base_addr+5) = 0;
  3087. counter_cmdbuf_size += 4;
  3088. #endif
  3089. //JMP RDY = 0
  3090. *(set_base_addr +4)= (OPCODE_JMP_RDY0) |0 |JMP_IE_1|0;
  3091. counter_cmdbuf_size += 4;
  3092. *(set_base_addr +5) = 0;
  3093. counter_cmdbuf_size += 4;
  3094. *(set_base_addr +6) = 0;
  3095. counter_cmdbuf_size += 4;
  3096. *(set_base_addr +7) = input_para->cmdbuf_id;
  3097. //don't add the last alignment DWORD in order to identify END command or JMP command.
  3098. //counter_cmdbuf_size += 4;
  3099. input_para->cmdbuf_size=8*4;
  3100. }
  3101. }
  3102. static void read_main_module_all_registers(u32 main_module_type)
  3103. {
  3104. int ret;
  3105. struct exchange_parameter input_para;
  3106. u32 irq_status_ret=0;
  3107. u32 *status_base_virt_addr;
  3108. input_para.executing_time=0;
  3109. input_para.priority=CMDBUF_PRIORITY_NORMAL;
  3110. input_para.module_type = main_module_type;
  3111. input_para.cmdbuf_size=0;
  3112. ret = reserve_cmdbuf(NULL,&input_para);
  3113. vcmd_manager[main_module_type][0]->status_cmdbuf_id = input_para.cmdbuf_id;
  3114. create_read_all_registers_cmdbuf(&input_para);
  3115. link_and_run_cmdbuf(NULL,&input_para);
  3116. //msleep(1000);
  3117. hantrovcmd_isr(input_para.core_id, &hantrovcmd_data[input_para.core_id]);
  3118. wait_cmdbuf_ready(NULL,input_para.cmdbuf_id,&irq_status_ret);
  3119. status_base_virt_addr=vcmd_status_buf_mem_pool.virtualAddress + input_para.cmdbuf_id*CMDBUF_MAX_SIZE/4+(vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_main_addr/2/4+0);
  3120. pr_info("vc8000_vcmd_driver: main module register 0:0x%x\n",*status_base_virt_addr);
  3121. pr_info("vc8000_vcmd_driver: main module register 80:0x%x\n",*(status_base_virt_addr+80));
  3122. pr_info("vc8000_vcmd_driver: main module register 214:0x%x\n",*(status_base_virt_addr+214));
  3123. pr_info("vc8000_vcmd_driver: main module register 226:0x%x\n", *(status_base_virt_addr+226));
  3124. pr_info("vc8000_vcmd_driver: main module register 287:0x%x\n", *(status_base_virt_addr+287));
  3125. //don't release cmdbuf because it can be used repeatedly
  3126. //release_cmdbuf(input_para.cmdbuf_id);
  3127. }
  3128. /*------------------------------------------------------------------------------
  3129. Function name : vcmd_pcie_init
  3130. Description : Initialize PCI Hw access
  3131. Return type : int
  3132. ------------------------------------------------------------------------------*/
  3133. static int vcmd_init(struct platform_device *pdev)
  3134. {
  3135. struct pci_dev *g_vcmd_dev = NULL; /* PCI device structure. */
  3136. unsigned long g_vcmd_base_ddr_hw; /* PCI base register address (memalloc) */
  3137. vcmd_buf_mem_pool.virtualAddress = dma_alloc_coherent(&pdev->dev, CMDBUF_POOL_TOTAL_SIZE*2 + CMDBUF_VCMD_REGISTER_TOTAL_SIZE,
  3138. &vcmd_buf_mem_pool.busAddress, GFP_KERNEL | GFP_DMA);
  3139. pr_info("Base memory val 0x%llx\n", vcmd_buf_mem_pool.busAddress);
  3140. vcmd_buf_mem_pool.size =CMDBUF_POOL_TOTAL_SIZE;
  3141. pr_info("Init: vcmd_buf_mem_pool.busAddress=0x%llx.\n",(long long unsigned int)vcmd_buf_mem_pool.busAddress);
  3142. if (vcmd_buf_mem_pool.virtualAddress == NULL ) {
  3143. pr_info("Init: failed to ioremap.\n");
  3144. return -1;
  3145. }
  3146. pr_info("Init: vcmd_buf_mem_pool.virtualAddress=0x%llx.\n",(long long unsigned int)vcmd_buf_mem_pool.virtualAddress);
  3147. vcmd_status_buf_mem_pool.busAddress = (void *)vcmd_buf_mem_pool.busAddress+CMDBUF_POOL_TOTAL_SIZE;
  3148. vcmd_status_buf_mem_pool.virtualAddress = (void *)vcmd_buf_mem_pool.virtualAddress+CMDBUF_POOL_TOTAL_SIZE;
  3149. vcmd_status_buf_mem_pool.size =CMDBUF_POOL_TOTAL_SIZE;
  3150. pr_info("Init: vcmd_status_buf_mem_pool.busAddress=0x%llx.\n",(long long unsigned int)vcmd_status_buf_mem_pool.busAddress);
  3151. if (vcmd_status_buf_mem_pool.virtualAddress == NULL ) {
  3152. pr_info("Init: failed to ioremap.\n");
  3153. return -1;
  3154. }
  3155. pr_info("Init: vcmd_status_buf_mem_pool.virtualAddress=0x%llx.\n",(long long unsigned int)vcmd_status_buf_mem_pool.virtualAddress);
  3156. vcmd_registers_mem_pool.busAddress = (void *)vcmd_buf_mem_pool.busAddress+CMDBUF_POOL_TOTAL_SIZE*2;
  3157. vcmd_registers_mem_pool.virtualAddress = (void *)vcmd_buf_mem_pool.virtualAddress+CMDBUF_POOL_TOTAL_SIZE*2;
  3158. vcmd_registers_mem_pool.size =CMDBUF_VCMD_REGISTER_TOTAL_SIZE;
  3159. pr_info("Init: vcmd_registers_mem_pool.busAddress=0x%llx.\n",(long long unsigned int)vcmd_registers_mem_pool.busAddress);
  3160. if (vcmd_registers_mem_pool.virtualAddress == NULL ) {
  3161. pr_info("Init: failed to ioremap.\n");
  3162. return -1;
  3163. }
  3164. pr_info("Init: vcmd_registers_mem_pool.virtualAddress=0x%llx.\n",(long long unsigned int)vcmd_registers_mem_pool.virtualAddress);
  3165. return 0;
  3166. out_pci_disable_device:
  3167. pci_disable_device(g_vcmd_dev);
  3168. out:
  3169. return -1;
  3170. }
  3171. static ssize_t encoder_config_write(struct file *filp,
  3172. const char __user *userbuf,
  3173. size_t count, loff_t *ppos)
  3174. {
  3175. struct hantrovcmd_dev *dev = hantrovcmd_data;
  3176. unsigned long value;
  3177. int ret;
  3178. if (count > VC8000E_MAX_CONFIG_LEN)
  3179. count = VC8000E_MAX_CONFIG_LEN;
  3180. else if (count <= 2)
  3181. return 0;
  3182. ret = copy_from_user(dev->config_buf, userbuf, count);
  3183. if (ret) {
  3184. ret = -EFAULT;
  3185. goto out;
  3186. }
  3187. //pr_info("hantrodec config: %s\n", dev->config_buf);
  3188. switch (dev->config_buf[0]) {
  3189. case 'd':
  3190. value = simple_strtoul(&(dev->config_buf[1]), NULL, 10);
  3191. pm_runtime_set_autosuspend_delay(&dev->pdev->dev, value);
  3192. pr_info("Set pm runtime auto suspend delay to %ldms\n", value);
  3193. break;
  3194. default:
  3195. pr_warn("Unsupported config!\n");
  3196. }
  3197. out:
  3198. return ret < 0 ? ret : count;
  3199. }
  3200. static ssize_t encoder_config_read(struct file *filp,
  3201. char __user *userbuf,
  3202. size_t count, loff_t *ppos)
  3203. {
  3204. struct hantrovcmd_dev *dev = hantrovcmd_data;
  3205. memset(dev->config_buf, 0, VC8000E_MAX_CONFIG_LEN);
  3206. return 0;
  3207. }
  3208. static const struct file_operations encoder_debug_ops = {
  3209. .write = encoder_config_write,
  3210. .read = encoder_config_read,
  3211. .open = simple_open,
  3212. .llseek = generic_file_llseek,
  3213. };
  3214. static int encoder_add_debugfs(struct platform_device *pdev)
  3215. {
  3216. root_debugfs_dir = debugfs_create_dir("vc8000e",NULL);
  3217. if (!root_debugfs_dir) {
  3218. dev_err(&pdev->dev, "Failed to create vc8000e debugfs\n");
  3219. return -EINVAL;
  3220. }
  3221. dev_info(&pdev->dev, "Create vc8000e debugfs.\n");
  3222. debugfs_create_file("config", 0600, root_debugfs_dir,
  3223. hantrovcmd_data, &encoder_debug_ops);
  3224. return 0;
  3225. }
  3226. /*-----------------------------------------
  3227. platform register
  3228. -----------------------------------------*/
  3229. static const struct of_device_id hantro_of_match[] = {
  3230. { .compatible = "thead,light-vc8000e", },
  3231. { /* sentinel */ },
  3232. };
  3233. static int check_power_domain(void)
  3234. {
  3235. struct device_node *dn = NULL;
  3236. struct property *info = NULL;
  3237. dn = of_find_node_by_name(NULL, "venc");
  3238. if (dn != NULL)
  3239. info = of_find_property(dn, "power-domains", NULL);
  3240. pr_debug("%s, %d: power gating is %s\n", __func__, __LINE__,
  3241. (info == NULL) ? "disabled" : "enabled");
  3242. return (info == NULL) ? 0 : 1;
  3243. }
  3244. static int encoder_runtime_suspend(struct device *dev)
  3245. {
  3246. struct hantrovcmd_dev *encdev = hantrovcmd_data;
  3247. pr_debug("%s, %d: Disable clock\n", __func__, __LINE__);
  3248. clk_disable_unprepare(encdev->cclk);
  3249. clk_disable_unprepare(encdev->aclk);
  3250. clk_disable_unprepare(encdev->pclk);
  3251. return 0;
  3252. }
  3253. static int encoder_runtime_resume(struct device *dev)
  3254. {
  3255. struct hantrovcmd_dev *encdev = hantrovcmd_data;
  3256. int ret;
  3257. ret = clk_prepare_enable(encdev->cclk);
  3258. if (ret < 0) {
  3259. dev_err(dev, "could not prepare or enable core clock\n");
  3260. return ret;
  3261. }
  3262. ret = clk_prepare_enable(encdev->aclk);
  3263. if (ret < 0) {
  3264. dev_err(dev, "could not prepare or enable axi clock\n");
  3265. clk_disable_unprepare(encdev->cclk);
  3266. return ret;
  3267. }
  3268. ret = clk_prepare_enable(encdev->pclk);
  3269. if (ret < 0) {
  3270. dev_err(dev, "could not prepare or enable apb clock\n");
  3271. clk_disable_unprepare(encdev->cclk);
  3272. clk_disable_unprepare(encdev->aclk);
  3273. return ret;
  3274. }
  3275. if (encdev->has_power_domains) {
  3276. #ifdef HANTROMMU_SUPPORT
  3277. MMURestore(mmu_hwregs);
  3278. #endif
  3279. vcmd_reset();
  3280. }
  3281. pr_debug("%s, %d: Enabled clock\n", __func__, __LINE__);
  3282. return 0;
  3283. }
  3284. int __init hantroenc_vcmd_probe(struct platform_device *pdev)
  3285. {
  3286. int i,k;
  3287. int result;
  3288. struct resource *mem;
  3289. mem = platform_get_resource(pdev,IORESOURCE_MEM,0);
  3290. if(mem->start)
  3291. vcmd_core_array[0].vcmd_base_addr = mem->start;
  3292. vcmd_core_array[0].vcmd_irq = platform_get_irq(pdev,0);
  3293. pr_info("%s:get irq %d\n",__func__,vcmd_core_array[0].vcmd_irq);
  3294. result = vcmd_init(pdev);
  3295. if(result)
  3296. goto err;
  3297. total_vcmd_core_num = 1;
  3298. for (i = 0; i< total_vcmd_core_num; i++)
  3299. {
  3300. pr_info("vcmd: module init - vcmdcore[%d] addr =0x%llx\n",i,
  3301. (long long unsigned int)vcmd_core_array[i].vcmd_base_addr);
  3302. }
  3303. hantrovcmd_data = (struct hantrovcmd_dev *)vmalloc(sizeof(struct hantrovcmd_dev)*total_vcmd_core_num);
  3304. if (hantrovcmd_data == NULL)
  3305. goto err1;
  3306. memset(hantrovcmd_data,0,sizeof(struct hantrovcmd_dev)*total_vcmd_core_num);
  3307. for(k=0;k<MAX_VCMD_TYPE;k++)
  3308. {
  3309. vcmd_type_core_num[k]=0;
  3310. vcmd_position[k]=0;
  3311. for(i=0;i<MAX_VCMD_NUMBER;i++)
  3312. {
  3313. vcmd_manager[k][i]=NULL;
  3314. }
  3315. }
  3316. hantrovcmd_data->pdev = pdev;
  3317. encoder_add_debugfs(pdev);
  3318. hantrovcmd_data->has_power_domains = check_power_domain();
  3319. hantrovcmd_data->aclk = devm_clk_get(&pdev->dev, "aclk");
  3320. if (IS_ERR(hantrovcmd_data->aclk)) {
  3321. dev_err(&pdev->dev, "failed to get axi clock\n");
  3322. goto err;
  3323. }
  3324. hantrovcmd_data->cclk = devm_clk_get(&pdev->dev, "cclk");
  3325. if (IS_ERR(hantrovcmd_data->cclk)) {
  3326. dev_err(&pdev->dev, "failed to get core clock\n");
  3327. goto err;
  3328. }
  3329. hantrovcmd_data->pclk = devm_clk_get(&pdev->dev, "pclk");
  3330. if (IS_ERR(hantrovcmd_data->pclk)) {
  3331. dev_err(&pdev->dev, "failed to get apb clock\n");
  3332. goto err;
  3333. }
  3334. pm_runtime_set_autosuspend_delay(&pdev->dev, VC8000E_PM_TIMEOUT);
  3335. pm_runtime_use_autosuspend(&pdev->dev);
  3336. pm_runtime_enable(&pdev->dev);
  3337. if (!pm_runtime_enabled(&pdev->dev)) {
  3338. if (encoder_runtime_resume(&pdev->dev))
  3339. {
  3340. pm_runtime_disable(&pdev->dev);
  3341. pm_runtime_dont_use_autosuspend(&pdev->dev);
  3342. }
  3343. }
  3344. pm_runtime_resume_and_get(&pdev->dev);
  3345. init_bi_list(&global_process_manager);
  3346. result = ConfigAXIFE(1); //1: normal, 2: bypass
  3347. if(result < 0)
  3348. {
  3349. vcmd_release_AXIFE_IO();
  3350. goto err1;
  3351. }
  3352. result = ConfigMMU();
  3353. if(result < 0)
  3354. {
  3355. vcmd_release_MMU_IO();
  3356. goto err1;
  3357. }
  3358. result = MMU_Kernel_map();
  3359. if(result < 0)
  3360. goto err;
  3361. for(i=0;i<total_vcmd_core_num;i++)
  3362. {
  3363. hantrovcmd_data[i].vcmd_core_cfg = vcmd_core_array[i];
  3364. hantrovcmd_data[i].hwregs = NULL;
  3365. hantrovcmd_data[i].core_id = i;
  3366. hantrovcmd_data[i].working_state= WORKING_STATE_IDLE;
  3367. hantrovcmd_data[i].sw_cmdbuf_rdy_num =0;
  3368. hantrovcmd_data[i].spinlock = &owner_lock_vcmd[i];
  3369. spin_lock_init(&owner_lock_vcmd[i]);
  3370. hantrovcmd_data[i].wait_queue = &wait_queue_vcmd[i];
  3371. init_waitqueue_head(&wait_queue_vcmd[i]);
  3372. hantrovcmd_data[i].wait_abort_queue=&abort_queue_vcmd[i];
  3373. init_waitqueue_head(&abort_queue_vcmd[i]);
  3374. init_bi_list(&hantrovcmd_data[i].list_manager);
  3375. hantrovcmd_data[i].duration_without_int = 0;
  3376. vcmd_manager[vcmd_core_array[i].sub_module_type][vcmd_type_core_num[vcmd_core_array[i].sub_module_type]]=&hantrovcmd_data[i];
  3377. vcmd_type_core_num[vcmd_core_array[i].sub_module_type]++;
  3378. hantrovcmd_data[i].vcmd_reg_mem_busAddress = vcmd_registers_mem_pool.busAddress + i*VCMD_REGISTER_SIZE-base_ddr_addr;
  3379. //next todo: split out
  3380. hantrovcmd_data[i].mmu_vcmd_reg_mem_busAddress = vcmd_registers_mem_pool.mmu_bus_address + i*VCMD_REGISTER_SIZE;
  3381. hantrovcmd_data[i].vcmd_reg_mem_virtualAddress = vcmd_registers_mem_pool.virtualAddress + i*VCMD_REGISTER_SIZE/4;
  3382. hantrovcmd_data[i].vcmd_reg_mem_size = VCMD_REGISTER_SIZE;
  3383. memset(hantrovcmd_data[i].vcmd_reg_mem_virtualAddress,0,VCMD_REGISTER_SIZE);
  3384. }
  3385. if (hantrovcmd_major == 0)
  3386. {
  3387. result = alloc_chrdev_region(&hantrovcmd_devt, 0, 1, "vc8000");
  3388. if (result != 0)
  3389. {
  3390. pr_err("%s: alloc_chrdev_region error\n", __func__);
  3391. goto err1;
  3392. }
  3393. hantrovcmd_major = MAJOR(hantrovcmd_devt);
  3394. hantrovcmd_minor = MINOR(hantrovcmd_devt);
  3395. }
  3396. else
  3397. {
  3398. hantrovcmd_devt = MKDEV(hantrovcmd_major, hantrovcmd_minor);
  3399. result = register_chrdev_region(hantrovcmd_devt, 1, "vc8000");
  3400. if (result)
  3401. {
  3402. pr_err("%s: register_chrdev_region error\n", __func__);
  3403. goto err1;
  3404. }
  3405. }
  3406. hantrovcmd_class = class_create(THIS_MODULE, "vc8000");
  3407. if (IS_ERR(hantrovcmd_class))
  3408. {
  3409. pr_err("%s, %d: class_create error!\n", __func__, __LINE__);
  3410. goto err;
  3411. }
  3412. hantrovcmd_devt = MKDEV(hantrovcmd_major, hantrovcmd_minor);
  3413. cdev_init(&hantrovcmd_cdev, &hantrovcmd_fops);
  3414. result = cdev_add(&hantrovcmd_cdev, hantrovcmd_devt, 1);
  3415. if ( result )
  3416. {
  3417. pr_err("%s, %d: cdev_add error!\n", __func__, __LINE__);
  3418. goto err;
  3419. }
  3420. device_create(hantrovcmd_class, NULL, hantrovcmd_devt,
  3421. NULL, "vc8000");
  3422. result = vcmd_reserve_IO();
  3423. if(result < 0)
  3424. {
  3425. goto err;
  3426. }
  3427. vcmd_reset_asic(hantrovcmd_data);
  3428. /* get the IRQ line */
  3429. for (i=0;i<total_vcmd_core_num;i++)
  3430. {
  3431. if (hantrovcmd_data[i].hwregs==NULL)
  3432. continue;
  3433. if(hantrovcmd_data[i].vcmd_core_cfg.vcmd_irq!= -1)
  3434. {
  3435. result = request_irq(hantrovcmd_data[i].vcmd_core_cfg.vcmd_irq, hantrovcmd_isr,
  3436. #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18))
  3437. SA_INTERRUPT | SA_SHIRQ,
  3438. #else
  3439. IRQF_SHARED,
  3440. #endif
  3441. "vc8000", (void *) &hantrovcmd_data[i]);
  3442. if(result == -EINVAL)
  3443. {
  3444. pr_err("vc8000_vcmd_driver: Bad vcmd_irq number or handler. core_id=%d\n",i);
  3445. vcmd_release_IO();
  3446. goto err;
  3447. }
  3448. else if(result == -EBUSY)
  3449. {
  3450. pr_err("vc8000_vcmd_driver: IRQ <%d> busy, change your config. core_id=%d\n",
  3451. hantrovcmd_data[i].vcmd_core_cfg.vcmd_irq,i);
  3452. vcmd_release_IO();
  3453. goto err;
  3454. }
  3455. }
  3456. else
  3457. {
  3458. pr_info("vc8000_vcmd_driver: IRQ not in use!\n");
  3459. }
  3460. }
  3461. //cmdbuf pool allocation
  3462. //init_vcmd_non_cachable_memory_allocate();
  3463. //for cmdbuf management
  3464. cmdbuf_used_pos=0;
  3465. for(k=0;k<TOTAL_DISCRETE_CMDBUF_NUM;k++)
  3466. {
  3467. cmdbuf_used[k]=0;
  3468. global_cmdbuf_node[k] = NULL;
  3469. }
  3470. //cmdbuf_used[0] not be used, because int vector must non-zero
  3471. cmdbuf_used_residual=TOTAL_DISCRETE_CMDBUF_NUM;
  3472. cmdbuf_used_pos=1;
  3473. cmdbuf_used[0]=1;
  3474. cmdbuf_used_residual -=1;
  3475. pr_info("vc8000_vcmd_driver: module inserted. Major <%d>\n", hantrovcmd_major);
  3476. create_kernel_process_manager();
  3477. for(i=0;i<MAX_VCMD_TYPE;i++)
  3478. {
  3479. if(vcmd_type_core_num[i]==0)
  3480. continue;
  3481. sema_init(&vcmd_reserve_cmdbuf_sem[i], 1);
  3482. }
  3483. #ifdef IRQ_SIMULATION
  3484. for(i=0;i<10000;i++)
  3485. {
  3486. timer_reserve[i].timer=NULL;
  3487. }
  3488. #endif
  3489. #ifndef DYNAMIC_MALLOC_VCMDNODE
  3490. g_cmdbuf_obj_pool = vmalloc(sizeof(struct cmdbuf_obj) * TOTAL_DISCRETE_CMDBUF_NUM);
  3491. g_cmdbuf_node_pool = vmalloc(sizeof(bi_list_node) * TOTAL_DISCRETE_CMDBUF_NUM);
  3492. #endif
  3493. /*read all registers for each type of module for analyzing configuration in cwl*/
  3494. for(i=0;i<MAX_VCMD_TYPE;i++)
  3495. {
  3496. if(vcmd_type_core_num[i]==0)
  3497. continue;
  3498. PDEBUG("hantrovcmd_init: vcmd_core_type is %d\n", i);
  3499. read_main_module_all_registers(i);
  3500. }
  3501. pm_runtime_mark_last_busy(&pdev->dev);
  3502. pm_runtime_put_autosuspend(&pdev->dev);
  3503. return 0;
  3504. err:
  3505. if (root_debugfs_dir) {
  3506. debugfs_remove_recursive(root_debugfs_dir);
  3507. root_debugfs_dir = NULL;
  3508. }
  3509. #ifdef HANTROMMU_SUPPORT
  3510. MMU_Kernel_unmap();
  3511. vcmd_pool_release(pdev);
  3512. #endif
  3513. unregister_chrdev_region(hantrovcmd_devt, 1);
  3514. pm_runtime_mark_last_busy(&pdev->dev);
  3515. pm_runtime_put_autosuspend(&pdev->dev);
  3516. err1:
  3517. if (hantrovcmd_data != NULL)
  3518. vfree(hantrovcmd_data);
  3519. pr_info("vc8000_vcmd_driver: module not inserted\n");
  3520. return result;
  3521. }
  3522. static int hantroenc_vcmd_remove(struct platform_device *pdev)
  3523. {
  3524. int i=0;
  3525. u32 result;
  3526. if (root_debugfs_dir) {
  3527. debugfs_remove_recursive(root_debugfs_dir);
  3528. root_debugfs_dir = NULL;
  3529. }
  3530. pm_runtime_resume_and_get(&pdev->dev);
  3531. for(i=0;i<total_vcmd_core_num;i++)
  3532. {
  3533. if (hantrovcmd_data[i].hwregs==NULL)
  3534. continue;
  3535. //disable interrupt at first
  3536. vcmd_write_reg((const void *) hantrovcmd_data[i].hwregs,VCMD_REGISTER_INT_CTL_OFFSET,0x0000);
  3537. //disable HW
  3538. vcmd_write_reg((const void *) hantrovcmd_data[i].hwregs,VCMD_REGISTER_CONTROL_OFFSET,0x0000);
  3539. //read status register
  3540. result =vcmd_read_reg((const void *) hantrovcmd_data[i].hwregs,VCMD_REGISTER_INT_STATUS_OFFSET);
  3541. //clean status register
  3542. vcmd_write_reg((const void *) hantrovcmd_data[i].hwregs,VCMD_REGISTER_INT_STATUS_OFFSET,result);
  3543. /* free the vcmd IRQ */
  3544. if(hantrovcmd_data[i].vcmd_core_cfg.vcmd_irq != -1)
  3545. {
  3546. free_irq(hantrovcmd_data[i].vcmd_core_cfg.vcmd_irq, (void *)&hantrovcmd_data[i]);
  3547. }
  3548. release_cmdbuf_node_cleanup(&hantrovcmd_data[i].list_manager);
  3549. }
  3550. release_process_node_cleanup(&global_process_manager);
  3551. #ifdef HANTROMMU_SUPPORT
  3552. MMUCleanup(mmu_hwregs);
  3553. #endif
  3554. vcmd_release_IO();
  3555. //release_vcmd_non_cachable_memory();
  3556. MMU_Kernel_unmap();
  3557. vcmd_pool_release(pdev);
  3558. pm_runtime_mark_last_busy(&pdev->dev);
  3559. pm_runtime_put_autosuspend(&pdev->dev);
  3560. pm_runtime_disable(&pdev->dev);
  3561. if (!pm_runtime_status_suspended(&pdev->dev))
  3562. encoder_runtime_suspend(&pdev->dev);
  3563. vfree(hantrovcmd_data);
  3564. cdev_del(&hantrovcmd_cdev);
  3565. device_destroy(hantrovcmd_class, hantrovcmd_devt);
  3566. unregister_chrdev_region(hantrovcmd_devt, 1);
  3567. class_destroy(hantrovcmd_class);
  3568. #ifndef DYNAMIC_MALLOC_VCMDNODE
  3569. if (g_cmdbuf_obj_pool) {
  3570. vfree(g_cmdbuf_obj_pool);
  3571. g_cmdbuf_obj_pool = NULL;
  3572. }
  3573. if (g_cmdbuf_node_pool) {
  3574. vfree(g_cmdbuf_node_pool);
  3575. g_cmdbuf_node_pool = NULL;
  3576. }
  3577. #endif
  3578. pr_info("vc8000_vcmd_driver: module removed\n");
  3579. return 0;
  3580. }
  3581. static const struct dev_pm_ops encoder_runtime_pm_ops = {
  3582. SET_RUNTIME_PM_OPS(encoder_runtime_suspend, encoder_runtime_resume, NULL)
  3583. };
  3584. static struct platform_driver hantroenc_vcmd_driver = {
  3585. .probe = hantroenc_vcmd_probe,
  3586. .remove = hantroenc_vcmd_remove,
  3587. .driver = {
  3588. .name = "encoder_hantroenc",
  3589. .owner = THIS_MODULE,
  3590. .of_match_table = of_match_ptr(hantro_of_match),
  3591. .pm = &encoder_runtime_pm_ops,
  3592. }
  3593. };
  3594. int __init hantroenc_vcmd_init(void)
  3595. {
  3596. int ret = 0;
  3597. pr_debug("enter %s\n",__func__);
  3598. ret = platform_driver_register(&hantroenc_vcmd_driver);
  3599. if(ret)
  3600. {
  3601. pr_err("register platform driver failed!\n");
  3602. }
  3603. return ret;
  3604. }
  3605. void __exit hantroenc_vcmd_cleanup(void)
  3606. {
  3607. pr_debug("enter %s\n",__func__);
  3608. platform_driver_unregister(&hantroenc_vcmd_driver);
  3609. return;
  3610. }
  3611. static int vcmd_reserve_IO(void)
  3612. {
  3613. u32 hwid;
  3614. int i;
  3615. u32 found_hw = 0;
  3616. pr_info("vcmd_reserve_IO: total_vcmd_core_num is %d\n", total_vcmd_core_num);
  3617. for (i=0;i<total_vcmd_core_num;i++)
  3618. {
  3619. hantrovcmd_data[i].hwregs = NULL;
  3620. if(!request_mem_region
  3621. (hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr, hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize, "vc8000_vcmd_driver"))
  3622. {
  3623. pr_info("hantrovcmd: failed to reserve HW regs for vcmd %d\n", i);
  3624. pr_info("hantrovcmd: vcmd_base_addr = 0x%08lx, iosize = %d\n",
  3625. hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr,
  3626. hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize);
  3627. continue;
  3628. }
  3629. #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,17,0))
  3630. hantrovcmd_data[i].hwregs =
  3631. (volatile u8 *) ioremap_nocache(hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr,
  3632. hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize);
  3633. #else
  3634. hantrovcmd_data[i].hwregs =
  3635. (volatile u8 *) ioremap(hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr,
  3636. hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize);
  3637. #endif
  3638. if(hantrovcmd_data[i].hwregs == NULL)
  3639. {
  3640. pr_info("hantrovcmd: failed to ioremap HW regs\n");
  3641. release_mem_region(hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr, hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize);
  3642. continue;
  3643. }
  3644. /*read hwid and check validness and store it*/
  3645. hwid = (u32)ioread32(( void *)hantrovcmd_data[i].hwregs);
  3646. pr_info("vcmd_reserve_IO: hantrovcmd_data[%d].hwregs=0x%p\n",i, hantrovcmd_data[i].hwregs);
  3647. pr_info("hwid=0x%08x\n", hwid);
  3648. hantrovcmd_data[i].hw_version_id = hwid;
  3649. /* check for vcmd HW ID */
  3650. if( ((hwid >> 16) & 0xFFFF) != VCMD_HW_ID )
  3651. {
  3652. pr_info("hantrovcmd: HW not found at 0x%llx\n",
  3653. (long long unsigned int)hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr);
  3654. iounmap(( void *) hantrovcmd_data[i].hwregs);
  3655. release_mem_region(hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr, hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize);
  3656. hantrovcmd_data[i].hwregs = NULL;
  3657. continue;
  3658. }
  3659. found_hw = 1;
  3660. pr_info(
  3661. "hantrovcmd: HW at base <0x%llx> with ID <0x%08x>\n",
  3662. (long long unsigned int)hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr, hwid);
  3663. }
  3664. if (found_hw == 0)
  3665. {
  3666. pr_err("hantrovcmd: NO ANY HW found!!\n");
  3667. return -1;
  3668. }
  3669. return 0;
  3670. }
  3671. static void vcmd_release_IO(void)
  3672. {
  3673. u32 i;
  3674. vcmd_release_AXIFE_IO();
  3675. vcmd_release_MMU_IO();
  3676. for (i=0;i<total_vcmd_core_num;i++)
  3677. {
  3678. if(hantrovcmd_data[i].hwregs)
  3679. {
  3680. iounmap((void *) hantrovcmd_data[i].hwregs);
  3681. release_mem_region(hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr, hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize);
  3682. hantrovcmd_data[i].hwregs = NULL;
  3683. }
  3684. }
  3685. }
  3686. #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18))
  3687. static irqreturn_t hantrovcmd_isr(int irq, void *dev_id, struct pt_regs *regs)
  3688. #else
  3689. static irqreturn_t hantrovcmd_isr(int irq, void *dev_id)
  3690. #endif
  3691. {
  3692. unsigned int handled = 0;
  3693. struct hantrovcmd_dev *dev = (struct hantrovcmd_dev *) dev_id;
  3694. u32 irq_status=0;
  3695. unsigned long flags;
  3696. bi_list_node* new_cmdbuf_node=NULL;
  3697. bi_list_node* base_cmdbuf_node=NULL;
  3698. struct cmdbuf_obj* cmdbuf_obj=NULL;
  3699. size_t exe_cmdbuf_busAddress;
  3700. u32 cmdbuf_processed_num=0;
  3701. u32 cmdbuf_id=0;
  3702. /*If core is not reserved by any user, but irq is received, just clean it*/
  3703. spin_lock_irqsave(dev->spinlock, flags);
  3704. if (dev->list_manager.head==NULL)
  3705. {
  3706. PDEBUG( "hantrovcmd_isr:received IRQ but core has nothing to do.\n");
  3707. irq_status = vcmd_read_reg((const void *)dev->hwregs,VCMD_REGISTER_INT_STATUS_OFFSET);
  3708. vcmd_write_reg((const void *)dev->hwregs,VCMD_REGISTER_INT_STATUS_OFFSET,irq_status);
  3709. spin_unlock_irqrestore(dev->spinlock, flags);
  3710. return IRQ_HANDLED;
  3711. }
  3712. PDEBUG( "hantrovcmd_isr: received IRQ!\n");
  3713. irq_status = vcmd_read_reg((const void *)dev->hwregs,VCMD_REGISTER_INT_STATUS_OFFSET);
  3714. #ifdef VCMD_DEBUG_INTERNAL
  3715. {
  3716. u32 i, fordebug;
  3717. for(i=0;i<ASIC_VCMD_SWREG_AMOUNT;i++)
  3718. {
  3719. fordebug=vcmd_read_reg ((const void *)dev->hwregs, i*4);
  3720. pr_info("vcmd register %d:0x%x\n",i,fordebug);
  3721. }
  3722. }
  3723. #endif
  3724. if(!irq_status)
  3725. {
  3726. //pr_info("hantrovcmd_isr error,irq_status :0x%x",irq_status);
  3727. spin_unlock_irqrestore(dev->spinlock, flags);
  3728. return IRQ_HANDLED;
  3729. }
  3730. PDEBUG( "irq_status of %d is:0x%x\n",dev->core_id,irq_status);
  3731. vcmd_write_reg((const void *)dev->hwregs,VCMD_REGISTER_INT_STATUS_OFFSET,irq_status);
  3732. dev->reg_mirror[VCMD_REGISTER_INT_STATUS_OFFSET/4] = irq_status;
  3733. if((dev->hw_version_id > HW_ID_1_0_C )&&(irq_status&0x3f))
  3734. {
  3735. //if error,read from register directly.
  3736. cmdbuf_id = vcmd_get_register_value((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_CMDBUF_EXECUTING_ID);
  3737. if(cmdbuf_id>=TOTAL_DISCRETE_CMDBUF_NUM)
  3738. {
  3739. pr_err("hantrovcmd_isr error cmdbuf_id greater than the ceiling !!\n");
  3740. spin_unlock_irqrestore(dev->spinlock, flags);
  3741. return IRQ_HANDLED;
  3742. }
  3743. }
  3744. else if((dev->hw_version_id > HW_ID_1_0_C ))
  3745. {
  3746. //read cmdbuf id from ddr
  3747. #ifdef VCMD_DEBUG_INTERNAL
  3748. {
  3749. u32 i, fordebug;
  3750. pr_info("ddr vcmd register phy_addr=0x%x\n",dev->vcmd_reg_mem_busAddress);
  3751. pr_info("ddr vcmd register virt_addr=0x%x\n",dev->vcmd_reg_mem_virtualAddress);
  3752. for(i=0;i<ASIC_VCMD_SWREG_AMOUNT;i++)
  3753. {
  3754. fordebug=*(dev->vcmd_reg_mem_virtualAddress+i);
  3755. pr_info("ddr vcmd register %d:0x%x\n",i,fordebug);
  3756. }
  3757. }
  3758. #endif
  3759. cmdbuf_id = *(dev->vcmd_reg_mem_virtualAddress+EXECUTING_CMDBUF_ID_ADDR);
  3760. pr_debug("hantrovcmd_isr: cmdbuf_id %d from virtual!!\n", cmdbuf_id);
  3761. if(cmdbuf_id>=TOTAL_DISCRETE_CMDBUF_NUM)
  3762. {
  3763. pr_err("hantrovcmd_isr error cmdbuf_id greater than the ceiling !!\n");
  3764. spin_unlock_irqrestore(dev->spinlock, flags);
  3765. return IRQ_HANDLED;
  3766. }
  3767. }
  3768. if(vcmd_get_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_RESET))
  3769. {
  3770. //reset error,all cmdbuf that is not done will be run again.
  3771. new_cmdbuf_node = dev->list_manager.head;
  3772. dev->working_state = WORKING_STATE_IDLE;
  3773. //find the first run_done=0
  3774. while(1)
  3775. {
  3776. if(new_cmdbuf_node==NULL)
  3777. break;
  3778. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3779. if((cmdbuf_obj->cmdbuf_run_done == 0))
  3780. break;
  3781. new_cmdbuf_node = new_cmdbuf_node->next;
  3782. }
  3783. base_cmdbuf_node = new_cmdbuf_node;
  3784. vcmd_delink_cmdbuf(dev,base_cmdbuf_node);
  3785. vcmd_link_cmdbuf(dev,base_cmdbuf_node);
  3786. if(dev->sw_cmdbuf_rdy_num !=0)
  3787. {
  3788. //restart new command
  3789. vcmd_start(dev,base_cmdbuf_node);
  3790. }
  3791. handled++;
  3792. spin_unlock_irqrestore(dev->spinlock, flags);
  3793. return IRQ_HANDLED;
  3794. }
  3795. if(vcmd_get_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_ABORT))
  3796. {
  3797. //abort error,don't need to reset
  3798. new_cmdbuf_node = dev->list_manager.head;
  3799. dev->working_state = WORKING_STATE_IDLE;
  3800. if(dev->hw_version_id > HW_ID_1_0_C )
  3801. {
  3802. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  3803. if(new_cmdbuf_node==NULL)
  3804. {
  3805. pr_err("hantrovcmd_isr error cmdbuf_id !!\n");
  3806. spin_unlock_irqrestore(dev->spinlock, flags);
  3807. return IRQ_HANDLED;
  3808. }
  3809. }
  3810. else
  3811. {
  3812. exe_cmdbuf_busAddress = VCMDGetAddrRegisterValue((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR);
  3813. //find the cmdbuf that tigers ABORT
  3814. while(1)
  3815. {
  3816. if(new_cmdbuf_node==NULL)
  3817. {
  3818. spin_unlock_irqrestore(dev->spinlock, flags);
  3819. return IRQ_HANDLED;
  3820. }
  3821. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3822. if((((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr) <=exe_cmdbuf_busAddress)&&(((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr+cmdbuf_obj->cmdbuf_size) >exe_cmdbuf_busAddress)) ) &&(cmdbuf_obj->cmdbuf_run_done==0))
  3823. break;
  3824. new_cmdbuf_node = new_cmdbuf_node->next;
  3825. }
  3826. }
  3827. base_cmdbuf_node = new_cmdbuf_node;
  3828. // this cmdbuf and cmdbufs prior to itself, run_done = 1
  3829. while(1)
  3830. {
  3831. if(new_cmdbuf_node==NULL)
  3832. break;
  3833. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3834. if((cmdbuf_obj->cmdbuf_run_done==0))
  3835. {
  3836. cmdbuf_obj->cmdbuf_run_done=1;
  3837. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  3838. cmdbuf_processed_num++;
  3839. }
  3840. else
  3841. break;
  3842. new_cmdbuf_node = new_cmdbuf_node->previous;
  3843. }
  3844. base_cmdbuf_node=base_cmdbuf_node->next;
  3845. vcmd_delink_cmdbuf(dev,base_cmdbuf_node);
  3846. if(software_triger_abort==0)
  3847. {
  3848. //for QCFE
  3849. vcmd_link_cmdbuf(dev,base_cmdbuf_node);
  3850. if(dev->sw_cmdbuf_rdy_num !=0)
  3851. {
  3852. //restart new command
  3853. vcmd_start(dev,base_cmdbuf_node);
  3854. }
  3855. }
  3856. spin_unlock_irqrestore(dev->spinlock, flags);
  3857. if(cmdbuf_processed_num)
  3858. wake_up_interruptible_all(dev->wait_queue);
  3859. //to let high priority cmdbuf be inserted
  3860. wake_up_interruptible_all(dev->wait_abort_queue);
  3861. handled++;
  3862. return IRQ_HANDLED;
  3863. }
  3864. if(vcmd_get_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_BUSERR))
  3865. {
  3866. //bus error, don't need to reset where to record status?
  3867. new_cmdbuf_node = dev->list_manager.head;
  3868. dev->working_state = WORKING_STATE_IDLE;
  3869. if(dev->hw_version_id > HW_ID_1_0_C )
  3870. {
  3871. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  3872. if(new_cmdbuf_node==NULL)
  3873. {
  3874. pr_err("hantrovcmd_isr error cmdbuf_id !!\n");
  3875. spin_unlock_irqrestore(dev->spinlock, flags);
  3876. return IRQ_HANDLED;
  3877. }
  3878. }
  3879. else
  3880. {
  3881. exe_cmdbuf_busAddress = VCMDGetAddrRegisterValue((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR);
  3882. //find the buserr cmdbuf
  3883. while(1)
  3884. {
  3885. if(new_cmdbuf_node==NULL)
  3886. {
  3887. spin_unlock_irqrestore(dev->spinlock, flags);
  3888. return IRQ_HANDLED;
  3889. }
  3890. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3891. if((((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr) <=exe_cmdbuf_busAddress)&&(((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr+cmdbuf_obj->cmdbuf_size) >exe_cmdbuf_busAddress)) ) &&(cmdbuf_obj->cmdbuf_run_done==0))
  3892. break;
  3893. new_cmdbuf_node = new_cmdbuf_node->next;
  3894. }
  3895. }
  3896. base_cmdbuf_node = new_cmdbuf_node;
  3897. // this cmdbuf and cmdbufs prior to itself, run_done = 1
  3898. while(1)
  3899. {
  3900. if(new_cmdbuf_node==NULL)
  3901. break;
  3902. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3903. if((cmdbuf_obj->cmdbuf_run_done==0))
  3904. {
  3905. cmdbuf_obj->cmdbuf_run_done=1;
  3906. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  3907. cmdbuf_processed_num++;
  3908. }
  3909. else
  3910. break;
  3911. new_cmdbuf_node = new_cmdbuf_node->previous;
  3912. }
  3913. new_cmdbuf_node = base_cmdbuf_node;
  3914. if(new_cmdbuf_node!=NULL)
  3915. {
  3916. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3917. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_BUSERR;
  3918. }
  3919. base_cmdbuf_node=base_cmdbuf_node->next;
  3920. vcmd_delink_cmdbuf(dev,base_cmdbuf_node);
  3921. vcmd_link_cmdbuf(dev,base_cmdbuf_node);
  3922. if(dev->sw_cmdbuf_rdy_num !=0)
  3923. {
  3924. //restart new command
  3925. vcmd_start(dev,base_cmdbuf_node);
  3926. }
  3927. spin_unlock_irqrestore(dev->spinlock, flags);
  3928. if(cmdbuf_processed_num)
  3929. wake_up_interruptible_all(dev->wait_queue);
  3930. handled++;
  3931. return IRQ_HANDLED;
  3932. }
  3933. if(vcmd_get_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_TIMEOUT))
  3934. {
  3935. //time out,need to reset
  3936. new_cmdbuf_node = dev->list_manager.head;
  3937. dev->working_state = WORKING_STATE_IDLE;
  3938. if(dev->hw_version_id > HW_ID_1_0_C )
  3939. {
  3940. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  3941. if(new_cmdbuf_node==NULL)
  3942. {
  3943. pr_err("hantrovcmd_isr error cmdbuf_id !!\n");
  3944. spin_unlock_irqrestore(dev->spinlock, flags);
  3945. return IRQ_HANDLED;
  3946. }
  3947. }
  3948. else
  3949. {
  3950. exe_cmdbuf_busAddress = VCMDGetAddrRegisterValue((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR);
  3951. //find the timeout cmdbuf
  3952. while(1)
  3953. {
  3954. if(new_cmdbuf_node==NULL)
  3955. {
  3956. spin_unlock_irqrestore(dev->spinlock, flags);
  3957. return IRQ_HANDLED;
  3958. }
  3959. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3960. if((((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr) <=exe_cmdbuf_busAddress)&&(((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr+cmdbuf_obj->cmdbuf_size) >exe_cmdbuf_busAddress)) ) &&(cmdbuf_obj->cmdbuf_run_done==0))
  3961. break;
  3962. new_cmdbuf_node = new_cmdbuf_node->next;
  3963. }
  3964. }
  3965. base_cmdbuf_node = new_cmdbuf_node;
  3966. new_cmdbuf_node = new_cmdbuf_node->previous;
  3967. // this cmdbuf and cmdbufs prior to itself, run_done = 1
  3968. while(1)
  3969. {
  3970. if(new_cmdbuf_node==NULL)
  3971. break;
  3972. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3973. if((cmdbuf_obj->cmdbuf_run_done==0))
  3974. {
  3975. cmdbuf_obj->cmdbuf_run_done=1;
  3976. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  3977. cmdbuf_processed_num++;
  3978. }
  3979. else
  3980. break;
  3981. new_cmdbuf_node = new_cmdbuf_node->previous;
  3982. }
  3983. vcmd_delink_cmdbuf(dev,base_cmdbuf_node);
  3984. vcmd_link_cmdbuf(dev,base_cmdbuf_node);
  3985. if(dev->sw_cmdbuf_rdy_num !=0)
  3986. {
  3987. //reset
  3988. vcmd_reset_current_asic(dev);
  3989. //restart new command
  3990. vcmd_start(dev,base_cmdbuf_node);
  3991. }
  3992. spin_unlock_irqrestore(dev->spinlock, flags);
  3993. if(cmdbuf_processed_num)
  3994. wake_up_interruptible_all(dev->wait_queue);
  3995. handled++;
  3996. return IRQ_HANDLED;
  3997. }
  3998. if(vcmd_get_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_CMDERR))
  3999. {
  4000. //command error,don't need to reset
  4001. new_cmdbuf_node = dev->list_manager.head;
  4002. dev->working_state = WORKING_STATE_IDLE;
  4003. if(dev->hw_version_id > HW_ID_1_0_C )
  4004. {
  4005. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  4006. if(new_cmdbuf_node==NULL)
  4007. {
  4008. pr_err("hantrovcmd_isr error cmdbuf_id %d!!\n", cmdbuf_id);
  4009. spin_unlock_irqrestore(dev->spinlock, flags);
  4010. return IRQ_HANDLED;
  4011. }
  4012. }
  4013. else
  4014. {
  4015. exe_cmdbuf_busAddress = VCMDGetAddrRegisterValue((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR);
  4016. //find the cmderror cmdbuf
  4017. while(1)
  4018. {
  4019. if(new_cmdbuf_node==NULL)
  4020. {
  4021. spin_unlock_irqrestore(dev->spinlock, flags);
  4022. return IRQ_HANDLED;
  4023. }
  4024. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  4025. if((((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr) <=exe_cmdbuf_busAddress)&&(((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr+cmdbuf_obj->cmdbuf_size) >exe_cmdbuf_busAddress)) ) &&(cmdbuf_obj->cmdbuf_run_done==0))
  4026. break;
  4027. new_cmdbuf_node = new_cmdbuf_node->next;
  4028. }
  4029. }
  4030. base_cmdbuf_node = new_cmdbuf_node;
  4031. // this cmdbuf and cmdbufs prior to itself, run_done = 1
  4032. while(1)
  4033. {
  4034. if(new_cmdbuf_node==NULL)
  4035. break;
  4036. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  4037. if((cmdbuf_obj->cmdbuf_run_done==0))
  4038. {
  4039. cmdbuf_obj->cmdbuf_run_done=1;
  4040. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  4041. cmdbuf_processed_num++;
  4042. }
  4043. else
  4044. break;
  4045. new_cmdbuf_node = new_cmdbuf_node->previous;
  4046. }
  4047. new_cmdbuf_node = base_cmdbuf_node;
  4048. if(new_cmdbuf_node!=NULL)
  4049. {
  4050. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  4051. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_CMDERR;//cmderr
  4052. }
  4053. base_cmdbuf_node=base_cmdbuf_node->next;
  4054. vcmd_delink_cmdbuf(dev,base_cmdbuf_node);
  4055. vcmd_link_cmdbuf(dev,base_cmdbuf_node);
  4056. if(dev->sw_cmdbuf_rdy_num !=0)
  4057. {
  4058. //restart new command
  4059. vcmd_start(dev,base_cmdbuf_node);
  4060. }
  4061. spin_unlock_irqrestore(dev->spinlock, flags);
  4062. if(cmdbuf_processed_num)
  4063. wake_up_interruptible_all(dev->wait_queue);
  4064. handled++;
  4065. return IRQ_HANDLED;
  4066. }
  4067. if(vcmd_get_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_ENDCMD))
  4068. {
  4069. //end command interrupt
  4070. new_cmdbuf_node = dev->list_manager.head;
  4071. dev->working_state = WORKING_STATE_IDLE;
  4072. if(dev->hw_version_id > HW_ID_1_0_C )
  4073. {
  4074. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  4075. if(new_cmdbuf_node==NULL)
  4076. {
  4077. pr_err("hantrovcmd_isr error cmdbuf_id !!\n");
  4078. spin_unlock_irqrestore(dev->spinlock, flags);
  4079. return IRQ_HANDLED;
  4080. }
  4081. }
  4082. else
  4083. {
  4084. //find the end cmdbuf
  4085. while(1)
  4086. {
  4087. if(new_cmdbuf_node==NULL)
  4088. {
  4089. spin_unlock_irqrestore(dev->spinlock, flags);
  4090. return IRQ_HANDLED;
  4091. }
  4092. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  4093. if((cmdbuf_obj->has_end_cmdbuf == 1)&&(cmdbuf_obj->cmdbuf_run_done==0))
  4094. break;
  4095. new_cmdbuf_node = new_cmdbuf_node->next;
  4096. }
  4097. }
  4098. base_cmdbuf_node = new_cmdbuf_node;
  4099. // this cmdbuf and cmdbufs prior to itself, run_done = 1
  4100. while(1)
  4101. {
  4102. if(new_cmdbuf_node==NULL)
  4103. break;
  4104. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  4105. if((cmdbuf_obj->cmdbuf_run_done==0))
  4106. {
  4107. cmdbuf_obj->cmdbuf_run_done=1;
  4108. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  4109. cmdbuf_processed_num++;
  4110. }
  4111. else
  4112. break;
  4113. new_cmdbuf_node = new_cmdbuf_node->previous;
  4114. }
  4115. base_cmdbuf_node=base_cmdbuf_node->next;
  4116. vcmd_delink_cmdbuf(dev,base_cmdbuf_node);
  4117. vcmd_link_cmdbuf(dev,base_cmdbuf_node);
  4118. if(dev->sw_cmdbuf_rdy_num !=0)
  4119. {
  4120. //restart new command
  4121. vcmd_start(dev,base_cmdbuf_node);
  4122. }
  4123. spin_unlock_irqrestore(dev->spinlock, flags);
  4124. if(cmdbuf_processed_num)
  4125. wake_up_interruptible_all(dev->wait_queue);
  4126. handled++;
  4127. return IRQ_HANDLED;
  4128. }
  4129. if(dev->hw_version_id <= HW_ID_1_0_C )
  4130. cmdbuf_id = vcmd_get_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_INTCMD);
  4131. if(cmdbuf_id)
  4132. {
  4133. if(dev->hw_version_id <= HW_ID_1_0_C )
  4134. {
  4135. if(cmdbuf_id>=TOTAL_DISCRETE_CMDBUF_NUM)
  4136. {
  4137. pr_err("hantrovcmd_isr error cmdbuf_id greater than the ceiling !!\n");
  4138. spin_unlock_irqrestore(dev->spinlock, flags);
  4139. return IRQ_HANDLED;
  4140. }
  4141. }
  4142. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  4143. if(new_cmdbuf_node==NULL)
  4144. {
  4145. pr_err("hantrovcmd_isr error cmdbuf_id !!\n");
  4146. spin_unlock_irqrestore(dev->spinlock, flags);
  4147. return IRQ_HANDLED;
  4148. }
  4149. // interrupt cmdbuf and cmdbufs prior to itself, run_done = 1
  4150. while(1)
  4151. {
  4152. if(new_cmdbuf_node==NULL)
  4153. break;
  4154. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  4155. if((cmdbuf_obj->cmdbuf_run_done==0))
  4156. {
  4157. cmdbuf_obj->cmdbuf_run_done=1;
  4158. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  4159. cmdbuf_processed_num++;
  4160. }
  4161. else
  4162. break;
  4163. new_cmdbuf_node = new_cmdbuf_node->previous;
  4164. }
  4165. handled++;
  4166. }
  4167. spin_unlock_irqrestore(dev->spinlock, flags);
  4168. if(cmdbuf_processed_num)
  4169. wake_up_interruptible_all(dev->wait_queue);
  4170. if(!handled)
  4171. {
  4172. PDEBUG("IRQ received, but not hantro's!\n");
  4173. }
  4174. return IRQ_HANDLED;
  4175. }
  4176. static void vcmd_reset_asic(struct hantrovcmd_dev * dev)
  4177. {
  4178. int i,n;
  4179. u32 result;
  4180. for (n=0;n<total_vcmd_core_num;n++)
  4181. {
  4182. if(dev[n].hwregs!=NULL)
  4183. {
  4184. //disable interrupt at first
  4185. vcmd_write_reg((const void *)dev[n].hwregs,VCMD_REGISTER_INT_CTL_OFFSET,0x0000);
  4186. //reset all
  4187. vcmd_write_reg((const void *)dev[n].hwregs,VCMD_REGISTER_CONTROL_OFFSET,0x0002);
  4188. //read status register
  4189. result =vcmd_read_reg((const void *)dev[n].hwregs,VCMD_REGISTER_INT_STATUS_OFFSET);
  4190. //clean status register
  4191. vcmd_write_reg((const void *)dev[n].hwregs,VCMD_REGISTER_INT_STATUS_OFFSET,result);
  4192. for(i = VCMD_REGISTER_CONTROL_OFFSET; i < dev[n].vcmd_core_cfg.vcmd_iosize; i += 4)
  4193. {
  4194. //set all register 0
  4195. vcmd_write_reg((const void *)dev[n].hwregs,i,0x0000);
  4196. }
  4197. //enable all interrupt
  4198. vcmd_write_reg((const void *)dev[n].hwregs,VCMD_REGISTER_INT_CTL_OFFSET,0xffffffff);
  4199. // gate all external interrupt
  4200. vcmd_write_reg((const void *)dev[n].hwregs,VCMD_REGISTER_EXT_INT_GATE_OFFSET,0xffffffff);
  4201. }
  4202. }
  4203. }
  4204. static void vcmd_reset_current_asic(struct hantrovcmd_dev * dev)
  4205. {
  4206. u32 result;
  4207. if(dev->hwregs!=NULL)
  4208. {
  4209. //disable interrupt at first
  4210. vcmd_write_reg((const void *)dev->hwregs,VCMD_REGISTER_INT_CTL_OFFSET,0x0000);
  4211. //reset all
  4212. vcmd_write_reg((const void *)dev->hwregs,VCMD_REGISTER_CONTROL_OFFSET,0x0002);
  4213. //read status register
  4214. result =vcmd_read_reg((const void *)dev->hwregs,VCMD_REGISTER_INT_STATUS_OFFSET);
  4215. //clean status register
  4216. vcmd_write_reg((const void *)dev->hwregs,VCMD_REGISTER_INT_STATUS_OFFSET,result);
  4217. }
  4218. }
  4219. #ifdef VCMD_DEBUG_INTERNAL
  4220. static void printk_vcmd_register_debug(const void *hwregs, char * info)
  4221. {
  4222. u32 i, fordebug;
  4223. for(i=0;i<ASIC_VCMD_SWREG_AMOUNT;i++)
  4224. {
  4225. fordebug=vcmd_read_reg ((const void *)hwregs, i*4);
  4226. pr_info("%s vcmd register %d:0x%x\n",info,i,fordebug);
  4227. }
  4228. }
  4229. #endif
  4230. static void vcmd_reset(void)
  4231. {
  4232. if (hantrovcmd_data) {
  4233. int i;
  4234. for(i=0;i<total_vcmd_core_num;i++) {
  4235. hantrovcmd_data[i].working_state = WORKING_STATE_IDLE;
  4236. hantrovcmd_data[i].sw_cmdbuf_rdy_num = 0;
  4237. }
  4238. vcmd_reset_asic(hantrovcmd_data);
  4239. }
  4240. }