hantro_mmu.c 58 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2014 - 2021 VERISILICON
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (C) 2014 - 2021 VERISILICON
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program; if not, write to the Free Software Foundation,
  43. * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  44. *
  45. *****************************************************************************
  46. *
  47. * Note: This software is released under dual MIT and GPL licenses. A
  48. * recipient may use this file under the terms of either the MIT license or
  49. * GPL License. If you wish to use only one license not the other, you can
  50. * indicate your decision by deleting one of the above license notices in your
  51. * version of this file.
  52. *
  53. *****************************************************************************/
  54. #ifdef __FREERTOS__
  55. #include "base_type.h"
  56. #include "dev_common_freertos.h"
  57. #include "io_tools.h"
  58. #elif defined(__linux__)
  59. #include <linux/version.h>
  60. #include <linux/slab.h>
  61. #include <linux/vmalloc.h>
  62. #include <linux/module.h>
  63. #include <linux/init.h>
  64. #include <linux/kernel.h>
  65. #include <linux/debugfs.h>
  66. #include <linux/types.h>
  67. #include <linux/device.h>
  68. #include <linux/pagemap.h>
  69. #include <linux/sched.h>
  70. #include <stddef.h>
  71. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,10,0))
  72. #include <linux/dma-map-ops.h>
  73. #else
  74. #include <linux/dma-contiguous.h>
  75. #endif
  76. #include <linux/platform_device.h>
  77. #include <linux/mod_devicetable.h>
  78. #include <linux/dma-buf.h>
  79. #include <asm/io.h>
  80. #endif
  81. #include "hantrommu.h"
  82. MODULE_DESCRIPTION("Verisilicon VPU Driver");
  83. MODULE_LICENSE("GPL");
  84. #ifndef NULL
  85. #ifdef __cplusplus
  86. #define NULL 0
  87. #else
  88. #define NULL ((void *)0)
  89. #endif
  90. #endif
  91. /*******************************************************************************
  92. ***** New MMU Defination *******************************************************/
  93. #define MMU_MTLB_SHIFT 22
  94. #define MMU_STLB_4K_SHIFT 12
  95. #define MMU_STLB_64K_SHIFT 16
  96. #define MMU_MTLB_BITS (32 - MMU_MTLB_SHIFT)
  97. #define MMU_PAGE_4K_BITS MMU_STLB_4K_SHIFT
  98. #define MMU_STLB_4K_BITS (32 - MMU_MTLB_BITS - MMU_PAGE_4K_BITS)
  99. #define MMU_PAGE_64K_BITS MMU_STLB_64K_SHIFT
  100. #define MMU_STLB_64K_BITS (32 - MMU_MTLB_BITS - MMU_PAGE_64K_BITS)
  101. #define MMU_MTLB_ENTRY_NUM (1 << MMU_MTLB_BITS)
  102. #define MMU_MTLB_SIZE (MMU_MTLB_ENTRY_NUM << 2)
  103. #define MMU_STLB_4K_ENTRY_NUM (1 << MMU_STLB_4K_BITS)
  104. #define MMU_STLB_4K_SIZE (MMU_STLB_4K_ENTRY_NUM << 2)
  105. #define MMU_PAGE_4K_SIZE (1 << MMU_STLB_4K_SHIFT)
  106. #define MMU_STLB_64K_ENTRY_NUM (1 << MMU_STLB_64K_BITS)
  107. #define MMU_STLB_64K_SIZE (MMU_STLB_64K_ENTRY_NUM << 2)
  108. #define MMU_PAGE_64K_SIZE (1 << MMU_STLB_64K_SHIFT)
  109. #define MMU_MTLB_MASK (~((1U << MMU_MTLB_SHIFT)-1))
  110. #define MMU_STLB_4K_MASK ((~0U << MMU_STLB_4K_SHIFT) ^ MMU_MTLB_MASK)
  111. #define MMU_PAGE_4K_MASK (MMU_PAGE_4K_SIZE - 1)
  112. #define MMU_STLB_64K_MASK ((~((1U << MMU_STLB_64K_SHIFT)-1)) ^ MMU_MTLB_MASK)
  113. #define MMU_PAGE_64K_MASK (MMU_PAGE_64K_SIZE - 1)
  114. /* Page offset definitions. */
  115. #define MMU_OFFSET_4K_BITS (32 - MMU_MTLB_BITS - MMU_STLB_4K_BITS)
  116. #define MMU_OFFSET_4K_MASK ((1U << MMU_OFFSET_4K_BITS) - 1)
  117. #define MMU_OFFSET_16K_BITS (32 - MMU_MTLB_BITS - MMU_STLB_16K_BITS)
  118. #define MMU_OFFSET_16K_MASK ((1U << MMU_OFFSET_16K_BITS) - 1)
  119. #define MMU_MTLB_ENTRY_HINTS_BITS 6
  120. #define MMU_MTLB_ENTRY_STLB_MASK (~((1U << MMU_MTLB_ENTRY_HINTS_BITS) - 1))
  121. #define MMU_MTLB_PRESENT 0x00000001
  122. #define MMU_MTLB_EXCEPTION 0x00000002
  123. #define MMU_MTLB_4K_PAGE 0x00000000
  124. #define MMU_STLB_PRESENT 0x00000001
  125. #define MMU_STLB_EXCEPTION 0x00000002
  126. #define MMU_STLB_4K_PAGE 0x00000000
  127. #define MMU_FALSE 0
  128. #define MMU_TRUE 1
  129. #define MMU_ERR_OS_FAIL (0xffff)
  130. #define MMU_EFAULT MMU_ERR_OS_FAIL
  131. #define MMU_ENOTTY MMU_ERR_OS_FAIL
  132. #define MMU_INFINITE ((u32) ~0U)
  133. #define MAX_NOPAGED_SIZE 0x20000
  134. #define MMU_SUPPRESS_OOM_MESSAGE 1
  135. #if MMU_SUPPRESS_OOM_MESSAGE
  136. #define MMU_NOWARN __GFP_NOWARN
  137. #else
  138. #define MMU_NOWARN 0
  139. #endif
  140. #define MMU_IS_ERROR(status) (status < 0)
  141. #define MMU_NO_ERROR(status) (status >= 0)
  142. #define MMU_IS_SUCCESS(status) (status == MMU_STATUS_OK)
  143. #undef MMUDEBUG
  144. #ifdef HANTROMMU_DEBUG
  145. # ifdef __KERNEL__
  146. # define MMUDEBUG(fmt, args...) printk( KERN_INFO "hantrommu: " fmt, ## args)
  147. # else
  148. # define MMUDEBUG(fmt, args...) fprintf(stderr, fmt, ## args)
  149. # endif
  150. #else
  151. # define MMUDEBUG(fmt, args...)
  152. #endif
  153. #define MMU_ON_ERROR(func) \
  154. do { \
  155. status = func; \
  156. if (MMU_IS_ERROR(status)){ \
  157. goto onerror; \
  158. } \
  159. }while (MMU_FALSE)
  160. #define WritePageEntry(page_entry, entry_value) \
  161. *(unsigned int *)(page_entry) =(unsigned int)(entry_value)
  162. #define ReadPageEntry(page_entry) *(unsigned int *)(page_entry)
  163. #define DRIVER_NAME "hantroencdma"
  164. /* simple map mode: generate mmu address which is same as input bus address*/
  165. unsigned int simple_map = 0;
  166. /* this shift should be an integral multiple of mmu page size(4096).
  167. It can generate a mmu address shift in simple map mode*/
  168. unsigned int map_shift = 0;
  169. /* module_param(name, type, perm) */
  170. module_param(simple_map, uint, 0);
  171. module_param(map_shift, uint, 0);
  172. enum MMURegion {
  173. MMU_REGION_IN,
  174. MMU_REGION_OUT,
  175. MMU_REGION_PRIVATE,
  176. MMU_REGION_PUB,
  177. MMU_REGION_COUNT
  178. };
  179. struct MMUNode {
  180. void *buf_virtual_address;
  181. unsigned int buf_bus_address; /* used in kernel map mode */
  182. int mtlb_start;
  183. int stlb_start;
  184. int mtlb_end;
  185. int stlb_end;
  186. unsigned int page_count;
  187. int process_id;
  188. struct file* filp;
  189. struct MMUNode *next;
  190. struct MMUNode *prev;
  191. };
  192. struct MMUDDRRegion {
  193. unsigned long long physical_address;
  194. unsigned long long virtual_address;
  195. unsigned int page_count;
  196. void *node_mutex;
  197. struct MMUNode *simple_map_head;
  198. struct MMUNode *simple_map_tail;
  199. struct MMUNode *free_map_head;
  200. struct MMUNode *map_head;
  201. struct MMUNode *free_map_tail;
  202. struct MMUNode *map_tail;
  203. };
  204. struct MMU {
  205. void *page_table_mutex;
  206. /* Master TLB information. */
  207. unsigned int mtlb_size;
  208. unsigned long long mtlb_physical;
  209. void *mtlb_virtual;
  210. unsigned int mtlb_entries;
  211. int enabled;
  212. unsigned int stlb_size;
  213. unsigned long long stlb_physical;
  214. void *stlb_virtual;
  215. struct MMUDDRRegion region[MMU_REGION_COUNT];
  216. unsigned int page_table_array_size;
  217. unsigned long long page_table_array_physical;
  218. void *page_table_array;
  219. };
  220. static struct MMU *g_mmu = NULL;
  221. extern unsigned long gBaseDDRHw;
  222. unsigned int mmu_enable = MMU_FALSE;
  223. static unsigned int mmu_init = MMU_FALSE;
  224. extern unsigned int pcie;
  225. static unsigned int region_in_mmu_start = REGION_IN_MMU_START;
  226. static unsigned int region_in_mmu_end = REGION_IN_MMU_END;
  227. static unsigned int region_out_mmu_start = REGION_OUT_MMU_START;
  228. static unsigned int region_out_mmu_end = REGION_OUT_MMU_END;
  229. static unsigned int region_private_mmu_start = REGION_PRIVATE_MMU_START;
  230. static unsigned int region_private_mmu_end = REGION_PRIVATE_MMU_END;
  231. static const struct platform_device_info hantro_platform_info = {
  232. .name = DRIVER_NAME,
  233. .id = -1,
  234. .dma_mask = DMA_BIT_MASK(32),
  235. };
  236. static int hantro_drm_probe(struct platform_device *pdev)
  237. {
  238. int result;
  239. struct device *dev = &pdev->dev;
  240. (void) dev;
  241. (void) result;
  242. return 0;
  243. }
  244. static int hantro_drm_remove(struct platform_device *pdev)
  245. {
  246. struct device *dev = &pdev->dev;
  247. (void) dev;
  248. return 0;
  249. }
  250. static const struct platform_device_id hantro_drm_platform_ids[] = {
  251. {
  252. .name = DRIVER_NAME,
  253. },
  254. {/* sentinel */ },
  255. };
  256. static const struct of_device_id hantro_of_match[] = {
  257. { .compatible = "thead,light-vc8000e-mmu", },
  258. {/* sentinel */}
  259. };
  260. static struct platform_driver hantro_drm_platform_driver = {
  261. .probe = hantro_drm_probe,
  262. .remove = hantro_drm_remove,
  263. .driver = {
  264. .name = DRIVER_NAME,
  265. .owner = THIS_MODULE,
  266. .of_match_table = hantro_of_match,
  267. },
  268. .id_table = hantro_drm_platform_ids,
  269. };
  270. struct platform_device *platformdev;
  271. static enum MMUStatus ZeroMemory(void *memory, unsigned int bytes) {
  272. memset(memory, 0, bytes);
  273. return MMU_STATUS_OK;
  274. }
  275. static enum MMUStatus AllocateMemory(unsigned int bytes, void **memory){
  276. void *pointer;
  277. enum MMUStatus status;
  278. if (bytes > MAX_NOPAGED_SIZE) {
  279. pointer = (void*) vmalloc(bytes);
  280. MMUDEBUG(" *****VMALLOC size*****%d\n", bytes);
  281. } else {
  282. pointer = (void*) kmalloc(bytes, GFP_KERNEL | MMU_NOWARN);
  283. MMUDEBUG(" *****KMALLOC size*****%d\n", bytes);
  284. }
  285. if (pointer == NULL) {
  286. /* Out of memory. */
  287. status = MMU_STATUS_OUT_OF_MEMORY;
  288. goto onerror;
  289. }
  290. /* Return pointer to the memory allocation. */
  291. *memory = pointer;
  292. return MMU_STATUS_OK;
  293. onerror:
  294. /* Return the status. */
  295. return status;
  296. }
  297. static enum MMUStatus FreeMemory(void *memory) {
  298. /* Free the memory from the OS pool. */
  299. if (is_vmalloc_addr(memory)) {
  300. MMUDEBUG(" *****VFREE*****%p\n", memory);
  301. vfree(memory);
  302. } else {
  303. MMUDEBUG(" *****KFREE*****%p\n", memory);
  304. kfree(memory);
  305. }
  306. return MMU_STATUS_OK;
  307. }
  308. static enum MMUStatus SMDeleteNode(struct MMUNode **pp) {
  309. (*pp)->prev->next = (*pp)->next;
  310. (*pp)->next->prev = (*pp)->prev;
  311. MMUDEBUG(" *****DeleteNode size*****%d\n", (*pp)->page_count);
  312. FreeMemory(*pp);
  313. return MMU_STATUS_OK;
  314. }
  315. static enum MMUStatus DeleteNode(struct MMUNode **pp) {
  316. (*pp)->prev->next = (*pp)->next;
  317. (*pp)->next->prev = (*pp)->prev;
  318. MMUDEBUG(" *****DeleteNode size*****%d\n", (*pp)->page_count);
  319. FreeMemory(*pp);
  320. return MMU_STATUS_OK;
  321. }
  322. static enum MMUStatus MergeNode(struct MMUNode *h,
  323. struct MMUNode **pp) {
  324. struct MMUNode *tmp0 = h->next;
  325. struct MMUNode *tmp1 = h->next;
  326. while(tmp0) {
  327. /* 1th step: find front contiguous memory node */
  328. if(tmp0->mtlb_end == (*pp)->mtlb_start &&
  329. tmp0->stlb_end == (*pp)->stlb_start) {
  330. tmp0->mtlb_end = (*pp)->mtlb_end;
  331. tmp0->stlb_end = (*pp)->stlb_end;
  332. tmp0->page_count += (*pp)->page_count;
  333. DeleteNode(pp);
  334. MMUDEBUG(" *****first merge to front. node size*****%d\n", tmp0->page_count);
  335. /* after merge to front contiguous memory node,
  336. find if there is behind contiguous memory node */
  337. while(tmp1) {
  338. /* merge */
  339. if(tmp1->mtlb_start == tmp0->mtlb_end &&
  340. tmp1->stlb_start == tmp0->stlb_end) {
  341. tmp1->mtlb_start = tmp0->mtlb_start;
  342. tmp1->stlb_start = tmp0->stlb_start;
  343. tmp1->page_count += tmp0->page_count;
  344. MMUDEBUG(" *****second merge to behind. node size*****%d\n", tmp1->page_count);
  345. DeleteNode(&tmp0);
  346. return MMU_STATUS_OK;
  347. }
  348. tmp1 = tmp1->next;
  349. }
  350. return MMU_STATUS_OK;
  351. /* 1th step: find behind contiguous memory node */
  352. } else if(tmp0->mtlb_start == (*pp)->mtlb_end &&
  353. tmp0->stlb_start == (*pp)->stlb_end) {
  354. tmp0->mtlb_start = (*pp)->mtlb_start;
  355. tmp0->stlb_start = (*pp)->stlb_start;
  356. tmp0->page_count += (*pp)->page_count;
  357. DeleteNode(pp);
  358. MMUDEBUG(" *****first merge to behind. node size*****%d\n", tmp0->page_count);
  359. /* after merge to behind contiguous memory node,
  360. find if there is front contiguous memory node */
  361. while(tmp1) {
  362. /* merge */
  363. if(tmp1->mtlb_end == tmp0->mtlb_start &&
  364. tmp1->stlb_end == tmp0->stlb_start) {
  365. tmp1->mtlb_end = tmp0->mtlb_end;
  366. tmp1->stlb_end = tmp0->stlb_end;
  367. tmp1->page_count += tmp0->page_count;
  368. MMUDEBUG(" *****second merge to front. node size*****%d\n", tmp1->page_count);
  369. DeleteNode(&tmp0);
  370. return MMU_STATUS_OK;
  371. }
  372. tmp1 = tmp1->next;
  373. }
  374. return MMU_STATUS_OK;
  375. }
  376. tmp0 = tmp0->next;
  377. }
  378. return MMU_STATUS_FALSE;
  379. }
  380. /* Insert a node to map list */
  381. static enum MMUStatus SMInsertNode(enum MMURegion e,
  382. struct MMUNode **pp) {
  383. struct MMUNode *h;
  384. h = g_mmu->region[e].simple_map_head;
  385. h->next->prev = *pp;
  386. (*pp)->next = h->next;
  387. (*pp)->prev = h;
  388. h->next = *pp;
  389. MMUDEBUG(" *****insert bm node*****%d\n", (*pp)->page_count);
  390. return MMU_STATUS_OK;
  391. }
  392. static enum MMUStatus InsertNode(enum MMURegion e,
  393. struct MMUNode **pp,
  394. unsigned int free) {
  395. enum MMUStatus status;
  396. struct MMUNode *h, *b;
  397. if(free) {
  398. h = g_mmu->region[e].free_map_head;
  399. b = g_mmu->region[e].map_head;
  400. status = MergeNode(h, pp);
  401. MMUDEBUG(" *****insert free*****%d\n", (*pp)->page_count);
  402. if(MMU_IS_ERROR(status)) {
  403. /* remove from map*/
  404. if((*pp)->prev != NULL && (*pp)->next != NULL) {
  405. (*pp)->prev->next = (*pp)->next;
  406. (*pp)->next->prev = (*pp)->prev;
  407. }
  408. /* insert to free map */
  409. h->next->prev = *pp;
  410. (*pp)->next = h->next;
  411. (*pp)->prev = h;
  412. h->next = *pp;
  413. }
  414. } else {
  415. h = g_mmu->region[e].map_head;
  416. h->next->prev = *pp;
  417. (*pp)->next = h->next;
  418. (*pp)->prev = h;
  419. h->next = *pp;
  420. MMUDEBUG(" *****insert unfree*****%d\n", (*pp)->page_count);
  421. }
  422. return MMU_STATUS_OK;
  423. }
  424. /* Create a Node */
  425. static enum MMUStatus SMCreateNode(enum MMURegion e,
  426. struct MMUNode **node,
  427. unsigned int page_count) {
  428. struct MMUNode *p, **new;
  429. p = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  430. new = &p;
  431. (*new)->mtlb_start = -1;
  432. (*new)->stlb_start = -1;
  433. (*new)->mtlb_end = -1;
  434. (*new)->stlb_end = -1;
  435. (*new)->process_id = 0;
  436. (*new)->filp = NULL;
  437. (*new)->page_count = 0;
  438. (*new)->prev = NULL;
  439. (*new)->next = NULL;
  440. /* Insert a uncomplete Node, it will be initialized later */
  441. SMInsertNode(e, new);
  442. /* return a new node for map buffer */
  443. *node = *new;
  444. return MMU_STATUS_OK;
  445. }
  446. /* Create initial Nodes */
  447. static enum MMUStatus SMCreateNodes(void) {
  448. struct MMUNode *simple_map_head;
  449. struct MMUNode *simple_map_tail;
  450. int i;
  451. /* Init each region map node */
  452. for (i = 0; i < MMU_REGION_COUNT ; i++) {
  453. simple_map_head = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  454. simple_map_tail = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  455. simple_map_head->mtlb_start = -1;
  456. simple_map_head->stlb_start = -1;
  457. simple_map_head->mtlb_end = -1;
  458. simple_map_head->stlb_end = -1;
  459. simple_map_head->process_id = 0;
  460. simple_map_head->filp = NULL;
  461. simple_map_head->page_count = 0;
  462. simple_map_head->prev = NULL;
  463. simple_map_head->next = simple_map_tail;
  464. simple_map_tail->mtlb_start = -1;
  465. simple_map_tail->stlb_start = -1;
  466. simple_map_tail->mtlb_end = -1;
  467. simple_map_tail->stlb_end = -1;
  468. simple_map_tail->process_id = 0;
  469. simple_map_tail->filp = NULL;
  470. simple_map_tail->page_count = 0;
  471. simple_map_tail->prev = simple_map_head;
  472. simple_map_tail->next = NULL;
  473. g_mmu->region[i].simple_map_head = simple_map_head;
  474. g_mmu->region[i].simple_map_tail = simple_map_tail;
  475. }
  476. return MMU_STATUS_OK;
  477. }
  478. static enum MMUStatus CreateNode(void) {
  479. struct MMUNode *free_map_head, *map_head, *p, **pp;
  480. struct MMUNode *free_map_tail, *map_tail;
  481. int i;
  482. unsigned int page_count;
  483. unsigned int prev_stlb = 0, prev_mtlb = 0;
  484. /* Init each region map node */
  485. for (i = 0; i < MMU_REGION_COUNT ; i++) {
  486. free_map_head = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  487. map_head = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  488. free_map_tail = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  489. map_tail = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  490. free_map_head->mtlb_start = map_head->mtlb_start = -1;
  491. free_map_head->stlb_start = map_head->stlb_start = -1;
  492. free_map_head->mtlb_end = map_head->mtlb_end = -1;
  493. free_map_head->stlb_end = map_head->stlb_end = -1;
  494. free_map_head->process_id = map_head->process_id = 0;
  495. free_map_head->filp = map_head->filp = NULL;
  496. free_map_head->page_count = map_head->page_count = 0;
  497. free_map_head->prev = map_head->prev = NULL;
  498. free_map_head->next = free_map_tail;
  499. map_head->next = map_tail;
  500. free_map_tail->mtlb_start = map_tail->mtlb_start = -1;
  501. free_map_tail->stlb_start = map_tail->stlb_start = -1;
  502. free_map_tail->mtlb_end = map_tail->mtlb_end = -1;
  503. free_map_tail->stlb_end = map_tail->stlb_end = -1;
  504. free_map_tail->process_id = map_tail->process_id = 0;
  505. free_map_tail->filp = map_tail->filp = NULL;
  506. free_map_tail->page_count = map_tail->page_count = 0;
  507. free_map_tail->prev = free_map_head;
  508. map_tail->prev = map_head;
  509. free_map_tail->next = map_tail->next = NULL;
  510. g_mmu->region[i].free_map_head = free_map_head;
  511. g_mmu->region[i].map_head = map_head;
  512. g_mmu->region[i].free_map_tail = free_map_tail;
  513. g_mmu->region[i].map_tail = map_tail;
  514. p = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  515. pp = &p;
  516. switch(i) {
  517. case MMU_REGION_IN:
  518. page_count = (REGION_IN_END - REGION_IN_START + 1)/PAGE_SIZE;
  519. p->stlb_start = region_in_mmu_start >> 12 & 0x3FF; //hold mmu addr: 0x0
  520. p->mtlb_start = region_in_mmu_start >> 22;
  521. //end point next region start: +1; for remainder: +1
  522. p->stlb_end = prev_stlb = region_in_mmu_end >> 12 & 0x3FF;
  523. p->mtlb_end = prev_mtlb = region_in_mmu_end >> 22;
  524. p->page_count = page_count - 1; //hold mmu addr: 0x0
  525. break;
  526. case MMU_REGION_OUT:
  527. page_count = (REGION_OUT_END - REGION_OUT_START + 1)/PAGE_SIZE;
  528. p->stlb_start = region_out_mmu_start >> 12 & 0x3FF;
  529. p->mtlb_start = region_out_mmu_start >> 22;
  530. p->stlb_end = prev_stlb = region_out_mmu_end >> 12 & 0x3FF;
  531. p->mtlb_end = prev_mtlb = region_out_mmu_end >> 22;
  532. p->page_count = page_count;
  533. break;
  534. case MMU_REGION_PRIVATE:
  535. page_count = (REGION_PRIVATE_END - REGION_PRIVATE_START + 1)/PAGE_SIZE;
  536. p->stlb_start = region_private_mmu_start >> 12 & 0x3FF;
  537. p->mtlb_start = region_private_mmu_start >> 22;
  538. p->stlb_end = prev_stlb = region_private_mmu_end >> 12 & 0x3FF;
  539. p->mtlb_end = prev_mtlb = region_private_mmu_end >> 22;
  540. p->page_count = page_count;
  541. break;
  542. case MMU_REGION_PUB:
  543. p->stlb_start = prev_stlb;
  544. p->mtlb_start = prev_mtlb;
  545. p->stlb_end = prev_stlb = MMU_STLB_4K_ENTRY_NUM - 1;
  546. p->mtlb_end = prev_mtlb = MMU_MTLB_ENTRY_NUM - 1;
  547. p->page_count = (p->mtlb_end - p->mtlb_start) * MMU_STLB_4K_ENTRY_NUM +
  548. p->stlb_end - p->stlb_start + 1;
  549. break;
  550. default:
  551. pr_notice(" *****MMU Region Error*****\n");
  552. break;
  553. }
  554. p->process_id = 0;
  555. p->filp = NULL;
  556. p->next = p->prev = NULL;
  557. InsertNode(i, pp, 1);
  558. }
  559. return MMU_STATUS_OK;
  560. }
  561. /* A simpile function to check if the map buffer is existed.
  562. it needs more complex version*/
  563. static enum MMUStatus SMCheckAddress(enum MMURegion e,
  564. void *virtual_address) {
  565. struct MMUNode *p;
  566. p = g_mmu->region[e].simple_map_head->next;
  567. while(p) {
  568. if(p->buf_virtual_address == virtual_address) {
  569. return MMU_STATUS_FALSE;
  570. }
  571. p = p->next;
  572. }
  573. return MMU_STATUS_OK;
  574. }
  575. static enum MMUStatus FindFreeNode(enum MMURegion e,
  576. struct MMUNode **node,
  577. unsigned int page_count) {
  578. struct MMUNode *p;
  579. p = g_mmu->region[e].free_map_head->next;
  580. while(p) {
  581. if(p->page_count >= page_count) {
  582. *node = p;
  583. return MMU_STATUS_OK;
  584. }
  585. p = p->next;
  586. }
  587. return MMU_STATUS_FALSE;
  588. }
  589. static enum MMUStatus SplitFreeNode(enum MMURegion e,
  590. struct MMUNode **node,
  591. unsigned int page_count) {
  592. struct MMUNode *p, **new;
  593. p = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  594. new = &p;
  595. **new = **node;
  596. (*new)->mtlb_start = (*node)->mtlb_start;
  597. (*new)->stlb_start = (*node)->stlb_start;
  598. (*new)->mtlb_end = (page_count + (*node)->stlb_start) /
  599. MMU_STLB_4K_ENTRY_NUM +
  600. (*node)->mtlb_start;
  601. (*new)->stlb_end = (page_count + (*node)->stlb_start) %
  602. MMU_STLB_4K_ENTRY_NUM;
  603. (*new)->process_id = (*node)->process_id;
  604. (*new)->page_count = page_count;
  605. MMUDEBUG(" *****new mtlb_start*****%d\n", (*new)->mtlb_start);
  606. MMUDEBUG(" *****new stlb_start*****%d\n", (*new)->stlb_start);
  607. MMUDEBUG(" *****new mtlb_end*****%d\n", (*new)->mtlb_end);
  608. MMUDEBUG(" *****new stlb_end*****%d\n", (*new)->stlb_end);
  609. /* Insert a new node in map */
  610. InsertNode(e, new, 0);
  611. /* Update free node in free map*/
  612. (*node)->page_count -= page_count;
  613. if((*node)->page_count == 0) {
  614. DeleteNode(node);
  615. MMUDEBUG(" *****old node deleted*****\n");
  616. } else {
  617. (*node)->mtlb_start = (*new)->mtlb_end;
  618. (*node)->stlb_start = (*new)->stlb_end;
  619. MMUDEBUG(" *****old mtlb_start*****%d\n", (*node)->mtlb_start);
  620. MMUDEBUG(" *****old stlb_start*****%d\n", (*node)->stlb_start);
  621. MMUDEBUG(" *****old mtlb_end*****%d\n", (*node)->mtlb_end);
  622. MMUDEBUG(" *****old stlb_end*****%d\n", (*node)->stlb_end);
  623. }
  624. /* return a new node for map buffer */
  625. *node = *new;
  626. return MMU_STATUS_OK;
  627. }
  628. static enum MMUStatus SMRemoveNode(enum MMURegion e,
  629. void *buf_virtual_address,
  630. unsigned int process_id) {
  631. struct MMUNode *p, **pp;
  632. p = g_mmu->region[e].simple_map_head->next;
  633. pp = &p;
  634. while(*pp) {
  635. if((*pp)->buf_virtual_address == buf_virtual_address &&
  636. (*pp)->process_id == process_id) {
  637. SMDeleteNode(pp);
  638. break;
  639. }
  640. *pp = (*pp)->next;
  641. }
  642. return MMU_STATUS_OK;
  643. }
  644. static enum MMUStatus RemoveNode(enum MMURegion e,
  645. void *buf_virtual_address,
  646. unsigned int process_id) {
  647. struct MMUNode *p, **pp;
  648. p = g_mmu->region[e].map_head->next;
  649. pp = &p;
  650. while(*pp) {
  651. if((*pp)->buf_virtual_address == buf_virtual_address &&
  652. (*pp)->process_id == process_id) {
  653. InsertNode(e, pp, 1);
  654. break;
  655. }
  656. *pp = (*pp)->next;
  657. }
  658. return MMU_STATUS_OK;
  659. }
  660. static enum MMUStatus SMRemoveKernelNode(enum MMURegion e,
  661. unsigned int buf_bus_address,
  662. unsigned int process_id) {
  663. struct MMUNode *p, **pp;
  664. p = g_mmu->region[e].simple_map_head->next;
  665. pp = &p;
  666. while(*pp) {
  667. if((*pp)->buf_bus_address == buf_bus_address &&
  668. (*pp)->process_id == process_id) {
  669. SMDeleteNode(pp);
  670. break;
  671. }
  672. *pp = (*pp)->next;
  673. }
  674. return MMU_STATUS_OK;
  675. }
  676. static enum MMUStatus RemoveKernelNode(enum MMURegion e,
  677. unsigned int buf_bus_address,
  678. unsigned int process_id) {
  679. struct MMUNode *p, **pp;
  680. p = g_mmu->region[e].map_head->next;
  681. pp = &p;
  682. while(*pp) {
  683. if((*pp)->buf_bus_address == buf_bus_address &&
  684. (*pp)->process_id == process_id) {
  685. InsertNode(e, pp, 1);
  686. break;
  687. }
  688. *pp = (*pp)->next;
  689. }
  690. return MMU_STATUS_OK;
  691. }
  692. static enum MMUStatus Delay(unsigned int delay) {
  693. if(delay > 0) {
  694. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)
  695. ktime_t dl = ktime_set((delay / MSEC_PER_SEC),
  696. (delay % MSEC_PER_SEC) * NSEC_PER_MSEC);
  697. __set_current_state(TASK_UNINTERRUPTIBLE);
  698. schedule_hrtimeout(&dl, HRTIMER_MODE_REL);
  699. #else
  700. msleep(delay);
  701. #endif
  702. }
  703. return MMU_STATUS_OK;
  704. }
  705. static enum MMUStatus CreateMutex(void **mtx) {
  706. enum MMUStatus status;
  707. /* Allocate the mutex structure. */
  708. status = AllocateMemory(sizeof(struct mutex), mtx);
  709. if (MMU_IS_SUCCESS(status)) {
  710. /* Initialize the mutex. */
  711. mutex_init(*(struct mutex **)mtx);
  712. }
  713. return status;
  714. }
  715. static enum MMUStatus DeleteMutex(void *mtx) {
  716. /* Destroy the mutex. */
  717. mutex_destroy((struct mutex *)mtx);
  718. /* Free the mutex structure. */
  719. FreeMemory(mtx);
  720. return MMU_STATUS_OK;
  721. }
  722. static enum MMUStatus AcquireMutex(void *mtx, unsigned int timeout) {
  723. if (timeout == MMU_INFINITE)
  724. {
  725. /* Lock the mutex. */
  726. mutex_lock(mtx);
  727. /* Success. */
  728. return MMU_STATUS_OK;
  729. }
  730. for (;;) {
  731. /* Try to acquire the mutex. */
  732. if (mutex_trylock(mtx)) {
  733. /* Success. */
  734. return MMU_STATUS_OK;
  735. }
  736. if (timeout-- == 0) {
  737. break;
  738. }
  739. /* Wait for 1 millisecond. */
  740. Delay(1);
  741. }
  742. return MMU_STATUS_OK;
  743. }
  744. static enum MMUStatus ReleaseMutex(void *mtx) {
  745. /* Release the mutex. */
  746. mutex_unlock(mtx);
  747. return MMU_STATUS_OK;
  748. }
  749. static inline enum MMUStatus QueryProcessPageTable(void *logical,
  750. unsigned long long *address) {
  751. unsigned long lg = (unsigned long)logical;
  752. unsigned long offset = lg & ~PAGE_MASK;
  753. struct vm_area_struct *vma;
  754. spinlock_t *ptl;
  755. pgd_t *pgd;
  756. pud_t *pud;
  757. pmd_t *pmd;
  758. pte_t *pte;
  759. if (is_vmalloc_addr(logical)) {
  760. /* vmalloc area. */
  761. *address = page_to_phys(vmalloc_to_page(logical)) | offset;
  762. return MMU_STATUS_OK;
  763. } else if (virt_addr_valid(lg)) {
  764. /* Kernel logical address. */
  765. *address = virt_to_phys(logical);
  766. return MMU_STATUS_OK;
  767. } else {
  768. /* Try user VM area. */
  769. if (!current->mm)
  770. return MMU_STATUS_NOT_FOUND;
  771. #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0)
  772. down_read(&current->mm->mmap_lock);
  773. #else
  774. down_read(&current->mm->mmap_sem);
  775. #endif
  776. vma = find_vma(current->mm, lg);
  777. #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0)
  778. up_read(&current->mm->mmap_lock);
  779. #else
  780. up_read(&current->mm->mmap_sem);
  781. #endif
  782. /* To check if mapped to user. */
  783. if (!vma)
  784. return MMU_STATUS_NOT_FOUND;
  785. pgd = pgd_offset(current->mm, lg);
  786. if (pgd_none(*pgd) || pgd_bad(*pgd))
  787. return MMU_STATUS_NOT_FOUND;
  788. #if (defined(CONFIG_CPU_CSKYV2) || defined(CONFIG_X86)) \
  789. && LINUX_VERSION_CODE >= KERNEL_VERSION (4,12,0)
  790. pud = pud_offset((p4d_t*)pgd, lg);
  791. #elif (defined(CONFIG_CPU_CSKYV2)) \
  792. && LINUX_VERSION_CODE >= KERNEL_VERSION (4,11,0)
  793. pud = pud_offset((p4d_t*)pgd, lg);
  794. #else
  795. pud = pud_offset((p4d_t*)pgd, lg);
  796. #endif
  797. if (pud_none(*pud) || pud_bad(*pud))
  798. return MMU_STATUS_NOT_FOUND;
  799. pmd = pmd_offset(pud, lg);
  800. if (pmd_none(*pmd) || pmd_bad(*pmd))
  801. return MMU_STATUS_NOT_FOUND;
  802. pte = pte_offset_map_lock(current->mm, pmd, lg, &ptl);
  803. if (!pte) {
  804. spin_unlock(ptl);
  805. return MMU_STATUS_NOT_FOUND;
  806. }
  807. if (!pte_present(*pte)) {
  808. pte_unmap_unlock(pte, ptl);
  809. return MMU_STATUS_NOT_FOUND;
  810. }
  811. *address = (pte_pfn(*pte) << PAGE_SHIFT) | offset;
  812. pte_unmap_unlock(pte, ptl);
  813. *address -= gBaseDDRHw;
  814. //MMUDEBUG(" QueryProcessPageTable map: virt %p -> %p\n", logical, (void *)*address);
  815. return MMU_STATUS_OK;
  816. }
  817. }
  818. static inline int GetProcessID(void) {
  819. return current->tgid;
  820. }
  821. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
  822. static inline int is_vmalloc_addr(void *addr) {
  823. unsigned long long addr = (unsigned long long)Addr;
  824. return addr >= VMALLOC_START && addr < VMALLOC_END;
  825. }
  826. #endif
  827. static enum MMUStatus GetPhysicalAddress(void *logical,
  828. unsigned long long *address) {
  829. enum MMUStatus status;
  830. status = QueryProcessPageTable(logical, address);
  831. return status;
  832. }
  833. static enum MMUStatus GetPageEntry(struct MMUNode *node,
  834. unsigned int **page_table_entry,
  835. unsigned int i) {
  836. int num = node->mtlb_start * MMU_STLB_4K_ENTRY_NUM +
  837. node->stlb_start + i;
  838. *page_table_entry = (unsigned int*)g_mmu->stlb_virtual + num;
  839. return MMU_STATUS_OK;
  840. }
  841. static enum MMUStatus SetupDynamicSpace(void) {
  842. int i;
  843. enum MMUStatus status;
  844. unsigned int stlb_entry;
  845. void *pointer;
  846. unsigned long long address;
  847. dma_addr_t dma_handle;
  848. unsigned int num_entries = MMU_MTLB_ENTRY_NUM;
  849. unsigned int *mtlb_virtual = (unsigned int *)g_mmu->mtlb_virtual;
  850. AcquireMutex(g_mmu->page_table_mutex, MMU_INFINITE);
  851. if(pcie) {
  852. pointer = ioremap(gBaseDDRHw+STLB_PCIE_START_ADDRESS, num_entries*MMU_STLB_4K_SIZE);
  853. g_mmu->stlb_virtual = pointer;
  854. MMUDEBUG(" *****stlb_virtual = %p**%d\n", pointer, num_entries*MMU_STLB_4K_SIZE);
  855. address = STLB_PCIE_START_ADDRESS;
  856. for(i = 0; i < num_entries; i++){
  857. stlb_entry = address
  858. /* 4KB page size */
  859. | (0 << 2)
  860. /* Ignore exception */
  861. | (0 << 1)
  862. /* Present */
  863. | (1 << 0);
  864. WritePageEntry(mtlb_virtual++, stlb_entry);
  865. address += MMU_STLB_4K_SIZE;
  866. }
  867. } else {
  868. g_mmu->stlb_virtual = (void *)((u64)(g_mmu->mtlb_virtual) + MMU_MTLB_SIZE);
  869. g_mmu->stlb_physical = address = g_mmu->mtlb_physical + MMU_MTLB_SIZE;
  870. g_mmu->stlb_size = num_entries * MMU_STLB_4K_SIZE;
  871. for(i = 0; i < num_entries; i++){
  872. stlb_entry = address
  873. /* 4KB page size */
  874. | (0 << 2)
  875. /* Ignore exception */
  876. | (0 << 1)
  877. /* Present */
  878. | (1 << 0);
  879. WritePageEntry(mtlb_virtual++, stlb_entry);
  880. address += MMU_STLB_4K_SIZE;
  881. }
  882. }
  883. ReleaseMutex(g_mmu->page_table_mutex);
  884. /* Initial map info. */
  885. if (simple_map)
  886. SMCreateNodes();
  887. else
  888. CreateNode();
  889. return MMU_STATUS_OK;
  890. onerror:
  891. /* Return status. */
  892. return status;
  893. }
  894. enum MMUStatus MMUInit(volatile unsigned char *hwregs) {
  895. enum MMUStatus status;
  896. unsigned i;
  897. int result;
  898. void *pointer;
  899. if (mmu_init == MMU_TRUE) {
  900. /* All mmu use common table and dev, just initial once*/
  901. pr_notice(" *****MMU Already Initialed*****\n");
  902. return MMU_STATUS_OK;
  903. }
  904. if(!hwregs || (ioread32((void*)(hwregs + MMU_REG_HW_ID))>>16) != 0x4D4D)
  905. return MMU_STATUS_NOT_FOUND;
  906. pr_notice(" *****MMU Init*****\n");
  907. platformdev = platform_device_register_full(&hantro_platform_info);
  908. if(platformdev == NULL) {
  909. pr_err("hantrodec create platform device fail\n");
  910. status = MMU_STATUS_FALSE;
  911. goto onerror;
  912. } else {
  913. pr_info("Create platform device success\n");
  914. }
  915. result = platform_driver_register(&hantro_drm_platform_driver);
  916. pr_notice("Platform driver status is %d\n", result);
  917. /* Allocate memory for the MMU object. */
  918. MMU_ON_ERROR(AllocateMemory(sizeof(struct MMU), &pointer));
  919. ZeroMemory(pointer, sizeof(struct MMU));
  920. g_mmu = pointer;
  921. g_mmu->page_table_mutex = NULL;
  922. /* Create the page table mutex. */
  923. MMU_ON_ERROR(CreateMutex(&g_mmu->page_table_mutex));
  924. for (i = 0; i < MMU_REGION_COUNT;i++) {
  925. MMU_ON_ERROR(CreateMutex(&g_mmu->region[i].node_mutex));
  926. }
  927. mmu_init = MMU_TRUE;
  928. return MMU_STATUS_OK;
  929. onerror:
  930. pr_notice(" *****MMU Init Error*****\n");
  931. return status;
  932. }
  933. enum MMUStatus MMURelease(void *filp, volatile unsigned char *hwregs) {
  934. int i, j;
  935. struct MMUNode *p, *tmp;
  936. unsigned long long address;
  937. unsigned int *page_table_entry;
  938. if(!hwregs || (ioread32((void*)(hwregs + MMU_REG_HW_ID))>>16) != 0x4D4D)
  939. return MMU_STATUS_FALSE;
  940. /* if mmu or TLB not enabled, return */
  941. if (simple_map) {
  942. if(g_mmu == NULL || g_mmu->region[0].simple_map_head == NULL)
  943. return MMU_STATUS_OK;
  944. } else {
  945. if(g_mmu == NULL || g_mmu->region[0].map_head == NULL)
  946. return MMU_STATUS_OK;
  947. }
  948. pr_notice(" *****MMU Release*****\n");
  949. AcquireMutex(g_mmu->page_table_mutex, MMU_INFINITE);
  950. if (simple_map) {
  951. for (i = 0; i < MMU_REGION_COUNT; i++) {
  952. p = g_mmu->region[i].simple_map_head->next;
  953. while(p) {
  954. tmp = p->next;
  955. if(p->filp == (struct file *)filp) {
  956. for(j = 0;j < p->page_count; j++) {
  957. GetPageEntry(p, &page_table_entry, j);
  958. address = 0;
  959. WritePageEntry(page_table_entry, address);
  960. }
  961. SMRemoveNode(i, p->buf_virtual_address, p->process_id);
  962. }
  963. p = tmp;
  964. }
  965. }
  966. } else {
  967. for (i = 0; i < MMU_REGION_COUNT; i++) {
  968. p = g_mmu->region[i].map_head->next;
  969. while(p) {
  970. tmp = p->next;
  971. if(p->filp == (struct file *)filp) {
  972. for(j = 0;j < p->page_count; j++) {
  973. GetPageEntry(p, &page_table_entry, j);
  974. address = 0;
  975. WritePageEntry(page_table_entry, address);
  976. }
  977. RemoveNode(i, p->buf_virtual_address, p->process_id);
  978. }
  979. p = tmp;
  980. }
  981. }
  982. }
  983. ReleaseMutex(g_mmu->page_table_mutex);
  984. return MMU_STATUS_OK;
  985. }
  986. enum MMUStatus MMUCleanup(volatile unsigned char *hwregs[MAX_SUBSYS_NUM][2]) {
  987. int i;
  988. struct MMUNode *p, *tmp;
  989. struct MMUNode *fp;
  990. for (i = 0; i < MAX_SUBSYS_NUM; i++) {
  991. if (hwregs[i][0] != NULL &&
  992. (ioread32((void*)(hwregs[i][0] + MMU_REG_HW_ID))>>16) != 0x4D4D)
  993. return MMU_STATUS_FALSE;
  994. if (hwregs[i][1] != NULL &&
  995. (ioread32((void*)(hwregs[i][1] + MMU_REG_HW_ID))>>16) != 0x4D4D)
  996. return MMU_STATUS_FALSE;
  997. }
  998. pr_info(" *****MMU cleanup*****\n");
  999. if (pcie) {
  1000. if (g_mmu->stlb_virtual)
  1001. iounmap(g_mmu->stlb_virtual);
  1002. if (g_mmu->mtlb_virtual)
  1003. iounmap(g_mmu->mtlb_virtual);
  1004. if (g_mmu->page_table_array)
  1005. iounmap(g_mmu->page_table_array);
  1006. } else {
  1007. if (g_mmu->stlb_virtual)
  1008. dma_free_coherent(&platformdev->dev, g_mmu->stlb_size,
  1009. g_mmu->stlb_virtual, (dma_addr_t)g_mmu->stlb_physical);
  1010. if (g_mmu->mtlb_virtual)
  1011. dma_free_coherent(&platformdev->dev, g_mmu->mtlb_size,
  1012. g_mmu->mtlb_virtual, (dma_addr_t)g_mmu->mtlb_physical);
  1013. if (g_mmu->page_table_array)
  1014. dma_free_coherent(&platformdev->dev, g_mmu->page_table_array_size,
  1015. g_mmu->page_table_array, (dma_addr_t)g_mmu->page_table_array_physical);
  1016. }
  1017. DeleteMutex(g_mmu->page_table_mutex);
  1018. for (i = 0; i < MMU_REGION_COUNT; i++) {
  1019. DeleteMutex(g_mmu->region[i].node_mutex);
  1020. if (simple_map) {
  1021. p = g_mmu->region[i].simple_map_head;
  1022. while(p) {
  1023. tmp = p->next;
  1024. FreeMemory(p);
  1025. p = tmp;
  1026. MMUDEBUG(" *****clean node*****\n");
  1027. }
  1028. } else {
  1029. fp = g_mmu->region[i].free_map_head;
  1030. p = g_mmu->region[i].map_head;
  1031. while(fp) {
  1032. tmp = fp->next;
  1033. FreeMemory(fp);
  1034. fp = tmp;
  1035. MMUDEBUG(" *****clean free node*****\n");
  1036. }
  1037. while(p) {
  1038. tmp = p->next;
  1039. FreeMemory(p);
  1040. p = tmp;
  1041. MMUDEBUG(" *****clean node*****\n");
  1042. }
  1043. }
  1044. }
  1045. FreeMemory(g_mmu);
  1046. platform_device_unregister(platformdev);
  1047. platform_driver_unregister(&hantro_drm_platform_driver);
  1048. pr_info("Unregister platform device.\n");
  1049. for (i = 0; i < MAX_SUBSYS_NUM; i++) {
  1050. if (hwregs[i][0] != NULL)
  1051. iowrite32(0, (void*)(hwregs[i][0] + MMU_REG_CONTROL));
  1052. if (hwregs[i][1] != NULL)
  1053. iowrite32(0, (void*)(hwregs[i][1] + MMU_REG_CONTROL));
  1054. }
  1055. mmu_enable = 0;
  1056. mmu_init = 0;
  1057. return MMU_STATUS_OK;
  1058. }
  1059. /*------------------------------------------------------------------------------
  1060. Function name: MMUEnable
  1061. Description:
  1062. Create TLB, set registers and enable MMU
  1063. For pcie, TLB buffers come from FPGA memory and The distribution is as follows
  1064. MTLB: start from: 0x00100000, size: 4K bits
  1065. page table array: 0x00200000 64 bits
  1066. STLB: 0x00300000 4M bits
  1067. ------------------------------------------------------------------------------*/
  1068. enum MMUStatus MMUEnable(volatile unsigned char *hwregs[MAX_SUBSYS_NUM][2]) {
  1069. enum MMUStatus status;
  1070. unsigned int address;
  1071. unsigned int mutex = MMU_FALSE;
  1072. dma_addr_t dma_handle;
  1073. u32 i = 0;
  1074. u32 address_ext;
  1075. u32 total_table_size;
  1076. if(mmu_enable == MMU_TRUE) {
  1077. pr_info(" *****MMU Already Enabled*****\n");
  1078. return MMU_STATUS_OK;
  1079. }
  1080. pr_info(" *****MMU Enable...*****\n");
  1081. AcquireMutex(g_mmu->page_table_mutex, MMU_INFINITE);
  1082. mutex = MMU_TRUE;
  1083. if(pcie) {
  1084. g_mmu->mtlb_size = MMU_MTLB_SIZE;
  1085. g_mmu->mtlb_virtual = ioremap(gBaseDDRHw+MTLB_PCIE_START_ADDRESS, g_mmu->mtlb_size);
  1086. MMUDEBUG("gBaseDDRHw=0x%llx, g_mmu->mtlb_virtual=0x%llx\n", gBaseDDRHw, g_mmu->mtlb_virtual);
  1087. g_mmu->mtlb_physical = MTLB_PCIE_START_ADDRESS;
  1088. g_mmu->page_table_array = ioremap(gBaseDDRHw+PAGE_PCIE_START_ADDRESS, PAGE_TABLE_ENTRY_SIZE);
  1089. } else {
  1090. /* Allocate the 4K mode MTLB table. */
  1091. total_table_size = MMU_MTLB_SIZE + MMU_MTLB_ENTRY_NUM*MMU_STLB_4K_SIZE;
  1092. g_mmu->mtlb_size = MMU_MTLB_SIZE;
  1093. g_mmu->mtlb_virtual = dma_alloc_coherent(&platformdev->dev, total_table_size,
  1094. &dma_handle, GFP_KERNEL | GFP_DMA);
  1095. MMUDEBUG(" *****g_mmu->mtlb_virtual = 0x%llx\n", g_mmu->mtlb_virtual);
  1096. g_mmu->mtlb_physical = (unsigned long long)dma_handle;
  1097. MMUDEBUG(" *****mtlb_physical = 0x%llx\n", (unsigned int)g_mmu->mtlb_physical);
  1098. if(g_mmu->mtlb_virtual == NULL) {
  1099. pr_err("hantrodec alloc buffer fail\n");
  1100. status = MMU_STATUS_FALSE;
  1101. goto onerror;
  1102. }
  1103. g_mmu->page_table_array_size = PAGE_TABLE_ENTRY_SIZE;
  1104. g_mmu->page_table_array = dma_alloc_coherent(&platformdev->dev, g_mmu->page_table_array_size,
  1105. &dma_handle, GFP_KERNEL | GFP_DMA);
  1106. MMUDEBUG(" *****g_mmu->page_table_array = 0x%llx\n", g_mmu->page_table_array);
  1107. g_mmu->page_table_array_physical = (unsigned long long)dma_handle;
  1108. MMUDEBUG(" *****page_table_array_physical = 0x%llx\n", (unsigned int)g_mmu->page_table_array_physical);
  1109. if(g_mmu->page_table_array == NULL) {
  1110. pr_err("hantrodec alloc buffer fail\n");
  1111. status = MMU_STATUS_FALSE;
  1112. goto onerror;
  1113. }
  1114. }
  1115. *((unsigned int*)g_mmu->page_table_array) =
  1116. (g_mmu->mtlb_physical & 0xFFFFFC00) | (0 << 0);
  1117. *((unsigned int *)g_mmu->page_table_array+1) =
  1118. (u32)(g_mmu->mtlb_physical >> 32)&0xff;
  1119. *((unsigned int *)g_mmu->page_table_array+2) =
  1120. (g_mmu->mtlb_physical & 0xFFFFFC00) | (0 << 0);
  1121. *((unsigned int *)g_mmu->page_table_array+3) =
  1122. (u32)(g_mmu->mtlb_physical >> 32)&0xff;
  1123. MMUDEBUG(" Page table array[0]: lsb = 0x%08x\n", ((int *)g_mmu->page_table_array)[0]);
  1124. MMUDEBUG(" msb = 0x%08x\n", ((int *)g_mmu->page_table_array)[1]);
  1125. ZeroMemory(g_mmu->mtlb_virtual, total_table_size);
  1126. ReleaseMutex(g_mmu->page_table_mutex);
  1127. MMU_ON_ERROR(SetupDynamicSpace());
  1128. if(pcie) {
  1129. address = PAGE_PCIE_START_ADDRESS;
  1130. } else {
  1131. address = g_mmu->page_table_array_physical;
  1132. address_ext = ((u32)(g_mmu->page_table_array_physical >> 32))&0xff;
  1133. }
  1134. #ifndef HANTROVCMD_ENABLE_IP_SUPPORT
  1135. /* set regs of all MMUs */
  1136. for (i = 0; i < MAX_SUBSYS_NUM; i++) {
  1137. if (hwregs[i][0] != NULL) {
  1138. MMUDEBUG("hwregs[%d][0]=%p, id=0x%08x", i, hwregs[i][0], ioread32((void*)hwregs[i][0] + MMU_REG_HW_ID));
  1139. iowrite32(address, (void*)(hwregs[i][0] + MMU_REG_ADDRESS));
  1140. iowrite32(address_ext, (void *)(hwregs[i][0] + MMU_REG_ADDRESS_MSB));
  1141. iowrite32(0x10000, (void*)(hwregs[i][0] + MMU_REG_PAGE_TABLE_ID));
  1142. iowrite32(0x00000, (void*)(hwregs[i][0] + MMU_REG_PAGE_TABLE_ID));
  1143. iowrite32(1, (void*)(hwregs[i][0] + MMU_REG_CONTROL));
  1144. }
  1145. if (hwregs[i][1] != NULL) {
  1146. MMUDEBUG("hwregs[%d][1]=%p, id=0x%08x", i, hwregs[i][1], ioread32((void*)hwregs[i][1] + MMU_REG_HW_ID));
  1147. iowrite32(address, (void*)(hwregs[i][1] + MMU_REG_ADDRESS));
  1148. iowrite32(address_ext, (void *)(hwregs[i][1] + MMU_REG_ADDRESS_MSB));
  1149. iowrite32(0x10000, (void*)(hwregs[i][1] + MMU_REG_PAGE_TABLE_ID));
  1150. iowrite32(0x00000, (void*)(hwregs[i][1] + MMU_REG_PAGE_TABLE_ID));
  1151. iowrite32(1, (void*)(hwregs[i][1] + MMU_REG_CONTROL));
  1152. }
  1153. }
  1154. #endif
  1155. mmu_enable = MMU_TRUE;
  1156. return MMU_STATUS_OK;
  1157. onerror:
  1158. if (mutex) {
  1159. ReleaseMutex(g_mmu->page_table_mutex);
  1160. }
  1161. MMUDEBUG(" *****MMU Enable Error*****\n");
  1162. return status;
  1163. }
  1164. /*------------------------------------------------------------------------------
  1165. Function name: MMUFlush
  1166. Description:
  1167. Flush MMU reg to update cache in MMU.
  1168. ------------------------------------------------------------------------------*/
  1169. static enum MMUStatus MMUFlush(u32 core_id, volatile unsigned char *hwregs[MAX_SUBSYS_NUM][2]) {
  1170. enum MMUStatus status;
  1171. unsigned int mutex = MMU_FALSE;
  1172. MMUDEBUG(" *****MMU Flush*****\n");
  1173. AcquireMutex(g_mmu->page_table_mutex, MMU_INFINITE);
  1174. mutex = MMU_TRUE;
  1175. if (hwregs[core_id][0] != NULL) {
  1176. iowrite32(0x10, (void*)(hwregs[core_id][0] + MMU_REG_FLUSH));
  1177. iowrite32(0x00, (void*)(hwregs[core_id][0] + MMU_REG_FLUSH));
  1178. } else {
  1179. pr_err("hantrodec alloc buffer fail\n");
  1180. status = MMU_STATUS_FALSE;
  1181. goto onerror;
  1182. }
  1183. if (hwregs[core_id][1] != NULL) {
  1184. iowrite32(0x10, (void*)(hwregs[core_id][1] + MMU_REG_FLUSH));
  1185. iowrite32(0x00, (void*)(hwregs[core_id][1] + MMU_REG_FLUSH));
  1186. }
  1187. ReleaseMutex(g_mmu->page_table_mutex);
  1188. return MMU_STATUS_OK;
  1189. onerror:
  1190. if (mutex) {
  1191. ReleaseMutex(g_mmu->page_table_mutex);
  1192. }
  1193. MMUDEBUG(" *****MMU Flush Error*****\n");
  1194. return status;
  1195. }
  1196. static enum MMUStatus MMUMemNodeMap(struct addr_desc *addr, struct file *filp) {
  1197. enum MMUStatus status;
  1198. unsigned int page_count = 0;
  1199. unsigned int i = 0;
  1200. struct MMUNode *p;
  1201. unsigned long long address = 0x0;
  1202. unsigned int *page_table_entry;
  1203. enum MMURegion e;
  1204. unsigned int mutex = MMU_FALSE;
  1205. u32 ext_addr;
  1206. MMUDEBUG(" *****MMU Map*****\n");
  1207. AcquireMutex(g_mmu->page_table_mutex, MMU_INFINITE);
  1208. mutex = MMU_TRUE;
  1209. page_count = (addr->size - 1)/PAGE_SIZE + 1;
  1210. GetPhysicalAddress(addr->virtual_address, &address);
  1211. MMUDEBUG(" *****MMU map address*****%x\n", address);
  1212. if(address >= REGION_IN_START &&
  1213. address + addr->size < REGION_IN_END)
  1214. e = MMU_REGION_IN;
  1215. else if(address >= REGION_OUT_START &&
  1216. address + addr->size < REGION_OUT_END)
  1217. e = MMU_REGION_OUT;
  1218. else if(address >= REGION_PRIVATE_START &&
  1219. address + addr->size < REGION_PRIVATE_END)
  1220. e = MMU_REGION_PRIVATE;
  1221. else
  1222. e = MMU_REGION_PUB;
  1223. if (simple_map) {
  1224. MMU_ON_ERROR(SMCheckAddress(e, addr->virtual_address));
  1225. SMCreateNode(e, &p, page_count);
  1226. MMUDEBUG(" *****Node map size*****%d\n", page_count);
  1227. p->buf_virtual_address = addr->virtual_address;
  1228. p->process_id = GetProcessID();
  1229. p->filp = filp;
  1230. p->mtlb_start = ((address + map_shift) >> MMU_MTLB_SHIFT);
  1231. p->stlb_start = ((address + map_shift) >> MMU_STLB_4K_SHIFT ) & 0x3FF;
  1232. p->mtlb_end = (page_count + p->stlb_start) / MMU_STLB_4K_ENTRY_NUM +
  1233. p->mtlb_start;
  1234. p->stlb_end = (page_count + p->stlb_start) % MMU_STLB_4K_ENTRY_NUM;
  1235. p->page_count = page_count;
  1236. for(i = 0;i < page_count; i++) {
  1237. GetPhysicalAddress(addr->virtual_address + i * PAGE_SIZE, &address);
  1238. GetPageEntry(p, &page_table_entry, i);
  1239. ext_addr = ((u32)(address>>32))&0xff;
  1240. address = (address & 0xFFFFF000)
  1241. /* ext address , physical address bits [39,32]*/
  1242. | (ext_addr << 4)
  1243. /* writable */
  1244. | (1 << 2)
  1245. /* Ignore exception */
  1246. | (0 << 1)
  1247. /* Present */
  1248. | (1 << 0);
  1249. WritePageEntry(page_table_entry, address);
  1250. }
  1251. /* Purpose of Bare_metal mode: input bus address==mmu address*/
  1252. addr->bus_address = p->mtlb_start << MMU_MTLB_SHIFT
  1253. | p->stlb_start << MMU_STLB_4K_SHIFT;
  1254. } else {
  1255. MMU_ON_ERROR(FindFreeNode(e, &p, page_count));
  1256. SplitFreeNode(e, &p, page_count);
  1257. MMUDEBUG(" *****Node map size*****%d\n", p->page_count);
  1258. p->buf_virtual_address = addr->virtual_address;
  1259. p->process_id = GetProcessID();
  1260. p->filp = filp;
  1261. for(i = 0;i < page_count; i++) {
  1262. GetPhysicalAddress(addr->virtual_address + i * PAGE_SIZE, &address);
  1263. GetPageEntry(p, &page_table_entry, i);
  1264. ext_addr = ((u32)(address>>32))&0xff;
  1265. address = (address & 0xFFFFF000)
  1266. /* ext address , physical address bits [39,32]*/
  1267. | (ext_addr << 4)
  1268. /* writable */
  1269. | (1 << 2)
  1270. /* Ignore exception */
  1271. | (0 << 1)
  1272. /* Present */
  1273. | (1 << 0);
  1274. WritePageEntry(page_table_entry, address);
  1275. }
  1276. addr->bus_address = p->mtlb_start << MMU_MTLB_SHIFT
  1277. | p->stlb_start << MMU_STLB_4K_SHIFT;
  1278. }
  1279. MMUDEBUG(" MMU_MTLB_SHIFT %d MMU_STLB_4K_SHIFT %d\n", MMU_MTLB_SHIFT, MMU_STLB_4K_SHIFT);
  1280. MMUDEBUG(" MMUMemNodeMap map total %d pages in region %d\nMTLB/STLB starts %d/%d, MTLB/STLB ends %d/%d\n",
  1281. page_count, (u32)e, p->mtlb_start, p->stlb_start, p->mtlb_end, p->stlb_end);
  1282. MMUDEBUG(" MMUMemNodeMap map %p -> 0x%08x\n", addr->virtual_address, addr->bus_address);
  1283. ReleaseMutex(g_mmu->page_table_mutex);
  1284. return MMU_STATUS_OK;
  1285. onerror:
  1286. if (mutex) {
  1287. ReleaseMutex(g_mmu->page_table_mutex);
  1288. }
  1289. MMUDEBUG(" *****MMU Map Error*****\n");
  1290. return status;
  1291. }
  1292. static enum MMUStatus MMUMemNodeUnmap(struct addr_desc *addr) {
  1293. unsigned int i;
  1294. unsigned long long address = 0x0;
  1295. unsigned int *page_table_entry;
  1296. int process_id = GetProcessID();
  1297. enum MMURegion e = MMU_REGION_COUNT;
  1298. enum MMUStatus status = MMU_STATUS_OUT_OF_MEMORY;
  1299. struct MMUNode *p;
  1300. unsigned int mutex = MMU_FALSE;
  1301. MMUDEBUG(" *****MMU Unmap*****\n");
  1302. AcquireMutex(g_mmu->page_table_mutex, MMU_INFINITE);
  1303. mutex = MMU_TRUE;
  1304. GetPhysicalAddress(addr->virtual_address, &address);
  1305. if(address >= REGION_IN_START &&
  1306. address < REGION_IN_END)
  1307. e = MMU_REGION_IN;
  1308. else if(address >= REGION_OUT_START &&
  1309. address < REGION_OUT_END)
  1310. e = MMU_REGION_OUT;
  1311. else if(address >= REGION_PRIVATE_START &&
  1312. address < REGION_PRIVATE_END)
  1313. e = MMU_REGION_PRIVATE;
  1314. else
  1315. e = MMU_REGION_PUB;
  1316. if (simple_map)
  1317. p = g_mmu->region[e].simple_map_head->next;
  1318. else
  1319. p = g_mmu->region[e].map_head->next;
  1320. /* Reset STLB of the node */
  1321. while(p) {
  1322. if(p->buf_virtual_address == addr->virtual_address &&
  1323. p->process_id == process_id) {
  1324. for(i = 0;i < p->page_count; i++) {
  1325. GetPageEntry(p, &page_table_entry, i);
  1326. address = 0;
  1327. WritePageEntry(page_table_entry, address);
  1328. }
  1329. break;
  1330. }
  1331. p = p->next;
  1332. }
  1333. if(!p)
  1334. goto onerror;
  1335. if (simple_map)
  1336. SMRemoveNode(e, addr->virtual_address, process_id);
  1337. else
  1338. RemoveNode(e, addr->virtual_address, process_id);
  1339. ReleaseMutex(g_mmu->page_table_mutex);
  1340. return MMU_STATUS_OK;
  1341. onerror:
  1342. if (mutex) {
  1343. ReleaseMutex(g_mmu->page_table_mutex);
  1344. }
  1345. MMUDEBUG(" *****MMU Unmap Error*****\n");
  1346. return status;
  1347. }
  1348. enum MMUStatus MMUKernelMemNodeMap(struct kernel_addr_desc *addr) {
  1349. enum MMUStatus status;
  1350. unsigned int page_count = 0;
  1351. unsigned int i = 0;
  1352. struct MMUNode *p;
  1353. unsigned long long address = 0x0;
  1354. unsigned int *page_table_entry;
  1355. enum MMURegion e;
  1356. unsigned int mutex = MMU_FALSE;
  1357. u32 ext_addr;
  1358. u32 page_entry_value = 0;
  1359. MMUDEBUG(" *****MMU Map*****\n");
  1360. AcquireMutex(g_mmu->page_table_mutex, MMU_INFINITE);
  1361. mutex = MMU_TRUE;
  1362. page_count = (addr->size - 1)/PAGE_SIZE + 1;
  1363. address = addr->bus_address;
  1364. MMUDEBUG(" *****MMU map address*****%x\n", address);
  1365. if(address >= REGION_IN_START &&
  1366. address + addr->size < REGION_IN_END)
  1367. e = MMU_REGION_IN;
  1368. else if(address >= REGION_OUT_START &&
  1369. address + addr->size < REGION_OUT_END)
  1370. e = MMU_REGION_OUT;
  1371. else if(address >= REGION_PRIVATE_START &&
  1372. address + addr->size < REGION_PRIVATE_END)
  1373. e = MMU_REGION_PRIVATE;
  1374. else
  1375. e = MMU_REGION_PUB;
  1376. if (simple_map) {
  1377. //TODO: should check bus addr
  1378. //MMU_ON_ERROR(SMCheckAddress(e, addr->virtual_address));
  1379. SMCreateNode(e, &p, page_count);
  1380. MMUDEBUG(" *****Node map size*****%d\n", page_count);
  1381. p->buf_bus_address = addr->bus_address;
  1382. p->process_id = GetProcessID();
  1383. p->filp = NULL;
  1384. p->mtlb_start = ((address + map_shift) >> MMU_MTLB_SHIFT);
  1385. p->stlb_start = ((address + map_shift) >> MMU_STLB_4K_SHIFT ) & 0x3FF;
  1386. p->mtlb_end = (page_count + p->stlb_start) / MMU_STLB_4K_ENTRY_NUM +
  1387. p->mtlb_start;
  1388. p->stlb_end = (page_count + p->stlb_start) % MMU_STLB_4K_ENTRY_NUM;
  1389. p->page_count = page_count;
  1390. for(i = 0;i < page_count; i++) {
  1391. /* this function used in kernel only, so we think it's a contunuous buffer*/
  1392. address += (i ? PAGE_SIZE : 0);
  1393. GetPageEntry(p, &page_table_entry, i);
  1394. ext_addr = ((u32)(address>>32))&0xff;
  1395. page_entry_value = (address & 0xFFFFF000)
  1396. /* ext address , physical address bits [39,32]*/
  1397. | (ext_addr << 4)
  1398. /* writable */
  1399. | (1 << 2)
  1400. /* Ignore exception */
  1401. | (0 << 1)
  1402. /* Present */
  1403. | (1 << 0);
  1404. WritePageEntry(page_table_entry, page_entry_value);
  1405. }
  1406. /* Purpose of Bare_metal mode: input bus address==mmu address*/
  1407. addr->mmu_bus_address = p->mtlb_start << MMU_MTLB_SHIFT
  1408. | p->stlb_start << MMU_STLB_4K_SHIFT;
  1409. } else {
  1410. MMU_ON_ERROR(FindFreeNode(e, &p, page_count));
  1411. SplitFreeNode(e, &p, page_count);
  1412. MMUDEBUG(" *****Node map size*****%d\n", p->page_count);
  1413. p->buf_bus_address = addr->bus_address;
  1414. p->process_id = GetProcessID();
  1415. p->filp = NULL;
  1416. for(i = 0;i < page_count; i++) {
  1417. /* this function used in kernel only, so we think it's a contunuous buffer*/
  1418. address += (i ? PAGE_SIZE : 0);
  1419. GetPageEntry(p, &page_table_entry, i);
  1420. ext_addr = ((u32)(address>>32))&0xff;
  1421. page_entry_value = (address & 0xFFFFF000)
  1422. /* ext address , physical address bits [39,32]*/
  1423. | (ext_addr << 4)
  1424. /* writable */
  1425. | (1 << 2)
  1426. /* Ignore exception */
  1427. | (0 << 1)
  1428. /* Present */
  1429. | (1 << 0);
  1430. WritePageEntry(page_table_entry, page_entry_value);
  1431. }
  1432. addr->mmu_bus_address = p->mtlb_start << MMU_MTLB_SHIFT
  1433. | p->stlb_start << MMU_STLB_4K_SHIFT;
  1434. }
  1435. MMUDEBUG(" KERNEL MMU_MTLB_SHIFT %d MMU_STLB_4K_SHIFT %d\n", MMU_MTLB_SHIFT, MMU_STLB_4K_SHIFT);
  1436. MMUDEBUG(" MMUKernelMemNodeMap map total %d pages in region %d\nMTLB/STLB starts %d/%d, MTLB/STLB ends %d/%d\n",
  1437. page_count, (u32)e, p->mtlb_start, p->stlb_start, p->mtlb_end, p->stlb_end);
  1438. MMUDEBUG(" MMUKernelMemNodeMap map 0x%llx -> 0x%08x\n", addr->bus_address, addr->mmu_bus_address);
  1439. ReleaseMutex(g_mmu->page_table_mutex);
  1440. return MMU_STATUS_OK;
  1441. onerror:
  1442. if (mutex) {
  1443. ReleaseMutex(g_mmu->page_table_mutex);
  1444. }
  1445. MMUDEBUG(" *****MMU Map Error*****\n");
  1446. return status;
  1447. }
  1448. enum MMUStatus MMUKernelMemNodeUnmap(struct kernel_addr_desc *addr) {
  1449. unsigned int i;
  1450. unsigned long long address = 0x0;
  1451. unsigned int *page_table_entry;
  1452. int process_id = GetProcessID();
  1453. enum MMURegion e = MMU_REGION_COUNT;
  1454. enum MMUStatus status = MMU_STATUS_OUT_OF_MEMORY;
  1455. struct MMUNode *p;
  1456. unsigned int mutex = MMU_FALSE;
  1457. MMUDEBUG(" *****MMU Unmap*****\n");
  1458. AcquireMutex(g_mmu->page_table_mutex, MMU_INFINITE);
  1459. mutex = MMU_TRUE;
  1460. address = addr->bus_address;
  1461. if(address >= REGION_IN_START &&
  1462. address < REGION_IN_END)
  1463. e = MMU_REGION_IN;
  1464. else if(address >= REGION_OUT_START &&
  1465. address < REGION_OUT_END)
  1466. e = MMU_REGION_OUT;
  1467. else if(address >= REGION_PRIVATE_START &&
  1468. address < REGION_PRIVATE_END)
  1469. e = MMU_REGION_PRIVATE;
  1470. else
  1471. e = MMU_REGION_PUB;
  1472. if (simple_map)
  1473. p = g_mmu->region[e].simple_map_head->next;
  1474. else
  1475. p = g_mmu->region[e].map_head->next;
  1476. /* Reset STLB of the node */
  1477. while(p) {
  1478. if(p->buf_bus_address == addr->bus_address &&
  1479. p->process_id == process_id) {
  1480. for(i = 0;i < p->page_count; i++) {
  1481. GetPageEntry(p, &page_table_entry, i);
  1482. address = 0;
  1483. WritePageEntry(page_table_entry, address);
  1484. }
  1485. break;
  1486. }
  1487. p = p->next;
  1488. }
  1489. if(!p)
  1490. goto onerror;
  1491. if (simple_map)
  1492. SMRemoveKernelNode(e, addr->bus_address, process_id);
  1493. else
  1494. RemoveKernelNode(e, addr->bus_address, process_id);
  1495. ReleaseMutex(g_mmu->page_table_mutex);
  1496. return MMU_STATUS_OK;
  1497. onerror:
  1498. if (mutex) {
  1499. ReleaseMutex(g_mmu->page_table_mutex);
  1500. }
  1501. MMUDEBUG(" *****MMU Unmap Error*****\n");
  1502. return status;
  1503. }
  1504. static long MMUCtlBufferMap(struct file *filp, unsigned long arg) {
  1505. struct addr_desc addr;
  1506. long tmp;
  1507. tmp = copy_from_user(&addr, (void*)arg, sizeof(struct addr_desc));
  1508. if (tmp) {
  1509. MMUDEBUG("copy_from_user failed, returned %li\n", tmp);
  1510. return -MMU_EFAULT;
  1511. }
  1512. MMUMemNodeMap(&addr, filp);
  1513. tmp = copy_to_user((void*) arg, &addr, sizeof(struct addr_desc));
  1514. if (tmp) {
  1515. MMUDEBUG("copy_to_user failed, returned %li\n", tmp);
  1516. return -MMU_EFAULT;
  1517. }
  1518. return 0;
  1519. }
  1520. static long MMUCtlBufferUnmap(unsigned long arg) {
  1521. struct addr_desc addr;
  1522. long tmp;
  1523. tmp = copy_from_user(&addr, (void*)arg, sizeof(struct addr_desc));
  1524. if (tmp) {
  1525. MMUDEBUG("copy_from_user failed, returned %li\n", tmp);
  1526. return -MMU_EFAULT;
  1527. }
  1528. MMUMemNodeUnmap(&addr);
  1529. return 0;
  1530. }
  1531. static long MMUCtlEnable(unsigned long arg, volatile unsigned char *hwregs[HXDEC_MAX_CORES][2]) {
  1532. unsigned int enable;
  1533. long tmp;
  1534. tmp = copy_from_user(&enable, (void*)arg, sizeof(unsigned int));
  1535. if (tmp) {
  1536. MMUDEBUG("copy_from_user failed, returned %li\n", tmp);
  1537. return -MMU_EFAULT;
  1538. }
  1539. MMUEnable(hwregs);
  1540. return 0;
  1541. }
  1542. static long MMUCtlFlush(unsigned long arg, volatile unsigned char *hwregs[HXDEC_MAX_CORES][2]) {
  1543. unsigned int core_id;
  1544. long tmp;
  1545. tmp = copy_from_user(&core_id, (void*)arg, sizeof(unsigned int));
  1546. if (tmp) {
  1547. MMUDEBUG("copy_from_user failed, returned %li\n", tmp);
  1548. return -MMU_EFAULT;
  1549. }
  1550. MMUFlush(core_id, hwregs);
  1551. return 0;
  1552. }
  1553. long MMUIoctl(unsigned int cmd, void *filp, unsigned long arg,
  1554. volatile unsigned char *hwregs[HXDEC_MAX_CORES][2]) {
  1555. u32 i = 0;
  1556. for (i = 0; i < MAX_SUBSYS_NUM; i++) {
  1557. if (hwregs[i][0] != NULL &&
  1558. (ioread32((void*)(hwregs[i][0] + MMU_REG_HW_ID))>>16) != 0x4D4D)
  1559. return -MMU_ENOTTY;
  1560. if (hwregs[i][1] != NULL &&
  1561. (ioread32((void*)(hwregs[i][1] + MMU_REG_HW_ID))>>16) != 0x4D4D)
  1562. return -MMU_ENOTTY;
  1563. MMUDEBUG("mmu_hwregs[%d][0].mmu_hwregs[0]=%p", i, hwregs[i][0]);
  1564. MMUDEBUG("mmu_hwregs[%d][1].mmu_hwregs[0]=%p", i, hwregs[i][1]);
  1565. }
  1566. switch (cmd) {
  1567. case HANTRO_IOCS_MMU_MEM_MAP: {
  1568. return (MMUCtlBufferMap((struct file *)filp, arg));
  1569. }
  1570. case HANTRO_IOCS_MMU_MEM_UNMAP: {
  1571. return (MMUCtlBufferUnmap(arg));
  1572. }
  1573. case HANTRO_IOCS_MMU_ENABLE: {
  1574. return (MMUCtlEnable(arg, hwregs));
  1575. }
  1576. case HANTRO_IOCS_MMU_FLUSH: {
  1577. return (MMUCtlFlush(arg, hwregs));
  1578. }
  1579. default:
  1580. return -MMU_ENOTTY;
  1581. }
  1582. }
  1583. unsigned long long GetMMUAddress(void)
  1584. {
  1585. unsigned long long address = 0;
  1586. if(pcie)
  1587. address = PAGE_PCIE_START_ADDRESS;
  1588. else
  1589. address = g_mmu->page_table_array_physical;
  1590. return address;
  1591. }
  1592. void MMURestore(volatile unsigned char *hwregs[MAX_SUBSYS_NUM][2])
  1593. {
  1594. if (g_mmu == NULL)
  1595. return;
  1596. int i;
  1597. unsigned int address;
  1598. u32 address_ext;
  1599. address = g_mmu->page_table_array_physical;
  1600. address_ext = ((u32)(g_mmu->page_table_array_physical >> 32))&0xff;
  1601. for (i = 0; i < MAX_SUBSYS_NUM; i++) {
  1602. if (hwregs[i][0] != NULL) {
  1603. iowrite32(address, (void*)(hwregs[i][0] + MMU_REG_ADDRESS));
  1604. iowrite32(address_ext, (void *)(hwregs[i][0] + MMU_REG_ADDRESS_MSB));
  1605. iowrite32(0x10000, (void*)(hwregs[i][0] + MMU_REG_PAGE_TABLE_ID));
  1606. iowrite32(0x00000, (void*)(hwregs[i][0] + MMU_REG_PAGE_TABLE_ID));
  1607. iowrite32(1, (void*)(hwregs[i][0] + MMU_REG_CONTROL));
  1608. }
  1609. if (hwregs[i][1] != NULL) {
  1610. iowrite32(address, (void*)(hwregs[i][1] + MMU_REG_ADDRESS));
  1611. iowrite32(address_ext, (void *)(hwregs[i][1] + MMU_REG_ADDRESS_MSB));
  1612. iowrite32(0x10000, (void*)(hwregs[i][1] + MMU_REG_PAGE_TABLE_ID));
  1613. iowrite32(0x00000, (void*)(hwregs[i][1] + MMU_REG_PAGE_TABLE_ID));
  1614. iowrite32(1, (void*)(hwregs[i][1] + MMU_REG_CONTROL));
  1615. }
  1616. }
  1617. }