hantro_vcmd.c 149 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2014 - 2021 VERISILICON
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (C) 2014 - 2021 VERISILICON
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program; if not, write to the Free Software Foundation,
  43. * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  44. *
  45. *****************************************************************************
  46. *
  47. * Note: This software is released under dual MIT and GPL licenses. A
  48. * recipient may use this file under the terms of either the MIT license or
  49. * GPL License. If you wish to use only one license not the other, you can
  50. * indicate your decision by deleting one of the above license notices in your
  51. * version of this file.
  52. *
  53. *****************************************************************************/
  54. #include <linux/kernel.h>
  55. #include <linux/module.h>
  56. /* needed for __init,__exit directives */
  57. #include <linux/init.h>
  58. /* needed for remap_page_range
  59. SetPageReserved
  60. ClearPageReserved
  61. */
  62. #include <linux/mm.h>
  63. /* obviously, for kmalloc */
  64. #include <linux/slab.h>
  65. /* for struct file_operations, register_chrdev() */
  66. #include <linux/fs.h>
  67. /* standard error codes */
  68. #include <linux/errno.h>
  69. #include <linux/moduleparam.h>
  70. /* request_irq(), free_irq() */
  71. #include <linux/interrupt.h>
  72. #include <linux/sched.h>
  73. #include <linux/semaphore.h>
  74. #include <linux/spinlock.h>
  75. /* needed for virt_to_phys() */
  76. #include <asm/io.h>
  77. #include <linux/pci.h>
  78. #include <linux/uaccess.h>
  79. #include <linux/ioport.h>
  80. #include <asm/irq.h>
  81. #include <linux/version.h>
  82. #include <linux/vmalloc.h>
  83. #include <linux/timer.h>
  84. #include <linux/delay.h>
  85. #include <linux/pm_runtime.h>
  86. /* our own stuff */
  87. #include <linux/platform_device.h>
  88. #include "vcmdswhwregisters.h"
  89. #include "bidirect_list.h"
  90. #include "vcmdswhwregisters.h"
  91. #include "hantrovcmd.h"
  92. #include "subsys.h"
  93. /*
  94. * Macros to help debugging
  95. */
  96. #undef PDEBUG /* undef it, just in case */
  97. //#define HANTRO_VCMD_DRIVER_DEBUG
  98. #ifdef HANTRO_VCMD_DRIVER_DEBUG
  99. # ifdef __KERNEL__
  100. /* This one if debugging is on, and kernel space */
  101. # define PDEBUG(fmt, args...) printk( KERN_INFO "vc8000_vcmd: " fmt, ## args)
  102. # else
  103. /* This one for user space */
  104. # define PDEBUG(fmt, args...) printf(__FILE__ ":%d: " fmt, __LINE__ , ## args)
  105. # endif
  106. #else
  107. # define PDEBUG(fmt, args...) /* not debugging: nothing */
  108. #endif
  109. /*------------------------------------------------------------------------
  110. *****************************VCMD CONFIGURATION BY CUSTOMER********************************
  111. -------------------------------------------------------------------------*/
  112. //video encoder vcmd configuration
  113. #define VCMD_ENC_IO_ADDR_0 0x90000 /*customer specify according to own platform*/
  114. #define VCMD_ENC_IO_SIZE_0 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  115. #define VCMD_ENC_INT_PIN_0 -1
  116. #define VCMD_ENC_MODULE_TYPE_0 0
  117. #define VCMD_ENC_MODULE_MAIN_ADDR_0 0x0000 /*customer specify according to own platform*/
  118. #define VCMD_ENC_MODULE_DEC400_ADDR_0 0XFFFF /*0xffff means no such kind of submodule*/
  119. #define VCMD_ENC_MODULE_L2CACHE_ADDR_0 0XFFFF
  120. #define VCMD_ENC_MODULE_MMU_ADDR_0 0XFFFF
  121. #define VCMD_ENC_IO_ADDR_1 0x91000 /*customer specify according to own platform*/
  122. #define VCMD_ENC_IO_SIZE_1 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  123. #define VCMD_ENC_INT_PIN_1 -1
  124. #define VCMD_ENC_MODULE_TYPE_1 0
  125. #define VCMD_ENC_MODULE_MAIN_ADDR_1 0x0000 /*customer specify according to own platform*/
  126. #define VCMD_ENC_MODULE_DEC400_ADDR_1 0XFFFF /*0xffff means no such kind of submodule*/
  127. #define VCMD_ENC_MODULE_L2CACHE_ADDR_1 0XFFFF
  128. #define VCMD_ENC_MODULE_MMU_ADDR_1 0XFFFF
  129. #define VCMD_ENC_IO_ADDR_2 0x92000 /*customer specify according to own platform*/
  130. #define VCMD_ENC_IO_SIZE_2 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  131. #define VCMD_ENC_INT_PIN_2 -1
  132. #define VCMD_ENC_MODULE_TYPE_2 0
  133. #define VCMD_ENC_MODULE_MAIN_ADDR_2 0x0000 /*customer specify according to own platform*/
  134. #define VCMD_ENC_MODULE_DEC400_ADDR_2 0XFFFF /*0xffff means no such kind of submodule*/
  135. #define VCMD_ENC_MODULE_L2CACHE_ADDR_2 0XFFFF
  136. #define VCMD_ENC_MODULE_MMU_ADDR_2 0XFFFF
  137. #define VCMD_ENC_IO_ADDR_3 0x93000 /*customer specify according to own platform*/
  138. #define VCMD_ENC_IO_SIZE_3 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  139. #define VCMD_ENC_INT_PIN_3 -1
  140. #define VCMD_ENC_MODULE_TYPE_3 0
  141. #define VCMD_ENC_MODULE_MAIN_ADDR_3 0x0000 /*customer specify according to own platform*/
  142. #define VCMD_ENC_MODULE_DEC400_ADDR_3 0XFFFF /*0xffff means no such kind of submodule*/
  143. #define VCMD_ENC_MODULE_L2CACHE_ADDR_3 0XFFFF
  144. #define VCMD_ENC_MODULE_MMU_ADDR_3 0XFFFF
  145. //video encoder cutree/IM vcmd configuration
  146. #define VCMD_IM_IO_ADDR_0 0xa0000 /*customer specify according to own platform*/
  147. #define VCMD_IM_IO_SIZE_0 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  148. #define VCMD_IM_INT_PIN_0 -1
  149. #define VCMD_IM_MODULE_TYPE_0 1
  150. #define VCMD_IM_MODULE_MAIN_ADDR_0 0x0000 /*customer specify according to own platform*/
  151. #define VCMD_IM_MODULE_DEC400_ADDR_0 0XFFFF /*0xffff means no such kind of submodule*/
  152. #define VCMD_IM_MODULE_L2CACHE_ADDR_0 0XFFFF
  153. #define VCMD_IM_MODULE_MMU_ADDR_0 0XFFFF
  154. #define VCMD_IM_IO_ADDR_1 0xa1000 /*customer specify according to own platform*/
  155. #define VCMD_IM_IO_SIZE_1 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  156. #define VCMD_IM_INT_PIN_1 -1
  157. #define VCMD_IM_MODULE_TYPE_1 1
  158. #define VCMD_IM_MODULE_MAIN_ADDR_1 0x0000 /*customer specify according to own platform*/
  159. #define VCMD_IM_MODULE_DEC400_ADDR_1 0XFFFF /*0xffff means no such kind of submodule*/
  160. #define VCMD_IM_MODULE_L2CACHE_ADDR_1 0XFFFF
  161. #define VCMD_IM_MODULE_MMU_ADDR_1 0XFFFF
  162. #define VCMD_IM_IO_ADDR_2 0xa2000 /*customer specify according to own platform*/
  163. #define VCMD_IM_IO_SIZE_2 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  164. #define VCMD_IM_INT_PIN_2 -1
  165. #define VCMD_IM_MODULE_TYPE_2 1
  166. #define VCMD_IM_MODULE_MAIN_ADDR_2 0x0000 /*customer specify according to own platform*/
  167. #define VCMD_IM_MODULE_DEC400_ADDR_2 0XFFFF /*0xffff means no such kind of submodule*/
  168. #define VCMD_IM_MODULE_L2CACHE_ADDR_2 0XFFFF
  169. #define VCMD_IM_MODULE_MMU_ADDR_2 0XFFFF
  170. #define VCMD_IM_IO_ADDR_3 0xa3000 /*customer specify according to own platform*/
  171. #define VCMD_IM_IO_SIZE_3 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  172. #define VCMD_IM_INT_PIN_3 -1
  173. #define VCMD_IM_MODULE_TYPE_3 1
  174. #define VCMD_IM_MODULE_MAIN_ADDR_3 0x0000 /*customer specify according to own platform*/
  175. #define VCMD_IM_MODULE_DEC400_ADDR_3 0XFFFF /*0xffff means no such kind of submodule*/
  176. #define VCMD_IM_MODULE_L2CACHE_ADDR_3 0XFFFF
  177. #define VCMD_IM_MODULE_MMU_ADDR_3 0XFFFF
  178. //video decoder vcmd configuration
  179. #define VCMD_DEC_IO_ADDR_0 0x600000 /*customer specify according to own platform*/
  180. #define VCMD_DEC_IO_SIZE_0 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  181. #define VCMD_DEC_INT_PIN_0 -1
  182. #define VCMD_DEC_MODULE_TYPE_0 2
  183. #define VCMD_DEC_MODULE_MAIN_ADDR_0 0x1000 /*customer specify according to own platform*/
  184. #define VCMD_DEC_MODULE_DEC400_ADDR_0 0XFFFF /*0xffff means no such kind of submodule*/
  185. #define VCMD_DEC_MODULE_L2CACHE_ADDR_0 0X2000
  186. #define VCMD_DEC_MODULE_MMU_ADDR_0 0XFFFF
  187. #define VCMD_DEC_IO_ADDR_1 0x700000 /*customer specify according to own platform*/
  188. #define VCMD_DEC_IO_SIZE_1 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  189. #define VCMD_DEC_INT_PIN_1 -1
  190. #define VCMD_DEC_MODULE_TYPE_1 2
  191. #define VCMD_DEC_MODULE_MAIN_ADDR_1 0x1000 /*customer specify according to own platform*/
  192. #define VCMD_DEC_MODULE_DEC400_ADDR_1 0XFFFF /*0xffff means no such kind of submodule*/
  193. #define VCMD_DEC_MODULE_L2CACHE_ADDR_1 0X2000
  194. #define VCMD_DEC_MODULE_MMU_ADDR_1 0XFFFF
  195. #define VCMD_DEC_IO_ADDR_2 0xb2000 /*customer specify according to own platform*/
  196. #define VCMD_DEC_IO_SIZE_2 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  197. #define VCMD_DEC_INT_PIN_2 -1
  198. #define VCMD_DEC_MODULE_TYPE_2 2
  199. #define VCMD_DEC_MODULE_MAIN_ADDR_2 0x0000 /*customer specify according to own platform*/
  200. #define VCMD_DEC_MODULE_DEC400_ADDR_2 0XFFFF /*0xffff means no such kind of submodule*/
  201. #define VCMD_DEC_MODULE_L2CACHE_ADDR_2 0XFFFF
  202. #define VCMD_DEC_MODULE_MMU_ADDR_2 0XFFFF
  203. #define VCMD_DEC_IO_ADDR_3 0xb3000 /*customer specify according to own platform*/
  204. #define VCMD_DEC_IO_SIZE_3 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  205. #define VCMD_DEC_INT_PIN_3 -1
  206. #define VCMD_DEC_MODULE_TYPE_3 2
  207. #define VCMD_DEC_MODULE_MAIN_ADDR_3 0x0000 /*customer specify according to own platform*/
  208. #define VCMD_DEC_MODULE_DEC400_ADDR_3 0XFFFF /*0xffff means no such kind of submodule*/
  209. #define VCMD_DEC_MODULE_L2CACHE_ADDR_3 0XFFFF
  210. #define VCMD_DEC_MODULE_MMU_ADDR_3 0XFFFF
  211. //JPEG encoder vcmd configuration
  212. #define VCMD_JPEGE_IO_ADDR_0 0x90000 /*customer specify according to own platform*/
  213. #define VCMD_JPEGE_IO_SIZE_0 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  214. #define VCMD_JPEGE_INT_PIN_0 -1
  215. #define VCMD_JPEGE_MODULE_TYPE_0 3
  216. #define VCMD_JPEGE_MODULE_MAIN_ADDR_0 0x1000 /*customer specify according to own platform*/
  217. #define VCMD_JPEGE_MODULE_DEC400_ADDR_0 0XFFFF /*0xffff means no such kind of submodule*/
  218. #define VCMD_JPEGE_MODULE_L2CACHE_ADDR_0 0XFFFF
  219. #define VCMD_JPEGE_MODULE_MMU_ADDR_0 0XFFFF
  220. #define VCMD_JPEGE_IO_ADDR_1 0xC1000 /*customer specify according to own platform*/
  221. #define VCMD_JPEGE_IO_SIZE_1 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  222. #define VCMD_JPEGE_INT_PIN_1 -1
  223. #define VCMD_JPEGE_MODULE_TYPE_1 3
  224. #define VCMD_JPEGE_MODULE_MAIN_ADDR_1 0x0000 /*customer specify according to own platform*/
  225. #define VCMD_JPEGE_MODULE_DEC400_ADDR_1 0XFFFF /*0xffff means no such kind of submodule*/
  226. #define VCMD_JPEGE_MODULE_L2CACHE_ADDR_1 0XFFFF
  227. #define VCMD_JPEGE_MODULE_MMU_ADDR_1 0XFFFF
  228. #define VCMD_JPEGE_IO_ADDR_2 0xC2000 /*customer specify according to own platform*/
  229. #define VCMD_JPEGE_IO_SIZE_2 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  230. #define VCMD_JPEGE_INT_PIN_2 -1
  231. #define VCMD_JPEGE_MODULE_TYPE_2 3
  232. #define VCMD_JPEGE_MODULE_MAIN_ADDR_2 0x0000 /*customer specify according to own platform*/
  233. #define VCMD_JPEGE_MODULE_DEC400_ADDR_2 0XFFFF /*0xffff means no such kind of submodule*/
  234. #define VCMD_JPEGE_MODULE_L2CACHE_ADDR_2 0XFFFF
  235. #define VCMD_JPEGE_MODULE_MMU_ADDR_2 0XFFFF
  236. #define VCMD_JPEGE_IO_ADDR_3 0xC3000 /*customer specify according to own platform*/
  237. #define VCMD_JPEGE_IO_SIZE_3 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  238. #define VCMD_JPEGE_INT_PIN_3 -1
  239. #define VCMD_JPEGE_MODULE_TYPE_3 3
  240. #define VCMD_JPEGE_MODULE_MAIN_ADDR_3 0x0000 /*customer specify according to own platform*/
  241. #define VCMD_JPEGE_MODULE_DEC400_ADDR_3 0XFFFF /*0xffff means no such kind of submodule*/
  242. #define VCMD_JPEGE_MODULE_L2CACHE_ADDR_3 0XFFFF
  243. #define VCMD_JPEGE_MODULE_MMU_ADDR_3 0XFFFF
  244. //JPEG decoder vcmd configuration
  245. #define VCMD_JPEGD_IO_ADDR_0 0x600000 /*customer specify according to own platform*/
  246. #define VCMD_JPEGD_IO_SIZE_0 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  247. #define VCMD_JPEGD_INT_PIN_0 -1
  248. #define VCMD_JPEGD_MODULE_TYPE_0 4
  249. #define VCMD_JPEGD_MODULE_MAIN_ADDR_0 0x1000 /*customer specify according to own platform*/
  250. #define VCMD_JPEGD_MODULE_DEC400_ADDR_0 0XFFFF /*0xffff means no such kind of submodule*/
  251. #define VCMD_JPEGD_MODULE_L2CACHE_ADDR_0 0XFFFF
  252. #define VCMD_JPEGD_MODULE_MMU_ADDR_0 0XFFFF
  253. #define VCMD_JPEGD_IO_ADDR_1 0xD1000 /*customer specify according to own platform*/
  254. #define VCMD_JPEGD_IO_SIZE_1 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  255. #define VCMD_JPEGD_INT_PIN_1 -1
  256. #define VCMD_JPEGD_MODULE_TYPE_1 4
  257. #define VCMD_JPEGD_MODULE_MAIN_ADDR_1 0x0000 /*customer specify according to own platform*/
  258. #define VCMD_JPEGD_MODULE_DEC400_ADDR_1 0XFFFF /*0xffff means no such kind of submodule*/
  259. #define VCMD_JPEGD_MODULE_L2CACHE_ADDR_1 0XFFFF
  260. #define VCMD_JPEGD_MODULE_MMU_ADDR_1 0XFFFF
  261. #define VCMD_JPEGD_IO_ADDR_2 0xD2000 /*customer specify according to own platform*/
  262. #define VCMD_JPEGD_IO_SIZE_2 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  263. #define VCMD_JPEGD_INT_PIN_2 -1
  264. #define VCMD_JPEGD_MODULE_TYPE_2 4
  265. #define VCMD_JPEGD_MODULE_MAIN_ADDR_2 0x0000 /*customer specify according to own platform*/
  266. #define VCMD_JPEGD_MODULE_DEC400_ADDR_2 0XFFFF /*0xffff means no such kind of submodule*/
  267. #define VCMD_JPEGD_MODULE_L2CACHE_ADDR_2 0XFFFF
  268. #define VCMD_JPEGD_MODULE_MMU_ADDR_2 0XFFFF
  269. #define VCMD_JPEGD_IO_ADDR_3 0xD3000 /*customer specify according to own platform*/
  270. #define VCMD_JPEGD_IO_SIZE_3 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  271. #define VCMD_JPEGD_INT_PIN_3 -1
  272. #define VCMD_JPEGD_MODULE_TYPE_3 4
  273. #define VCMD_JPEGD_MODULE_MAIN_ADDR_3 0x0000 /*customer specify according to own platform*/
  274. #define VCMD_JPEGD_MODULE_DEC400_ADDR_3 0XFFFF /*0xffff means no such kind of submodule*/
  275. #define VCMD_JPEGD_MODULE_L2CACHE_ADDR_3 0XFFFF
  276. #define VCMD_JPEGD_MODULE_MMU_ADDR_3 0XFFFF
  277. /*for all vcmds, the core info should be listed here for subsequent use*/
  278. struct vcmd_config vcmd_core_array[MAX_SUBSYS_NUM]= {
  279. #if 0
  280. //encoder configuration
  281. {VCMD_ENC_IO_ADDR_0,
  282. VCMD_ENC_IO_SIZE_0,
  283. VCMD_ENC_INT_PIN_0,
  284. VCMD_ENC_MODULE_TYPE_0,
  285. VCMD_ENC_MODULE_MAIN_ADDR_0,
  286. VCMD_ENC_MODULE_DEC400_ADDR_0,
  287. VCMD_ENC_MODULE_L2CACHE_ADDR_0,
  288. VCMD_ENC_MODULE_MMU_ADDR_0},
  289. {VCMD_ENC_IO_ADDR_1,
  290. VCMD_ENC_IO_SIZE_1,
  291. VCMD_ENC_INT_PIN_1,
  292. VCMD_ENC_MODULE_TYPE_1,
  293. VCMD_ENC_MODULE_MAIN_ADDR_1,
  294. VCMD_ENC_MODULE_DEC400_ADDR_1,
  295. VCMD_ENC_MODULE_L2CACHE_ADDR_1,
  296. VCMD_ENC_MODULE_MMU_ADDR_1},
  297. {VCMD_ENC_IO_ADDR_2,
  298. VCMD_ENC_IO_SIZE_2,
  299. VCMD_ENC_INT_PIN_2,
  300. VCMD_ENC_MODULE_TYPE_2,
  301. VCMD_ENC_MODULE_MAIN_ADDR_2,
  302. VCMD_ENC_MODULE_DEC400_ADDR_2,
  303. VCMD_ENC_MODULE_L2CACHE_ADDR_2,
  304. VCMD_ENC_MODULE_MMU_ADDR_2},
  305. {VCMD_ENC_IO_ADDR_3,
  306. VCMD_ENC_IO_SIZE_3,
  307. VCMD_ENC_INT_PIN_3,
  308. VCMD_ENC_MODULE_TYPE_3,
  309. VCMD_ENC_MODULE_MAIN_ADDR_3,
  310. VCMD_ENC_MODULE_DEC400_ADDR_3,
  311. VCMD_ENC_MODULE_L2CACHE_ADDR_3,
  312. VCMD_ENC_MODULE_MMU_ADDR_3},
  313. //cutree/IM configuration
  314. {VCMD_IM_IO_ADDR_0,
  315. VCMD_IM_IO_SIZE_0,
  316. VCMD_IM_INT_PIN_0,
  317. VCMD_IM_MODULE_TYPE_0,
  318. VCMD_IM_MODULE_MAIN_ADDR_0,
  319. VCMD_IM_MODULE_DEC400_ADDR_0,
  320. VCMD_IM_MODULE_L2CACHE_ADDR_0,
  321. VCMD_IM_MODULE_MMU_ADDR_0},
  322. {VCMD_IM_IO_ADDR_1,
  323. VCMD_IM_IO_SIZE_1,
  324. VCMD_IM_INT_PIN_1,
  325. VCMD_IM_MODULE_TYPE_1,
  326. VCMD_IM_MODULE_MAIN_ADDR_1,
  327. VCMD_IM_MODULE_DEC400_ADDR_1,
  328. VCMD_IM_MODULE_L2CACHE_ADDR_1,
  329. VCMD_IM_MODULE_MMU_ADDR_1},
  330. {VCMD_IM_IO_ADDR_2,
  331. VCMD_IM_IO_SIZE_2,
  332. VCMD_IM_INT_PIN_2,
  333. VCMD_IM_MODULE_TYPE_2,
  334. VCMD_IM_MODULE_MAIN_ADDR_2,
  335. VCMD_IM_MODULE_DEC400_ADDR_2,
  336. VCMD_IM_MODULE_L2CACHE_ADDR_2,
  337. VCMD_IM_MODULE_MMU_ADDR_2},
  338. {VCMD_IM_IO_ADDR_3,
  339. VCMD_IM_IO_SIZE_3,
  340. VCMD_IM_INT_PIN_3,
  341. VCMD_IM_MODULE_TYPE_3,
  342. VCMD_IM_MODULE_MAIN_ADDR_3,
  343. VCMD_IM_MODULE_DEC400_ADDR_3,
  344. VCMD_IM_MODULE_L2CACHE_ADDR_3,
  345. VCMD_IM_MODULE_MMU_ADDR_3},
  346. #endif
  347. //decoder configuration
  348. {VCMD_DEC_IO_ADDR_0,
  349. VCMD_DEC_IO_SIZE_0,
  350. VCMD_DEC_INT_PIN_0,
  351. VCMD_DEC_MODULE_TYPE_0,
  352. VCMD_DEC_MODULE_MAIN_ADDR_0,
  353. VCMD_DEC_MODULE_DEC400_ADDR_0,
  354. VCMD_DEC_MODULE_L2CACHE_ADDR_0,
  355. VCMD_DEC_MODULE_MMU_ADDR_0},
  356. {VCMD_DEC_IO_ADDR_1,
  357. VCMD_DEC_IO_SIZE_1,
  358. VCMD_DEC_INT_PIN_1,
  359. VCMD_DEC_MODULE_TYPE_1,
  360. VCMD_DEC_MODULE_MAIN_ADDR_1,
  361. VCMD_DEC_MODULE_DEC400_ADDR_1,
  362. VCMD_DEC_MODULE_L2CACHE_ADDR_1,
  363. VCMD_DEC_MODULE_MMU_ADDR_1},
  364. #if 0
  365. {VCMD_DEC_IO_ADDR_2,
  366. VCMD_DEC_IO_SIZE_2,
  367. VCMD_DEC_INT_PIN_2,
  368. VCMD_DEC_MODULE_TYPE_2,
  369. VCMD_DEC_MODULE_MAIN_ADDR_2,
  370. VCMD_DEC_MODULE_DEC400_ADDR_2,
  371. VCMD_DEC_MODULE_L2CACHE_ADDR_2,
  372. VCMD_DEC_MODULE_MMU_ADDR_2},
  373. {VCMD_DEC_IO_ADDR_3,
  374. VCMD_DEC_IO_SIZE_3,
  375. VCMD_DEC_INT_PIN_3,
  376. VCMD_DEC_MODULE_TYPE_3,
  377. VCMD_DEC_MODULE_MAIN_ADDR_3,
  378. VCMD_DEC_MODULE_DEC400_ADDR_3,
  379. VCMD_DEC_MODULE_L2CACHE_ADDR_3,
  380. VCMD_DEC_MODULE_MMU_ADDR_3},
  381. #endif
  382. #if 0
  383. //JPEG encoder configuration
  384. {VCMD_JPEGE_IO_ADDR_0,
  385. VCMD_JPEGE_IO_SIZE_0,
  386. VCMD_JPEGE_INT_PIN_0,
  387. VCMD_JPEGE_MODULE_TYPE_0,
  388. VCMD_JPEGE_MODULE_MAIN_ADDR_0,
  389. VCMD_JPEGE_MODULE_DEC400_ADDR_0,
  390. VCMD_JPEGE_MODULE_L2CACHE_ADDR_0,
  391. VCMD_JPEGE_MODULE_MMU_ADDR_0},
  392. #endif
  393. #if 0
  394. {VCMD_JPEGE_IO_ADDR_1,
  395. VCMD_JPEGE_IO_SIZE_1,
  396. VCMD_JPEGE_INT_PIN_1,
  397. VCMD_JPEGE_MODULE_TYPE_1,
  398. VCMD_JPEGE_MODULE_MAIN_ADDR_1,
  399. VCMD_JPEGE_MODULE_DEC400_ADDR_1,
  400. VCMD_JPEGE_MODULE_L2CACHE_ADDR_1,
  401. VCMD_JPEGE_MODULE_MMU_ADDR_1},
  402. {VCMD_JPEGE_IO_ADDR_2,
  403. VCMD_JPEGE_IO_SIZE_2,
  404. VCMD_JPEGE_INT_PIN_2,
  405. VCMD_JPEGE_MODULE_TYPE_2,
  406. VCMD_JPEGE_MODULE_MAIN_ADDR_2,
  407. VCMD_JPEGE_MODULE_DEC400_ADDR_2,
  408. VCMD_JPEGE_MODULE_L2CACHE_ADDR_2,
  409. VCMD_JPEGE_MODULE_MMU_ADDR_2},
  410. {VCMD_JPEGE_IO_ADDR_3,
  411. VCMD_JPEGE_IO_SIZE_3,
  412. VCMD_JPEGE_INT_PIN_3,
  413. VCMD_JPEGE_MODULE_TYPE_3,
  414. VCMD_JPEGE_MODULE_MAIN_ADDR_3,
  415. VCMD_JPEGE_MODULE_DEC400_ADDR_3,
  416. VCMD_JPEGE_MODULE_L2CACHE_ADDR_3,
  417. VCMD_JPEGE_MODULE_MMU_ADDR_3},
  418. //JPEG decoder configuration
  419. {VCMD_JPEGD_IO_ADDR_0,
  420. VCMD_JPEGD_IO_SIZE_0,
  421. VCMD_JPEGD_INT_PIN_0,
  422. VCMD_JPEGD_MODULE_TYPE_0,
  423. VCMD_JPEGD_MODULE_MAIN_ADDR_0,
  424. VCMD_JPEGD_MODULE_DEC400_ADDR_0,
  425. VCMD_JPEGD_MODULE_L2CACHE_ADDR_0,
  426. VCMD_JPEGD_MODULE_MMU_ADDR_0},
  427. {VCMD_JPEGD_IO_ADDR_1,
  428. VCMD_JPEGD_IO_SIZE_1,
  429. VCMD_JPEGD_INT_PIN_1,
  430. VCMD_JPEGD_MODULE_TYPE_1,
  431. VCMD_JPEGD_MODULE_MAIN_ADDR_1,
  432. VCMD_JPEGD_MODULE_DEC400_ADDR_1,
  433. VCMD_JPEGD_MODULE_L2CACHE_ADDR_1,
  434. VCMD_JPEGD_MODULE_MMU_ADDR_1},
  435. {VCMD_JPEGD_IO_ADDR_2,
  436. VCMD_JPEGD_IO_SIZE_2,
  437. VCMD_JPEGD_INT_PIN_2,
  438. VCMD_JPEGD_MODULE_TYPE_2,
  439. VCMD_JPEGD_MODULE_MAIN_ADDR_2,
  440. VCMD_JPEGD_MODULE_DEC400_ADDR_2,
  441. VCMD_JPEGD_MODULE_L2CACHE_ADDR_2,
  442. VCMD_JPEGD_MODULE_MMU_ADDR_2},
  443. {VCMD_JPEGD_IO_ADDR_3,
  444. VCMD_JPEGD_IO_SIZE_3,
  445. VCMD_JPEGD_INT_PIN_3,
  446. VCMD_JPEGD_MODULE_TYPE_3,
  447. VCMD_JPEGD_MODULE_MAIN_ADDR_3,
  448. VCMD_JPEGD_MODULE_DEC400_ADDR_3,
  449. VCMD_JPEGD_MODULE_L2CACHE_ADDR_3,
  450. VCMD_JPEGD_MODULE_MMU_ADDR_3},
  451. #endif
  452. };
  453. /*these size need to be modified according to hw config.*/
  454. #define VCMD_ENCODER_REGISTER_SIZE (479 * 4)
  455. #define VCMD_DECODER_REGISTER_SIZE (1023 * 4)
  456. #define VCMD_IM_REGISTER_SIZE (479 * 4)
  457. #define VCMD_JPEG_ENCODER_REGISTER_SIZE (479 * 4)
  458. #define VCMD_JPEG_DECODER_REGISTER_SIZE (1023 * 4)
  459. #define MAX_VCMD_NUMBER (MAX_VCMD_TYPE*MAX_SAME_MODULE_TYPE_CORE_NUMBER) //
  460. #define HW_WORK_STATE_PEND 3
  461. #define MAX_CMDBUF_INT_NUMBER 1
  462. #define INT_MIN_SUM_OF_IMAGE_SIZE (4096*2160*MAX_SAME_MODULE_TYPE_CORE_NUMBER*MAX_CMDBUF_INT_NUMBER)
  463. #define MAX_PROCESS_CORE_NUMBER 4*8
  464. #define PROCESS_MAX_VIDEO_SIZE (4096*2160*MAX_SAME_MODULE_TYPE_CORE_NUMBER*MAX_PROCESS_CORE_NUMBER)
  465. #define PROCESS_MAX_JPEG_SIZE (2147483648) //32768*32768*2
  466. #define PROCESS_MAX_SUM_OF_IMAGE_SIZE (PROCESS_MAX_VIDEO_SIZE>PROCESS_MAX_JPEG_SIZE?PROCESS_MAX_VIDEO_SIZE:PROCESS_MAX_JPEG_SIZE)
  467. #define MAX_SAME_MODULE_TYPE_CORE_NUMBER 4
  468. /*******************PCIE CONFIG*************************/
  469. /*******************PCIE CONFIG*************************/
  470. #define PCI_VENDOR_ID_HANTRO 0x10ee//0x16c3
  471. #define PCI_DEVICE_ID_HANTRO_PCI 0x8014// 0x7011
  472. /* Base address got control register */
  473. #define PCI_H2_BAR 4
  474. /* Base address DDR register */
  475. #define PCI_DDR_BAR 0
  476. static size_t base_ddr_addr = 0; /*pcie address need to substract this value then can be put to register*/
  477. /********variables declaration related with race condition**********/
  478. #define CMDBUF_MAX_SIZE (512*4*4)
  479. #define CMDBUF_POOL_TOTAL_SIZE (2*1024*1024) //approximately=128x(320x240)=128x2k=128x8kbyte=1Mbytes
  480. #define TOTAL_DISCRETE_CMDBUF_NUM (CMDBUF_POOL_TOTAL_SIZE/CMDBUF_MAX_SIZE)
  481. #define CMDBUF_VCMD_REGISTER_TOTAL_SIZE 9*1024*1024-CMDBUF_POOL_TOTAL_SIZE*2
  482. #define VCMD_REGISTER_SIZE (128*4)
  483. #ifndef DYNAMIC_MALLOC_VCMDNODE
  484. static struct cmdbuf_obj *g_cmdbuf_obj_pool;
  485. static struct bi_list_node *g_cmdbuf_node_pool;
  486. #endif
  487. struct noncache_mem
  488. {
  489. u32 *virtualAddress;
  490. dma_addr_t busAddress;
  491. unsigned int mmu_bus_address; /* buffer physical address in MMU*/
  492. u32 size;
  493. u16 cmdbuf_id;
  494. };
  495. struct process_manager_obj
  496. {
  497. struct file *filp;
  498. u64 total_exe_time;
  499. spinlock_t spinlock;
  500. u32 pm_count;
  501. wait_queue_head_t wait_queue;
  502. } ;
  503. struct cmdbuf_obj
  504. {
  505. u32 module_type; //current CMDBUF type: input vc8000e=0,IM=1,vc8000d=2,jpege=3, jpegd=4
  506. u32 priority; //current CMDBUFpriority: normal=0, high=1
  507. u64 executing_time; //current CMDBUFexecuting_time=encoded_image_size*(rdoLevel+1)*(rdoq+1);
  508. u32 cmdbuf_size; //current CMDBUF size
  509. u32 *cmdbuf_virtualAddress; //current CMDBUF start virtual address.
  510. size_t cmdbuf_busAddress; //current CMDBUF start physical address.
  511. unsigned int mmu_cmdbuf_busAddress; //current CMDBUF start mmu mapping address.
  512. u32 *status_virtualAddress; //current status CMDBUF start virtual address.
  513. size_t status_busAddress; //current status CMDBUF start physical address.
  514. unsigned int mmu_status_busAddress; //current status CMDBUF start mmu mapping address.
  515. u32 status_size; //current status CMDBUF size
  516. u32 executing_status; //current CMDBUF executing status.
  517. struct file *filp; //file pointer in the same process.
  518. u16 core_id; //which vcmd core is used.
  519. u16 cmdbuf_id; //used to manage CMDBUF in driver.It is a handle to identify cmdbuf.also is an interrupt vector.position in pool,same as status position.
  520. u8 cmdbuf_data_loaded; //0 means sw has not copied data into this CMDBUF; 1 means sw has copied data into this CMDBUF
  521. u8 cmdbuf_data_linked; //0 :not linked, 1:linked.
  522. u8 cmdbuf_run_done; //if 0,waiting for CMDBUF finish; if 1, op code in CMDBUF has finished one by one. HANTRO_VCMD_IOCH_WAIT_CMDBUF will check this variable.
  523. u8 cmdbuf_need_remove; // if 0, not need to remove CMDBUF; 1 CMDBUF can be removed if it is not the last CMDBUF;
  524. u32 waited; // if 0, the cmd buf hasn't been waited, otherwise, has been waited.
  525. u8 has_end_cmdbuf; //if 1, the last opcode is end opCode.
  526. u8 no_normal_int_cmdbuf; //if 1, JMP will not send normal interrupt.
  527. struct process_manager_obj* process_manager_obj;
  528. };
  529. struct hantrovcmd_dev
  530. {
  531. struct vcmd_config vcmd_core_cfg; //config of each core,such as base addr, irq,etc
  532. u32 core_id; //vcmd core id for driver and sw internal use
  533. u32 sw_cmdbuf_rdy_num;
  534. spinlock_t* spinlock;
  535. wait_queue_head_t * wait_queue;
  536. wait_queue_head_t * wait_abort_queue;
  537. bi_list list_manager;
  538. volatile u8 *hwregs;/* IO mem base */
  539. u32 reg_mirror[ASIC_VCMD_SWREG_AMOUNT];
  540. u32 duration_without_int; //number of cmdbufs without interrupt.
  541. volatile u8 working_state;
  542. u64 total_exe_time;
  543. u16 status_cmdbuf_id;//used for analyse configuration in cwl.
  544. u32 hw_version_id; /*megvii 0x43421001, later 0x43421102*/
  545. u32 *vcmd_reg_mem_virtualAddress;//start virtual address of vcmd registers memory of CMDBUF.
  546. size_t vcmd_reg_mem_busAddress; //start physical address of vcmd registers memory of CMDBUF.
  547. unsigned int mmu_vcmd_reg_mem_busAddress; //start mmu mapping address of vcmd registers memory of CMDBUF.
  548. u32 vcmd_reg_mem_size; // size of vcmd registers memory of CMDBUF.
  549. struct platform_device *pdev;
  550. } ;
  551. /*
  552. * Ioctl definitions
  553. */
  554. #define VCMD_HW_ID 0x4342
  555. static struct noncache_mem vcmd_buf_mem_pool;
  556. static struct noncache_mem vcmd_status_buf_mem_pool;
  557. static struct noncache_mem vcmd_registers_mem_pool;
  558. static u16 cmdbuf_used[TOTAL_DISCRETE_CMDBUF_NUM];
  559. static u16 cmdbuf_used_pos;
  560. static u16 cmdbuf_used_residual;
  561. static struct hantrovcmd_dev* vcmd_manager[MAX_VCMD_TYPE][MAX_VCMD_NUMBER];
  562. bi_list_node* global_cmdbuf_node[TOTAL_DISCRETE_CMDBUF_NUM];
  563. bi_list global_process_manager;
  564. static u16 vcmd_position[MAX_VCMD_TYPE];
  565. static int vcmd_type_core_num[MAX_VCMD_TYPE];
  566. #define EXECUTING_CMDBUF_ID_ADDR 26
  567. #define VCMD_EXE_CMDBUF_COUNT 3
  568. #define WORKING_STATE_IDLE 0
  569. #define WORKING_STATE_WORKING 1
  570. #define CMDBUF_EXE_STATUS_OK 0
  571. #define CMDBUF_EXE_STATUS_CMDERR 1
  572. #define CMDBUF_EXE_STATUS_BUSERR 2
  573. struct semaphore vcmd_reserve_cmdbuf_sem[MAX_VCMD_TYPE]; //for reserve
  574. extern unsigned long gBaseDDRHw; /* PCI base register address (memalloc) */
  575. extern unsigned int mmu_enable;
  576. /***************************TYPE AND FUNCTION DECLARATION****************/
  577. /* here's all the must remember stuff */
  578. static int vcmd_reserve_IO(void);
  579. static void vcmd_release_IO(void);
  580. static void vcmd_reset_asic(struct hantrovcmd_dev * dev);
  581. static void vcmd_reset_current_asic(struct hantrovcmd_dev * dev);
  582. static int allocate_cmdbuf(struct noncache_mem* new_cmdbuf_addr,struct noncache_mem* new_status_cmdbuf_addr);
  583. static void vcmd_link_cmdbuf(struct hantrovcmd_dev *dev,bi_list_node* last_linked_cmdbuf_node);
  584. static void vcmd_start(struct hantrovcmd_dev *dev,bi_list_node* first_linked_cmdbuf_node);
  585. static void create_kernel_process_manager(void);
  586. #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18))
  587. static irqreturn_t hantrovcmd_isr(int irq, void *dev_id, struct pt_regs *regs);
  588. #else
  589. static irqreturn_t hantrovcmd_isr(int irq, void *dev_id);
  590. #endif
  591. static void printk_vcmd_register_debug(const void *hwregs, char * info);
  592. /*********************local variable declaration*****************/
  593. /* and this is our MAJOR; use 0 for dynamic allocation (recommended)*/
  594. int total_vcmd_core_num = 0;
  595. /* dynamic allocation*/
  596. static struct hantrovcmd_dev* hantrovcmd_data = NULL;
  597. //#define VCMD_DEBUG_INTERNAL
  598. //#define IRQ_SIMULATION
  599. #ifdef IRQ_SIMULATION
  600. struct timer_manager
  601. {
  602. u32 core_id; //vcmd core id for driver and sw internal use
  603. u32 timer_id;
  604. struct timer_list *timer;
  605. } ;
  606. static struct timer_list timer[10000];
  607. struct timer_manager timer_reserve[10000];
  608. #if 0
  609. static struct timer_list timer0;
  610. static struct timer_list timer1;
  611. #endif
  612. #endif
  613. //hw_queue can be used for reserve cmdbuf memory
  614. DECLARE_WAIT_QUEUE_HEAD(vcmd_cmdbuf_memory_wait);
  615. DEFINE_SPINLOCK(vcmd_cmdbuf_alloc_lock);
  616. DEFINE_SPINLOCK(vcmd_process_manager_lock);
  617. spinlock_t owner_lock_vcmd[MAX_VCMD_NUMBER];
  618. wait_queue_head_t wait_queue_vcmd[MAX_VCMD_NUMBER];
  619. wait_queue_head_t abort_queue_vcmd[MAX_VCMD_NUMBER];
  620. /* mc wait queue, used in wait_cmdbuf_ready with ANY_CMDBUF_ID. */
  621. static wait_queue_head_t mc_wait_queue;
  622. #if 0
  623. /*allocate non-cacheable DMA memory*/
  624. #define DRIVER_NAME_HANTRO_NON_CACH_MEM "non_cach_memory"
  625. static struct platform_device *noncachable_mem_dev = NULL;
  626. static const struct platform_device_info hantro_platform_info = {
  627. .name = DRIVER_NAME_HANTRO_NON_CACH_MEM,
  628. .id = -1,
  629. .dma_mask = DMA_BIT_MASK(32),
  630. };
  631. static int hantro_noncachable_mem_probe(struct platform_device *pdev)
  632. {
  633. struct device *dev = &pdev->dev;
  634. vcmd_buf_mem_pool.virtualAddress = dma_alloc_coherent(dev,CMDBUF_POOL_TOTAL_SIZE,&vcmd_buf_mem_pool.busAddress, GFP_KERNEL | GFP_DMA);
  635. vcmd_buf_mem_pool.size = CMDBUF_POOL_TOTAL_SIZE;
  636. vcmd_status_buf_mem_pool.virtualAddress = dma_alloc_coherent(dev,CMDBUF_POOL_TOTAL_SIZE,&vcmd_status_buf_mem_pool.busAddress, GFP_KERNEL | GFP_DMA);
  637. vcmd_status_buf_mem_pool.size = CMDBUF_POOL_TOTAL_SIZE;
  638. return 0;
  639. }
  640. static int hantro_noncachable_mem_remove(struct platform_device *pdev)
  641. {
  642. struct device *dev = &pdev->dev;
  643. dma_free_coherent(dev,vcmd_buf_mem_pool.size,vcmd_buf_mem_pool.virtualAddress,vcmd_buf_mem_pool.busAddress);
  644. dma_free_coherent(dev,vcmd_status_buf_mem_pool.size,vcmd_status_buf_mem_pool.virtualAddress,vcmd_status_buf_mem_pool.busAddress);
  645. return 0;
  646. }
  647. static const struct platform_device_id hantro_noncachable_mem_platform_ids[]={
  648. {
  649. .name = DRIVER_NAME_HANTRO_NON_CACH_MEM,
  650. },
  651. {/* sentinel */},
  652. };
  653. static const struct of_device_id hantro_of_match[]={
  654. {
  655. .compatible = "thead,light-vc8000d",
  656. },
  657. {/* sentinel */},
  658. };
  659. static struct platform_driver hantro_noncachable_mem_platform_driver = {
  660. .probe = hantro_noncachable_mem_probe,
  661. .remove = hantro_noncachable_mem_remove,
  662. .driver ={
  663. .name = DRIVER_NAME_HANTRO_NON_CACH_MEM,
  664. .owner = THIS_MODULE,
  665. .of_match_table = hantro_of_match,
  666. },
  667. .id_table = hantro_noncachable_mem_platform_ids,
  668. };
  669. static void init_vcmd_non_cachable_memory_allocate(void)
  670. {
  671. /*create device: This will create a {struct platform_device}, It has a member dev, which is a {struct device} */
  672. noncachable_mem_dev = platform_device_register_full(&hantro_platform_info);
  673. /*when this function is called, the .probe callback is invoked.*/
  674. platform_driver_register(&hantro_noncachable_mem_platform_driver);
  675. }
  676. static void release_vcmd_non_cachable_memory(void)
  677. {
  678. /* when this fucntion is called, .remove callback will be invoked. use it to clean up all resources allocated in .probe.*/
  679. platform_driver_unregister(&hantro_noncachable_mem_platform_driver);
  680. /*destroy the device*/
  681. platform_device_unregister(noncachable_mem_dev);
  682. }
  683. #endif
  684. void PrintInstr(u32 i, u32 instr, u32 *size) {
  685. if ((instr & 0xF8000000) == OPCODE_WREG) {
  686. int length = ((instr >> 16) & 0x3FF);
  687. pr_info("current cmdbuf data %d = 0x%08x => [%s %s %d 0x%x]\n", i, instr, "WREG", ((instr >> 26) & 0x1) ? "FIX" : "",
  688. length, (instr & 0xFFFF));
  689. *size = ((length+2)>>1)<<1;
  690. } else if ((instr & 0xF8000000) == OPCODE_END) {
  691. pr_info("current cmdbuf data %d = 0x%08x => [%s]\n", i, instr, "END");
  692. *size = 2;
  693. } else if ((instr & 0xF8000000) == OPCODE_NOP) {
  694. pr_info("current cmdbuf data %d = 0x%08x => [%s]\n", i, instr, "NOP");
  695. *size = 2;
  696. } else if ((instr & 0xF8000000) == OPCODE_RREG) {
  697. int length = ((instr >> 16) & 0x3FF);
  698. pr_info("current cmdbuf data %d = 0x%08x => [%s %s %d 0x%x]\n", i, instr, "RREG", ((instr >> 26) & 0x1) ? "FIX" : "",
  699. length, (instr & 0xFFFF));
  700. *size = 4;
  701. } else if ((instr & 0xF8000000) == OPCODE_JMP) {
  702. pr_info("current cmdbuf data %d = 0x%08x => [%s %s %s]\n", i, instr, "JMP", ((instr >> 26) & 0x1) ? "RDY" : "",
  703. ((instr >> 25) & 0x1) ? "IE" : "");
  704. *size = 4;
  705. } else if ((instr & 0xF8000000) == OPCODE_STALL) {
  706. pr_info("current cmdbuf data %d = 0x%08x => [%s %s 0x%x]\n", i, instr, "STALL", ((instr >> 26) & 0x1) ? "IM" : "",
  707. (instr & 0xFFFF));
  708. *size = 2;
  709. } else if ((instr & 0xF8000000) == OPCODE_CLRINT) {
  710. pr_info("current cmdbuf data %d = 0x%08x => [%s %d 0x%x]\n", i, instr, "CLRINT", (instr >> 25) & 0x3,
  711. (instr & 0xFFFF));
  712. *size = 2;
  713. } else
  714. *size = 1;
  715. }
  716. /**********************************************************************************************************\
  717. *cmdbuf object management
  718. \***********************************************************************************************************/
  719. #ifdef DYNAMIC_MALLOC_VCMDNODE
  720. static struct cmdbuf_obj* create_cmdbuf_obj(void)
  721. {
  722. struct cmdbuf_obj* cmdbuf_obj=NULL;
  723. cmdbuf_obj=vmalloc(sizeof(struct cmdbuf_obj));
  724. if(cmdbuf_obj==NULL)
  725. {
  726. PDEBUG ("%s\n","vmalloc for cmdbuf_obj fail!");
  727. return cmdbuf_obj;
  728. }
  729. memset(cmdbuf_obj,0,sizeof(struct cmdbuf_obj));
  730. return cmdbuf_obj;
  731. }
  732. #endif
  733. #ifdef DYNAMIC_MALLOC_VCMDNODE
  734. static void free_cmdbuf_obj(struct cmdbuf_obj* cmdbuf_obj)
  735. {
  736. if(cmdbuf_obj==NULL)
  737. {
  738. PDEBUG ("%s\n","remove_cmdbuf_obj NULL");
  739. return;
  740. }
  741. //free current cmdbuf_obj
  742. vfree(cmdbuf_obj);
  743. return;
  744. }
  745. #endif
  746. static void free_cmdbuf_mem(u16 cmdbuf_id )
  747. {
  748. unsigned long flags;
  749. spin_lock_irqsave(&vcmd_cmdbuf_alloc_lock, flags);
  750. cmdbuf_used[cmdbuf_id]=0;
  751. cmdbuf_used_residual +=1;
  752. spin_unlock_irqrestore(&vcmd_cmdbuf_alloc_lock, flags);
  753. wake_up_interruptible_all(&vcmd_cmdbuf_memory_wait);
  754. }
  755. static bi_list_node* create_cmdbuf_node(void)
  756. {
  757. bi_list_node* current_node=NULL;
  758. struct cmdbuf_obj* cmdbuf_obj=NULL;
  759. struct noncache_mem new_cmdbuf_addr;
  760. struct noncache_mem new_status_cmdbuf_addr;
  761. if(wait_event_interruptible(vcmd_cmdbuf_memory_wait, allocate_cmdbuf(&new_cmdbuf_addr,&new_status_cmdbuf_addr)) )
  762. return NULL;
  763. #ifdef DYNAMIC_MALLOC_VCMDNODE
  764. cmdbuf_obj=create_cmdbuf_obj();
  765. #else
  766. cmdbuf_obj = g_cmdbuf_obj_pool + new_cmdbuf_addr.cmdbuf_id;
  767. if (cmdbuf_obj)
  768. memset(cmdbuf_obj, 0, sizeof(struct cmdbuf_obj));
  769. #endif
  770. if(cmdbuf_obj==NULL)
  771. {
  772. PDEBUG ("%s\n","create_cmdbuf_obj fail!");
  773. free_cmdbuf_mem(new_cmdbuf_addr.cmdbuf_id);
  774. return NULL;
  775. }
  776. cmdbuf_obj->cmdbuf_busAddress = new_cmdbuf_addr.busAddress;
  777. cmdbuf_obj->mmu_cmdbuf_busAddress = new_cmdbuf_addr.mmu_bus_address;
  778. cmdbuf_obj->cmdbuf_virtualAddress = new_cmdbuf_addr.virtualAddress;
  779. cmdbuf_obj->cmdbuf_size = new_cmdbuf_addr.size;
  780. cmdbuf_obj->cmdbuf_id = new_cmdbuf_addr.cmdbuf_id;
  781. cmdbuf_obj->status_busAddress = new_status_cmdbuf_addr.busAddress;
  782. cmdbuf_obj->mmu_status_busAddress = new_status_cmdbuf_addr.mmu_bus_address;
  783. cmdbuf_obj->status_virtualAddress = new_status_cmdbuf_addr.virtualAddress;
  784. cmdbuf_obj->status_size = new_status_cmdbuf_addr.size;
  785. #ifdef DYNAMIC_MALLOC_VCMDNODE
  786. current_node=bi_list_create_node();
  787. #else
  788. current_node = g_cmdbuf_node_pool + cmdbuf_obj->cmdbuf_id;
  789. if (current_node)
  790. memset(current_node, 0, sizeof(bi_list_node));
  791. #endif
  792. if(current_node==NULL)
  793. {
  794. PDEBUG ("%s\n","bi_list_create_node fail!");
  795. free_cmdbuf_mem(new_cmdbuf_addr.cmdbuf_id);
  796. #ifdef DYNAMIC_MALLOC_VCMDNODE
  797. free_cmdbuf_obj(cmdbuf_obj);
  798. #endif
  799. return NULL;
  800. }
  801. current_node->data = (void*)cmdbuf_obj;
  802. current_node->next = NULL;
  803. current_node->previous = NULL;
  804. return current_node;
  805. }
  806. static void free_cmdbuf_node(bi_list_node* cmdbuf_node)
  807. {
  808. struct cmdbuf_obj* cmdbuf_obj=NULL;
  809. if(cmdbuf_node==NULL)
  810. {
  811. PDEBUG ("%s\n","remove_cmdbuf_node NULL");
  812. return;
  813. }
  814. cmdbuf_obj = (struct cmdbuf_obj*)cmdbuf_node->data;
  815. //free cmdbuf mem in pool
  816. free_cmdbuf_mem(cmdbuf_obj->cmdbuf_id);
  817. #ifdef DYNAMIC_MALLOC_VCMDNODE
  818. //free struct cmdbuf_obj
  819. free_cmdbuf_obj(cmdbuf_obj);
  820. //free current cmdbuf_node entity.
  821. bi_list_free_node(cmdbuf_node);
  822. #endif
  823. return;
  824. }
  825. //just remove, not free the node.
  826. static bi_list_node* remove_cmdbuf_node_from_list(bi_list* list,bi_list_node* cmdbuf_node)
  827. {
  828. if(cmdbuf_node==NULL)
  829. {
  830. PDEBUG ("%s\n","remove_cmdbuf_node_from_list NULL");
  831. return NULL;
  832. }
  833. if(cmdbuf_node->next)
  834. {
  835. bi_list_remove_node(list,cmdbuf_node);
  836. return cmdbuf_node;
  837. }
  838. else
  839. {
  840. //the last one, should not be removed.
  841. return NULL;
  842. }
  843. }
  844. //calculate executing_time of each vcmd
  845. static u64 calculate_executing_time_after_node(bi_list_node* exe_cmdbuf_node)
  846. {
  847. u64 time_run_all=0;
  848. struct cmdbuf_obj* cmdbuf_obj_temp=NULL;
  849. while(1)
  850. {
  851. if(exe_cmdbuf_node==NULL)
  852. break;
  853. cmdbuf_obj_temp=(struct cmdbuf_obj* )exe_cmdbuf_node->data;
  854. time_run_all += cmdbuf_obj_temp->executing_time;
  855. exe_cmdbuf_node = exe_cmdbuf_node->next;
  856. }
  857. return time_run_all;
  858. }
  859. static u64 calculate_executing_time_after_node_high_priority(bi_list_node* exe_cmdbuf_node)
  860. {
  861. u64 time_run_all=0;
  862. struct cmdbuf_obj* cmdbuf_obj_temp=NULL;
  863. if(exe_cmdbuf_node==NULL)
  864. return time_run_all;
  865. cmdbuf_obj_temp=(struct cmdbuf_obj* )exe_cmdbuf_node->data;
  866. time_run_all += cmdbuf_obj_temp->executing_time;
  867. exe_cmdbuf_node = exe_cmdbuf_node->next;
  868. while(1)
  869. {
  870. if(exe_cmdbuf_node==NULL)
  871. break;
  872. cmdbuf_obj_temp=(struct cmdbuf_obj* )exe_cmdbuf_node->data;
  873. if(cmdbuf_obj_temp->priority==CMDBUF_PRIORITY_NORMAL)
  874. break;
  875. time_run_all += cmdbuf_obj_temp->executing_time;
  876. exe_cmdbuf_node = exe_cmdbuf_node->next;
  877. }
  878. return time_run_all;
  879. }
  880. /**********************************************************************************************************\
  881. *cmdbuf pool management
  882. \***********************************************************************************************************/
  883. static int allocate_cmdbuf(struct noncache_mem* new_cmdbuf_addr,struct noncache_mem* new_status_cmdbuf_addr)
  884. {
  885. unsigned long flags;
  886. spin_lock_irqsave(&vcmd_cmdbuf_alloc_lock, flags);
  887. if(cmdbuf_used_residual==0)
  888. {
  889. spin_unlock_irqrestore(&vcmd_cmdbuf_alloc_lock, flags);
  890. //no empty cmdbuf
  891. return 0;
  892. }
  893. //there is one cmdbuf at least
  894. while(1)
  895. {
  896. if(cmdbuf_used[cmdbuf_used_pos]==0&&(global_cmdbuf_node[cmdbuf_used_pos]==NULL ))
  897. {
  898. cmdbuf_used[cmdbuf_used_pos]=1;
  899. cmdbuf_used_residual -=1;
  900. new_cmdbuf_addr->virtualAddress=vcmd_buf_mem_pool.virtualAddress + cmdbuf_used_pos*CMDBUF_MAX_SIZE/4;
  901. new_cmdbuf_addr->busAddress=vcmd_buf_mem_pool.busAddress + cmdbuf_used_pos*CMDBUF_MAX_SIZE;
  902. new_cmdbuf_addr->mmu_bus_address=vcmd_buf_mem_pool.mmu_bus_address + cmdbuf_used_pos*CMDBUF_MAX_SIZE;
  903. new_cmdbuf_addr->size=CMDBUF_MAX_SIZE;
  904. new_cmdbuf_addr->cmdbuf_id = cmdbuf_used_pos;
  905. new_status_cmdbuf_addr->virtualAddress=vcmd_status_buf_mem_pool.virtualAddress + cmdbuf_used_pos*CMDBUF_MAX_SIZE/4;
  906. new_status_cmdbuf_addr->busAddress=vcmd_status_buf_mem_pool.busAddress + cmdbuf_used_pos*CMDBUF_MAX_SIZE;
  907. new_status_cmdbuf_addr->mmu_bus_address=vcmd_status_buf_mem_pool.mmu_bus_address + cmdbuf_used_pos*CMDBUF_MAX_SIZE;
  908. new_status_cmdbuf_addr->size=CMDBUF_MAX_SIZE;
  909. new_status_cmdbuf_addr->cmdbuf_id = cmdbuf_used_pos;
  910. cmdbuf_used_pos++;
  911. if(cmdbuf_used_pos>=TOTAL_DISCRETE_CMDBUF_NUM)
  912. cmdbuf_used_pos=0;
  913. spin_unlock_irqrestore(&vcmd_cmdbuf_alloc_lock, flags);
  914. return 1;
  915. }
  916. else
  917. {
  918. cmdbuf_used_pos++;
  919. if(cmdbuf_used_pos>=TOTAL_DISCRETE_CMDBUF_NUM)
  920. cmdbuf_used_pos=0;
  921. }
  922. }
  923. return 0;
  924. }
  925. static bi_list_node* get_cmdbuf_node_in_list_by_addr(size_t cmdbuf_addr,bi_list* list)
  926. {
  927. bi_list_node* new_cmdbuf_node=NULL;
  928. struct cmdbuf_obj* cmdbuf_obj=NULL;
  929. new_cmdbuf_node=list->head;
  930. while(1)
  931. {
  932. if(new_cmdbuf_node==NULL)
  933. return NULL;
  934. cmdbuf_obj=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  935. if(((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr) <=cmdbuf_addr)&&(((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr+cmdbuf_obj->cmdbuf_size) >cmdbuf_addr)) )
  936. {
  937. return new_cmdbuf_node;
  938. }
  939. new_cmdbuf_node=new_cmdbuf_node->next;
  940. }
  941. return NULL;
  942. }
  943. static int wait_abort_rdy(struct hantrovcmd_dev*dev)
  944. {
  945. return dev->working_state == WORKING_STATE_IDLE;
  946. }
  947. static int select_vcmd(bi_list_node* new_cmdbuf_node)
  948. {
  949. struct cmdbuf_obj* cmdbuf_obj=NULL;
  950. bi_list_node* curr_cmdbuf_node=NULL;
  951. bi_list* list=NULL;
  952. struct hantrovcmd_dev*dev=NULL;
  953. struct hantrovcmd_dev*smallest_dev=NULL;
  954. u64 executing_time=0xffffffffffffffff;
  955. int counter=0;
  956. unsigned long flags=0;
  957. u32 hw_rdy_cmdbuf_num=0;
  958. size_t exe_cmdbuf_addr=0;
  959. struct cmdbuf_obj* cmdbuf_obj_temp=NULL;
  960. u32 cmdbuf_id=0;
  961. cmdbuf_obj=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  962. //there is an empty vcmd to be used
  963. while(1)
  964. {
  965. dev = vcmd_manager[cmdbuf_obj->module_type][vcmd_position[cmdbuf_obj->module_type]];
  966. list=&dev->list_manager;
  967. spin_lock_irqsave(dev->spinlock, flags);
  968. if( list->tail==NULL)
  969. {
  970. bi_list_insert_node_tail(list,new_cmdbuf_node);
  971. spin_unlock_irqrestore(dev->spinlock, flags);
  972. vcmd_position[cmdbuf_obj->module_type]++;
  973. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  974. vcmd_position[cmdbuf_obj->module_type]=0;
  975. cmdbuf_obj->core_id = dev->core_id;
  976. return 0;
  977. }
  978. else
  979. {
  980. spin_unlock_irqrestore(dev->spinlock, flags);
  981. vcmd_position[cmdbuf_obj->module_type]++;
  982. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  983. vcmd_position[cmdbuf_obj->module_type]=0;
  984. counter++;
  985. }
  986. if(counter>=vcmd_type_core_num[cmdbuf_obj->module_type])
  987. break;
  988. }
  989. //there is a vcmd which tail node -> cmdbuf_run_done == 1. It means this vcmd has nothing to do, so we select it.
  990. counter =0;
  991. while(1)
  992. {
  993. dev = vcmd_manager[cmdbuf_obj->module_type][vcmd_position[cmdbuf_obj->module_type]];
  994. list=&dev->list_manager;
  995. spin_lock_irqsave(dev->spinlock, flags);
  996. curr_cmdbuf_node = list->tail;
  997. if(curr_cmdbuf_node == NULL)
  998. {
  999. bi_list_insert_node_tail(list,new_cmdbuf_node);
  1000. spin_unlock_irqrestore(dev->spinlock, flags);
  1001. vcmd_position[cmdbuf_obj->module_type]++;
  1002. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1003. vcmd_position[cmdbuf_obj->module_type]=0;
  1004. cmdbuf_obj->core_id = dev->core_id;
  1005. return 0;
  1006. }
  1007. cmdbuf_obj_temp =(struct cmdbuf_obj*) curr_cmdbuf_node->data;
  1008. if(cmdbuf_obj_temp->cmdbuf_run_done ==1)
  1009. {
  1010. bi_list_insert_node_tail(list,new_cmdbuf_node);
  1011. spin_unlock_irqrestore(dev->spinlock, flags);
  1012. vcmd_position[cmdbuf_obj->module_type]++;
  1013. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1014. vcmd_position[cmdbuf_obj->module_type]=0;
  1015. cmdbuf_obj->core_id = dev->core_id;
  1016. return 0;
  1017. }
  1018. else
  1019. {
  1020. spin_unlock_irqrestore(dev->spinlock, flags);
  1021. vcmd_position[cmdbuf_obj->module_type]++;
  1022. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1023. vcmd_position[cmdbuf_obj->module_type]=0;
  1024. counter++;
  1025. }
  1026. if(counter>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1027. break;
  1028. }
  1029. //another case, tail = executing node, and vcmd=pend state (finish but not generate interrupt)
  1030. counter =0;
  1031. while(1)
  1032. {
  1033. dev = vcmd_manager[cmdbuf_obj->module_type][vcmd_position[cmdbuf_obj->module_type]];
  1034. list=&dev->list_manager;
  1035. //read executing cmdbuf address
  1036. if(dev->hw_version_id <= HW_ID_1_0_C )
  1037. hw_rdy_cmdbuf_num = vcmd_get_register_value((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_EXE_CMDBUF_COUNT);
  1038. else
  1039. {
  1040. hw_rdy_cmdbuf_num = *(dev->vcmd_reg_mem_virtualAddress+VCMD_EXE_CMDBUF_COUNT);
  1041. if(hw_rdy_cmdbuf_num!=dev->sw_cmdbuf_rdy_num)
  1042. hw_rdy_cmdbuf_num += 1;
  1043. }
  1044. spin_lock_irqsave(dev->spinlock, flags);
  1045. curr_cmdbuf_node = list->tail;
  1046. if(curr_cmdbuf_node == NULL)
  1047. {
  1048. bi_list_insert_node_tail(list,new_cmdbuf_node);
  1049. spin_unlock_irqrestore(dev->spinlock, flags);
  1050. vcmd_position[cmdbuf_obj->module_type]++;
  1051. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1052. vcmd_position[cmdbuf_obj->module_type]=0;
  1053. cmdbuf_obj->core_id = dev->core_id;
  1054. return 0;
  1055. }
  1056. if((dev->sw_cmdbuf_rdy_num ==hw_rdy_cmdbuf_num))
  1057. {
  1058. bi_list_insert_node_tail(list,new_cmdbuf_node);
  1059. spin_unlock_irqrestore(dev->spinlock, flags);
  1060. vcmd_position[cmdbuf_obj->module_type]++;
  1061. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1062. vcmd_position[cmdbuf_obj->module_type]=0;
  1063. cmdbuf_obj->core_id = dev->core_id;
  1064. return 0;
  1065. }
  1066. else
  1067. {
  1068. spin_unlock_irqrestore(dev->spinlock, flags);
  1069. vcmd_position[cmdbuf_obj->module_type]++;
  1070. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1071. vcmd_position[cmdbuf_obj->module_type]=0;
  1072. counter++;
  1073. }
  1074. if(counter>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1075. break;
  1076. }
  1077. //there is no idle vcmd,if low priority,calculate exe time, select the least one.
  1078. // or if high priority, calculate the exe time, select the least one and abort it.
  1079. if(cmdbuf_obj->priority==CMDBUF_PRIORITY_NORMAL)
  1080. {
  1081. counter =0;
  1082. //calculate total execute time of all devices
  1083. while(1)
  1084. {
  1085. dev = vcmd_manager[cmdbuf_obj->module_type][vcmd_position[cmdbuf_obj->module_type]];
  1086. //read executing cmdbuf address
  1087. if(dev->hw_version_id <= HW_ID_1_0_C )
  1088. {
  1089. exe_cmdbuf_addr = VCMDGetAddrRegisterValue((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR);
  1090. list=&dev->list_manager;
  1091. spin_lock_irqsave(dev->spinlock, flags);
  1092. //get the executing cmdbuf node.
  1093. curr_cmdbuf_node=get_cmdbuf_node_in_list_by_addr(exe_cmdbuf_addr,list);
  1094. //calculate total execute time of this device
  1095. dev->total_exe_time=calculate_executing_time_after_node(curr_cmdbuf_node);
  1096. spin_unlock_irqrestore(dev->spinlock, flags);
  1097. }
  1098. else
  1099. {
  1100. //cmdbuf_id = vcmd_get_register_value((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_CMDBUF_EXECUTING_ID);
  1101. cmdbuf_id = *(dev->vcmd_reg_mem_virtualAddress+EXECUTING_CMDBUF_ID_ADDR+1);
  1102. spin_lock_irqsave(dev->spinlock, flags);
  1103. if(cmdbuf_id>=TOTAL_DISCRETE_CMDBUF_NUM||cmdbuf_id == 0)
  1104. {
  1105. pr_err("cmdbuf_id greater than the ceiling !!\n");
  1106. spin_unlock_irqrestore(dev->spinlock, flags);
  1107. return -1;
  1108. }
  1109. //get the executing cmdbuf node.
  1110. curr_cmdbuf_node=global_cmdbuf_node[cmdbuf_id];
  1111. if(curr_cmdbuf_node==NULL)
  1112. {
  1113. list=&dev->list_manager;
  1114. curr_cmdbuf_node = list->head;
  1115. while(1)
  1116. {
  1117. if(curr_cmdbuf_node == NULL)
  1118. break;
  1119. cmdbuf_obj_temp =(struct cmdbuf_obj*) curr_cmdbuf_node->data;
  1120. if(cmdbuf_obj_temp->cmdbuf_data_linked&&cmdbuf_obj_temp->cmdbuf_run_done==0)
  1121. break;
  1122. curr_cmdbuf_node = curr_cmdbuf_node->next;
  1123. }
  1124. }
  1125. //calculate total execute time of this device
  1126. dev->total_exe_time=calculate_executing_time_after_node(curr_cmdbuf_node);
  1127. spin_unlock_irqrestore(dev->spinlock, flags);
  1128. }
  1129. vcmd_position[cmdbuf_obj->module_type]++;
  1130. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1131. vcmd_position[cmdbuf_obj->module_type]=0;
  1132. counter++;
  1133. if(counter>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1134. break;
  1135. }
  1136. //find the device with the least total_exe_time.
  1137. counter =0;
  1138. executing_time=0xffffffffffffffff;
  1139. while(1)
  1140. {
  1141. dev = vcmd_manager[cmdbuf_obj->module_type][vcmd_position[cmdbuf_obj->module_type]];
  1142. if(dev->total_exe_time <= executing_time)
  1143. {
  1144. executing_time = dev->total_exe_time;
  1145. smallest_dev = dev;
  1146. }
  1147. vcmd_position[cmdbuf_obj->module_type]++;
  1148. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1149. vcmd_position[cmdbuf_obj->module_type]=0;
  1150. counter++;
  1151. if(counter>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1152. break;
  1153. }
  1154. //insert list
  1155. list = &smallest_dev->list_manager;
  1156. spin_lock_irqsave(smallest_dev->spinlock, flags);
  1157. bi_list_insert_node_tail(list,new_cmdbuf_node);
  1158. spin_unlock_irqrestore(smallest_dev->spinlock, flags);
  1159. cmdbuf_obj->core_id = smallest_dev->core_id;
  1160. return 0;
  1161. }
  1162. else
  1163. {
  1164. //CMDBUF_PRIORITY_HIGH
  1165. counter =0;
  1166. //calculate total execute time of all devices
  1167. while(1)
  1168. {
  1169. dev = vcmd_manager[cmdbuf_obj->module_type][vcmd_position[cmdbuf_obj->module_type]];
  1170. if(dev->hw_version_id <= HW_ID_1_0_C )
  1171. {
  1172. //read executing cmdbuf address
  1173. exe_cmdbuf_addr = VCMDGetAddrRegisterValue((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR);
  1174. list=&dev->list_manager;
  1175. spin_lock_irqsave(dev->spinlock, flags);
  1176. //get the executing cmdbuf node.
  1177. curr_cmdbuf_node=get_cmdbuf_node_in_list_by_addr(exe_cmdbuf_addr,list);
  1178. //calculate total execute time of this device
  1179. dev->total_exe_time=calculate_executing_time_after_node_high_priority(curr_cmdbuf_node);
  1180. spin_unlock_irqrestore(dev->spinlock, flags);
  1181. }
  1182. else
  1183. {
  1184. //cmdbuf_id = vcmd_get_register_value((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_CMDBUF_EXECUTING_ID);
  1185. cmdbuf_id = *(dev->vcmd_reg_mem_virtualAddress+EXECUTING_CMDBUF_ID_ADDR);
  1186. spin_lock_irqsave(dev->spinlock, flags);
  1187. if(cmdbuf_id>=TOTAL_DISCRETE_CMDBUF_NUM||cmdbuf_id == 0)
  1188. {
  1189. pr_err("cmdbuf_id greater than the ceiling !!\n");
  1190. spin_unlock_irqrestore(dev->spinlock, flags);
  1191. return -1;
  1192. }
  1193. //get the executing cmdbuf node.
  1194. curr_cmdbuf_node=global_cmdbuf_node[cmdbuf_id];
  1195. if(curr_cmdbuf_node==NULL)
  1196. {
  1197. list=&dev->list_manager;
  1198. curr_cmdbuf_node = list->head;
  1199. while(1)
  1200. {
  1201. if(curr_cmdbuf_node == NULL)
  1202. break;
  1203. cmdbuf_obj_temp =(struct cmdbuf_obj*) curr_cmdbuf_node->data;
  1204. if(cmdbuf_obj_temp->cmdbuf_data_linked&&cmdbuf_obj_temp->cmdbuf_run_done==0)
  1205. break;
  1206. curr_cmdbuf_node = curr_cmdbuf_node->next;
  1207. }
  1208. }
  1209. //calculate total execute time of this device
  1210. dev->total_exe_time=calculate_executing_time_after_node(curr_cmdbuf_node);
  1211. spin_unlock_irqrestore(dev->spinlock, flags);
  1212. }
  1213. vcmd_position[cmdbuf_obj->module_type]++;
  1214. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1215. vcmd_position[cmdbuf_obj->module_type]=0;
  1216. counter++;
  1217. if(counter>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1218. break;
  1219. }
  1220. //find the smallest device.
  1221. counter =0;
  1222. executing_time=0xffffffffffffffff;
  1223. while(1)
  1224. {
  1225. dev = vcmd_manager[cmdbuf_obj->module_type][vcmd_position[cmdbuf_obj->module_type]];
  1226. if(dev->total_exe_time <= executing_time)
  1227. {
  1228. executing_time = dev->total_exe_time;
  1229. smallest_dev = dev;
  1230. }
  1231. vcmd_position[cmdbuf_obj->module_type]++;
  1232. if(vcmd_position[cmdbuf_obj->module_type]>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1233. vcmd_position[cmdbuf_obj->module_type]=0;
  1234. counter++;
  1235. if(counter>=vcmd_type_core_num[cmdbuf_obj->module_type])
  1236. break;
  1237. }
  1238. //abort the vcmd and wait
  1239. vcmd_write_register_value((const void *)smallest_dev->hwregs,smallest_dev->reg_mirror,HWIF_VCMD_START_TRIGGER,0);
  1240. if(wait_event_interruptible(*smallest_dev->wait_abort_queue, wait_abort_rdy(smallest_dev)) )
  1241. return -ERESTARTSYS;
  1242. //need to select inserting position again because hw maybe have run to the next node.
  1243. //CMDBUF_PRIORITY_HIGH
  1244. spin_lock_irqsave(smallest_dev->spinlock, flags);
  1245. curr_cmdbuf_node = smallest_dev->list_manager.head;
  1246. while(1)
  1247. {
  1248. //if list is empty or tail,insert to tail
  1249. if(curr_cmdbuf_node == NULL)
  1250. break;
  1251. cmdbuf_obj_temp= (struct cmdbuf_obj*)curr_cmdbuf_node->data;
  1252. //if find the first node which priority is normal, insert node prior to the node
  1253. if((cmdbuf_obj_temp->priority==CMDBUF_PRIORITY_NORMAL) && (cmdbuf_obj_temp->cmdbuf_run_done==0))
  1254. break;
  1255. curr_cmdbuf_node = curr_cmdbuf_node->next;
  1256. }
  1257. bi_list_insert_node_before(list,curr_cmdbuf_node,new_cmdbuf_node);
  1258. cmdbuf_obj->core_id = smallest_dev->core_id;
  1259. spin_unlock_irqrestore(smallest_dev->spinlock, flags);
  1260. return 0;
  1261. }
  1262. return 0;
  1263. }
  1264. static int wait_process_resource_rdy(struct process_manager_obj* process_manager_obj )
  1265. {
  1266. return process_manager_obj->total_exe_time<=PROCESS_MAX_SUM_OF_IMAGE_SIZE;
  1267. }
  1268. static long reserve_cmdbuf(struct file *filp,struct exchange_parameter* input_para)
  1269. {
  1270. bi_list_node* new_cmdbuf_node=NULL;
  1271. struct cmdbuf_obj* cmdbuf_obj=NULL;
  1272. bi_list_node* process_manager_node=NULL;
  1273. struct process_manager_obj* process_manager_obj=NULL;
  1274. unsigned long flags;
  1275. input_para->cmdbuf_id = 0;
  1276. if(input_para->cmdbuf_size>CMDBUF_MAX_SIZE)
  1277. {
  1278. return -1;
  1279. }
  1280. PDEBUG("reserve cmdbuf filp %p\n", (void *)filp);
  1281. spin_lock_irqsave(&vcmd_process_manager_lock, flags);
  1282. process_manager_node = global_process_manager.head;
  1283. while(1)
  1284. {
  1285. if (process_manager_node == NULL)
  1286. {
  1287. //should not happen
  1288. pr_err("hantrovcmd: ERROR process_manager_node !!\n");
  1289. spin_unlock_irqrestore(&vcmd_process_manager_lock, flags);
  1290. return -1;
  1291. }
  1292. process_manager_obj = (struct process_manager_obj*)process_manager_node->data;
  1293. PDEBUG("reserve loop: node %p, filp %p\n", (void *)process_manager_node,
  1294. (void *)process_manager_obj->filp);
  1295. if (filp == process_manager_obj->filp)
  1296. break;
  1297. process_manager_node = process_manager_node->next;
  1298. }
  1299. spin_unlock_irqrestore(&vcmd_process_manager_lock, flags);
  1300. spin_lock_irqsave(&process_manager_obj->spinlock, flags);
  1301. process_manager_obj->total_exe_time += input_para->executing_time;
  1302. spin_unlock_irqrestore(&process_manager_obj->spinlock, flags);
  1303. if(wait_event_interruptible(process_manager_obj->wait_queue, wait_process_resource_rdy(process_manager_obj)))
  1304. return -1;
  1305. new_cmdbuf_node=create_cmdbuf_node();
  1306. if(new_cmdbuf_node==NULL)
  1307. return -1;
  1308. cmdbuf_obj = (struct cmdbuf_obj* )new_cmdbuf_node->data;
  1309. cmdbuf_obj->module_type = input_para->module_type;
  1310. cmdbuf_obj->priority = input_para->priority;
  1311. cmdbuf_obj->executing_time = input_para->executing_time;
  1312. cmdbuf_obj->cmdbuf_size = CMDBUF_MAX_SIZE;
  1313. input_para->cmdbuf_size =CMDBUF_MAX_SIZE;
  1314. cmdbuf_obj->filp = filp;
  1315. cmdbuf_obj->process_manager_obj =process_manager_obj;
  1316. input_para->cmdbuf_id=cmdbuf_obj->cmdbuf_id;
  1317. global_cmdbuf_node[input_para->cmdbuf_id] = new_cmdbuf_node;
  1318. return 0;
  1319. }
  1320. static long release_cmdbuf(struct file *filp,u16 cmdbuf_id)
  1321. {
  1322. struct cmdbuf_obj* cmdbuf_obj=NULL;
  1323. bi_list_node* last_cmdbuf_node=NULL;
  1324. bi_list_node* new_cmdbuf_node=NULL;
  1325. bi_list* list=NULL;
  1326. u32 module_type;
  1327. unsigned long flags;
  1328. struct hantrovcmd_dev* dev=NULL;
  1329. /*get cmdbuf object according to cmdbuf_id*/
  1330. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  1331. if(new_cmdbuf_node==NULL)
  1332. {
  1333. //should not happen
  1334. pr_err("hantrovcmd: ERROR cmdbuf_id !!\n");
  1335. return -1;
  1336. }
  1337. cmdbuf_obj=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  1338. if(cmdbuf_obj->filp!=filp)
  1339. {
  1340. //should not happen
  1341. pr_err("hantrovcmd: ERROR cmdbuf_id !!\n");
  1342. return -1;
  1343. }
  1344. module_type = cmdbuf_obj->module_type;
  1345. //TODO
  1346. if (down_interruptible(&vcmd_reserve_cmdbuf_sem[module_type]))
  1347. return -ERESTARTSYS;
  1348. dev = &hantrovcmd_data[cmdbuf_obj->core_id];
  1349. //spin_lock_irqsave(dev->spinlock, flags);
  1350. list=&dev->list_manager;
  1351. cmdbuf_obj->cmdbuf_need_remove=1;
  1352. last_cmdbuf_node = new_cmdbuf_node->previous;
  1353. while(1)
  1354. {
  1355. //remove current node
  1356. cmdbuf_obj=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  1357. if(cmdbuf_obj->cmdbuf_need_remove==1)
  1358. {
  1359. new_cmdbuf_node=remove_cmdbuf_node_from_list(list,new_cmdbuf_node);
  1360. if(new_cmdbuf_node)
  1361. {
  1362. //free node
  1363. global_cmdbuf_node[cmdbuf_obj->cmdbuf_id] = NULL;
  1364. if(cmdbuf_obj->process_manager_obj)
  1365. {
  1366. spin_lock_irqsave(&cmdbuf_obj->process_manager_obj->spinlock, flags);
  1367. cmdbuf_obj->process_manager_obj->total_exe_time -= cmdbuf_obj->executing_time;
  1368. spin_unlock_irqrestore(&cmdbuf_obj->process_manager_obj->spinlock, flags);
  1369. wake_up_interruptible_all(&cmdbuf_obj->process_manager_obj->wait_queue);
  1370. }
  1371. free_cmdbuf_node(new_cmdbuf_node);
  1372. }
  1373. }
  1374. if(last_cmdbuf_node==NULL)
  1375. break;
  1376. new_cmdbuf_node=last_cmdbuf_node;
  1377. last_cmdbuf_node=new_cmdbuf_node->previous;
  1378. }
  1379. //spin_unlock_irqrestore(dev->spinlock, flags);
  1380. up(&vcmd_reserve_cmdbuf_sem[module_type]);
  1381. return 0;
  1382. }
  1383. static long release_cmdbuf_node(bi_list* list,bi_list_node*cmdbuf_node)
  1384. {
  1385. bi_list_node* new_cmdbuf_node=NULL;
  1386. struct cmdbuf_obj* cmdbuf_obj=NULL;
  1387. /*get cmdbuf object according to cmdbuf_id*/
  1388. new_cmdbuf_node=cmdbuf_node;
  1389. if(new_cmdbuf_node==NULL)
  1390. return -1;
  1391. //remove node from list
  1392. new_cmdbuf_node=remove_cmdbuf_node_from_list(list,new_cmdbuf_node);
  1393. if(new_cmdbuf_node)
  1394. {
  1395. //free node
  1396. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  1397. global_cmdbuf_node[cmdbuf_obj->cmdbuf_id] = NULL;
  1398. free_cmdbuf_node(new_cmdbuf_node);
  1399. return 0;
  1400. }
  1401. return 1;
  1402. }
  1403. static long release_cmdbuf_node_cleanup(bi_list* list)
  1404. {
  1405. bi_list_node* new_cmdbuf_node=NULL;
  1406. struct cmdbuf_obj* cmdbuf_obj=NULL;
  1407. while(1)
  1408. {
  1409. new_cmdbuf_node=list->head;
  1410. if(new_cmdbuf_node==NULL)
  1411. return 0;
  1412. //remove node from list
  1413. bi_list_remove_node(list,new_cmdbuf_node);
  1414. //free node
  1415. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  1416. global_cmdbuf_node[cmdbuf_obj->cmdbuf_id] = NULL;
  1417. free_cmdbuf_node(new_cmdbuf_node);
  1418. }
  1419. return 0;
  1420. }
  1421. static bi_list_node* find_last_linked_cmdbuf(bi_list_node* current_node)
  1422. {
  1423. bi_list_node* new_cmdbuf_node=current_node;
  1424. bi_list_node* last_cmdbuf_node;
  1425. struct cmdbuf_obj* cmdbuf_obj=NULL;
  1426. if(current_node==NULL)
  1427. return NULL;
  1428. last_cmdbuf_node = new_cmdbuf_node;
  1429. new_cmdbuf_node = new_cmdbuf_node->previous;
  1430. while(1)
  1431. {
  1432. if(new_cmdbuf_node==NULL)
  1433. return last_cmdbuf_node;
  1434. cmdbuf_obj=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  1435. if(cmdbuf_obj->cmdbuf_data_linked)
  1436. {
  1437. return new_cmdbuf_node;
  1438. }
  1439. last_cmdbuf_node = new_cmdbuf_node;
  1440. new_cmdbuf_node = new_cmdbuf_node->previous;
  1441. }
  1442. return NULL;
  1443. }
  1444. static long link_and_run_cmdbuf(struct file *filp,struct exchange_parameter* input_para)
  1445. {
  1446. struct cmdbuf_obj* cmdbuf_obj=NULL;
  1447. bi_list_node* new_cmdbuf_node=NULL;
  1448. bi_list_node* last_cmdbuf_node;
  1449. u32* jmp_addr=NULL;
  1450. u32 opCode;
  1451. u32 tempOpcode;
  1452. u32 record_last_cmdbuf_rdy_num;
  1453. struct hantrovcmd_dev* dev=NULL;
  1454. unsigned long flags;
  1455. int return_value;
  1456. u16 cmdbuf_id=input_para->cmdbuf_id;
  1457. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  1458. if(new_cmdbuf_node==NULL)
  1459. {
  1460. //should not happen
  1461. pr_err("hantrovcmd: ERROR cmdbuf_id !!\n");
  1462. return -1;
  1463. }
  1464. cmdbuf_obj=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  1465. if(cmdbuf_obj->filp!=filp)
  1466. {
  1467. //should not happen
  1468. pr_err("hantrovcmd: ERROR cmdbuf_id !!\n");
  1469. return -1;
  1470. }
  1471. cmdbuf_obj->cmdbuf_data_loaded=1;
  1472. cmdbuf_obj->cmdbuf_size=input_para->cmdbuf_size;
  1473. cmdbuf_obj->waited = 0;
  1474. #ifdef VCMD_DEBUG_INTERNAL
  1475. {
  1476. u32 i, inst = 0, size = 0;
  1477. pr_info("vcmd link, current cmdbuf content\n");
  1478. for(i=0;i<cmdbuf_obj->cmdbuf_size/4;i++)
  1479. {
  1480. if (i == inst) {
  1481. PrintInstr(i, *(cmdbuf_obj->cmdbuf_virtualAddress+i), &size);
  1482. inst += size;
  1483. } else {
  1484. pr_info("current cmdbuf data %d = 0x%x\n",i,*(cmdbuf_obj->cmdbuf_virtualAddress+i));
  1485. }
  1486. }
  1487. }
  1488. #endif
  1489. //test nop and end opcode, then assign value.
  1490. cmdbuf_obj->has_end_cmdbuf=0; //0: has jmp opcode,1 has end code
  1491. cmdbuf_obj->no_normal_int_cmdbuf=0; //0: interrupt when JMP,1 not interrupt when JMP
  1492. jmp_addr = cmdbuf_obj->cmdbuf_virtualAddress + (cmdbuf_obj->cmdbuf_size/4);
  1493. opCode=tempOpcode = *(jmp_addr-4);
  1494. opCode >>=27;
  1495. opCode <<=27;
  1496. //we can't identify END opcode or JMP opcode, so we don't support END opcode in control sw and driver.
  1497. if(opCode == OPCODE_JMP)
  1498. {
  1499. //jmp
  1500. opCode=tempOpcode;
  1501. opCode &=0x02000000;
  1502. if(opCode == JMP_IE_1)
  1503. {
  1504. cmdbuf_obj->no_normal_int_cmdbuf=0;
  1505. }
  1506. else
  1507. {
  1508. cmdbuf_obj->no_normal_int_cmdbuf=1;
  1509. }
  1510. }
  1511. else
  1512. {
  1513. //not support other opcode
  1514. return -1;
  1515. }
  1516. if (down_interruptible(&vcmd_reserve_cmdbuf_sem[cmdbuf_obj->module_type]))
  1517. return -ERESTARTSYS;
  1518. return_value=select_vcmd(new_cmdbuf_node);
  1519. if(return_value)
  1520. return return_value;
  1521. dev = &hantrovcmd_data[cmdbuf_obj->core_id];
  1522. input_para->core_id = cmdbuf_obj->core_id;
  1523. pr_debug("filp=%p, VCMD Link CMDBUF [%d] to core [%d]\n", (void *)filp, cmdbuf_id, input_para->core_id);
  1524. //set ddr address for vcmd registers copy.
  1525. if(dev->hw_version_id > HW_ID_1_0_C )
  1526. {
  1527. //read vcmd executing register into ddr memory.
  1528. //now core id is got and output ddr address of vcmd register can be filled in.
  1529. //each core has its own fixed output ddr address of vcmd registers.
  1530. jmp_addr = cmdbuf_obj->cmdbuf_virtualAddress;
  1531. if (mmu_enable) {
  1532. *(jmp_addr + 2) = 0;
  1533. *(jmp_addr+1) = (u32)((dev->mmu_vcmd_reg_mem_busAddress + (EXECUTING_CMDBUF_ID_ADDR+1)*4));
  1534. } else {
  1535. if(sizeof(size_t) == 8) {
  1536. *(jmp_addr + 2) = (u32)((u64)(dev->vcmd_reg_mem_busAddress + (EXECUTING_CMDBUF_ID_ADDR+1)*4)>>32);
  1537. } else {
  1538. *(jmp_addr + 2) = 0;
  1539. }
  1540. *(jmp_addr+1) = (u32)((dev->vcmd_reg_mem_busAddress + (EXECUTING_CMDBUF_ID_ADDR+1)*4));
  1541. }
  1542. jmp_addr = cmdbuf_obj->cmdbuf_virtualAddress + (cmdbuf_obj->cmdbuf_size/4);
  1543. //read vcmd all registers into ddr memory.
  1544. //now core id is got and output ddr address of vcmd registers can be filled in.
  1545. //each core has its own fixed output ddr address of vcmd registers.
  1546. if (mmu_enable) {
  1547. if(sizeof(size_t) == 8) {
  1548. *(jmp_addr-6) = 0;
  1549. }
  1550. *(jmp_addr-7) = (u32)(dev->mmu_vcmd_reg_mem_busAddress);
  1551. } else {
  1552. if(sizeof(size_t) == 8) {
  1553. *(jmp_addr-6) = (u32)((u64)dev->vcmd_reg_mem_busAddress>>32);
  1554. } else {
  1555. *(jmp_addr-6) = 0;
  1556. }
  1557. *(jmp_addr-7) = (u32)(dev->vcmd_reg_mem_busAddress);
  1558. }
  1559. }
  1560. //start to link and/or run
  1561. spin_lock_irqsave(dev->spinlock, flags);
  1562. last_cmdbuf_node = find_last_linked_cmdbuf(new_cmdbuf_node);
  1563. record_last_cmdbuf_rdy_num=dev->sw_cmdbuf_rdy_num;
  1564. vcmd_link_cmdbuf(dev,last_cmdbuf_node);
  1565. if(dev->working_state==WORKING_STATE_IDLE)
  1566. {
  1567. //run
  1568. while (last_cmdbuf_node &&
  1569. ((struct cmdbuf_obj*)last_cmdbuf_node->data)->cmdbuf_run_done)
  1570. last_cmdbuf_node = last_cmdbuf_node->next;
  1571. if (last_cmdbuf_node && last_cmdbuf_node->data) {
  1572. PDEBUG("vcmd start for cmdbuf id %d, cmdbuf_run_done = %d\n",
  1573. ((struct cmdbuf_obj*)last_cmdbuf_node->data)->cmdbuf_id,
  1574. ((struct cmdbuf_obj*)last_cmdbuf_node->data)->cmdbuf_run_done);
  1575. }
  1576. vcmd_start(dev,last_cmdbuf_node);
  1577. }
  1578. else
  1579. {
  1580. //just update cmdbuf ready number
  1581. if(record_last_cmdbuf_rdy_num!=dev->sw_cmdbuf_rdy_num)
  1582. vcmd_write_register_value((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_RDY_CMDBUF_COUNT,dev->sw_cmdbuf_rdy_num);
  1583. }
  1584. spin_unlock_irqrestore(dev->spinlock, flags);
  1585. up(&vcmd_reserve_cmdbuf_sem[cmdbuf_obj->module_type]);
  1586. return 0;
  1587. }
  1588. /******************************************************************************/
  1589. static int check_cmdbuf_irq(struct hantrovcmd_dev* dev,struct cmdbuf_obj* cmdbuf_obj,u32 *irq_status_ret)
  1590. {
  1591. int rdy = 0;
  1592. unsigned long flags;
  1593. spin_lock_irqsave(dev->spinlock, flags);
  1594. if(cmdbuf_obj->cmdbuf_run_done)
  1595. {
  1596. rdy = 1;
  1597. *irq_status_ret=cmdbuf_obj->executing_status;//need to decide how to assign this variable
  1598. }
  1599. spin_unlock_irqrestore(dev->spinlock, flags);
  1600. return rdy;
  1601. }
  1602. /******************************************************************************/
  1603. static int check_mc_cmdbuf_irq(struct file *filp,struct cmdbuf_obj* cmdbuf_obj,u32 *irq_status_ret)
  1604. {
  1605. int k;
  1606. bi_list_node* new_cmdbuf_node=NULL;
  1607. struct hantrovcmd_dev* dev=NULL;
  1608. for(k=0;k<TOTAL_DISCRETE_CMDBUF_NUM;k++)
  1609. {
  1610. new_cmdbuf_node = global_cmdbuf_node[k];
  1611. if(new_cmdbuf_node==NULL)
  1612. continue;
  1613. cmdbuf_obj=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  1614. if(!cmdbuf_obj || cmdbuf_obj->filp != filp)
  1615. continue;
  1616. dev = &hantrovcmd_data[cmdbuf_obj->core_id];
  1617. if (check_cmdbuf_irq(dev, cmdbuf_obj, irq_status_ret) == 1) {
  1618. /* Return cmdbuf_id when ANY_CMDBUF_ID is used. */
  1619. if (!cmdbuf_obj->waited) {
  1620. *irq_status_ret = cmdbuf_obj->cmdbuf_id;
  1621. cmdbuf_obj->waited = 1;
  1622. return 1;
  1623. }
  1624. }
  1625. }
  1626. return 0;
  1627. }
  1628. #ifdef IRQ_SIMULATION
  1629. void get_random_bytes(void *buf, int nbytes);
  1630. #if 0
  1631. void hantrovcmd_trigger_irq_0(struct timer_list* timer)
  1632. {
  1633. PDEBUG("trigger core 0 irq\n");
  1634. del_timer(timer);
  1635. hantrovcmd_isr(0,(void *)&hantrovcmd_data[0]);
  1636. }
  1637. void hantrovcmd_trigger_irq_1(struct timer_list* timer)
  1638. {
  1639. PDEBUG("trigger core 1 irq\n");
  1640. del_timer(timer);
  1641. hantrovcmd_isr(0,(void *)&hantrovcmd_data[1]);
  1642. }
  1643. #else
  1644. void hantrovcmd_trigger_irq(struct timer_list *timer)
  1645. {
  1646. u32 timer_id=0;
  1647. u32 core_id=0;
  1648. u32 i;
  1649. for(i=0;i<10000;i++)
  1650. {
  1651. if(timer_reserve[i].timer==timer)
  1652. {
  1653. timer_id=timer_reserve[i].timer_id;
  1654. core_id = timer_reserve[i].core_id;
  1655. break;
  1656. }
  1657. }
  1658. PDEBUG("trigger core 0 irq\n");
  1659. hantrovcmd_isr(core_id,(void *)&hantrovcmd_data[core_id]);
  1660. del_timer(timer);
  1661. timer_reserve[timer_id].timer=NULL;
  1662. }
  1663. #endif
  1664. #endif
  1665. static unsigned int wait_cmdbuf_ready(struct file *filp,u16 cmdbuf_id,u32 *irq_status_ret)
  1666. {
  1667. struct cmdbuf_obj* cmdbuf_obj=NULL;
  1668. bi_list_node* new_cmdbuf_node=NULL;
  1669. struct hantrovcmd_dev* dev=NULL;
  1670. if (cmdbuf_id != ANY_CMDBUF_ID) {
  1671. PDEBUG("wait_cmdbuf_ready\n");
  1672. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  1673. if(new_cmdbuf_node==NULL)
  1674. {
  1675. //should not happen
  1676. pr_err("hantrovcmd: ERROR cmdbuf_id !!\n");
  1677. return -1;
  1678. }
  1679. cmdbuf_obj=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  1680. if(cmdbuf_obj->filp!=filp)
  1681. {
  1682. //should not happen
  1683. pr_err("hantrovcmd: ERROR cmdbuf_id !!\n");
  1684. return -1;
  1685. }
  1686. dev = &hantrovcmd_data[cmdbuf_obj->core_id];
  1687. #ifdef IRQ_SIMULATION
  1688. {
  1689. u64 random_num;
  1690. //get_random_bytes(&random_num, sizeof(u32));
  1691. random_num = (u32)((u64)100*cmdbuf_obj->executing_time/(4096*2160)+50);
  1692. PDEBUG("random_num=%d\n",random_num);
  1693. #if 0
  1694. /*init a timer to trigger irq*/
  1695. if (cmdbuf_obj->core_id==0)
  1696. {
  1697. //init_timer(&timer0);
  1698. //timer0.function = hantrovcmd_trigger_irq_0;
  1699. timer_setup(&timer0,hantrovcmd_trigger_irq_0,0);
  1700. timer0.expires = jiffies + random_num*HZ/10; //the expires time is 1s
  1701. add_timer(&timer0);
  1702. }
  1703. if (cmdbuf_obj->core_id==1)
  1704. {
  1705. //init_timer(&timer1);
  1706. //timer1.function = hantrovcmd_trigger_irq_1;
  1707. timer_setup(&timer1,hantrovcmd_trigger_irq_1,0);
  1708. timer1.expires = jiffies + random_num*HZ/10; //the expires time is 1s
  1709. add_timer(&timer1);
  1710. }
  1711. #else
  1712. {
  1713. u32 i;
  1714. struct timer_list *temp_timer=NULL;
  1715. for(i=0;i<10000;i++)
  1716. {
  1717. if(timer_reserve[i].timer==NULL)
  1718. {
  1719. timer_reserve[i].timer_id=i;
  1720. timer_reserve[i].core_id=cmdbuf_obj->core_id;
  1721. temp_timer=timer_reserve[i].timer =&timer[i] ;
  1722. break;
  1723. }
  1724. }
  1725. //if (cmdbuf_obj->core_id==0)
  1726. {
  1727. //init_timer(&timer0);
  1728. //timer0.function = hantrovcmd_trigger_irq_0;
  1729. timer_setup(temp_timer,hantrovcmd_trigger_irq,0);
  1730. temp_timer->expires = jiffies + random_num*HZ/10; //the expires time is 1s
  1731. add_timer(temp_timer);
  1732. }
  1733. }
  1734. #endif
  1735. }
  1736. #endif
  1737. if(wait_event_interruptible(*dev->wait_queue, check_cmdbuf_irq(dev,cmdbuf_obj,irq_status_ret)))
  1738. {
  1739. PDEBUG("vcmd_wait_queue_0 interrupted\n");
  1740. return -ERESTARTSYS;
  1741. }
  1742. pr_info("filp=%p, VCMD Wait CMDBUF [%d]\n", (void *)filp, cmdbuf_id);
  1743. return 0;
  1744. } else {
  1745. if (check_mc_cmdbuf_irq(filp, cmdbuf_obj, irq_status_ret))
  1746. return 0;
  1747. if(wait_event_interruptible(mc_wait_queue, check_mc_cmdbuf_irq(filp,cmdbuf_obj,irq_status_ret)))
  1748. {
  1749. PDEBUG("multicore wait queue interrupted\n");
  1750. return -ERESTARTSYS;
  1751. }
  1752. return 0;
  1753. }
  1754. }
  1755. long hantrovcmd_ioctl(struct file *filp,
  1756. unsigned int cmd, unsigned long arg)
  1757. {
  1758. int err = 0;
  1759. static int last_polling_cmd = 0;
  1760. struct process_manager_obj* process_manager_obj=NULL;
  1761. if (cmd != HANTRO_VCMD_IOCH_POLLING_CMDBUF) {
  1762. last_polling_cmd = 0;
  1763. PDEBUG("ioctl cmd 0x%08x\n", cmd);
  1764. } else {
  1765. if (!last_polling_cmd)
  1766. PDEBUG("ioctl cmd 0x%08x\n", cmd);
  1767. last_polling_cmd = 1;
  1768. }
  1769. /*
  1770. * extract the type and number bitfields, and don't encode
  1771. * wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok()
  1772. */
  1773. if(_IOC_TYPE(cmd) != HANTRO_VCMD_IOC_MAGIC )
  1774. return -ENOTTY;
  1775. if((_IOC_TYPE(cmd) == HANTRO_VCMD_IOC_MAGIC &&
  1776. _IOC_NR(cmd) > HANTRO_VCMD_IOC_MAXNR) )
  1777. return -ENOTTY;
  1778. /*
  1779. * the direction is a bitmask, and VERIFY_WRITE catches R/W
  1780. * transfers. `Type' is user-oriented, while
  1781. * access_ok is kernel-oriented, so the concept of "read" and
  1782. * "write" is reversed
  1783. */
  1784. #if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))
  1785. if(_IOC_DIR(cmd) & _IOC_READ)
  1786. err = !access_ok(VERIFY_WRITE, (void *) arg, _IOC_SIZE(cmd));
  1787. else if(_IOC_DIR(cmd) & _IOC_WRITE)
  1788. err = !access_ok(VERIFY_READ, (void *) arg, _IOC_SIZE(cmd));
  1789. #else
  1790. if(_IOC_DIR(cmd) & _IOC_READ)
  1791. err = !access_ok((void *) arg, _IOC_SIZE(cmd));
  1792. else if(_IOC_DIR(cmd) & _IOC_WRITE)
  1793. err = !access_ok((void *) arg, _IOC_SIZE(cmd));
  1794. #endif
  1795. if(err)
  1796. return -EFAULT;
  1797. process_manager_obj = (struct process_manager_obj*)filp->private_data;
  1798. switch (cmd)
  1799. {
  1800. case HANTRO_VCMD_IOCH_GET_CMDBUF_PARAMETER:
  1801. {
  1802. struct cmdbuf_mem_parameter local_cmdbuf_mem_data;
  1803. PDEBUG(" VCMD Reserve CMDBUF\n");
  1804. local_cmdbuf_mem_data.cmdbuf_unit_size = CMDBUF_MAX_SIZE;
  1805. local_cmdbuf_mem_data.status_cmdbuf_unit_size = CMDBUF_MAX_SIZE;
  1806. local_cmdbuf_mem_data.cmdbuf_total_size = CMDBUF_POOL_TOTAL_SIZE;
  1807. local_cmdbuf_mem_data.status_cmdbuf_total_size = CMDBUF_POOL_TOTAL_SIZE;
  1808. local_cmdbuf_mem_data.phy_status_cmdbuf_addr = vcmd_status_buf_mem_pool.busAddress;
  1809. local_cmdbuf_mem_data.phy_cmdbuf_addr = vcmd_buf_mem_pool.busAddress;
  1810. if (mmu_enable) {
  1811. local_cmdbuf_mem_data.mmu_phy_status_cmdbuf_addr = vcmd_status_buf_mem_pool.mmu_bus_address;
  1812. local_cmdbuf_mem_data.mmu_phy_cmdbuf_addr = vcmd_buf_mem_pool.mmu_bus_address;
  1813. } else {
  1814. local_cmdbuf_mem_data.mmu_phy_status_cmdbuf_addr = 0;
  1815. local_cmdbuf_mem_data.mmu_phy_cmdbuf_addr = 0;
  1816. }
  1817. local_cmdbuf_mem_data.base_ddr_addr = base_ddr_addr;
  1818. copy_to_user((struct cmdbuf_mem_parameter*)arg,&local_cmdbuf_mem_data,sizeof(struct cmdbuf_mem_parameter));
  1819. break;
  1820. }
  1821. case HANTRO_VCMD_IOCH_GET_VCMD_PARAMETER:
  1822. {
  1823. struct config_parameter input_para;
  1824. PDEBUG(" VCMD get vcmd config parameter \n");
  1825. copy_from_user(&input_para,(struct config_parameter*)arg,sizeof(struct config_parameter));
  1826. if(vcmd_type_core_num[input_para.module_type])
  1827. {
  1828. input_para.submodule_main_addr = vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_main_addr;
  1829. input_para.submodule_dec400_addr = vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_dec400_addr;
  1830. input_para.submodule_L2Cache_addr = vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_L2Cache_addr;
  1831. input_para.submodule_MMU_addr = vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_MMU_addr;
  1832. input_para.submodule_MMUWrite_addr = vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_MMUWrite_addr;
  1833. input_para.submodule_axife_addr = vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_axife_addr;
  1834. input_para.config_status_cmdbuf_id = vcmd_manager[input_para.module_type][0]->status_cmdbuf_id;
  1835. input_para.vcmd_hw_version_id = vcmd_manager[input_para.module_type][0]->hw_version_id;
  1836. input_para.vcmd_core_num = vcmd_type_core_num[input_para.module_type];
  1837. }
  1838. else
  1839. {
  1840. input_para.submodule_main_addr = 0xffff;
  1841. input_para.submodule_dec400_addr = 0xffff;
  1842. input_para.submodule_L2Cache_addr = 0xffff;
  1843. input_para.submodule_MMU_addr = 0xffff;
  1844. input_para.submodule_MMUWrite_addr = 0xffff;
  1845. input_para.submodule_axife_addr = 0xffff;
  1846. input_para.config_status_cmdbuf_id = 0;
  1847. input_para.vcmd_core_num = 0;
  1848. input_para.vcmd_hw_version_id =HW_ID_1_0_C;
  1849. }
  1850. copy_to_user((struct config_parameter*)arg,&input_para,sizeof(struct config_parameter));
  1851. break;
  1852. }
  1853. case HANTRO_VCMD_IOCH_RESERVE_CMDBUF:
  1854. {
  1855. int ret;
  1856. struct exchange_parameter input_para;
  1857. copy_from_user(&input_para,(struct exchange_parameter*)arg,sizeof(struct exchange_parameter));
  1858. ret = reserve_cmdbuf(filp,&input_para);
  1859. if (ret == 0)
  1860. copy_to_user((struct exchange_parameter*)arg,&input_para,sizeof(struct exchange_parameter));
  1861. pr_debug("filp=%p, VCMD Reserve CMDBUF [%d]\n", (void *)filp, input_para.cmdbuf_id);
  1862. return ret;
  1863. }
  1864. case HANTRO_VCMD_IOCH_LINK_RUN_CMDBUF:
  1865. {
  1866. struct exchange_parameter input_para;
  1867. long retVal;
  1868. copy_from_user(&input_para,(struct exchange_parameter*)arg,sizeof(struct exchange_parameter));
  1869. PDEBUG("VCMD link and run cmdbuf\n");
  1870. retVal = pm_runtime_resume_and_get(&hantrovcmd_data[0].pdev->dev);
  1871. if (retVal < 0)
  1872. return retVal;
  1873. if (process_manager_obj)
  1874. process_manager_obj->pm_count++;
  1875. retVal = link_and_run_cmdbuf(filp,&input_para);
  1876. copy_to_user((struct exchange_parameter*)arg,&input_para,sizeof(struct exchange_parameter));
  1877. return retVal;
  1878. break;
  1879. }
  1880. case HANTRO_VCMD_IOCH_WAIT_CMDBUF:
  1881. {
  1882. u16 cmdbuf_id;
  1883. unsigned int tmp;
  1884. u32 irq_status_ret=0;
  1885. __get_user(cmdbuf_id, (u16*)arg);
  1886. /*high 16 bits are core id, low 16 bits are cmdbuf_id*/
  1887. PDEBUG("VCMD wait for CMDBUF finishing. \n");
  1888. //TODO
  1889. tmp = wait_cmdbuf_ready(filp,cmdbuf_id,&irq_status_ret);
  1890. cmdbuf_id=(u16)irq_status_ret;
  1891. if (tmp==0)
  1892. {
  1893. __put_user(cmdbuf_id, (u16 *)arg);
  1894. return tmp;//return core_id
  1895. }
  1896. else
  1897. {
  1898. __put_user(0, (u16 *)arg);
  1899. return -1;
  1900. }
  1901. break;
  1902. }
  1903. case HANTRO_VCMD_IOCH_RELEASE_CMDBUF:
  1904. {
  1905. u16 cmdbuf_id;
  1906. __get_user(cmdbuf_id, (u16*)arg);
  1907. /*16 bits are cmdbuf_id*/
  1908. PDEBUG("VCMD release CMDBUF\n");
  1909. pm_runtime_mark_last_busy(&hantrovcmd_data[0].pdev->dev);
  1910. pm_runtime_put_autosuspend(&hantrovcmd_data[0].pdev->dev);
  1911. if (process_manager_obj)
  1912. process_manager_obj->pm_count--;
  1913. release_cmdbuf(filp,cmdbuf_id);
  1914. return 0;
  1915. break;
  1916. }
  1917. case HANTRO_VCMD_IOCH_POLLING_CMDBUF:
  1918. {
  1919. u16 core_id;
  1920. __get_user(core_id, (u16*)arg);
  1921. /*16 bits are cmdbuf_id*/
  1922. if(core_id>=total_vcmd_core_num)
  1923. return -1;
  1924. hantrovcmd_isr(core_id,&hantrovcmd_data[core_id]);
  1925. return 0;
  1926. break;
  1927. }
  1928. default:
  1929. {
  1930. break;
  1931. }
  1932. }
  1933. return 0;
  1934. }
  1935. /**********************************************************************************************************\
  1936. *process manager object management
  1937. \***********************************************************************************************************/
  1938. static struct process_manager_obj* create_process_manager_obj(void)
  1939. {
  1940. struct process_manager_obj* process_manager_obj=NULL;
  1941. process_manager_obj=vmalloc(sizeof(struct process_manager_obj));
  1942. if(process_manager_obj==NULL)
  1943. {
  1944. PDEBUG ("%s\n","vmalloc for process_manager_obj fail!");
  1945. return process_manager_obj;
  1946. }
  1947. memset(process_manager_obj,0,sizeof(struct process_manager_obj));
  1948. return process_manager_obj;
  1949. }
  1950. static void free_process_manager_obj( struct process_manager_obj* process_manager_obj)
  1951. {
  1952. if(process_manager_obj==NULL)
  1953. {
  1954. PDEBUG ("%s\n","free_process_manager_obj NULL");
  1955. return;
  1956. }
  1957. //free current cmdbuf_obj
  1958. vfree(process_manager_obj);
  1959. return;
  1960. }
  1961. static bi_list_node* create_process_manager_node(void)
  1962. {
  1963. bi_list_node* current_node=NULL;
  1964. struct process_manager_obj* process_manager_obj=NULL;
  1965. process_manager_obj=create_process_manager_obj();
  1966. if(process_manager_obj==NULL)
  1967. {
  1968. PDEBUG ("%s\n","create_process_manager_obj fail!");
  1969. return NULL;
  1970. }
  1971. process_manager_obj->total_exe_time = 0;
  1972. process_manager_obj->pm_count = 0;
  1973. spin_lock_init(&process_manager_obj->spinlock);
  1974. init_waitqueue_head(&process_manager_obj->wait_queue);
  1975. current_node=bi_list_create_node();
  1976. if(current_node==NULL)
  1977. {
  1978. PDEBUG ("%s\n","bi_list_create_node fail!");
  1979. free_process_manager_obj(process_manager_obj);
  1980. return NULL;
  1981. }
  1982. current_node->data = (void*)process_manager_obj;
  1983. return current_node;
  1984. }
  1985. static void free_process_manager_node(bi_list_node* process_node)
  1986. {
  1987. struct process_manager_obj* process_manager_obj=NULL;
  1988. if(process_node==NULL)
  1989. {
  1990. PDEBUG ("%s\n","free_process_manager_node NULL");
  1991. return;
  1992. }
  1993. process_manager_obj = (struct process_manager_obj*)process_node->data;
  1994. //free struct process_manager_obj
  1995. free_process_manager_obj (process_manager_obj);
  1996. //free current process_manager_obj entity.
  1997. bi_list_free_node(process_node);
  1998. return;
  1999. }
  2000. static long release_process_node_cleanup(bi_list* list)
  2001. {
  2002. bi_list_node* new_process_node=NULL;
  2003. while(1)
  2004. {
  2005. new_process_node=list->head;
  2006. if(new_process_node==NULL)
  2007. break;
  2008. //remove node from list
  2009. bi_list_remove_node(list,new_process_node);
  2010. //remove node from list
  2011. free_process_manager_node(new_process_node);
  2012. }
  2013. return 0;
  2014. }
  2015. static void create_kernel_process_manager(void)
  2016. {
  2017. bi_list_node* process_manager_node;
  2018. struct process_manager_obj* process_manager_obj=NULL;
  2019. process_manager_node = create_process_manager_node();
  2020. process_manager_obj = (struct process_manager_obj*)process_manager_node->data;
  2021. process_manager_obj->filp = NULL;
  2022. bi_list_insert_node_tail(&global_process_manager,process_manager_node);
  2023. }
  2024. /* Update the last JMP cmd in cmdbuf_ojb in order to jump to next_cmdbuf_obj. */
  2025. static void cmdbuf_update_jmp_cmd(int hw_version_id,
  2026. struct cmdbuf_obj *cmdbuf_obj,
  2027. struct cmdbuf_obj *next_cmdbuf_obj,
  2028. int jmp_IE_1) {
  2029. u32 *jmp_addr;
  2030. u32 operation_code;
  2031. if(!cmdbuf_obj)
  2032. return;
  2033. if(cmdbuf_obj->has_end_cmdbuf==0)
  2034. {
  2035. //need to link, current cmdbuf link to next cmdbuf
  2036. jmp_addr = cmdbuf_obj->cmdbuf_virtualAddress + (cmdbuf_obj->cmdbuf_size/4);
  2037. if (!next_cmdbuf_obj) {
  2038. // If next cmdbuf is not available, set the RDY to 0.
  2039. operation_code = *(jmp_addr-4);
  2040. operation_code >>=16;
  2041. operation_code <<=16;
  2042. *(jmp_addr-4)=(u32)(operation_code & ~JMP_RDY_1);
  2043. } else {
  2044. if(hw_version_id > HW_ID_1_0_C )
  2045. {
  2046. //set next cmdbuf id
  2047. *(jmp_addr-1) = next_cmdbuf_obj->cmdbuf_id;
  2048. }
  2049. if (mmu_enable) {
  2050. if(sizeof(size_t) == 8) {
  2051. *(jmp_addr-2)=(u32)((u64)(next_cmdbuf_obj->mmu_cmdbuf_busAddress)>>32);
  2052. } else {
  2053. *(jmp_addr-2)=0;
  2054. }
  2055. *(jmp_addr-3)=(u32)(next_cmdbuf_obj->mmu_cmdbuf_busAddress);
  2056. } else {
  2057. if(sizeof(size_t) == 8) {
  2058. *(jmp_addr-2)=(u32)((u64)(next_cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr)>>32);
  2059. } else {
  2060. *(jmp_addr-2)=0;
  2061. }
  2062. *(jmp_addr-3)=(u32)(next_cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr);
  2063. }
  2064. operation_code = *(jmp_addr-4);
  2065. operation_code >>=16;
  2066. operation_code <<=16;
  2067. *(jmp_addr-4)=(u32)(operation_code |JMP_RDY_1|jmp_IE_1|((next_cmdbuf_obj->cmdbuf_size+7)/8));
  2068. }
  2069. #ifdef VCMD_DEBUG_INTERNAL
  2070. {
  2071. u32 i;
  2072. pr_info("vcmd link, last cmdbuf content\n");
  2073. for(i=cmdbuf_obj->cmdbuf_size/4 -8;i<cmdbuf_obj->cmdbuf_size/4;i++)
  2074. {
  2075. pr_info("current linked cmdbuf data %d =0x%x\n",i,*(cmdbuf_obj->cmdbuf_virtualAddress+i));
  2076. }
  2077. }
  2078. #endif
  2079. }
  2080. }
  2081. /* delink given cmd buffer (cmdbuf_node) and remove it from list.
  2082. Also modify the last JMP of buf P to point to cmdbuf N.
  2083. Used when a process is terminated but there are pending cmd bufs in vmcd list.
  2084. E.g.,
  2085. before:
  2086. L->L->...->P->X->N-> ... ->L
  2087. ^ ^ ^
  2088. head cmdbuf_node tail
  2089. end:
  2090. L->L->...->P->N-> ... ->L
  2091. ^ ^
  2092. head tail
  2093. Return: pointer to N or NULL if N doesn't exist.
  2094. */
  2095. void vcmd_delink_rm_cmdbuf(struct hantrovcmd_dev *dev, bi_list_node* cmdbuf_node)
  2096. {
  2097. bi_list *list = &dev->list_manager;
  2098. struct cmdbuf_obj* cmdbuf_obj = (struct cmdbuf_obj*)cmdbuf_node->data;
  2099. bi_list_node* prev = cmdbuf_node->previous;
  2100. bi_list_node* next = cmdbuf_node->next;
  2101. PDEBUG("Delink and remove cmdbuf [%d] from vcmd list.\n", cmdbuf_obj->cmdbuf_id);
  2102. #ifdef HANTRO_VCMD_DRIVER_DEBUG
  2103. if (prev) {
  2104. PDEBUG("prev cmdbuf [%d].\n", ((struct cmdbuf_obj*)prev->data)->cmdbuf_id);
  2105. } else {
  2106. PDEBUG("NO prev cmdbuf.\n");
  2107. }
  2108. if (next) {
  2109. PDEBUG("next cmdbuf [%d].\n", ((struct cmdbuf_obj*)next->data)->cmdbuf_id);
  2110. } else {
  2111. PDEBUG("NO next cmdbuf.\n");
  2112. }
  2113. #endif
  2114. bi_list_remove_node(list, cmdbuf_node);
  2115. global_cmdbuf_node[cmdbuf_obj->cmdbuf_id] = NULL;
  2116. free_cmdbuf_node(cmdbuf_node);
  2117. cmdbuf_update_jmp_cmd(dev->hw_version_id, prev ? prev->data : NULL, next ? next->data : NULL,
  2118. dev->duration_without_int > INT_MIN_SUM_OF_IMAGE_SIZE);
  2119. }
  2120. int hantrovcmd_open(struct inode *inode, struct file *filp)
  2121. {
  2122. int result = 0;
  2123. struct hantrovcmd_dev *dev = hantrovcmd_data;
  2124. bi_list_node* process_manager_node;
  2125. unsigned long flags;
  2126. struct process_manager_obj* process_manager_obj=NULL;
  2127. filp->private_data = NULL;
  2128. process_manager_node = create_process_manager_node();
  2129. if(process_manager_node== NULL)
  2130. return -1;
  2131. process_manager_obj = (struct process_manager_obj*)process_manager_node->data;
  2132. process_manager_obj->filp = filp;
  2133. spin_lock_irqsave(&vcmd_process_manager_lock, flags);
  2134. bi_list_insert_node_tail(&global_process_manager,process_manager_node);
  2135. spin_unlock_irqrestore(&vcmd_process_manager_lock, flags);
  2136. filp->private_data = process_manager_node->data;
  2137. PDEBUG("dev opened\n");
  2138. PDEBUG("process node %p for filp opened %p\n", (void *)process_manager_node, (void *)filp);
  2139. return result;
  2140. }
  2141. int hantrovcmd_release(struct inode *inode, struct file *filp)
  2142. {
  2143. struct hantrovcmd_dev *dev = hantrovcmd_data;
  2144. u32 core_id = 0;
  2145. u32 release_cmdbuf_num=0;
  2146. bi_list_node* new_cmdbuf_node=NULL;
  2147. struct cmdbuf_obj* cmdbuf_obj_temp=NULL;
  2148. bi_list_node* process_manager_node;
  2149. struct process_manager_obj* process_manager_obj=NULL;
  2150. int vcmd_aborted = 0; // vcmd is aborted in this function
  2151. struct cmdbuf_obj* restart_cmdbuf = NULL;
  2152. unsigned long flags;
  2153. long retVal=0;
  2154. PDEBUG("dev closed for process %p via hantrovcmd_release\n", (void *)filp);
  2155. if (down_interruptible(&vcmd_reserve_cmdbuf_sem[dev->vcmd_core_cfg.sub_module_type]))
  2156. return -ERESTARTSYS;
  2157. for (core_id = 0;core_id < total_vcmd_core_num; core_id++)
  2158. {
  2159. if((&dev[core_id])==NULL)
  2160. continue;
  2161. spin_lock_irqsave(dev[core_id].spinlock, flags);
  2162. new_cmdbuf_node=dev[core_id].list_manager.head;
  2163. while(1)
  2164. {
  2165. if(new_cmdbuf_node==NULL)
  2166. break;
  2167. cmdbuf_obj_temp=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  2168. PDEBUG("Process %p is releasing: checking cmdbuf %d of process %p.\n",
  2169. filp, cmdbuf_obj_temp->cmdbuf_id, cmdbuf_obj_temp->filp);
  2170. if (dev[core_id].hwregs && (cmdbuf_obj_temp->filp == filp))
  2171. {
  2172. if(cmdbuf_obj_temp->cmdbuf_run_done)
  2173. {
  2174. cmdbuf_obj_temp->cmdbuf_need_remove=1;
  2175. retVal=release_cmdbuf_node(&dev[core_id].list_manager,new_cmdbuf_node);
  2176. if(retVal==1)
  2177. cmdbuf_obj_temp->process_manager_obj = NULL;
  2178. }
  2179. else if(cmdbuf_obj_temp->cmdbuf_data_linked==0)
  2180. {
  2181. cmdbuf_obj_temp->cmdbuf_data_linked = 1;
  2182. cmdbuf_obj_temp->cmdbuf_run_done=1;
  2183. cmdbuf_obj_temp->cmdbuf_need_remove=1;
  2184. retVal=release_cmdbuf_node(&dev[core_id].list_manager,new_cmdbuf_node);
  2185. if(retVal==1)
  2186. cmdbuf_obj_temp->process_manager_obj = NULL;
  2187. }
  2188. else if(cmdbuf_obj_temp->cmdbuf_data_linked==1 && dev[core_id].working_state==WORKING_STATE_IDLE)
  2189. {
  2190. vcmd_delink_rm_cmdbuf(&dev[core_id], new_cmdbuf_node);
  2191. if (restart_cmdbuf == cmdbuf_obj_temp)
  2192. restart_cmdbuf = new_cmdbuf_node->next ? new_cmdbuf_node->next->data : NULL;
  2193. if (restart_cmdbuf) {
  2194. PDEBUG("Set restart cmdbuf [%d].\n", restart_cmdbuf->cmdbuf_id);
  2195. } else {
  2196. PDEBUG("Set restart cmdbuf to NULL.\n");
  2197. }
  2198. }
  2199. else if(cmdbuf_obj_temp->cmdbuf_data_linked==1 && dev[core_id].working_state==WORKING_STATE_WORKING)
  2200. {
  2201. bi_list_node* last_cmdbuf_node = NULL;
  2202. bi_list_node* done_cmdbuf_node = NULL;
  2203. int abort_cmdbuf_id;
  2204. int loop_count = 0;
  2205. //abort the vcmd and wait
  2206. PDEBUG("Abort due to linked cmdbuf %d of current process.\n", cmdbuf_obj_temp->cmdbuf_id);
  2207. printk_vcmd_register_debug((const void *)dev->hwregs, "Before trigger to 0");
  2208. // disable abort interrupt
  2209. //vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_IRQ_ABORT_EN,0);
  2210. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_START_TRIGGER,0);
  2211. vcmd_aborted = 1;
  2212. printk_vcmd_register_debug((const void *)dev->hwregs,"After trigger to 0");
  2213. // Wait vcmd core aborted and vcmd enters IDLE mode.
  2214. //while (dev[core_id].working_state != WORKING_STATE_IDLE) {
  2215. while (vcmd_get_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_WORK_STATE)) {
  2216. loop_count++;
  2217. if (!(loop_count % 10)) {
  2218. u32 irq_status = vcmd_read_reg((const void *)dev->hwregs, VCMD_REGISTER_INT_STATUS_OFFSET);
  2219. pr_err("hantrovcmd: expected idle state, but irq status = 0x%0x\n", irq_status);
  2220. pr_err("hantrovcmd: vcmd current status is %d\n", vcmd_get_register_value((const void *)dev->hwregs, dev[core_id].reg_mirror, HWIF_VCMD_WORK_STATE));
  2221. }
  2222. mdelay(10); // wait 10ms
  2223. if (loop_count > 100) { // too long
  2224. pr_err("hantrovcmd: too long before vcmd core to IDLE state\n");
  2225. process_manager_obj = (struct process_manager_obj*)filp->private_data;
  2226. if (process_manager_obj)
  2227. {
  2228. while(process_manager_obj->pm_count > 0)
  2229. {
  2230. pm_runtime_mark_last_busy(&dev[0].pdev->dev);
  2231. pm_runtime_put_autosuspend(&dev[0].pdev->dev);
  2232. process_manager_obj->pm_count--;
  2233. }
  2234. }
  2235. spin_unlock_irqrestore(dev[core_id].spinlock, flags);
  2236. up(&vcmd_reserve_cmdbuf_sem[dev->vcmd_core_cfg.sub_module_type]);
  2237. return -ERESTARTSYS;
  2238. }
  2239. }
  2240. dev[core_id].working_state = WORKING_STATE_IDLE;
  2241. // clear interrupt & restore abort_e
  2242. if (vcmd_get_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_IRQ_ABORT)) {
  2243. PDEBUG("Abort interrupt triggered, now clear it to avoid abort int...\n");
  2244. vcmd_write_reg((const void *)dev->hwregs, VCMD_REGISTER_INT_STATUS_OFFSET, 0x1<<4);
  2245. PDEBUG("Now irq status = 0x%0x.\n", vcmd_read_reg((const void *)dev->hwregs, VCMD_REGISTER_INT_STATUS_OFFSET));
  2246. }
  2247. //printk_vcmd_register_debug((const void *)dev->hwregs, "vcmd status to IDLE");
  2248. abort_cmdbuf_id = vcmd_get_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_CMDBUF_EXECUTING_ID);
  2249. PDEBUG("Abort when executing cmd buf %d.\n", abort_cmdbuf_id);
  2250. dev[core_id].sw_cmdbuf_rdy_num = 0;
  2251. dev[core_id].duration_without_int = 0;
  2252. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_EXE_CMDBUF_COUNT,0);
  2253. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_RDY_CMDBUF_COUNT,0);
  2254. /* Mark cmdbuf_run_done to 1 for all the cmd buf executed. */
  2255. done_cmdbuf_node = dev[core_id].list_manager.head;
  2256. while (done_cmdbuf_node) {
  2257. if (!((struct cmdbuf_obj*)done_cmdbuf_node->data)->cmdbuf_run_done) {
  2258. ((struct cmdbuf_obj*)done_cmdbuf_node->data)->cmdbuf_run_done = 1;
  2259. ((struct cmdbuf_obj*)done_cmdbuf_node->data)->cmdbuf_data_linked = 0;
  2260. PDEBUG("Set cmdbuf [%d] cmdbuf_run_done to 1.\n", ((struct cmdbuf_obj*)done_cmdbuf_node->data)->cmdbuf_id);
  2261. }
  2262. if (((struct cmdbuf_obj*)done_cmdbuf_node->data)->cmdbuf_id == abort_cmdbuf_id)
  2263. break;
  2264. done_cmdbuf_node = done_cmdbuf_node->next;
  2265. }
  2266. if (cmdbuf_obj_temp->cmdbuf_run_done) {
  2267. /* current cmdbuf is in fact has been executed, but due to interrupt is not triggered, the status is not updated.
  2268. Just delink and remove it from the list. */
  2269. if (done_cmdbuf_node && done_cmdbuf_node->data) {
  2270. PDEBUG("done_cmdbuf_node is cmdbuf [%d].\n", ((struct cmdbuf_obj*)done_cmdbuf_node->data)->cmdbuf_id);
  2271. }
  2272. done_cmdbuf_node = done_cmdbuf_node->next;
  2273. if (done_cmdbuf_node)
  2274. restart_cmdbuf = (struct cmdbuf_obj*)done_cmdbuf_node->data;
  2275. if (restart_cmdbuf) {
  2276. PDEBUG("Set restart cmdbuf [%d] via if.\n", restart_cmdbuf->cmdbuf_id);
  2277. }
  2278. } else {
  2279. last_cmdbuf_node = new_cmdbuf_node;
  2280. /* cmd buf num from aborted cmd buf to current cmdbuf_obj_temp */
  2281. if (cmdbuf_obj_temp->cmdbuf_id != abort_cmdbuf_id) {
  2282. last_cmdbuf_node = new_cmdbuf_node->previous;
  2283. while (last_cmdbuf_node &&
  2284. ((struct cmdbuf_obj*)last_cmdbuf_node->data)->cmdbuf_id != abort_cmdbuf_id) {
  2285. restart_cmdbuf = (struct cmdbuf_obj*)last_cmdbuf_node->data;
  2286. last_cmdbuf_node = last_cmdbuf_node->previous;
  2287. dev[core_id].sw_cmdbuf_rdy_num++;
  2288. dev[core_id].duration_without_int += restart_cmdbuf->executing_time;
  2289. PDEBUG("Keep valid cmdbuf [%d] in the list.\n", restart_cmdbuf->cmdbuf_id);
  2290. }
  2291. }
  2292. if (restart_cmdbuf) {
  2293. PDEBUG("Set restart cmdbuf [%d] via else.\n", restart_cmdbuf->cmdbuf_id);
  2294. }
  2295. }
  2296. // remove first linked cmdbuf from list
  2297. vcmd_delink_rm_cmdbuf(&dev[core_id], new_cmdbuf_node);
  2298. }
  2299. release_cmdbuf_num++;
  2300. PDEBUG("release reserved cmdbuf\n");
  2301. } else if (vcmd_aborted && !cmdbuf_obj_temp->cmdbuf_run_done) {
  2302. /* VCMD is aborted, need to re-calculate the duration_without_int */
  2303. if (!restart_cmdbuf)
  2304. restart_cmdbuf = cmdbuf_obj_temp; /* first cmdbuf to be restarted */
  2305. dev[core_id].duration_without_int += cmdbuf_obj_temp->executing_time;
  2306. dev[core_id].sw_cmdbuf_rdy_num++;
  2307. }
  2308. new_cmdbuf_node = new_cmdbuf_node->next;
  2309. }
  2310. if (restart_cmdbuf) {
  2311. u32 irq_status1, irq_status2;
  2312. PDEBUG("Restart from cmdbuf [%d] after aborting.\n", restart_cmdbuf->cmdbuf_id);
  2313. irq_status1 = vcmd_read_reg((const void *)dev->hwregs, VCMD_REGISTER_INT_STATUS_OFFSET);
  2314. vcmd_write_reg((const void *)dev->hwregs, VCMD_REGISTER_INT_STATUS_OFFSET, irq_status1);
  2315. irq_status2 = vcmd_read_reg((const void *)dev->hwregs, VCMD_REGISTER_INT_STATUS_OFFSET);
  2316. PDEBUG("Clear irq status from 0x%0x -> 0x%0x\n", irq_status1, irq_status2);
  2317. if (mmu_enable) {
  2318. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR,
  2319. (u32)(restart_cmdbuf->mmu_cmdbuf_busAddress));
  2320. if(sizeof(size_t) == 8) {
  2321. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR_MSB,(u32)((u64)(restart_cmdbuf->mmu_cmdbuf_busAddress)>>32));
  2322. } else {
  2323. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR_MSB, 0);
  2324. }
  2325. } else {
  2326. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR,(u32)(restart_cmdbuf->cmdbuf_busAddress-base_ddr_addr));
  2327. if(sizeof(size_t) == 8) {
  2328. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR_MSB,(u32)((u64)(restart_cmdbuf->cmdbuf_busAddress-base_ddr_addr)>>32));
  2329. } else {
  2330. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR_MSB, 0);
  2331. }
  2332. }
  2333. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_EXE_CMDBUF_COUNT,0);
  2334. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_EXE_CMDBUF_LENGTH,(u32)((restart_cmdbuf->cmdbuf_size+7)/8));
  2335. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_CMDBUF_EXECUTING_ID,restart_cmdbuf->cmdbuf_id);
  2336. PDEBUG("====dev->sw_cmdbuf_rdy_num is %d\n", dev[core_id].sw_cmdbuf_rdy_num);
  2337. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_RDY_CMDBUF_COUNT,dev[core_id].sw_cmdbuf_rdy_num);
  2338. printk_vcmd_register_debug((const void *)dev->hwregs, "before restart");
  2339. vcmd_write_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_START_TRIGGER,1);
  2340. PDEBUG("Restart from cmdbuf [%d] after aborting: start trigger = %d.\n", restart_cmdbuf->cmdbuf_id,
  2341. vcmd_get_register_value((const void *)dev[core_id].hwregs,dev[core_id].reg_mirror,HWIF_VCMD_START_TRIGGER));
  2342. PDEBUG("dev state from %d -> WORKING.\n", dev[core_id].working_state);
  2343. dev[core_id].working_state = WORKING_STATE_WORKING;
  2344. printk_vcmd_register_debug((const void *)dev->hwregs, "after restart");
  2345. } else {
  2346. PDEBUG("No more command buffer to be restarted!\n");
  2347. }
  2348. spin_unlock_irqrestore(dev[core_id].spinlock, flags);
  2349. // VCMD aborted but not restarted, nedd to wake up
  2350. if (vcmd_aborted && !restart_cmdbuf)
  2351. wake_up_interruptible_all(dev[core_id].wait_queue);
  2352. }
  2353. if(release_cmdbuf_num)
  2354. wake_up_interruptible_all(&vcmd_cmdbuf_memory_wait);
  2355. spin_lock_irqsave(&vcmd_process_manager_lock, flags);
  2356. process_manager_node = global_process_manager.head;
  2357. while(1)
  2358. {
  2359. if(process_manager_node == NULL)
  2360. break;
  2361. process_manager_obj = (struct process_manager_obj*)process_manager_node->data;
  2362. if(process_manager_obj->filp == filp)
  2363. break;
  2364. process_manager_node = process_manager_node->next;
  2365. }
  2366. if (process_manager_obj)
  2367. {
  2368. while(process_manager_obj->pm_count > 0)
  2369. {
  2370. pm_runtime_mark_last_busy(&dev[0].pdev->dev);
  2371. pm_runtime_put_autosuspend(&dev[0].pdev->dev);
  2372. process_manager_obj->pm_count--;
  2373. }
  2374. }
  2375. //remove node from list
  2376. PDEBUG("process node %p for filp to be removed: %p\n", (void *)process_manager_node, (void *)process_manager_obj->filp);
  2377. bi_list_remove_node(&global_process_manager,process_manager_node);
  2378. spin_unlock_irqrestore(&vcmd_process_manager_lock, flags);
  2379. free_process_manager_node(process_manager_node);
  2380. up(&vcmd_reserve_cmdbuf_sem[dev->vcmd_core_cfg.sub_module_type]);
  2381. return 0;
  2382. }
  2383. /*------------------------------------------------------------------------------
  2384. Function name : vcmd_pcie_init
  2385. Description : Initialize PCI Hw access
  2386. Return type : int
  2387. ------------------------------------------------------------------------------*/
  2388. static int vcmd_init(struct platform_device *pdev)
  2389. {
  2390. int i =0;
  2391. struct kernel_addr_desc addr;
  2392. struct pci_dev *g_vcmd_dev = NULL; /* PCI device structure. */
  2393. vcmd_buf_mem_pool.virtualAddress = dma_alloc_coherent(&pdev->dev, CMDBUF_POOL_TOTAL_SIZE*2 + CMDBUF_VCMD_REGISTER_TOTAL_SIZE,
  2394. &vcmd_buf_mem_pool.busAddress, GFP_KERNEL | GFP_DMA);
  2395. pr_info("Base memory val 0x%llx\n", vcmd_buf_mem_pool.busAddress);
  2396. pr_info("Base memory len 0x%x\n", CMDBUF_POOL_TOTAL_SIZE*2 + CMDBUF_VCMD_REGISTER_TOTAL_SIZE);
  2397. vcmd_buf_mem_pool.size =CMDBUF_POOL_TOTAL_SIZE;
  2398. pr_info("Init: vcmd_buf_mem_pool.busAddress=0x%llx.\n",(long long unsigned int)vcmd_buf_mem_pool.busAddress);
  2399. if (vcmd_buf_mem_pool.virtualAddress == NULL ) {
  2400. pr_info("Init: failed to ioremap.\n");
  2401. return -1;
  2402. }
  2403. pr_info("Init: vcmd_buf_mem_pool.virtualAddress=0x%llx.\n",(long long unsigned int)vcmd_buf_mem_pool.virtualAddress);
  2404. if (mmu_enable) {
  2405. addr.bus_address = vcmd_buf_mem_pool.busAddress - gBaseDDRHw;
  2406. addr.size = vcmd_buf_mem_pool.size;
  2407. if(MMUKernelMemNodeMap(&addr) != MMU_STATUS_OK) {
  2408. return -1;
  2409. }
  2410. vcmd_buf_mem_pool.mmu_bus_address = addr.mmu_bus_address;
  2411. pr_info("Init: vcmd_buf_mem_pool.mmu_bus_address=0x%llx.\n",(long long unsigned int)vcmd_buf_mem_pool.mmu_bus_address);
  2412. }
  2413. vcmd_status_buf_mem_pool.busAddress = (void *)vcmd_buf_mem_pool.busAddress+CMDBUF_POOL_TOTAL_SIZE;
  2414. vcmd_status_buf_mem_pool.virtualAddress = (void *)vcmd_buf_mem_pool.virtualAddress+CMDBUF_POOL_TOTAL_SIZE;
  2415. vcmd_status_buf_mem_pool.size =CMDBUF_POOL_TOTAL_SIZE;
  2416. pr_info("Init: vcmd_status_buf_mem_pool.busAddress=0x%llx.\n",(long long unsigned int)vcmd_status_buf_mem_pool.busAddress);
  2417. if (vcmd_status_buf_mem_pool.virtualAddress == NULL ) {
  2418. pr_info("Init: failed to ioremap.\n");
  2419. return -1;
  2420. }
  2421. pr_info("Init: vcmd_status_buf_mem_pool.virtualAddress=0x%llx.\n",(long long unsigned int)vcmd_status_buf_mem_pool.virtualAddress);
  2422. if (mmu_enable) {
  2423. addr.bus_address = vcmd_status_buf_mem_pool.busAddress - gBaseDDRHw;
  2424. addr.size = vcmd_status_buf_mem_pool.size;
  2425. if(MMUKernelMemNodeMap(&addr) != MMU_STATUS_OK) {
  2426. return -1;
  2427. }
  2428. vcmd_status_buf_mem_pool.mmu_bus_address = addr.mmu_bus_address;
  2429. pr_info("Init: vcmd_status_buf_mem_pool.mmu_bus_address=0x%llx.\n",(long long unsigned int)vcmd_status_buf_mem_pool.mmu_bus_address);
  2430. }
  2431. vcmd_registers_mem_pool.busAddress = (void *)vcmd_buf_mem_pool.busAddress+CMDBUF_POOL_TOTAL_SIZE*2;
  2432. vcmd_registers_mem_pool.virtualAddress = (void *)vcmd_buf_mem_pool.virtualAddress+CMDBUF_POOL_TOTAL_SIZE*2;
  2433. vcmd_registers_mem_pool.size =CMDBUF_VCMD_REGISTER_TOTAL_SIZE;
  2434. pr_info("Init: vcmd_registers_mem_pool.busAddress=0x%llx.\n",(long long unsigned int)vcmd_registers_mem_pool.busAddress);
  2435. if (vcmd_registers_mem_pool.virtualAddress == NULL ) {
  2436. pr_info("Init: failed to ioremap.\n");
  2437. return -1;
  2438. }
  2439. pr_info("Init: vcmd_registers_mem_pool.virtualAddress=0x%llx.\n",(long long unsigned int)vcmd_registers_mem_pool.virtualAddress);
  2440. if (mmu_enable) {
  2441. addr.bus_address = vcmd_registers_mem_pool.busAddress - gBaseDDRHw;
  2442. addr.size = vcmd_registers_mem_pool.size;
  2443. if(MMUKernelMemNodeMap(&addr) != MMU_STATUS_OK) {
  2444. return -1;
  2445. }
  2446. vcmd_registers_mem_pool.mmu_bus_address = addr.mmu_bus_address;
  2447. pr_info("Init: vcmd_registers_mem_pool.mmu_bus_address=0x%llx.\n",(long long unsigned int)vcmd_registers_mem_pool.mmu_bus_address);
  2448. }
  2449. return 0;
  2450. out_pci_disable_device:
  2451. pci_disable_device(g_vcmd_dev);
  2452. out:
  2453. return -1;
  2454. }
  2455. static void vcmd_link_cmdbuf(struct hantrovcmd_dev *dev,bi_list_node* last_linked_cmdbuf_node)
  2456. {
  2457. bi_list_node* new_cmdbuf_node=NULL;
  2458. bi_list_node* next_cmdbuf_node=NULL;
  2459. struct cmdbuf_obj* cmdbuf_obj=NULL;
  2460. struct cmdbuf_obj* next_cmdbuf_obj=NULL;
  2461. u32 * jmp_addr=NULL;
  2462. u32 operation_code;
  2463. new_cmdbuf_node = last_linked_cmdbuf_node;
  2464. //for the first cmdbuf.
  2465. if(new_cmdbuf_node!=NULL)
  2466. {
  2467. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  2468. if((cmdbuf_obj->cmdbuf_data_linked==0) )
  2469. {
  2470. dev->sw_cmdbuf_rdy_num ++;
  2471. cmdbuf_obj->cmdbuf_data_linked=1;
  2472. dev->duration_without_int = 0;
  2473. if(cmdbuf_obj->has_end_cmdbuf==0)
  2474. {
  2475. if(cmdbuf_obj->no_normal_int_cmdbuf==1)
  2476. {
  2477. dev->duration_without_int = cmdbuf_obj->executing_time;
  2478. //maybe nop is modified, so write back.
  2479. if(dev->duration_without_int>=INT_MIN_SUM_OF_IMAGE_SIZE)
  2480. {
  2481. jmp_addr = cmdbuf_obj->cmdbuf_virtualAddress + (cmdbuf_obj->cmdbuf_size/4);
  2482. operation_code = *(jmp_addr-4);
  2483. operation_code = JMP_IE_1|operation_code;
  2484. *(jmp_addr-4) = operation_code;
  2485. dev->duration_without_int = 0;
  2486. }
  2487. }
  2488. }
  2489. }
  2490. }
  2491. while(1)
  2492. {
  2493. if(new_cmdbuf_node==NULL)
  2494. break;
  2495. if(new_cmdbuf_node->next==NULL)
  2496. break;
  2497. next_cmdbuf_node = new_cmdbuf_node->next;
  2498. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  2499. next_cmdbuf_obj = (struct cmdbuf_obj*)next_cmdbuf_node->data;
  2500. if(cmdbuf_obj->has_end_cmdbuf==0 && !next_cmdbuf_obj->cmdbuf_run_done)
  2501. {
  2502. //need to link, current cmdbuf link to next cmdbuf
  2503. PDEBUG("Link cmdbuf %d to cmdbuf %d", cmdbuf_obj->cmdbuf_id, next_cmdbuf_obj->cmdbuf_id);
  2504. jmp_addr = cmdbuf_obj->cmdbuf_virtualAddress + (cmdbuf_obj->cmdbuf_size/4);
  2505. if(dev->hw_version_id > HW_ID_1_0_C )
  2506. {
  2507. //set next cmdbuf id
  2508. *(jmp_addr-1) = next_cmdbuf_obj->cmdbuf_id;
  2509. }
  2510. if (mmu_enable) {
  2511. if(sizeof(size_t) == 8) {
  2512. *(jmp_addr-2)=(u32)((u64)(next_cmdbuf_obj->mmu_cmdbuf_busAddress)>>32);
  2513. } else {
  2514. *(jmp_addr-2)=0;
  2515. }
  2516. *(jmp_addr-3)=(u32)(next_cmdbuf_obj->mmu_cmdbuf_busAddress);
  2517. } else {
  2518. if(sizeof(size_t) == 8) {
  2519. *(jmp_addr-2)=(u32)((u64)(next_cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr)>>32);
  2520. } else {
  2521. *(jmp_addr-2)=0;
  2522. }
  2523. *(jmp_addr-3)=(u32)(next_cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr);
  2524. }
  2525. operation_code = *(jmp_addr-4);
  2526. operation_code >>=16;
  2527. operation_code <<=16;
  2528. *(jmp_addr-4)=(u32)(operation_code |JMP_RDY_1|((next_cmdbuf_obj->cmdbuf_size+7)/8));
  2529. next_cmdbuf_obj->cmdbuf_data_linked = 1;
  2530. dev->sw_cmdbuf_rdy_num ++;
  2531. //modify nop code of next cmdbuf
  2532. if(next_cmdbuf_obj->has_end_cmdbuf==0)
  2533. {
  2534. if(next_cmdbuf_obj->no_normal_int_cmdbuf==1)
  2535. {
  2536. dev->duration_without_int +=next_cmdbuf_obj->executing_time;
  2537. //maybe we see the modified nop before abort, so need to write back.
  2538. if(dev->duration_without_int>=INT_MIN_SUM_OF_IMAGE_SIZE)
  2539. {
  2540. jmp_addr = next_cmdbuf_obj->cmdbuf_virtualAddress + (next_cmdbuf_obj->cmdbuf_size/4);
  2541. operation_code = *(jmp_addr-4);
  2542. operation_code = JMP_IE_1|operation_code;
  2543. *(jmp_addr-4) = operation_code;
  2544. dev->duration_without_int = 0;
  2545. }
  2546. }
  2547. }
  2548. else
  2549. {
  2550. dev->duration_without_int = 0;
  2551. }
  2552. #ifdef VCMD_DEBUG_INTERNAL
  2553. {
  2554. u32 i;
  2555. pr_info("vcmd link, last cmdbuf content\n");
  2556. for(i=cmdbuf_obj->cmdbuf_size/4 -8;i<cmdbuf_obj->cmdbuf_size/4;i++)
  2557. {
  2558. pr_info("current linked cmdbuf data %d =0x%x\n",i,*(cmdbuf_obj->cmdbuf_virtualAddress+i));
  2559. }
  2560. }
  2561. #endif
  2562. }
  2563. else
  2564. break;
  2565. new_cmdbuf_node = new_cmdbuf_node->next;
  2566. }
  2567. return;
  2568. }
  2569. /* delink all the cmd buffers from the cmdbuf in front oflast_linked_cmdbuf_node
  2570. to head of the list. All the cmd bufs marked as X will be delinked.
  2571. E.g.,
  2572. X->X->...->X->L->L-> ... ->L
  2573. ^ ^ ^
  2574. head last_linked_cmdbuf_node tail
  2575. */
  2576. static void vcmd_delink_cmdbuf(struct hantrovcmd_dev *dev,bi_list_node* last_linked_cmdbuf_node)
  2577. {
  2578. bi_list_node* new_cmdbuf_node=NULL;
  2579. struct cmdbuf_obj* cmdbuf_obj=NULL;
  2580. new_cmdbuf_node = last_linked_cmdbuf_node;
  2581. while(1)
  2582. {
  2583. if(new_cmdbuf_node==NULL)
  2584. break;
  2585. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  2586. if(cmdbuf_obj->cmdbuf_data_linked)
  2587. {
  2588. cmdbuf_obj->cmdbuf_data_linked = 0;
  2589. }
  2590. else
  2591. break;
  2592. new_cmdbuf_node = new_cmdbuf_node->next;
  2593. }
  2594. dev->sw_cmdbuf_rdy_num=0;
  2595. }
  2596. static void vcmd_start(struct hantrovcmd_dev *dev,bi_list_node* first_linked_cmdbuf_node)
  2597. {
  2598. struct cmdbuf_obj* cmdbuf_obj=NULL;
  2599. if(dev->working_state == WORKING_STATE_IDLE)
  2600. {
  2601. if((first_linked_cmdbuf_node!=NULL) && dev->sw_cmdbuf_rdy_num)
  2602. {
  2603. cmdbuf_obj = (struct cmdbuf_obj*)first_linked_cmdbuf_node->data;
  2604. printk_vcmd_register_debug((const void *)dev->hwregs, "vcmd_start enters");
  2605. //0x40
  2606. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_AXI_CLK_GATE_DISABLE,0);
  2607. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_MASTER_OUT_CLK_GATE_DISABLE,1);//this bit should be set 1 only when need to reset dec400
  2608. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_CORE_CLK_GATE_DISABLE,0);
  2609. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_ABORT_MODE,0);
  2610. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_RESET_CORE,0);
  2611. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_RESET_ALL,0);
  2612. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_START_TRIGGER,0);
  2613. //0x48
  2614. if(dev->hw_version_id <= HW_ID_1_0_C)
  2615. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_INTCMD_EN,0xffff);
  2616. else
  2617. {
  2618. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_JMPP_EN,1);
  2619. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_JMPD_EN,1);
  2620. }
  2621. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_RESET_EN,1);
  2622. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_ABORT_EN,1);
  2623. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_CMDERR_EN,1);
  2624. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_TIMEOUT_EN,1);
  2625. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_BUSERR_EN,1);
  2626. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_ENDCMD_EN,1);
  2627. //0x4c
  2628. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_TIMEOUT_EN,1);
  2629. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_TIMEOUT_CYCLES,0x1dcd6500);
  2630. if (mmu_enable) {
  2631. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR,(u32)(cmdbuf_obj->mmu_cmdbuf_busAddress));
  2632. if(sizeof(size_t) == 8) {
  2633. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR_MSB,(u32)((u64)(cmdbuf_obj->mmu_cmdbuf_busAddress)>>32));
  2634. } else {
  2635. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR_MSB, 0);
  2636. }
  2637. } else {
  2638. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR,(u32)(cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr));
  2639. if(sizeof(size_t) == 8) {
  2640. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR_MSB,(u32)((u64)(cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr)>>32));
  2641. } else {
  2642. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR_MSB, 0);
  2643. }
  2644. }
  2645. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_EXE_CMDBUF_LENGTH,(u32)((cmdbuf_obj->cmdbuf_size+7)/8));
  2646. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_RDY_CMDBUF_COUNT,dev->sw_cmdbuf_rdy_num);
  2647. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_MAX_BURST_LEN,0x10);
  2648. if(dev->hw_version_id > HW_ID_1_0_C )
  2649. {
  2650. vcmd_write_register_value((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_CMDBUF_EXECUTING_ID,(u32)cmdbuf_obj->cmdbuf_id);
  2651. }
  2652. vcmd_write_reg((const void *)dev->hwregs,0x40,dev->reg_mirror[0x40/4]);
  2653. vcmd_write_reg((const void *)dev->hwregs,0x44,vcmd_read_reg((const void *)dev->hwregs,0x44));
  2654. vcmd_write_reg((const void *)dev->hwregs,0x48,dev->reg_mirror[0x48/4]);
  2655. vcmd_write_reg((const void *)dev->hwregs,0x4c,dev->reg_mirror[0x4c/4]);
  2656. vcmd_write_reg((const void *)dev->hwregs,0x50,dev->reg_mirror[0x50/4]);
  2657. vcmd_write_reg((const void *)dev->hwregs,0x54,dev->reg_mirror[0x54/4]);
  2658. vcmd_write_reg((const void *)dev->hwregs,0x58,dev->reg_mirror[0x58/4]);
  2659. vcmd_write_reg((const void *)dev->hwregs,0x5c,dev->reg_mirror[0x5c/4]);
  2660. vcmd_write_reg((const void *)dev->hwregs,0x60,dev->reg_mirror[0x60/4]);
  2661. vcmd_write_reg((const void *)dev->hwregs,0x64,0xffffffff);//not interrupt cpu
  2662. dev->working_state = WORKING_STATE_WORKING;
  2663. //start
  2664. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_MASTER_OUT_CLK_GATE_DISABLE,0);//this bit should be set 1 only when need to reset dec400
  2665. vcmd_set_register_mirror_value(dev->reg_mirror,HWIF_VCMD_START_TRIGGER,1);
  2666. vcmd_write_reg((const void *)dev->hwregs,0x40,dev->reg_mirror[0x40/4]);
  2667. printk_vcmd_register_debug((const void *)dev->hwregs, "vcmd_start exits ");
  2668. }
  2669. }
  2670. }
  2671. static void create_read_all_registers_cmdbuf(struct exchange_parameter* input_para)
  2672. {
  2673. u32 register_range[]={VCMD_ENCODER_REGISTER_SIZE,
  2674. VCMD_IM_REGISTER_SIZE,
  2675. VCMD_DECODER_REGISTER_SIZE,
  2676. VCMD_JPEG_ENCODER_REGISTER_SIZE,
  2677. VCMD_JPEG_DECODER_REGISTER_SIZE};
  2678. u32 counter_cmdbuf_size=0;
  2679. u32 * set_base_addr=vcmd_buf_mem_pool.virtualAddress + input_para->cmdbuf_id*CMDBUF_MAX_SIZE/4;
  2680. //u32 *status_base_virt_addr=vcmd_status_buf_mem_pool.virtualAddress + input_para->cmdbuf_id*CMDBUF_MAX_SIZE/4+(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_main_addr/2/4+0);
  2681. ptr_t status_base_phy_addr=vcmd_status_buf_mem_pool.busAddress + input_para->cmdbuf_id*CMDBUF_MAX_SIZE+(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_main_addr/2+0);
  2682. u32 map_status_base_phy_addr=vcmd_status_buf_mem_pool.mmu_bus_address + input_para->cmdbuf_id*CMDBUF_MAX_SIZE+(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_main_addr/2+0);
  2683. u32 offset_inc=0;
  2684. if(vcmd_manager[input_para->module_type][0]->hw_version_id>HW_ID_1_0_C)
  2685. {
  2686. pr_info("vc8000_vcmd_driver:create cmdbuf data when hw_version_id = 0x%x\n",vcmd_manager[input_para->module_type][0]->hw_version_id);
  2687. //read vcmd executing cmdbuf id registers to ddr for balancing core load.
  2688. *(set_base_addr+0) = (OPCODE_RREG) |(1<<16) |(EXECUTING_CMDBUF_ID_ADDR*4);
  2689. counter_cmdbuf_size += 4;
  2690. *(set_base_addr+1) = (u32)0; //will be changed in link stage
  2691. counter_cmdbuf_size += 4;
  2692. *(set_base_addr+2) = (u32)0; //will be changed in link stage
  2693. counter_cmdbuf_size += 4;
  2694. //alignment
  2695. *(set_base_addr+3) = 0;
  2696. counter_cmdbuf_size += 4;
  2697. //read main IP all registers
  2698. *(set_base_addr+4) = (OPCODE_RREG) |((register_range[input_para->module_type]/4)<<16) |(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_main_addr+0);
  2699. counter_cmdbuf_size += 4;
  2700. if (mmu_enable) {
  2701. *(set_base_addr+5) = map_status_base_phy_addr;
  2702. } else {
  2703. *(set_base_addr+5) = (u32)(status_base_phy_addr-base_ddr_addr);
  2704. }
  2705. counter_cmdbuf_size += 4;
  2706. if (mmu_enable) {
  2707. *(set_base_addr+6) = 0;
  2708. } else {
  2709. if(sizeof(size_t) == 8) {
  2710. *(set_base_addr+6) = (u32)((u64)(status_base_phy_addr-base_ddr_addr)>>32);
  2711. } else {
  2712. *(set_base_addr+6) = 0;
  2713. }
  2714. }
  2715. counter_cmdbuf_size += 4;
  2716. //alignment
  2717. *(set_base_addr+7) = 0;
  2718. counter_cmdbuf_size += 4;
  2719. if(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_L2Cache_addr != 0xffff)
  2720. {
  2721. offset_inc = 4;
  2722. status_base_phy_addr=vcmd_status_buf_mem_pool.busAddress + input_para->cmdbuf_id*CMDBUF_MAX_SIZE+(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_L2Cache_addr/2+0);
  2723. map_status_base_phy_addr=vcmd_status_buf_mem_pool.mmu_bus_address + input_para->cmdbuf_id*CMDBUF_MAX_SIZE+(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_L2Cache_addr/2+0);
  2724. //read L2cache IP first register
  2725. *(set_base_addr+8) = (OPCODE_RREG) |(1<<16) |(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_L2Cache_addr+0);
  2726. counter_cmdbuf_size += 4;
  2727. if (mmu_enable) {
  2728. *(set_base_addr+9) = map_status_base_phy_addr;
  2729. } else {
  2730. *(set_base_addr+9) = (u32)(status_base_phy_addr-base_ddr_addr);
  2731. }
  2732. counter_cmdbuf_size += 4;
  2733. if (mmu_enable) {
  2734. *(set_base_addr+10) = 0;
  2735. } else {
  2736. if(sizeof(size_t) == 8) {
  2737. *(set_base_addr+10) = (u32)((u64)(status_base_phy_addr-base_ddr_addr)>>32);
  2738. } else {
  2739. *(set_base_addr+10) = 0;
  2740. }
  2741. }
  2742. counter_cmdbuf_size += 4;
  2743. //alignment
  2744. *(set_base_addr+11) = 0;
  2745. counter_cmdbuf_size += 4;
  2746. }
  2747. #if 0
  2748. //INT code, interrupt immediately
  2749. *(set_base_addr+4) = (OPCODE_INT) |0 |input_para->cmdbuf_id;
  2750. counter_cmdbuf_size += 4;
  2751. //alignment
  2752. *(set_base_addr+5) = 0;
  2753. counter_cmdbuf_size += 4;
  2754. #endif
  2755. //read vcmd registers to ddr
  2756. *(set_base_addr+8+offset_inc) = (OPCODE_RREG) |(27<<16) |(0);
  2757. counter_cmdbuf_size += 4;
  2758. *(set_base_addr+9+offset_inc) = (u32)0; //will be changed in link stage
  2759. counter_cmdbuf_size += 4;
  2760. *(set_base_addr+10+offset_inc) = (u32)0; //will be changed in link stage
  2761. counter_cmdbuf_size += 4;
  2762. //alignment
  2763. *(set_base_addr+11+offset_inc) = 0;
  2764. counter_cmdbuf_size += 4;
  2765. //JMP RDY = 0
  2766. *(set_base_addr +12+offset_inc)= (OPCODE_JMP_RDY0) |0 |JMP_IE_1|0;
  2767. counter_cmdbuf_size += 4;
  2768. *(set_base_addr +13+offset_inc) = 0;
  2769. counter_cmdbuf_size += 4;
  2770. *(set_base_addr +14+offset_inc) = 0;
  2771. counter_cmdbuf_size += 4;
  2772. *(set_base_addr +15+offset_inc) = input_para->cmdbuf_id;
  2773. //don't add the last alignment DWORD in order to identify END command or JMP command.
  2774. //counter_cmdbuf_size += 4;
  2775. input_para->cmdbuf_size=(16+offset_inc)*4;
  2776. }
  2777. else
  2778. {
  2779. pr_info("vc8000_vcmd_driver:create cmdbuf data when hw_version_id = 0x%x\n",vcmd_manager[input_para->module_type][0]->hw_version_id);
  2780. //read all registers
  2781. *(set_base_addr+0) = (OPCODE_RREG) |((register_range[input_para->module_type]/4)<<16) |(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_main_addr+0);
  2782. counter_cmdbuf_size += 4;
  2783. if (mmu_enable) {
  2784. *(set_base_addr+1) = map_status_base_phy_addr;
  2785. } else {
  2786. *(set_base_addr+1) = (u32)(status_base_phy_addr-base_ddr_addr);
  2787. }
  2788. counter_cmdbuf_size += 4;
  2789. if (mmu_enable) {
  2790. *(set_base_addr+2) = 0;
  2791. } else {
  2792. if(sizeof(size_t) == 8) {
  2793. *(set_base_addr+2) = (u32)((u64)(status_base_phy_addr-base_ddr_addr)>>32);
  2794. } else {
  2795. *(set_base_addr+2) = 0;
  2796. }
  2797. }
  2798. counter_cmdbuf_size += 4;
  2799. //alignment
  2800. *(set_base_addr+3) = 0;
  2801. counter_cmdbuf_size += 4;
  2802. #if 0
  2803. //INT code, interrupt immediately
  2804. *(set_base_addr+4) = (OPCODE_INT) |0 |input_para->cmdbuf_id;
  2805. counter_cmdbuf_size += 4;
  2806. //alignment
  2807. *(set_base_addr+5) = 0;
  2808. counter_cmdbuf_size += 4;
  2809. #endif
  2810. //JMP RDY = 0
  2811. *(set_base_addr +4)= (OPCODE_JMP_RDY0) |0 |JMP_IE_1|0;
  2812. counter_cmdbuf_size += 4;
  2813. *(set_base_addr +5) = 0;
  2814. counter_cmdbuf_size += 4;
  2815. *(set_base_addr +6) = 0;
  2816. counter_cmdbuf_size += 4;
  2817. *(set_base_addr +7) = input_para->cmdbuf_id;
  2818. //don't add the last alignment DWORD in order to identify END command or JMP command.
  2819. //counter_cmdbuf_size += 4;
  2820. input_para->cmdbuf_size=8*4;
  2821. }
  2822. }
  2823. static void read_main_module_all_registers(u32 main_module_type)
  2824. {
  2825. int ret;
  2826. struct exchange_parameter input_para;
  2827. u32 irq_status_ret=0;
  2828. u32 *status_base_virt_addr;
  2829. input_para.executing_time=0;
  2830. input_para.priority=CMDBUF_PRIORITY_NORMAL;
  2831. input_para.module_type = main_module_type;
  2832. input_para.cmdbuf_size=0;
  2833. ret = reserve_cmdbuf(NULL,&input_para);
  2834. vcmd_manager[main_module_type][0]->status_cmdbuf_id = input_para.cmdbuf_id;
  2835. create_read_all_registers_cmdbuf(&input_para);
  2836. link_and_run_cmdbuf(NULL,&input_para);
  2837. //msleep(1000);
  2838. hantrovcmd_isr(input_para.core_id, &hantrovcmd_data[input_para.core_id]);
  2839. wait_cmdbuf_ready(NULL,input_para.cmdbuf_id,&irq_status_ret);
  2840. status_base_virt_addr=vcmd_status_buf_mem_pool.virtualAddress + input_para.cmdbuf_id*CMDBUF_MAX_SIZE/4+(vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_main_addr/2/4+0);
  2841. pr_info("vc8000_vcmd_driver: main module register 0:0x%x\n",*status_base_virt_addr);
  2842. pr_info("vc8000_vcmd_driver: main module register 50:0x%08x\n",*(status_base_virt_addr+50));
  2843. pr_info("vc8000_vcmd_driver: main module register 54:0x%08x\n",*(status_base_virt_addr+54));
  2844. pr_info("vc8000_vcmd_driver: main module register 56:0x%08x\n",*(status_base_virt_addr+56));
  2845. pr_info("vc8000_vcmd_driver: main module register 309:0x%x\n",*(status_base_virt_addr+309));
  2846. //don't release cmdbuf because it can be used repeatedly
  2847. //release_cmdbuf(input_para.cmdbuf_id);
  2848. }
  2849. int hantrovcmd_init(struct platform_device *pdev)
  2850. {
  2851. int i,k;
  2852. int result;
  2853. struct kernel_addr_desc addr;
  2854. //total_vcmd_core_num = sizeof(vcmd_core_array)/sizeof(struct vcmd_config);
  2855. result = vcmd_init(pdev);
  2856. if(result)
  2857. goto err;
  2858. for (i = 0; i< total_vcmd_core_num; i++)
  2859. {
  2860. pr_info("vcmd: module init - vcmdcore[%d] addr =0x%llx\n",i,
  2861. (long long unsigned int)vcmd_core_array[i].vcmd_base_addr);
  2862. }
  2863. hantrovcmd_data = (struct hantrovcmd_dev *)vmalloc(sizeof(struct hantrovcmd_dev)*total_vcmd_core_num);
  2864. if (hantrovcmd_data == NULL)
  2865. goto err;
  2866. memset(hantrovcmd_data,0,sizeof(struct hantrovcmd_dev)*total_vcmd_core_num);
  2867. hantrovcmd_data[0].pdev = pdev;
  2868. for(k=0;k<MAX_VCMD_TYPE;k++)
  2869. {
  2870. vcmd_type_core_num[k]=0;
  2871. vcmd_position[k]=0;
  2872. for(i=0;i<MAX_VCMD_NUMBER;i++)
  2873. {
  2874. vcmd_manager[k][i]=NULL;
  2875. }
  2876. }
  2877. init_bi_list(&global_process_manager);
  2878. for(i=0;i<total_vcmd_core_num;i++)
  2879. {
  2880. hantrovcmd_data[i].vcmd_core_cfg = vcmd_core_array[i];
  2881. hantrovcmd_data[i].hwregs = NULL;
  2882. hantrovcmd_data[i].core_id = i;
  2883. hantrovcmd_data[i].working_state= WORKING_STATE_IDLE;
  2884. hantrovcmd_data[i].sw_cmdbuf_rdy_num =0;
  2885. hantrovcmd_data[i].spinlock = &owner_lock_vcmd[i];
  2886. spin_lock_init(&owner_lock_vcmd[i]);
  2887. hantrovcmd_data[i].wait_queue = &wait_queue_vcmd[i];
  2888. init_waitqueue_head(&wait_queue_vcmd[i]);
  2889. hantrovcmd_data[i].wait_abort_queue=&abort_queue_vcmd[i];
  2890. init_waitqueue_head(&abort_queue_vcmd[i]);
  2891. init_bi_list(&hantrovcmd_data[i].list_manager);
  2892. hantrovcmd_data[i].duration_without_int = 0;
  2893. vcmd_manager[vcmd_core_array[i].sub_module_type][vcmd_type_core_num[vcmd_core_array[i].sub_module_type]]=&hantrovcmd_data[i];
  2894. vcmd_type_core_num[vcmd_core_array[i].sub_module_type]++;
  2895. hantrovcmd_data[i].vcmd_reg_mem_busAddress = vcmd_registers_mem_pool.busAddress + i*VCMD_REGISTER_SIZE-base_ddr_addr;
  2896. hantrovcmd_data[i].mmu_vcmd_reg_mem_busAddress = vcmd_registers_mem_pool.mmu_bus_address + i*VCMD_REGISTER_SIZE;
  2897. hantrovcmd_data[i].vcmd_reg_mem_virtualAddress = vcmd_registers_mem_pool.virtualAddress + i*VCMD_REGISTER_SIZE/4;
  2898. hantrovcmd_data[i].vcmd_reg_mem_size = VCMD_REGISTER_SIZE;
  2899. memset(hantrovcmd_data[i].vcmd_reg_mem_virtualAddress,0,VCMD_REGISTER_SIZE);
  2900. }
  2901. init_waitqueue_head(&mc_wait_queue);
  2902. #if 0
  2903. result = register_chrdev(hantrovcmd_major, "hantrodec", &hantrovcmd_fops);
  2904. if(result < 0)
  2905. {
  2906. pr_info("vc8000_vcmd_driver: unable to get major <%d>\n",
  2907. hantrovcmd_major);
  2908. goto err1;
  2909. }
  2910. else if(result != 0) /* this is for dynamic major */
  2911. {
  2912. hantrovcmd_major = result;
  2913. }
  2914. #endif
  2915. result = vcmd_reserve_IO();
  2916. if(result < 0)
  2917. {
  2918. goto err;
  2919. }
  2920. vcmd_reset_asic(hantrovcmd_data);
  2921. hantrovcmd_data[0].vcmd_core_cfg.vcmd_irq = platform_get_irq(pdev, 0);
  2922. pr_info("%s:get irq %d\n",__func__,hantrovcmd_data[0].vcmd_core_cfg.vcmd_irq);
  2923. /* get the IRQ line */
  2924. for (i=0;i<total_vcmd_core_num;i++)
  2925. {
  2926. if (hantrovcmd_data[i].hwregs==NULL)
  2927. continue;
  2928. #ifdef VCMD_DEBUG_INTERNAL
  2929. {
  2930. u32 j, fordebug;
  2931. for(j=0;j<ASIC_VCMD_SWREG_AMOUNT;j++)
  2932. {
  2933. fordebug=vcmd_read_reg ((const void *)hantrovcmd_data[i].hwregs, j*4);
  2934. pr_info("vcmd register %d:0x%x\n",j,fordebug);
  2935. }
  2936. }
  2937. #endif
  2938. if(hantrovcmd_data[i].vcmd_core_cfg.vcmd_irq!= -1)
  2939. {
  2940. result = request_irq(hantrovcmd_data[i].vcmd_core_cfg.vcmd_irq, hantrovcmd_isr,
  2941. #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18))
  2942. SA_INTERRUPT | SA_SHIRQ,
  2943. #else
  2944. IRQF_SHARED,
  2945. #endif
  2946. "vc8000_vcmd_driver", (void *) &hantrovcmd_data[i]);
  2947. if(result == -EINVAL)
  2948. {
  2949. pr_err("vc8000_vcmd_driver: Bad vcmd_irq number or handler. core_id=%d\n",i);
  2950. vcmd_release_IO();
  2951. goto err;
  2952. }
  2953. else if(result == -EBUSY)
  2954. {
  2955. pr_err("vc8000_vcmd_driver: IRQ <%d> busy, change your config. core_id=%d\n",
  2956. hantrovcmd_data[i].vcmd_core_cfg.vcmd_irq,i);
  2957. vcmd_release_IO();
  2958. goto err;
  2959. } else {
  2960. pr_info("vc8000_vcmd_driver: request IRQ <%d> successfully for subsystem %d\n",
  2961. hantrovcmd_data[i].vcmd_core_cfg.vcmd_irq, i);
  2962. }
  2963. }
  2964. else
  2965. {
  2966. pr_info("vc8000_vcmd_driver: IRQ not in use!\n");
  2967. }
  2968. }
  2969. //cmdbuf pool allocation
  2970. //init_vcmd_non_cachable_memory_allocate();
  2971. //for cmdbuf management
  2972. cmdbuf_used_pos=0;
  2973. for(k=0;k<TOTAL_DISCRETE_CMDBUF_NUM;k++)
  2974. {
  2975. cmdbuf_used[k]=0;
  2976. global_cmdbuf_node[k] = NULL;
  2977. }
  2978. //cmdbuf_used[0] not be used, because int vector must non-zero
  2979. cmdbuf_used_residual=TOTAL_DISCRETE_CMDBUF_NUM;
  2980. cmdbuf_used_pos=1;
  2981. cmdbuf_used[0]=1;
  2982. cmdbuf_used_residual -=1;
  2983. create_kernel_process_manager();
  2984. for(i=0;i<MAX_VCMD_TYPE;i++)
  2985. {
  2986. if(vcmd_type_core_num[i]==0)
  2987. continue;
  2988. sema_init(&vcmd_reserve_cmdbuf_sem[i], 1);
  2989. }
  2990. #ifdef IRQ_SIMULATION
  2991. for(i=0;i<10000;i++)
  2992. {
  2993. timer_reserve[i].timer=NULL;
  2994. }
  2995. #endif
  2996. #ifndef DYNAMIC_MALLOC_VCMDNODE
  2997. g_cmdbuf_obj_pool = vmalloc(sizeof(struct cmdbuf_obj) * TOTAL_DISCRETE_CMDBUF_NUM);
  2998. g_cmdbuf_node_pool = vmalloc(sizeof(bi_list_node) * TOTAL_DISCRETE_CMDBUF_NUM);
  2999. #endif
  3000. /*read all registers for each type of module for analyzing configuration in cwl*/
  3001. for(i=0;i<MAX_VCMD_TYPE;i++)
  3002. {
  3003. if(vcmd_type_core_num[i]==0)
  3004. continue;
  3005. read_main_module_all_registers(i);
  3006. }
  3007. return 0;
  3008. err:
  3009. if (vcmd_buf_mem_pool.virtualAddress) {
  3010. if (mmu_enable) {
  3011. addr.bus_address = vcmd_buf_mem_pool.busAddress;
  3012. addr.size = vcmd_buf_mem_pool.size;
  3013. MMUKernelMemNodeUnmap(&addr);
  3014. }
  3015. dma_free_coherent(&pdev->dev, CMDBUF_POOL_TOTAL_SIZE*2 + CMDBUF_VCMD_REGISTER_TOTAL_SIZE,
  3016. vcmd_buf_mem_pool.virtualAddress, vcmd_buf_mem_pool.busAddress);
  3017. }
  3018. if (vcmd_status_buf_mem_pool.virtualAddress) {
  3019. if (mmu_enable) {
  3020. addr.bus_address = vcmd_status_buf_mem_pool.busAddress;
  3021. addr.size = vcmd_status_buf_mem_pool.size;
  3022. MMUKernelMemNodeUnmap(&addr);
  3023. }
  3024. }
  3025. if (vcmd_registers_mem_pool.virtualAddress) {
  3026. if (mmu_enable) {
  3027. addr.bus_address = vcmd_registers_mem_pool.busAddress;
  3028. addr.size = vcmd_registers_mem_pool.size;
  3029. MMUKernelMemNodeUnmap(&addr);
  3030. }
  3031. }
  3032. if (hantrovcmd_data != NULL)
  3033. vfree(hantrovcmd_data);
  3034. pr_info("vc8000_vcmd_driver: module not inserted\n");
  3035. return result;
  3036. }
  3037. void hantrovcmd_cleanup(struct platform_device *pdev)
  3038. {
  3039. int i=0;
  3040. u32 result;
  3041. for(i=0;i<total_vcmd_core_num;i++)
  3042. {
  3043. if (hantrovcmd_data[i].hwregs==NULL)
  3044. continue;
  3045. //disable interrupt at first
  3046. vcmd_write_reg((const void *) hantrovcmd_data[i].hwregs,VCMD_REGISTER_INT_CTL_OFFSET,0x0000);
  3047. //disable HW
  3048. vcmd_write_reg((const void *) hantrovcmd_data[i].hwregs,VCMD_REGISTER_CONTROL_OFFSET,0x0000);
  3049. //read status register
  3050. result =vcmd_read_reg((const void *) hantrovcmd_data[i].hwregs,VCMD_REGISTER_INT_STATUS_OFFSET);
  3051. //clean status register
  3052. vcmd_write_reg((const void *) hantrovcmd_data[i].hwregs,VCMD_REGISTER_INT_STATUS_OFFSET,result);
  3053. /* free the vcmd IRQ */
  3054. if(hantrovcmd_data[i].vcmd_core_cfg.vcmd_irq != -1)
  3055. {
  3056. free_irq(hantrovcmd_data[i].vcmd_core_cfg.vcmd_irq, (void *)&hantrovcmd_data[i]);
  3057. }
  3058. release_cmdbuf_node_cleanup(&hantrovcmd_data[i].list_manager);
  3059. }
  3060. release_process_node_cleanup(&global_process_manager);
  3061. vcmd_release_IO();
  3062. vfree(hantrovcmd_data);
  3063. dma_free_coherent(&pdev->dev, CMDBUF_POOL_TOTAL_SIZE*2 + CMDBUF_VCMD_REGISTER_TOTAL_SIZE,
  3064. vcmd_buf_mem_pool.virtualAddress, vcmd_buf_mem_pool.busAddress);
  3065. #ifndef DYNAMIC_MALLOC_VCMDNODE
  3066. if (g_cmdbuf_obj_pool) {
  3067. vfree(g_cmdbuf_obj_pool);
  3068. g_cmdbuf_obj_pool = NULL;
  3069. }
  3070. if (g_cmdbuf_node_pool) {
  3071. vfree(g_cmdbuf_node_pool);
  3072. g_cmdbuf_node_pool = NULL;
  3073. }
  3074. #endif
  3075. pr_info("vc8000_vcmd_driver: module removed\n");
  3076. return;
  3077. }
  3078. static int vcmd_reserve_IO(void)
  3079. {
  3080. u32 hwid;
  3081. int i;
  3082. u32 found_hw = 0;
  3083. for (i=0;i<total_vcmd_core_num;i++)
  3084. {
  3085. hantrovcmd_data[i].hwregs = NULL;
  3086. if(!request_mem_region
  3087. (hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr, hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize, "vc8000_vcmd_driver"))
  3088. {
  3089. pr_info("hantrovcmd: failed to reserve HW regs for vcmd %d\n", i);
  3090. pr_info("hantrovcmd: vcmd_base_addr = 0x%08lx, iosize = %d\n",
  3091. hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr,
  3092. hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize);
  3093. continue;
  3094. }
  3095. #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,17,0))
  3096. hantrovcmd_data[i].hwregs =
  3097. (volatile u8 *) ioremap_nocache(hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr,
  3098. hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize);
  3099. #else
  3100. hantrovcmd_data[i].hwregs =
  3101. (volatile u8 *) ioremap(hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr,
  3102. hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize);
  3103. #endif
  3104. if(hantrovcmd_data[i].hwregs == NULL)
  3105. {
  3106. pr_info("hantrovcmd: failed to ioremap HW regs\n");
  3107. release_mem_region(hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr, hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize);
  3108. continue;
  3109. }
  3110. /*read hwid and check validness and store it*/
  3111. hwid = (u32)ioread32(( void *)hantrovcmd_data[i].hwregs);
  3112. pr_info("hwid=0x%08x\n", hwid);
  3113. hantrovcmd_data[i].hw_version_id = hwid;
  3114. /* check for vcmd HW ID */
  3115. if( ((hwid >> 16) & 0xFFFF) != VCMD_HW_ID )
  3116. {
  3117. pr_info("hantrovcmd: HW not found at 0x%llx\n",
  3118. (long long unsigned int)hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr);
  3119. iounmap(( void *) hantrovcmd_data[i].hwregs);
  3120. release_mem_region(hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr, hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize);
  3121. hantrovcmd_data[i].hwregs = NULL;
  3122. continue;
  3123. }
  3124. found_hw = 1;
  3125. pr_info(
  3126. "hantrovcmd: HW at base <0x%llx> with ID <0x%08x>\n",
  3127. (long long unsigned int)hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr, hwid);
  3128. }
  3129. if (found_hw == 0)
  3130. {
  3131. pr_err("hantrovcmd: NO ANY HW found!!\n");
  3132. return -1;
  3133. }
  3134. return 0;
  3135. }
  3136. static void vcmd_release_IO(void)
  3137. {
  3138. u32 i;
  3139. for (i=0;i<total_vcmd_core_num;i++)
  3140. {
  3141. if(hantrovcmd_data[i].hwregs)
  3142. {
  3143. iounmap((void *) hantrovcmd_data[i].hwregs);
  3144. release_mem_region(hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr, hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize);
  3145. hantrovcmd_data[i].hwregs = NULL;
  3146. }
  3147. }
  3148. }
  3149. #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18))
  3150. static irqreturn_t hantrovcmd_isr(int irq, void *dev_id, struct pt_regs *regs)
  3151. #else
  3152. static irqreturn_t hantrovcmd_isr(int irq, void *dev_id)
  3153. #endif
  3154. {
  3155. unsigned int handled = 0;
  3156. struct hantrovcmd_dev *dev = (struct hantrovcmd_dev *) dev_id;
  3157. u32 irq_status=0;
  3158. unsigned long flags;
  3159. bi_list_node* new_cmdbuf_node=NULL;
  3160. bi_list_node* base_cmdbuf_node=NULL;
  3161. struct cmdbuf_obj* cmdbuf_obj=NULL;
  3162. size_t exe_cmdbuf_busAddress;
  3163. u32 cmdbuf_processed_num=0;
  3164. u32 cmdbuf_id=0;
  3165. static u32 count = 0;
  3166. /*If core is not reserved by any user, but irq is received, just clean it*/
  3167. spin_lock_irqsave(dev->spinlock, flags);
  3168. if (dev->list_manager.head==NULL)
  3169. {
  3170. u32 irq_status1=0;
  3171. if (count % 100000 == 0)
  3172. PDEBUG( "hantrovcmd_isr:received IRQ but core has nothing to do.\n");
  3173. irq_status = vcmd_read_reg((const void *)dev->hwregs,VCMD_REGISTER_INT_STATUS_OFFSET);
  3174. vcmd_write_reg((const void *)dev->hwregs,VCMD_REGISTER_INT_STATUS_OFFSET,irq_status);
  3175. spin_unlock_irqrestore(dev->spinlock, flags);
  3176. irq_status1 = vcmd_read_reg((const void *)dev->hwregs,VCMD_REGISTER_INT_STATUS_OFFSET);
  3177. if (count++ % 100000 == 0)
  3178. PDEBUG( "hantrovcmd_isr: irq status 0x%x -> 0x%x\n", irq_status, irq_status1);
  3179. return IRQ_HANDLED;
  3180. }
  3181. PDEBUG( "hantrovcmd_isr:received IRQ!\n");
  3182. irq_status = vcmd_read_reg((const void *)dev->hwregs,VCMD_REGISTER_INT_STATUS_OFFSET);
  3183. #ifdef VCMD_DEBUG_INTERNAL
  3184. {
  3185. u32 i, fordebug;
  3186. for(i=0;i<ASIC_VCMD_SWREG_AMOUNT;i++)
  3187. {
  3188. fordebug=vcmd_read_reg ((const void *)dev->hwregs, i*4);
  3189. pr_info("vcmd register %d:0x%x\n",i,fordebug);
  3190. }
  3191. }
  3192. #endif
  3193. if(!irq_status)
  3194. {
  3195. //pr_info("hantrovcmd_isr error,irq_status :0x%x",irq_status);
  3196. spin_unlock_irqrestore(dev->spinlock, flags);
  3197. return IRQ_HANDLED;
  3198. }
  3199. PDEBUG( "irq_status of %d is:%x\n",dev->core_id,irq_status);
  3200. vcmd_write_reg((const void *)dev->hwregs,VCMD_REGISTER_INT_STATUS_OFFSET,irq_status);
  3201. dev->reg_mirror[VCMD_REGISTER_INT_STATUS_OFFSET/4] = irq_status;
  3202. if((dev->hw_version_id > HW_ID_1_0_C )&&(irq_status&0x3f))
  3203. {
  3204. //if error,read from register directly.
  3205. cmdbuf_id = vcmd_get_register_value((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_CMDBUF_EXECUTING_ID);
  3206. if(cmdbuf_id>=TOTAL_DISCRETE_CMDBUF_NUM)
  3207. {
  3208. pr_err("hantrovcmd_isr error cmdbuf_id greater than the ceiling !!\n");
  3209. spin_unlock_irqrestore(dev->spinlock, flags);
  3210. return IRQ_HANDLED;
  3211. }
  3212. }
  3213. else if((dev->hw_version_id > HW_ID_1_0_C ))
  3214. {
  3215. //read cmdbuf id from ddr
  3216. #ifdef VCMD_DEBUG_INTERNAL
  3217. {
  3218. u32 i, fordebug;
  3219. pr_info("ddr vcmd register phy_addr=0x%x\n",dev->vcmd_reg_mem_busAddress);
  3220. pr_info("ddr vcmd register virt_addr=0x%x\n",dev->vcmd_reg_mem_virtualAddress);
  3221. for(i=0;i<ASIC_VCMD_SWREG_AMOUNT;i++)
  3222. {
  3223. fordebug=*(dev->vcmd_reg_mem_virtualAddress+i);
  3224. pr_info("ddr vcmd register %d:0x%x\n",i,fordebug);
  3225. }
  3226. }
  3227. #endif
  3228. cmdbuf_id = *(dev->vcmd_reg_mem_virtualAddress+EXECUTING_CMDBUF_ID_ADDR);
  3229. if(cmdbuf_id>=TOTAL_DISCRETE_CMDBUF_NUM)
  3230. {
  3231. pr_err("hantrovcmd_isr error cmdbuf_id greater than the ceiling !!\n");
  3232. spin_unlock_irqrestore(dev->spinlock, flags);
  3233. return IRQ_HANDLED;
  3234. }
  3235. }
  3236. if(vcmd_get_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_RESET))
  3237. {
  3238. //reset error,all cmdbuf that is not done will be run again.
  3239. new_cmdbuf_node = dev->list_manager.head;
  3240. dev->working_state = WORKING_STATE_IDLE;
  3241. //find the first run_done=0
  3242. while(1)
  3243. {
  3244. if(new_cmdbuf_node==NULL)
  3245. break;
  3246. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3247. if((cmdbuf_obj->cmdbuf_run_done == 0))
  3248. break;
  3249. new_cmdbuf_node = new_cmdbuf_node->next;
  3250. }
  3251. base_cmdbuf_node = new_cmdbuf_node;
  3252. vcmd_delink_cmdbuf(dev,base_cmdbuf_node);
  3253. vcmd_link_cmdbuf(dev,base_cmdbuf_node);
  3254. if(dev->sw_cmdbuf_rdy_num !=0)
  3255. {
  3256. //restart new command
  3257. vcmd_start(dev,base_cmdbuf_node);
  3258. }
  3259. handled++;
  3260. spin_unlock_irqrestore(dev->spinlock, flags);
  3261. return IRQ_HANDLED;
  3262. }
  3263. if(vcmd_get_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_ABORT))
  3264. {
  3265. //abort error,don't need to reset
  3266. new_cmdbuf_node = dev->list_manager.head;
  3267. dev->working_state = WORKING_STATE_IDLE;
  3268. if(dev->hw_version_id > HW_ID_1_0_C )
  3269. {
  3270. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  3271. if(new_cmdbuf_node==NULL)
  3272. {
  3273. pr_err("hantrovcmd_isr error cmdbuf_id !!\n");
  3274. spin_unlock_irqrestore(dev->spinlock, flags);
  3275. return IRQ_HANDLED;
  3276. }
  3277. }
  3278. else
  3279. {
  3280. exe_cmdbuf_busAddress = VCMDGetAddrRegisterValue((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR);
  3281. //find the cmdbuf that triggers ABORT
  3282. while(1)
  3283. {
  3284. if(new_cmdbuf_node==NULL)
  3285. {
  3286. spin_unlock_irqrestore(dev->spinlock, flags);
  3287. return IRQ_HANDLED;
  3288. }
  3289. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3290. if((((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr) <=exe_cmdbuf_busAddress)&&(((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr+cmdbuf_obj->cmdbuf_size) >exe_cmdbuf_busAddress)) ) &&(cmdbuf_obj->cmdbuf_run_done==0))
  3291. break;
  3292. new_cmdbuf_node = new_cmdbuf_node->next;
  3293. }
  3294. }
  3295. base_cmdbuf_node = new_cmdbuf_node;
  3296. // this cmdbuf and cmdbufs prior to itself, run_done = 1
  3297. while(1)
  3298. {
  3299. if(new_cmdbuf_node==NULL)
  3300. break;
  3301. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3302. if((cmdbuf_obj->cmdbuf_run_done==0))
  3303. {
  3304. cmdbuf_obj->cmdbuf_run_done=1;
  3305. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  3306. cmdbuf_processed_num++;
  3307. }
  3308. else
  3309. break;
  3310. new_cmdbuf_node = new_cmdbuf_node->previous;
  3311. }
  3312. base_cmdbuf_node=base_cmdbuf_node->next;
  3313. vcmd_delink_cmdbuf(dev,base_cmdbuf_node);
  3314. spin_unlock_irqrestore(dev->spinlock, flags);
  3315. if(cmdbuf_processed_num)
  3316. wake_up_interruptible_all(dev->wait_queue);
  3317. //to let high priority cmdbuf be inserted
  3318. wake_up_interruptible_all(dev->wait_abort_queue);
  3319. wake_up_interruptible_all(&mc_wait_queue);
  3320. handled++;
  3321. return IRQ_HANDLED;
  3322. }
  3323. if(vcmd_get_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_BUSERR))
  3324. {
  3325. //bus error, don't need to reset where to record status?
  3326. new_cmdbuf_node = dev->list_manager.head;
  3327. dev->working_state = WORKING_STATE_IDLE;
  3328. if(dev->hw_version_id > HW_ID_1_0_C )
  3329. {
  3330. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  3331. if(new_cmdbuf_node==NULL)
  3332. {
  3333. pr_err("hantrovcmd_isr error cmdbuf_id !!\n");
  3334. spin_unlock_irqrestore(dev->spinlock, flags);
  3335. return IRQ_HANDLED;
  3336. }
  3337. }
  3338. else
  3339. {
  3340. exe_cmdbuf_busAddress = VCMDGetAddrRegisterValue((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR);
  3341. //find the buserr cmdbuf
  3342. while(1)
  3343. {
  3344. if(new_cmdbuf_node==NULL)
  3345. {
  3346. spin_unlock_irqrestore(dev->spinlock, flags);
  3347. return IRQ_HANDLED;
  3348. }
  3349. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3350. if((((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr) <=exe_cmdbuf_busAddress)&&(((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr+cmdbuf_obj->cmdbuf_size) >exe_cmdbuf_busAddress)) ) &&(cmdbuf_obj->cmdbuf_run_done==0))
  3351. break;
  3352. new_cmdbuf_node = new_cmdbuf_node->next;
  3353. }
  3354. }
  3355. base_cmdbuf_node = new_cmdbuf_node;
  3356. // this cmdbuf and cmdbufs prior to itself, run_done = 1
  3357. while(1)
  3358. {
  3359. if(new_cmdbuf_node==NULL)
  3360. break;
  3361. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3362. if((cmdbuf_obj->cmdbuf_run_done==0))
  3363. {
  3364. cmdbuf_obj->cmdbuf_run_done=1;
  3365. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  3366. cmdbuf_processed_num++;
  3367. }
  3368. else
  3369. break;
  3370. new_cmdbuf_node = new_cmdbuf_node->previous;
  3371. }
  3372. new_cmdbuf_node = base_cmdbuf_node;
  3373. if(new_cmdbuf_node!=NULL)
  3374. {
  3375. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3376. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_BUSERR;
  3377. }
  3378. base_cmdbuf_node=base_cmdbuf_node->next;
  3379. vcmd_delink_cmdbuf(dev,base_cmdbuf_node);
  3380. vcmd_link_cmdbuf(dev,base_cmdbuf_node);
  3381. if(dev->sw_cmdbuf_rdy_num !=0)
  3382. {
  3383. //restart new command
  3384. vcmd_start(dev,base_cmdbuf_node);
  3385. }
  3386. spin_unlock_irqrestore(dev->spinlock, flags);
  3387. if(cmdbuf_processed_num)
  3388. wake_up_interruptible_all(dev->wait_queue);
  3389. handled++;
  3390. wake_up_interruptible_all(&mc_wait_queue);
  3391. return IRQ_HANDLED;
  3392. }
  3393. if(vcmd_get_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_TIMEOUT))
  3394. {
  3395. //time out,need to reset
  3396. new_cmdbuf_node = dev->list_manager.head;
  3397. dev->working_state = WORKING_STATE_IDLE;
  3398. if(dev->hw_version_id > HW_ID_1_0_C )
  3399. {
  3400. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  3401. if(new_cmdbuf_node==NULL)
  3402. {
  3403. pr_err("hantrovcmd_isr error cmdbuf_id !!\n");
  3404. spin_unlock_irqrestore(dev->spinlock, flags);
  3405. return IRQ_HANDLED;
  3406. }
  3407. }
  3408. else
  3409. {
  3410. exe_cmdbuf_busAddress = VCMDGetAddrRegisterValue((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR);
  3411. //find the timeout cmdbuf
  3412. while(1)
  3413. {
  3414. if(new_cmdbuf_node==NULL)
  3415. {
  3416. spin_unlock_irqrestore(dev->spinlock, flags);
  3417. return IRQ_HANDLED;
  3418. }
  3419. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3420. if((((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr) <=exe_cmdbuf_busAddress)&&(((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr+cmdbuf_obj->cmdbuf_size) >exe_cmdbuf_busAddress)) ) &&(cmdbuf_obj->cmdbuf_run_done==0))
  3421. break;
  3422. new_cmdbuf_node = new_cmdbuf_node->next;
  3423. }
  3424. }
  3425. base_cmdbuf_node = new_cmdbuf_node;
  3426. new_cmdbuf_node = new_cmdbuf_node->previous;
  3427. // this cmdbuf and cmdbufs prior to itself, run_done = 1
  3428. while(1)
  3429. {
  3430. if(new_cmdbuf_node==NULL)
  3431. break;
  3432. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3433. if((cmdbuf_obj->cmdbuf_run_done==0))
  3434. {
  3435. cmdbuf_obj->cmdbuf_run_done=1;
  3436. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  3437. cmdbuf_processed_num++;
  3438. }
  3439. else
  3440. break;
  3441. new_cmdbuf_node = new_cmdbuf_node->previous;
  3442. }
  3443. vcmd_delink_cmdbuf(dev,base_cmdbuf_node);
  3444. vcmd_link_cmdbuf(dev,base_cmdbuf_node);
  3445. if(dev->sw_cmdbuf_rdy_num !=0)
  3446. {
  3447. //reset
  3448. vcmd_reset_current_asic(dev);
  3449. //restart new command
  3450. vcmd_start(dev,base_cmdbuf_node);
  3451. }
  3452. spin_unlock_irqrestore(dev->spinlock, flags);
  3453. if(cmdbuf_processed_num)
  3454. wake_up_interruptible_all(dev->wait_queue);
  3455. handled++;
  3456. wake_up_interruptible_all(&mc_wait_queue);
  3457. return IRQ_HANDLED;
  3458. }
  3459. if(vcmd_get_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_CMDERR))
  3460. {
  3461. //command error,don't need to reset
  3462. new_cmdbuf_node = dev->list_manager.head;
  3463. dev->working_state = WORKING_STATE_IDLE;
  3464. if(dev->hw_version_id > HW_ID_1_0_C )
  3465. {
  3466. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  3467. if(new_cmdbuf_node==NULL)
  3468. {
  3469. pr_err("hantrovcmd_isr error cmdbuf_id !!\n");
  3470. spin_unlock_irqrestore(dev->spinlock, flags);
  3471. return IRQ_HANDLED;
  3472. }
  3473. }
  3474. else
  3475. {
  3476. exe_cmdbuf_busAddress = VCMDGetAddrRegisterValue((const void *)dev->hwregs,dev->reg_mirror,HWIF_VCMD_EXECUTING_CMD_ADDR);
  3477. //find the cmderror cmdbuf
  3478. while(1)
  3479. {
  3480. if(new_cmdbuf_node==NULL)
  3481. {
  3482. spin_unlock_irqrestore(dev->spinlock, flags);
  3483. return IRQ_HANDLED;
  3484. }
  3485. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3486. if((((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr) <=exe_cmdbuf_busAddress)&&(((cmdbuf_obj->cmdbuf_busAddress-base_ddr_addr+cmdbuf_obj->cmdbuf_size) >exe_cmdbuf_busAddress)) ) &&(cmdbuf_obj->cmdbuf_run_done==0))
  3487. break;
  3488. new_cmdbuf_node = new_cmdbuf_node->next;
  3489. }
  3490. }
  3491. base_cmdbuf_node = new_cmdbuf_node;
  3492. // this cmdbuf and cmdbufs prior to itself, run_done = 1
  3493. while(1)
  3494. {
  3495. if(new_cmdbuf_node==NULL)
  3496. break;
  3497. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3498. if((cmdbuf_obj->cmdbuf_run_done==0))
  3499. {
  3500. cmdbuf_obj->cmdbuf_run_done=1;
  3501. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  3502. cmdbuf_processed_num++;
  3503. }
  3504. else
  3505. break;
  3506. new_cmdbuf_node = new_cmdbuf_node->previous;
  3507. }
  3508. new_cmdbuf_node = base_cmdbuf_node;
  3509. if(new_cmdbuf_node!=NULL)
  3510. {
  3511. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3512. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_CMDERR;//cmderr
  3513. }
  3514. base_cmdbuf_node=base_cmdbuf_node->next;
  3515. vcmd_delink_cmdbuf(dev,base_cmdbuf_node);
  3516. vcmd_link_cmdbuf(dev,base_cmdbuf_node);
  3517. if(dev->sw_cmdbuf_rdy_num !=0)
  3518. {
  3519. //restart new command
  3520. vcmd_start(dev,base_cmdbuf_node);
  3521. }
  3522. spin_unlock_irqrestore(dev->spinlock, flags);
  3523. if(cmdbuf_processed_num)
  3524. wake_up_interruptible_all(dev->wait_queue);
  3525. handled++;
  3526. wake_up_interruptible_all(&mc_wait_queue);
  3527. return IRQ_HANDLED;
  3528. }
  3529. if(vcmd_get_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_ENDCMD))
  3530. {
  3531. //end command interrupt
  3532. new_cmdbuf_node = dev->list_manager.head;
  3533. dev->working_state = WORKING_STATE_IDLE;
  3534. if(dev->hw_version_id > HW_ID_1_0_C )
  3535. {
  3536. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  3537. if(new_cmdbuf_node==NULL)
  3538. {
  3539. pr_err("hantrovcmd_isr error cmdbuf_id !!\n");
  3540. spin_unlock_irqrestore(dev->spinlock, flags);
  3541. return IRQ_HANDLED;
  3542. }
  3543. }
  3544. else
  3545. {
  3546. //find the end cmdbuf
  3547. while(1)
  3548. {
  3549. if(new_cmdbuf_node==NULL)
  3550. {
  3551. spin_unlock_irqrestore(dev->spinlock, flags);
  3552. return IRQ_HANDLED;
  3553. }
  3554. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3555. if((cmdbuf_obj->has_end_cmdbuf == 1)&&(cmdbuf_obj->cmdbuf_run_done==0))
  3556. break;
  3557. new_cmdbuf_node = new_cmdbuf_node->next;
  3558. }
  3559. }
  3560. base_cmdbuf_node = new_cmdbuf_node;
  3561. // this cmdbuf and cmdbufs prior to itself, run_done = 1
  3562. while(1)
  3563. {
  3564. if(new_cmdbuf_node==NULL)
  3565. break;
  3566. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3567. if((cmdbuf_obj->cmdbuf_run_done==0))
  3568. {
  3569. cmdbuf_obj->cmdbuf_run_done=1;
  3570. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  3571. cmdbuf_processed_num++;
  3572. }
  3573. else
  3574. break;
  3575. new_cmdbuf_node = new_cmdbuf_node->previous;
  3576. }
  3577. base_cmdbuf_node=base_cmdbuf_node->next;
  3578. vcmd_delink_cmdbuf(dev,base_cmdbuf_node);
  3579. vcmd_link_cmdbuf(dev,base_cmdbuf_node);
  3580. if(dev->sw_cmdbuf_rdy_num !=0)
  3581. {
  3582. //restart new command
  3583. vcmd_start(dev,base_cmdbuf_node);
  3584. }
  3585. spin_unlock_irqrestore(dev->spinlock, flags);
  3586. if(cmdbuf_processed_num)
  3587. wake_up_interruptible_all(dev->wait_queue);
  3588. handled++;
  3589. wake_up_interruptible_all(&mc_wait_queue);
  3590. return IRQ_HANDLED;
  3591. }
  3592. if(dev->hw_version_id <= HW_ID_1_0_C )
  3593. cmdbuf_id = vcmd_get_register_mirror_value(dev->reg_mirror,HWIF_VCMD_IRQ_INTCMD);
  3594. if(cmdbuf_id)
  3595. {
  3596. if(dev->hw_version_id <= HW_ID_1_0_C )
  3597. {
  3598. if(cmdbuf_id>=TOTAL_DISCRETE_CMDBUF_NUM)
  3599. {
  3600. pr_err("hantrovcmd_isr error cmdbuf_id greater than the ceiling !!\n");
  3601. spin_unlock_irqrestore(dev->spinlock, flags);
  3602. return IRQ_HANDLED;
  3603. }
  3604. }
  3605. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  3606. if(new_cmdbuf_node==NULL)
  3607. {
  3608. pr_err("hantrovcmd_isr error cmdbuf_id !!\n");
  3609. spin_unlock_irqrestore(dev->spinlock, flags);
  3610. return IRQ_HANDLED;
  3611. }
  3612. // interrupt cmdbuf and cmdbufs prior to itself, run_done = 1
  3613. while(1)
  3614. {
  3615. if(new_cmdbuf_node==NULL)
  3616. break;
  3617. cmdbuf_obj = (struct cmdbuf_obj*)new_cmdbuf_node->data;
  3618. if((cmdbuf_obj->cmdbuf_run_done==0))
  3619. {
  3620. cmdbuf_obj->cmdbuf_run_done=1;
  3621. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  3622. cmdbuf_processed_num++;
  3623. }
  3624. else
  3625. break;
  3626. new_cmdbuf_node = new_cmdbuf_node->previous;
  3627. }
  3628. handled++;
  3629. }
  3630. spin_unlock_irqrestore(dev->spinlock, flags);
  3631. if(cmdbuf_processed_num)
  3632. wake_up_interruptible_all(dev->wait_queue);
  3633. if(!handled)
  3634. {
  3635. PDEBUG("IRQ received, but not hantro's!\n");
  3636. }
  3637. wake_up_interruptible_all(&mc_wait_queue);
  3638. return IRQ_HANDLED;
  3639. }
  3640. void vcmd_reset_asic(struct hantrovcmd_dev * dev)
  3641. {
  3642. int i,n;
  3643. u32 result;
  3644. for (n=0;n<total_vcmd_core_num;n++)
  3645. {
  3646. if(dev[n].hwregs!=NULL)
  3647. {
  3648. //disable interrupt at first
  3649. vcmd_write_reg((const void *)dev[n].hwregs,VCMD_REGISTER_INT_CTL_OFFSET,0x0000);
  3650. //reset all
  3651. vcmd_write_reg((const void *)dev[n].hwregs,VCMD_REGISTER_CONTROL_OFFSET,0x0002);
  3652. //read status register
  3653. result =vcmd_read_reg((const void *)dev[n].hwregs,VCMD_REGISTER_INT_STATUS_OFFSET);
  3654. //clean status register
  3655. vcmd_write_reg((const void *)dev[n].hwregs,VCMD_REGISTER_INT_STATUS_OFFSET,result);
  3656. for(i = VCMD_REGISTER_CONTROL_OFFSET; i < dev[n].vcmd_core_cfg.vcmd_iosize; i += 4)
  3657. {
  3658. //set all register 0
  3659. vcmd_write_reg((const void *)dev[n].hwregs,i,0x0000);
  3660. }
  3661. //enable all interrupt
  3662. vcmd_write_reg((const void *)dev[n].hwregs,VCMD_REGISTER_INT_CTL_OFFSET,0xffffffff);
  3663. }
  3664. }
  3665. }
  3666. static void vcmd_reset_current_asic(struct hantrovcmd_dev * dev)
  3667. {
  3668. u32 result;
  3669. if(dev->hwregs!=NULL)
  3670. {
  3671. //disable interrupt at first
  3672. vcmd_write_reg((const void *)dev->hwregs,VCMD_REGISTER_INT_CTL_OFFSET,0x0000);
  3673. //reset all
  3674. vcmd_write_reg((const void *)dev->hwregs,VCMD_REGISTER_CONTROL_OFFSET,0x0002);
  3675. //read status register
  3676. result =vcmd_read_reg((const void *)dev->hwregs,VCMD_REGISTER_INT_STATUS_OFFSET);
  3677. //clean status register
  3678. vcmd_write_reg((const void *)dev->hwregs,VCMD_REGISTER_INT_STATUS_OFFSET,result);
  3679. }
  3680. }
  3681. static void printk_vcmd_register_debug(const void *hwregs, char * info) {
  3682. #ifdef HANTRO_VCMD_DRIVER_DEBUG
  3683. u32 i, fordebug;
  3684. for(i = 0; i < ASIC_VCMD_SWREG_AMOUNT; i++) {
  3685. fordebug = vcmd_read_reg ((const void *)hwregs, i*4);
  3686. pr_info("%s vcmd register %d:0x%x\n",info,i,fordebug);
  3687. }
  3688. #endif
  3689. }
  3690. void hantrovcmd_reset(void)
  3691. {
  3692. if (hantrovcmd_data) {
  3693. int i;
  3694. for(i=0;i<total_vcmd_core_num;i++) {
  3695. hantrovcmd_data[i].working_state = WORKING_STATE_IDLE;
  3696. hantrovcmd_data[i].sw_cmdbuf_rdy_num = 0;
  3697. }
  3698. vcmd_reset_asic(hantrovcmd_data);
  3699. }
  3700. }