hantro_mmu.c 57 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2014 - 2021 VERISILICON
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (C) 2014 - 2021 VERISILICON
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program; if not, write to the Free Software Foundation,
  43. * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  44. *
  45. *****************************************************************************
  46. *
  47. * Note: This software is released under dual MIT and GPL licenses. A
  48. * recipient may use this file under the terms of either the MIT license or
  49. * GPL License. If you wish to use only one license not the other, you can
  50. * indicate your decision by deleting one of the above license notices in your
  51. * version of this file.
  52. *
  53. *****************************************************************************/
  54. #include <linux/version.h>
  55. #include <linux/slab.h>
  56. #include <linux/vmalloc.h>
  57. #include <linux/module.h>
  58. #include <linux/init.h>
  59. #include <linux/kernel.h>
  60. #include <linux/debugfs.h>
  61. #include <linux/types.h>
  62. #include <linux/device.h>
  63. #include <linux/pagemap.h>
  64. #include <linux/sched.h>
  65. #include <stddef.h>
  66. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,10,0))
  67. #include <linux/dma-map-ops.h>
  68. #else
  69. #include <linux/dma-contiguous.h>
  70. #endif
  71. #include <linux/platform_device.h>
  72. #include <linux/version.h>
  73. #include <linux/mod_devicetable.h>
  74. #include <linux/dma-buf.h>
  75. #include "hantrommu.h"
  76. #include "subsys.h"
  77. MODULE_DESCRIPTION("Verisilicon VPU Driver");
  78. MODULE_LICENSE("GPL");
  79. #ifndef NULL
  80. #ifdef __cplusplus
  81. #define NULL 0
  82. #else
  83. #define NULL ((void *)0)
  84. #endif
  85. #endif
  86. #define MMU_REG_OFFSET 0
  87. #define MMU_REG_HW_ID (MMU_REG_OFFSET + 6*4)
  88. #define MMU_REG_FLUSH (MMU_REG_OFFSET + 97*4)
  89. #define MMU_REG_PAGE_TABLE_ID (MMU_REG_OFFSET + 107*4)
  90. #define MMU_REG_CONTROL (MMU_REG_OFFSET + 226*4)
  91. #define MMU_REG_ADDRESS (MMU_REG_OFFSET + 227*4)
  92. #define MMU_REG_ADDRESS_MSB (MMU_REG_OFFSET + 228*4)
  93. /*******************************************************************************
  94. ***** New MMU Defination *******************************************************/
  95. #define MMU_MTLB_SHIFT 22
  96. #define MMU_STLB_4K_SHIFT 12
  97. #define MMU_STLB_64K_SHIFT 16
  98. #define MMU_MTLB_BITS (32 - MMU_MTLB_SHIFT)
  99. #define MMU_PAGE_4K_BITS MMU_STLB_4K_SHIFT
  100. #define MMU_STLB_4K_BITS (32 - MMU_MTLB_BITS - MMU_PAGE_4K_BITS)
  101. #define MMU_PAGE_64K_BITS MMU_STLB_64K_SHIFT
  102. #define MMU_STLB_64K_BITS (32 - MMU_MTLB_BITS - MMU_PAGE_64K_BITS)
  103. #define MMU_MTLB_ENTRY_NUM (1 << MMU_MTLB_BITS)
  104. #define MMU_MTLB_SIZE (MMU_MTLB_ENTRY_NUM << 2)
  105. #define MMU_STLB_4K_ENTRY_NUM (1 << MMU_STLB_4K_BITS)
  106. #define MMU_STLB_4K_SIZE (MMU_STLB_4K_ENTRY_NUM << 2)
  107. #define MMU_PAGE_4K_SIZE (1 << MMU_STLB_4K_SHIFT)
  108. #define MMU_STLB_64K_ENTRY_NUM (1 << MMU_STLB_64K_BITS)
  109. #define MMU_STLB_64K_SIZE (MMU_STLB_64K_ENTRY_NUM << 2)
  110. #define MMU_PAGE_64K_SIZE (1 << MMU_STLB_64K_SHIFT)
  111. #define MMU_MTLB_MASK (~((1U << MMU_MTLB_SHIFT)-1))
  112. #define MMU_STLB_4K_MASK ((~0U << MMU_STLB_4K_SHIFT) ^ MMU_MTLB_MASK)
  113. #define MMU_PAGE_4K_MASK (MMU_PAGE_4K_SIZE - 1)
  114. #define MMU_STLB_64K_MASK ((~((1U << MMU_STLB_64K_SHIFT)-1)) ^ MMU_MTLB_MASK)
  115. #define MMU_PAGE_64K_MASK (MMU_PAGE_64K_SIZE - 1)
  116. /* Page offset definitions. */
  117. #define MMU_OFFSET_4K_BITS (32 - MMU_MTLB_BITS - MMU_STLB_4K_BITS)
  118. #define MMU_OFFSET_4K_MASK ((1U << MMU_OFFSET_4K_BITS) - 1)
  119. #define MMU_OFFSET_16K_BITS (32 - MMU_MTLB_BITS - MMU_STLB_16K_BITS)
  120. #define MMU_OFFSET_16K_MASK ((1U << MMU_OFFSET_16K_BITS) - 1)
  121. #define MMU_MTLB_ENTRY_HINTS_BITS 6
  122. #define MMU_MTLB_ENTRY_STLB_MASK (~((1U << MMU_MTLB_ENTRY_HINTS_BITS) - 1))
  123. #define MMU_MTLB_PRESENT 0x00000001
  124. #define MMU_MTLB_EXCEPTION 0x00000002
  125. #define MMU_MTLB_4K_PAGE 0x00000000
  126. #define MMU_STLB_PRESENT 0x00000001
  127. #define MMU_STLB_EXCEPTION 0x00000002
  128. #define MMU_STLB_4K_PAGE 0x00000000
  129. #define MMU_FALSE 0
  130. #define MMU_TRUE 1
  131. #define MMU_ERR_OS_FAIL (0xffff)
  132. #define MMU_EFAULT MMU_ERR_OS_FAIL
  133. #define MMU_ENOTTY MMU_ERR_OS_FAIL
  134. #define MMU_INFINITE ((u32) ~0U)
  135. #define MAX_NOPAGED_SIZE 0x20000
  136. #define MMU_SUPPRESS_OOM_MESSAGE 1
  137. #define MTLB_PCIE_START_ADDRESS 0x00100000
  138. #define PAGE_PCIE_START_ADDRESS 0x00200000 /* page_table_entry start address */
  139. #define STLB_PCIE_START_ADDRESS 0x00300000
  140. #define PAGE_TABLE_ENTRY_SIZE 64
  141. #if MMU_SUPPRESS_OOM_MESSAGE
  142. #define MMU_NOWARN __GFP_NOWARN
  143. #else
  144. #define MMU_NOWARN 0
  145. #endif
  146. #define MMU_IS_ERROR(status) (status < 0)
  147. #define MMU_NO_ERROR(status) (status >= 0)
  148. #define MMU_IS_SUCCESS(status) (status == MMU_STATUS_OK)
  149. #undef MMUDEBUG
  150. #ifdef HANTROMMU_DEBUG
  151. # ifdef __KERNEL__
  152. # define MMUDEBUG(fmt, args...) printk( KERN_INFO "hantrommu: " fmt, ## args)
  153. # else
  154. # define MMUDEBUG(fmt, args...) fprintf(stderr, fmt, ## args)
  155. # endif
  156. #else
  157. # define MMUDEBUG(fmt, args...)
  158. #endif
  159. #define MMU_ON_ERROR(func) \
  160. do { \
  161. status = func; \
  162. if (MMU_IS_ERROR(status)){ \
  163. goto onerror; \
  164. } \
  165. }while (MMU_FALSE)
  166. #define WritePageEntry(page_entry, entry_value) \
  167. *(unsigned int *)(page_entry) =(unsigned int)(entry_value)
  168. #define ReadPageEntry(page_entry) *(unsigned int *)(page_entry)
  169. #define DRIVER_NAME "hantrodecdma"
  170. /* simple map mode: generate mmu address which is same as input bus address*/
  171. unsigned int simple_map = 0;
  172. /* this shift should be an integral multiple of mmu page size(4096).
  173. It can generate a mmu address shift in simple map mode*/
  174. unsigned int map_shift = 0;
  175. /* module_param(name, type, perm) */
  176. module_param(simple_map, uint, 0);
  177. module_param(map_shift, uint, 0);
  178. enum MMURegion {
  179. MMU_REGION_IN,
  180. MMU_REGION_OUT,
  181. MMU_REGION_PRIVATE,
  182. MMU_REGION_PUB,
  183. MMU_REGION_COUNT
  184. };
  185. struct MMUNode {
  186. void *buf_virtual_address;
  187. unsigned int buf_bus_address; /* used in kernel map mode */
  188. int mtlb_start;
  189. int stlb_start;
  190. int mtlb_end;
  191. int stlb_end;
  192. unsigned int page_count;
  193. int process_id;
  194. struct file* filp;
  195. struct MMUNode *next;
  196. struct MMUNode *prev;
  197. };
  198. struct MMUDDRRegion {
  199. unsigned long long physical_address;
  200. unsigned long long virtual_address;
  201. unsigned int page_count;
  202. void *node_mutex;
  203. struct MMUNode *simple_map_head;
  204. struct MMUNode *simple_map_tail;
  205. struct MMUNode *free_map_head;
  206. struct MMUNode *map_head;
  207. struct MMUNode *free_map_tail;
  208. struct MMUNode *map_tail;
  209. };
  210. struct MMU {
  211. void *page_table_mutex;
  212. /* Master TLB information. */
  213. unsigned int mtlb_size;
  214. unsigned long long mtlb_physical;
  215. void *mtlb_virtual;
  216. unsigned int mtlb_entries;
  217. int enabled;
  218. unsigned int stlb_size;
  219. unsigned long long stlb_physical;
  220. void *stlb_virtual;
  221. struct MMUDDRRegion region[MMU_REGION_COUNT];
  222. unsigned int page_table_array_size;
  223. unsigned long long page_table_array_physical;
  224. void *page_table_array;
  225. };
  226. static struct MMU *g_mmu = NULL;
  227. extern unsigned long gBaseDDRHw;
  228. unsigned int mmu_enable = MMU_FALSE;
  229. static unsigned int mmu_init = MMU_FALSE;
  230. extern unsigned int pcie;
  231. static unsigned int region_in_mmu_start = REGION_IN_MMU_START;
  232. static unsigned int region_in_mmu_end = REGION_IN_MMU_END;
  233. static unsigned int region_out_mmu_start = REGION_OUT_MMU_START;
  234. static unsigned int region_out_mmu_end = REGION_OUT_MMU_END;
  235. static unsigned int region_private_mmu_start = REGION_PRIVATE_MMU_START;
  236. static unsigned int region_private_mmu_end = REGION_PRIVATE_MMU_END;
  237. static const struct platform_device_info hantro_platform_info = {
  238. .name = DRIVER_NAME,
  239. .id = -1,
  240. .dma_mask = DMA_BIT_MASK(32),
  241. };
  242. static int hantro_drm_probe(struct platform_device *pdev)
  243. {
  244. int result;
  245. struct device *dev = &pdev->dev;
  246. (void) dev;
  247. (void) result;
  248. return 0;
  249. }
  250. static int hantro_drm_remove(struct platform_device *pdev)
  251. {
  252. struct device *dev = &pdev->dev;
  253. (void) dev;
  254. return 0;
  255. }
  256. static const struct platform_device_id hantro_drm_platform_ids[] = {
  257. {
  258. .name = DRIVER_NAME,
  259. },
  260. {/* sentinel */ },
  261. };
  262. static const struct of_device_id hantro_of_match[] = {
  263. { .compatible = "thead,light-vc8000d-mmu", },
  264. {/* sentinel */}
  265. };
  266. static struct platform_driver hantro_drm_platform_driver = {
  267. .probe = hantro_drm_probe,
  268. .remove = hantro_drm_remove,
  269. .driver = {
  270. .name = DRIVER_NAME,
  271. .owner = THIS_MODULE,
  272. .of_match_table = hantro_of_match,
  273. },
  274. .id_table = hantro_drm_platform_ids,
  275. };
  276. struct platform_device *platformdev;
  277. static enum MMUStatus ZeroMemory(void *memory, unsigned int bytes) {
  278. memset(memory, 0, bytes);
  279. return MMU_STATUS_OK;
  280. }
  281. static enum MMUStatus AllocateMemory(unsigned int bytes, void **memory){
  282. void *pointer;
  283. enum MMUStatus status;
  284. if (bytes > MAX_NOPAGED_SIZE) {
  285. pointer = (void*) vmalloc(bytes);
  286. MMUDEBUG(" *****VMALLOC size*****%d\n", bytes);
  287. } else {
  288. pointer = (void*) kmalloc(bytes, GFP_KERNEL | MMU_NOWARN);
  289. MMUDEBUG(" *****KMALLOC size*****%d\n", bytes);
  290. }
  291. if (pointer == NULL) {
  292. /* Out of memory. */
  293. status = MMU_STATUS_OUT_OF_MEMORY;
  294. goto onerror;
  295. }
  296. /* Return pointer to the memory allocation. */
  297. *memory = pointer;
  298. return MMU_STATUS_OK;
  299. onerror:
  300. /* Return the status. */
  301. return status;
  302. }
  303. static enum MMUStatus FreeMemory(void *memory) {
  304. /* Free the memory from the OS pool. */
  305. if (is_vmalloc_addr(memory)) {
  306. MMUDEBUG(" *****VFREE*****%p\n", memory);
  307. vfree(memory);
  308. } else {
  309. MMUDEBUG(" *****KFREE*****%p\n", memory);
  310. kfree(memory);
  311. }
  312. return MMU_STATUS_OK;
  313. }
  314. static enum MMUStatus SMDeleteNode(struct MMUNode **pp) {
  315. (*pp)->prev->next = (*pp)->next;
  316. (*pp)->next->prev = (*pp)->prev;
  317. MMUDEBUG(" *****DeleteNode size*****%d\n", (*pp)->page_count);
  318. FreeMemory(*pp);
  319. return MMU_STATUS_OK;
  320. }
  321. static enum MMUStatus DeleteNode(struct MMUNode **pp) {
  322. (*pp)->prev->next = (*pp)->next;
  323. (*pp)->next->prev = (*pp)->prev;
  324. MMUDEBUG(" *****DeleteNode size*****%d\n", (*pp)->page_count);
  325. FreeMemory(*pp);
  326. return MMU_STATUS_OK;
  327. }
  328. static enum MMUStatus MergeNode(struct MMUNode *h,
  329. struct MMUNode **pp) {
  330. struct MMUNode *tmp0 = h->next;
  331. struct MMUNode *tmp1 = h->next;
  332. while(tmp0) {
  333. /* 1th step: find front contiguous memory node */
  334. if(tmp0->mtlb_end == (*pp)->mtlb_start &&
  335. tmp0->stlb_end == (*pp)->stlb_start) {
  336. tmp0->mtlb_end = (*pp)->mtlb_end;
  337. tmp0->stlb_end = (*pp)->stlb_end;
  338. tmp0->page_count += (*pp)->page_count;
  339. DeleteNode(pp);
  340. MMUDEBUG(" *****first merge to front. node size*****%d\n", tmp0->page_count);
  341. /* after merge to front contiguous memory node,
  342. find if there is behind contiguous memory node */
  343. while(tmp1) {
  344. /* merge */
  345. if(tmp1->mtlb_start == tmp0->mtlb_end &&
  346. tmp1->stlb_start == tmp0->stlb_end) {
  347. tmp1->mtlb_start = tmp0->mtlb_start;
  348. tmp1->stlb_start = tmp0->stlb_start;
  349. tmp1->page_count += tmp0->page_count;
  350. MMUDEBUG(" *****second merge to behind. node size*****%d\n", tmp1->page_count);
  351. DeleteNode(&tmp0);
  352. return MMU_STATUS_OK;
  353. }
  354. tmp1 = tmp1->next;
  355. }
  356. return MMU_STATUS_OK;
  357. /* 1th step: find behind contiguous memory node */
  358. } else if(tmp0->mtlb_start == (*pp)->mtlb_end &&
  359. tmp0->stlb_start == (*pp)->stlb_end) {
  360. tmp0->mtlb_start = (*pp)->mtlb_start;
  361. tmp0->stlb_start = (*pp)->stlb_start;
  362. tmp0->page_count += (*pp)->page_count;
  363. DeleteNode(pp);
  364. MMUDEBUG(" *****first merge to behind. node size*****%d\n", tmp0->page_count);
  365. /* after merge to behind contiguous memory node,
  366. find if there is front contiguous memory node */
  367. while(tmp1) {
  368. /* merge */
  369. if(tmp1->mtlb_end == tmp0->mtlb_start &&
  370. tmp1->stlb_end == tmp0->stlb_start) {
  371. tmp1->mtlb_end = tmp0->mtlb_end;
  372. tmp1->stlb_end = tmp0->stlb_end;
  373. tmp1->page_count += tmp0->page_count;
  374. MMUDEBUG(" *****second merge to front. node size*****%d\n", tmp1->page_count);
  375. DeleteNode(&tmp0);
  376. return MMU_STATUS_OK;
  377. }
  378. tmp1 = tmp1->next;
  379. }
  380. return MMU_STATUS_OK;
  381. }
  382. tmp0 = tmp0->next;
  383. }
  384. return MMU_STATUS_FALSE;
  385. }
  386. /* Insert a node to map list */
  387. static enum MMUStatus SMInsertNode(enum MMURegion e,
  388. struct MMUNode **pp) {
  389. struct MMUNode *h;
  390. h = g_mmu->region[e].simple_map_head;
  391. h->next->prev = *pp;
  392. (*pp)->next = h->next;
  393. (*pp)->prev = h;
  394. h->next = *pp;
  395. MMUDEBUG(" *****insert bm node*****%d\n", (*pp)->page_count);
  396. return MMU_STATUS_OK;
  397. }
  398. static enum MMUStatus InsertNode(enum MMURegion e,
  399. struct MMUNode **pp,
  400. unsigned int free) {
  401. enum MMUStatus status;
  402. struct MMUNode *h, *b;
  403. if(free) {
  404. h = g_mmu->region[e].free_map_head;
  405. b = g_mmu->region[e].map_head;
  406. status = MergeNode(h, pp);
  407. MMUDEBUG(" *****insert free*****%d\n", (*pp)->page_count);
  408. if(MMU_IS_ERROR(status)) {
  409. /* remove from map*/
  410. if((*pp)->prev != NULL && (*pp)->next != NULL) {
  411. (*pp)->prev->next = (*pp)->next;
  412. (*pp)->next->prev = (*pp)->prev;
  413. }
  414. /* insert to free map */
  415. h->next->prev = *pp;
  416. (*pp)->next = h->next;
  417. (*pp)->prev = h;
  418. h->next = *pp;
  419. }
  420. } else {
  421. h = g_mmu->region[e].map_head;
  422. h->next->prev = *pp;
  423. (*pp)->next = h->next;
  424. (*pp)->prev = h;
  425. h->next = *pp;
  426. MMUDEBUG(" *****insert unfree*****%d\n", (*pp)->page_count);
  427. }
  428. return MMU_STATUS_OK;
  429. }
  430. /* Create a Node */
  431. static enum MMUStatus SMCreateNode(enum MMURegion e,
  432. struct MMUNode **node,
  433. unsigned int page_count) {
  434. struct MMUNode *p, **new;
  435. p = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  436. new = &p;
  437. (*new)->mtlb_start = -1;
  438. (*new)->stlb_start = -1;
  439. (*new)->mtlb_end = -1;
  440. (*new)->stlb_end = -1;
  441. (*new)->process_id = 0;
  442. (*new)->filp = NULL;
  443. (*new)->page_count = 0;
  444. (*new)->prev = NULL;
  445. (*new)->next = NULL;
  446. /* Insert a uncomplete Node, it will be initialized later */
  447. SMInsertNode(e, new);
  448. /* return a new node for map buffer */
  449. *node = *new;
  450. return MMU_STATUS_OK;
  451. }
  452. /* Create initial Nodes */
  453. static enum MMUStatus SMCreateNodes(void) {
  454. struct MMUNode *simple_map_head;
  455. struct MMUNode *simple_map_tail;
  456. int i;
  457. /* Init each region map node */
  458. for (i = 0; i < MMU_REGION_COUNT ; i++) {
  459. simple_map_head = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  460. simple_map_tail = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  461. simple_map_head->mtlb_start = -1;
  462. simple_map_head->stlb_start = -1;
  463. simple_map_head->mtlb_end = -1;
  464. simple_map_head->stlb_end = -1;
  465. simple_map_head->process_id = 0;
  466. simple_map_head->filp = NULL;
  467. simple_map_head->page_count = 0;
  468. simple_map_head->prev = NULL;
  469. simple_map_head->next = simple_map_tail;
  470. simple_map_tail->mtlb_start = -1;
  471. simple_map_tail->stlb_start = -1;
  472. simple_map_tail->mtlb_end = -1;
  473. simple_map_tail->stlb_end = -1;
  474. simple_map_tail->process_id = 0;
  475. simple_map_tail->filp = NULL;
  476. simple_map_tail->page_count = 0;
  477. simple_map_tail->prev = simple_map_head;
  478. simple_map_tail->next = NULL;
  479. g_mmu->region[i].simple_map_head = simple_map_head;
  480. g_mmu->region[i].simple_map_tail = simple_map_tail;
  481. }
  482. return MMU_STATUS_OK;
  483. }
  484. static enum MMUStatus CreateNode(void) {
  485. struct MMUNode *free_map_head, *map_head, *p, **pp;
  486. struct MMUNode *free_map_tail, *map_tail;
  487. int i;
  488. unsigned int page_count;
  489. unsigned int prev_stlb = 0, prev_mtlb = 0;
  490. /* Init each region map node */
  491. for (i = 0; i < MMU_REGION_COUNT ; i++) {
  492. free_map_head = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  493. map_head = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  494. free_map_tail = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  495. map_tail = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  496. free_map_head->mtlb_start = map_head->mtlb_start = -1;
  497. free_map_head->stlb_start = map_head->stlb_start = -1;
  498. free_map_head->mtlb_end = map_head->mtlb_end = -1;
  499. free_map_head->stlb_end = map_head->stlb_end = -1;
  500. free_map_head->process_id = map_head->process_id = 0;
  501. free_map_head->filp = map_head->filp = NULL;
  502. free_map_head->page_count = map_head->page_count = 0;
  503. free_map_head->prev = map_head->prev = NULL;
  504. free_map_head->next = free_map_tail;
  505. map_head->next = map_tail;
  506. free_map_tail->mtlb_start = map_tail->mtlb_start = -1;
  507. free_map_tail->stlb_start = map_tail->stlb_start = -1;
  508. free_map_tail->mtlb_end = map_tail->mtlb_end = -1;
  509. free_map_tail->stlb_end = map_tail->stlb_end = -1;
  510. free_map_tail->process_id = map_tail->process_id = 0;
  511. free_map_tail->filp = map_tail->filp = NULL;
  512. free_map_tail->page_count = map_tail->page_count = 0;
  513. free_map_tail->prev = free_map_head;
  514. map_tail->prev = map_head;
  515. free_map_tail->next = map_tail->next = NULL;
  516. g_mmu->region[i].free_map_head = free_map_head;
  517. g_mmu->region[i].map_head = map_head;
  518. g_mmu->region[i].free_map_tail = free_map_tail;
  519. g_mmu->region[i].map_tail = map_tail;
  520. p = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  521. pp = &p;
  522. switch(i) {
  523. case MMU_REGION_IN:
  524. page_count = (REGION_IN_END - REGION_IN_START + 1)/PAGE_SIZE;
  525. p->stlb_start = region_in_mmu_start >> 12 & 0x3FF; //hold mmu addr: 0x0
  526. p->mtlb_start = region_in_mmu_start >> 22;
  527. //end point next region start: +1; for remainder: +1
  528. p->stlb_end = prev_stlb = region_in_mmu_end >> 12 & 0x3FF;
  529. p->mtlb_end = prev_mtlb = region_in_mmu_end >> 22;
  530. p->page_count = page_count - 1; //hold mmu addr: 0x0
  531. break;
  532. case MMU_REGION_OUT:
  533. page_count = (REGION_OUT_END - REGION_OUT_START + 1)/PAGE_SIZE;
  534. p->stlb_start = region_out_mmu_start >> 12 & 0x3FF;
  535. p->mtlb_start = region_out_mmu_start >> 22;
  536. p->stlb_end = prev_stlb = region_out_mmu_end >> 12 & 0x3FF;
  537. p->mtlb_end = prev_mtlb = region_out_mmu_end >> 22;
  538. p->page_count = page_count;
  539. break;
  540. case MMU_REGION_PRIVATE:
  541. page_count = (REGION_PRIVATE_END - REGION_PRIVATE_START + 1)/PAGE_SIZE;
  542. p->stlb_start = region_private_mmu_start >> 12 & 0x3FF;
  543. p->mtlb_start = region_private_mmu_start >> 22;
  544. p->stlb_end = prev_stlb = region_private_mmu_end >> 12 & 0x3FF;
  545. p->mtlb_end = prev_mtlb = region_private_mmu_end >> 22;
  546. p->page_count = page_count;
  547. break;
  548. case MMU_REGION_PUB:
  549. p->stlb_start = prev_stlb;
  550. p->mtlb_start = prev_mtlb;
  551. p->stlb_end = prev_stlb = MMU_STLB_4K_ENTRY_NUM - 1;
  552. p->mtlb_end = prev_mtlb = MMU_MTLB_ENTRY_NUM - 1;
  553. p->page_count = (p->mtlb_end - p->mtlb_start) * MMU_STLB_4K_ENTRY_NUM +
  554. p->stlb_end - p->stlb_start + 1;
  555. break;
  556. default:
  557. pr_notice(" *****MMU Region Error*****\n");
  558. break;
  559. }
  560. p->process_id = 0;
  561. p->filp = NULL;
  562. p->next = p->prev = NULL;
  563. InsertNode(i, pp, 1);
  564. }
  565. return MMU_STATUS_OK;
  566. }
  567. /* A simpile function to check if the map buffer is existed.
  568. it needs more complex version*/
  569. static enum MMUStatus SMCheckAddress(enum MMURegion e,
  570. void *virtual_address) {
  571. struct MMUNode *p;
  572. p = g_mmu->region[e].simple_map_head->next;
  573. while(p) {
  574. if(p->buf_virtual_address == virtual_address) {
  575. return MMU_STATUS_FALSE;
  576. }
  577. p = p->next;
  578. }
  579. return MMU_STATUS_OK;
  580. }
  581. static enum MMUStatus FindFreeNode(enum MMURegion e,
  582. struct MMUNode **node,
  583. unsigned int page_count) {
  584. struct MMUNode *p;
  585. p = g_mmu->region[e].free_map_head->next;
  586. while(p) {
  587. if(p->page_count >= page_count) {
  588. *node = p;
  589. return MMU_STATUS_OK;
  590. }
  591. p = p->next;
  592. }
  593. return MMU_STATUS_FALSE;
  594. }
  595. static enum MMUStatus SplitFreeNode(enum MMURegion e,
  596. struct MMUNode **node,
  597. unsigned int page_count) {
  598. struct MMUNode *p, **new;
  599. p = kmalloc(sizeof(struct MMUNode), GFP_KERNEL | MMU_NOWARN);
  600. new = &p;
  601. **new = **node;
  602. (*new)->mtlb_start = (*node)->mtlb_start;
  603. (*new)->stlb_start = (*node)->stlb_start;
  604. (*new)->mtlb_end = (page_count + (*node)->stlb_start) /
  605. MMU_STLB_4K_ENTRY_NUM +
  606. (*node)->mtlb_start;
  607. (*new)->stlb_end = (page_count + (*node)->stlb_start) %
  608. MMU_STLB_4K_ENTRY_NUM;
  609. (*new)->process_id = (*node)->process_id;
  610. (*new)->page_count = page_count;
  611. MMUDEBUG(" *****new mtlb_start*****%d\n", (*new)->mtlb_start);
  612. MMUDEBUG(" *****new stlb_start*****%d\n", (*new)->stlb_start);
  613. MMUDEBUG(" *****new mtlb_end*****%d\n", (*new)->mtlb_end);
  614. MMUDEBUG(" *****new stlb_end*****%d\n", (*new)->stlb_end);
  615. /* Insert a new node in map */
  616. InsertNode(e, new, 0);
  617. /* Update free node in free map*/
  618. (*node)->page_count -= page_count;
  619. if((*node)->page_count == 0) {
  620. DeleteNode(node);
  621. MMUDEBUG(" *****old node deleted*****\n");
  622. } else {
  623. (*node)->mtlb_start = (*new)->mtlb_end;
  624. (*node)->stlb_start = (*new)->stlb_end;
  625. MMUDEBUG(" *****old mtlb_start*****%d\n", (*node)->mtlb_start);
  626. MMUDEBUG(" *****old stlb_start*****%d\n", (*node)->stlb_start);
  627. MMUDEBUG(" *****old mtlb_end*****%d\n", (*node)->mtlb_end);
  628. MMUDEBUG(" *****old stlb_end*****%d\n", (*node)->stlb_end);
  629. }
  630. /* return a new node for map buffer */
  631. *node = *new;
  632. return MMU_STATUS_OK;
  633. }
  634. static enum MMUStatus SMRemoveNode(enum MMURegion e,
  635. void *buf_virtual_address,
  636. unsigned int process_id) {
  637. struct MMUNode *p, **pp;
  638. p = g_mmu->region[e].simple_map_head->next;
  639. pp = &p;
  640. while(*pp) {
  641. if((*pp)->buf_virtual_address == buf_virtual_address &&
  642. (*pp)->process_id == process_id) {
  643. SMDeleteNode(pp);
  644. break;
  645. }
  646. *pp = (*pp)->next;
  647. }
  648. return MMU_STATUS_OK;
  649. }
  650. static enum MMUStatus RemoveNode(enum MMURegion e,
  651. void *buf_virtual_address,
  652. unsigned int process_id) {
  653. struct MMUNode *p, **pp;
  654. p = g_mmu->region[e].map_head->next;
  655. pp = &p;
  656. while(*pp) {
  657. if((*pp)->buf_virtual_address == buf_virtual_address &&
  658. (*pp)->process_id == process_id) {
  659. InsertNode(e, pp, 1);
  660. break;
  661. }
  662. *pp = (*pp)->next;
  663. }
  664. return MMU_STATUS_OK;
  665. }
  666. static enum MMUStatus SMRemoveKernelNode(enum MMURegion e,
  667. unsigned int buf_bus_address,
  668. unsigned int process_id) {
  669. struct MMUNode *p, **pp;
  670. p = g_mmu->region[e].simple_map_head->next;
  671. pp = &p;
  672. while(*pp) {
  673. if((*pp)->buf_bus_address == buf_bus_address &&
  674. (*pp)->process_id == process_id) {
  675. SMDeleteNode(pp);
  676. break;
  677. }
  678. *pp = (*pp)->next;
  679. }
  680. return MMU_STATUS_OK;
  681. }
  682. static enum MMUStatus RemoveKernelNode(enum MMURegion e,
  683. unsigned int buf_bus_address,
  684. unsigned int process_id) {
  685. struct MMUNode *p, **pp;
  686. p = g_mmu->region[e].map_head->next;
  687. pp = &p;
  688. while(*pp) {
  689. if((*pp)->buf_bus_address == buf_bus_address &&
  690. (*pp)->process_id == process_id) {
  691. InsertNode(e, pp, 1);
  692. break;
  693. }
  694. *pp = (*pp)->next;
  695. }
  696. return MMU_STATUS_OK;
  697. }
  698. static enum MMUStatus Delay(unsigned int delay) {
  699. if(delay > 0) {
  700. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)
  701. ktime_t dl = ktime_set((delay / MSEC_PER_SEC),
  702. (delay % MSEC_PER_SEC) * NSEC_PER_MSEC);
  703. __set_current_state(TASK_UNINTERRUPTIBLE);
  704. schedule_hrtimeout(&dl, HRTIMER_MODE_REL);
  705. #else
  706. msleep(delay);
  707. #endif
  708. }
  709. return MMU_STATUS_OK;
  710. }
  711. static enum MMUStatus CreateMutex(void **mtx) {
  712. enum MMUStatus status;
  713. /* Allocate the mutex structure. */
  714. status = AllocateMemory(sizeof(struct mutex), mtx);
  715. if (MMU_IS_SUCCESS(status)) {
  716. /* Initialize the mutex. */
  717. mutex_init(*(struct mutex **)mtx);
  718. }
  719. return status;
  720. }
  721. static enum MMUStatus DeleteMutex(void *mtx) {
  722. /* Destroy the mutex. */
  723. mutex_destroy((struct mutex *)mtx);
  724. /* Free the mutex structure. */
  725. FreeMemory(mtx);
  726. return MMU_STATUS_OK;
  727. }
  728. static enum MMUStatus AcquireMutex(void *mtx, unsigned int timeout) {
  729. if (timeout == MMU_INFINITE)
  730. {
  731. /* Lock the mutex. */
  732. mutex_lock(mtx);
  733. /* Success. */
  734. return MMU_STATUS_OK;
  735. }
  736. for (;;) {
  737. /* Try to acquire the mutex. */
  738. if (mutex_trylock(mtx)) {
  739. /* Success. */
  740. return MMU_STATUS_OK;
  741. }
  742. if (timeout-- == 0) {
  743. break;
  744. }
  745. /* Wait for 1 millisecond. */
  746. Delay(1);
  747. }
  748. return MMU_STATUS_OK;
  749. }
  750. static enum MMUStatus ReleaseMutex(void *mtx) {
  751. /* Release the mutex. */
  752. mutex_unlock(mtx);
  753. return MMU_STATUS_OK;
  754. }
  755. static inline enum MMUStatus QueryProcessPageTable(void *logical,
  756. unsigned long long *address) {
  757. unsigned long lg = (unsigned long)logical;
  758. unsigned long offset = lg & ~PAGE_MASK;
  759. struct vm_area_struct *vma;
  760. spinlock_t *ptl;
  761. pgd_t *pgd;
  762. pud_t *pud;
  763. pmd_t *pmd;
  764. pte_t *pte;
  765. if (is_vmalloc_addr(logical)) {
  766. /* vmalloc area. */
  767. *address = page_to_phys(vmalloc_to_page(logical)) | offset;
  768. return MMU_STATUS_OK;
  769. } else if (virt_addr_valid(lg)) {
  770. /* Kernel logical address. */
  771. *address = virt_to_phys(logical);
  772. return MMU_STATUS_OK;
  773. } else {
  774. /* Try user VM area. */
  775. if (!current->mm)
  776. return MMU_STATUS_NOT_FOUND;
  777. #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0)
  778. down_read(&current->mm->mmap_lock);
  779. #else
  780. down_read(&current->mm->mmap_sem);
  781. #endif
  782. vma = find_vma(current->mm, lg);
  783. #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0)
  784. up_read(&current->mm->mmap_lock);
  785. #else
  786. up_read(&current->mm->mmap_sem);
  787. #endif
  788. /* To check if mapped to user. */
  789. if (!vma)
  790. return MMU_STATUS_NOT_FOUND;
  791. pgd = pgd_offset(current->mm, lg);
  792. if (pgd_none(*pgd) || pgd_bad(*pgd))
  793. return MMU_STATUS_NOT_FOUND;
  794. #if (defined(CONFIG_CPU_CSKYV2) || defined(CONFIG_X86)) \
  795. && LINUX_VERSION_CODE >= KERNEL_VERSION (4,12,0)
  796. pud = pud_offset((p4d_t*)pgd, lg);
  797. #elif (defined(CONFIG_CPU_CSKYV2) || defined(CONFIG_RISCV)) \
  798. && LINUX_VERSION_CODE >= KERNEL_VERSION (4,11,0)
  799. pud = pud_offset((p4d_t*)pgd, lg);
  800. #else
  801. pud = pud_offset(pgd, lg);
  802. #endif
  803. if (pud_none(*pud) || pud_bad(*pud))
  804. return MMU_STATUS_NOT_FOUND;
  805. pmd = pmd_offset(pud, lg);
  806. if (pmd_none(*pmd) || pmd_bad(*pmd))
  807. return MMU_STATUS_NOT_FOUND;
  808. pte = pte_offset_map_lock(current->mm, pmd, lg, &ptl);
  809. if (!pte) {
  810. spin_unlock(ptl);
  811. return MMU_STATUS_NOT_FOUND;
  812. }
  813. if (!pte_present(*pte)) {
  814. pte_unmap_unlock(pte, ptl);
  815. return MMU_STATUS_NOT_FOUND;
  816. }
  817. *address = (pte_pfn(*pte) << PAGE_SHIFT) | offset;
  818. pte_unmap_unlock(pte, ptl);
  819. *address -= gBaseDDRHw;
  820. //MMUDEBUG(" QueryProcessPageTable map: virt %p -> %p\n", logical, (void *)*address);
  821. return MMU_STATUS_OK;
  822. }
  823. }
  824. static inline int GetProcessID(void) {
  825. return current->tgid;
  826. }
  827. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
  828. static inline int is_vmalloc_addr(void *addr) {
  829. unsigned long long addr = (unsigned long long)Addr;
  830. return addr >= VMALLOC_START && addr < VMALLOC_END;
  831. }
  832. #endif
  833. static enum MMUStatus GetPhysicalAddress(void *logical,
  834. unsigned long long *address) {
  835. enum MMUStatus status;
  836. status = QueryProcessPageTable(logical, address);
  837. return status;
  838. }
  839. static enum MMUStatus GetPageEntry(struct MMUNode *node,
  840. unsigned int **page_table_entry,
  841. unsigned int i) {
  842. int num = node->mtlb_start * MMU_STLB_4K_ENTRY_NUM +
  843. node->stlb_start + i;
  844. *page_table_entry = (unsigned int*)g_mmu->stlb_virtual + num;
  845. return MMU_STATUS_OK;
  846. }
  847. static enum MMUStatus SetupDynamicSpace(void) {
  848. int i;
  849. enum MMUStatus status;
  850. unsigned int stlb_entry;
  851. void *pointer;
  852. unsigned long long address;
  853. dma_addr_t dma_handle;
  854. unsigned int num_entries = MMU_MTLB_ENTRY_NUM;
  855. unsigned int *mtlb_virtual = (unsigned int *)g_mmu->mtlb_virtual;
  856. AcquireMutex(g_mmu->page_table_mutex, MMU_INFINITE);
  857. if(pcie) {
  858. pointer = ioremap(gBaseDDRHw+STLB_PCIE_START_ADDRESS, num_entries*MMU_STLB_4K_SIZE);
  859. g_mmu->stlb_virtual = pointer;
  860. MMUDEBUG(" *****stlb_virtual = %p**%d\n", pointer, num_entries*MMU_STLB_4K_SIZE);
  861. address = STLB_PCIE_START_ADDRESS;
  862. for(i = 0; i < num_entries; i++){
  863. stlb_entry = address
  864. /* 4KB page size */
  865. | (0 << 2)
  866. /* Ignore exception */
  867. | (0 << 1)
  868. /* Present */
  869. | (1 << 0);
  870. WritePageEntry(mtlb_virtual++, stlb_entry);
  871. address += MMU_STLB_4K_SIZE;
  872. }
  873. } else {
  874. g_mmu->stlb_virtual = (void *)((u64)(g_mmu->mtlb_virtual) + MMU_MTLB_SIZE);
  875. g_mmu->stlb_physical = address = g_mmu->mtlb_physical + MMU_MTLB_SIZE;
  876. g_mmu->stlb_size = num_entries * MMU_STLB_4K_SIZE;
  877. for(i = 0; i < num_entries; i++){
  878. stlb_entry = address
  879. /* 4KB page size */
  880. | (0 << 2)
  881. /* Ignore exception */
  882. | (0 << 1)
  883. /* Present */
  884. | (1 << 0);
  885. WritePageEntry(mtlb_virtual++, stlb_entry);
  886. address += MMU_STLB_4K_SIZE;
  887. }
  888. }
  889. ReleaseMutex(g_mmu->page_table_mutex);
  890. /* Initial map info. */
  891. if (simple_map)
  892. SMCreateNodes();
  893. else
  894. CreateNode();
  895. return MMU_STATUS_OK;
  896. onerror:
  897. /* Return status. */
  898. return status;
  899. }
  900. enum MMUStatus MMUInit(volatile unsigned char *hwregs) {
  901. enum MMUStatus status;
  902. unsigned i;
  903. int result;
  904. void *pointer;
  905. if (mmu_init == MMU_TRUE) {
  906. /* All mmu use common table and dev, just initial once*/
  907. pr_notice(" *****MMU Already Initialed*****\n");
  908. return MMU_STATUS_OK;
  909. }
  910. if(!hwregs || (ioread32((void*)(hwregs + MMU_REG_HW_ID))>>16) != 0x4D4D)
  911. return MMU_STATUS_NOT_FOUND;
  912. pr_notice(" *****MMU Init*****\n");
  913. platformdev = platform_device_register_full(&hantro_platform_info);
  914. if(platformdev == NULL) {
  915. pr_err("hantrodec create platform device fail\n");
  916. status = MMU_STATUS_FALSE;
  917. goto onerror;
  918. } else {
  919. pr_info("Create platform device success\n");
  920. }
  921. result = platform_driver_register(&hantro_drm_platform_driver);
  922. pr_notice("Platform driver status is %d\n", result);
  923. /* Allocate memory for the MMU object. */
  924. MMU_ON_ERROR(AllocateMemory(sizeof(struct MMU), &pointer));
  925. ZeroMemory(pointer, sizeof(struct MMU));
  926. g_mmu = pointer;
  927. g_mmu->page_table_mutex = NULL;
  928. /* Create the page table mutex. */
  929. MMU_ON_ERROR(CreateMutex(&g_mmu->page_table_mutex));
  930. for (i = 0; i < MMU_REGION_COUNT;i++) {
  931. MMU_ON_ERROR(CreateMutex(&g_mmu->region[i].node_mutex));
  932. }
  933. mmu_init = MMU_TRUE;
  934. return MMU_STATUS_OK;
  935. onerror:
  936. pr_notice(" *****MMU Init Error*****\n");
  937. return status;
  938. }
  939. enum MMUStatus MMURelease(void *filp, volatile unsigned char *hwregs) {
  940. int i, j;
  941. struct MMUNode *p, *tmp;
  942. unsigned long long address;
  943. unsigned int *page_table_entry;
  944. if(!hwregs || (ioread32((void*)(hwregs + MMU_REG_HW_ID))>>16) != 0x4D4D)
  945. return MMU_STATUS_FALSE;
  946. /* if mmu or TLB not enabled, return */
  947. if (simple_map) {
  948. if(g_mmu == NULL || g_mmu->region[0].simple_map_head == NULL)
  949. return MMU_STATUS_OK;
  950. } else {
  951. if(g_mmu == NULL || g_mmu->region[0].map_head == NULL)
  952. return MMU_STATUS_OK;
  953. }
  954. pr_notice(" *****MMU Release*****\n");
  955. AcquireMutex(g_mmu->page_table_mutex, MMU_INFINITE);
  956. if (simple_map) {
  957. for (i = 0; i < MMU_REGION_COUNT; i++) {
  958. p = g_mmu->region[i].simple_map_head->next;
  959. while(p) {
  960. tmp = p->next;
  961. if(p->filp == (struct file *)filp) {
  962. for(j = 0;j < p->page_count; j++) {
  963. GetPageEntry(p, &page_table_entry, j);
  964. address = 0;
  965. WritePageEntry(page_table_entry, address);
  966. }
  967. SMRemoveNode(i, p->buf_virtual_address, p->process_id);
  968. }
  969. p = tmp;
  970. }
  971. }
  972. } else {
  973. for (i = 0; i < MMU_REGION_COUNT; i++) {
  974. p = g_mmu->region[i].map_head->next;
  975. while(p) {
  976. tmp = p->next;
  977. if(p->filp == (struct file *)filp) {
  978. for(j = 0;j < p->page_count; j++) {
  979. GetPageEntry(p, &page_table_entry, j);
  980. address = 0;
  981. WritePageEntry(page_table_entry, address);
  982. }
  983. RemoveNode(i, p->buf_virtual_address, p->process_id);
  984. }
  985. p = tmp;
  986. }
  987. }
  988. }
  989. ReleaseMutex(g_mmu->page_table_mutex);
  990. return MMU_STATUS_OK;
  991. }
  992. enum MMUStatus MMUCleanup(volatile unsigned char *hwregs[MAX_SUBSYS_NUM][2]) {
  993. int i;
  994. struct MMUNode *p, *tmp;
  995. struct MMUNode *fp;
  996. for (i = 0; i < MAX_SUBSYS_NUM; i++) {
  997. if (hwregs[i][0] != NULL &&
  998. (ioread32((void*)(hwregs[i][0] + MMU_REG_HW_ID))>>16) != 0x4D4D)
  999. return MMU_STATUS_FALSE;
  1000. if (hwregs[i][1] != NULL &&
  1001. (ioread32((void*)(hwregs[i][1] + MMU_REG_HW_ID))>>16) != 0x4D4D)
  1002. return MMU_STATUS_FALSE;
  1003. }
  1004. pr_info(" *****MMU cleanup*****\n");
  1005. if (pcie) {
  1006. if (g_mmu->stlb_virtual)
  1007. iounmap(g_mmu->stlb_virtual);
  1008. if (g_mmu->mtlb_virtual)
  1009. iounmap(g_mmu->mtlb_virtual);
  1010. if (g_mmu->page_table_array)
  1011. iounmap(g_mmu->page_table_array);
  1012. } else {
  1013. if (g_mmu->stlb_virtual)
  1014. dma_free_coherent(&platformdev->dev, g_mmu->stlb_size,
  1015. g_mmu->stlb_virtual, (dma_addr_t)g_mmu->stlb_physical);
  1016. if (g_mmu->mtlb_virtual)
  1017. dma_free_coherent(&platformdev->dev, g_mmu->mtlb_size,
  1018. g_mmu->mtlb_virtual, (dma_addr_t)g_mmu->mtlb_physical);
  1019. if (g_mmu->page_table_array)
  1020. dma_free_coherent(&platformdev->dev, g_mmu->page_table_array_size,
  1021. g_mmu->page_table_array, (dma_addr_t)g_mmu->page_table_array_physical);
  1022. }
  1023. DeleteMutex(g_mmu->page_table_mutex);
  1024. for (i = 0; i < MMU_REGION_COUNT; i++) {
  1025. DeleteMutex(g_mmu->region[i].node_mutex);
  1026. if (simple_map) {
  1027. p = g_mmu->region[i].simple_map_head;
  1028. while(p) {
  1029. tmp = p->next;
  1030. FreeMemory(p);
  1031. p = tmp;
  1032. MMUDEBUG(" *****clean node*****\n");
  1033. }
  1034. } else {
  1035. fp = g_mmu->region[i].free_map_head;
  1036. p = g_mmu->region[i].map_head;
  1037. while(fp) {
  1038. tmp = fp->next;
  1039. FreeMemory(fp);
  1040. fp = tmp;
  1041. MMUDEBUG(" *****clean free node*****\n");
  1042. }
  1043. while(p) {
  1044. tmp = p->next;
  1045. FreeMemory(p);
  1046. p = tmp;
  1047. MMUDEBUG(" *****clean node*****\n");
  1048. }
  1049. }
  1050. }
  1051. FreeMemory(g_mmu);
  1052. platform_device_unregister(platformdev);
  1053. platform_driver_unregister(&hantro_drm_platform_driver);
  1054. pr_info("Unregister platform device.\n");
  1055. for (i = 0; i < MAX_SUBSYS_NUM; i++) {
  1056. if (hwregs[i][0] != NULL)
  1057. iowrite32(0, (void*)(hwregs[i][0] + MMU_REG_CONTROL));
  1058. if (hwregs[i][1] != NULL)
  1059. iowrite32(0, (void*)(hwregs[i][1] + MMU_REG_CONTROL));
  1060. }
  1061. mmu_enable = 0;
  1062. mmu_init = 0;
  1063. return MMU_STATUS_OK;
  1064. }
  1065. /*------------------------------------------------------------------------------
  1066. Function name: MMUEnable
  1067. Description:
  1068. Create TLB, set registers and enable MMU
  1069. For pcie, TLB buffers come from FPGA memory and The distribution is as follows
  1070. MTLB: start from: 0x00100000, size: 4K bits
  1071. page table array: 0x00200000 64 bits
  1072. STLB: 0x00300000 4M bits
  1073. ------------------------------------------------------------------------------*/
  1074. enum MMUStatus MMUEnable(volatile unsigned char *hwregs[MAX_SUBSYS_NUM][2]) {
  1075. enum MMUStatus status;
  1076. unsigned int address;
  1077. unsigned int mutex = MMU_FALSE;
  1078. dma_addr_t dma_handle;
  1079. u32 i = 0;
  1080. u32 address_ext;
  1081. u32 total_table_size = 0;
  1082. if(mmu_enable == MMU_TRUE) {
  1083. pr_info(" *****MMU Already Enabled*****\n");
  1084. return MMU_STATUS_OK;
  1085. }
  1086. pr_info(" *****MMU Enable...*****\n");
  1087. AcquireMutex(g_mmu->page_table_mutex, MMU_INFINITE);
  1088. mutex = MMU_TRUE;
  1089. if(pcie) {
  1090. g_mmu->mtlb_size = MMU_MTLB_SIZE;
  1091. g_mmu->mtlb_virtual = ioremap(gBaseDDRHw+MTLB_PCIE_START_ADDRESS, g_mmu->mtlb_size);
  1092. g_mmu->mtlb_physical = MTLB_PCIE_START_ADDRESS;
  1093. g_mmu->page_table_array = ioremap(gBaseDDRHw+PAGE_PCIE_START_ADDRESS, PAGE_TABLE_ENTRY_SIZE);
  1094. } else {
  1095. /* Allocate the 4K mode MTLB table. */
  1096. total_table_size = MMU_MTLB_SIZE + MMU_MTLB_ENTRY_NUM*MMU_STLB_4K_SIZE;
  1097. g_mmu->mtlb_size = MMU_MTLB_SIZE;
  1098. g_mmu->mtlb_virtual = dma_alloc_coherent(&platformdev->dev, total_table_size,
  1099. &dma_handle, GFP_KERNEL | GFP_DMA);
  1100. MMUDEBUG(" *****g_mmu->mtlb_virtual = 0x%p\n", g_mmu->mtlb_virtual);
  1101. g_mmu->mtlb_physical = (unsigned long long)dma_handle;
  1102. MMUDEBUG(" *****mtlb_physical = 0x%llx\n", (unsigned int)g_mmu->mtlb_physical);
  1103. if(g_mmu->mtlb_virtual == NULL) {
  1104. pr_err("hantrodec alloc buffer fail\n");
  1105. status = MMU_STATUS_FALSE;
  1106. goto onerror;
  1107. }
  1108. g_mmu->page_table_array_size = PAGE_TABLE_ENTRY_SIZE;
  1109. g_mmu->page_table_array = dma_alloc_coherent(&platformdev->dev, g_mmu->page_table_array_size,
  1110. &dma_handle, GFP_KERNEL | GFP_DMA);
  1111. MMUDEBUG(" *****g_mmu->page_table_array = 0x%p\n", g_mmu->page_table_array);
  1112. g_mmu->page_table_array_physical = (unsigned long long)dma_handle;
  1113. MMUDEBUG(" *****page_table_array_physical = 0x%llx\n", (unsigned int)g_mmu->page_table_array_physical);
  1114. if(g_mmu->page_table_array == NULL) {
  1115. pr_err("hantrodec alloc buffer fail\n");
  1116. status = MMU_STATUS_FALSE;
  1117. goto onerror;
  1118. }
  1119. }
  1120. *((unsigned int*)g_mmu->page_table_array) =
  1121. (g_mmu->mtlb_physical & 0xFFFFF000) | (0 << 0);
  1122. *((unsigned int *)g_mmu->page_table_array+1) =
  1123. (u32)(g_mmu->mtlb_physical >> 32)&0xff;
  1124. *((unsigned int *)g_mmu->page_table_array+2) =
  1125. (g_mmu->mtlb_physical & 0xFFFFF000) | (0 << 0);
  1126. *((unsigned int *)g_mmu->page_table_array+3) =
  1127. (u32)(g_mmu->mtlb_physical >> 32)&0xff;
  1128. MMUDEBUG(" Page table array[0]: lsb = 0x%llx\n", ((int *)g_mmu->page_table_array)[0]);
  1129. MMUDEBUG(" msb = 0x%llx\n", ((int *)g_mmu->page_table_array)[1]);
  1130. ZeroMemory(g_mmu->mtlb_virtual, total_table_size);
  1131. ReleaseMutex(g_mmu->page_table_mutex);
  1132. MMU_ON_ERROR(SetupDynamicSpace());
  1133. if(pcie) {
  1134. address = PAGE_PCIE_START_ADDRESS;
  1135. } else {
  1136. address = g_mmu->page_table_array_physical;
  1137. address_ext = ((u32)(g_mmu->page_table_array_physical >> 32))&0xff;
  1138. }
  1139. /* set regs of all MMUs */
  1140. for (i = 0; i < MAX_SUBSYS_NUM; i++) {
  1141. if (hwregs[i][0] != NULL) {
  1142. iowrite32(address, (void*)(hwregs[i][0] + MMU_REG_ADDRESS));
  1143. iowrite32(address_ext, (void *)(hwregs[i][0] + MMU_REG_ADDRESS_MSB));
  1144. iowrite32(0x10000, (void*)(hwregs[i][0] + MMU_REG_PAGE_TABLE_ID));
  1145. iowrite32(0x00000, (void*)(hwregs[i][0] + MMU_REG_PAGE_TABLE_ID));
  1146. iowrite32(1, (void*)(hwregs[i][0] + MMU_REG_CONTROL));
  1147. }
  1148. if (hwregs[i][1] != NULL) {
  1149. iowrite32(address, (void*)(hwregs[i][1] + MMU_REG_ADDRESS));
  1150. iowrite32(address_ext, (void *)(hwregs[i][1] + MMU_REG_ADDRESS_MSB));
  1151. iowrite32(0x10000, (void*)(hwregs[i][1] + MMU_REG_PAGE_TABLE_ID));
  1152. iowrite32(0x00000, (void*)(hwregs[i][1] + MMU_REG_PAGE_TABLE_ID));
  1153. iowrite32(1, (void*)(hwregs[i][1] + MMU_REG_CONTROL));
  1154. }
  1155. }
  1156. mmu_enable = MMU_TRUE;
  1157. return MMU_STATUS_OK;
  1158. onerror:
  1159. if (mutex) {
  1160. ReleaseMutex(g_mmu->page_table_mutex);
  1161. }
  1162. MMUDEBUG(" *****MMU Enable Error*****\n");
  1163. return status;
  1164. }
  1165. /*------------------------------------------------------------------------------
  1166. Function name: MMUFlush
  1167. Description:
  1168. Flush MMU reg to update cache in MMU.
  1169. ------------------------------------------------------------------------------*/
  1170. static enum MMUStatus MMUFlush(u32 core_id, volatile unsigned char *hwregs[MAX_SUBSYS_NUM][2]) {
  1171. enum MMUStatus status;
  1172. unsigned int mutex = MMU_FALSE;
  1173. MMUDEBUG(" *****MMU Flush*****\n");
  1174. AcquireMutex(g_mmu->page_table_mutex, MMU_INFINITE);
  1175. mutex = MMU_TRUE;
  1176. if (hwregs[core_id][0] != NULL) {
  1177. iowrite32(0x10, (void*)(hwregs[core_id][0] + MMU_REG_FLUSH));
  1178. iowrite32(0x00, (void*)(hwregs[core_id][0] + MMU_REG_FLUSH));
  1179. } else {
  1180. pr_err("hantrodec alloc buffer fail\n");
  1181. status = MMU_STATUS_FALSE;
  1182. goto onerror;
  1183. }
  1184. if (hwregs[core_id][1] != NULL) {
  1185. iowrite32(0x10, (void*)(hwregs[core_id][1] + MMU_REG_FLUSH));
  1186. iowrite32(0x00, (void*)(hwregs[core_id][1] + MMU_REG_FLUSH));
  1187. }
  1188. ReleaseMutex(g_mmu->page_table_mutex);
  1189. return MMU_STATUS_OK;
  1190. onerror:
  1191. if (mutex) {
  1192. ReleaseMutex(g_mmu->page_table_mutex);
  1193. }
  1194. MMUDEBUG(" *****MMU Flush Error*****\n");
  1195. return status;
  1196. }
  1197. static enum MMUStatus MMUMemNodeMap(struct addr_desc *addr, struct file *filp) {
  1198. enum MMUStatus status;
  1199. unsigned int page_count = 0;
  1200. unsigned int i = 0;
  1201. struct MMUNode *p;
  1202. unsigned long long address = 0x0;
  1203. unsigned int *page_table_entry;
  1204. enum MMURegion e;
  1205. unsigned int mutex = MMU_FALSE;
  1206. u32 ext_addr;
  1207. u32 page_entry_value = 0;
  1208. MMUDEBUG(" *****MMU Map*****\n");
  1209. AcquireMutex(g_mmu->page_table_mutex, MMU_INFINITE);
  1210. mutex = MMU_TRUE;
  1211. page_count = (addr->size - 1)/PAGE_SIZE + 1;
  1212. GetPhysicalAddress(addr->virtual_address, &address);
  1213. MMUDEBUG(" *****MMU map address*****%x\n", address);
  1214. if(address >= REGION_IN_START &&
  1215. address + addr->size < REGION_IN_END)
  1216. e = MMU_REGION_IN;
  1217. else if(address >= REGION_OUT_START &&
  1218. address + addr->size < REGION_OUT_END)
  1219. e = MMU_REGION_OUT;
  1220. else if(address >= REGION_PRIVATE_START &&
  1221. address + addr->size < REGION_PRIVATE_END)
  1222. e = MMU_REGION_PRIVATE;
  1223. else
  1224. e = MMU_REGION_PUB;
  1225. if (simple_map) {
  1226. MMU_ON_ERROR(SMCheckAddress(e, addr->virtual_address));
  1227. SMCreateNode(e, &p, page_count);
  1228. MMUDEBUG(" *****Node map size*****%d\n", page_count);
  1229. p->buf_virtual_address = addr->virtual_address;
  1230. p->process_id = GetProcessID();
  1231. p->filp = filp;
  1232. p->mtlb_start = ((address + map_shift) >> MMU_MTLB_SHIFT);
  1233. p->stlb_start = ((address + map_shift) >> MMU_STLB_4K_SHIFT ) & 0x3FF;
  1234. p->mtlb_end = (page_count + p->stlb_start) / MMU_STLB_4K_ENTRY_NUM +
  1235. p->mtlb_start;
  1236. p->stlb_end = (page_count + p->stlb_start) % MMU_STLB_4K_ENTRY_NUM;
  1237. p->page_count = page_count;
  1238. for(i = 0;i < page_count; i++) {
  1239. GetPhysicalAddress(addr->virtual_address + i * PAGE_SIZE, &address);
  1240. GetPageEntry(p, &page_table_entry, i);
  1241. ext_addr = ((u32)(address>>32))&0xff;
  1242. page_entry_value = (address & 0xFFFFF000)
  1243. /* ext address , physical address bits [39,32]*/
  1244. | (ext_addr << 4)
  1245. /* writable */
  1246. | (1 << 2)
  1247. /* Ignore exception */
  1248. | (0 << 1)
  1249. /* Present */
  1250. | (1 << 0);
  1251. WritePageEntry(page_table_entry, page_entry_value);
  1252. }
  1253. /* Purpose of Bare_metal mode: input bus address==mmu address*/
  1254. addr->bus_address = p->mtlb_start << MMU_MTLB_SHIFT
  1255. | p->stlb_start << MMU_STLB_4K_SHIFT;
  1256. } else {
  1257. MMU_ON_ERROR(FindFreeNode(e, &p, page_count));
  1258. SplitFreeNode(e, &p, page_count);
  1259. MMUDEBUG(" *****Node map size*****%d\n", p->page_count);
  1260. p->buf_virtual_address = addr->virtual_address;
  1261. p->process_id = GetProcessID();
  1262. p->filp = filp;
  1263. for(i = 0;i < page_count; i++) {
  1264. GetPhysicalAddress(addr->virtual_address + i * PAGE_SIZE, &address);
  1265. GetPageEntry(p, &page_table_entry, i);
  1266. ext_addr = ((u32)(address>>32))&0xff;
  1267. page_entry_value = (address & 0xFFFFF000)
  1268. /* ext address , physical address bits [39,32]*/
  1269. | (ext_addr << 4)
  1270. /* writable */
  1271. | (1 << 2)
  1272. /* Ignore exception */
  1273. | (0 << 1)
  1274. /* Present */
  1275. | (1 << 0);
  1276. WritePageEntry(page_table_entry, page_entry_value);
  1277. }
  1278. addr->bus_address = p->mtlb_start << MMU_MTLB_SHIFT
  1279. | p->stlb_start << MMU_STLB_4K_SHIFT;
  1280. }
  1281. MMUDEBUG(" MMU_MTLB_SHIFT %d MMU_STLB_4K_SHIFT %d\n", MMU_MTLB_SHIFT, MMU_STLB_4K_SHIFT);
  1282. MMUDEBUG(" MMUMemNodeMap map total %d pages in region %d\nMTLB/STLB starts %d/%d, MTLB/STLB ends %d/%d\n",
  1283. page_count, (u32)e, p->mtlb_start, p->stlb_start, p->mtlb_end, p->stlb_end);
  1284. MMUDEBUG(" MMUMemNodeMap map %p -> 0x%08x\n", addr->virtual_address, addr->bus_address);
  1285. ReleaseMutex(g_mmu->page_table_mutex);
  1286. return MMU_STATUS_OK;
  1287. onerror:
  1288. if (mutex) {
  1289. ReleaseMutex(g_mmu->page_table_mutex);
  1290. }
  1291. MMUDEBUG(" *****MMU Map Error*****\n");
  1292. return status;
  1293. }
  1294. static enum MMUStatus MMUMemNodeUnmap(struct addr_desc *addr) {
  1295. unsigned int i;
  1296. unsigned long long address = 0x0;
  1297. unsigned int *page_table_entry;
  1298. int process_id = GetProcessID();
  1299. enum MMURegion e = MMU_REGION_COUNT;
  1300. enum MMUStatus status = MMU_STATUS_OUT_OF_MEMORY;
  1301. struct MMUNode *p;
  1302. unsigned int mutex = MMU_FALSE;
  1303. MMUDEBUG(" *****MMU Unmap*****\n");
  1304. AcquireMutex(g_mmu->page_table_mutex, MMU_INFINITE);
  1305. mutex = MMU_TRUE;
  1306. GetPhysicalAddress(addr->virtual_address, &address);
  1307. if(address >= REGION_IN_START &&
  1308. address < REGION_IN_END)
  1309. e = MMU_REGION_IN;
  1310. else if(address >= REGION_OUT_START &&
  1311. address < REGION_OUT_END)
  1312. e = MMU_REGION_OUT;
  1313. else if(address >= REGION_PRIVATE_START &&
  1314. address < REGION_PRIVATE_END)
  1315. e = MMU_REGION_PRIVATE;
  1316. else
  1317. e = MMU_REGION_PUB;
  1318. if (simple_map)
  1319. p = g_mmu->region[e].simple_map_head->next;
  1320. else
  1321. p = g_mmu->region[e].map_head->next;
  1322. /* Reset STLB of the node */
  1323. while(p) {
  1324. if(p->buf_virtual_address == addr->virtual_address &&
  1325. p->process_id == process_id) {
  1326. for(i = 0;i < p->page_count; i++) {
  1327. GetPageEntry(p, &page_table_entry, i);
  1328. address = 0;
  1329. WritePageEntry(page_table_entry, address);
  1330. }
  1331. break;
  1332. }
  1333. p = p->next;
  1334. }
  1335. if(!p)
  1336. goto onerror;
  1337. if (simple_map)
  1338. SMRemoveNode(e, addr->virtual_address, process_id);
  1339. else
  1340. RemoveNode(e, addr->virtual_address, process_id);
  1341. ReleaseMutex(g_mmu->page_table_mutex);
  1342. return MMU_STATUS_OK;
  1343. onerror:
  1344. if (mutex) {
  1345. ReleaseMutex(g_mmu->page_table_mutex);
  1346. }
  1347. MMUDEBUG(" *****MMU Unmap Error*****\n");
  1348. return status;
  1349. }
  1350. enum MMUStatus MMUKernelMemNodeMap(struct kernel_addr_desc *addr) {
  1351. enum MMUStatus status;
  1352. unsigned int page_count = 0;
  1353. unsigned int i = 0;
  1354. struct MMUNode *p;
  1355. unsigned long long address = 0x0;
  1356. unsigned int *page_table_entry;
  1357. enum MMURegion e;
  1358. unsigned int mutex = MMU_FALSE;
  1359. u32 ext_addr;
  1360. u32 page_entry_value = 0;
  1361. MMUDEBUG(" *****MMU Map*****\n");
  1362. AcquireMutex(g_mmu->page_table_mutex, MMU_INFINITE);
  1363. mutex = MMU_TRUE;
  1364. page_count = (addr->size - 1)/PAGE_SIZE + 1;
  1365. address = addr->bus_address;
  1366. MMUDEBUG(" *****MMU map address*****%llx\n", address);
  1367. if(address >= REGION_IN_START &&
  1368. address + addr->size < REGION_IN_END)
  1369. e = MMU_REGION_IN;
  1370. else if(address >= REGION_OUT_START &&
  1371. address + addr->size < REGION_OUT_END)
  1372. e = MMU_REGION_OUT;
  1373. else if(address >= REGION_PRIVATE_START &&
  1374. address + addr->size < REGION_PRIVATE_END)
  1375. e = MMU_REGION_PRIVATE;
  1376. else
  1377. e = MMU_REGION_PUB;
  1378. if (simple_map) {
  1379. //TODO: should check bus addr
  1380. //MMU_ON_ERROR(SMCheckAddress(e, addr->virtual_address));
  1381. SMCreateNode(e, &p, page_count);
  1382. MMUDEBUG(" *****Node map size*****%d\n", page_count);
  1383. p->buf_bus_address = addr->bus_address;
  1384. p->process_id = GetProcessID();
  1385. p->filp = NULL;
  1386. p->mtlb_start = ((address + map_shift) >> MMU_MTLB_SHIFT);
  1387. p->stlb_start = ((address + map_shift) >> MMU_STLB_4K_SHIFT ) & 0x3FF;
  1388. p->mtlb_end = (page_count + p->stlb_start) / MMU_STLB_4K_ENTRY_NUM +
  1389. p->mtlb_start;
  1390. p->stlb_end = (page_count + p->stlb_start) % MMU_STLB_4K_ENTRY_NUM;
  1391. p->page_count = page_count;
  1392. for(i = 0;i < page_count; i++) {
  1393. /* this function used in kernel only, so we think it's a contunuous buffer*/
  1394. address += (i ? PAGE_SIZE : 0);
  1395. GetPageEntry(p, &page_table_entry, i);
  1396. ext_addr = ((u32)(address>>32))&0xff;
  1397. page_entry_value = (address & 0xFFFFF000)
  1398. /* ext address , physical address bits [39,32]*/
  1399. | (ext_addr << 4)
  1400. /* writable */
  1401. | (1 << 2)
  1402. /* Ignore exception */
  1403. | (0 << 1)
  1404. /* Present */
  1405. | (1 << 0);
  1406. WritePageEntry(page_table_entry, page_entry_value);
  1407. }
  1408. /* Purpose of Bare_metal mode: input bus address==mmu address*/
  1409. addr->mmu_bus_address = p->mtlb_start << MMU_MTLB_SHIFT
  1410. | p->stlb_start << MMU_STLB_4K_SHIFT;
  1411. } else {
  1412. MMU_ON_ERROR(FindFreeNode(e, &p, page_count));
  1413. SplitFreeNode(e, &p, page_count);
  1414. MMUDEBUG(" *****Node map size*****%d\n", p->page_count);
  1415. p->buf_bus_address = addr->bus_address;
  1416. p->process_id = GetProcessID();
  1417. p->filp = NULL;
  1418. for(i = 0;i < page_count; i++) {
  1419. /* this function used in kernel only, so we think it's a contunuous buffer*/
  1420. address += (i ? PAGE_SIZE : 0);
  1421. GetPageEntry(p, &page_table_entry, i);
  1422. ext_addr = ((u32)(address>>32))&0xff;
  1423. page_entry_value = (address & 0xFFFFF000)
  1424. /* ext address , physical address bits [39,32]*/
  1425. | (ext_addr << 4)
  1426. /* writable */
  1427. | (1 << 2)
  1428. /* Ignore exception */
  1429. | (0 << 1)
  1430. /* Present */
  1431. | (1 << 0);
  1432. WritePageEntry(page_table_entry, page_entry_value);
  1433. }
  1434. addr->mmu_bus_address = p->mtlb_start << MMU_MTLB_SHIFT
  1435. | p->stlb_start << MMU_STLB_4K_SHIFT;
  1436. }
  1437. MMUDEBUG(" KERNEL MMU_MTLB_SHIFT %d MMU_STLB_4K_SHIFT %d\n", MMU_MTLB_SHIFT, MMU_STLB_4K_SHIFT);
  1438. MMUDEBUG(" MMUKernelMemNodeMap map total %d pages in region %d\nMTLB/STLB starts %d/%d, MTLB/STLB ends %d/%d\n",
  1439. page_count, (u32)e, p->mtlb_start, p->stlb_start, p->mtlb_end, p->stlb_end);
  1440. MMUDEBUG(" MMUKernelMemNodeMap map 0x%llx -> 0x%08x\n", addr->bus_address, addr->mmu_bus_address);
  1441. ReleaseMutex(g_mmu->page_table_mutex);
  1442. return MMU_STATUS_OK;
  1443. onerror:
  1444. if (mutex) {
  1445. ReleaseMutex(g_mmu->page_table_mutex);
  1446. }
  1447. MMUDEBUG(" *****MMU Map Error*****\n");
  1448. return status;
  1449. }
  1450. enum MMUStatus MMUKernelMemNodeUnmap(struct kernel_addr_desc *addr) {
  1451. unsigned int i;
  1452. unsigned long long address = 0x0;
  1453. unsigned int *page_table_entry;
  1454. int process_id = GetProcessID();
  1455. enum MMURegion e = MMU_REGION_COUNT;
  1456. enum MMUStatus status = MMU_STATUS_OUT_OF_MEMORY;
  1457. struct MMUNode *p;
  1458. unsigned int mutex = MMU_FALSE;
  1459. MMUDEBUG(" *****MMU Unmap*****\n");
  1460. AcquireMutex(g_mmu->page_table_mutex, MMU_INFINITE);
  1461. mutex = MMU_TRUE;
  1462. address = addr->bus_address;
  1463. if(address >= REGION_IN_START &&
  1464. address < REGION_IN_END)
  1465. e = MMU_REGION_IN;
  1466. else if(address >= REGION_OUT_START &&
  1467. address < REGION_OUT_END)
  1468. e = MMU_REGION_OUT;
  1469. else if(address >= REGION_PRIVATE_START &&
  1470. address < REGION_PRIVATE_END)
  1471. e = MMU_REGION_PRIVATE;
  1472. else
  1473. e = MMU_REGION_PUB;
  1474. if (simple_map)
  1475. p = g_mmu->region[e].simple_map_head->next;
  1476. else
  1477. p = g_mmu->region[e].map_head->next;
  1478. /* Reset STLB of the node */
  1479. while(p) {
  1480. if(p->buf_bus_address == addr->bus_address &&
  1481. p->process_id == process_id) {
  1482. for(i = 0;i < p->page_count; i++) {
  1483. GetPageEntry(p, &page_table_entry, i);
  1484. address = 0;
  1485. WritePageEntry(page_table_entry, address);
  1486. }
  1487. break;
  1488. }
  1489. p = p->next;
  1490. }
  1491. if(!p)
  1492. goto onerror;
  1493. if (simple_map)
  1494. SMRemoveKernelNode(e, addr->bus_address, process_id);
  1495. else
  1496. RemoveKernelNode(e, addr->bus_address, process_id);
  1497. ReleaseMutex(g_mmu->page_table_mutex);
  1498. return MMU_STATUS_OK;
  1499. onerror:
  1500. if (mutex) {
  1501. ReleaseMutex(g_mmu->page_table_mutex);
  1502. }
  1503. MMUDEBUG(" *****MMU Unmap Error*****\n");
  1504. return status;
  1505. }
  1506. static long MMUCtlBufferMap(struct file *filp, unsigned long arg) {
  1507. struct addr_desc addr;
  1508. long tmp;
  1509. tmp = copy_from_user(&addr, (void*)arg, sizeof(struct addr_desc));
  1510. if (tmp) {
  1511. MMUDEBUG("copy_from_user failed, returned %li\n", tmp);
  1512. return -MMU_EFAULT;
  1513. }
  1514. MMUMemNodeMap(&addr, filp);
  1515. tmp = copy_to_user((void*) arg, &addr, sizeof(struct addr_desc));
  1516. if (tmp) {
  1517. MMUDEBUG("copy_to_user failed, returned %li\n", tmp);
  1518. return -MMU_EFAULT;
  1519. }
  1520. return 0;
  1521. }
  1522. static long MMUCtlBufferUnmap(unsigned long arg) {
  1523. struct addr_desc addr;
  1524. long tmp;
  1525. tmp = copy_from_user(&addr, (void*)arg, sizeof(struct addr_desc));
  1526. if (tmp) {
  1527. MMUDEBUG("copy_from_user failed, returned %li\n", tmp);
  1528. return -MMU_EFAULT;
  1529. }
  1530. MMUMemNodeUnmap(&addr);
  1531. return 0;
  1532. }
  1533. static long MMUCtlFlush(unsigned long arg, volatile unsigned char *hwregs[HXDEC_MAX_CORES][2]) {
  1534. unsigned int core_id;
  1535. long tmp;
  1536. tmp = copy_from_user(&core_id, (void*)arg, sizeof(unsigned int));
  1537. if (tmp) {
  1538. MMUDEBUG("copy_from_user failed, returned %li\n", tmp);
  1539. return -MMU_EFAULT;
  1540. }
  1541. MMUFlush(core_id, hwregs);
  1542. return 0;
  1543. }
  1544. long MMUIoctl(unsigned int cmd, void *filp, unsigned long arg,
  1545. volatile unsigned char *hwregs[HXDEC_MAX_CORES][2]) {
  1546. u32 i = 0;
  1547. for (i = 0; i < MAX_SUBSYS_NUM; i++) {
  1548. if (hwregs[i][0] != NULL &&
  1549. (ioread32((void*)(hwregs[i][0] + MMU_REG_HW_ID))>>16) != 0x4D4D)
  1550. return -MMU_ENOTTY;
  1551. if (hwregs[i][1] != NULL &&
  1552. (ioread32((void*)(hwregs[i][1] + MMU_REG_HW_ID))>>16) != 0x4D4D)
  1553. return -MMU_ENOTTY;
  1554. }
  1555. switch (cmd) {
  1556. case HANTRO_IOCS_MMU_MEM_MAP: {
  1557. return (MMUCtlBufferMap((struct file *)filp, arg));
  1558. }
  1559. case HANTRO_IOCS_MMU_MEM_UNMAP: {
  1560. return (MMUCtlBufferUnmap(arg));
  1561. }
  1562. case HANTRO_IOCS_MMU_FLUSH: {
  1563. return (MMUCtlFlush(arg, hwregs));
  1564. }
  1565. default:
  1566. return -MMU_ENOTTY;
  1567. }
  1568. }
  1569. void MMURestore(volatile unsigned char *hwregs[MAX_SUBSYS_NUM][2])
  1570. {
  1571. if (g_mmu == NULL)
  1572. return;
  1573. int i;
  1574. unsigned int address;
  1575. u32 address_ext;
  1576. address = g_mmu->page_table_array_physical;
  1577. address_ext = ((u32)(g_mmu->page_table_array_physical >> 32))&0xff;
  1578. for (i = 0; i < MAX_SUBSYS_NUM; i++) {
  1579. if (hwregs[i][0] != NULL) {
  1580. iowrite32(address, (void*)(hwregs[i][0] + MMU_REG_ADDRESS));
  1581. iowrite32(address_ext, (void *)(hwregs[i][0] + MMU_REG_ADDRESS_MSB));
  1582. iowrite32(0x10000, (void*)(hwregs[i][0] + MMU_REG_PAGE_TABLE_ID));
  1583. iowrite32(0x00000, (void*)(hwregs[i][0] + MMU_REG_PAGE_TABLE_ID));
  1584. iowrite32(1, (void*)(hwregs[i][0] + MMU_REG_CONTROL));
  1585. }
  1586. if (hwregs[i][1] != NULL) {
  1587. iowrite32(address, (void*)(hwregs[i][1] + MMU_REG_ADDRESS));
  1588. iowrite32(address_ext, (void *)(hwregs[i][1] + MMU_REG_ADDRESS_MSB));
  1589. iowrite32(0x10000, (void*)(hwregs[i][1] + MMU_REG_PAGE_TABLE_ID));
  1590. iowrite32(0x00000, (void*)(hwregs[i][1] + MMU_REG_PAGE_TABLE_ID));
  1591. iowrite32(1, (void*)(hwregs[i][1] + MMU_REG_CONTROL));
  1592. }
  1593. }
  1594. }