hantro_vcmd_freertos.c 133 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2014 - 2021 VERISILICON
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (C) 2014 - 2021 VERISILICON
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program; if not, write to the Free Software Foundation,
  43. * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  44. *
  45. *****************************************************************************
  46. *
  47. * Note: This software is released under dual MIT and GPL licenses. A
  48. * recipient may use this file under the terms of either the MIT license or
  49. * GPL License. If you wish to use only one license not the other, you can
  50. * indicate your decision by deleting one of the above license notices in your
  51. * version of this file.
  52. *
  53. *****************************************************************************/
  54. /*------------------------------------------------------------------------------
  55. -- Abstract : vc8000 Vcmd device driver (kernel module)
  56. ------------------------------------------------------------------------------*/
  57. /* our own stuff */
  58. #include "vcmdswhwregisters.h"
  59. #include "bidirect_list.h"
  60. #include "hantrovcmd.h"
  61. #include "subsys.h"
  62. #include "io_tools.h"
  63. #include "osal.h"
  64. #include "memalloc_freertos.h"
  65. //Netint xtensa cpu and FreeRTOS OS
  66. #include "xtensa_api.h"
  67. //#include "../src/libxmp/xmp-library.h" //For atomic operations
  68. #include <xtensa/xtruntime.h> //interrupt for xtensa
  69. /*
  70. * Macros to help debugging
  71. */
  72. #undef PDEBUG /* undef it, just in case */
  73. #ifdef HANTRO_VCMD_DRIVER_DEBUG
  74. # ifdef __KERNEL__
  75. /* This one if debugging is on, and kernel space */
  76. # define PDEBUG(fmt, args...) printk( KERN_INFO "vc8000_vcmd: " fmt, ## args)
  77. # else
  78. /* This one for user space */
  79. # define PDEBUG(fmt, args...) printf(":%d: " fmt, __LINE__ , ## args)
  80. # endif
  81. #else
  82. # define PDEBUG(fmt, args...) /* not debugging: nothing */
  83. #endif
  84. /*-----------------------------------------------------------------------------------------
  85. ************************CPU Xtensa OS FreeRTOS PORTING LAYER*******************************
  86. ------------------------------------------------------------------------------------------*/
  87. static u32 g_vc8000_int_enable_mask = 0;
  88. //VCMD for netint
  89. #define SYS_REG_INT_TOP_BASE (0x02800000)
  90. //ENCODER
  91. #if 0
  92. #define CPU_INT_IRQ 8 /* All Encoder Modules' interrupt will be connected to CPU IRQ 8 */
  93. #define SYS_INT_MASK (0x220)
  94. #define SYS_REG_INT_VAL (SYS_REG_INT_TOP_BASE + 0x3c)
  95. #define SYS_REG_INT_STAT (SYS_REG_INT_TOP_BASE + 0x40)
  96. #define SYS_REG_INT_EN (SYS_REG_INT_TOP_BASE + 0x44)
  97. #else
  98. //DECODER
  99. #define CPU_INT_IRQ 9
  100. #define SYS_INT_MASK (0x001)
  101. #define SYS_REG_INT_VAL (SYS_REG_INT_TOP_BASE + 0x48)
  102. #define SYS_REG_INT_STAT (SYS_REG_INT_TOP_BASE + 0x4c)
  103. #define SYS_REG_INT_EN (SYS_REG_INT_TOP_BASE + 0x50)
  104. #endif
  105. /*------------------------------------------------------------------------
  106. *****************************VCMD CONFIGURATION BY CUSTOMER********************************
  107. -------------------------------------------------------------------------*/
  108. //video encoder vcmd configuration
  109. #define VCMD_ENC_IO_ADDR_0 0x90000 /*customer specify according to own platform*/
  110. #define VCMD_ENC_IO_SIZE_0 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  111. #define VCMD_ENC_INT_PIN_0 -1
  112. #define VCMD_ENC_MODULE_TYPE_0 0
  113. #define VCMD_ENC_MODULE_MAIN_ADDR_0 0x0000 /*customer specify according to own platform*/
  114. #define VCMD_ENC_MODULE_DEC400_ADDR_0 0XFFFF /*0xffff means no such kind of submodule*/
  115. #define VCMD_ENC_MODULE_L2CACHE_ADDR_0 0XFFFF
  116. #define VCMD_ENC_MODULE_MMU_ADDR_0 0XFFFF
  117. #define VCMD_ENC_IO_ADDR_1 (0x02300000 + 0x40000) /*customer specify according to own platform*/
  118. #define VCMD_ENC_IO_SIZE_1 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  119. #define VCMD_ENC_INT_PIN_1 5
  120. #define VCMD_ENC_MODULE_TYPE_1 0
  121. #define VCMD_ENC_MODULE_MAIN_ADDR_1 0x1000 /*customer specify according to own platform*/
  122. #define VCMD_ENC_MODULE_DEC400_ADDR_1 0X2000 /*0xffff means no such kind of submodule*/
  123. #define VCMD_ENC_MODULE_L2CACHE_ADDR_1 0XFFFF
  124. #define VCMD_ENC_MODULE_MMU_ADDR_1 0XFFFF
  125. #define VCMD_ENC_IO_ADDR_2 0x92000 /*customer specify according to own platform*/
  126. #define VCMD_ENC_IO_SIZE_2 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  127. #define VCMD_ENC_INT_PIN_2 -1
  128. #define VCMD_ENC_MODULE_TYPE_2 0
  129. #define VCMD_ENC_MODULE_MAIN_ADDR_2 0x0000 /*customer specify according to own platform*/
  130. #define VCMD_ENC_MODULE_DEC400_ADDR_2 0XFFFF /*0xffff means no such kind of submodule*/
  131. #define VCMD_ENC_MODULE_L2CACHE_ADDR_2 0XFFFF
  132. #define VCMD_ENC_MODULE_MMU_ADDR_2 0XFFFF
  133. #define VCMD_ENC_IO_ADDR_3 0x93000 /*customer specify according to own platform*/
  134. #define VCMD_ENC_IO_SIZE_3 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  135. #define VCMD_ENC_INT_PIN_3 -1
  136. #define VCMD_ENC_MODULE_TYPE_3 0
  137. #define VCMD_ENC_MODULE_MAIN_ADDR_3 0x0000 /*customer specify according to own platform*/
  138. #define VCMD_ENC_MODULE_DEC400_ADDR_3 0XFFFF /*0xffff means no such kind of submodule*/
  139. #define VCMD_ENC_MODULE_L2CACHE_ADDR_3 0XFFFF
  140. #define VCMD_ENC_MODULE_MMU_ADDR_3 0XFFFF
  141. //video encoder cutree/IM vcmd configuration
  142. #define VCMD_IM_IO_ADDR_0 0xa00000 /*customer specify according to own platform*/
  143. #define VCMD_IM_IO_SIZE_0 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  144. #define VCMD_IM_INT_PIN_0 -1
  145. #define VCMD_IM_MODULE_TYPE_0 1
  146. #define VCMD_IM_MODULE_MAIN_ADDR_0 0x0000 /*customer specify according to own platform*/
  147. #define VCMD_IM_MODULE_DEC400_ADDR_0 0XFFFF /*0xffff means no such kind of submodule*/
  148. #define VCMD_IM_MODULE_L2CACHE_ADDR_0 0XFFFF
  149. #define VCMD_IM_MODULE_MMU_ADDR_0 0XFFFF
  150. #define VCMD_IM_IO_ADDR_1 (0x02300000 + 0x44000) /*customer specify according to own platform*/
  151. #define VCMD_IM_IO_SIZE_1 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  152. #define VCMD_IM_INT_PIN_1 9
  153. #define VCMD_IM_MODULE_TYPE_1 1
  154. #define VCMD_IM_MODULE_MAIN_ADDR_1 0x1000 /*customer specify according to own platform*/
  155. #define VCMD_IM_MODULE_DEC400_ADDR_1 0XFFFF /*0xffff means no such kind of submodule*/
  156. #define VCMD_IM_MODULE_L2CACHE_ADDR_1 0XFFFF
  157. #define VCMD_IM_MODULE_MMU_ADDR_1 0XFFFF
  158. #define VCMD_IM_IO_ADDR_2 0xa2000 /*customer specify according to own platform*/
  159. #define VCMD_IM_IO_SIZE_2 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  160. #define VCMD_IM_INT_PIN_2 -1
  161. #define VCMD_IM_MODULE_TYPE_2 1
  162. #define VCMD_IM_MODULE_MAIN_ADDR_2 0x0000 /*customer specify according to own platform*/
  163. #define VCMD_IM_MODULE_DEC400_ADDR_2 0XFFFF /*0xffff means no such kind of submodule*/
  164. #define VCMD_IM_MODULE_L2CACHE_ADDR_2 0XFFFF
  165. #define VCMD_IM_MODULE_MMU_ADDR_2 0XFFFF
  166. #define VCMD_IM_IO_ADDR_3 0xa3000 /*customer specify according to own platform*/
  167. #define VCMD_IM_IO_SIZE_3 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  168. #define VCMD_IM_INT_PIN_3 -1
  169. #define VCMD_IM_MODULE_TYPE_3 1
  170. #define VCMD_IM_MODULE_MAIN_ADDR_3 0x0000 /*customer specify according to own platform*/
  171. #define VCMD_IM_MODULE_DEC400_ADDR_3 0XFFFF /*0xffff means no such kind of submodule*/
  172. #define VCMD_IM_MODULE_L2CACHE_ADDR_3 0XFFFF
  173. #define VCMD_IM_MODULE_MMU_ADDR_3 0XFFFF
  174. //video decoder vcmd configuration
  175. #define VCMD_DEC_IO_ADDR_0 0x02310000 /*customer specify according to own platform*/
  176. #define VCMD_DEC_IO_SIZE_0 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  177. #define VCMD_DEC_INT_PIN_0 0
  178. #define VCMD_DEC_MODULE_TYPE_0 2
  179. #define VCMD_DEC_MODULE_MAIN_ADDR_0 0x2000 /*customer specify according to own platform*/
  180. #define VCMD_DEC_MODULE_DEC400_ADDR_0 0X6000 /*0xffff means no such kind of submodule*/
  181. #define VCMD_DEC_MODULE_L2CACHE_ADDR_0 0X4000
  182. #define VCMD_DEC_MODULE_MMU_ADDR_0 0XFFFF
  183. #define VCMD_DEC_IO_ADDR_1 0xb1000 /*customer specify according to own platform*/
  184. #define VCMD_DEC_IO_SIZE_1 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  185. #define VCMD_DEC_INT_PIN_1 -1
  186. #define VCMD_DEC_MODULE_TYPE_1 2
  187. #define VCMD_DEC_MODULE_MAIN_ADDR_1 0x0000 /*customer specify according to own platform*/
  188. #define VCMD_DEC_MODULE_DEC400_ADDR_1 0XFFFF /*0xffff means no such kind of submodule*/
  189. #define VCMD_DEC_MODULE_L2CACHE_ADDR_1 0XFFFF
  190. #define VCMD_DEC_MODULE_MMU_ADDR_1 0XFFFF
  191. #define VCMD_DEC_IO_ADDR_2 0xb2000 /*customer specify according to own platform*/
  192. #define VCMD_DEC_IO_SIZE_2 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  193. #define VCMD_DEC_INT_PIN_2 -1
  194. #define VCMD_DEC_MODULE_TYPE_2 2
  195. #define VCMD_DEC_MODULE_MAIN_ADDR_2 0x0000 /*customer specify according to own platform*/
  196. #define VCMD_DEC_MODULE_DEC400_ADDR_2 0XFFFF /*0xffff means no such kind of submodule*/
  197. #define VCMD_DEC_MODULE_L2CACHE_ADDR_2 0XFFFF
  198. #define VCMD_DEC_MODULE_MMU_ADDR_2 0XFFFF
  199. #define VCMD_DEC_IO_ADDR_3 0xb3000 /*customer specify according to own platform*/
  200. #define VCMD_DEC_IO_SIZE_3 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  201. #define VCMD_DEC_INT_PIN_3 -1
  202. #define VCMD_DEC_MODULE_TYPE_3 2
  203. #define VCMD_DEC_MODULE_MAIN_ADDR_3 0x0000 /*customer specify according to own platform*/
  204. #define VCMD_DEC_MODULE_DEC400_ADDR_3 0XFFFF /*0xffff means no such kind of submodule*/
  205. #define VCMD_DEC_MODULE_L2CACHE_ADDR_3 0XFFFF
  206. #define VCMD_DEC_MODULE_MMU_ADDR_3 0XFFFF
  207. //JPEG encoder vcmd configuration
  208. #define VCMD_JPEGE_IO_ADDR_0 0x90000 /*customer specify according to own platform*/
  209. #define VCMD_JPEGE_IO_SIZE_0 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  210. #define VCMD_JPEGE_INT_PIN_0 -1
  211. #define VCMD_JPEGE_MODULE_TYPE_0 3
  212. #define VCMD_JPEGE_MODULE_MAIN_ADDR_0 0x1000 /*customer specify according to own platform*/
  213. #define VCMD_JPEGE_MODULE_DEC400_ADDR_0 0XFFFF /*0xffff means no such kind of submodule*/
  214. #define VCMD_JPEGE_MODULE_L2CACHE_ADDR_0 0XFFFF
  215. #define VCMD_JPEGE_MODULE_MMU_ADDR_0 0XFFFF
  216. #define VCMD_JPEGE_IO_ADDR_1 0xC1000 /*customer specify according to own platform*/
  217. #define VCMD_JPEGE_IO_SIZE_1 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  218. #define VCMD_JPEGE_INT_PIN_1 -1
  219. #define VCMD_JPEGE_MODULE_TYPE_1 3
  220. #define VCMD_JPEGE_MODULE_MAIN_ADDR_1 0x0000 /*customer specify according to own platform*/
  221. #define VCMD_JPEGE_MODULE_DEC400_ADDR_1 0XFFFF /*0xffff means no such kind of submodule*/
  222. #define VCMD_JPEGE_MODULE_L2CACHE_ADDR_1 0XFFFF
  223. #define VCMD_JPEGE_MODULE_MMU_ADDR_1 0XFFFF
  224. #define VCMD_JPEGE_IO_ADDR_2 0xC2000 /*customer specify according to own platform*/
  225. #define VCMD_JPEGE_IO_SIZE_2 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  226. #define VCMD_JPEGE_INT_PIN_2 -1
  227. #define VCMD_JPEGE_MODULE_TYPE_2 3
  228. #define VCMD_JPEGE_MODULE_MAIN_ADDR_2 0x0000 /*customer specify according to own platform*/
  229. #define VCMD_JPEGE_MODULE_DEC400_ADDR_2 0XFFFF /*0xffff means no such kind of submodule*/
  230. #define VCMD_JPEGE_MODULE_L2CACHE_ADDR_2 0XFFFF
  231. #define VCMD_JPEGE_MODULE_MMU_ADDR_2 0XFFFF
  232. #define VCMD_JPEGE_IO_ADDR_3 0xC3000 /*customer specify according to own platform*/
  233. #define VCMD_JPEGE_IO_SIZE_3 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  234. #define VCMD_JPEGE_INT_PIN_3 -1
  235. #define VCMD_JPEGE_MODULE_TYPE_3 3
  236. #define VCMD_JPEGE_MODULE_MAIN_ADDR_3 0x0000 /*customer specify according to own platform*/
  237. #define VCMD_JPEGE_MODULE_DEC400_ADDR_3 0XFFFF /*0xffff means no such kind of submodule*/
  238. #define VCMD_JPEGE_MODULE_L2CACHE_ADDR_3 0XFFFF
  239. #define VCMD_JPEGE_MODULE_MMU_ADDR_3 0XFFFF
  240. //JPEG decoder vcmd configuration
  241. #define VCMD_JPEGD_IO_ADDR_0 0xD0000 /*customer specify according to own platform*/
  242. #define VCMD_JPEGD_IO_SIZE_0 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  243. #define VCMD_JPEGD_INT_PIN_0 -1
  244. #define VCMD_JPEGD_MODULE_TYPE_0 4
  245. #define VCMD_JPEGD_MODULE_MAIN_ADDR_0 0x0000 /*customer specify according to own platform*/
  246. #define VCMD_JPEGD_MODULE_DEC400_ADDR_0 0XFFFF /*0xffff means no such kind of submodule*/
  247. #define VCMD_JPEGD_MODULE_L2CACHE_ADDR_0 0XFFFF
  248. #define VCMD_JPEGD_MODULE_MMU_ADDR_0 0XFFFF
  249. #define VCMD_JPEGD_IO_ADDR_1 0xD1000 /*customer specify according to own platform*/
  250. #define VCMD_JPEGD_IO_SIZE_1 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  251. #define VCMD_JPEGD_INT_PIN_1 -1
  252. #define VCMD_JPEGD_MODULE_TYPE_1 4
  253. #define VCMD_JPEGD_MODULE_MAIN_ADDR_1 0x0000 /*customer specify according to own platform*/
  254. #define VCMD_JPEGD_MODULE_DEC400_ADDR_1 0XFFFF /*0xffff means no such kind of submodule*/
  255. #define VCMD_JPEGD_MODULE_L2CACHE_ADDR_1 0XFFFF
  256. #define VCMD_JPEGD_MODULE_MMU_ADDR_1 0XFFFF
  257. #define VCMD_JPEGD_IO_ADDR_2 0xD2000 /*customer specify according to own platform*/
  258. #define VCMD_JPEGD_IO_SIZE_2 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  259. #define VCMD_JPEGD_INT_PIN_2 -1
  260. #define VCMD_JPEGD_MODULE_TYPE_2 4
  261. #define VCMD_JPEGD_MODULE_MAIN_ADDR_2 0x0000 /*customer specify according to own platform*/
  262. #define VCMD_JPEGD_MODULE_DEC400_ADDR_2 0XFFFF /*0xffff means no such kind of submodule*/
  263. #define VCMD_JPEGD_MODULE_L2CACHE_ADDR_2 0XFFFF
  264. #define VCMD_JPEGD_MODULE_MMU_ADDR_2 0XFFFF
  265. #define VCMD_JPEGD_IO_ADDR_3 0xD3000 /*customer specify according to own platform*/
  266. #define VCMD_JPEGD_IO_SIZE_3 (ASIC_VCMD_SWREG_AMOUNT * 4) /* bytes */
  267. #define VCMD_JPEGD_INT_PIN_3 -1
  268. #define VCMD_JPEGD_MODULE_TYPE_3 4
  269. #define VCMD_JPEGD_MODULE_MAIN_ADDR_3 0x0000 /*customer specify according to own platform*/
  270. #define VCMD_JPEGD_MODULE_DEC400_ADDR_3 0XFFFF /*0xffff means no such kind of submodule*/
  271. #define VCMD_JPEGD_MODULE_L2CACHE_ADDR_3 0XFFFF
  272. #define VCMD_JPEGD_MODULE_MMU_ADDR_3 0XFFFF
  273. #define NETINT
  274. //#define MAGVII
  275. /*for all vcmds, the core info should be listed here for subsequent use*/
  276. struct vcmd_config vcmd_core_array[] = {
  277. //encoder configuration
  278. #if 0
  279. {VCMD_ENC_IO_ADDR_0,
  280. VCMD_ENC_IO_SIZE_0,
  281. VCMD_ENC_INT_PIN_0,
  282. VCMD_ENC_MODULE_TYPE_0,
  283. VCMD_ENC_MODULE_MAIN_ADDR_0,
  284. VCMD_ENC_MODULE_DEC400_ADDR_0,
  285. VCMD_ENC_MODULE_L2CACHE_ADDR_0,
  286. VCMD_ENC_MODULE_MMU_ADDR_0},
  287. {VCMD_ENC_IO_ADDR_1,
  288. VCMD_ENC_IO_SIZE_1,
  289. VCMD_ENC_INT_PIN_1,
  290. VCMD_ENC_MODULE_TYPE_1,
  291. VCMD_ENC_MODULE_MAIN_ADDR_1,
  292. VCMD_ENC_MODULE_DEC400_ADDR_1,
  293. VCMD_ENC_MODULE_L2CACHE_ADDR_1,
  294. VCMD_ENC_MODULE_MMU_ADDR_1},
  295. {VCMD_ENC_IO_ADDR_2,
  296. VCMD_ENC_IO_SIZE_2,
  297. VCMD_ENC_INT_PIN_2,
  298. VCMD_ENC_MODULE_TYPE_2,
  299. VCMD_ENC_MODULE_MAIN_ADDR_2,
  300. VCMD_ENC_MODULE_DEC400_ADDR_2,
  301. VCMD_ENC_MODULE_L2CACHE_ADDR_2,
  302. VCMD_ENC_MODULE_MMU_ADDR_2},
  303. {VCMD_ENC_IO_ADDR_3,
  304. VCMD_ENC_IO_SIZE_3,
  305. VCMD_ENC_INT_PIN_3,
  306. VCMD_ENC_MODULE_TYPE_3,
  307. VCMD_ENC_MODULE_MAIN_ADDR_3,
  308. VCMD_ENC_MODULE_DEC400_ADDR_3,
  309. VCMD_ENC_MODULE_L2CACHE_ADDR_3,
  310. VCMD_ENC_MODULE_MMU_ADDR_3},
  311. //cutree/IM configuration
  312. {VCMD_IM_IO_ADDR_0,
  313. VCMD_IM_IO_SIZE_0,
  314. VCMD_IM_INT_PIN_0,
  315. VCMD_IM_MODULE_TYPE_0,
  316. VCMD_IM_MODULE_MAIN_ADDR_0,
  317. VCMD_IM_MODULE_DEC400_ADDR_0,
  318. VCMD_IM_MODULE_L2CACHE_ADDR_0,
  319. VCMD_IM_MODULE_MMU_ADDR_0},
  320. {VCMD_IM_IO_ADDR_1,
  321. VCMD_IM_IO_SIZE_1,
  322. VCMD_IM_INT_PIN_1,
  323. VCMD_IM_MODULE_TYPE_1,
  324. VCMD_IM_MODULE_MAIN_ADDR_1,
  325. VCMD_IM_MODULE_DEC400_ADDR_1,
  326. VCMD_IM_MODULE_L2CACHE_ADDR_1,
  327. VCMD_IM_MODULE_MMU_ADDR_1},
  328. {VCMD_IM_IO_ADDR_2,
  329. VCMD_IM_IO_SIZE_2,
  330. VCMD_IM_INT_PIN_2,
  331. VCMD_IM_MODULE_TYPE_2,
  332. VCMD_IM_MODULE_MAIN_ADDR_2,
  333. VCMD_IM_MODULE_DEC400_ADDR_2,
  334. VCMD_IM_MODULE_L2CACHE_ADDR_2,
  335. VCMD_IM_MODULE_MMU_ADDR_2},
  336. {VCMD_IM_IO_ADDR_3,
  337. VCMD_IM_IO_SIZE_3,
  338. VCMD_IM_INT_PIN_3,
  339. VCMD_IM_MODULE_TYPE_3,
  340. VCMD_IM_MODULE_MAIN_ADDR_3,
  341. VCMD_IM_MODULE_DEC400_ADDR_3,
  342. VCMD_IM_MODULE_L2CACHE_ADDR_3,
  343. VCMD_IM_MODULE_MMU_ADDR_3},
  344. #endif
  345. #ifdef NETINT
  346. //decoder configuration
  347. {VCMD_DEC_IO_ADDR_0,
  348. VCMD_DEC_IO_SIZE_0,
  349. VCMD_DEC_INT_PIN_0,
  350. VCMD_DEC_MODULE_TYPE_0,
  351. VCMD_DEC_MODULE_MAIN_ADDR_0,
  352. VCMD_DEC_MODULE_DEC400_ADDR_0,
  353. VCMD_DEC_MODULE_L2CACHE_ADDR_0,
  354. VCMD_DEC_MODULE_MMU_ADDR_0},
  355. #endif
  356. #if 0
  357. {VCMD_DEC_IO_ADDR_1,
  358. VCMD_DEC_IO_SIZE_1,
  359. VCMD_DEC_INT_PIN_1,
  360. VCMD_DEC_MODULE_TYPE_1,
  361. VCMD_DEC_MODULE_MAIN_ADDR_1,
  362. VCMD_DEC_MODULE_DEC400_ADDR_1,
  363. VCMD_DEC_MODULE_L2CACHE_ADDR_1,
  364. VCMD_DEC_MODULE_MMU_ADDR_1},
  365. {VCMD_DEC_IO_ADDR_2,
  366. VCMD_DEC_IO_SIZE_2,
  367. VCMD_DEC_INT_PIN_2,
  368. VCMD_DEC_MODULE_TYPE_2,
  369. VCMD_DEC_MODULE_MAIN_ADDR_2,
  370. VCMD_DEC_MODULE_DEC400_ADDR_2,
  371. VCMD_DEC_MODULE_L2CACHE_ADDR_2,
  372. VCMD_DEC_MODULE_MMU_ADDR_2},
  373. {VCMD_DEC_IO_ADDR_3,
  374. VCMD_DEC_IO_SIZE_3,
  375. VCMD_DEC_INT_PIN_3,
  376. VCMD_DEC_MODULE_TYPE_3,
  377. VCMD_DEC_MODULE_MAIN_ADDR_3,
  378. VCMD_DEC_MODULE_DEC400_ADDR_3,
  379. VCMD_DEC_MODULE_L2CACHE_ADDR_3,
  380. VCMD_DEC_MODULE_MMU_ADDR_3},
  381. #endif
  382. #ifdef MAGVII
  383. //JPEG encoder configuration
  384. {VCMD_JPEGE_IO_ADDR_0,
  385. VCMD_JPEGE_IO_SIZE_0,
  386. VCMD_JPEGE_INT_PIN_0,
  387. VCMD_JPEGE_MODULE_TYPE_0,
  388. VCMD_JPEGE_MODULE_MAIN_ADDR_0,
  389. VCMD_JPEGE_MODULE_DEC400_ADDR_0,
  390. VCMD_JPEGE_MODULE_L2CACHE_ADDR_0,
  391. VCMD_JPEGE_MODULE_MMU_ADDR_0},
  392. #endif
  393. #if 0
  394. {VCMD_JPEGE_IO_ADDR_1,
  395. VCMD_JPEGE_IO_SIZE_1,
  396. VCMD_JPEGE_INT_PIN_1,
  397. VCMD_JPEGE_MODULE_TYPE_1,
  398. VCMD_JPEGE_MODULE_MAIN_ADDR_1,
  399. VCMD_JPEGE_MODULE_DEC400_ADDR_1,
  400. VCMD_JPEGE_MODULE_L2CACHE_ADDR_1,
  401. VCMD_JPEGE_MODULE_MMU_ADDR_1},
  402. {VCMD_JPEGE_IO_ADDR_2,
  403. VCMD_JPEGE_IO_SIZE_2,
  404. VCMD_JPEGE_INT_PIN_2,
  405. VCMD_JPEGE_MODULE_TYPE_2,
  406. VCMD_JPEGE_MODULE_MAIN_ADDR_2,
  407. VCMD_JPEGE_MODULE_DEC400_ADDR_2,
  408. VCMD_JPEGE_MODULE_L2CACHE_ADDR_2,
  409. VCMD_JPEGE_MODULE_MMU_ADDR_2},
  410. {VCMD_JPEGE_IO_ADDR_3,
  411. VCMD_JPEGE_IO_SIZE_3,
  412. VCMD_JPEGE_INT_PIN_3,
  413. VCMD_JPEGE_MODULE_TYPE_3,
  414. VCMD_JPEGE_MODULE_MAIN_ADDR_3,
  415. VCMD_JPEGE_MODULE_DEC400_ADDR_3,
  416. VCMD_JPEGE_MODULE_L2CACHE_ADDR_3,
  417. VCMD_JPEGE_MODULE_MMU_ADDR_3},
  418. //JPEG decoder configuration
  419. {VCMD_JPEGD_IO_ADDR_0,
  420. VCMD_JPEGD_IO_SIZE_0,
  421. VCMD_JPEGD_INT_PIN_0,
  422. VCMD_JPEGD_MODULE_TYPE_0,
  423. VCMD_JPEGD_MODULE_MAIN_ADDR_0,
  424. VCMD_JPEGD_MODULE_DEC400_ADDR_0,
  425. VCMD_JPEGD_MODULE_L2CACHE_ADDR_0,
  426. VCMD_JPEGD_MODULE_MMU_ADDR_0},
  427. {VCMD_JPEGD_IO_ADDR_1,
  428. VCMD_JPEGD_IO_SIZE_1,
  429. VCMD_JPEGD_INT_PIN_1,
  430. VCMD_JPEGD_MODULE_TYPE_1,
  431. VCMD_JPEGD_MODULE_MAIN_ADDR_1,
  432. VCMD_JPEGD_MODULE_DEC400_ADDR_1,
  433. VCMD_JPEGD_MODULE_L2CACHE_ADDR_1,
  434. VCMD_JPEGD_MODULE_MMU_ADDR_1},
  435. {VCMD_JPEGD_IO_ADDR_2,
  436. VCMD_JPEGD_IO_SIZE_2,
  437. VCMD_JPEGD_INT_PIN_2,
  438. VCMD_JPEGD_MODULE_TYPE_2,
  439. VCMD_JPEGD_MODULE_MAIN_ADDR_2,
  440. VCMD_JPEGD_MODULE_DEC400_ADDR_2,
  441. VCMD_JPEGD_MODULE_L2CACHE_ADDR_2,
  442. VCMD_JPEGD_MODULE_MMU_ADDR_2},
  443. {VCMD_JPEGD_IO_ADDR_3,
  444. VCMD_JPEGD_IO_SIZE_3,
  445. VCMD_JPEGD_INT_PIN_3,
  446. VCMD_JPEGD_MODULE_TYPE_3,
  447. VCMD_JPEGD_MODULE_MAIN_ADDR_3,
  448. VCMD_JPEGD_MODULE_DEC400_ADDR_3,
  449. VCMD_JPEGD_MODULE_L2CACHE_ADDR_3,
  450. VCMD_JPEGD_MODULE_MMU_ADDR_3},
  451. #endif
  452. };
  453. /*these size need to be modified according to hw config.*/
  454. #define VCMD_ENCODER_REGISTER_SIZE (479 * 4)
  455. #define VCMD_DECODER_REGISTER_SIZE (512 * 4)
  456. #define VCMD_IM_REGISTER_SIZE (479 * 4)
  457. #define VCMD_JPEG_ENCODER_REGISTER_SIZE (479 * 4)
  458. #define VCMD_JPEG_DECODER_REGISTER_SIZE (512 * 4)
  459. #define MAX_VCMD_NUMBER (MAX_VCMD_TYPE*MAX_SAME_MODULE_TYPE_CORE_NUMBER) //
  460. #define HW_WORK_STATE_PEND 3
  461. #define MAX_CMDBUF_INT_NUMBER 1
  462. #define INT_MIN_SUM_OF_IMAGE_SIZE (4096*2160*MAX_SAME_MODULE_TYPE_CORE_NUMBER*MAX_CMDBUF_INT_NUMBER)
  463. #if PROCESS_MANAGER
  464. #define MAX_PROCESS_CORE_NUMBER 4*8
  465. #define PROCESS_MAX_SUM_OF_IMAGE_SIZE (4096*2160*MAX_SAME_MODULE_TYPE_CORE_NUMBER*MAX_PROCESS_CORE_NUMBER)
  466. #endif
  467. #define MAX_SAME_MODULE_TYPE_CORE_NUMBER 4
  468. /*******************PCIE CONFIG*************************/
  469. #define PCI_VENDOR_ID_HANTRO 0x10ee //0x16c3
  470. #define PCI_DEVICE_ID_HANTRO_PCI 0x8014 // 0x7011
  471. /* Base address got control register */
  472. #define PCI_H2_BAR 4
  473. /* Base address DDR register */
  474. #define PCI_DDR_BAR 0
  475. /*struct pci_dev * */ void *g_vcmd_dev = NULL; /* PCI device structure. */
  476. unsigned long g_vcmd_base_hdwr = 0; /* PCI base register address (Hardware address) */
  477. unsigned long g_vcmd_base_ddr_hw = 0; /* PCI base register address (memalloc) */
  478. u32 g_vcmd_base_len = 0; /* Base register address Length */
  479. static ptr_t /*size_t*/ base_ddr_addr = 0; /*pcie address need to substract this value then can be put to register*/
  480. /********variables declaration related with race condition**********/
  481. #define CMDBUF_MAX_SIZE (512 * 4 * 4)
  482. #define CMDBUF_POOL_TOTAL_SIZE (2 * 1024 * 1024) //approximately=2Mbytes
  483. #define TOTAL_DISCRETE_CMDBUF_NUM (CMDBUF_POOL_TOTAL_SIZE / CMDBUF_MAX_SIZE)
  484. #define CMDBUF_VCMD_REGISTER_TOTAL_SIZE 0x100000 // 1M
  485. #define VCMD_REGISTER_SIZE (128 * 4)
  486. struct noncache_mem
  487. {
  488. u32 *virtualAddress;
  489. ptr_t /* dma_addr_t */ busAddress;
  490. u32 size;
  491. u16 cmdbuf_id;
  492. };
  493. #if PROCESS_MANAGER
  494. struct process_manager_obj
  495. {
  496. /*struct file */ int filp;
  497. u32 total_exe_time;
  498. spinlock_t spinlock;
  499. /* wait_queue_head_t */ sem_t wait_queue;
  500. };
  501. #endif
  502. struct cmdbuf_obj
  503. {
  504. u32 module_type; //current CMDBUF type: input vc8000e=0,IM=1,vc8000d=2,jpege=3, jpegd=4
  505. u32 priority; //current CMDBUFpriority: normal=0, high=1
  506. u32 executing_time; //current CMDBUFexecuting_time=encoded_image_size*(rdoLevel+1)*(rdoq+1);
  507. u32 cmdbuf_size; //current CMDBUF size
  508. u32 *cmdbuf_virtualAddress; //current CMDBUF start virtual address.
  509. ptr_t /*size_t*/ cmdbuf_busAddress; //current CMDBUF start physical address.
  510. u32 *status_virtualAddress; //current status CMDBUF start virtual address.
  511. ptr_t /*size_t*/ status_busAddress; //current status CMDBUF start physical address.
  512. u32 status_size; //current status CMDBUF size
  513. u32 executing_status; //current CMDBUF executing status.
  514. /*struct file */ int filp; //file pointer in the same process.
  515. u16 core_id; //which vcmd core is used.
  516. u16 cmdbuf_id; //used to manage CMDBUF in driver.It is a handle to identify cmdbuf.also is an interrupt vector.position in pool,same as status position.
  517. u8 cmdbuf_data_loaded; //0 means sw has not copied data into this CMDBUF; 1 means sw has copied data into this CMDBUF
  518. u8 cmdbuf_data_linked; //0 :not linked, 1:linked.
  519. volatile u8 cmdbuf_run_done; //if 0,waiting for CMDBUF finish; if 1, op code in CMDBUF has finished one by one. HANTRO_VCMD_IOCH_WAIT_CMDBUF will check this variable.
  520. u8 cmdbuf_need_remove; // if 0, not need to remove CMDBUF; 1 CMDBUF can be removed if it is not the last CMDBUF;
  521. u32 waited; // if 0, the cmd buf hasn't been waited, otherwise, has been waited
  522. u8 has_end_cmdbuf; //if 1, the last opcode is end opCode.
  523. u8 no_normal_int_cmdbuf; //if 1, JMP will not send normal interrupt.
  524. #ifdef PROCESS_MANAGER
  525. struct process_manager_obj* process_manager_obj;
  526. #endif
  527. };
  528. struct hantrovcmd_dev
  529. {
  530. struct vcmd_config vcmd_core_cfg; //config of each core,such as base addr, irq,etc
  531. u32 core_id; //vcmd core id for driver and sw internal use
  532. u32 sw_cmdbuf_rdy_num;
  533. spinlock_t *spinlock;
  534. //wait_queue_head_t * wait_queue;
  535. //wait_queue_head_t * wait_abort_queue;
  536. bi_list list_manager;
  537. volatile u8 *hwregs; /* IO mem base */
  538. u32 reg_mirror[ASIC_VCMD_SWREG_AMOUNT];
  539. u32 duration_without_int; //number of cmdbufs without interrupt.
  540. u8 working_state;
  541. u32 total_exe_time;
  542. u16 status_cmdbuf_id; //used for analyse configuration in cwl.
  543. u32 hw_version_id; /*megvii 0x43421001, later 0x43421102*/
  544. u32 *vcmd_reg_mem_virtualAddress; //start virtual address of vcmd registers memory of CMDBUF.
  545. ptr_t /*size_t*/ vcmd_reg_mem_busAddress; //start physical address of vcmd registers memory of CMDBUF.
  546. u32 vcmd_reg_mem_size; //size of vcmd registers memory of CMDBUF.
  547. };
  548. /*
  549. * Ioctl definitions
  550. */
  551. #define VCMD_HW_ID 0x4342
  552. static struct noncache_mem vcmd_buf_mem_pool = {0};
  553. static struct noncache_mem vcmd_status_buf_mem_pool = {0};
  554. static struct noncache_mem vcmd_registers_mem_pool = {0};
  555. static u16 cmdbuf_used[TOTAL_DISCRETE_CMDBUF_NUM] = {0};
  556. static u16 cmdbuf_used_pos = 0;
  557. static u16 cmdbuf_used_residual = 0;
  558. static struct hantrovcmd_dev *vcmd_manager[MAX_VCMD_TYPE][MAX_VCMD_NUMBER] = {NULL};
  559. bi_list_node *global_cmdbuf_node[TOTAL_DISCRETE_CMDBUF_NUM] = {NULL};
  560. #if PROCESS_MANAGER
  561. bi_list global_process_manager = {NULL};
  562. #endif
  563. static u16 vcmd_position[MAX_VCMD_TYPE] = {0};
  564. static int vcmd_type_core_num[MAX_VCMD_TYPE] = {0};
  565. #define EXECUTING_CMDBUF_ID_ADDR 26
  566. #define VCMD_EXE_CMDBUF_COUNT 3
  567. #define WORKING_STATE_IDLE 0
  568. #define WORKING_STATE_WORKING 1
  569. #define CMDBUF_EXE_STATUS_OK 0
  570. #define CMDBUF_EXE_STATUS_CMDERR 1
  571. #define CMDBUF_EXE_STATUS_BUSERR 2
  572. /*struct semaphore*/ pthread_mutex_t vcmd_reserve_cmdbuf_sem[MAX_VCMD_TYPE]; //for reserve
  573. static void queue_vcmd_init(void *semaphore);
  574. static void queue_vcmd_wakeup(void *semaphore);
  575. static u32 queue_vcmd_wait(void *semaphore);
  576. /***************************TYPE AND FUNCTION DECLARATION****************/
  577. /* here's all the must remember stuff */
  578. static int vcmd_reserve_IO(void);
  579. static void vcmd_release_IO(void);
  580. static void vcmd_reset_asic(struct hantrovcmd_dev *dev);
  581. static void vcmd_reset_current_asic(struct hantrovcmd_dev *dev);
  582. static int allocate_cmdbuf(struct noncache_mem *new_cmdbuf_addr, struct noncache_mem *new_status_cmdbuf_addr);
  583. static void vcmd_link_cmdbuf(struct hantrovcmd_dev *dev, bi_list_node *last_linked_cmdbuf_node);
  584. static void vcmd_start(struct hantrovcmd_dev *dev, bi_list_node *first_linked_cmdbuf_node);
  585. static void create_kernel_process_manager(void);
  586. static irqreturn_t hantrovcmd_isr(/*int irq, */ void *dev_id);
  587. /* Interrupt */
  588. /*********************request_irq, disable_irq, enable_irq need to be provided by customer*********************/
  589. static int RegisterIRQ(i32 i, IRQHandler isr, i32 flag, const char *name, void *data);
  590. static void IntEnableIRQ(u32 irq);
  591. static void IntDisableIRQ(u32 irq);
  592. static void IntClearIRQStatus(u32 irq);
  593. static u32 IntGetIRQStatus(u32 irq);
  594. static inline uint32_t ReadInterruptStatus(void);
  595. /*********************local variable declaration*****************/
  596. static unsigned long vcmd_sram_base = 0;
  597. static unsigned int vcmd_sram_size = 0;
  598. /* and this is our MAJOR; use 0 for dynamic allocation (recommended)*/
  599. static int hantrovcmd_major = 0;
  600. int total_vcmd_core_num = 0;
  601. /* dynamic allocation*/
  602. static struct hantrovcmd_dev *hantrovcmd_data = NULL;
  603. //#define VCMD_DEBUG_INTERNAL
  604. //#define IRQ_SIMULATION
  605. #ifdef IRQ_SIMULATION
  606. struct timer_manager
  607. {
  608. u32 core_id; //vcmd core id for driver and sw internal use
  609. u32 timer_id;
  610. TimerHandle_t * /*struct timer_list * */ timer;
  611. };
  612. static TimerHandle_t /*struct timer_list */ timer[10000];
  613. struct timer_manager timer_reserve[10000];
  614. #if 0
  615. static struct timer_list timer0;
  616. static struct timer_list timer1;
  617. #endif
  618. #endif
  619. //hw_queue can be used for reserve cmdbuf memory
  620. //DECLARE_WAIT_QUEUE_HEAD(vcmd_cmdbuf_memory_wait);
  621. sem_t vcmd_cmdbuf_memory_wait;
  622. //DEFINE_SPINLOCK(vcmd_cmdbuf_alloc_lock);
  623. pthread_mutex_t vcmd_cmdbuf_alloc_lock = PTHREAD_MUTEX_INITIALIZER;
  624. #if PROCESS_MANAGER
  625. //DEFINE_SPINLOCK(vcmd_process_manager_lock);
  626. pthread_mutex_t vcmd_process_manager_lock = PTHREAD_MUTEX_INITIALIZER;
  627. #endif
  628. spinlock_t owner_lock_vcmd[MAX_VCMD_NUMBER];
  629. static u8 vcmd_init_flag = 0;
  630. #ifdef VCMD_POLLING
  631. /*wait_queue_head_t*/ sem_t wait_queue_vcmd[TOTAL_DISCRETE_CMDBUF_NUM /*MAX_VCMD_NUMBER*/];
  632. /*wait_queue_head_t*/ sem_t abort_queue_vcmd[TOTAL_DISCRETE_CMDBUF_NUM /*MAX_VCMD_NUMBER*/];
  633. #else
  634. /*wait_queue_head_t*/ SemaphoreHandle_t wait_queue_vcmd[TOTAL_DISCRETE_CMDBUF_NUM /*MAX_VCMD_NUMBER*/];
  635. /*wait_queue_head_t*/ SemaphoreHandle_t abort_queue_vcmd[TOTAL_DISCRETE_CMDBUF_NUM /*MAX_VCMD_NUMBER*/];
  636. #endif
  637. /* mc wait queue, used in wait_cmdbuf_ready with ANY_CMDBUF_ID. */
  638. static /*wait_queue_head_t*/ /*sem_t*/SemaphoreHandle_t mc_wait_queue;
  639. #if 0
  640. /*allocate non-cacheable DMA memory*/
  641. #define DRIVER_NAME_HANTRO_NON_CACH_MEM "non_cach_memory"
  642. static struct platform_device *noncachable_mem_dev = NULL;
  643. static const struct platform_device_info hantro_platform_info = {
  644. .name = DRIVER_NAME_HANTRO_NON_CACH_MEM,
  645. .id = -1,
  646. .dma_mask = DMA_BIT_MASK(32),
  647. };
  648. static int hantro_noncachable_mem_probe(struct platform_device *pdev)
  649. {
  650. struct device *dev = &pdev->dev;
  651. vcmd_buf_mem_pool.virtualAddress = dma_alloc_coherent(dev,CMDBUF_POOL_TOTAL_SIZE,&vcmd_buf_mem_pool.busAddress, GFP_KERNEL | GFP_DMA);
  652. vcmd_buf_mem_pool.size = CMDBUF_POOL_TOTAL_SIZE;
  653. vcmd_status_buf_mem_pool.virtualAddress = dma_alloc_coherent(dev,CMDBUF_POOL_TOTAL_SIZE,&vcmd_status_buf_mem_pool.busAddress, GFP_KERNEL | GFP_DMA);
  654. vcmd_status_buf_mem_pool.size = CMDBUF_POOL_TOTAL_SIZE;
  655. return 0;
  656. }
  657. static int hantro_noncachable_mem_remove(struct platform_device *pdev)
  658. {
  659. struct device *dev = &pdev->dev;
  660. dma_free_coherent(dev,vcmd_buf_mem_pool.size,vcmd_buf_mem_pool.virtualAddress,vcmd_buf_mem_pool.busAddress);
  661. dma_free_coherent(dev,vcmd_status_buf_mem_pool.size,vcmd_status_buf_mem_pool.virtualAddress,vcmd_status_buf_mem_pool.busAddress);
  662. return 0;
  663. }
  664. static const struct platform_device_id hantro_noncachable_mem_platform_ids[]={
  665. {
  666. .name = DRIVER_NAME_HANTRO_NON_CACH_MEM,
  667. },
  668. {/* sentinel */},
  669. };
  670. static const struct of_device_id hantro_of_match[]={
  671. {
  672. .compatible = "thead,light-vc8000d",
  673. },
  674. {/* sentinel */},
  675. };
  676. static struct platform_driver hantro_noncachable_mem_platform_driver = {
  677. .probe = hantro_noncachable_mem_probe,
  678. .remove = hantro_noncachable_mem_remove,
  679. .driver ={
  680. .name = DRIVER_NAME_HANTRO_NON_CACH_MEM,
  681. .owner = THIS_MODULE,
  682. .of_match_table = hantro_of_match,
  683. },
  684. .id_table = hantro_noncachable_mem_platform_ids,
  685. };
  686. static void init_vcmd_non_cachable_memory_allocate(void)
  687. {
  688. /*create device: This will create a {struct platform_device}, It has a member dev, which is a {struct device} */
  689. noncachable_mem_dev = platform_device_register_full(&hantro_platform_info);
  690. /*when this function is called, the .probe callback is invoked.*/
  691. platform_driver_register(&hantro_noncachable_mem_platform_driver);
  692. }
  693. static void release_vcmd_non_cachable_memory(void)
  694. {
  695. /* when this fucntion is called, .remove callback will be invoked. use it to clean up all resources allocated in .probe.*/
  696. platform_driver_unregister(&hantro_noncachable_mem_platform_driver);
  697. /*destroy the device*/
  698. platform_device_unregister(noncachable_mem_dev);
  699. }
  700. #endif
  701. void PrintInstr(u32 i, u32 instr, u32 *size)
  702. {
  703. if ((instr & 0xF8000000) == OPCODE_WREG)
  704. {
  705. int length = ((instr >> 16) & 0x3FF);
  706. printk(KERN_INFO "current cmdbuf data %d = 0x%08x => [%s %s %d 0x%x]\n", i, instr, "WREG", ((instr >> 26) & 0x1) ? "FIX" : "",
  707. length, (instr & 0xFFFF));
  708. *size = ((length + 2) >> 1) << 1;
  709. }
  710. else if ((instr & 0xF8000000) == OPCODE_END)
  711. {
  712. printk(KERN_INFO "current cmdbuf data %d = 0x%08x => [%s]\n", i, instr, "END");
  713. *size = 2;
  714. }
  715. else if ((instr & 0xF8000000) == OPCODE_NOP)
  716. {
  717. printk(KERN_INFO "current cmdbuf data %d = 0x%08x => [%s]\n", i, instr, "NOP");
  718. *size = 2;
  719. }
  720. else if ((instr & 0xF8000000) == OPCODE_RREG)
  721. {
  722. int length = ((instr >> 16) & 0x3FF);
  723. printk(KERN_INFO "current cmdbuf data %d = 0x%08x => [%s %s %d 0x%x]\n", i, instr, "RREG", ((instr >> 26) & 0x1) ? "FIX" : "",
  724. length, (instr & 0xFFFF));
  725. *size = 4;
  726. }
  727. else if ((instr & 0xF8000000) == OPCODE_JMP)
  728. {
  729. printk(KERN_INFO "current cmdbuf data %d = 0x%08x => [%s %s %s]\n", i, instr, "JMP", ((instr >> 26) & 0x1) ? "RDY" : "",
  730. ((instr >> 25) & 0x1) ? "IE" : "");
  731. *size = 4;
  732. }
  733. else if ((instr & 0xF8000000) == OPCODE_STALL)
  734. {
  735. printk(KERN_INFO "current cmdbuf data %d = 0x%08x => [%s %s 0x%x]\n", i, instr, "STALL", ((instr >> 26) & 0x1) ? "IM" : "",
  736. (instr & 0xFFFF));
  737. *size = 2;
  738. }
  739. else if ((instr & 0xF8000000) == OPCODE_CLRINT)
  740. {
  741. printk(KERN_INFO "current cmdbuf data %d = 0x%08x => [%s %d 0x%x]\n", i, instr, "CLRINT", (instr >> 25) & 0x3,
  742. (instr & 0xFFFF));
  743. *size = 2;
  744. }
  745. else
  746. *size = 1;
  747. }
  748. /**********************************************************************************************************\
  749. *cmdbuf object management
  750. \***********************************************************************************************************/
  751. static struct cmdbuf_obj *create_cmdbuf_obj(void)
  752. {
  753. struct cmdbuf_obj *cmdbuf_obj = NULL;
  754. cmdbuf_obj = vmalloc(sizeof(struct cmdbuf_obj));
  755. if (cmdbuf_obj == NULL)
  756. {
  757. PDEBUG("%s\n", "vmalloc for cmdbuf_obj fail!");
  758. return cmdbuf_obj;
  759. }
  760. memset(cmdbuf_obj, 0, sizeof(struct cmdbuf_obj));
  761. return cmdbuf_obj;
  762. }
  763. static void free_cmdbuf_obj(struct cmdbuf_obj *cmdbuf_obj)
  764. {
  765. if (cmdbuf_obj == NULL)
  766. {
  767. PDEBUG("%s\n", "remove_cmdbuf_obj NULL");
  768. return;
  769. }
  770. //free current cmdbuf_obj
  771. vfree(cmdbuf_obj);
  772. return;
  773. }
  774. static void free_cmdbuf_mem(u16 cmdbuf_id)
  775. {
  776. unsigned long flags;
  777. spin_lock_irqsave(&vcmd_cmdbuf_alloc_lock, flags);
  778. cmdbuf_used[cmdbuf_id] = 0;
  779. cmdbuf_used_residual += 1;
  780. spin_unlock_irqrestore(&vcmd_cmdbuf_alloc_lock, flags);
  781. #if 1
  782. sem_post(&vcmd_cmdbuf_memory_wait);
  783. PDEBUG("Release cmdbuf_id [%d], remain cmd buffer %d\n", cmdbuf_id, vcmd_cmdbuf_memory_wait.value);
  784. #else
  785. wake_up_interruptible_all(&vcmd_cmdbuf_memory_wait);
  786. #endif
  787. }
  788. static bi_list_node *create_cmdbuf_node(void)
  789. {
  790. bi_list_node *current_node = NULL;
  791. struct cmdbuf_obj *cmdbuf_obj = NULL;
  792. struct noncache_mem new_cmdbuf_addr = {0};
  793. struct noncache_mem new_status_cmdbuf_addr = {0};
  794. #if 1
  795. if (sem_wait(&vcmd_cmdbuf_memory_wait))
  796. { //wait cmdbuf, need to sem_wait until some cmdbuf was posted
  797. PDEBUG("%s\n", "wait vcmd_cmdbuf_memory fail!");
  798. return NULL;
  799. }
  800. allocate_cmdbuf(&new_cmdbuf_addr, &new_status_cmdbuf_addr);
  801. #else
  802. if (wait_event_interruptible(vcmd_cmdbuf_memory_wait, allocate_cmdbuf(&new_cmdbuf_addr, &new_status_cmdbuf_addr)))
  803. return NULL;
  804. #endif
  805. cmdbuf_obj = create_cmdbuf_obj();
  806. if (cmdbuf_obj == NULL)
  807. {
  808. PDEBUG("%s\n", "create_cmdbuf_obj fail!");
  809. free_cmdbuf_mem(new_cmdbuf_addr.cmdbuf_id);
  810. return NULL;
  811. }
  812. cmdbuf_obj->cmdbuf_busAddress = new_cmdbuf_addr.busAddress;
  813. cmdbuf_obj->cmdbuf_virtualAddress = new_cmdbuf_addr.virtualAddress;
  814. cmdbuf_obj->cmdbuf_size = new_cmdbuf_addr.size;
  815. cmdbuf_obj->cmdbuf_id = new_cmdbuf_addr.cmdbuf_id;
  816. cmdbuf_obj->status_busAddress = new_status_cmdbuf_addr.busAddress;
  817. cmdbuf_obj->status_virtualAddress = new_status_cmdbuf_addr.virtualAddress;
  818. cmdbuf_obj->status_size = new_status_cmdbuf_addr.size;
  819. current_node = bi_list_create_node();
  820. if (current_node == NULL)
  821. {
  822. PDEBUG("%s\n", "bi_list_create_node fail!");
  823. free_cmdbuf_mem(new_cmdbuf_addr.cmdbuf_id);
  824. free_cmdbuf_obj(cmdbuf_obj);
  825. return NULL;
  826. }
  827. current_node->data = (void *)cmdbuf_obj;
  828. current_node->next = NULL;
  829. current_node->previous = NULL;
  830. return current_node;
  831. }
  832. static void free_cmdbuf_node(bi_list_node *cmdbuf_node)
  833. {
  834. struct cmdbuf_obj *cmdbuf_obj = NULL;
  835. if (cmdbuf_node == NULL)
  836. {
  837. PDEBUG("%s\n", "remove_cmdbuf_node NULL");
  838. return;
  839. }
  840. cmdbuf_obj = (struct cmdbuf_obj *)cmdbuf_node->data;
  841. //free cmdbuf mem in pool
  842. free_cmdbuf_mem(cmdbuf_obj->cmdbuf_id);
  843. //free struct cmdbuf_obj
  844. free_cmdbuf_obj(cmdbuf_obj);
  845. //free current cmdbuf_node entity.
  846. bi_list_free_node(cmdbuf_node);
  847. return;
  848. }
  849. //just remove, not free the node.
  850. static bi_list_node *remove_cmdbuf_node_from_list(bi_list *list, bi_list_node *cmdbuf_node)
  851. {
  852. if (cmdbuf_node == NULL)
  853. {
  854. PDEBUG("%s\n", "remove_cmdbuf_node_from_list NULL");
  855. return NULL;
  856. }
  857. if (cmdbuf_node->next)
  858. {
  859. bi_list_remove_node(list, cmdbuf_node);
  860. return cmdbuf_node;
  861. }
  862. else
  863. {
  864. //the last one, should not be removed.
  865. return NULL;
  866. }
  867. }
  868. //calculate executing_time of each vcmd
  869. static u32 calculate_executing_time_after_node(bi_list_node *exe_cmdbuf_node)
  870. {
  871. u32 time_run_all = 0;
  872. struct cmdbuf_obj *cmdbuf_obj_temp = NULL;
  873. while (1)
  874. {
  875. if (exe_cmdbuf_node == NULL)
  876. break;
  877. cmdbuf_obj_temp = (struct cmdbuf_obj *)exe_cmdbuf_node->data;
  878. time_run_all += cmdbuf_obj_temp->executing_time;
  879. exe_cmdbuf_node = exe_cmdbuf_node->next;
  880. }
  881. return time_run_all;
  882. }
  883. static u32 calculate_executing_time_after_node_high_priority(bi_list_node *exe_cmdbuf_node)
  884. {
  885. u32 time_run_all = 0;
  886. struct cmdbuf_obj *cmdbuf_obj_temp = NULL;
  887. if (exe_cmdbuf_node == NULL)
  888. return time_run_all;
  889. cmdbuf_obj_temp = (struct cmdbuf_obj *)exe_cmdbuf_node->data;
  890. time_run_all += cmdbuf_obj_temp->executing_time;
  891. exe_cmdbuf_node = exe_cmdbuf_node->next;
  892. while (1)
  893. {
  894. if (exe_cmdbuf_node == NULL)
  895. break;
  896. cmdbuf_obj_temp = (struct cmdbuf_obj *)exe_cmdbuf_node->data;
  897. if (cmdbuf_obj_temp->priority == CMDBUF_PRIORITY_NORMAL)
  898. break;
  899. time_run_all += cmdbuf_obj_temp->executing_time;
  900. exe_cmdbuf_node = exe_cmdbuf_node->next;
  901. }
  902. return time_run_all;
  903. }
  904. /**********************************************************************************************************\
  905. *cmdbuf pool management
  906. \***********************************************************************************************************/
  907. static int allocate_cmdbuf(struct noncache_mem *new_cmdbuf_addr, struct noncache_mem *new_status_cmdbuf_addr)
  908. {
  909. unsigned long flags;
  910. spin_lock_irqsave(&vcmd_cmdbuf_alloc_lock, flags);
  911. if (cmdbuf_used_residual == 0)
  912. {
  913. spin_unlock_irqrestore(&vcmd_cmdbuf_alloc_lock, flags);
  914. //no empty cmdbuf
  915. return 0;
  916. }
  917. //there is one cmdbuf at least
  918. while (1)
  919. {
  920. if (cmdbuf_used[cmdbuf_used_pos] == 0 && (global_cmdbuf_node[cmdbuf_used_pos] == NULL))
  921. {
  922. cmdbuf_used[cmdbuf_used_pos] = 1;
  923. cmdbuf_used_residual -= 1;
  924. new_cmdbuf_addr->virtualAddress = vcmd_buf_mem_pool.virtualAddress + cmdbuf_used_pos * CMDBUF_MAX_SIZE / 4;
  925. new_cmdbuf_addr->busAddress = vcmd_buf_mem_pool.busAddress + cmdbuf_used_pos * CMDBUF_MAX_SIZE;
  926. new_cmdbuf_addr->size = CMDBUF_MAX_SIZE;
  927. new_cmdbuf_addr->cmdbuf_id = cmdbuf_used_pos;
  928. new_status_cmdbuf_addr->virtualAddress = vcmd_status_buf_mem_pool.virtualAddress + cmdbuf_used_pos * CMDBUF_MAX_SIZE / 4;
  929. new_status_cmdbuf_addr->busAddress = vcmd_status_buf_mem_pool.busAddress + cmdbuf_used_pos * CMDBUF_MAX_SIZE;
  930. new_status_cmdbuf_addr->size = CMDBUF_MAX_SIZE;
  931. new_status_cmdbuf_addr->cmdbuf_id = cmdbuf_used_pos;
  932. cmdbuf_used_pos++;
  933. if (cmdbuf_used_pos >= TOTAL_DISCRETE_CMDBUF_NUM)
  934. cmdbuf_used_pos = 0;
  935. spin_unlock_irqrestore(&vcmd_cmdbuf_alloc_lock, flags);
  936. return 1;
  937. }
  938. else
  939. {
  940. cmdbuf_used_pos++;
  941. if (cmdbuf_used_pos >= TOTAL_DISCRETE_CMDBUF_NUM)
  942. cmdbuf_used_pos = 0;
  943. }
  944. }
  945. return 0;
  946. }
  947. static bi_list_node *get_cmdbuf_node_in_list_by_addr(/*size_t*/ ptr_t cmdbuf_addr, bi_list *list)
  948. {
  949. bi_list_node *new_cmdbuf_node = NULL;
  950. struct cmdbuf_obj *cmdbuf_obj = NULL;
  951. new_cmdbuf_node = list->head;
  952. while (1)
  953. {
  954. if (new_cmdbuf_node == NULL)
  955. return NULL;
  956. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  957. if (((cmdbuf_obj->cmdbuf_busAddress - base_ddr_addr) <= cmdbuf_addr) && (((cmdbuf_obj->cmdbuf_busAddress - base_ddr_addr + cmdbuf_obj->cmdbuf_size) > cmdbuf_addr)))
  958. {
  959. return new_cmdbuf_node;
  960. }
  961. new_cmdbuf_node = new_cmdbuf_node->next;
  962. }
  963. return NULL;
  964. }
  965. static int wait_abort_rdy(struct hantrovcmd_dev *dev)
  966. {
  967. return dev->working_state == WORKING_STATE_IDLE;
  968. }
  969. static inline void increase_vcmd_position(u32 module_type)
  970. {
  971. vcmd_position[module_type]++;
  972. if (vcmd_position[module_type] >= vcmd_type_core_num[module_type])
  973. vcmd_position[module_type] = 0;
  974. }
  975. static inline int vcmd_is_free(struct hantrovcmd_dev *dev)
  976. {
  977. bi_list *list = NULL;
  978. struct cmdbuf_obj *cmdbuf_obj_temp = NULL;
  979. list = &dev->list_manager;
  980. if (dev->list_manager.tail == NULL)
  981. {
  982. //no vcmd_buf is linked
  983. return 1;
  984. }
  985. cmdbuf_obj_temp = (struct cmdbuf_obj *)list->tail->data;
  986. if(cmdbuf_obj_temp->cmdbuf_run_done == 1)
  987. {
  988. //last vcmd_buf is done.
  989. return 1;
  990. }
  991. return 0;
  992. }
  993. static int vcmd_get_executing_time(struct hantrovcmd_dev *dev, int priority)
  994. {
  995. bi_list *list = NULL;
  996. bi_list_node *curr_cmdbuf_node = NULL;
  997. struct cmdbuf_obj *cmdbuf_obj_temp = NULL;
  998. ptr_t exe_cmdbuf_addr = 0;
  999. unsigned long flags = 0;
  1000. u32 cmdbuf_id = 0;
  1001. list = &dev->list_manager;
  1002. //read executing cmdbuf address
  1003. if (dev->hw_version_id <= HW_ID_1_0_C)
  1004. {
  1005. exe_cmdbuf_addr = VCMDGetAddrRegisterValue((const void *)dev->hwregs, dev->reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR);
  1006. spin_lock_irqsave(dev->spinlock, flags);
  1007. //get the executing cmdbuf node.
  1008. curr_cmdbuf_node = get_cmdbuf_node_in_list_by_addr(exe_cmdbuf_addr, list);
  1009. }
  1010. else
  1011. {
  1012. cmdbuf_id = *(dev->vcmd_reg_mem_virtualAddress + EXECUTING_CMDBUF_ID_ADDR + 1);
  1013. if (cmdbuf_id >= TOTAL_DISCRETE_CMDBUF_NUM || cmdbuf_id == 0)
  1014. {
  1015. printk(KERN_ERR "cmdbuf_id greater than the ceiling !!\n");
  1016. return -1;
  1017. }
  1018. spin_lock_irqsave(dev->spinlock, flags);
  1019. //get the executing cmdbuf node.
  1020. curr_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  1021. if (curr_cmdbuf_node == NULL)
  1022. {
  1023. curr_cmdbuf_node = list->head;
  1024. while (1)
  1025. {
  1026. if (curr_cmdbuf_node == NULL)
  1027. break;
  1028. cmdbuf_obj_temp = (struct cmdbuf_obj *)curr_cmdbuf_node->data;
  1029. if (cmdbuf_obj_temp->cmdbuf_data_linked && cmdbuf_obj_temp->cmdbuf_run_done == 0)
  1030. break;
  1031. curr_cmdbuf_node = curr_cmdbuf_node->next;
  1032. }
  1033. }
  1034. }
  1035. //calculate total execute time of this device
  1036. if(priority == CMDBUF_PRIORITY_HIGH)
  1037. dev->total_exe_time = calculate_executing_time_after_node_high_priority(curr_cmdbuf_node);
  1038. else
  1039. dev->total_exe_time = calculate_executing_time_after_node(curr_cmdbuf_node);
  1040. spin_unlock_irqrestore(dev->spinlock, flags);
  1041. return 0;
  1042. }
  1043. static int select_vcmd(bi_list_node *new_cmdbuf_node)
  1044. {
  1045. struct cmdbuf_obj *cmdbuf_obj = NULL;
  1046. bi_list_node *curr_cmdbuf_node = NULL;
  1047. bi_list *list = NULL;
  1048. struct hantrovcmd_dev *dev = NULL;
  1049. struct hantrovcmd_dev *smallest_dev = NULL;
  1050. u32 executing_time = 0xffff;
  1051. int counter = 0;
  1052. unsigned long flags = 0;
  1053. u32 hw_rdy_cmdbuf_num = 0;
  1054. /*size_t*/ ptr_t exe_cmdbuf_addr = 0;
  1055. struct cmdbuf_obj *cmdbuf_obj_temp = NULL;
  1056. u32 cmdbuf_id = 0;
  1057. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  1058. int ret;
  1059. //if there is an empty vcmd
  1060. for(counter=0; counter<vcmd_type_core_num[cmdbuf_obj->module_type]; counter++)
  1061. {
  1062. dev = vcmd_manager[cmdbuf_obj->module_type][vcmd_position[cmdbuf_obj->module_type]];
  1063. increase_vcmd_position(cmdbuf_obj->module_type);
  1064. list = &dev->list_manager;
  1065. spin_lock_irqsave(dev->spinlock, flags);
  1066. if (vcmd_is_free(dev))
  1067. {
  1068. bi_list_insert_node_tail(list, new_cmdbuf_node);
  1069. spin_unlock_irqrestore(dev->spinlock, flags);
  1070. cmdbuf_obj->core_id = dev->core_id;
  1071. return 0;
  1072. }
  1073. spin_unlock_irqrestore(dev->spinlock, flags);
  1074. }
  1075. //another case, tail = executing node, and vcmd=pend state (finish but not generate interrupt)
  1076. for(counter=0; counter<vcmd_type_core_num[cmdbuf_obj->module_type]; counter++)
  1077. {
  1078. dev = vcmd_manager[cmdbuf_obj->module_type][vcmd_position[cmdbuf_obj->module_type]];
  1079. increase_vcmd_position(cmdbuf_obj->module_type);
  1080. list = &dev->list_manager;
  1081. //read executing cmdbuf address
  1082. if (dev->hw_version_id <= HW_ID_1_0_C)
  1083. hw_rdy_cmdbuf_num = vcmd_get_register_value((const void *)dev->hwregs, dev->reg_mirror, HWIF_VCMD_EXE_CMDBUF_COUNT);
  1084. else
  1085. {
  1086. hw_rdy_cmdbuf_num = *(dev->vcmd_reg_mem_virtualAddress + VCMD_EXE_CMDBUF_COUNT);
  1087. if (hw_rdy_cmdbuf_num != dev->sw_cmdbuf_rdy_num)
  1088. hw_rdy_cmdbuf_num += 1;
  1089. }
  1090. if (dev->sw_cmdbuf_rdy_num == hw_rdy_cmdbuf_num)
  1091. {
  1092. spin_lock_irqsave(dev->spinlock, flags);
  1093. bi_list_insert_node_tail(list, new_cmdbuf_node);
  1094. spin_unlock_irqrestore(dev->spinlock, flags);
  1095. cmdbuf_obj->core_id = dev->core_id;
  1096. return 0;
  1097. }
  1098. }
  1099. //there is no idle vcmd,if low priority,calculate exe time, select the least one.
  1100. // or if high priority, calculate the exe time, select the least one and abort it.
  1101. executing_time = 0xffffffff;
  1102. for(counter=0; counter<vcmd_type_core_num[cmdbuf_obj->module_type]; counter++)
  1103. {
  1104. dev = vcmd_manager[cmdbuf_obj->module_type][vcmd_position[cmdbuf_obj->module_type]];
  1105. increase_vcmd_position(cmdbuf_obj->module_type);
  1106. ret = vcmd_get_executing_time(dev, cmdbuf_obj->priority);
  1107. if(ret)
  1108. return ret;
  1109. if (dev->total_exe_time <= executing_time)
  1110. {
  1111. executing_time = dev->total_exe_time;
  1112. smallest_dev = dev;
  1113. }
  1114. }
  1115. if (cmdbuf_obj->priority == CMDBUF_PRIORITY_NORMAL)
  1116. {
  1117. //insert list
  1118. list = &smallest_dev->list_manager;
  1119. spin_lock_irqsave(smallest_dev->spinlock, flags);
  1120. bi_list_insert_node_tail(list, new_cmdbuf_node);
  1121. spin_unlock_irqrestore(smallest_dev->spinlock, flags);
  1122. cmdbuf_obj->core_id = smallest_dev->core_id;
  1123. return 0;
  1124. }
  1125. else
  1126. {
  1127. //CMDBUF_PRIORITY_HIGH
  1128. //abort the vcmd and wait
  1129. vcmd_write_register_value((const void *)smallest_dev->hwregs, smallest_dev->reg_mirror, HWIF_VCMD_START_TRIGGER, 0);
  1130. #if 1
  1131. #if 1
  1132. //use yield
  1133. while(1)
  1134. {
  1135. if (cmdbuf_obj->cmdbuf_run_done)
  1136. break;
  1137. sched_yield();
  1138. }
  1139. #else
  1140. queue_vcmd_wait(&abort_queue_vcmd[cmdbuf_obj->cmdbuf_id]);
  1141. #endif
  1142. #else
  1143. if (wait_event_interruptible(*smallest_dev->wait_abort_queue, wait_abort_rdy(dev)))
  1144. return -ERESTARTSYS;
  1145. #endif
  1146. //need to select inserting position again because hw maybe have run to the next node.
  1147. //CMDBUF_PRIORITY_HIGH
  1148. spin_lock_irqsave(smallest_dev->spinlock, flags);
  1149. curr_cmdbuf_node = smallest_dev->list_manager.head;
  1150. while (1)
  1151. {
  1152. //if list is empty or tail,insert to tail
  1153. if (curr_cmdbuf_node == NULL)
  1154. break;
  1155. cmdbuf_obj_temp = (struct cmdbuf_obj *)curr_cmdbuf_node->data;
  1156. //if find the first node which priority is normal, insert node prior to the node
  1157. if ((cmdbuf_obj_temp->priority == CMDBUF_PRIORITY_NORMAL) && (cmdbuf_obj_temp->cmdbuf_run_done == 0))
  1158. break;
  1159. curr_cmdbuf_node = curr_cmdbuf_node->next;
  1160. }
  1161. bi_list_insert_node_before(list, curr_cmdbuf_node, new_cmdbuf_node);
  1162. cmdbuf_obj->core_id = smallest_dev->core_id;
  1163. spin_unlock_irqrestore(smallest_dev->spinlock, flags);
  1164. return 0;
  1165. }
  1166. return 0;
  1167. }
  1168. #if PROCESS_MANAGER
  1169. static int wait_process_resource_rdy(struct process_manager_obj *process_manager_obj)
  1170. {
  1171. return process_manager_obj->total_exe_time <= PROCESS_MAX_SUM_OF_IMAGE_SIZE;
  1172. }
  1173. #endif
  1174. static long reserve_cmdbuf(/*struct file */ int filp, struct exchange_parameter *input_para)
  1175. {
  1176. bi_list_node *new_cmdbuf_node = NULL;
  1177. struct cmdbuf_obj *cmdbuf_obj = NULL;
  1178. bi_list_node *process_manager_node = NULL;
  1179. #if PROCESS_MANAGER
  1180. struct process_manager_obj *process_manager_obj = NULL;
  1181. #endif
  1182. unsigned long flags = 0;
  1183. input_para->cmdbuf_id = 0;
  1184. if (input_para->cmdbuf_size > CMDBUF_MAX_SIZE)
  1185. {
  1186. return -1;
  1187. }
  1188. PDEBUG("reserve cmdbuf filp %p\n", (void *)filp);
  1189. #if PROCESS_MANAGER
  1190. spin_lock_irqsave(&vcmd_process_manager_lock, flags);
  1191. process_manager_node = global_process_manager.head;
  1192. while (1)
  1193. {
  1194. if (process_manager_node == NULL)
  1195. {
  1196. //should not happen
  1197. printk(KERN_ERR "hantrovcmd: ERROR process_manager_node !!\n");
  1198. spin_unlock_irqrestore(&vcmd_process_manager_lock, flags);
  1199. return -1;
  1200. }
  1201. process_manager_obj = (struct process_manager_obj *)process_manager_node->data;
  1202. PDEBUG("reserve loop: node %p, filp %p\n", (void *)process_manager_node,
  1203. (void *)process_manager_obj->filp);
  1204. if (filp == process_manager_obj->filp)
  1205. {
  1206. spin_lock_irqsave(&process_manager_obj->spinlock, flags);
  1207. process_manager_obj->total_exe_time += input_para->executing_time;
  1208. spin_unlock_irqrestore(&process_manager_obj->spinlock, flags);
  1209. break;
  1210. }
  1211. process_manager_node = process_manager_node->next;
  1212. }
  1213. spin_unlock_irqrestore(&vcmd_process_manager_lock, flags);
  1214. if (wait_event_interruptible(process_manager_obj->wait_queue, wait_process_resource_rdy(process_manager_obj)))
  1215. return -1;
  1216. #endif
  1217. new_cmdbuf_node = create_cmdbuf_node();
  1218. if (new_cmdbuf_node == NULL)
  1219. return -1;
  1220. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  1221. cmdbuf_obj->module_type = input_para->module_type;
  1222. cmdbuf_obj->priority = input_para->priority;
  1223. cmdbuf_obj->executing_time = input_para->executing_time;
  1224. cmdbuf_obj->cmdbuf_size = CMDBUF_MAX_SIZE;
  1225. input_para->cmdbuf_size = CMDBUF_MAX_SIZE;
  1226. cmdbuf_obj->filp = filp;
  1227. #if PROCESS_MANAGER
  1228. cmdbuf_obj->process_manager_obj = process_manager_obj;
  1229. #endif
  1230. input_para->cmdbuf_id = cmdbuf_obj->cmdbuf_id;
  1231. global_cmdbuf_node[input_para->cmdbuf_id] = new_cmdbuf_node;
  1232. return 0;
  1233. }
  1234. static long release_cmdbuf(/*struct file */ int filp, u16 cmdbuf_id)
  1235. {
  1236. struct cmdbuf_obj *cmdbuf_obj = NULL;
  1237. bi_list_node *last_cmdbuf_node = NULL;
  1238. bi_list_node *new_cmdbuf_node = NULL;
  1239. bi_list *list = NULL;
  1240. u32 module_type;
  1241. unsigned long flags;
  1242. struct hantrovcmd_dev *dev = NULL;
  1243. /*get cmdbuf object according to cmdbuf_id*/
  1244. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  1245. if (new_cmdbuf_node == NULL)
  1246. {
  1247. //should not happen
  1248. printk(KERN_ERR "hantrovcmd: ERROR cmdbuf_id !!\n");
  1249. return -1;
  1250. }
  1251. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  1252. if (cmdbuf_obj->filp != filp)
  1253. {
  1254. //should not happen
  1255. printk(KERN_ERR "hantrovcmd: ERROR cmdbuf_id !!\n");
  1256. return -1;
  1257. }
  1258. module_type = cmdbuf_obj->module_type;
  1259. //TODO
  1260. if (down_interruptible(&vcmd_reserve_cmdbuf_sem[module_type]))
  1261. return -ERESTARTSYS;
  1262. dev = &hantrovcmd_data[cmdbuf_obj->core_id];
  1263. //spin_lock_irqsave(dev->spinlock, flags);
  1264. list = &dev->list_manager;
  1265. cmdbuf_obj->cmdbuf_need_remove = 1;
  1266. last_cmdbuf_node = new_cmdbuf_node->previous;
  1267. while (1)
  1268. {
  1269. //remove current node
  1270. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  1271. if (cmdbuf_obj->cmdbuf_need_remove == 1)
  1272. {
  1273. new_cmdbuf_node = remove_cmdbuf_node_from_list(list, new_cmdbuf_node);
  1274. if (new_cmdbuf_node)
  1275. {
  1276. //free node
  1277. global_cmdbuf_node[cmdbuf_obj->cmdbuf_id] = NULL;
  1278. #if PROCESS_MANAGER
  1279. if (cmdbuf_obj->process_manager_obj)
  1280. {
  1281. spin_lock_irqsave(&cmdbuf_obj->process_manager_obj->spinlock, flags);
  1282. cmdbuf_obj->process_manager_obj->total_exe_time -= cmdbuf_obj->executing_time;
  1283. spin_unlock_irqrestore(&cmdbuf_obj->process_manager_obj->spinlock, flags);
  1284. wake_up_interruptible_all(&cmdbuf_obj->process_manager_obj->wait_queue);
  1285. }
  1286. #endif
  1287. free_cmdbuf_node(new_cmdbuf_node);
  1288. }
  1289. }
  1290. if (last_cmdbuf_node == NULL)
  1291. break;
  1292. new_cmdbuf_node = last_cmdbuf_node;
  1293. last_cmdbuf_node = new_cmdbuf_node->previous;
  1294. }
  1295. //spin_unlock_irqrestore(dev->spinlock, flags);
  1296. up(&vcmd_reserve_cmdbuf_sem[module_type]);
  1297. return 0;
  1298. }
  1299. static long release_cmdbuf_node(bi_list *list, bi_list_node *cmdbuf_node)
  1300. {
  1301. bi_list_node *new_cmdbuf_node = NULL;
  1302. struct cmdbuf_obj *cmdbuf_obj = NULL;
  1303. /*get cmdbuf object according to cmdbuf_id*/
  1304. new_cmdbuf_node = cmdbuf_node;
  1305. if (new_cmdbuf_node == NULL)
  1306. return -1;
  1307. //remove node from list
  1308. new_cmdbuf_node = remove_cmdbuf_node_from_list(list, new_cmdbuf_node);
  1309. if (new_cmdbuf_node)
  1310. {
  1311. //free node
  1312. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  1313. global_cmdbuf_node[cmdbuf_obj->cmdbuf_id] = NULL;
  1314. free_cmdbuf_node(new_cmdbuf_node);
  1315. return 0;
  1316. }
  1317. return 1;
  1318. }
  1319. static long release_cmdbuf_node_cleanup(bi_list *list)
  1320. {
  1321. bi_list_node *new_cmdbuf_node = NULL;
  1322. struct cmdbuf_obj *cmdbuf_obj = NULL;
  1323. while (1)
  1324. {
  1325. new_cmdbuf_node = list->head;
  1326. if (new_cmdbuf_node == NULL)
  1327. return 0;
  1328. //remove node from list
  1329. bi_list_remove_node(list, new_cmdbuf_node);
  1330. //free node
  1331. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  1332. global_cmdbuf_node[cmdbuf_obj->cmdbuf_id] = NULL;
  1333. free_cmdbuf_node(new_cmdbuf_node);
  1334. }
  1335. return 0;
  1336. }
  1337. static bi_list_node *find_last_linked_cmdbuf(bi_list_node *current_node)
  1338. {
  1339. bi_list_node *new_cmdbuf_node = current_node;
  1340. bi_list_node *last_cmdbuf_node;
  1341. struct cmdbuf_obj *cmdbuf_obj = NULL;
  1342. if (current_node == NULL)
  1343. return NULL;
  1344. last_cmdbuf_node = new_cmdbuf_node;
  1345. new_cmdbuf_node = new_cmdbuf_node->previous;
  1346. while (1)
  1347. {
  1348. if (new_cmdbuf_node == NULL)
  1349. return last_cmdbuf_node;
  1350. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  1351. if (cmdbuf_obj->cmdbuf_data_linked)
  1352. {
  1353. return new_cmdbuf_node;
  1354. }
  1355. last_cmdbuf_node = new_cmdbuf_node;
  1356. new_cmdbuf_node = new_cmdbuf_node->previous;
  1357. }
  1358. return NULL;
  1359. }
  1360. static long link_and_run_cmdbuf(/*struct file */ int filp, struct exchange_parameter *input_para)
  1361. {
  1362. struct cmdbuf_obj *cmdbuf_obj = NULL;
  1363. bi_list_node *new_cmdbuf_node = NULL;
  1364. bi_list_node *last_cmdbuf_node = NULL;
  1365. u32 *jmp_addr = NULL;
  1366. u32 opCode = 0;
  1367. u32 tempOpcode = 0;
  1368. u32 record_last_cmdbuf_rdy_num = 0;
  1369. struct hantrovcmd_dev *dev = NULL;
  1370. unsigned long flags = 0;
  1371. int return_value = 0;
  1372. u16 cmdbuf_id = input_para->cmdbuf_id;
  1373. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  1374. if (new_cmdbuf_node == NULL)
  1375. {
  1376. //should not happen
  1377. printk(KERN_ERR "hantrovcmd: ERROR cmdbuf_id !!\n");
  1378. return -1;
  1379. }
  1380. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  1381. if (cmdbuf_obj->filp != filp)
  1382. {
  1383. //should not happen
  1384. printk(KERN_ERR "hantrovcmd: ERROR cmdbuf_id !!\n");
  1385. return -1;
  1386. }
  1387. cmdbuf_obj->cmdbuf_data_loaded = 1;
  1388. cmdbuf_obj->cmdbuf_size = input_para->cmdbuf_size;
  1389. cmdbuf_obj->waited = 0;
  1390. #ifdef VCMD_DEBUG_INTERNAL
  1391. {
  1392. u32 i, inst = 0, size = 0;
  1393. printk(KERN_INFO "vcmd link, current cmdbuf content\n");
  1394. for (i = 0; i < cmdbuf_obj->cmdbuf_size / 4; i++)
  1395. {
  1396. if (i == inst)
  1397. {
  1398. PrintInstr(i, *(cmdbuf_obj->cmdbuf_virtualAddress + i), &size);
  1399. inst += size;
  1400. }
  1401. else
  1402. {
  1403. printk(KERN_INFO "current cmdbuf data %d = 0x%x\n", i, *(cmdbuf_obj->cmdbuf_virtualAddress + i));
  1404. }
  1405. }
  1406. }
  1407. #endif
  1408. //test nop and end opcode, then assign value.
  1409. cmdbuf_obj->has_end_cmdbuf = 0; //0: has jmp opcode,1 has end code
  1410. cmdbuf_obj->no_normal_int_cmdbuf = 0; //0: interrupt when JMP,1 not interrupt when JMP
  1411. jmp_addr = cmdbuf_obj->cmdbuf_virtualAddress + (cmdbuf_obj->cmdbuf_size / 4);
  1412. opCode = tempOpcode = *(jmp_addr - 4);
  1413. opCode >>= 27;
  1414. opCode <<= 27;
  1415. //we can't identify END opcode or JMP opcode, so we don't support END opcode in control sw and driver.
  1416. if (opCode == OPCODE_JMP)
  1417. {
  1418. //jmp
  1419. opCode = tempOpcode;
  1420. opCode &= 0x02000000;
  1421. if (opCode == JMP_IE_1)
  1422. {
  1423. cmdbuf_obj->no_normal_int_cmdbuf = 0;
  1424. }
  1425. else
  1426. {
  1427. cmdbuf_obj->no_normal_int_cmdbuf = 1;
  1428. }
  1429. }
  1430. else
  1431. {
  1432. //not support other opcode
  1433. return -1;
  1434. }
  1435. if (down_interruptible(&vcmd_reserve_cmdbuf_sem[cmdbuf_obj->module_type]))
  1436. return -ERESTARTSYS;
  1437. return_value = select_vcmd(new_cmdbuf_node);
  1438. if (return_value)
  1439. return return_value;
  1440. dev = &hantrovcmd_data[cmdbuf_obj->core_id];
  1441. input_para->core_id = cmdbuf_obj->core_id;
  1442. printk(KERN_INFO "Allocate cmd buffer [%d] to core [%d], remain cmd buffer %d\n", cmdbuf_id, input_para->core_id, vcmd_cmdbuf_memory_wait.value);
  1443. //set ddr address for vcmd registers copy.
  1444. if (dev->hw_version_id > HW_ID_1_0_C)
  1445. {
  1446. //read vcmd executing register into ddr memory.
  1447. //now core id is got and output ddr address of vcmd register can be filled in.
  1448. //each core has its own fixed output ddr address of vcmd registers.
  1449. jmp_addr = cmdbuf_obj->cmdbuf_virtualAddress;
  1450. if (sizeof(ptr_t) == 8)
  1451. {
  1452. *(jmp_addr + 2) = (u32)((u64)(dev->vcmd_reg_mem_busAddress + (EXECUTING_CMDBUF_ID_ADDR + 1) * 4) >> 32);
  1453. }
  1454. else
  1455. {
  1456. *(jmp_addr + 2) = 0;
  1457. }
  1458. *(jmp_addr + 1) = (u32)((dev->vcmd_reg_mem_busAddress + (EXECUTING_CMDBUF_ID_ADDR + 1) * 4));
  1459. jmp_addr = cmdbuf_obj->cmdbuf_virtualAddress + (cmdbuf_obj->cmdbuf_size / 4);
  1460. //read vcmd all registers into ddr memory.
  1461. //now core id is got and output ddr address of vcmd registers can be filled in.
  1462. //each core has its own fixed output ddr address of vcmd registers.
  1463. if (sizeof(ptr_t) == 8)
  1464. {
  1465. *(jmp_addr - 6) = (u32)((u64)dev->vcmd_reg_mem_busAddress >> 32);
  1466. }
  1467. else
  1468. {
  1469. *(jmp_addr - 6) = 0;
  1470. }
  1471. *(jmp_addr - 7) = (u32)(dev->vcmd_reg_mem_busAddress);
  1472. }
  1473. //start to link and/or run
  1474. spin_lock_irqsave(dev->spinlock, flags);
  1475. last_cmdbuf_node = find_last_linked_cmdbuf(new_cmdbuf_node);
  1476. record_last_cmdbuf_rdy_num = dev->sw_cmdbuf_rdy_num;
  1477. vcmd_link_cmdbuf(dev, last_cmdbuf_node);
  1478. if (dev->working_state == WORKING_STATE_IDLE)
  1479. {
  1480. //run
  1481. vcmd_start(dev, last_cmdbuf_node);
  1482. }
  1483. else
  1484. {
  1485. //just update cmdbuf ready number
  1486. if (record_last_cmdbuf_rdy_num != dev->sw_cmdbuf_rdy_num) {
  1487. _Pragma("flush_memory");
  1488. xthal_dcache_all_writeback_inv();
  1489. _Pragma("flush_memory");
  1490. vcmd_write_register_value((const void *)dev->hwregs, dev->reg_mirror, HWIF_VCMD_RDY_CMDBUF_COUNT, dev->sw_cmdbuf_rdy_num);
  1491. }
  1492. }
  1493. spin_unlock_irqrestore(dev->spinlock, flags);
  1494. up(&vcmd_reserve_cmdbuf_sem[cmdbuf_obj->module_type]);
  1495. return 0;
  1496. }
  1497. /******************************************************************************/
  1498. static int check_cmdbuf_irq(struct hantrovcmd_dev *dev, struct cmdbuf_obj *cmdbuf_obj, u32 *irq_status_ret)
  1499. {
  1500. int rdy = 0;
  1501. unsigned long flags;
  1502. spin_lock_irqsave(dev->spinlock, flags);
  1503. if (cmdbuf_obj->cmdbuf_run_done)
  1504. {
  1505. rdy = 1;
  1506. *irq_status_ret = cmdbuf_obj->executing_status; //need to decide how to assign this variable
  1507. }
  1508. spin_unlock_irqrestore(dev->spinlock, flags);
  1509. return rdy;
  1510. }
  1511. /******************************************************************************/
  1512. static int check_mc_cmdbuf_irq(/*struct file * */ int filp, struct cmdbuf_obj *cmdbuf_obj, u32 *irq_status_ret)
  1513. {
  1514. int k;
  1515. bi_list_node *new_cmdbuf_node = NULL;
  1516. struct hantrovcmd_dev *dev = NULL;
  1517. for(k=0;k<TOTAL_DISCRETE_CMDBUF_NUM;k++)
  1518. {
  1519. new_cmdbuf_node = global_cmdbuf_node[k];
  1520. if(new_cmdbuf_node==NULL)
  1521. continue;
  1522. cmdbuf_obj=(struct cmdbuf_obj*)new_cmdbuf_node->data;
  1523. if(!cmdbuf_obj || cmdbuf_obj->filp != filp)
  1524. continue;
  1525. dev = &hantrovcmd_data[cmdbuf_obj->core_id];
  1526. if (check_cmdbuf_irq(dev, cmdbuf_obj, irq_status_ret) == 1) {
  1527. /* Return cmdbuf_id when ANY_CMDBUF_ID is used. */
  1528. if (!cmdbuf_obj->waited) {
  1529. *irq_status_ret = cmdbuf_obj->cmdbuf_id;
  1530. cmdbuf_obj->waited = 1;
  1531. return 1;
  1532. }
  1533. }
  1534. }
  1535. // check no job
  1536. //if (k == TOTAL_DISCRETE_CMDBUF_NUM)
  1537. // return 1;
  1538. return 0;
  1539. }
  1540. #ifdef IRQ_SIMULATION
  1541. void get_random_bytes(void *buf, int nbytes);
  1542. #if 0
  1543. void hantrovcmd_trigger_irq_0(struct timer_list* timer)
  1544. {
  1545. PDEBUG("trigger core 0 irq\n");
  1546. del_timer(timer);
  1547. hantrovcmd_isr(0,(void *)&hantrovcmd_data[0]);
  1548. }
  1549. void hantrovcmd_trigger_irq_1(struct timer_list* timer)
  1550. {
  1551. PDEBUG("trigger core 1 irq\n");
  1552. del_timer(timer);
  1553. hantrovcmd_isr(0,(void *)&hantrovcmd_data[1]);
  1554. }
  1555. #else
  1556. void hantrovcmd_trigger_irq(TimerHandle_t * /*struct timer_list * */ timer)
  1557. {
  1558. u32 timer_id = 0;
  1559. u32 core_id = 0;
  1560. u32 i;
  1561. for (i = 0; i < 10000; i++)
  1562. {
  1563. if (timer_reserve[i].timer == timer)
  1564. {
  1565. timer_id = timer_reserve[i].timer_id;
  1566. core_id = timer_reserve[i].core_id;
  1567. break;
  1568. }
  1569. }
  1570. PDEBUG("trigger core 0 irq\n");
  1571. hantrovcmd_isr(/*core_id,*/ (void *)&hantrovcmd_data[core_id]);
  1572. //del_timer(timer);
  1573. xTimerDelete(timer);
  1574. timer_reserve[timer_id].timer = NULL;
  1575. }
  1576. #endif
  1577. #endif
  1578. static unsigned int wait_cmdbuf_ready(/*struct file */ int filp, u16 cmdbuf_id, u32 *irq_status_ret)
  1579. {
  1580. struct cmdbuf_obj *cmdbuf_obj = NULL;
  1581. bi_list_node *new_cmdbuf_node = NULL;
  1582. struct hantrovcmd_dev *dev = NULL;
  1583. if(cmdbuf_id != ANY_CMDBUF_ID) {
  1584. PDEBUG("wait_cmdbuf_ready cmdbuf_id [%d]\n", cmdbuf_id);
  1585. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  1586. if (new_cmdbuf_node == NULL)
  1587. {
  1588. //should not happen
  1589. printk(KERN_ERR "hantrovcmd: ERROR cmdbuf_id !!\n");
  1590. return -1;
  1591. }
  1592. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  1593. if (cmdbuf_obj->filp != filp)
  1594. {
  1595. //should not happen
  1596. printk(KERN_ERR "hantrovcmd: ERROR cmdbuf_id !!\n");
  1597. return -1;
  1598. }
  1599. dev = &hantrovcmd_data[cmdbuf_obj->core_id];
  1600. #ifdef IRQ_SIMULATION
  1601. {
  1602. u32 random_num;
  1603. //get_random_bytes(&random_num, sizeof(u32));
  1604. random_num = (u32)((u64)100 * cmdbuf_obj->executing_time / (4096 * 2160) + 50);
  1605. PDEBUG("random_num=%d\n", random_num);
  1606. #if 0
  1607. /*init a timer to trigger irq*/
  1608. if (cmdbuf_obj->core_id==0)
  1609. {
  1610. //init_timer(&timer0);
  1611. //timer0.function = hantrovcmd_trigger_irq_0;
  1612. timer_setup(&timer0,hantrovcmd_trigger_irq_0,0);
  1613. timer0.expires = jiffies + random_num*HZ/10; //the expires time is 1s
  1614. add_timer(&timer0);
  1615. }
  1616. if (cmdbuf_obj->core_id==1)
  1617. {
  1618. //init_timer(&timer1);
  1619. //timer1.function = hantrovcmd_trigger_irq_1;
  1620. timer_setup(&timer1,hantrovcmd_trigger_irq_1,0);
  1621. timer1.expires = jiffies + random_num*HZ/10; //the expires time is 1s
  1622. add_timer(&timer1);
  1623. }
  1624. #else
  1625. {
  1626. u32 i;
  1627. /*struct timer_list */ TimerHandle_t *temp_timer = NULL;
  1628. for (i = 0; i < 10000; i++)
  1629. {
  1630. if (timer_reserve[i].timer == NULL)
  1631. {
  1632. timer_reserve[i].timer_id = i;
  1633. timer_reserve[i].core_id = cmdbuf_obj->core_id;
  1634. temp_timer = timer_reserve[i].timer = &timer[i];
  1635. break;
  1636. }
  1637. }
  1638. //if (cmdbuf_obj->core_id==0)
  1639. {
  1640. #if 1
  1641. temp_timer = xTimerCreate("Timer", pdMS_TO_TICKS(1000), pdTRUE, (void *)0, hantrovcmd_trigger_irq);
  1642. if (temp_timer == NULL)
  1643. {
  1644. /* The timer was not created. */
  1645. }
  1646. else if (xTimerStart(temp_timer, 0) != pdPASS)
  1647. {
  1648. /* The timer could not be set into the Active state. */
  1649. }
  1650. #else
  1651. //init_timer(&timer0);
  1652. //timer0.function = hantrovcmd_trigger_irq_0;
  1653. timer_setup(temp_timer, hantrovcmd_trigger_irq, 0);
  1654. temp_timer->expires = jiffies + random_num * HZ / 10; //the expires time is 1s
  1655. add_timer(temp_timer);
  1656. #endif
  1657. }
  1658. }
  1659. #endif
  1660. }
  1661. #endif
  1662. #if 1
  1663. #if 1
  1664. //use yield
  1665. while(1)
  1666. {
  1667. if (cmdbuf_obj->cmdbuf_run_done)
  1668. break;
  1669. sched_yield();
  1670. }
  1671. #else
  1672. //wait a wait_queue
  1673. if (queue_vcmd_wait(&wait_queue_vcmd[cmdbuf_obj->cmdbuf_id]))
  1674. {
  1675. PDEBUG("wait vcmd_wait_queue failed\n");
  1676. //abort the vcmd
  1677. vcmd_write_register_value((const void *)dev->hwregs, dev->reg_mirror, HWIF_VCMD_START_TRIGGER, 0);
  1678. return -ERESTARTSYS;
  1679. }
  1680. #endif
  1681. #else
  1682. if (wait_event_interruptible(*dev->wait_queue, check_cmdbuf_irq(dev, cmdbuf_obj, irq_status_ret)))
  1683. {
  1684. PDEBUG("vcmd_wait_queue_0 interrupted\n");
  1685. //abort the vcmd
  1686. vcmd_write_register_value((const void *)dev->hwregs, dev->reg_mirror, HWIF_VCMD_START_TRIGGER, 0);
  1687. return -ERESTARTSYS;
  1688. }
  1689. #endif
  1690. } else {
  1691. /*if (check_mc_cmdbuf_irq(filp, cmdbuf_obj, irq_status_ret))
  1692. return 0;
  1693. if (wait_event_interruptible(mc_wait_queue, check_mc_cmdbuf_irq(filp, cmdbuf_obj, irq_status_ret)))
  1694. {
  1695. PDEBUG("multicore wait_queue interrupted\n");
  1696. return -ERESTARTSYS;
  1697. }*/
  1698. while(1) {
  1699. if (check_mc_cmdbuf_irq(filp, cmdbuf_obj, irq_status_ret)) {
  1700. return 0;
  1701. }
  1702. queue_vcmd_wait(&mc_wait_queue);
  1703. }
  1704. }
  1705. return 0;
  1706. }
  1707. long hantrovcmd_ioctl(int filp, unsigned int cmd, void *arg)
  1708. {
  1709. int err = 0;
  1710. PDEBUG("ioctl cmd 0x%08x, filp 0x%x\n", cmd, filp);
  1711. /*
  1712. * extract the type and number bitfields, and don't encode
  1713. * wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok()
  1714. */
  1715. if (_IOC_TYPE(cmd) != HANTRO_VCMD_IOC_MAGIC)
  1716. return -ENOTTY;
  1717. if ((_IOC_TYPE(cmd) == HANTRO_VCMD_IOC_MAGIC &&
  1718. _IOC_NR(cmd) > HANTRO_VCMD_IOC_MAXNR))
  1719. return -ENOTTY;
  1720. /*
  1721. * the direction is a bitmask, and VERIFY_WRITE catches R/W
  1722. * transfers. `Type' is user-oriented, while
  1723. * access_ok is kernel-oriented, so the concept of "read" and
  1724. * "write" is reversed
  1725. */
  1726. if (_IOC_DIR(cmd) & _IOC_READ)
  1727. err = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd));
  1728. else if (_IOC_DIR(cmd) & _IOC_WRITE)
  1729. err = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd));
  1730. if (err)
  1731. return -EFAULT;
  1732. switch (cmd)
  1733. {
  1734. case HANTRO_VCMD_IOCH_GET_CMDBUF_PARAMETER:
  1735. {
  1736. struct cmdbuf_mem_parameter local_cmdbuf_mem_data = {NULL, 0};
  1737. PDEBUG("VCMD-Get VCMD CMDBUF Parameter. \n");
  1738. local_cmdbuf_mem_data.cmdbuf_unit_size = CMDBUF_MAX_SIZE;
  1739. local_cmdbuf_mem_data.status_cmdbuf_unit_size = CMDBUF_MAX_SIZE;
  1740. local_cmdbuf_mem_data.cmdbuf_total_size = CMDBUF_POOL_TOTAL_SIZE;
  1741. local_cmdbuf_mem_data.status_cmdbuf_total_size = CMDBUF_POOL_TOTAL_SIZE;
  1742. local_cmdbuf_mem_data.phy_status_cmdbuf_addr = vcmd_status_buf_mem_pool.busAddress;
  1743. local_cmdbuf_mem_data.phy_cmdbuf_addr = vcmd_buf_mem_pool.busAddress;
  1744. local_cmdbuf_mem_data.base_ddr_addr = base_ddr_addr;
  1745. copy_to_user((struct cmdbuf_mem_parameter *)arg, &local_cmdbuf_mem_data, sizeof(struct cmdbuf_mem_parameter));
  1746. break;
  1747. }
  1748. case HANTRO_VCMD_IOCH_GET_VCMD_PARAMETER:
  1749. {
  1750. struct config_parameter input_para = {0};
  1751. PDEBUG("VCMD-Get VCMD Config Parameter. \n");
  1752. copy_from_user(&input_para, (struct config_parameter *)arg, sizeof(struct config_parameter));
  1753. if (vcmd_type_core_num[input_para.module_type])
  1754. {
  1755. input_para.submodule_main_addr = vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_main_addr;
  1756. input_para.submodule_dec400_addr = vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_dec400_addr;
  1757. input_para.submodule_L2Cache_addr = vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_L2Cache_addr;
  1758. input_para.submodule_MMU_addr = vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_MMU_addr;
  1759. input_para.config_status_cmdbuf_id = vcmd_manager[input_para.module_type][0]->status_cmdbuf_id;
  1760. input_para.vcmd_hw_version_id = vcmd_manager[input_para.module_type][0]->hw_version_id;
  1761. input_para.vcmd_core_num = vcmd_type_core_num[input_para.module_type];
  1762. }
  1763. else
  1764. {
  1765. input_para.submodule_main_addr = 0xffff;
  1766. input_para.submodule_dec400_addr = 0xffff;
  1767. input_para.submodule_L2Cache_addr = 0xffff;
  1768. input_para.submodule_MMU_addr = 0xffff;
  1769. input_para.config_status_cmdbuf_id = 0;
  1770. input_para.vcmd_core_num = 0;
  1771. input_para.vcmd_hw_version_id = HW_ID_1_0_C;
  1772. }
  1773. copy_to_user((struct config_parameter *)arg, &input_para, sizeof(struct config_parameter));
  1774. break;
  1775. }
  1776. case HANTRO_VCMD_IOCH_RESERVE_CMDBUF:
  1777. {
  1778. int ret = 0;
  1779. struct exchange_parameter input_para = {0};
  1780. PDEBUG("VCMD-Reserve CMDBUF. \n");
  1781. copy_from_user(&input_para, (struct exchange_parameter *)arg, sizeof(struct exchange_parameter));
  1782. ret = reserve_cmdbuf(filp, &input_para);
  1783. if (ret == 0)
  1784. copy_to_user((struct exchange_parameter *)arg, &input_para, sizeof(struct exchange_parameter));
  1785. return ret;
  1786. }
  1787. case HANTRO_VCMD_IOCH_LINK_RUN_CMDBUF:
  1788. {
  1789. struct exchange_parameter input_para = {0};
  1790. long retVal = 0;
  1791. copy_from_user(&input_para, (struct exchange_parameter *)arg, sizeof(struct exchange_parameter));
  1792. PDEBUG("VCMD-Link and Run CMDBUF. \n");
  1793. retVal = link_and_run_cmdbuf(filp, &input_para);
  1794. copy_to_user((struct exchange_parameter *)arg, &input_para, sizeof(struct exchange_parameter));
  1795. return retVal;
  1796. break;
  1797. }
  1798. case HANTRO_VCMD_IOCH_WAIT_CMDBUF:
  1799. {
  1800. u16 cmdbuf_id = 0;
  1801. unsigned int tmp = 0;
  1802. u32 irq_status_ret = 0;
  1803. __get_user(cmdbuf_id, (u16 *)arg);
  1804. /*high 16 bits are core id, low 16 bits are cmdbuf_id*/
  1805. PDEBUG("VCMD-Wait for CMDBUF Finishing. \n");
  1806. tmp = wait_cmdbuf_ready(filp, cmdbuf_id, &irq_status_ret);
  1807. cmdbuf_id = (u16)irq_status_ret;
  1808. if (tmp == 0)
  1809. {
  1810. __put_user(cmdbuf_id, (u16 *)arg);
  1811. return tmp; //return core_id
  1812. }
  1813. else
  1814. {
  1815. __put_user(0, (u16 *)arg);
  1816. return -1;
  1817. }
  1818. break;
  1819. }
  1820. case HANTRO_VCMD_IOCH_RELEASE_CMDBUF:
  1821. {
  1822. u16 cmdbuf_id = 0;
  1823. __get_user(cmdbuf_id, (u16 *)arg);
  1824. /*16 bits are cmdbuf_id*/
  1825. PDEBUG("VCMD-Release CMDBUF. \n");
  1826. release_cmdbuf(filp, cmdbuf_id);
  1827. return 0;
  1828. break;
  1829. }
  1830. case HANTRO_VCMD_IOCH_POLLING_CMDBUF:
  1831. {
  1832. u16 core_id = 0;
  1833. __get_user(core_id, (u16 *)arg);
  1834. /*16 bits are cmdbuf_id*/
  1835. if (core_id >= total_vcmd_core_num)
  1836. return -1;
  1837. hantrovcmd_isr(/*core_id,*/ &hantrovcmd_data[core_id]);
  1838. return 0;
  1839. break;
  1840. }
  1841. default:
  1842. {
  1843. break;
  1844. }
  1845. }
  1846. return 0;
  1847. }
  1848. /**********************************************************************************************************\
  1849. *process manager object management
  1850. \***********************************************************************************************************/
  1851. #if PROCESS_MANAGER
  1852. static struct process_manager_obj *create_process_manager_obj(void)
  1853. {
  1854. struct process_manager_obj *process_manager_obj = NULL;
  1855. process_manager_obj = vmalloc(sizeof(struct process_manager_obj));
  1856. if (process_manager_obj == NULL)
  1857. {
  1858. PDEBUG("%s\n", "vmalloc for process_manager_obj fail!");
  1859. return process_manager_obj;
  1860. }
  1861. memset(process_manager_obj, 0, sizeof(struct process_manager_obj));
  1862. return process_manager_obj;
  1863. }
  1864. static void free_process_manager_obj(struct process_manager_obj *process_manager_obj)
  1865. {
  1866. if (process_manager_obj == NULL)
  1867. {
  1868. PDEBUG("%s\n", "free_process_manager_obj NULL");
  1869. return;
  1870. }
  1871. //free current cmdbuf_obj
  1872. vfree(process_manager_obj);
  1873. return;
  1874. }
  1875. static bi_list_node *create_process_manager_node(void)
  1876. {
  1877. bi_list_node *current_node = NULL;
  1878. struct process_manager_obj *process_manager_obj = NULL;
  1879. process_manager_obj = create_process_manager_obj();
  1880. if (process_manager_obj == NULL)
  1881. {
  1882. PDEBUG("%s\n", "create_process_manager_obj fail!");
  1883. return NULL;
  1884. }
  1885. process_manager_obj->total_exe_time = 0;
  1886. spin_lock_init(&process_manager_obj->spinlock);
  1887. //init_waitqueue_head(&process_manager_obj->wait_queue);
  1888. sem_init(&process_manager_obj->wait_queue, 0, ???);
  1889. current_node = bi_list_create_node();
  1890. if (current_node == NULL)
  1891. {
  1892. PDEBUG("%s\n", "bi_list_create_node fail!");
  1893. free_process_manager_obj(process_manager_obj);
  1894. return NULL;
  1895. }
  1896. current_node->data = (void *)process_manager_obj;
  1897. return current_node;
  1898. }
  1899. static void free_process_manager_node(bi_list_node *process_node)
  1900. {
  1901. struct process_manager_obj *process_manager_obj = NULL;
  1902. if (process_node == NULL)
  1903. {
  1904. PDEBUG("%s\n", "free_process_manager_node NULL");
  1905. return;
  1906. }
  1907. process_manager_obj = (struct process_manager_obj *)process_node->data;
  1908. //free struct process_manager_obj
  1909. free_process_manager_obj(process_manager_obj);
  1910. //free current process_manager_obj entity.
  1911. bi_list_free_node(process_node);
  1912. return;
  1913. }
  1914. static long release_process_node_cleanup(bi_list *list)
  1915. {
  1916. bi_list_node *new_process_node = NULL;
  1917. while (1)
  1918. {
  1919. new_process_node = list->head;
  1920. if (new_process_node == NULL)
  1921. break;
  1922. //remove node from list
  1923. bi_list_remove_node(list, new_process_node);
  1924. //remove node from list
  1925. free_process_manager_node(new_process_node);
  1926. }
  1927. return 0;
  1928. }
  1929. static void create_kernel_process_manager(void)
  1930. {
  1931. bi_list_node *process_manager_node;
  1932. struct process_manager_obj *process_manager_obj = NULL;
  1933. process_manager_node = create_process_manager_node();
  1934. process_manager_obj = (struct process_manager_obj *)process_manager_node->data;
  1935. //process_manager_obj->filp = NULL;
  1936. process_manager_obj->filp = 0;
  1937. bi_list_insert_node_tail(&global_process_manager, process_manager_node);
  1938. }
  1939. #endif
  1940. int hantrovcmd_open(int *inode, int filp)
  1941. {
  1942. int result = 0;
  1943. struct hantrovcmd_dev *dev = hantrovcmd_data;
  1944. #if PROCESS_MANAGER
  1945. bi_list_node *process_manager_node;
  1946. unsigned long flags;
  1947. struct process_manager_obj *process_manager_obj = NULL;
  1948. //filp->private_data = (void *) dev;
  1949. process_manager_node = create_process_manager_node();
  1950. if (process_manager_node == NULL)
  1951. return -1;
  1952. process_manager_obj = (struct process_manager_obj *)process_manager_node->data;
  1953. process_manager_obj->filp = filp;
  1954. spin_lock_irqsave(&vcmd_process_manager_lock, flags);
  1955. bi_list_insert_node_tail(&global_process_manager, process_manager_node);
  1956. spin_unlock_irqrestore(&vcmd_process_manager_lock, flags);
  1957. #endif
  1958. PDEBUG("dev opened, filp 0x%x\n", filp);
  1959. return result;
  1960. }
  1961. int hantrovcmd_release(/*struct inode*/ int *inode, /*struct file */ int filp)
  1962. {
  1963. struct hantrovcmd_dev *dev; // = hantrovcmd_data; //(struct hantrovcmd_dev *) filp->private_data;
  1964. u32 core_id = 0;
  1965. u32 release_cmdbuf_num = 0;
  1966. bi_list_node *new_cmdbuf_node = NULL;
  1967. struct cmdbuf_obj *cmdbuf_obj_temp = NULL;
  1968. #if PROCESS_MANAGER
  1969. bi_list_node *process_manager_node;
  1970. struct process_manager_obj *process_manager_obj = NULL;
  1971. #endif
  1972. unsigned long flags;
  1973. long retVal = 0;
  1974. PDEBUG("dev closed, filp 0x%x\n", filp);
  1975. // printf(".");
  1976. for (core_id = 0; core_id < total_vcmd_core_num; core_id++)
  1977. {
  1978. dev = &hantrovcmd_data[core_id];
  1979. if (dev->hwregs == NULL)
  1980. continue;
  1981. if (down_interruptible(&vcmd_reserve_cmdbuf_sem[dev->vcmd_core_cfg.sub_module_type]))
  1982. return -ERESTARTSYS;
  1983. spin_lock_irqsave(dev->spinlock, flags);
  1984. new_cmdbuf_node = dev->list_manager.head;
  1985. while (1)
  1986. {
  1987. if (new_cmdbuf_node == NULL)
  1988. break;
  1989. cmdbuf_obj_temp = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  1990. if (cmdbuf_obj_temp->filp == filp)
  1991. {
  1992. if (cmdbuf_obj_temp->cmdbuf_run_done)
  1993. {
  1994. cmdbuf_obj_temp->cmdbuf_need_remove = 1;
  1995. retVal = release_cmdbuf_node(&dev->list_manager, new_cmdbuf_node);
  1996. #if PROCESS_MANAGER
  1997. if (retVal == 1)
  1998. cmdbuf_obj_temp->process_manager_obj = NULL;
  1999. #endif
  2000. }
  2001. else if (cmdbuf_obj_temp->cmdbuf_data_linked == 0)
  2002. {
  2003. cmdbuf_obj_temp->cmdbuf_data_linked = 1;
  2004. cmdbuf_obj_temp->cmdbuf_run_done = 1;
  2005. cmdbuf_obj_temp->cmdbuf_need_remove = 1;
  2006. retVal = release_cmdbuf_node(&dev->list_manager, new_cmdbuf_node);
  2007. #if PROCESS_MANAGER
  2008. if (retVal == 1)
  2009. cmdbuf_obj_temp->process_manager_obj = NULL;
  2010. #endif
  2011. }
  2012. else if (cmdbuf_obj_temp->cmdbuf_data_linked == 1 && dev->working_state == WORKING_STATE_IDLE)
  2013. {
  2014. cmdbuf_obj_temp->cmdbuf_run_done = 1;
  2015. cmdbuf_obj_temp->cmdbuf_need_remove = 1;
  2016. retVal = release_cmdbuf_node(&dev->list_manager, new_cmdbuf_node);
  2017. #if PROCESS_MANAGER
  2018. if (retVal == 1)
  2019. cmdbuf_obj_temp->process_manager_obj = NULL;
  2020. #endif
  2021. }
  2022. else if (cmdbuf_obj_temp->cmdbuf_data_linked == 1 && dev->working_state == WORKING_STATE_WORKING)
  2023. {
  2024. bi_list_node *last_cmdbuf_node;
  2025. u32 record_last_cmdbuf_rdy_num;
  2026. //abort the vcmd and wait
  2027. vcmd_write_register_value((const void *)dev->hwregs, dev->reg_mirror, HWIF_VCMD_START_TRIGGER, 0);
  2028. #if 1
  2029. #if 1
  2030. while(1)
  2031. {
  2032. if (cmdbuf_obj_temp->cmdbuf_run_done)
  2033. break;
  2034. sched_yield();
  2035. }
  2036. #else
  2037. queue_vcmd_wait(&abort_queue_vcmd[cmdbuf_obj_temp->cmdbuf_id]);
  2038. #endif
  2039. #else
  2040. if (wait_event_interruptible(*dev->wait_abort_queue, wait_abort_rdy(&dev[core_id])))
  2041. return -ERESTARTSYS;
  2042. #endif
  2043. cmdbuf_obj_temp->cmdbuf_run_done = 1;
  2044. cmdbuf_obj_temp->cmdbuf_need_remove = 1;
  2045. //printf("hantrovcmd_release before: vcmd_cmdbuf_memory_wait sem value %d\n", vcmd_cmdbuf_memory_wait.value);
  2046. retVal = release_cmdbuf_node(&dev->list_manager, new_cmdbuf_node);
  2047. #if PROCESS_MANAGER
  2048. if (retVal == 1)
  2049. cmdbuf_obj_temp->process_manager_obj = NULL;
  2050. #endif
  2051. //link
  2052. last_cmdbuf_node = find_last_linked_cmdbuf(dev->list_manager.tail);
  2053. record_last_cmdbuf_rdy_num = dev->sw_cmdbuf_rdy_num;
  2054. vcmd_link_cmdbuf(dev, last_cmdbuf_node);
  2055. //re-run
  2056. if (dev->sw_cmdbuf_rdy_num)
  2057. vcmd_start(dev, last_cmdbuf_node);
  2058. }
  2059. release_cmdbuf_num++;
  2060. }
  2061. new_cmdbuf_node = new_cmdbuf_node->next;
  2062. }
  2063. spin_unlock_irqrestore(dev->spinlock, flags);
  2064. up(&vcmd_reserve_cmdbuf_sem[dev->vcmd_core_cfg.sub_module_type]);
  2065. }
  2066. #if 0
  2067. if(release_cmdbuf_num)
  2068. wake_up_interruptible_all(&vcmd_cmdbuf_memory_wait);
  2069. #endif
  2070. #if PROCESS_MANAGER
  2071. spin_lock_irqsave(&vcmd_process_manager_lock, flags);
  2072. process_manager_node = global_process_manager.head;
  2073. while (1)
  2074. {
  2075. if (process_manager_node == NULL)
  2076. break;
  2077. process_manager_obj = (struct process_manager_obj *)process_manager_node->data;
  2078. if (process_manager_obj->filp == filp)
  2079. break;
  2080. process_manager_node = process_manager_node->next;
  2081. }
  2082. //remove node from list
  2083. PDEBUG("process node %p for filp to be removed: %p\n", (void *)process_manager_node, (void *)process_manager_obj->filp);
  2084. bi_list_remove_node(&global_process_manager, process_manager_node);
  2085. spin_unlock_irqrestore(&vcmd_process_manager_lock, flags);
  2086. free_process_manager_node(process_manager_node);
  2087. #endif
  2088. return 0;
  2089. }
  2090. static void vcmd_link_cmdbuf(struct hantrovcmd_dev *dev, bi_list_node *last_linked_cmdbuf_node)
  2091. {
  2092. bi_list_node *new_cmdbuf_node = NULL;
  2093. bi_list_node *next_cmdbuf_node = NULL;
  2094. struct cmdbuf_obj *cmdbuf_obj = NULL;
  2095. struct cmdbuf_obj *next_cmdbuf_obj = NULL;
  2096. u32 *jmp_addr = NULL;
  2097. u32 operation_code = 0;
  2098. new_cmdbuf_node = last_linked_cmdbuf_node;
  2099. //for the first cmdbuf.
  2100. if (new_cmdbuf_node != NULL)
  2101. {
  2102. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  2103. if (cmdbuf_obj->cmdbuf_data_linked == 0)
  2104. {
  2105. dev->sw_cmdbuf_rdy_num++;
  2106. cmdbuf_obj->cmdbuf_data_linked = 1;
  2107. dev->duration_without_int = 0;
  2108. if (cmdbuf_obj->has_end_cmdbuf == 0)
  2109. {
  2110. if (cmdbuf_obj->no_normal_int_cmdbuf == 1)
  2111. {
  2112. dev->duration_without_int = cmdbuf_obj->executing_time;
  2113. //maybe nop is modified, so write back.
  2114. if (dev->duration_without_int >= INT_MIN_SUM_OF_IMAGE_SIZE)
  2115. {
  2116. jmp_addr = cmdbuf_obj->cmdbuf_virtualAddress + (cmdbuf_obj->cmdbuf_size / 4);
  2117. operation_code = *(jmp_addr - 4);
  2118. operation_code = JMP_IE_1 | operation_code;
  2119. *(jmp_addr - 4) = operation_code;
  2120. dev->duration_without_int = 0;
  2121. }
  2122. }
  2123. }
  2124. }
  2125. }
  2126. while (1)
  2127. {
  2128. if (new_cmdbuf_node == NULL)
  2129. break;
  2130. if (new_cmdbuf_node->next == NULL)
  2131. break;
  2132. next_cmdbuf_node = new_cmdbuf_node->next;
  2133. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  2134. next_cmdbuf_obj = (struct cmdbuf_obj *)next_cmdbuf_node->data;
  2135. if (cmdbuf_obj->has_end_cmdbuf == 0)
  2136. {
  2137. //need to link, current cmdbuf link to next cmdbuf
  2138. jmp_addr = cmdbuf_obj->cmdbuf_virtualAddress + (cmdbuf_obj->cmdbuf_size / 4);
  2139. if (dev->hw_version_id > HW_ID_1_0_C)
  2140. {
  2141. //set next cmdbuf id
  2142. *(jmp_addr - 1) = next_cmdbuf_obj->cmdbuf_id;
  2143. }
  2144. if (sizeof(ptr_t) == 8)
  2145. {
  2146. *(jmp_addr - 2) = (u32)((u64)(next_cmdbuf_obj->cmdbuf_busAddress - base_ddr_addr) >> 32);
  2147. }
  2148. else
  2149. {
  2150. *(jmp_addr - 2) = 0;
  2151. }
  2152. *(jmp_addr - 3) = (u32)(next_cmdbuf_obj->cmdbuf_busAddress - base_ddr_addr);
  2153. operation_code = *(jmp_addr - 4);
  2154. operation_code >>= 16;
  2155. operation_code <<= 16;
  2156. *(jmp_addr - 4) = (u32)(operation_code | JMP_RDY_1 | ((next_cmdbuf_obj->cmdbuf_size + 7) / 8));
  2157. next_cmdbuf_obj->cmdbuf_data_linked = 1;
  2158. dev->sw_cmdbuf_rdy_num++;
  2159. //modify nop code of next cmdbuf
  2160. if (next_cmdbuf_obj->has_end_cmdbuf == 0)
  2161. {
  2162. if (next_cmdbuf_obj->no_normal_int_cmdbuf == 1)
  2163. {
  2164. dev->duration_without_int += next_cmdbuf_obj->executing_time;
  2165. //maybe we see the modified nop before abort, so need to write back.
  2166. if (dev->duration_without_int >= INT_MIN_SUM_OF_IMAGE_SIZE)
  2167. {
  2168. jmp_addr = next_cmdbuf_obj->cmdbuf_virtualAddress + (next_cmdbuf_obj->cmdbuf_size / 4);
  2169. operation_code = *(jmp_addr - 4);
  2170. operation_code = JMP_IE_1 | operation_code;
  2171. *(jmp_addr - 4) = operation_code;
  2172. dev->duration_without_int = 0;
  2173. }
  2174. }
  2175. }
  2176. else
  2177. {
  2178. dev->duration_without_int = 0;
  2179. }
  2180. #ifdef VCMD_DEBUG_INTERNAL
  2181. {
  2182. u32 i;
  2183. printk(KERN_INFO "vcmd link, last cmdbuf content\n");
  2184. for (i = cmdbuf_obj->cmdbuf_size / 4 - 8; i < cmdbuf_obj->cmdbuf_size / 4; i++)
  2185. {
  2186. printk(KERN_INFO "current linked cmdbuf data %d =0x%x\n", i, *(cmdbuf_obj->cmdbuf_virtualAddress + i));
  2187. }
  2188. }
  2189. #endif
  2190. }
  2191. else
  2192. break;
  2193. new_cmdbuf_node = new_cmdbuf_node->next;
  2194. }
  2195. return;
  2196. }
  2197. /*------------------------------------------------------------------------------
  2198. Function name : vcmd_pcie_init
  2199. Description : Initialize PCI Hw access
  2200. Return type : int
  2201. ------------------------------------------------------------------------------*/
  2202. static int vcmd_pcie_init(void)
  2203. {
  2204. int i = 0;
  2205. g_vcmd_dev = pci_get_device(PCI_VENDOR_ID_HANTRO, PCI_DEVICE_ID_HANTRO_PCI, g_vcmd_dev);
  2206. //if (NULL == g_vcmd_dev) {
  2207. // printk(KERN_ERR "Init: Hardware not found.\n");
  2208. // goto out;
  2209. //}
  2210. if (0 > pci_enable_device(g_vcmd_dev))
  2211. {
  2212. printk(KERN_ERR "Init: Device not enabled.\n");
  2213. goto out;
  2214. }
  2215. g_vcmd_base_hdwr = pci_resource_start(g_vcmd_dev, PCI_H2_BAR);
  2216. //if (0 > g_vcmd_base_hdwr) {
  2217. // printk(KERN_INFO "Init: Base Address not set.\n");
  2218. // goto out_pci_disable_device;
  2219. //}
  2220. printk(KERN_INFO "Base hw val 0x%llx\n", (long long unsigned int)g_vcmd_base_hdwr);
  2221. g_vcmd_base_len = pci_resource_len(g_vcmd_dev, PCI_H2_BAR);
  2222. printk(KERN_INFO "Base hw len 0x%d\n", (unsigned int)g_vcmd_base_len);
  2223. for (i = 0; i < total_vcmd_core_num; i++)
  2224. {
  2225. vcmd_core_array[i].vcmd_base_addr = g_vcmd_base_hdwr + vcmd_core_array[i].vcmd_base_addr; //the offset is based on which bus interface is chosen
  2226. }
  2227. vcmd_sram_base = g_vcmd_base_hdwr + 0x000000; //axi0 interface
  2228. vcmd_sram_size = 0x80000;
  2229. g_vcmd_base_ddr_hw = pci_resource_start(g_vcmd_dev, PCI_DDR_BAR);
  2230. //if (0 > g_vcmd_base_ddr_hw) {
  2231. // printk(KERN_INFO "PcieInit: Base Address not set.\n");
  2232. // goto out_pci_disable_device;
  2233. //}
  2234. printk(KERN_INFO "Base memory val 0x%08x\n", (unsigned int)g_vcmd_base_ddr_hw);
  2235. base_ddr_addr = g_vcmd_base_ddr_hw;
  2236. g_vcmd_base_len = pci_resource_len(g_vcmd_dev, PCI_DDR_BAR);
  2237. printk(KERN_INFO "Base memory len 0x%d\n", (unsigned int)g_vcmd_base_len);
  2238. //Get bus addr for VCMD devide
  2239. vcmd_buf_mem_pool.busAddress = GetBusAddrForIODevide(CMDBUF_POOL_TOTAL_SIZE * 2 + 0x100000); //5M //g_vcmd_base_ddr_hw+0x800000;
  2240. vcmd_buf_mem_pool.size = CMDBUF_POOL_TOTAL_SIZE;
  2241. if (!request_mem_region(vcmd_buf_mem_pool.busAddress, vcmd_buf_mem_pool.size,
  2242. "vc8000_vcmd_driver"))
  2243. {
  2244. printk(KERN_INFO "Init: failed to request hw region.\n");
  2245. return -1;
  2246. }
  2247. printk(KERN_INFO "Init: vcmd_buf_mem_pool.busAddress=0x%llx.\n", (long long unsigned int)vcmd_buf_mem_pool.busAddress);
  2248. vcmd_buf_mem_pool.virtualAddress = (u32 *)DirectMemoryMap(vcmd_buf_mem_pool.busAddress, vcmd_buf_mem_pool.size);
  2249. if (vcmd_buf_mem_pool.virtualAddress == NULL)
  2250. {
  2251. printk(KERN_INFO "Init: failed to ioremap.\n");
  2252. return -1;
  2253. }
  2254. printk(KERN_INFO "Init: vcmd_buf_mem_pool.virtualAddress=0x%llx.\n", (long long unsigned int)vcmd_buf_mem_pool.virtualAddress);
  2255. vcmd_status_buf_mem_pool.busAddress = vcmd_buf_mem_pool.busAddress + CMDBUF_POOL_TOTAL_SIZE;
  2256. vcmd_status_buf_mem_pool.size = CMDBUF_POOL_TOTAL_SIZE;
  2257. if (!request_mem_region(vcmd_status_buf_mem_pool.busAddress, vcmd_status_buf_mem_pool.size,
  2258. "vc8000_vcmd_driver"))
  2259. {
  2260. printk(KERN_INFO "Init: failed to request hw region.\n");
  2261. return -1;
  2262. }
  2263. printk(KERN_INFO "Init: vcmd_status_buf_mem_pool.busAddress=0x%llx.\n", (long long unsigned int)vcmd_status_buf_mem_pool.busAddress);
  2264. vcmd_status_buf_mem_pool.virtualAddress = (u32 *)DirectMemoryMap(vcmd_status_buf_mem_pool.busAddress,
  2265. vcmd_status_buf_mem_pool.size);
  2266. if (vcmd_status_buf_mem_pool.virtualAddress == NULL)
  2267. {
  2268. printk(KERN_INFO "Init: failed to ioremap.\n");
  2269. return -1;
  2270. }
  2271. printk(KERN_INFO "Init: vcmd_status_buf_mem_pool.virtualAddress=0x%llx.\n", (long long unsigned int)vcmd_status_buf_mem_pool.virtualAddress);
  2272. vcmd_registers_mem_pool.busAddress = vcmd_status_buf_mem_pool.busAddress + CMDBUF_POOL_TOTAL_SIZE;
  2273. vcmd_registers_mem_pool.size = CMDBUF_VCMD_REGISTER_TOTAL_SIZE;
  2274. if (!request_mem_region(vcmd_registers_mem_pool.busAddress, vcmd_registers_mem_pool.size,
  2275. "vc8000_vcmd_driver"))
  2276. {
  2277. printk(KERN_INFO "Init: failed to request hw region.\n");
  2278. return -1;
  2279. }
  2280. printk(KERN_INFO "Init: vcmd_registers_mem_pool.busAddress=0x%llx.\n", (long long unsigned int)vcmd_registers_mem_pool.busAddress);
  2281. vcmd_registers_mem_pool.virtualAddress = (u32 *)DirectMemoryMap(vcmd_registers_mem_pool.busAddress,
  2282. vcmd_registers_mem_pool.size);
  2283. if (vcmd_registers_mem_pool.virtualAddress == NULL)
  2284. {
  2285. printk(KERN_INFO "Init: failed to ioremap.\n");
  2286. return -1;
  2287. }
  2288. printk(KERN_INFO "Init: vcmd_registers_mem_pool.virtualAddress=0x%llx.\n", (long long unsigned int)vcmd_registers_mem_pool.virtualAddress);
  2289. return 0;
  2290. out_pci_disable_device:
  2291. pci_disable_device(g_vcmd_dev);
  2292. out:
  2293. return -1;
  2294. }
  2295. static void vcmd_delink_cmdbuf(struct hantrovcmd_dev *dev, bi_list_node *last_linked_cmdbuf_node)
  2296. {
  2297. bi_list_node *new_cmdbuf_node = NULL;
  2298. struct cmdbuf_obj *cmdbuf_obj = NULL;
  2299. new_cmdbuf_node = last_linked_cmdbuf_node;
  2300. while (1)
  2301. {
  2302. if (new_cmdbuf_node == NULL)
  2303. break;
  2304. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  2305. if (cmdbuf_obj->cmdbuf_data_linked)
  2306. {
  2307. cmdbuf_obj->cmdbuf_data_linked = 0;
  2308. }
  2309. else
  2310. break;
  2311. new_cmdbuf_node = new_cmdbuf_node->next;
  2312. }
  2313. dev->sw_cmdbuf_rdy_num = 0;
  2314. }
  2315. static void vcmd_start(struct hantrovcmd_dev *dev, bi_list_node *first_linked_cmdbuf_node)
  2316. {
  2317. struct cmdbuf_obj *cmdbuf_obj = NULL;
  2318. if (dev->working_state == WORKING_STATE_IDLE)
  2319. {
  2320. if ((first_linked_cmdbuf_node != NULL) && dev->sw_cmdbuf_rdy_num)
  2321. {
  2322. cmdbuf_obj = (struct cmdbuf_obj *)first_linked_cmdbuf_node->data;
  2323. //0x40
  2324. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_AXI_CLK_GATE_DISABLE, 0);
  2325. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_MASTER_OUT_CLK_GATE_DISABLE, 1); //this bit should be set 1 only when need to reset dec400
  2326. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_CORE_CLK_GATE_DISABLE, 0);
  2327. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_ABORT_MODE, 0);
  2328. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_RESET_CORE, 0);
  2329. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_RESET_ALL, 0);
  2330. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_START_TRIGGER, 0);
  2331. //0x48
  2332. if (dev->hw_version_id <= HW_ID_1_0_C)
  2333. {
  2334. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_IRQ_INTCMD_EN, 0xffff);
  2335. }
  2336. else
  2337. {
  2338. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_IRQ_JMPP_EN, 1);
  2339. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_IRQ_JMPD_EN, 1);
  2340. }
  2341. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_IRQ_RESET_EN, 1);
  2342. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_IRQ_ABORT_EN, 1);
  2343. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_IRQ_CMDERR_EN, 1);
  2344. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_IRQ_TIMEOUT_EN, 1);
  2345. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_IRQ_BUSERR_EN, 1);
  2346. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_IRQ_ENDCMD_EN, 1);
  2347. //0x4c
  2348. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_TIMEOUT_EN, 1);
  2349. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_TIMEOUT_CYCLES, 0x1dcd6500);
  2350. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR, (u32)(cmdbuf_obj->cmdbuf_busAddress - base_ddr_addr));
  2351. if (sizeof(ptr_t) == 8)
  2352. {
  2353. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR_MSB, (u32)((u64)(cmdbuf_obj->cmdbuf_busAddress - base_ddr_addr) >> 32));
  2354. }
  2355. else
  2356. {
  2357. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR_MSB, 0);
  2358. }
  2359. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_EXE_CMDBUF_LENGTH, (u32)((cmdbuf_obj->cmdbuf_size + 7) / 8));
  2360. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_RDY_CMDBUF_COUNT, dev->sw_cmdbuf_rdy_num);
  2361. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_MAX_BURST_LEN, 0x10);
  2362. if (dev->hw_version_id > HW_ID_1_0_C)
  2363. {
  2364. vcmd_write_register_value((const void *)dev->hwregs, dev->reg_mirror, HWIF_VCMD_CMDBUF_EXECUTING_ID, (u32)cmdbuf_obj->cmdbuf_id);
  2365. }
  2366. vcmd_write_reg((const void *)dev->hwregs, 0x40, dev->reg_mirror[0x40 / 4]);
  2367. vcmd_write_reg((const void *)dev->hwregs, 0x44, vcmd_read_reg((const void *)dev->hwregs, 0x44));
  2368. vcmd_write_reg((const void *)dev->hwregs, 0x48, dev->reg_mirror[0x48 / 4]);
  2369. vcmd_write_reg((const void *)dev->hwregs, 0x4c, dev->reg_mirror[0x4c / 4]);
  2370. vcmd_write_reg((const void *)dev->hwregs, 0x50, dev->reg_mirror[0x50 / 4]);
  2371. vcmd_write_reg((const void *)dev->hwregs, 0x54, dev->reg_mirror[0x54 / 4]);
  2372. vcmd_write_reg((const void *)dev->hwregs, 0x58, dev->reg_mirror[0x58 / 4]);
  2373. vcmd_write_reg((const void *)dev->hwregs, 0x5c, dev->reg_mirror[0x5c / 4]);
  2374. vcmd_write_reg((const void *)dev->hwregs, 0x60, dev->reg_mirror[0x60 / 4]);
  2375. #if 1
  2376. vcmd_write_reg((const void *)dev->hwregs, 0x64, 0xffffffff); //not interrupt cpu
  2377. #else
  2378. // Top 20 needs to mask abnormal interrupt
  2379. vcmd_write_reg((const void *)dev->hwregs, 0x64, 0xffff0000);
  2380. #endif
  2381. dev->working_state = WORKING_STATE_WORKING;
  2382. //start
  2383. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_MASTER_OUT_CLK_GATE_DISABLE, 0); //this bit should be set 1 only when need to reset dec400
  2384. vcmd_set_register_mirror_value(dev->reg_mirror, HWIF_VCMD_START_TRIGGER, 1);
  2385. vcmd_write_reg((const void *)dev->hwregs, 0x40, dev->reg_mirror[0x40 / 4]);
  2386. }
  2387. }
  2388. }
  2389. static void create_read_all_registers_cmdbuf(struct exchange_parameter *input_para)
  2390. {
  2391. u32 register_range[] = {VCMD_ENCODER_REGISTER_SIZE,
  2392. VCMD_IM_REGISTER_SIZE,
  2393. VCMD_DECODER_REGISTER_SIZE,
  2394. VCMD_JPEG_ENCODER_REGISTER_SIZE,
  2395. VCMD_JPEG_DECODER_REGISTER_SIZE};
  2396. u32 counter_cmdbuf_size = 0;
  2397. u32 *set_base_addr = vcmd_buf_mem_pool.virtualAddress + input_para->cmdbuf_id * CMDBUF_MAX_SIZE / 4;
  2398. //u32 *status_base_virt_addr=vcmd_status_buf_mem_pool.virtualAddress + input_para->cmdbuf_id*CMDBUF_MAX_SIZE/4+(vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_main_addr/2/4+0);
  2399. ptr_t status_base_phy_addr = vcmd_status_buf_mem_pool.busAddress + input_para->cmdbuf_id * CMDBUF_MAX_SIZE + (vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_main_addr / 2 + 0);
  2400. u32 offset_inc = 0;
  2401. u32 offset_inc_dec400 = 0;
  2402. if (vcmd_manager[input_para->module_type][0]->hw_version_id > HW_ID_1_0_C)
  2403. {
  2404. printk(KERN_INFO "vc8000_vcmd_driver:create cmdbuf data when hw_version_id = 0x%x\n", vcmd_manager[input_para->module_type][0]->hw_version_id);
  2405. //read vcmd executing cmdbuf id registers to ddr for balancing core load.
  2406. *(set_base_addr + 0) = (OPCODE_RREG) | (1 << 16) | (EXECUTING_CMDBUF_ID_ADDR * 4);
  2407. counter_cmdbuf_size += 4;
  2408. *(set_base_addr + 1) = (u32)0; //will be changed in link stage
  2409. counter_cmdbuf_size += 4;
  2410. *(set_base_addr + 2) = (u32)0; //will be changed in link stage
  2411. counter_cmdbuf_size += 4;
  2412. //alignment
  2413. *(set_base_addr + 3) = 0;
  2414. counter_cmdbuf_size += 4;
  2415. //read main IP all registers
  2416. *(set_base_addr + 4) = (OPCODE_RREG) | ((register_range[input_para->module_type] / 4) << 16) | (vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_main_addr + 0);
  2417. counter_cmdbuf_size += 4;
  2418. *(set_base_addr + 5) = (u32)(status_base_phy_addr - base_ddr_addr);
  2419. counter_cmdbuf_size += 4;
  2420. if (sizeof(ptr_t) == 8)
  2421. {
  2422. *(set_base_addr + 6) = (u32)((u64)(status_base_phy_addr - base_ddr_addr) >> 32);
  2423. }
  2424. else
  2425. {
  2426. *(set_base_addr + 6) = 0;
  2427. }
  2428. counter_cmdbuf_size += 4;
  2429. //alignment
  2430. *(set_base_addr + 7) = 0;
  2431. counter_cmdbuf_size += 4;
  2432. if (vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_L2Cache_addr != 0xffff)
  2433. {
  2434. //read L2 cache register
  2435. offset_inc = 4;
  2436. status_base_phy_addr = vcmd_status_buf_mem_pool.busAddress + input_para->cmdbuf_id * CMDBUF_MAX_SIZE + (vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_L2Cache_addr / 2 + 0);
  2437. //read L2cache IP first register
  2438. *(set_base_addr + 8) = (OPCODE_RREG) | (1 << 16) | (vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_L2Cache_addr + 0);
  2439. counter_cmdbuf_size += 4;
  2440. *(set_base_addr + 9) = (u32)(status_base_phy_addr - base_ddr_addr);
  2441. counter_cmdbuf_size += 4;
  2442. if (sizeof(ptr_t) == 8)
  2443. {
  2444. *(set_base_addr + 10) = (u32)((u64)(status_base_phy_addr - base_ddr_addr) >> 32);
  2445. }
  2446. else
  2447. {
  2448. *(set_base_addr + 10) = 0;
  2449. }
  2450. counter_cmdbuf_size += 4;
  2451. //alignment
  2452. *(set_base_addr + 11) = 0;
  2453. counter_cmdbuf_size += 4;
  2454. }
  2455. #if 0
  2456. if (vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_dec400_addr != 0xffff)
  2457. {
  2458. //read dec400 register
  2459. offset_inc_dec400 = 4;
  2460. status_base_phy_addr = vcmd_status_buf_mem_pool.busAddress + input_para->cmdbuf_id * CMDBUF_MAX_SIZE + (vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_dec400_addr / 2 + 0);
  2461. //read L2cache IP first register
  2462. *(set_base_addr + 8 + offset_inc) = (OPCODE_RREG) | (0x2b << 16) | (vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_dec400_addr + 0);
  2463. counter_cmdbuf_size += 4;
  2464. *(set_base_addr + 9 + offset_inc) = (u32)(status_base_phy_addr - base_ddr_addr);
  2465. counter_cmdbuf_size += 4;
  2466. if (sizeof(ptr_t) == 8)
  2467. {
  2468. *(set_base_addr + 10 + offset_inc) = (u32)((u64)(status_base_phy_addr - base_ddr_addr) >> 32);
  2469. }
  2470. else
  2471. {
  2472. *(set_base_addr + 10 + offset_inc) = 0;
  2473. }
  2474. counter_cmdbuf_size += 4;
  2475. //alignment
  2476. *(set_base_addr + 11 + offset_inc) = 0;
  2477. counter_cmdbuf_size += 4;
  2478. }
  2479. #endif
  2480. #if 0
  2481. //INT code, interrupt immediately
  2482. *(set_base_addr+4) = (OPCODE_INT) |0 |input_para->cmdbuf_id;
  2483. counter_cmdbuf_size += 4;
  2484. //alignment
  2485. *(set_base_addr+5) = 0;
  2486. counter_cmdbuf_size += 4;
  2487. #endif
  2488. //read vcmd registers to ddr
  2489. *(set_base_addr + 8 + offset_inc + offset_inc_dec400) = (OPCODE_RREG) | (27 << 16) | (0);
  2490. counter_cmdbuf_size += 4;
  2491. *(set_base_addr + 9 + offset_inc + offset_inc_dec400) = (u32)0; //will be changed in link stage
  2492. counter_cmdbuf_size += 4;
  2493. *(set_base_addr + 10 + offset_inc + offset_inc_dec400) = (u32)0; //will be changed in link stage
  2494. counter_cmdbuf_size += 4;
  2495. //alignment
  2496. *(set_base_addr + 11 + offset_inc + offset_inc_dec400) = 0;
  2497. counter_cmdbuf_size += 4;
  2498. //JMP RDY = 0
  2499. *(set_base_addr + 12 + offset_inc + offset_inc_dec400) = (OPCODE_JMP_RDY0) | 0 | JMP_IE_1 | 0;
  2500. counter_cmdbuf_size += 4;
  2501. *(set_base_addr + 13 + offset_inc + offset_inc_dec400) = 0;
  2502. counter_cmdbuf_size += 4;
  2503. *(set_base_addr + 14 + offset_inc + offset_inc_dec400) = 0;
  2504. counter_cmdbuf_size += 4;
  2505. *(set_base_addr + 15 + offset_inc + offset_inc_dec400) = input_para->cmdbuf_id;
  2506. //don't add the last alignment DWORD in order to identify END command or JMP command.
  2507. //counter_cmdbuf_size += 4;
  2508. input_para->cmdbuf_size = (16 + offset_inc + offset_inc_dec400) * 4;
  2509. }
  2510. else
  2511. {
  2512. printk(KERN_INFO "vc8000_vcmd_driver:create cmdbuf data when hw_version_id = 0x%x\n", vcmd_manager[input_para->module_type][0]->hw_version_id);
  2513. //read all registers
  2514. *(set_base_addr + 0) = (OPCODE_RREG) | ((register_range[input_para->module_type] / 4) << 16) | (vcmd_manager[input_para->module_type][0]->vcmd_core_cfg.submodule_main_addr + 0);
  2515. counter_cmdbuf_size += 4;
  2516. *(set_base_addr + 1) = (u32)(status_base_phy_addr - base_ddr_addr);
  2517. counter_cmdbuf_size += 4;
  2518. if (sizeof(ptr_t) == 8)
  2519. {
  2520. *(set_base_addr + 2) = (u32)((u64)(status_base_phy_addr - base_ddr_addr) >> 32);
  2521. }
  2522. else
  2523. {
  2524. *(set_base_addr + 2) = 0;
  2525. }
  2526. counter_cmdbuf_size += 4;
  2527. //alignment
  2528. *(set_base_addr + 3) = 0;
  2529. counter_cmdbuf_size += 4;
  2530. #if 0
  2531. //INT code, interrupt immediately
  2532. *(set_base_addr+4) = (OPCODE_INT) |0 |input_para->cmdbuf_id;
  2533. counter_cmdbuf_size += 4;
  2534. //alignment
  2535. *(set_base_addr+5) = 0;
  2536. counter_cmdbuf_size += 4;
  2537. #endif
  2538. //JMP RDY = 0
  2539. *(set_base_addr + 4) = (OPCODE_JMP_RDY0) | 0 | JMP_IE_1 | 0;
  2540. counter_cmdbuf_size += 4;
  2541. *(set_base_addr + 5) = 0;
  2542. counter_cmdbuf_size += 4;
  2543. *(set_base_addr + 6) = 0;
  2544. counter_cmdbuf_size += 4;
  2545. *(set_base_addr + 7) = input_para->cmdbuf_id;
  2546. //don't add the last alignment DWORD in order to identify END command or JMP command.
  2547. //counter_cmdbuf_size += 4;
  2548. input_para->cmdbuf_size = 8 * 4;
  2549. }
  2550. }
  2551. volatile int tmpTimer=100000;
  2552. static void read_main_module_all_registers(u32 main_module_type)
  2553. {
  2554. int ret;
  2555. struct exchange_parameter input_para;
  2556. u32 irq_status_ret = 0;
  2557. u32 *status_base_virt_addr;
  2558. input_para.executing_time = 0;
  2559. input_para.priority = CMDBUF_PRIORITY_NORMAL;
  2560. input_para.module_type = main_module_type;
  2561. input_para.cmdbuf_size = 0;
  2562. //ret = reserve_cmdbuf(NULL,&input_para);
  2563. ret = reserve_cmdbuf(0, &input_para);
  2564. vcmd_manager[main_module_type][0]->status_cmdbuf_id = input_para.cmdbuf_id;
  2565. create_read_all_registers_cmdbuf(&input_para);
  2566. //link_and_run_cmdbuf(NULL,&input_para);
  2567. link_and_run_cmdbuf(0, &input_para);
  2568. #if 0
  2569. msleep(1000);
  2570. #else
  2571. while(tmpTimer--);
  2572. #endif
  2573. hantrovcmd_isr(/*input_para.core_id,*/ &hantrovcmd_data[input_para.core_id]);
  2574. //wait_cmdbuf_ready(NULL,input_para.cmdbuf_id,&irq_status_ret);
  2575. wait_cmdbuf_ready(0, input_para.cmdbuf_id, &irq_status_ret);
  2576. status_base_virt_addr = vcmd_status_buf_mem_pool.virtualAddress + input_para.cmdbuf_id * CMDBUF_MAX_SIZE / 4 + (vcmd_manager[input_para.module_type][0]->vcmd_core_cfg.submodule_main_addr / 2 / 4 + 0);
  2577. printf(KERN_INFO "vc8000_vcmd_driver: main module register 0:0x%x\n", *status_base_virt_addr);
  2578. printf(KERN_INFO "vc8000_vcmd_driver: main module register 50:0x%08x\n", *(status_base_virt_addr + 50));
  2579. printf(KERN_INFO "vc8000_vcmd_driver: main module register 54:0x%08x\n", *(status_base_virt_addr + 54));
  2580. printf(KERN_INFO "vc8000_vcmd_driver: main module register 56:0x%08x\n", *(status_base_virt_addr + 56));
  2581. printf(KERN_INFO "vc8000_vcmd_driver: main module register 309:0x%08x\n", *(status_base_virt_addr + 309));
  2582. //don't release cmdbuf because it can be used repeatedly
  2583. //release_cmdbuf(NULL, input_para.cmdbuf_id);
  2584. //release_cmdbuf(0,input_para.cmdbuf_id);
  2585. }
  2586. int __init hantrovcmd_init(void)
  2587. {
  2588. int i = 0, k = 0;
  2589. int result = 0, irq_enabled = 0;
  2590. total_vcmd_core_num = sizeof(vcmd_core_array) / sizeof(struct vcmd_config);
  2591. result = vcmd_pcie_init();
  2592. if (result)
  2593. goto err1;
  2594. for (i = 0; i < total_vcmd_core_num; i++)
  2595. {
  2596. printk(KERN_INFO "vcmd: module init - vcmdcore[%d] addr =0x%llx\n", i,
  2597. (long long unsigned int)vcmd_core_array[i].vcmd_base_addr);
  2598. }
  2599. hantrovcmd_data = (struct hantrovcmd_dev *)vmalloc(sizeof(struct hantrovcmd_dev) * total_vcmd_core_num);
  2600. if (hantrovcmd_data == NULL)
  2601. goto err1;
  2602. memset(hantrovcmd_data, 0, sizeof(struct hantrovcmd_dev) * total_vcmd_core_num);
  2603. for (k = 0; k < MAX_VCMD_TYPE; k++)
  2604. {
  2605. vcmd_type_core_num[k] = 0;
  2606. vcmd_position[k] = 0;
  2607. for (i = 0; i < MAX_VCMD_NUMBER; i++)
  2608. {
  2609. vcmd_manager[k][i] = NULL;
  2610. }
  2611. }
  2612. #if PROCESS_MANAGER
  2613. init_bi_list(&global_process_manager);
  2614. #endif
  2615. for (i = 0; i < total_vcmd_core_num; i++)
  2616. {
  2617. hantrovcmd_data[i].vcmd_core_cfg = vcmd_core_array[i];
  2618. hantrovcmd_data[i].hwregs = NULL;
  2619. hantrovcmd_data[i].core_id = i;
  2620. hantrovcmd_data[i].working_state = WORKING_STATE_IDLE;
  2621. hantrovcmd_data[i].sw_cmdbuf_rdy_num = 0;
  2622. hantrovcmd_data[i].spinlock = &owner_lock_vcmd[i];
  2623. spin_lock_init(&owner_lock_vcmd[i]);
  2624. #if 1
  2625. // hantrovcmd_data[i].wait_queue = &wait_queue_vcmd[i];
  2626. //wait_queue_vcmd[i] = xSemaphoreCreateCounting(0x7FFU, 0);
  2627. // sem_init(&wait_queue_vcmd[i], 0, 0);
  2628. // hantrovcmd_data[i].wait_abort_queue=&abort_queue_vcmd[i];
  2629. //abort_queue_vcmd[i] = xSemaphoreCreateCounting(0x7FFU, 0);
  2630. // sem_init(&abort_queue_vcmd[i], 0, 0);
  2631. #else
  2632. hantrovcmd_data[i].wait_queue = &wait_queue_vcmd[i];
  2633. init_waitqueue_head(&wait_queue_vcmd[i]);
  2634. hantrovcmd_data[i].wait_abort_queue = &abort_queue_vcmd[i];
  2635. init_waitqueue_head(&abort_queue_vcmd[i]);
  2636. #endif
  2637. init_bi_list(&hantrovcmd_data[i].list_manager);
  2638. hantrovcmd_data[i].duration_without_int = 0;
  2639. vcmd_manager[vcmd_core_array[i].sub_module_type][vcmd_type_core_num[vcmd_core_array[i].sub_module_type]] = &hantrovcmd_data[i];
  2640. vcmd_type_core_num[vcmd_core_array[i].sub_module_type]++;
  2641. hantrovcmd_data[i].vcmd_reg_mem_busAddress = vcmd_registers_mem_pool.busAddress + i * VCMD_REGISTER_SIZE - base_ddr_addr;
  2642. hantrovcmd_data[i].vcmd_reg_mem_virtualAddress = vcmd_registers_mem_pool.virtualAddress + i * VCMD_REGISTER_SIZE / 4;
  2643. hantrovcmd_data[i].vcmd_reg_mem_size = VCMD_REGISTER_SIZE;
  2644. memset(hantrovcmd_data[i].vcmd_reg_mem_virtualAddress, 0, VCMD_REGISTER_SIZE);
  2645. }
  2646. //init_waitqueue_head(&mc_wait_queue);
  2647. //sema_init(&mc_wait_queue, 0);
  2648. queue_vcmd_init(&mc_wait_queue);
  2649. for (i = 0; i < TOTAL_DISCRETE_CMDBUF_NUM; i++)
  2650. {
  2651. queue_vcmd_init(&wait_queue_vcmd[i]);
  2652. queue_vcmd_init(&abort_queue_vcmd[i]);
  2653. }
  2654. result = register_chrdev(hantrovcmd_major, "vc8000_vcmd_driver", &hantrovcmd_fops);
  2655. if (result < 0)
  2656. {
  2657. printk(KERN_INFO "vc8000_vcmd_driver: unable to get major <%d>\n",
  2658. hantrovcmd_major);
  2659. goto err1;
  2660. }
  2661. else if (result != 0) /* this is for dynamic major */
  2662. {
  2663. hantrovcmd_major = result;
  2664. }
  2665. result = vcmd_reserve_IO();
  2666. if (result < 0)
  2667. {
  2668. goto err;
  2669. }
  2670. vcmd_reset_asic(hantrovcmd_data);
  2671. /* get the IRQ line */
  2672. for (i = 0; i < total_vcmd_core_num; i++)
  2673. {
  2674. if (hantrovcmd_data[i].hwregs == NULL)
  2675. continue;
  2676. if (hantrovcmd_data[i].vcmd_core_cfg.vcmd_irq != -1)
  2677. {
  2678. //cpu interrrupt enable
  2679. IntEnableIRQ(hantrovcmd_data[i].vcmd_core_cfg.vcmd_irq);
  2680. irq_enabled = 1;
  2681. }
  2682. else
  2683. {
  2684. printk(KERN_INFO "vc8000_vcmd_driver: IRQ not in use!\n");
  2685. }
  2686. }
  2687. if (irq_enabled == 1)
  2688. {
  2689. result = request_irq(CPU_INT_IRQ, hantrovcmd_isr,
  2690. IRQF_SHARED,
  2691. "vc8000_vcmd_driver", (void *)&hantrovcmd_data[i]);
  2692. if (result == -EINVAL)
  2693. {
  2694. printk(KERN_ERR "vc8000_vcmd_driver: Bad vcmd_irq number or handler, core_id=%d\n", i);
  2695. vcmd_release_IO();
  2696. goto err;
  2697. }
  2698. else if (result == -EBUSY)
  2699. {
  2700. printk(KERN_ERR "vc8000_vcmd_driver: IRQ <%d> busy, change your config, core_id=%d\n",
  2701. hantrovcmd_data[i].vcmd_core_cfg.vcmd_irq, i);
  2702. vcmd_release_IO();
  2703. goto err;
  2704. }
  2705. }
  2706. //cmdbuf pool allocation
  2707. //init_vcmd_non_cachable_memory_allocate();
  2708. //for cmdbuf management
  2709. cmdbuf_used_pos = 0;
  2710. for (k = 0; k < TOTAL_DISCRETE_CMDBUF_NUM; k++)
  2711. {
  2712. cmdbuf_used[k] = 0;
  2713. global_cmdbuf_node[k] = NULL;
  2714. }
  2715. //cmdbuf_used[0] not be used, because int vector must non-zero
  2716. cmdbuf_used_residual = TOTAL_DISCRETE_CMDBUF_NUM;
  2717. cmdbuf_used_pos = 1;
  2718. cmdbuf_used[0] = 1;
  2719. cmdbuf_used_residual -= 1;
  2720. printk(KERN_INFO "vc8000_vcmd_driver: module inserted. Major <%d>\n", hantrovcmd_major);
  2721. #if PROCESS_MANAGER
  2722. create_kernel_process_manager();
  2723. #endif
  2724. for (i = 0; i < MAX_VCMD_TYPE; i++)
  2725. {
  2726. if (vcmd_type_core_num[i] == 0)
  2727. continue;
  2728. #if 1
  2729. vcmd_reserve_cmdbuf_sem[i] = PTHREAD_MUTEX_INITIALIZER;
  2730. #else
  2731. sema_init(&vcmd_reserve_cmdbuf_sem[i], 1);
  2732. #endif
  2733. }
  2734. sema_init(&vcmd_cmdbuf_memory_wait, TOTAL_DISCRETE_CMDBUF_NUM - 1);
  2735. #ifdef IRQ_SIMULATION
  2736. for (i = 0; i < 10000; i++)
  2737. {
  2738. timer_reserve[i].timer = NULL;
  2739. }
  2740. #endif
  2741. /*read all registers for each type of module for analyzing configuration in cwl*/
  2742. vcmd_init_flag = 1;
  2743. for (i = 0; i < MAX_VCMD_TYPE; i++)
  2744. {
  2745. if (vcmd_type_core_num[i] == 0)
  2746. continue;
  2747. read_main_module_all_registers(i);
  2748. }
  2749. vcmd_init_flag = 0;
  2750. printf("vcmd init successful...\n");
  2751. return 0;
  2752. err:
  2753. unregister_chrdev(hantrovcmd_major, "vc8000_vcmd_driver");
  2754. err1:
  2755. if (hantrovcmd_data != NULL)
  2756. vfree(hantrovcmd_data);
  2757. printk(KERN_INFO "vc8000_vcmd_driver: module not inserted\n");
  2758. return result;
  2759. }
  2760. void __exit hantrovcmd_cleanup(void)
  2761. {
  2762. int i = 0;
  2763. u32 result;
  2764. for (i = 0; i < total_vcmd_core_num; i++)
  2765. {
  2766. if (hantrovcmd_data[i].hwregs == NULL)
  2767. continue;
  2768. //disable interrupt at first
  2769. vcmd_write_reg((const void *)hantrovcmd_data[i].hwregs, VCMD_REGISTER_INT_CTL_OFFSET, 0x0000);
  2770. //disable HW
  2771. vcmd_write_reg((const void *)hantrovcmd_data[i].hwregs, VCMD_REGISTER_CONTROL_OFFSET, 0x0000);
  2772. //read status register
  2773. result = vcmd_read_reg((const void *)hantrovcmd_data[i].hwregs, VCMD_REGISTER_INT_STATUS_OFFSET);
  2774. //clean status register
  2775. vcmd_write_reg((const void *)hantrovcmd_data[i].hwregs, VCMD_REGISTER_INT_STATUS_OFFSET, result);
  2776. /* free the vcmd IRQ */
  2777. if (hantrovcmd_data[i].vcmd_core_cfg.vcmd_irq != -1)
  2778. {
  2779. free_irq(hantrovcmd_data[i].vcmd_core_cfg.vcmd_irq, (void *)&hantrovcmd_data[i]);
  2780. }
  2781. release_cmdbuf_node_cleanup(&hantrovcmd_data[i].list_manager);
  2782. }
  2783. #if PROCESS_MANAGER
  2784. release_process_node_cleanup(&global_process_manager);
  2785. #endif
  2786. vcmd_release_IO();
  2787. vfree(hantrovcmd_data);
  2788. //release_vcmd_non_cachable_memory();
  2789. iounmap((void *)vcmd_buf_mem_pool.virtualAddress);
  2790. release_mem_region(vcmd_buf_mem_pool.busAddress, vcmd_buf_mem_pool.size);
  2791. iounmap((void *)vcmd_status_buf_mem_pool.virtualAddress);
  2792. release_mem_region(vcmd_status_buf_mem_pool.busAddress, vcmd_status_buf_mem_pool.size);
  2793. iounmap((void *)vcmd_registers_mem_pool.virtualAddress);
  2794. release_mem_region(vcmd_registers_mem_pool.busAddress, vcmd_registers_mem_pool.size);
  2795. unregister_chrdev(hantrovcmd_major, "vc8000_vcmd_driver");
  2796. printk(KERN_INFO "vc8000_vcmd_driver: module removed\n");
  2797. return;
  2798. }
  2799. static int vcmd_reserve_IO(void)
  2800. {
  2801. u32 hwid;
  2802. int i;
  2803. u32 found_hw = 0;
  2804. for (i = 0; i < total_vcmd_core_num; i++)
  2805. {
  2806. hantrovcmd_data[i].hwregs = NULL;
  2807. if (!request_mem_region(hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr, hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize, "vc8000_vcmd_driver"))
  2808. {
  2809. printk(KERN_INFO "hantrovcmd: failed to reserve HW regs\n");
  2810. continue;
  2811. }
  2812. hantrovcmd_data[i].hwregs =
  2813. (volatile u8 *)ioremap_nocache(hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr,
  2814. hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize);
  2815. if (hantrovcmd_data[i].hwregs == NULL)
  2816. {
  2817. printk(KERN_INFO "hantrovcmd: failed to ioremap HW regs\n");
  2818. release_mem_region(hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr, hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize);
  2819. continue;
  2820. }
  2821. /*read hwid and check validness and store it*/
  2822. hwid = (u32)ioread32((void *)hantrovcmd_data[i].hwregs);
  2823. printk(KERN_INFO "hwid=0x%08x\n", hwid);
  2824. hantrovcmd_data[i].hw_version_id = hwid;
  2825. /* check for vcmd HW ID */
  2826. if (((hwid >> 16) & 0xFFFF) != VCMD_HW_ID)
  2827. {
  2828. printk(KERN_INFO "hantrovcmd: HW not found at 0x%llx\n",
  2829. (long long unsigned int)hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr);
  2830. iounmap((void *)hantrovcmd_data[i].hwregs);
  2831. release_mem_region(hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr, hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize);
  2832. hantrovcmd_data[i].hwregs = NULL;
  2833. continue;
  2834. }
  2835. found_hw = 1;
  2836. printk(KERN_INFO
  2837. "hantrovcmd: HW at base <0x%llx> with ID <0x%08x>\n",
  2838. (long long unsigned int)hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr, hwid);
  2839. }
  2840. if (found_hw == 0)
  2841. {
  2842. printk(KERN_ERR "hantrovcmd: NO ANY HW found!!\n");
  2843. return -1;
  2844. }
  2845. return 0;
  2846. }
  2847. static void vcmd_release_IO(void)
  2848. {
  2849. u32 i;
  2850. for (i = 0; i < total_vcmd_core_num; i++)
  2851. {
  2852. if (hantrovcmd_data[i].hwregs)
  2853. {
  2854. iounmap((void *)hantrovcmd_data[i].hwregs);
  2855. release_mem_region(hantrovcmd_data[i].vcmd_core_cfg.vcmd_base_addr, hantrovcmd_data[i].vcmd_core_cfg.vcmd_iosize);
  2856. hantrovcmd_data[i].hwregs = NULL;
  2857. }
  2858. }
  2859. }
  2860. static irqreturn_t ProcessingInterrupt(void *dev_id, unsigned int * handled)
  2861. {
  2862. struct hantrovcmd_dev *dev = (struct hantrovcmd_dev *) dev_id;
  2863. unsigned long flags = 0;
  2864. bi_list_node *new_cmdbuf_node = NULL;
  2865. bi_list_node *base_cmdbuf_node = NULL;
  2866. struct cmdbuf_obj *cmdbuf_obj = NULL;
  2867. ptr_t /*size_t*/ exe_cmdbuf_busAddress = 0;
  2868. u32 irq_status = 0;
  2869. u32 cmdbuf_processed_num = 0;
  2870. u32 cmdbuf_id = 0;
  2871. /*If core is not reserved by any user, but irq is received, just clean it*/
  2872. isr_spin_lock_irqsave(dev->spinlock, flags);
  2873. if (dev->list_manager.head == NULL)
  2874. {
  2875. PDEBUG("In ISR, received IRQ but core has nothing to do.\n");
  2876. irq_status = vcmd_read_reg((const void *)dev->hwregs, VCMD_REGISTER_INT_STATUS_OFFSET);
  2877. vcmd_write_reg((const void *)dev->hwregs, VCMD_REGISTER_INT_STATUS_OFFSET, irq_status);
  2878. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  2879. return IRQ_HANDLED;
  2880. }
  2881. irq_status = vcmd_read_reg((const void *)dev->hwregs, VCMD_REGISTER_INT_STATUS_OFFSET);
  2882. #ifdef VCMD_DEBUG_INTERNAL
  2883. {
  2884. u32 i, fordebug;
  2885. for (i = 0; i < ASIC_VCMD_SWREG_AMOUNT; i++)
  2886. {
  2887. fordebug = vcmd_read_reg((const void *)dev->hwregs, i * 4);
  2888. printk(KERN_INFO "vcmd register %d:0x%x\n", i, fordebug);
  2889. }
  2890. }
  2891. #endif
  2892. if (!irq_status)
  2893. {
  2894. //printk(KERN_INFO"hantrovcmd_isr error,irq_status :0x%x",irq_status);
  2895. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  2896. return IRQ_HANDLED;
  2897. }
  2898. PDEBUG("In ISR, received IRQ, irq_status of %d is:%x\n", dev->core_id, irq_status);
  2899. vcmd_write_reg((const void *)dev->hwregs, VCMD_REGISTER_INT_STATUS_OFFSET, irq_status);
  2900. dev->reg_mirror[VCMD_REGISTER_INT_STATUS_OFFSET / 4] = irq_status;
  2901. if ((dev->hw_version_id > HW_ID_1_0_C) && (irq_status & 0x3f))
  2902. {
  2903. //if error,read from register directly.
  2904. cmdbuf_id = vcmd_get_register_value((const void *)dev->hwregs, dev->reg_mirror, HWIF_VCMD_CMDBUF_EXECUTING_ID);
  2905. if (cmdbuf_id >= TOTAL_DISCRETE_CMDBUF_NUM)
  2906. {
  2907. printk(KERN_ERR "hantrovcmd_isr error cmdbuf_id greater than the ceiling !!\n");
  2908. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  2909. return IRQ_HANDLED;
  2910. }
  2911. }
  2912. else if ((dev->hw_version_id > HW_ID_1_0_C))
  2913. {
  2914. //read cmdbuf id from ddr
  2915. #ifdef VCMD_DEBUG_INTERNAL
  2916. {
  2917. u32 i, fordebug;
  2918. printk(KERN_INFO "ddr vcmd register phy_addr=0x%x\n", dev->vcmd_reg_mem_busAddress);
  2919. printk(KERN_INFO "ddr vcmd register virt_addr=0x%x\n", dev->vcmd_reg_mem_virtualAddress);
  2920. for (i = 0; i < ASIC_VCMD_SWREG_AMOUNT; i++)
  2921. {
  2922. fordebug = *(dev->vcmd_reg_mem_virtualAddress + i);
  2923. printk(KERN_INFO "ddr vcmd register %d:0x%x\n", i, fordebug);
  2924. }
  2925. }
  2926. #endif
  2927. cmdbuf_id = *(dev->vcmd_reg_mem_virtualAddress + EXECUTING_CMDBUF_ID_ADDR);
  2928. PDEBUG("In ISR, the current cmdbuf_id is [%d]\n", cmdbuf_id);
  2929. if (cmdbuf_id >= TOTAL_DISCRETE_CMDBUF_NUM)
  2930. {
  2931. printk(KERN_ERR "hantrovcmd_isr error cmdbuf_id greater than the ceiling !!\n");
  2932. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  2933. return IRQ_HANDLED;
  2934. }
  2935. }
  2936. if (vcmd_get_register_mirror_value(dev->reg_mirror, HWIF_VCMD_IRQ_RESET))
  2937. {
  2938. //reset error,all cmdbuf that is not done will be run again.
  2939. new_cmdbuf_node = dev->list_manager.head;
  2940. dev->working_state = WORKING_STATE_IDLE;
  2941. //find the first run_done=0
  2942. while (1)
  2943. {
  2944. if (new_cmdbuf_node == NULL)
  2945. break;
  2946. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  2947. if (cmdbuf_obj->cmdbuf_run_done == 0)
  2948. break;
  2949. new_cmdbuf_node = new_cmdbuf_node->next;
  2950. }
  2951. base_cmdbuf_node = new_cmdbuf_node;
  2952. vcmd_delink_cmdbuf(dev, base_cmdbuf_node);
  2953. vcmd_link_cmdbuf(dev, base_cmdbuf_node);
  2954. if (dev->sw_cmdbuf_rdy_num != 0)
  2955. {
  2956. //restart new command
  2957. vcmd_start(dev, base_cmdbuf_node);
  2958. }
  2959. (*handled)++;
  2960. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  2961. return IRQ_HANDLED;
  2962. }
  2963. if (vcmd_get_register_mirror_value(dev->reg_mirror, HWIF_VCMD_IRQ_ABORT))
  2964. {
  2965. //abort error,don't need to reset
  2966. new_cmdbuf_node = dev->list_manager.head;
  2967. dev->working_state = WORKING_STATE_IDLE;
  2968. if (dev->hw_version_id > HW_ID_1_0_C)
  2969. {
  2970. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  2971. if (new_cmdbuf_node == NULL)
  2972. {
  2973. printk(KERN_ERR "hantrovcmd_isr error cmdbuf_id !!\n");
  2974. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  2975. return IRQ_HANDLED;
  2976. }
  2977. }
  2978. else
  2979. {
  2980. exe_cmdbuf_busAddress = VCMDGetAddrRegisterValue((const void *)dev->hwregs, dev->reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR);
  2981. //find the cmderror cmdbuf
  2982. while (1)
  2983. {
  2984. if (new_cmdbuf_node == NULL)
  2985. {
  2986. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  2987. return IRQ_HANDLED;
  2988. }
  2989. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  2990. if ((((cmdbuf_obj->cmdbuf_busAddress - base_ddr_addr) <= exe_cmdbuf_busAddress) && (((cmdbuf_obj->cmdbuf_busAddress - base_ddr_addr + cmdbuf_obj->cmdbuf_size) > exe_cmdbuf_busAddress))) && (cmdbuf_obj->cmdbuf_run_done == 0))
  2991. break;
  2992. new_cmdbuf_node = new_cmdbuf_node->next;
  2993. }
  2994. }
  2995. base_cmdbuf_node = new_cmdbuf_node;
  2996. // this cmdbuf and cmdbufs prior to itself, run_done = 1
  2997. while (1)
  2998. {
  2999. if (new_cmdbuf_node == NULL)
  3000. break;
  3001. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  3002. if (cmdbuf_obj->cmdbuf_run_done == 0)
  3003. {
  3004. cmdbuf_obj->cmdbuf_run_done = 1;
  3005. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  3006. queue_vcmd_wakeup(&wait_queue_vcmd[cmdbuf_obj->cmdbuf_id]);
  3007. cmdbuf_processed_num++;
  3008. }
  3009. else
  3010. break;
  3011. new_cmdbuf_node = new_cmdbuf_node->previous;
  3012. }
  3013. base_cmdbuf_node = base_cmdbuf_node->next;
  3014. vcmd_delink_cmdbuf(dev, base_cmdbuf_node);
  3015. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  3016. #if 1
  3017. //queue_vcmd_wakeup(&abort_queue_vcmd[cmdbuf_id]);
  3018. queue_vcmd_wakeup(&mc_wait_queue);
  3019. #else
  3020. if (cmdbuf_processed_num)
  3021. wake_up_interruptible_all(dev->wait_queue);
  3022. //to let high priority cmdbuf be inserted
  3023. wake_up_interruptible_all(dev->wait_abort_queue);
  3024. wake_up_interruptible_all(&mc_wait_queue);
  3025. #endif
  3026. (*handled)++;
  3027. return IRQ_HANDLED;
  3028. }
  3029. if (vcmd_get_register_mirror_value(dev->reg_mirror, HWIF_VCMD_IRQ_BUSERR))
  3030. {
  3031. //bus error ,don't need to reset , where to record status?
  3032. new_cmdbuf_node = dev->list_manager.head;
  3033. dev->working_state = WORKING_STATE_IDLE;
  3034. if (dev->hw_version_id > HW_ID_1_0_C)
  3035. {
  3036. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  3037. if (new_cmdbuf_node == NULL)
  3038. {
  3039. printk(KERN_ERR "hantrovcmd_isr error cmdbuf_id !!\n");
  3040. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  3041. return IRQ_HANDLED;
  3042. }
  3043. }
  3044. else
  3045. {
  3046. exe_cmdbuf_busAddress = VCMDGetAddrRegisterValue((const void *)dev->hwregs, dev->reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR);
  3047. //find the buserr cmdbuf
  3048. while (1)
  3049. {
  3050. if (new_cmdbuf_node == NULL)
  3051. {
  3052. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  3053. return IRQ_HANDLED;
  3054. }
  3055. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  3056. if ((((cmdbuf_obj->cmdbuf_busAddress - base_ddr_addr) <= exe_cmdbuf_busAddress) && (((cmdbuf_obj->cmdbuf_busAddress - base_ddr_addr + cmdbuf_obj->cmdbuf_size) > exe_cmdbuf_busAddress))) && (cmdbuf_obj->cmdbuf_run_done == 0))
  3057. break;
  3058. new_cmdbuf_node = new_cmdbuf_node->next;
  3059. }
  3060. }
  3061. base_cmdbuf_node = new_cmdbuf_node;
  3062. // this cmdbuf and cmdbufs prior to itself, run_done = 1
  3063. while (1)
  3064. {
  3065. if (new_cmdbuf_node == NULL)
  3066. break;
  3067. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  3068. if (cmdbuf_obj->cmdbuf_run_done == 0)
  3069. {
  3070. cmdbuf_obj->cmdbuf_run_done = 1;
  3071. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  3072. //queue_vcmd_wakeup(&wait_queue_vcmd[cmdbuf_obj->cmdbuf_id]);
  3073. cmdbuf_processed_num++;
  3074. }
  3075. else
  3076. break;
  3077. new_cmdbuf_node = new_cmdbuf_node->previous;
  3078. }
  3079. new_cmdbuf_node = base_cmdbuf_node;
  3080. if (new_cmdbuf_node != NULL)
  3081. {
  3082. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  3083. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_BUSERR;
  3084. }
  3085. base_cmdbuf_node = base_cmdbuf_node->next;
  3086. vcmd_delink_cmdbuf(dev, base_cmdbuf_node);
  3087. vcmd_link_cmdbuf(dev, base_cmdbuf_node);
  3088. if (dev->sw_cmdbuf_rdy_num != 0)
  3089. {
  3090. //restart new command
  3091. vcmd_start(dev, base_cmdbuf_node);
  3092. }
  3093. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  3094. #if PROCESS_MANAGER
  3095. if (cmdbuf_processed_num)
  3096. wake_up_interruptible_all(dev->wait_queue);
  3097. #endif
  3098. (*handled)++;
  3099. //wake_up_interruptible_all(&mc_wait_queue);
  3100. queue_vcmd_wakeup(&mc_wait_queue);
  3101. return IRQ_HANDLED;
  3102. }
  3103. if (vcmd_get_register_mirror_value(dev->reg_mirror, HWIF_VCMD_IRQ_TIMEOUT))
  3104. {
  3105. //time out,need to reset
  3106. new_cmdbuf_node = dev->list_manager.head;
  3107. dev->working_state = WORKING_STATE_IDLE;
  3108. if (dev->hw_version_id > HW_ID_1_0_C)
  3109. {
  3110. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  3111. if (new_cmdbuf_node == NULL)
  3112. {
  3113. printk(KERN_ERR "hantrovcmd_isr error cmdbuf_id !!\n");
  3114. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  3115. return IRQ_HANDLED;
  3116. }
  3117. }
  3118. else
  3119. {
  3120. exe_cmdbuf_busAddress = VCMDGetAddrRegisterValue((const void *)dev->hwregs, dev->reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR);
  3121. //find the timeout cmdbuf
  3122. while (1)
  3123. {
  3124. if (new_cmdbuf_node == NULL)
  3125. {
  3126. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  3127. return IRQ_HANDLED;
  3128. }
  3129. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  3130. if ((((cmdbuf_obj->cmdbuf_busAddress - base_ddr_addr) <= exe_cmdbuf_busAddress) && (((cmdbuf_obj->cmdbuf_busAddress - base_ddr_addr + cmdbuf_obj->cmdbuf_size) > exe_cmdbuf_busAddress))) && (cmdbuf_obj->cmdbuf_run_done == 0))
  3131. break;
  3132. new_cmdbuf_node = new_cmdbuf_node->next;
  3133. }
  3134. }
  3135. base_cmdbuf_node = new_cmdbuf_node;
  3136. new_cmdbuf_node = new_cmdbuf_node->previous;
  3137. // this cmdbuf and cmdbufs prior to itself, run_done = 1
  3138. while (1)
  3139. {
  3140. if (new_cmdbuf_node == NULL)
  3141. break;
  3142. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  3143. if (cmdbuf_obj->cmdbuf_run_done == 0)
  3144. {
  3145. cmdbuf_obj->cmdbuf_run_done = 1;
  3146. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  3147. //queue_vcmd_wakeup(&wait_queue_vcmd[cmdbuf_obj->cmdbuf_id]);
  3148. cmdbuf_processed_num++;
  3149. }
  3150. else
  3151. break;
  3152. new_cmdbuf_node = new_cmdbuf_node->previous;
  3153. }
  3154. vcmd_delink_cmdbuf(dev, base_cmdbuf_node);
  3155. vcmd_link_cmdbuf(dev, base_cmdbuf_node);
  3156. if (dev->sw_cmdbuf_rdy_num != 0)
  3157. {
  3158. //reset
  3159. vcmd_reset_current_asic(dev);
  3160. //restart new command
  3161. vcmd_start(dev, base_cmdbuf_node);
  3162. }
  3163. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  3164. #if PROCESS_MANAGER
  3165. if (cmdbuf_processed_num)
  3166. wake_up_interruptible_all(dev->wait_queue);
  3167. #endif
  3168. (*handled)++;
  3169. //wake_up_interruptible_all(&mc_wait_queue);
  3170. queue_vcmd_wakeup(&mc_wait_queue);
  3171. return IRQ_HANDLED;
  3172. }
  3173. if (vcmd_get_register_mirror_value(dev->reg_mirror, HWIF_VCMD_IRQ_CMDERR))
  3174. {
  3175. //command error,don't need to reset
  3176. new_cmdbuf_node = dev->list_manager.head;
  3177. dev->working_state = WORKING_STATE_IDLE;
  3178. if (dev->hw_version_id > HW_ID_1_0_C)
  3179. {
  3180. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  3181. if (new_cmdbuf_node == NULL)
  3182. {
  3183. printk(KERN_ERR "hantrovcmd_isr error cmdbuf_id !!\n");
  3184. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  3185. return IRQ_HANDLED;
  3186. }
  3187. }
  3188. else
  3189. {
  3190. exe_cmdbuf_busAddress = VCMDGetAddrRegisterValue((const void *)dev->hwregs, dev->reg_mirror, HWIF_VCMD_EXECUTING_CMD_ADDR);
  3191. //find the cmderror cmdbuf
  3192. while (1)
  3193. {
  3194. if (new_cmdbuf_node == NULL)
  3195. {
  3196. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  3197. return IRQ_HANDLED;
  3198. }
  3199. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  3200. if ((((cmdbuf_obj->cmdbuf_busAddress - base_ddr_addr) <= exe_cmdbuf_busAddress) && (((cmdbuf_obj->cmdbuf_busAddress - base_ddr_addr + cmdbuf_obj->cmdbuf_size) > exe_cmdbuf_busAddress))) && (cmdbuf_obj->cmdbuf_run_done == 0))
  3201. break;
  3202. new_cmdbuf_node = new_cmdbuf_node->next;
  3203. }
  3204. }
  3205. base_cmdbuf_node = new_cmdbuf_node;
  3206. // this cmdbuf and cmdbufs prior to itself, run_done = 1
  3207. while (1)
  3208. {
  3209. if (new_cmdbuf_node == NULL)
  3210. break;
  3211. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  3212. if (cmdbuf_obj->cmdbuf_run_done == 0)
  3213. {
  3214. cmdbuf_obj->cmdbuf_run_done = 1;
  3215. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  3216. //queue_vcmd_wakeup(&wait_queue_vcmd[cmdbuf_obj->cmdbuf_id]);
  3217. cmdbuf_processed_num++;
  3218. }
  3219. else
  3220. break;
  3221. new_cmdbuf_node = new_cmdbuf_node->previous;
  3222. }
  3223. new_cmdbuf_node = base_cmdbuf_node;
  3224. if (new_cmdbuf_node != NULL)
  3225. {
  3226. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  3227. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_CMDERR; //cmderr
  3228. }
  3229. base_cmdbuf_node = base_cmdbuf_node->next;
  3230. vcmd_delink_cmdbuf(dev, base_cmdbuf_node);
  3231. vcmd_link_cmdbuf(dev, base_cmdbuf_node);
  3232. if (dev->sw_cmdbuf_rdy_num != 0)
  3233. {
  3234. //restart new command
  3235. vcmd_start(dev, base_cmdbuf_node);
  3236. }
  3237. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  3238. #if PROCESS_MANAGER
  3239. if (cmdbuf_processed_num)
  3240. wake_up_interruptible_all(dev->wait_queue);
  3241. #endif
  3242. (*handled)++;
  3243. //wake_up_interruptible_all(&mc_wait_queue);
  3244. queue_vcmd_wakeup(&mc_wait_queue);
  3245. return IRQ_HANDLED;
  3246. }
  3247. if (vcmd_get_register_mirror_value(dev->reg_mirror, HWIF_VCMD_IRQ_ENDCMD))
  3248. {
  3249. //end command interrupt
  3250. new_cmdbuf_node = dev->list_manager.head;
  3251. dev->working_state = WORKING_STATE_IDLE;
  3252. if (dev->hw_version_id > HW_ID_1_0_C)
  3253. {
  3254. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  3255. if (new_cmdbuf_node == NULL)
  3256. {
  3257. printk(KERN_ERR "hantrovcmd_isr error cmdbuf_id !!\n");
  3258. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  3259. return IRQ_HANDLED;
  3260. }
  3261. }
  3262. else
  3263. {
  3264. //find the end cmdbuf
  3265. while (1)
  3266. {
  3267. if (new_cmdbuf_node == NULL)
  3268. {
  3269. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  3270. return IRQ_HANDLED;
  3271. }
  3272. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  3273. if ((cmdbuf_obj->has_end_cmdbuf == 1) && (cmdbuf_obj->cmdbuf_run_done == 0))
  3274. break;
  3275. new_cmdbuf_node = new_cmdbuf_node->next;
  3276. }
  3277. }
  3278. base_cmdbuf_node = new_cmdbuf_node;
  3279. // this cmdbuf and cmdbufs prior to itself, run_done = 1
  3280. while (1)
  3281. {
  3282. if (new_cmdbuf_node == NULL)
  3283. break;
  3284. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  3285. if (cmdbuf_obj->cmdbuf_run_done == 0)
  3286. {
  3287. cmdbuf_obj->cmdbuf_run_done = 1;
  3288. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  3289. //queue_vcmd_wakeup(&wait_queue_vcmd[cmdbuf_obj->cmdbuf_id]);
  3290. cmdbuf_processed_num++;
  3291. }
  3292. else
  3293. break;
  3294. new_cmdbuf_node = new_cmdbuf_node->previous;
  3295. }
  3296. base_cmdbuf_node = base_cmdbuf_node->next;
  3297. vcmd_delink_cmdbuf(dev, base_cmdbuf_node);
  3298. vcmd_link_cmdbuf(dev, base_cmdbuf_node);
  3299. if (dev->sw_cmdbuf_rdy_num != 0)
  3300. {
  3301. //restart new command
  3302. vcmd_start(dev, base_cmdbuf_node);
  3303. }
  3304. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  3305. #if PROCESS_MANAGER
  3306. if (cmdbuf_processed_num)
  3307. wake_up_interruptible_all(dev->wait_queue);
  3308. #endif
  3309. (*handled)++;
  3310. //wake_up_interruptible_all(&mc_wait_queue);
  3311. queue_vcmd_wakeup(&mc_wait_queue);
  3312. return IRQ_HANDLED;
  3313. }
  3314. if (dev->hw_version_id <= HW_ID_1_0_C)
  3315. cmdbuf_id = vcmd_get_register_mirror_value(dev->reg_mirror, HWIF_VCMD_IRQ_INTCMD);
  3316. if (cmdbuf_id)
  3317. {
  3318. if (dev->hw_version_id <= HW_ID_1_0_C)
  3319. {
  3320. if (cmdbuf_id >= TOTAL_DISCRETE_CMDBUF_NUM)
  3321. {
  3322. printk(KERN_ERR "hantrovcmd_isr error cmdbuf_id greater than the ceiling !!\n");
  3323. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  3324. return IRQ_HANDLED;
  3325. }
  3326. }
  3327. new_cmdbuf_node = global_cmdbuf_node[cmdbuf_id];
  3328. if (new_cmdbuf_node == NULL)
  3329. {
  3330. printk(KERN_ERR "hantrovcmd_isr error cmdbuf_id !!\n");
  3331. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  3332. return IRQ_HANDLED;
  3333. }
  3334. // interrupt cmdbuf and cmdbufs prior to itself, run_done = 1
  3335. while (1)
  3336. {
  3337. if (new_cmdbuf_node == NULL)
  3338. break;
  3339. cmdbuf_obj = (struct cmdbuf_obj *)new_cmdbuf_node->data;
  3340. if (cmdbuf_obj->cmdbuf_run_done == 0)
  3341. {
  3342. cmdbuf_obj->cmdbuf_run_done = 1;
  3343. cmdbuf_obj->executing_status = CMDBUF_EXE_STATUS_OK;
  3344. //queue_vcmd_wakeup(&wait_queue_vcmd[cmdbuf_obj->cmdbuf_id]);
  3345. PDEBUG("In ISR, post wait_queue_vcmd[%d]\n", cmdbuf_obj->cmdbuf_id);
  3346. cmdbuf_processed_num++;
  3347. }
  3348. else
  3349. break;
  3350. new_cmdbuf_node = new_cmdbuf_node->previous;
  3351. }
  3352. (*handled)++;
  3353. }
  3354. isr_spin_unlock_irqrestore(dev->spinlock, flags);
  3355. #if PROCESS_MANAGER
  3356. if (cmdbuf_processed_num)
  3357. wake_up_interruptible_all(dev->wait_queue);
  3358. #endif
  3359. return IRQ_HANDLED;
  3360. }
  3361. static irqreturn_t hantrovcmd_isr(void *dev_id)
  3362. {
  3363. struct hantrovcmd_dev *dev = NULL;
  3364. unsigned int handled = 0;
  3365. u32 i = 0, irq = 0, intr_val = 0, core_id = 0;
  3366. if (vcmd_init_flag)
  3367. {
  3368. ProcessingInterrupt(dev_id, &handled);
  3369. for (i = 0; i < total_vcmd_core_num; i++)
  3370. IntClearIRQStatus(vcmd_core_array[i].vcmd_irq);
  3371. }
  3372. else
  3373. {
  3374. intr_val = (u32)ioread32((void *)SYS_REG_INT_STAT/*SYS_REG_INT_VAL*/);
  3375. PDEBUG("In ISR, the interrupt value is 0x%x\n", intr_val);
  3376. irq = 0;
  3377. while (intr_val)
  3378. {
  3379. if (intr_val & 1)
  3380. {
  3381. for (i = 0; i < total_vcmd_core_num; i++)
  3382. {
  3383. if (vcmd_core_array[i].vcmd_irq != irq)
  3384. {
  3385. continue;
  3386. }
  3387. else
  3388. { //found out the trigger source cor for interrupt
  3389. /* get dev & core_id */
  3390. core_id = i;
  3391. dev = &hantrovcmd_data[core_id];
  3392. IntClearIRQStatus(irq);
  3393. /* interrupt processing */
  3394. ProcessingInterrupt(dev, &handled);
  3395. break; // have found the trigger source core, exit the for(total_vcmd_core)
  3396. }
  3397. }
  3398. }
  3399. /* next irq */
  3400. intr_val >>= 1;
  3401. irq++;
  3402. }
  3403. }
  3404. if (!handled)
  3405. {
  3406. printf("IRQ received, but not hantro's!\n");
  3407. }
  3408. //wake_up_interruptible_all(&mc_wait_queue);
  3409. queue_vcmd_wakeup(&mc_wait_queue);
  3410. #if 0
  3411. static int i_lxj = 0;
  3412. printf("post %d mc_wait_queue\n", ++i_lxj);
  3413. #endif
  3414. return IRQ_HANDLED;
  3415. }
  3416. void vcmd_reset_asic(struct hantrovcmd_dev *dev)
  3417. {
  3418. int i, n;
  3419. u32 result;
  3420. for (n = 0; n < total_vcmd_core_num; n++)
  3421. {
  3422. if (dev[n].hwregs != NULL)
  3423. {
  3424. //disable interrupt at first
  3425. vcmd_write_reg((const void *)dev[n].hwregs, VCMD_REGISTER_INT_CTL_OFFSET, 0x0000);
  3426. //reset all
  3427. vcmd_write_reg((const void *)dev[n].hwregs, VCMD_REGISTER_CONTROL_OFFSET, 0x0004);
  3428. //read status register
  3429. result = vcmd_read_reg((const void *)dev[n].hwregs, VCMD_REGISTER_INT_STATUS_OFFSET);
  3430. //clean status register
  3431. vcmd_write_reg((const void *)dev[n].hwregs, VCMD_REGISTER_INT_STATUS_OFFSET, result);
  3432. for (i = VCMD_REGISTER_CONTROL_OFFSET; i < dev[n].vcmd_core_cfg.vcmd_iosize; i += 4)
  3433. {
  3434. //set all register 0
  3435. vcmd_write_reg((const void *)dev[n].hwregs, i, 0x0000);
  3436. }
  3437. //enable all interrupt
  3438. vcmd_write_reg((const void *)dev[n].hwregs, VCMD_REGISTER_INT_CTL_OFFSET, 0xffffffff);
  3439. }
  3440. }
  3441. }
  3442. static void vcmd_reset_current_asic(struct hantrovcmd_dev *dev)
  3443. {
  3444. u32 result;
  3445. if (dev->hwregs != NULL)
  3446. {
  3447. //disable interrupt at first
  3448. vcmd_write_reg((const void *)dev->hwregs, VCMD_REGISTER_INT_CTL_OFFSET, 0x0000);
  3449. //reset all
  3450. vcmd_write_reg((const void *)dev->hwregs, VCMD_REGISTER_CONTROL_OFFSET, 0x0002);
  3451. //read status register
  3452. result = vcmd_read_reg((const void *)dev->hwregs, VCMD_REGISTER_INT_STATUS_OFFSET);
  3453. //clean status register
  3454. vcmd_write_reg((const void *)dev->hwregs, VCMD_REGISTER_INT_STATUS_OFFSET, result);
  3455. }
  3456. }
  3457. /*
  3458. * the related code for xtensa interrupt interfaces
  3459. */
  3460. av_unused int RegisterIRQ(i32 irq_offset, IRQHandler isr_handler, i32 flag, const char *name, void *data)
  3461. {
  3462. //CPU interrupt handler
  3463. //_xtos_set_interrupt_handle
  3464. u32 irq_mask = 1 << irq_offset; //irq_offset -> Irq[0] is 8
  3465. u32 enabled_int = 0;
  3466. if ((xthal_get_intenable() & irq_mask) == 0)
  3467. {
  3468. /* Clear MCPU DB2 interrupt before enable */
  3469. xthal_set_intclear(irq_mask);
  3470. /* Assign Interrupt handler */
  3471. xt_set_interrupt_handler(irq_offset, (xt_handler)isr_handler, data);
  3472. xt_ints_on(irq_mask);
  3473. enabled_int = xthal_get_intenable();
  3474. PDEBUG("INTs are enabled: 0x%x\n", enabled_int);
  3475. }
  3476. return 0;
  3477. }
  3478. static void IntEnableIRQ(u32 irq_offset)
  3479. {
  3480. //sys reg interrupt enable
  3481. u32 irq_mask = 1 << irq_offset;
  3482. u32 curr_en;
  3483. *((volatile uint32_t *)SYS_REG_INT_STAT) = irq_mask; // clear this irq
  3484. curr_en = ioread32((void *)SYS_REG_INT_EN) | irq_mask;
  3485. *((volatile uint32_t *)SYS_REG_INT_EN) = curr_en; // enable this irq
  3486. g_vc8000_int_enable_mask |= irq_mask;
  3487. }
  3488. av_unused void IntDisableIRQ(u32 irq_offset)
  3489. {
  3490. //sys reg interrupt disable
  3491. u32 irq_mask = 1 << irq_offset;
  3492. u32 curr_en;
  3493. *((volatile uint32_t *)SYS_REG_INT_STAT) = irq_mask; // clear this irq
  3494. curr_en = ioread32((void *)SYS_REG_INT_EN) & (~irq_mask);
  3495. *((volatile uint32_t *)SYS_REG_INT_EN) = curr_en; // disable this irq
  3496. }
  3497. static void IntClearIRQStatus(u32 irq_offset)
  3498. {
  3499. //sys reg interrupt clear
  3500. u32 irq_mask = 1 << irq_offset;
  3501. *((volatile uint32_t *)SYS_REG_INT_STAT) = irq_mask; // clear this irq
  3502. }
  3503. static inline uint32_t ReadInterruptStatus(void)
  3504. {
  3505. uint32_t interrupt;
  3506. __asm__ __volatile__("rsr %0, interrupt"
  3507. : "=a"(interrupt));
  3508. return interrupt;
  3509. }
  3510. //For debug
  3511. av_unused u32 IntGetIRQStatus(u32 irq_offset)
  3512. {
  3513. uint32_t ret_val;
  3514. //ReadInterruptStatus
  3515. ret_val = ReadInterruptStatus();
  3516. //mask other interrupts ?
  3517. ret_val &= (1 << irq_offset);
  3518. // return 1 if requested interrupt is set
  3519. if (ret_val)
  3520. ret_val = 1;
  3521. return 0;
  3522. }
  3523. void queue_vcmd_init(void *semaphore)
  3524. {
  3525. #ifdef VCMD_POLLING
  3526. sem_t *sem_temp = (sem_t *)semaphore;
  3527. sem_init(sem_temp, 0, 0);
  3528. #else
  3529. SemaphoreHandle_t *sem_temp = (SemaphoreHandle_t *)semaphore;
  3530. *sem_temp = xSemaphoreCreateBinary(); //xSemaphoreCreateCounting(0x7FFU, 0);
  3531. #endif
  3532. }
  3533. u32 queue_vcmd_wait(void *semaphore)
  3534. {
  3535. #ifdef VCMD_POLLING
  3536. sem_t *sem_temp = (sem_t *)semaphore;
  3537. sem_wait(sem_temp);
  3538. #else
  3539. SemaphoreHandle_t *sem_temp = (SemaphoreHandle_t *)semaphore;
  3540. xSemaphoreTake(*sem_temp, portMAX_DELAY);
  3541. #endif
  3542. return 0;
  3543. }
  3544. void queue_vcmd_wakeup(void *semaphore)
  3545. {
  3546. //use sched_yield to free the cpu cycles of hantrovcmd_isr functions
  3547. //u32 wake_up_start = xthal_get_ccount();
  3548. #ifdef VCMD_POLLING
  3549. sem_t * sem_temp = (sem_t *) semaphore;
  3550. sem_post(sem_temp);
  3551. #else
  3552. SemaphoreHandle_t * sem_temp = (SemaphoreHandle_t *)semaphore;
  3553. if(vcmd_init_flag)
  3554. xSemaphoreGive(*sem_temp);
  3555. else
  3556. xSemaphoreGiveFromISR(*sem_temp, NULL);
  3557. #endif
  3558. //u32 wake_up_end = xthal_get_ccount();
  3559. //printf("sem post cpu cycle is %d\n", wake_up_end-wake_up_start);
  3560. }