hantro_dec_freertos.c 61 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2014 - 2021 VERISILICON
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (C) 2014 - 2021 VERISILICON
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program; if not, write to the Free Software Foundation,
  43. * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  44. *
  45. *****************************************************************************
  46. *
  47. * Note: This software is released under dual MIT and GPL licenses. A
  48. * recipient may use this file under the terms of either the MIT license or
  49. * GPL License. If you wish to use only one license not the other, you can
  50. * indicate your decision by deleting one of the above license notices in your
  51. * version of this file.
  52. *
  53. *****************************************************************************/
  54. #include "hantrodec.h"
  55. #include "dwl_defs.h"
  56. #include "subsys.h"
  57. #include "io_tools.h"
  58. #include "osal.h"
  59. #include "xtensa_api.h"
  60. //#include "../src/libxmp/xmp-library.h" //For atomic operations
  61. #include <xtensa/xtruntime.h> //interrupt for xtensa
  62. #include <stdint.h>
  63. #include <string.h>
  64. #undef PDEBUG
  65. #ifdef HANTRODEC_DEBUG
  66. # ifdef __KERNEL__
  67. # define PDEBUG(fmt, args...) printk( KERN_INFO "hantrodec: " fmt, ## args)
  68. # else
  69. # define PDEBUG(fmt, args...) fprintf(stderr, fmt, ## args)
  70. # endif
  71. #else
  72. # define PDEBUG(fmt, ...)
  73. #endif
  74. /*-----------------------------------------------------------------------------------------
  75. ************************CPU Xtensa OS FreeRTOS PORTING LAYER*******************************
  76. ------------------------------------------------------------------------------------------*/
  77. static u32 g_vc8000_int_enable_mask = 0;
  78. //VCMD for netint
  79. #define SYS_REG_INT_TOP_BASE (0x02800000)
  80. //ENCODER
  81. #if 0
  82. #define CPU_INT_IRQ 8 /* All Encoder Modules' interrupt will be connected to CPU IRQ 8 */
  83. #define SYS_INT_MASK (0x220)
  84. #define SYS_REG_INT_VAL (SYS_REG_INT_TOP_BASE + 0x3c)
  85. #define SYS_REG_INT_STAT (SYS_REG_INT_TOP_BASE + 0x40)
  86. #define SYS_REG_INT_EN (SYS_REG_INT_TOP_BASE + 0x44)
  87. #else
  88. //DECODER
  89. #define CPU_INT_IRQ 9
  90. #define SYS_INT_MASK (0x001)
  91. #define SYS_REG_INT_VAL (SYS_REG_INT_TOP_BASE + 0x48)
  92. #define SYS_REG_INT_STAT (SYS_REG_INT_TOP_BASE + 0x4c)
  93. #define SYS_REG_INT_EN (SYS_REG_INT_TOP_BASE + 0x50)
  94. #endif
  95. /* hantro G1 regs config including dec and pp */
  96. #define HANTRO_DEC_ORG_REGS 60
  97. #define HANTRO_PP_ORG_REGS 41
  98. #define HANTRO_DEC_EXT_REGS 27
  99. #define HANTRO_PP_EXT_REGS 9
  100. //#define HANTRO_G1_DEC_TOTAL_REGS (HANTRO_DEC_ORG_REGS + HANTRO_DEC_EXT_REGS)
  101. #define HANTRO_PP_TOTAL_REGS (HANTRO_PP_ORG_REGS + HANTRO_PP_EXT_REGS)
  102. #define HANTRO_G1_DEC_REGS 155 /*G1 total regs*/
  103. //#define HANTRO_DEC_ORG_FIRST_REG 0
  104. //#define HANTRO_DEC_ORG_LAST_REG 59
  105. //#define HANTRO_DEC_EXT_FIRST_REG 119
  106. //#define HANTRO_DEC_EXT_LAST_REG 145
  107. #define HANTRO_PP_ORG_FIRST_REG 60
  108. #define HANTRO_PP_ORG_LAST_REG 100
  109. #define HANTRO_PP_EXT_FIRST_REG 146
  110. #define HANTRO_PP_EXT_LAST_REG 154
  111. /* hantro G2 reg config */
  112. #define HANTRO_G2_DEC_REGS 337 /*G2 total regs*/
  113. #define HANTRO_G2_DEC_FIRST_REG 0
  114. #define HANTRO_G2_DEC_LAST_REG HANTRO_G2_DEC_REGS-1
  115. /* hantro VC8000D reg config */
  116. #define HANTRO_VC8000D_REGS 503 /*VC8000D total regs*/
  117. #define HANTRO_VC8000D_FIRST_REG 0
  118. #define HANTRO_VC8000D_LAST_REG HANTRO_VC8000D_REGS-1
  119. /* Logic module IRQs */
  120. #define HXDEC_NO_IRQ -1
  121. #define MAX(a, b) (((a) > (b)) ? (a) : (b))
  122. #define DEC_IO_SIZE_MAX (MAX(MAX(HANTRO_G2_DEC_REGS, HANTRO_G1_DEC_REGS), HANTRO_VC8000D_REGS) * 4)
  123. /* User should modify these configuration if do porting to own platform. */
  124. /* Please guarantee the base_addr, io_size, dec_irq belong to same core. */
  125. /* Defines use kernel clk cfg or not**/
  126. //#define CLK_CFG
  127. #if 0
  128. #ifdef CLK_CFG
  129. #define CLK_ID "hantrodec_clk" /*this id should conform with platform define*/
  130. #endif
  131. #endif
  132. /* Logic module base address */
  133. #define SOCLE_LOGIC_0_BASE (0x02310000 + 0x2000)
  134. #define SOCLE_LOGIC_1_BASE -1 //(0x02350000 + 0x2000)
  135. #define SOCLE_LOGIC_2_BASE -1 //(0x02390000 + 0x2000)
  136. #define SOCLE_LOGIC_3_BASE -1 //(0x023D0000 + 0x2000)
  137. //#define VEXPRESS_LOGIC_0_BASE 0xFC010000
  138. //#define VEXPRESS_LOGIC_1_BASE 0xFC020000
  139. #define DEC_IO_SIZE_0 DEC_IO_SIZE_MAX /* bytes */
  140. #define DEC_IO_SIZE_1 DEC_IO_SIZE_MAX /* bytes */
  141. #define DEC_IO_SIZE_2 DEC_IO_SIZE_MAX /* bytes */
  142. #define DEC_IO_SIZE_3 DEC_IO_SIZE_MAX /* bytes */
  143. #define DEC_IRQ_0 9 //3
  144. #define DEC_IRQ_1 HXDEC_NO_IRQ
  145. #define IS_G1(hw_id) (((hw_id) == 0x6731)? 1 : 0)
  146. #define IS_G2(hw_id) (((hw_id) == 0x6732)? 1 : 0)
  147. #define IS_VC8000D(hw_id) (((hw_id) == 0x8001)? 1 : 0)
  148. static const int DecHwId[] = {
  149. 0x6731, /* G1 */
  150. 0x6732, /* G2 */
  151. 0x8001 /* VC8000D */
  152. };
  153. unsigned long base_port = 0;
  154. volatile unsigned char *reg = NULL;
  155. int vcmd = 0;
  156. unsigned long multicorebase[HXDEC_MAX_CORES] = {
  157. SOCLE_LOGIC_0_BASE,
  158. SOCLE_LOGIC_1_BASE,
  159. SOCLE_LOGIC_2_BASE,
  160. SOCLE_LOGIC_3_BASE
  161. };
  162. int irq[HXDEC_MAX_CORES] = {
  163. DEC_IRQ_0,
  164. -1,
  165. -1,
  166. -1
  167. };
  168. unsigned int iosize[HXDEC_MAX_CORES] = {
  169. DEC_IO_SIZE_0,
  170. DEC_IO_SIZE_1,
  171. DEC_IO_SIZE_2,
  172. DEC_IO_SIZE_3
  173. };
  174. /* Because one core may contain multi-pipeline, so multicore base may be changed */
  175. unsigned long multicorebase_actual[HXDEC_MAX_CORES];
  176. struct subsys_config vpu_subsys[MAX_SUBSYS_NUM];
  177. int elements = 4;
  178. #if 0
  179. #ifdef CLK_CFG
  180. struct clk *clk_cfg;
  181. int is_clk_on;
  182. struct timer_list timer;
  183. #endif
  184. #endif
  185. static int hantrodec_major = 0; /* dynamic allocation */
  186. /* here's all the must remember stuff */
  187. typedef struct {
  188. char *buffer;
  189. volatile unsigned int iosize[HXDEC_MAX_CORES];
  190. volatile u8 *hwregs[HXDEC_MAX_CORES];
  191. volatile int irq[HXDEC_MAX_CORES];
  192. int hw_id[HXDEC_MAX_CORES];
  193. int cores;
  194. //struct fasync_struct *async_queue_dec;
  195. //struct fasync_struct *async_queue_pp;
  196. } hantrodec_t;
  197. typedef struct {
  198. u32 cfg[HXDEC_MAX_CORES]; /* indicate the supported format */
  199. u32 cfg_backup[HXDEC_MAX_CORES]; /* back up of cfg */
  200. int its_main_core_id[HXDEC_MAX_CORES]; /* indicate if main core exist */
  201. int its_aux_core_id[HXDEC_MAX_CORES]; /* indicate if aux core exist */
  202. } core_cfg;
  203. static hantrodec_t hantrodec_data; /* dynamic allocation? */
  204. static int ReserveIO(void);
  205. static void ReleaseIO(void);
  206. static void ResetAsic(hantrodec_t * dev);
  207. #ifdef HANTRODEC_DEBUG
  208. static void dump_regs(hantrodec_t *dev);
  209. #endif
  210. /* Interrupt */
  211. /*********************request_irq, disable_irq, enable_irq need to be provided by customer*********************/
  212. static int RegisterIRQ(i32 i, IRQHandler isr, i32 flag, const char* name, void *data);
  213. static void IntEnableIRQ(u32 irq);
  214. static void IntDisableIRQ(u32 irq);
  215. static void IntClearIRQStatus(u32 irq, u32 type);
  216. static u32 IntGetIRQStatus(u32 irq);
  217. static inline uint32_t ReadInterruptStatus(void);
  218. /* IRQ handler */
  219. static irqreturn_t hantrodec_isr(void *args);
  220. static u32 dec_regs[HXDEC_MAX_CORES][DEC_IO_SIZE_MAX/4];
  221. #undef down_interruptible
  222. #undef up
  223. #define down_interruptible(a) sem_wait(a)
  224. #define up(a) sem_post(a)
  225. sem_t dec_core_sem;
  226. sem_t pp_core_sem;
  227. static int dec_irq = 0;
  228. static int pp_irq = 0;
  229. /*********************the atomic operations need to be provided by customer*********************/
  230. atomic_t irq_rx = ATOMIC_INIT(0);
  231. atomic_t irq_tx = ATOMIC_INIT(0);
  232. static int dec_owner[HXDEC_MAX_CORES];
  233. static int pp_owner[HXDEC_MAX_CORES];
  234. static int CoreHasFormat(const u32 *cfg, int core, u32 format);
  235. #if 0
  236. /* spinlock_t owner_lock = SPIN_LOCK_UNLOCKED; */
  237. DEFINE_SPINLOCK(owner_lock);
  238. DECLARE_WAIT_QUEUE_HEAD(dec_wait_queue);
  239. DECLARE_WAIT_QUEUE_HEAD(pp_wait_queue);
  240. DECLARE_WAIT_QUEUE_HEAD(hw_queue);
  241. #ifdef CLK_CFG
  242. DEFINE_SPINLOCK(clk_lock);
  243. #endif
  244. #endif
  245. pthread_mutex_t owner_lock = PTHREAD_MUTEX_INITIALIZER;
  246. sem_t dec_wait_queue;
  247. sem_t pp_wait_queue;
  248. sem_t hw_queue;
  249. #define DWL_CLIENT_TYPE_H264_DEC 1U
  250. #define DWL_CLIENT_TYPE_MPEG4_DEC 2U
  251. #define DWL_CLIENT_TYPE_JPEG_DEC 3U
  252. #define DWL_CLIENT_TYPE_PP 4U
  253. #define DWL_CLIENT_TYPE_VC1_DEC 5U
  254. #define DWL_CLIENT_TYPE_MPEG2_DEC 6U
  255. #define DWL_CLIENT_TYPE_VP6_DEC 7U
  256. #define DWL_CLIENT_TYPE_AVS_DEC 8U
  257. #define DWL_CLIENT_TYPE_RV_DEC 9U
  258. #define DWL_CLIENT_TYPE_VP8_DEC 10U
  259. #define DWL_CLIENT_TYPE_VP9_DEC 11U
  260. #define DWL_CLIENT_TYPE_HEVC_DEC 12U
  261. static core_cfg config;
  262. static void ReadCoreConfig(hantrodec_t *dev) {
  263. int c;
  264. u32 reg, tmp, mask;
  265. memset(config.cfg, 0, sizeof(config.cfg));
  266. for(c = 0; c < dev->cores; c++) {
  267. /* Decoder configuration */
  268. if (IS_G1(dev->hw_id[c])) {
  269. reg = ioread32((void*)(dev->hwregs[c] + HANTRODEC_SYNTH_CFG * 4));
  270. tmp = (reg >> DWL_H264_E) & 0x3U;
  271. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has H264\n", c);
  272. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_H264_DEC : 0;
  273. tmp = (reg >> DWL_JPEG_E) & 0x01U;
  274. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has JPEG\n", c);
  275. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_JPEG_DEC : 0;
  276. tmp = (reg >> DWL_HJPEG_E) & 0x01U;
  277. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has HJPEG\n", c);
  278. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_JPEG_DEC : 0;
  279. tmp = (reg >> DWL_MPEG4_E) & 0x3U;
  280. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has MPEG4\n", c);
  281. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_MPEG4_DEC : 0;
  282. tmp = (reg >> DWL_VC1_E) & 0x3U;
  283. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has VC1\n", c);
  284. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_VC1_DEC: 0;
  285. tmp = (reg >> DWL_MPEG2_E) & 0x01U;
  286. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has MPEG2\n", c);
  287. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_MPEG2_DEC : 0;
  288. tmp = (reg >> DWL_VP6_E) & 0x01U;
  289. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has VP6\n", c);
  290. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_VP6_DEC : 0;
  291. reg = ioread32((void*)(dev->hwregs[c] + HANTRODEC_SYNTH_CFG_2 * 4));
  292. /* VP7 and WEBP is part of VP8 */
  293. mask = (1 << DWL_VP8_E) | (1 << DWL_VP7_E) | (1 << DWL_WEBP_E);
  294. tmp = (reg & mask);
  295. if(tmp & (1 << DWL_VP8_E))
  296. printk(KERN_INFO "hantrodec: core[%d] has VP8\n", c);
  297. if(tmp & (1 << DWL_VP7_E))
  298. printk(KERN_INFO "hantrodec: core[%d] has VP7\n", c);
  299. if(tmp & (1 << DWL_WEBP_E))
  300. printk(KERN_INFO "hantrodec: core[%d] has WebP\n", c);
  301. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_VP8_DEC : 0;
  302. tmp = (reg >> DWL_AVS_E) & 0x01U;
  303. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has AVS\n", c);
  304. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_AVS_DEC: 0;
  305. tmp = (reg >> DWL_RV_E) & 0x03U;
  306. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has RV\n", c);
  307. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_RV_DEC : 0;
  308. /* Post-processor configuration */
  309. reg = ioread32((void*)(dev->hwregs[c] + HANTROPP_SYNTH_CFG * 4));
  310. tmp = (reg >> DWL_G1_PP_E) & 0x01U;
  311. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has PP\n", c);
  312. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_PP : 0;
  313. } else if((IS_G2(dev->hw_id[c]))) {
  314. reg = ioread32((void*)(dev->hwregs[c] + HANTRODEC_CFG_STAT * 4));
  315. tmp = (reg >> DWL_G2_HEVC_E) & 0x01U;
  316. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has HEVC\n", c);
  317. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_HEVC_DEC : 0;
  318. tmp = (reg >> DWL_G2_VP9_E) & 0x01U;
  319. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has VP9\n", c);
  320. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_VP9_DEC : 0;
  321. /* Post-processor configuration */
  322. reg = ioread32((void*)(dev->hwregs[c] + HANTRODECPP_SYNTH_CFG * 4));
  323. tmp = (reg >> DWL_G2_PP_E) & 0x01U;
  324. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has PP\n", c);
  325. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_PP : 0;
  326. } else if((IS_VC8000D(dev->hw_id[c])) && config.its_main_core_id[c] < 0) {
  327. reg = ioread32((void*)(dev->hwregs[c] + HANTRODEC_SYNTH_CFG * 4));
  328. tmp = (reg >> DWL_H264_E) & 0x3U;
  329. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has H264\n", c);
  330. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_H264_DEC : 0;
  331. tmp = (reg >> DWL_H264HIGH10_E) & 0x01U;
  332. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has H264HIGH10\n", c);
  333. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_H264_DEC : 0;
  334. tmp = (reg >> DWL_JPEG_E) & 0x01U;
  335. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has JPEG\n", c);
  336. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_JPEG_DEC : 0;
  337. tmp = (reg >> DWL_HJPEG_E) & 0x01U;
  338. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has HJPEG\n", c);
  339. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_JPEG_DEC : 0;
  340. tmp = (reg >> DWL_MPEG4_E) & 0x3U;
  341. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has MPEG4\n", c);
  342. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_MPEG4_DEC : 0;
  343. tmp = (reg >> DWL_VC1_E) & 0x3U;
  344. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has VC1\n", c);
  345. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_VC1_DEC: 0;
  346. tmp = (reg >> DWL_MPEG2_E) & 0x01U;
  347. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has MPEG2\n", c);
  348. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_MPEG2_DEC : 0;
  349. tmp = (reg >> DWL_VP6_E) & 0x01U;
  350. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has VP6\n", c);
  351. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_VP6_DEC : 0;
  352. reg = ioread32((void*)(dev->hwregs[c] + HANTRODEC_SYNTH_CFG_2 * 4));
  353. /* VP7 and WEBP is part of VP8 */
  354. mask = (1 << DWL_VP8_E) | (1 << DWL_VP7_E) | (1 << DWL_WEBP_E);
  355. tmp = (reg & mask);
  356. if(tmp & (1 << DWL_VP8_E))
  357. printk(KERN_INFO "hantrodec: core[%d] has VP8\n", c);
  358. if(tmp & (1 << DWL_VP7_E))
  359. printk(KERN_INFO "hantrodec: core[%d] has VP7\n", c);
  360. if(tmp & (1 << DWL_WEBP_E))
  361. printk(KERN_INFO "hantrodec: core[%d] has WebP\n", c);
  362. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_VP8_DEC : 0;
  363. tmp = (reg >> DWL_AVS_E) & 0x01U;
  364. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has AVS\n", c);
  365. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_AVS_DEC: 0;
  366. tmp = (reg >> DWL_RV_E) & 0x03U;
  367. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has RV\n", c);
  368. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_RV_DEC : 0;
  369. reg = ioread32((void*)(dev->hwregs[c] + HANTRODEC_SYNTH_CFG_3 * 4));
  370. tmp = (reg >> DWL_HEVC_E) & 0x07U;
  371. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has HEVC\n", c);
  372. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_HEVC_DEC : 0;
  373. tmp = (reg >> DWL_VP9_E) & 0x07U;
  374. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has VP9\n", c);
  375. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_VP9_DEC : 0;
  376. /* Post-processor configuration */
  377. reg = ioread32((void*)(dev->hwregs[c] + HANTRODECPP_CFG_STAT * 4));
  378. tmp = (reg >> DWL_PP_E) & 0x01U;
  379. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has PP\n", c);
  380. config.cfg[c] |= tmp ? 1 << DWL_CLIENT_TYPE_PP : 0;
  381. if (config.its_aux_core_id[c] >= 0) {
  382. /* set main_core_id and aux_core_id */
  383. reg = ioread32((void*)(dev->hwregs[c] + HANTRODEC_SYNTH_CFG_2 * 4));
  384. tmp = (reg >> DWL_H264_PIPELINE_E) & 0x01U;
  385. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has pipeline H264\n", c);
  386. config.cfg[config.its_aux_core_id[c]] |= tmp ? 1 << DWL_CLIENT_TYPE_H264_DEC : 0;
  387. tmp = (reg >> DWL_JPEG_PIPELINE_E) & 0x01U;
  388. if(tmp) printk(KERN_INFO "hantrodec: core[%d] has pipeline JPEG\n", c);
  389. config.cfg[config.its_aux_core_id[c]] |= tmp ? 1 << DWL_CLIENT_TYPE_JPEG_DEC : 0;
  390. }
  391. }
  392. }
  393. memcpy(config.cfg_backup, config.cfg, sizeof(config.cfg));
  394. }
  395. static int CoreHasFormat(const u32 *cfg, int core, u32 format) {
  396. return (cfg[core] & (1 << format)) ? 1 : 0;
  397. }
  398. int GetDecCore(long core, hantrodec_t *dev, int filp, unsigned long format) {
  399. int success = 0;
  400. unsigned long flags;
  401. spin_lock_irqsave(&owner_lock, flags);
  402. if(CoreHasFormat(config.cfg, core, format) && dec_owner[core] == 0 /*&& config.its_main_core_id[core] >= 0*/) {
  403. dec_owner[core] = filp;
  404. success = 1;
  405. /* If one main core takes one format which doesn't supported by aux core, set aux core's cfg to none video format support */
  406. if (config.its_aux_core_id[core] >= 0 &&
  407. !CoreHasFormat(config.cfg, config.its_aux_core_id[core], format)) {
  408. config.cfg[config.its_aux_core_id[core]] = 0;
  409. }
  410. /* If one aux core takes one format, set main core's cfg to aux core supported video format */
  411. else if (config.its_main_core_id[core] >= 0) {
  412. config.cfg[config.its_main_core_id[core]] = config.cfg[core];
  413. }
  414. }
  415. spin_unlock_irqrestore(&owner_lock, flags);
  416. return success;
  417. }
  418. int GetDecCoreAny(long *core, hantrodec_t *dev, int filp,
  419. unsigned long format) {
  420. int success = 0;
  421. long c;
  422. *core = -1;
  423. for(c = 0; c < dev->cores; c++) {
  424. /* a free core that has format */
  425. /* xuanji: simplely impto get core for single core, exists issue */
  426. if(GetDecCore(c, dev, filp, format)) {
  427. success = 1;
  428. *core = c;
  429. break;
  430. }
  431. }
  432. return success;
  433. }
  434. int GetDecCoreID(hantrodec_t *dev, int filp,
  435. unsigned long format) {
  436. long c;
  437. unsigned long flags;
  438. int core_id = -1;
  439. for(c = 0; c < dev->cores; c++) {
  440. /* a core that has format */
  441. spin_lock_irqsave(&owner_lock, flags);
  442. if(CoreHasFormat(config.cfg, c, format)) {
  443. core_id = c;
  444. spin_unlock_irqrestore(&owner_lock, flags);
  445. break;
  446. }
  447. spin_unlock_irqrestore(&owner_lock, flags);
  448. }
  449. return core_id;
  450. }
  451. #if 0
  452. static int hantrodec_choose_core(int is_g1) {
  453. volatile unsigned char *reg = NULL;
  454. unsigned int blk_base = 0x38320000;
  455. PDEBUG("hantrodec_choose_core\n");
  456. if (!request_mem_region(blk_base, 0x1000, "blk_ctl")) {
  457. printk(KERN_INFO "blk_ctl: failed to reserve HW regs\n");
  458. return -EBUSY;
  459. }
  460. reg = (volatile u8 *) ioremap_nocache(blk_base, 0x1000);
  461. if (reg == NULL ) {
  462. printk(KERN_INFO "blk_ctl: failed to ioremap HW regs\n");
  463. if (reg)
  464. iounmap((void *)reg);
  465. release_mem_region(blk_base, 0x1000);
  466. return -EBUSY;
  467. }
  468. // G1 use, set to 1; G2 use, set to 0, choose the one you are using
  469. if (is_g1)
  470. iowrite32(0x1, (void*)(reg + 0x14)); // VPUMIX only use G1, user should modify the reg according to platform design
  471. else
  472. iowrite32(0x0, (void*)(reg + 0x14)); // VPUMIX only use G2, user should modify the reg according to platform design
  473. if (reg)
  474. iounmap((void *)reg);
  475. release_mem_region(blk_base, 0x1000);
  476. PDEBUG("hantrodec_choose_core OK!\n");
  477. return 0;
  478. }
  479. #endif
  480. long ReserveDecoder(hantrodec_t *dev, int filp, unsigned long format) {
  481. long core = -1;
  482. /* reserve a core */
  483. if (down_interruptible(&dec_core_sem))
  484. return -ERESTARTSYS;
  485. /* lock a core that has specific format*/
  486. if(wait_event_interruptible(hw_queue,GetDecCoreAny(&core, dev, filp, format) != 0 ))
  487. return -ERESTARTSYS;
  488. /* xuanji: simplely imp to get core for single core, exists issue */
  489. GetDecCoreAny(&core, dev, filp, format);
  490. #if 0
  491. if(IS_G1(dev->hw_id[core])) {
  492. if (0 == hantrodec_choose_core(1))
  493. printk("G1 is reserved\n");
  494. else
  495. return -1;
  496. } else {
  497. if (0 == hantrodec_choose_core(0))
  498. printk("G2 is reserved\n");
  499. else
  500. return -1;
  501. }
  502. #endif
  503. return core;
  504. }
  505. void ReleaseDecoder(hantrodec_t *dev, long core) {
  506. u32 status;
  507. unsigned long flags;
  508. status = ioread32((void*)(dev->hwregs[core] + HANTRODEC_IRQ_STAT_DEC_OFF));
  509. /* make sure HW is disabled */
  510. if(status & HANTRODEC_DEC_E) {
  511. printk(KERN_INFO "hantrodec: DEC[%li] still enabled -> reset\n", core);
  512. /* abort decoder */
  513. status |= HANTRODEC_DEC_ABORT | HANTRODEC_DEC_IRQ_DISABLE;
  514. iowrite32(status, (void*)(dev->hwregs[core] + HANTRODEC_IRQ_STAT_DEC_OFF));
  515. }
  516. spin_lock_irqsave(&owner_lock, flags);
  517. /* If aux core released, revert main core's config back */
  518. if (config.its_main_core_id[core] >= 0) {
  519. config.cfg[config.its_main_core_id[core]] = config.cfg_backup[config.its_main_core_id[core]];
  520. }
  521. /* If main core released, revert aux core's config back */
  522. if (config.its_aux_core_id[core] >= 0) {
  523. config.cfg[config.its_aux_core_id[core]] = config.cfg_backup[config.its_aux_core_id[core]];
  524. }
  525. dec_owner[core] = 0;
  526. spin_unlock_irqrestore(&owner_lock, flags);
  527. up(&dec_core_sem);
  528. wake_up_interruptible_all(&hw_queue);
  529. }
  530. long ReservePostProcessor(hantrodec_t *dev, int filp) {
  531. unsigned long flags;
  532. long core = 0;
  533. /* single core PP only */
  534. if (down_interruptible(&pp_core_sem))
  535. return -ERESTARTSYS;
  536. spin_lock_irqsave(&owner_lock, flags);
  537. pp_owner[core] = filp;
  538. spin_unlock_irqrestore(&owner_lock, flags);
  539. return core;
  540. }
  541. void ReleasePostProcessor(hantrodec_t *dev, long core) {
  542. unsigned long flags;
  543. u32 status = ioread32((void*)(dev->hwregs[core] + HANTRO_IRQ_STAT_PP_OFF));
  544. /* make sure HW is disabled */
  545. if(status & HANTRO_PP_E) {
  546. printk(KERN_INFO "hantrodec: PP[%li] still enabled -> reset\n", core);
  547. /* disable IRQ */
  548. status |= HANTRO_PP_IRQ_DISABLE;
  549. /* disable postprocessor */
  550. status &= (~HANTRO_PP_E);
  551. iowrite32(0x10, (void*)(dev->hwregs[core] + HANTRO_IRQ_STAT_PP_OFF));
  552. }
  553. spin_lock_irqsave(&owner_lock, flags);
  554. pp_owner[core] = 0;
  555. spin_unlock_irqrestore(&owner_lock, flags);
  556. up(&pp_core_sem);
  557. }
  558. long ReserveDecPp(hantrodec_t *dev, int filp, unsigned long format) {
  559. /* reserve core 0, DEC+PP for pipeline */
  560. unsigned long flags;
  561. long core = 0;
  562. /* check that core has the requested dec format */
  563. if(!CoreHasFormat(config.cfg, core, format))
  564. return -EFAULT;
  565. /* check that core has PP */
  566. if(!CoreHasFormat(config.cfg, core, DWL_CLIENT_TYPE_PP))
  567. return -EFAULT;
  568. /* reserve a core */
  569. if (down_interruptible(&dec_core_sem))
  570. return -ERESTARTSYS;
  571. /* wait until the core is available */
  572. if(wait_event_interruptible(hw_queue, GetDecCore(core, dev, filp, format) != 0)) {
  573. up(&dec_core_sem);
  574. return -ERESTARTSYS;
  575. }
  576. /* xuanji: simplely imp to get core for single core, exists issue */
  577. GetDecCore(core, dev, filp, format);
  578. if (down_interruptible(&pp_core_sem)) {
  579. ReleaseDecoder(dev, core);
  580. return -ERESTARTSYS;
  581. }
  582. spin_lock_irqsave(&owner_lock, flags);
  583. pp_owner[core] = filp;
  584. spin_unlock_irqrestore(&owner_lock, flags);
  585. return core;
  586. }
  587. long DecFlushRegs(hantrodec_t *dev, struct core_desc *core) {
  588. long ret = 0, i;
  589. u32 id = core->id;
  590. #if 1
  591. ret = copy_from_user(dec_regs[id], core->regs, HANTRO_VC8000D_REGS*4);
  592. if (ret) {
  593. PDEBUG("Hantrodec copy_from_user failed, returned %li\n", ret);
  594. return -EFAULT;
  595. }
  596. /* write all regs but the status reg[1] to hardware */
  597. iowrite32(0x0, (void*)(dev->hwregs[id] + 4));
  598. for(i = 2; i <= HANTRO_VC8000D_LAST_REG; i++) {
  599. iowrite32(dec_regs[id][i], (void*)(dev->hwregs[id] + i*4));
  600. }
  601. #else
  602. if (IS_G1(dev->hw_id[id])) {
  603. /* copy original dec regs to kernal space*/
  604. ret = copy_from_user(dec_regs[id], core->regs, HANTRO_DEC_ORG_REGS*4);
  605. if (ret) {
  606. PDEBUG("copy_from_user failed, returned %li\n", ret);
  607. return -EFAULT;
  608. }
  609. #ifdef USE_64BIT_ENV
  610. /* copy extended dec regs to kernal space*/
  611. ret = copy_from_user(dec_regs[id] + HANTRO_DEC_EXT_FIRST_REG,
  612. core->regs + HANTRO_DEC_EXT_FIRST_REG,
  613. HANTRO_DEC_EXT_REGS*4);
  614. #endif
  615. if (ret) {
  616. PDEBUG("copy_from_user failed, returned %li\n", ret);
  617. return -EFAULT;
  618. }
  619. /* write dec regs but the status reg[1] to hardware */
  620. /* both original and extended regs need to be written */
  621. for(i = 2; i <= HANTRO_DEC_ORG_LAST_REG; i++) {
  622. iowrite32(dec_regs[id][i], dev->hwregs[id] + i*4);
  623. }
  624. #ifdef USE_64BIT_ENV
  625. for(i = HANTRO_DEC_EXT_FIRST_REG; i <= HANTRO_DEC_EXT_LAST_REG; i++)
  626. iowrite32(dec_regs[id][i], dev->hwregs[id] + i*4);
  627. #endif
  628. } else {
  629. ret = copy_from_user(dec_regs[id], core->regs, HANTRO_G2_DEC_REGS*4);
  630. if (ret) {
  631. PDEBUG("copy_from_user failed, returned %li\n", ret);
  632. return -EFAULT;
  633. }
  634. /* write all regs but the status reg[1] to hardware */
  635. for(i = 2; i <= HANTRO_G2_DEC_LAST_REG; i++) {
  636. #if 0
  637. if(i==2)
  638. //dec_regs[id][i] = 0x78777777;
  639. //dec_regs[id][i] = 0x78778787;
  640. //c_regs[id][i] = 0x78888888; //64bit
  641. {
  642. printk("reg2=%08x\n",dec_regs[id][i]);
  643. //dec_regs[id][i] = 0xF0F00000;//128bit 0xF0F0F000
  644. }
  645. //dec_regs[id][i] = 0xF0F0000F;//128bit 0xF0F00000 for big endian
  646. if(i==58) {
  647. printk("reg58=%08x\n",dec_regs[id][i]);
  648. //dec_regs[id][i]= 0x210;//128bit
  649. //dec_regs[id][i]= 0x110;//64bit
  650. }
  651. if(i==3) {
  652. printk("reg3=%08x\n",dec_regs[id][i]);
  653. //dec_regs[id][i] |= 0x00F00000;//128bit
  654. //dec_regs[id][i]= 0x110;//64bit
  655. }
  656. #endif
  657. iowrite32(dec_regs[id][i], dev->hwregs[id] + i*4);
  658. }
  659. }
  660. #endif
  661. /* write the status register, which may start the decoder */
  662. iowrite32(dec_regs[id][1], (void*)(dev->hwregs[id] + 4));
  663. PDEBUG("Hantrodec flushed registers on core %d\n", id);
  664. return 0;
  665. }
  666. long DecWriteRegs(hantrodec_t *dev, struct core_desc *core)
  667. {
  668. long ret = 0, i;
  669. u32 id = core->id;
  670. i = core->reg_id;
  671. ret = copy_from_user(dec_regs[id] + core->reg_id, core->regs + core->reg_id, 4);
  672. if (ret) {
  673. PDEBUG("Hantrodec copy_from_user failed, returned %li\n", ret);
  674. return -EFAULT;
  675. }
  676. iowrite32(dec_regs[id][i], (void*)(dev->hwregs[id] + i*4));
  677. return 0;
  678. }
  679. long DecReadRegs(hantrodec_t *dev, struct core_desc *core)
  680. {
  681. long ret, i;
  682. u32 id = core->id;
  683. i = core->reg_id;
  684. /* user has to know exactly what they are asking for */
  685. //if(core->size != (HANTRO_VC8000D_REGS * 4))
  686. // return -EFAULT;
  687. /* read specific registers from hardware */
  688. i = core->reg_id;
  689. dec_regs[id][i] = ioread32((void*)(dev->hwregs[id] + i*4));
  690. /* put registers to user space*/
  691. ret = copy_to_user(core->regs + core->reg_id, dec_regs[id] + core->reg_id, 4);
  692. if (ret) {
  693. PDEBUG("Hantrodec copy_to_user failed, returned %li\n", ret);
  694. return -EFAULT;
  695. }
  696. return 0;
  697. }
  698. long DecRefreshRegs(hantrodec_t *dev, struct core_desc *core) {
  699. long ret, i;
  700. u32 id = core->id;
  701. #if 1
  702. //for(i = 0; i <= HANTRO_DEC_ORG_LAST_REG; i++) {
  703. for(i = 0; i <= HANTRO_VC8000D_LAST_REG; i++) {
  704. dec_regs[id][i] = ioread32((void*)(dev->hwregs[id] + i*4));
  705. }
  706. //ret = copy_to_user(core->regs, dec_regs[id], HANTRO_DEC_ORG_REGS*4);
  707. ret = copy_to_user(core->regs, dec_regs[id], HANTRO_G2_DEC_REGS*4);
  708. if (ret) {
  709. PDEBUG("Hantrodec copy_to_user failed, returned %li\n", ret);
  710. return -EFAULT;
  711. }
  712. #else
  713. if (IS_G1(dev->hw_id[id])) {
  714. #ifdef USE_64BIT_ENV
  715. /* user has to know exactly what they are asking for */
  716. if(core->size != (HANTRO_DEC_TOTAL_REGS * 4))
  717. return -EFAULT;
  718. #else
  719. /* user has to know exactly what they are asking for */
  720. //if(core->size != (HANTRO_DEC_ORG_REGS * 4))
  721. // return -EFAULT;
  722. #endif
  723. /* read all registers from hardware */
  724. /* both original and extended regs need to be read */
  725. for(i = 0; i <= HANTRO_DEC_ORG_LAST_REG; i++)
  726. dec_regs[id][i] = ioread32(dev->hwregs[id] + i*4);
  727. #ifdef USE_64BIT_ENV
  728. for(i = HANTRO_DEC_EXT_FIRST_REG; i <= HANTRO_DEC_EXT_LAST_REG; i++)
  729. dec_regs[id][i] = ioread32(dev->hwregs[id] + i*4);
  730. #endif
  731. /* put registers to user space*/
  732. /* put original registers to user space*/
  733. ret = copy_to_user(core->regs, dec_regs[id], HANTRO_DEC_ORG_REGS*4);
  734. #ifdef USE_64BIT_ENV
  735. /*put extended registers to user space*/
  736. ret = copy_to_user(core->regs + HANTRO_DEC_EXT_FIRST_REG,
  737. dec_regs[id] + HANTRO_DEC_EXT_FIRST_REG,
  738. HANTRO_DEC_EXT_REGS * 4);
  739. #endif
  740. if (ret) {
  741. PDEBUG("copy_to_user failed, returned %li\n", ret);
  742. return -EFAULT;
  743. }
  744. } else {
  745. /* user has to know exactly what they are asking for */
  746. if(core->size != (HANTRO_G2_DEC_REGS * 4))
  747. return -EFAULT;
  748. /* read all registers from hardware */
  749. for(i = 0; i <= HANTRO_G2_DEC_LAST_REG; i++)
  750. dec_regs[id][i] = ioread32(dev->hwregs[id] + i*4);
  751. /* put registers to user space*/
  752. ret = copy_to_user(core->regs, dec_regs[id], HANTRO_G2_DEC_REGS*4);
  753. if (ret) {
  754. PDEBUG("copy_to_user failed, returned %li\n", ret);
  755. return -EFAULT;
  756. }
  757. }
  758. #endif
  759. return 0;
  760. }
  761. static int CheckDecIrq(hantrodec_t *dev, int id) {
  762. unsigned long flags;
  763. int rdy = 0;
  764. const u32 irq_mask = (1 << id);
  765. spin_lock_irqsave(&owner_lock, flags);
  766. if(dec_irq & irq_mask) {
  767. /* reset the wait condition(s) */
  768. dec_irq &= ~irq_mask;
  769. rdy = 1;
  770. }
  771. spin_unlock_irqrestore(&owner_lock, flags);
  772. return rdy;
  773. }
  774. long WaitDecReadyAndRefreshRegs(hantrodec_t *dev, struct core_desc *core) {
  775. u32 id = core->id;
  776. long ret;
  777. PDEBUG("Hantrodec wait_event_interruptible DEC[%d]\n", id);
  778. ret = wait_event_interruptible(dec_wait_queue, CheckDecIrq(dev, id));
  779. if(ret) {
  780. PDEBUG("Hantrodec DEC[%d] wait_event_interruptible interrupted\n", id);
  781. return -ERESTARTSYS;
  782. }
  783. /* xuanji: simplely imp to get core for single core, exists issue */
  784. CheckDecIrq(dev, id);
  785. atomic_inc(&irq_tx);
  786. /* refresh registers */
  787. return DecRefreshRegs(dev, core);
  788. }
  789. long PPFlushRegs(hantrodec_t *dev, struct core_desc *core) {
  790. long ret = 0;
  791. u32 id = core->id;
  792. u32 i;
  793. /* copy original dec regs to kernal space*/
  794. ret = copy_from_user(dec_regs[id] + HANTRO_PP_ORG_FIRST_REG,
  795. core->regs + HANTRO_PP_ORG_FIRST_REG,
  796. HANTRO_PP_ORG_REGS*4);
  797. if(sizeof(addr_t) == 8) {
  798. /* copy extended dec regs to kernal space*/
  799. ret = copy_from_user(dec_regs[id] + HANTRO_PP_EXT_FIRST_REG,
  800. core->regs + HANTRO_PP_EXT_FIRST_REG,
  801. HANTRO_PP_EXT_REGS*4);
  802. }
  803. if (ret) {
  804. PDEBUG("Hantrodec copy_from_user failed, returned %li\n", ret);
  805. return -EFAULT;
  806. }
  807. /* write all regs but the status reg[1] to hardware */
  808. /* both original and extended regs need to be written */
  809. for(i = HANTRO_PP_ORG_FIRST_REG + 1; i <= HANTRO_PP_ORG_LAST_REG; i++)
  810. iowrite32(dec_regs[id][i], (void*)(dev->hwregs[id] + i*4));
  811. if(sizeof(addr_t) == 8) {
  812. for(i = HANTRO_PP_EXT_FIRST_REG; i <= HANTRO_PP_EXT_LAST_REG; i++)
  813. iowrite32(dec_regs[id][i], (void*)(dev->hwregs[id] + i*4));
  814. }
  815. /* write the stat reg, which may start the PP */
  816. iowrite32(dec_regs[id][HANTRO_PP_ORG_FIRST_REG],
  817. (void*)(dev->hwregs[id] + HANTRO_PP_ORG_FIRST_REG * 4));
  818. return 0;
  819. }
  820. long PPRefreshRegs(hantrodec_t *dev, struct core_desc *core) {
  821. long i, ret;
  822. u32 id = core->id;
  823. if(sizeof(addr_t) == 8) {
  824. /* user has to know exactly what they are asking for */
  825. if(core->size != (HANTRO_PP_TOTAL_REGS * 4))
  826. return -EFAULT;
  827. } else {
  828. /* user has to know exactly what they are asking for */
  829. if(core->size != (HANTRO_PP_ORG_REGS * 4))
  830. return -EFAULT;
  831. }
  832. /* read all registers from hardware */
  833. /* both original and extended regs need to be read */
  834. for(i = HANTRO_PP_ORG_FIRST_REG; i <= HANTRO_PP_ORG_LAST_REG; i++)
  835. dec_regs[id][i] = ioread32((void*)(dev->hwregs[id] + i*4));
  836. if(sizeof(addr_t) == 8) {
  837. for(i = HANTRO_PP_EXT_FIRST_REG; i <= HANTRO_PP_EXT_LAST_REG; i++)
  838. dec_regs[id][i] = ioread32((void*)(dev->hwregs[id] + i*4));
  839. }
  840. /* put registers to user space*/
  841. /* put original registers to user space*/
  842. ret = copy_to_user(core->regs + HANTRO_PP_ORG_FIRST_REG,
  843. dec_regs[id] + HANTRO_PP_ORG_FIRST_REG,
  844. HANTRO_PP_ORG_REGS*4);
  845. if(sizeof(addr_t) == 8) {
  846. /* put extended registers to user space*/
  847. ret = copy_to_user(core->regs + HANTRO_PP_EXT_FIRST_REG,
  848. dec_regs[id] + HANTRO_PP_EXT_FIRST_REG,
  849. HANTRO_PP_EXT_REGS * 4);
  850. }
  851. if (ret) {
  852. PDEBUG("Hantrodec copy_to_user failed, returned %li\n", ret);
  853. return -EFAULT;
  854. }
  855. return 0;
  856. }
  857. static int CheckPPIrq(hantrodec_t *dev, int id) {
  858. unsigned long flags;
  859. int rdy = 0;
  860. const u32 irq_mask = (1 << id);
  861. spin_lock_irqsave(&owner_lock, flags);
  862. if(pp_irq & irq_mask) {
  863. /* reset the wait condition(s) */
  864. pp_irq &= ~irq_mask;
  865. rdy = 1;
  866. }
  867. spin_unlock_irqrestore(&owner_lock, flags);
  868. return rdy;
  869. }
  870. long WaitPPReadyAndRefreshRegs(hantrodec_t *dev, struct core_desc *core) {
  871. u32 id = core->id;
  872. PDEBUG("Hantrodec wait_event_interruptible PP[%d]\n", id);
  873. if(wait_event_interruptible(pp_wait_queue, CheckPPIrq(dev, id))) {
  874. PDEBUG("Hantrodec PP[%d] wait_event_interruptible interrupted\n", id);
  875. return -ERESTARTSYS;
  876. }
  877. /* xuanji: simplely imp to get core for single core, exists issue */
  878. CheckPPIrq(dev, id);
  879. atomic_inc(&irq_tx);
  880. /* refresh registers */
  881. return PPRefreshRegs(dev, core);
  882. }
  883. static int CheckCoreIrq(hantrodec_t *dev, const int filp, int *id) {
  884. unsigned long flags;
  885. int rdy = 0, n = 0;
  886. do {
  887. u32 irq_mask = (1 << n);
  888. spin_lock_irqsave(&owner_lock, flags);
  889. if(dec_irq & irq_mask) {
  890. if (dec_owner[n] == filp) {
  891. /* we have an IRQ for our client */
  892. /* reset the wait condition(s) */
  893. dec_irq &= ~irq_mask;
  894. /* signal ready core no. for our client */
  895. *id = n;
  896. rdy = 1;
  897. spin_unlock_irqrestore(&owner_lock, flags);
  898. break;
  899. } else if(dec_owner[n] == 0) {
  900. /* zombie IRQ */
  901. printk(KERN_INFO "IRQ on core[%d], but no owner!!!\n", n);
  902. /* reset the wait condition(s) */
  903. dec_irq &= ~irq_mask;
  904. }
  905. }
  906. spin_unlock_irqrestore(&owner_lock, flags);
  907. n++; /* next core */
  908. } while(n < dev->cores);
  909. return rdy;
  910. }
  911. long WaitCoreReady(hantrodec_t *dev, const int filp, int *id) {
  912. PDEBUG("Hantrodec wait_event_interruptible CORE\n");
  913. if(wait_event_interruptible(dec_wait_queue, CheckCoreIrq(dev, filp, id))) {
  914. PDEBUG("Hantrodec CORE wait_event_interruptible interrupted\n");
  915. return -ERESTARTSYS;
  916. }
  917. /* xuanji: simplely imp to get core for single core, exists issue */
  918. CheckCoreIrq(dev, filp, id);
  919. atomic_inc(&irq_tx);
  920. return 0;
  921. }
  922. /*------------------------------------------------------------------------------
  923. Function name : hantrodec_ioctl
  924. Description : communication method to/from the user space
  925. Return type : long
  926. ------------------------------------------------------------------------------*/
  927. long hantrodec_ioctl(int filp, unsigned int cmd, void *arg) {
  928. int err = 0;
  929. long tmp;
  930. #if 0
  931. #ifdef CLK_CFG
  932. unsigned long flags;
  933. #endif
  934. #endif
  935. #ifdef HW_PERFORMANCE
  936. struct timeval *end_time_arg;
  937. #endif
  938. PDEBUG("Hantrodec ioctl cmd 0x%08x\n", cmd);
  939. /*
  940. * extract the type and number bitfields, and don't decode
  941. * wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok()
  942. */
  943. if (_IOC_TYPE(cmd) != HANTRODEC_IOC_MAGIC &&
  944. //_IOC_TYPE(cmd) != HANTRO_IOC_MMU &&
  945. _IOC_TYPE(cmd) != HANTRO_VCMD_IOC_MAGIC)
  946. return -ENOTTY;
  947. if ((_IOC_TYPE(cmd) == HANTRODEC_IOC_MAGIC &&
  948. _IOC_NR(cmd) > HANTRODEC_IOC_MAXNR) ||
  949. //(_IOC_TYPE(cmd) == HANTRO_IOC_MMU &&
  950. //_IOC_NR(cmd) > HANTRO_IOC_MMU_MAXNR) ||
  951. (_IOC_TYPE(cmd) == HANTRO_VCMD_IOC_MAGIC &&
  952. _IOC_NR(cmd) > HANTRO_VCMD_IOC_MAXNR))
  953. return -ENOTTY;
  954. /*
  955. * the direction is a bitmask, and VERIFY_WRITE catches R/W
  956. * transfers. `Type' is user-oriented, while
  957. * access_ok is kernel-oriented, so the concept of "read" and
  958. * "write" is reversed
  959. */
  960. if (_IOC_DIR(cmd) & _IOC_READ)
  961. err = !access_ok(VERIFY_WRITE, (void *) arg, _IOC_SIZE(cmd));
  962. else if (_IOC_DIR(cmd) & _IOC_WRITE)
  963. err = !access_ok(VERIFY_READ, (void *) arg, _IOC_SIZE(cmd));
  964. if (err)
  965. return -EFAULT;
  966. #if 0
  967. #ifdef CLK_CFG
  968. spin_lock_irqsave(&clk_lock, flags);
  969. if (clk_cfg!=NULL && !IS_ERR(clk_cfg)&&(is_clk_on==0)) {
  970. printk("Hantrodec turn on clock by user\n");
  971. if (clk_enable(clk_cfg)) {
  972. spin_unlock_irqrestore(&clk_lock, flags);
  973. return -EFAULT;
  974. } else
  975. is_clk_on=1;
  976. }
  977. spin_unlock_irqrestore(&clk_lock, flags);
  978. mod_timer(&timer, jiffies + 10*HZ); /*the interval is 10s*/
  979. #endif
  980. #endif
  981. switch (cmd) {
  982. case HANTRODEC_IOC_CLI: {
  983. __u32 id;
  984. __get_user(id, (__u32*)arg);
  985. if(id >= hantrodec_data.cores) {
  986. return -EFAULT;
  987. }
  988. disable_irq(hantrodec_data.irq[id]);
  989. break;
  990. }
  991. case HANTRODEC_IOC_STI: {
  992. __u32 id;
  993. __get_user(id, (__u32*)arg);
  994. if(id >= hantrodec_data.cores) {
  995. return -EFAULT;
  996. }
  997. enable_irq(hantrodec_data.irq[id]);
  998. break;
  999. }
  1000. case HANTRODEC_IOCGHWOFFSET: {
  1001. __u32 id;
  1002. __get_user(id, (__u32*)arg);
  1003. if(id >= hantrodec_data.cores) {
  1004. return -EFAULT;
  1005. }
  1006. __put_user(multicorebase_actual[id], (unsigned long *) arg);
  1007. break;
  1008. }
  1009. case HANTRODEC_IOCGHWIOSIZE: {
  1010. __u32 id;
  1011. __u32 io_size;
  1012. __get_user(id, (__u32*)arg);
  1013. if(id >= hantrodec_data.cores) {
  1014. return -EFAULT;
  1015. }
  1016. io_size = hantrodec_data.iosize[id];
  1017. __put_user(io_size, (u32 *) arg);
  1018. return 0;
  1019. }
  1020. case HANTRODEC_IOC_MC_OFFSETS: {
  1021. tmp = copy_to_user((unsigned long *) arg, multicorebase_actual, sizeof(multicorebase_actual));
  1022. if (err) {
  1023. PDEBUG("Hantrodec copy_to_user failed, returned %li\n", tmp);
  1024. return -EFAULT;
  1025. }
  1026. break;
  1027. }
  1028. case HANTRODEC_IOC_MC_CORES:
  1029. __put_user(hantrodec_data.cores, (unsigned int *) arg);
  1030. PDEBUG("Hantrodec hantrodec_data.cores=%d\n", hantrodec_data.cores);
  1031. break;
  1032. case HANTRODEC_IOCS_DEC_PUSH_REG: {
  1033. struct core_desc core;
  1034. uint32_t curr_int_status = 0;
  1035. /* get registers from user space*/
  1036. tmp = copy_from_user(&core, (void*)arg, sizeof(struct core_desc));
  1037. if (tmp) {
  1038. PDEBUG("Hantrodec copy_from_user failed, returned %li\n", tmp);
  1039. return -EFAULT;
  1040. }
  1041. DecFlushRegs(&hantrodec_data, &core);
  1042. curr_int_status = ReadInterruptStatus();
  1043. break;
  1044. }
  1045. case HANTRODEC_IOCS_DEC_WRITE_REG: {
  1046. struct core_desc core;
  1047. /* get registers from user space*/
  1048. tmp = copy_from_user(&core, (void*)arg, sizeof(struct core_desc));
  1049. if (tmp) {
  1050. PDEBUG("Hantrodec copy_from_user failed, returned %li\n", tmp);
  1051. return -EFAULT;
  1052. }
  1053. DecWriteRegs(&hantrodec_data, &core);
  1054. break;
  1055. }
  1056. case HANTRODEC_IOCS_PP_PUSH_REG: {
  1057. struct core_desc core;
  1058. /* get registers from user space*/
  1059. tmp = copy_from_user(&core, (void*)arg, sizeof(struct core_desc));
  1060. if (tmp) {
  1061. PDEBUG("Hantrodec copy_from_user failed, returned %li\n", tmp);
  1062. return -EFAULT;
  1063. }
  1064. PPFlushRegs(&hantrodec_data, &core);
  1065. break;
  1066. }
  1067. case HANTRODEC_IOCS_DEC_PULL_REG: {
  1068. struct core_desc core;
  1069. /* get registers from user space*/
  1070. tmp = copy_from_user(&core, (void*)arg, sizeof(struct core_desc));
  1071. if (tmp) {
  1072. PDEBUG("Hantrodec copy_from_user failed, returned %li\n", tmp);
  1073. return -EFAULT;
  1074. }
  1075. return DecRefreshRegs(&hantrodec_data, &core);
  1076. }
  1077. case HANTRODEC_IOCS_DEC_READ_REG: {
  1078. struct core_desc core;
  1079. /* get registers from user space*/
  1080. tmp = copy_from_user(&core, (void*)arg, sizeof(struct core_desc));
  1081. if (tmp) {
  1082. PDEBUG("Hantrodec copy_from_user failed, returned %li\n", tmp);
  1083. return -EFAULT;
  1084. }
  1085. return DecReadRegs(&hantrodec_data, &core);
  1086. }
  1087. case HANTRODEC_IOCS_PP_PULL_REG: {
  1088. struct core_desc core;
  1089. /* get registers from user space*/
  1090. tmp = copy_from_user(&core, (void*)arg, sizeof(struct core_desc));
  1091. if (tmp) {
  1092. PDEBUG("Hantrodec copy_from_user failed, returned %li\n", tmp);
  1093. return -EFAULT;
  1094. }
  1095. return PPRefreshRegs(&hantrodec_data, &core);
  1096. }
  1097. case HANTRODEC_IOCH_DEC_RESERVE: {
  1098. u32 format = 0;
  1099. __get_user(format, (unsigned long *)arg);
  1100. PDEBUG("Hantrodec Reserve DEC core, format = %li\n", format);
  1101. return ReserveDecoder(&hantrodec_data, filp, format);
  1102. }
  1103. case HANTRODEC_IOCT_DEC_RELEASE: {
  1104. u32 core = *(unsigned long *)arg;
  1105. if(core >= hantrodec_data.cores || dec_owner[core] != filp) {
  1106. PDEBUG("Hantrodec bogus DEC release, core = %li\n", core);
  1107. return -EFAULT;
  1108. }
  1109. PDEBUG("Hantrodec Release DEC, core = %li\n", core);
  1110. ReleaseDecoder(&hantrodec_data, core);
  1111. break;
  1112. }
  1113. case HANTRODEC_IOCQ_PP_RESERVE:
  1114. return ReservePostProcessor(&hantrodec_data, filp);
  1115. case HANTRODEC_IOCT_PP_RELEASE: {
  1116. u32 core = 0;
  1117. __get_user(core, (unsigned long *)arg);
  1118. if(core != 0 || pp_owner[core] != filp) {
  1119. PDEBUG("Hantrodec bogus PP release %li\n", core);
  1120. return -EFAULT;
  1121. }
  1122. ReleasePostProcessor(&hantrodec_data, core);
  1123. break;
  1124. }
  1125. case HANTRODEC_IOCX_DEC_WAIT: {
  1126. struct core_desc core;
  1127. /* get registers from user space */
  1128. tmp = copy_from_user(&core, (void*)arg, sizeof(struct core_desc));
  1129. if (tmp) {
  1130. PDEBUG("Hantrodec copy_from_user failed, returned %li\n", tmp);
  1131. return -EFAULT;
  1132. }
  1133. return WaitDecReadyAndRefreshRegs(&hantrodec_data, &core);
  1134. }
  1135. case HANTRODEC_IOCX_PP_WAIT: {
  1136. struct core_desc core;
  1137. /* get registers from user space */
  1138. tmp = copy_from_user(&core, (void*)arg, sizeof(struct core_desc));
  1139. if (tmp) {
  1140. PDEBUG("Hantrodec copy_from_user failed, returned %li\n", tmp);
  1141. return -EFAULT;
  1142. }
  1143. return WaitPPReadyAndRefreshRegs(&hantrodec_data, &core);
  1144. }
  1145. case HANTRODEC_IOCG_CORE_WAIT: {
  1146. int id;
  1147. uint32_t curr_int_status = 0;
  1148. curr_int_status = ReadInterruptStatus();
  1149. tmp = WaitCoreReady(&hantrodec_data, filp, &id);
  1150. __put_user(id, (int *) arg);
  1151. return tmp;
  1152. }
  1153. case HANTRODEC_IOX_ASIC_ID: {
  1154. u32 id;
  1155. __get_user(id, (u32*)arg);
  1156. if(id >= hantrodec_data.cores) {
  1157. return -EFAULT;
  1158. }
  1159. id = ioread32((void*)(hantrodec_data.hwregs[id]));
  1160. __put_user(id, (u32 *) arg);
  1161. return 0;
  1162. }
  1163. case HANTRODEC_IOCG_CORE_ID: {
  1164. u32 format = 0;
  1165. __get_user(format, (unsigned long *)arg);
  1166. PDEBUG("Hantrodec Get DEC Core_id, format = %li\n", format);
  1167. return GetDecCoreID(&hantrodec_data, filp, format);
  1168. }
  1169. case HANTRODEC_IOX_ASIC_BUILD_ID: {
  1170. u32 id, hw_id;
  1171. __get_user(id, (u32*)arg);
  1172. if(id >= hantrodec_data.cores) {
  1173. return -EFAULT;
  1174. }
  1175. hw_id = ioread32((void*)(hantrodec_data.hwregs[id]));
  1176. if (IS_G1(hw_id >> 16) || IS_G2(hw_id >> 16))
  1177. __put_user(hw_id, (u32 *) arg);
  1178. else {
  1179. hw_id = ioread32((void*)(hantrodec_data.hwregs[id] + HANTRODEC_HW_BUILD_ID_OFF));
  1180. __put_user(hw_id, (u32 *) arg);
  1181. }
  1182. return 0;
  1183. }
  1184. case HANTRODEC_DEBUG_STATUS: {
  1185. printk(KERN_INFO "hantrodec: dec_irq = 0x%08x \n", dec_irq);
  1186. printk(KERN_INFO "hantrodec: pp_irq = 0x%08x \n", pp_irq);
  1187. printk(KERN_INFO "hantrodec: IRQs received/sent2user = %d / %d \n",
  1188. atomic_read(&irq_rx), atomic_read(&irq_tx));
  1189. for (tmp = 0; tmp < hantrodec_data.cores; tmp++) {
  1190. printk(KERN_INFO "hantrodec: dec_core[%li] %s\n",
  1191. tmp, dec_owner[tmp] == NULL ? "FREE" : "RESERVED");
  1192. printk(KERN_INFO "hantrodec: pp_core[%li] %s\n",
  1193. tmp, pp_owner[tmp] == NULL ? "FREE" : "RESERVED");
  1194. }
  1195. return 0;
  1196. }
  1197. case HANTRODEC_IOX_SUBSYS: {
  1198. struct subsys_desc subsys = {0};
  1199. /* TODO(min): check all the subsys */
  1200. if (vcmd) {
  1201. subsys.subsys_vcmd_num = 1;
  1202. subsys.subsys_num = subsys.subsys_vcmd_num;
  1203. } else {
  1204. subsys.subsys_num = hantrodec_data.cores;
  1205. subsys.subsys_vcmd_num = 0;
  1206. }
  1207. copy_to_user((u32 *) arg, &subsys, sizeof(struct subsys_desc));
  1208. return 0;
  1209. }
  1210. case HANTRODEC_IOCX_POLL: {
  1211. hantrodec_isr(&hantrodec_data);
  1212. return 0;
  1213. }
  1214. default:
  1215. if (_IOC_TYPE(cmd) == HANTRO_VCMD_IOC_MAGIC) {
  1216. return (hantrovcmd_ioctl(filp, cmd, arg));
  1217. }
  1218. return -ENOTTY;
  1219. }
  1220. return 0;
  1221. }
  1222. /*------------------------------------------------------------------------------
  1223. Function name : hantrodec_open
  1224. Description : open method
  1225. Return type : int
  1226. ------------------------------------------------------------------------------*/
  1227. int hantrodec_open(int *inode, int filp) {
  1228. PDEBUG("Hantrodec dev opened\n");
  1229. if (vcmd)
  1230. hantrovcmd_open(inode, filp);
  1231. return 0;
  1232. }
  1233. /*------------------------------------------------------------------------------
  1234. Function name : hantrodec_release
  1235. Description : Release driver
  1236. Return type : int
  1237. ------------------------------------------------------------------------------*/
  1238. int hantrodec_release(int *inode, int filp) {
  1239. int n;
  1240. hantrodec_t *dev = &hantrodec_data;
  1241. PDEBUG("Hantrodec closing ...\n");
  1242. if (vcmd) {
  1243. hantrovcmd_release(inode, filp);
  1244. return 0;
  1245. }
  1246. for(n = 0; n < dev->cores; n++) {
  1247. if(dec_owner[n] == filp) {
  1248. PDEBUG("Hantrodec releasing dec core %i lock\n", n);
  1249. ReleaseDecoder(dev, n);
  1250. }
  1251. }
  1252. for(n = 0; n < 1; n++) {
  1253. if(pp_owner[n] == filp) {
  1254. PDEBUG("Hantrodec releasing pp core %i lock\n", n);
  1255. ReleasePostProcessor(dev, n);
  1256. }
  1257. }
  1258. PDEBUG("Hantrodec closed\n");
  1259. return 0;
  1260. }
  1261. #if 0
  1262. #ifdef CLK_CFG
  1263. void hantrodec_disable_clk(unsigned long value) {
  1264. unsigned long flags;
  1265. /*entering this function means decoder is idle over expiry.So disable clk*/
  1266. if (clk_cfg!=NULL && !IS_ERR(clk_cfg)) {
  1267. spin_lock_irqsave(&clk_lock, flags);
  1268. if (is_clk_on==1) {
  1269. clk_disable(clk_cfg);
  1270. is_clk_on = 0;
  1271. printk("turned off hantrodec clk\n");
  1272. }
  1273. spin_unlock_irqrestore(&clk_lock, flags);
  1274. }
  1275. }
  1276. #endif
  1277. #endif
  1278. /* VFS methods */
  1279. /*
  1280. static struct file_operations hantrodec_fops = {
  1281. .owner = THIS_MODULE,
  1282. .open = hantrodec_open,
  1283. .release = hantrodec_release,
  1284. .unlocked_ioctl = hantrodec_ioctl,
  1285. .fasync = NULL
  1286. };
  1287. */
  1288. /*------------------------------------------------------------------------------
  1289. Function name : hantrodec_init
  1290. Description : Initialize the driver
  1291. Return type : int
  1292. ------------------------------------------------------------------------------*/
  1293. int __init hantrodec_init(void) {
  1294. int result, i;
  1295. PDEBUG("Hantrodec module init\n");
  1296. CheckSubsysCoreArray(vpu_subsys, &vcmd);
  1297. if (vcmd) {
  1298. result = hantrovcmd_init();
  1299. if (result) return result;
  1300. return 0;
  1301. }
  1302. printk(KERN_INFO "hantrodec: dec/pp kernel module. \n");
  1303. /* If base_port is set, use that for single core legacy mode */
  1304. if(base_port != 0) {
  1305. multicorebase[0] = base_port;
  1306. elements = 1;
  1307. printk(KERN_INFO "hantrodec: Init single core at 0x%08lx IRQ=%i\n",
  1308. multicorebase[0], irq[0]);
  1309. } else {
  1310. printk(KERN_INFO "hantrodec: Init multi core[0] at 0x%16lx\n"
  1311. " core[1] at 0x%16lx\n"
  1312. " core[2] at 0x%16lx\n"
  1313. " core[3] at 0x%16lx\n"
  1314. " IRQ_0=%i\n"
  1315. " IRQ_1=%i\n",
  1316. multicorebase[0], multicorebase[1],
  1317. multicorebase[2], multicorebase[3],
  1318. irq[0],irq[1]);
  1319. }
  1320. hantrodec_data.cores = 0;
  1321. hantrodec_data.iosize[0] = DEC_IO_SIZE_0;
  1322. hantrodec_data.irq[0] = irq[0];
  1323. hantrodec_data.iosize[1] = DEC_IO_SIZE_1;
  1324. hantrodec_data.irq[1] = irq[1];
  1325. for(i=0; i< HXDEC_MAX_CORES; i++) {
  1326. hantrodec_data.hwregs[i] = 0;
  1327. /* If user gave less core bases that we have by default,
  1328. * invalidate default bases
  1329. */
  1330. if(elements && i>=elements) {
  1331. multicorebase[i] = -1;
  1332. }
  1333. }
  1334. //hantrodec_data.async_queue_dec = NULL;
  1335. //hantrodec_data.async_queue_pp = NULL;
  1336. result = register_chrdev(hantrodec_major, "hantrodec", &hantrodec_fops);
  1337. if(result < 0) {
  1338. printk(KERN_INFO "hantrodec: unable to get major %d\n", hantrodec_major);
  1339. goto err;
  1340. } else if(result != 0) { /* this is for dynamic major */
  1341. hantrodec_major = result;
  1342. }
  1343. #if 0
  1344. #ifdef CLK_CFG
  1345. /* first get clk instance pointer */
  1346. clk_cfg = clk_get(NULL, CLK_ID);
  1347. if (!clk_cfg||IS_ERR(clk_cfg)) {
  1348. printk("get handrodec clk failed!\n");
  1349. goto err;
  1350. }
  1351. /* prepare and enable clk */
  1352. if(clk_prepare_enable(clk_cfg)) {
  1353. printk("try to enable handrodec clk failed!\n");
  1354. goto err;
  1355. }
  1356. is_clk_on = 1;
  1357. /*init a timer to disable clk*/
  1358. init_timer(&timer);
  1359. timer.function = &hantrodec_disable_clk;
  1360. timer.expires = jiffies + 100*HZ; //the expires time is 100s
  1361. add_timer(&timer);
  1362. #endif
  1363. #endif
  1364. result = ReserveIO();
  1365. if(result < 0) {
  1366. goto err;
  1367. }
  1368. memset(dec_owner, 0, sizeof(dec_owner));
  1369. memset(pp_owner, 0, sizeof(pp_owner));
  1370. sema_init(&dec_core_sem, hantrodec_data.cores);
  1371. sema_init(&pp_core_sem, 1);
  1372. sem_init(&dec_wait_queue, 0, 0);
  1373. sem_init(&pp_wait_queue, 0, 0);
  1374. sem_init(&hw_queue, 0, hantrodec_data.cores);
  1375. /* read configuration fo all cores */
  1376. ReadCoreConfig(&hantrodec_data);
  1377. /* reset hardware */
  1378. ResetAsic(&hantrodec_data);
  1379. /* register irq for each core */
  1380. if(irq[0] > 0) {
  1381. result = request_irq(irq[0], hantrodec_isr, IRQF_SHARED, "hantrodec", (void *) &hantrodec_data);
  1382. if(result != 0) {
  1383. if(result == -EINVAL) {
  1384. printk(KERN_ERR "hantrodec: Bad irq number or handler\n");
  1385. } else if(result == -EBUSY) {
  1386. printk(KERN_ERR "hantrodec: IRQ <%d> busy, change your config\n",
  1387. hantrodec_data.irq[0]);
  1388. }
  1389. ReleaseIO();
  1390. goto err;
  1391. }
  1392. } else {
  1393. printk(KERN_INFO "hantrodec: IRQ not in use!\n");
  1394. }
  1395. if(irq[1] > 0) {
  1396. result = request_irq(irq[1], hantrodec_isr,
  1397. //#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18))
  1398. // SA_INTERRUPT | SA_SHIRQ,
  1399. //#else
  1400. IRQF_SHARED,
  1401. //#endif
  1402. "hantrodec", (void *) &hantrodec_data);
  1403. if(result != 0) {
  1404. if(result == -EINVAL) {
  1405. printk(KERN_ERR "hantrodec: Bad irq number or handler\n");
  1406. } else if(result == -EBUSY) {
  1407. printk(KERN_ERR "hantrodec: IRQ <%d> busy, change your config\n",
  1408. hantrodec_data.irq[1]);
  1409. }
  1410. ReleaseIO();
  1411. goto err;
  1412. }
  1413. } else {
  1414. printk(KERN_INFO "hantrodec: IRQ not in use!\n");
  1415. }
  1416. printk(KERN_INFO "hantrodec: module inserted. Major = %d\n", hantrodec_major);
  1417. return 0;
  1418. err:
  1419. ReleaseIO();
  1420. printk(KERN_INFO "hantrodec: module not inserted\n");
  1421. unregister_chrdev(hantrodec_major, "hantrodec");
  1422. return result;
  1423. }
  1424. /*------------------------------------------------------------------------------
  1425. Function name : hantrodec_cleanup
  1426. Description : clean up
  1427. Return type : int
  1428. ------------------------------------------------------------------------------*/
  1429. void __exit hantrodec_cleanup(void) {
  1430. hantrodec_t *dev = &hantrodec_data;
  1431. int n = 0;
  1432. /* reset hardware */
  1433. ResetAsic(dev);
  1434. /* free the IRQ */
  1435. for (n = 0; n < dev->cores; n++) {
  1436. if(dev->irq[n] != -1) {
  1437. free_irq(dev->irq[n], (void *) dev);
  1438. }
  1439. }
  1440. ReleaseIO();
  1441. #if 0
  1442. #ifdef CLK_CFG
  1443. if (clk_cfg!=NULL && !IS_ERR(clk_cfg)) {
  1444. clk_disable_unprepare(clk_cfg);
  1445. is_clk_on = 0;
  1446. printk("turned off hantrodec clk\n");
  1447. }
  1448. /*delete timer*/
  1449. del_timer(&timer);
  1450. #endif
  1451. #endif
  1452. unregister_chrdev(hantrodec_major, "hantrodec");
  1453. printk(KERN_INFO "hantrodec: module removed\n");
  1454. return;
  1455. }
  1456. /*------------------------------------------------------------------------------
  1457. Function name : CheckHwId
  1458. Return type : int
  1459. ------------------------------------------------------------------------------*/
  1460. static int CheckHwId(hantrodec_t * dev) {
  1461. long int hwid;
  1462. int i;
  1463. size_t num_hw = sizeof(DecHwId) / sizeof(*DecHwId);
  1464. int found = 0;
  1465. for (i = 0; i < dev->cores; i++) {
  1466. if (dev->hwregs[i] != NULL ) {
  1467. hwid = readl(dev->hwregs[i]);
  1468. printk(KERN_INFO "hantrodec: core %d HW ID=0x%16lx\n", i, hwid);
  1469. hwid = (hwid >> 16) & 0xFFFF; /* product version only */
  1470. while (num_hw--) {
  1471. if (hwid == DecHwId[num_hw]) {
  1472. printk(KERN_INFO "hantrodec: Supported HW found at 0x%16lx\n",
  1473. multicorebase_actual[i]);
  1474. found++;
  1475. dev->hw_id[i] = hwid;
  1476. break;
  1477. }
  1478. }
  1479. if (!found) {
  1480. printk(KERN_INFO "hantrodec: Unknown HW found at 0x%16lx\n",
  1481. multicorebase_actual[i]);
  1482. return 0;
  1483. }
  1484. found = 0;
  1485. num_hw = sizeof(DecHwId) / sizeof(*DecHwId);
  1486. }
  1487. }
  1488. return 1;
  1489. }
  1490. /*------------------------------------------------------------------------------
  1491. Function name : ReserveIO
  1492. Description : IO reserve
  1493. Return type : int
  1494. ------------------------------------------------------------------------------*/
  1495. static int ReserveIO(void) {
  1496. int i = 0;
  1497. long int hwid = 0;
  1498. u32 reg = 0;
  1499. memcpy(multicorebase_actual, multicorebase, HXDEC_MAX_CORES * sizeof(unsigned long));
  1500. memcpy((unsigned int*)(hantrodec_data.iosize), iosize, HXDEC_MAX_CORES * sizeof(unsigned int));
  1501. memcpy((unsigned int*)(hantrodec_data.irq), irq, HXDEC_MAX_CORES * sizeof(int));
  1502. for (i = 0; i < HXDEC_MAX_CORES; i++) {
  1503. if (multicorebase_actual[i] != -1) {
  1504. if (!request_mem_region(multicorebase_actual[i], hantrodec_data.iosize[i],
  1505. "hantrodec0")) {
  1506. printk(KERN_INFO "hantrodec: failed to reserve HW regs\n");
  1507. return -EBUSY;
  1508. }
  1509. hantrodec_data.hwregs[i] = (volatile u8 *) ioremap_nocache(multicorebase_actual[i],
  1510. hantrodec_data.iosize[i]);
  1511. if (hantrodec_data.hwregs[i] == NULL ) {
  1512. printk(KERN_INFO "hantrodec: failed to ioremap HW regs\n");
  1513. ReleaseIO();
  1514. return -EBUSY;
  1515. }
  1516. hantrodec_data.cores++;
  1517. config.its_main_core_id[i] = -1;
  1518. config.its_aux_core_id[i] = -1;
  1519. hwid = ((readl(hantrodec_data.hwregs[i])) >> 16) & 0xFFFF; /* product version only */
  1520. if (IS_VC8000D(hwid)) {
  1521. reg = readl(hantrodec_data.hwregs[i] + HANTRODEC_SYNTH_CFG_2_OFF);
  1522. if (((reg >> DWL_H264_PIPELINE_E) & 0x01U) || ((reg >> DWL_JPEG_PIPELINE_E) & 0x01U)) {
  1523. i++;
  1524. config.its_aux_core_id[i-1] = i;
  1525. config.its_main_core_id[i] = i-1;
  1526. config.its_aux_core_id[i] = -1;
  1527. multicorebase_actual[i] = multicorebase_actual[i-1] + 0x800;
  1528. hantrodec_data.iosize[i] = hantrodec_data.iosize[i-1];
  1529. memcpy(multicorebase_actual+i+1, multicorebase+i,
  1530. (HXDEC_MAX_CORES - i - 1) * sizeof(unsigned long));
  1531. memcpy((unsigned int*)hantrodec_data.iosize+i+1, iosize+i,
  1532. (HXDEC_MAX_CORES - i - 1) * sizeof(unsigned int));
  1533. if (!request_mem_region(multicorebase_actual[i], hantrodec_data.iosize[i],
  1534. "hantrodec0")) {
  1535. printk(KERN_INFO "hantrodec: failed to reserve HW regs\n");
  1536. return -EBUSY;
  1537. }
  1538. hantrodec_data.hwregs[i] = (volatile u8 *) ioremap_nocache(multicorebase_actual[i],
  1539. hantrodec_data.iosize[i]);
  1540. if (hantrodec_data.hwregs[i] == NULL ) {
  1541. printk(KERN_INFO "hantrodec: failed to ioremap HW regs\n");
  1542. ReleaseIO();
  1543. return -EBUSY;
  1544. }
  1545. hantrodec_data.cores++;
  1546. }
  1547. }
  1548. }
  1549. }
  1550. /* check for correct HW */
  1551. if (!CheckHwId(&hantrodec_data)) {
  1552. ReleaseIO();
  1553. return -EBUSY;
  1554. }
  1555. return 0;
  1556. }
  1557. /*------------------------------------------------------------------------------
  1558. Function name : releaseIO
  1559. Description : release
  1560. Return type : void
  1561. ------------------------------------------------------------------------------*/
  1562. static void ReleaseIO(void) {
  1563. int i = 0;
  1564. for (i = 0; i < hantrodec_data.cores; i++) {
  1565. if (hantrodec_data.hwregs[i])
  1566. iounmap((void *) hantrodec_data.hwregs[i]);
  1567. release_mem_region(multicorebase_actual[i], hantrodec_data.iosize[i]);
  1568. }
  1569. }
  1570. /*------------------------------------------------------------------------------
  1571. Function name : hantrodec_isr
  1572. Description : interrupt handler
  1573. Return type : irqreturn_t
  1574. ------------------------------------------------------------------------------*/
  1575. static irqreturn_t hantrodec_isr(void *args) {
  1576. unsigned long flags = 0;
  1577. unsigned int handled = 0;
  1578. int i = 0;
  1579. volatile u8 *hwregs = NULL;
  1580. hantrodec_t *dev = (hantrodec_t *) args;
  1581. u32 irq_status_dec = 0;
  1582. spin_lock_irqsave(&owner_lock, flags);
  1583. IntClearIRQStatus(irq[0], 0);
  1584. for(i=0; i<dev->cores; i++) {
  1585. volatile u8 *hwregs = dev->hwregs[i];
  1586. /* interrupt status register read */
  1587. irq_status_dec = ioread32((void*)(hwregs + HANTRODEC_IRQ_STAT_DEC_OFF));
  1588. if(irq_status_dec & HANTRODEC_DEC_IRQ) {
  1589. /* clear dec IRQ */
  1590. irq_status_dec &= (~HANTRODEC_DEC_IRQ);
  1591. iowrite32(irq_status_dec, (void*)(hwregs + HANTRODEC_IRQ_STAT_DEC_OFF));
  1592. PDEBUG("Hantrodec decoder IRQ received! core %d\n", i);
  1593. atomic_inc(&irq_rx);
  1594. dec_irq |= (1 << i);
  1595. wake_up_interruptible_all(&dec_wait_queue);
  1596. handled++;
  1597. }
  1598. }
  1599. spin_unlock_irqrestore(&owner_lock, flags);
  1600. if(!handled) {
  1601. PDEBUG("Hantrodec IRQ received, but not hantrodec's!\n");
  1602. }
  1603. (void)flags;
  1604. return IRQ_RETVAL(handled);
  1605. }
  1606. /*------------------------------------------------------------------------------
  1607. Function name : ResetAsic
  1608. Description : reset asic
  1609. Return type :
  1610. ------------------------------------------------------------------------------*/
  1611. void ResetAsic(hantrodec_t * dev) {
  1612. int i, j;
  1613. u32 status;
  1614. for (j = 0; j < dev->cores; j++) {
  1615. status = ioread32((void *)(dev->hwregs[j] + HANTRODEC_IRQ_STAT_DEC_OFF));
  1616. if( status & HANTRODEC_DEC_E) {
  1617. /* abort with IRQ disabled */
  1618. status = HANTRODEC_DEC_ABORT | HANTRODEC_DEC_IRQ_DISABLE;
  1619. iowrite32(status, (void *)(dev->hwregs[j] + HANTRODEC_IRQ_STAT_DEC_OFF));
  1620. }
  1621. if (IS_G1(dev->hw_id[j]))
  1622. /* reset PP */
  1623. iowrite32(0, (void *)(dev->hwregs[j] + HANTRO_IRQ_STAT_PP_OFF));
  1624. for (i = 4; i < dev->iosize[j]; i += 4) {
  1625. iowrite32(0, (void *)(dev->hwregs[j] + i));
  1626. }
  1627. }
  1628. }
  1629. /*------------------------------------------------------------------------------
  1630. Function name : dump_regs
  1631. Description : Dump registers
  1632. Return type :
  1633. ------------------------------------------------------------------------------*/
  1634. #ifdef HANTRODEC_DEBUG
  1635. void dump_regs(hantrodec_t *dev) {
  1636. int i,c;
  1637. PDEBUG("Hantrodec Reg Dump Start\n");
  1638. for(c = 0; c < dev->cores; c++) {
  1639. for(i = 0; i < dev->iosize[c]; i += 4*4) {
  1640. PDEBUG("\toffset %04X: %08X %08X %08X %08X\n", i,
  1641. ioread32(dev->hwregs[c] + i),
  1642. ioread32(dev->hwregs[c] + i + 4),
  1643. ioread32(dev->hwregs[c] + i + 16),
  1644. ioread32(dev->hwregs[c] + i + 24));
  1645. }
  1646. }
  1647. PDEBUG("Hantrodec Reg Dump End\n");
  1648. }
  1649. #endif
  1650. av_unused int RegisterIRQ(i32 irq_offset, IRQHandler isr_handler, i32 flag, const char* name, void* data) {
  1651. //_xtos_set_interrupt_handle
  1652. u32 irq_mask = 1 << irq_offset; //irq_offset -> Irq[0] is 3
  1653. u32 enabled_int = 0;
  1654. if ((xthal_get_intenable() & irq_mask) == 0)
  1655. {
  1656. /* Clear MCPU DB2 interrupt before enable */
  1657. xthal_set_intclear(irq_mask);
  1658. /* Assign Interrupt handler */
  1659. xt_set_interrupt_handler(irq_offset, (xt_handler) isr_handler, data);
  1660. *((volatile uint32_t *)0x0280004c) = 0x1; // clear current irq for slice 0
  1661. *((volatile uint32_t *)0x02800050) = 0x1; // enable dec irq for slice 0
  1662. xt_ints_on(irq_mask);
  1663. }
  1664. enabled_int = xthal_get_intenable();
  1665. printf("INTs are enabled: 0x%x\n", enabled_int);
  1666. return 0;
  1667. }
  1668. av_unused void IntEnableIRQ(u32 irq_offset) {
  1669. //_xtos_interrupt_enable
  1670. u32 irq_mask = 1 << irq_offset;
  1671. u32 enabled_int = 0;
  1672. xt_ints_on(irq_mask);
  1673. enabled_int = xthal_get_intenable();
  1674. printf("INTs are enabled 2: 0x%x\n", enabled_int);
  1675. }
  1676. av_unused void IntDisableIRQ(u32 irq_offset) {
  1677. //_xtos_interrupt_disable
  1678. u32 irq_mask = 1 << irq_offset;
  1679. u32 enabled_int = 0;
  1680. xt_ints_off(irq_mask);
  1681. enabled_int = xthal_get_intenable();
  1682. printf("INTs are disabled 3: 0x%x\n", enabled_int);
  1683. }
  1684. av_unused void IntClearIRQStatus(u32 irq_offset, u32 type) {
  1685. //xthal_set_intclear
  1686. *((volatile uint32_t *)0x0280004c) = 0x1; // clear current irq for slice 0
  1687. u32 irq_mask = 1 << irq_offset;
  1688. xthal_set_intclear(irq_mask);
  1689. }
  1690. static inline uint32_t ReadInterruptStatus(void) {
  1691. uint32_t interrupt;
  1692. __asm__ __volatile__("rsr %0, interrupt": "=a"(interrupt));
  1693. return interrupt;
  1694. }
  1695. //For debug
  1696. av_unused u32 IntGetIRQStatus(u32 irq_offset) {
  1697. uint32_t ret_val;
  1698. //ReadInterruptStatus
  1699. ret_val = ReadInterruptStatus();
  1700. //mask other interrupts ?
  1701. ret_val &= (1 << irq_offset);
  1702. // return 1 if requested interrupt is set
  1703. if (ret_val)
  1704. ret_val = 1;
  1705. return 0;
  1706. }