vse_regs.h 16 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. #ifndef _VSE_REGS_H_
  54. #define _VSE_REGS_H_
  55. /* product identification */
  56. #define VSE_REG_ID 0x00000000
  57. /* VSE CTL
  58. 17 regs_enable_ram_clk "clk domain ram clock 1: enable 0: disable"
  59. 16 auto_upd
  60. 15 cfg_upd
  61. 14 dma_frame_start_clk
  62. 13:11 input select
  63. 000 isp0 mp
  64. 001 isp0 sp
  65. 010 isp1 mp
  66. 011 isp1 sp
  67. 100 dewarp
  68. 101 dma
  69. 10:9 input format
  70. 00 YUV422SP
  71. 01 YUV422I
  72. 10 YUV420SP
  73. 8 soft reset
  74. 7:0 path enable
  75. bit:0 path 0
  76. bit:1 path 1
  77. bit:2 path 2
  78. */
  79. #define VSE_REG_CTRL 0x00000004
  80. #define VSE_CONTROL_ENABLE_RAM_CLK 17
  81. #define VSE_CONTROL_AUTO_UPDATE_BIT 16
  82. #define VSE_CONTROL_CONFIG_UPDATE_BIT 15
  83. #define VSE_CONTROL_DMA_FRAME_START_BIT 14
  84. #define VSE_CONTROL_INPUT_SELECT_SHIFT 11
  85. #define VSE_CONTROL_INPUT_SELECT (7 << 11)
  86. #define VSE_CONTROL_INPUT_FORMAT_SHIFT 9
  87. #define VSE_CONTROL_INPUT_FORMAT (3 << 9)
  88. #define VSE_CONTROL_SOFT_RESET_BIT 8
  89. #define VSE_CONTROL_PATH2_ENABLE_BIT 2
  90. #define VSE_CONTROL_PATH1_ENABLE_BIT 1
  91. #define VSE_CONTROL_PATH0_ENABLE_BIT 0
  92. /* input size 28:16 height, 12:0 width */
  93. #define VSE_REG_IN_SIZE 0x00000008
  94. #define VSE_REG_CTRL_SHD 0x0000000C
  95. /* RSZ CTL
  96. 10 auto update
  97. 9 config update
  98. 8 crop enable
  99. 7 scale vc up
  100. 6 scale vy up
  101. 5 scale hc up
  102. 4 scale hy up
  103. 3 scale vc enable
  104. 2 scale vy enable
  105. 1 scale hc enable
  106. 0 scale hy enable
  107. */
  108. #define VSE_REG_RSZ0_CTL 0x00000010
  109. #define VSE_REG_RSZ1_CTL 0x000000A0 /* repeat */
  110. #define VSE_REG_RSZ2_CTL 0x00000130 /* repeat */
  111. #define VSE_RSZBASE(c) ((c) == 0 ? VSE_REG_RSZ0_CTL : ((c) == 1 ? VSE_REG_RSZ1_CTL : VSE_REG_RSZ2_CTL))
  112. /* NOTICE: repeat 3 times, using as VSE_REG_RSZX_CTL + VSE_RSZ_SCALE_HY */
  113. #define VSE_RSZ_SCALE_HY 0x00000004
  114. #define VSE_RSZ_SCALE_HCB 0x00000008
  115. #define VSE_RSZ_SCALE_HCR 0x0000000C
  116. #define VSE_RSZ_SCALE_VY 0x00000010
  117. #define VSE_RSZ_SCALE_VC 0x00000014
  118. #define VSE_RSZ_PHASE_HY 0x00000018
  119. #define VSE_RSZ_PHASE_HC 0x0000001C
  120. #define VSE_RSZ_PHASE_VY 0x00000020
  121. #define VSE_RSZ_PHASE_VC 0x00000024
  122. #define VSE_RSZ_SCALE_LUT_ADDR 0x00000028
  123. #define VSE_RSZ_SCALE_LUT 0x0000002C
  124. /* RSZ0 CTRL SHD
  125. 8 crop enable
  126. 7 scale vc up
  127. 6 scale vy up
  128. 5 scale hc up
  129. 4 scale hy up
  130. 3 scale vc enable
  131. 2 scale vy enable
  132. 1 scale hc enable
  133. 0 scale hy enable
  134. */
  135. #define VSE_RSZ_CTRL_SHD 0x00000030
  136. #define VSE_RSZ_SCALE_HY_SHD 0x00000034
  137. #define VSE_RSZ_SCALE_HCB_SHD 0x00000038
  138. #define VSE_RSZ_SCALE_HCR_SHD 0x0000003C
  139. #define VSE_RSZ_SCALE_VY_SHD 0x00000040
  140. #define VSE_RSZ_SCALE_VC_SHD 0x00000044
  141. #define VSE_RSZ_PHASE_HY_SHD 0x00000048
  142. #define VSE_RSZ_PHASE_HC_SHD 0x0000004C
  143. #define VSE_RSZ_PHASE_VY_SHD 0x00000050
  144. #define VSE_RSZ_PHASE_VC_SHD 0x00000054
  145. /* 28:16 h end, 12:0 h start */
  146. #define VSE_RSZ_CROP_XDIR 0x00000058
  147. /* 28:16 v end, 12:0 v start */
  148. #define VSE_RSZ_CROP_YDIR 0x0000005C
  149. #define VSE_RSZ_CROP_XDIR_SHD 0x00000060
  150. #define VSE_RSZ_CROP_YDIR_SHD 0x00000064
  151. /* 2:0 frame scale */
  152. #define VSE_RSZ_FRAME_RATE 0x00000068
  153. /* frame conv ctrl
  154. 10 rsz_pack_format
  155. 9 expand_8to10_method
  156. 8 expand_8to10_enable
  157. 7 cfg_422nocosited
  158. 6 cfg_cbcr_full
  159. 5 cfg_y_full
  160. 4:2 rsz_output_format
  161. 1:0 rsz_input_format
  162. */
  163. #define VSE_REG_FORMAT_CONV_CTRL 0x0000006C
  164. /********************************************************/
  165. /* END OF RSZ REGS */
  166. #define VSE_REG_HBLANK_VALUE 0x000001A0
  167. #define VSE_REG_VBLANK_VALUE 0x000001A4
  168. #define VSE_REG_VSYNC_WIDTH 0x000001A8
  169. #define VSE_REG_HSYNC_PREAMBLE 0x000001AC
  170. /* mi ctrl
  171. 4 mi3_ycbcr_rdma_start
  172. 3 mi3_ycbcr_rdma_path_enable
  173. 2 mi2_ycbcr_path_enable
  174. 1 mi1_ycbcr_path_enable
  175. 0 mi0_ycbcr_path_enable
  176. */
  177. #define VSE_REG_MI_CTRL 0x000001B0
  178. #define VSE_REG_MI_CTRL_SHD 0x000001B4
  179. /* mi0 ctrl
  180. 5 mi0_init_offset_en : Enables updating of the offset counters shadow registers for mi0 picture to the programmed register init values.
  181. 4 mi0_init_base_en : Enables updating of the base address and buffer size shadow registers for mi0 picture to the programmed register init values
  182. 3 mi0_cfg_upd : Forced configuration update. Leads to an immediate update of the shadow registers.
  183. 2 mi0_mi_skip : Skip of current or next starting mi0 picture
  184. 1 mi0_auto_update : automatic update of configuration registers for mi0 path at frame end. 1: enabled 0: disabled
  185. 0 mi0_pingpong_enable : pingpong mode of configuration registers for mi0 path at frame end. 1: enabled 0: disabled
  186. */
  187. /* REPEAT 3 TIMES */
  188. #define VSE_REG_MI_PATH_0 0x000001C0
  189. #define VSE_REG_MI_PATH_1 0x00000260
  190. #define VSE_REG_MI_PATH_2 0x00000310
  191. #define VSE_MI_BASE(c) ((c) == 0 ? VSE_REG_MI_PATH_0 : ((c) == 1 ? VSE_REG_MI_PATH_1 : VSE_REG_MI_PATH_2))
  192. /* mi0 format
  193. 8:7 mi0_wr_yuv_nvy
  194. 6 mi0_wr_yuv_n21
  195. 5 mi0_wr_fmt_aligned : 0 unaligned, 1 aligned
  196. 4:3 mi0_wr_yuv_str
  197. 2:1 mi0_wr_yuv_fmt
  198. 0 mi0_wr_yuv_bit : 0 8bit, 1 10 bit.
  199. */
  200. #define VSE_REG_MI_FMT 0x00000004
  201. /* Base address of mi0 picture Y component ring buffer. */
  202. #define VSE_REG_MI_Y_BASE_ADDR_INIT 0x00000014
  203. /* Size of mi0 picture Y component ring buffer. */
  204. #define VSE_REG_MI_Y_SIZE_INIT 0x00000018
  205. /* Offset counter init value of mi0 picture Y component ring buffer. */
  206. #define VSE_REG_MI_Y_OFFSET_COUNT_INIT 0x0000001C
  207. /* Line length of mi0 picture Y component or RGB picture n pixel, also known as line stride. */
  208. #define VSE_REG_MI_Y_LENGTH 0x00000020
  209. /* Image width of the mi0 picture Y component or RGB picture in pixel */
  210. #define VSE_REG_MI_Y_PIC_WIDTH 0x00000024
  211. /* Image height of the y component or RGB picture in pixel. */
  212. #define VSE_REG_MI_Y_PIC_HEIGHT 0x00000028
  213. /* Image size of the Y component or RGB picture in pixel which has to be the Y line length multiplied by the Y image height */
  214. #define VSE_REG_MI_Y_PIC_SIZE 0x0000002C
  215. /* CBCR */
  216. #define VSE_REG_MI_CB_BASE_ADDR_INIT 0x00000030
  217. #define VSE_REG_MI_CB_SIZE_INIT 0x00000034
  218. #define VSE_REG_MI_CB_OFFSET_COUNT_INIT 0x00000038
  219. #define VSE_REG_MI_CR_BASE_ADDR_INIT 0x0000003C
  220. #define VSE_REG_MI_CR_SIZE_INIT 0x00000040
  221. #define VSE_REG_MI_CR_OFFSET_COUNT_INIT 0x00000044
  222. /* 2nd ping pong base address of main picture Y component buffer. */
  223. #define VSE_REG_MI_Y_BASE_ADDR_INIT2 0x00000048
  224. #define VSE_REG_MI_CB_BASE_ADDR_INIT2 0x0000004C
  225. #define VSE_REG_MI_CR_BASE_ADDR_INIT2 0x00000050
  226. /* Offset counter value which points to the start address of the previously processed picture. Updated at frame end. */
  227. #define VSE_REG_MI_Y_OFFS_CNT_START 0x00000054
  228. #define VSE_REG_MI_CB_OFFS_CNT_START 0x00000058
  229. #define VSE_REG_MI_CR_OFFS_CNT_START 0x0000005C
  230. /* MI SHD */
  231. #define VSE_REG_MI_Y_BASE_ADDR_SHD 0x00000060
  232. #define VSE_REG_MI_Y_SIZE_SHD 0x00000064
  233. #define VSE_REG_MI_Y_OFFS_COUNT_SHD 0x00000068
  234. #define VSE_REG_MI_CB_BASE_ADDR_SHD 0x0000006C
  235. #define VSE_REG_MI_CB_SIZE_SHD 0x00000070
  236. #define VSE_REG_MI_CB_OFFS_COUNT_SHD 0x00000074
  237. #define VSE_REG_MI_CR_BASE_ADDR_SHD 0x00000078
  238. #define VSE_REG_MI_CR_SIZE_SHD 0x0000007C
  239. #define VSE_REG_MI_CR_OFFS_COUNT_SHD 0x00000080
  240. #define VSE_REG_MI_STATUS_CLR 0x00000084
  241. #define VSE_REG_MI_CTRL_STATUS 0x00000088
  242. #define VSE_REG_MI_Y_IRQ_OFFS_INIT 0x0000008C
  243. #define VSE_REG_MI_Y_IRQ_OFFS_SHD 0x00000090
  244. /********************************************************/
  245. /* END OF MI0 MI1 MI2 */
  246. /* MI3 DMA CTL
  247. 7 regs_enable_ram_clk "clk domain ram clock 1: enable 0: disable"
  248. 6:5 burst_len_chrom
  249. 4:3 burst_len_lum
  250. 2 frame start
  251. 1 soft reset
  252. 0 soft_upd
  253. */
  254. #define VSE_REG_DMA_CTRL 0x000003A8
  255. /* MI3 DMA FORMAT
  256. 8:7 mi3_rd_yuv_nvy
  257. 6 mi3_rd_yuv_n21
  258. 5 mi3_rd_fmt_aligned
  259. 4:3 mi3_rd_yuv_str
  260. 2:1 mi3_rd_yuv_fmt
  261. 0 mi3_rd_yuv_bit
  262. */
  263. #define VSE_REG_DMA_FORMAT 0x000003AC
  264. #define VSE_REG_DMA_Y_PIC_WIDTH 0x000003B0
  265. #define VSE_REG_DMA_Y_PIC_HEIGHT 0x000003B4
  266. #define VSE_REG_DMA_Y_PIC_STRIDE 0x000003B8
  267. #define VSE_REG_Y_PIC_START_ADDR 0x000003BC
  268. #define VSE_REG_CB_PIC_START_ADDR 0x000003C0
  269. #define VSE_REG_CR_PIC_START_ADDR 0x000003C4
  270. #define VSE_REG_Y_START_ADDR_SHD 0x000003C8
  271. #define VSE_REG_CB_START_ADDR_SHD 0x000003CC
  272. #define VSE_REG_CR_START_ADDR_SHD 0x000003D0
  273. /* #define VSE_REG_DMA_STATUS 0x000003D4 */
  274. /********************************************************/
  275. /* END OF MI3 */
  276. /* MI0 bus config
  277. 19:16 mi_m0_wr_swap_v
  278. 15:12 mi_m0_wr_swap_u
  279. 11:8 mi_m0_wr_swap_y
  280. 7:6 mi_m0_rd_issue_cap
  281. 5:4 mi_m0_wr_issue_cap
  282. 3:2 mi_m0_rd_burst_len
  283. 1:0 mi_m0_wr_burst_len
  284. */
  285. #define VSE_REG_MI0_BUS_CONFIG 0x000003E0
  286. /* MI0 bus id
  287. 24 mi_m0_rd_id_en
  288. 23:16 mi_m0_rd_id_cfg
  289. 8 mi_m0_wr_id_en
  290. 7:0 mi_m0_wr_id_cfg
  291. */
  292. #define VSE_REG_MI0_BUS_ID 0x000003E4
  293. #define VSE_REG_MI0_BUS_TIME_OUT 0x000003E8
  294. #define VSE_REG_MI0_AXI_STATUS 0x000003EC
  295. #define VSE_REG_MI1_BUS_CONFIG 0x000003F0
  296. #define VSE_REG_MI1_BUS_ID 0x000003F4
  297. #define VSE_REG_MI1_BUS_TIME_OUT 0x000003F8
  298. #define VSE_REG_MI1_AXI_STATUS 0x000003FC
  299. /********************************************************/
  300. /* END OF BUS CONFIG */
  301. /* MI IMSC STATUS
  302. 12 mi_dma_ycbcr_ready
  303. 11 wrap_mi2_cr
  304. 10 wrap_mi2_cb
  305. 9 wrap_mi2_y
  306. 8 wrap_mi1_cr
  307. 7 wrap_mi1_cb
  308. 6 wrap_mi1_y
  309. 5 wrap_mi0_cr
  310. 4 wrap_mi0_cb
  311. 3 wrap_mi0_y
  312. 2 mi2_ycbcr_frame_end
  313. 1 mi1_ycbcr_frame_end
  314. 0 mi0_ycbcr_frame_end
  315. */
  316. #define VSE_REG_MI_IMSC 0x00000400
  317. /* MI IMSC ERROR
  318. 5 mi2_bus_buserr
  319. 4 mi2_bus_timeo
  320. 3 mi1_bus_buserr
  321. 2 mi1_bus_timeo
  322. 1 mi0_bus_buserr
  323. 0 mi0_bus_timeo
  324. */
  325. #define VSE_REG_MI_IMSC1 0x00000404
  326. #define VSE_REG_MI_ISR 0x00000408 /* same as imsc */
  327. #define VSE_REG_MI_ISR1 0x0000040C /* same as imsc1 */
  328. #define VSE_REG_MI_MSI 0x00000410
  329. #define VSE_REG_MI_MSI1 0x00000414
  330. #define VSE_REG_MI_ICR 0x00000418
  331. #define VSE_REG_MI_ICR1 0x0000041C
  332. #define VSE_REG_MI_RIS 0x00000420
  333. #define VSE_REG_MI_RIS1 0x00000424
  334. /* slice of VSE_REG_FORMAT_CONV_CTRL */
  335. #define VSE_FORMAT_CONV_ENABLE_PACK_SHIFT 10
  336. #define VSE_FORMAT_CONV_ENABLE_PACK (1 << 10)
  337. #define VSE_FORMAT_CONV_EXPAND_8TO10_METHOD_SHIFT 9
  338. #define VSE_FORMAT_CONV_EXPAND_8TO10_METHOD (1 << 9)
  339. #define VSE_FORMAT_CONV_EXPAND_8TO10_ENABLE_SHIFT 8
  340. #define VSE_FORMAT_CONV_EXPAND_8TO10_ENABLE (1 << 8)
  341. #define VSE_FORMAT_CONV_CONFIG_422NOCO_SHIFT 7
  342. #define VSE_FORMAT_CONV_CONFIG_422NOCO (1 << 7)
  343. #define VSE_FORMAT_CONV_CBCR_FULL_SHIFT 6
  344. #define VSE_FORMAT_CONV_CBCR_FULL (1 << 6)
  345. #define VSE_FORMAT_CONV_Y_FULL_SHIFT 5
  346. #define VSE_FORMAT_CONV_Y_FULL (1 << 5)
  347. #define VSE_FORMAT_CONV_OUTPUT_FORMAT_SHIFT 2
  348. #define VSE_FORMAT_CONV_OUTPUT_FORMAT (7 << 2)
  349. #define VSE_FORMAT_CONV_INPUT_FORMAT_SHIFT 0
  350. #define VSE_FORMAT_CONV_INPUT_FORMAT (3)
  351. /* slice of VSE_REG_RSZ0_CTL */
  352. #define VSE_RESIZE_CONTROL_AUTO_UPDATE_BIT 10
  353. #define VSE_RESIZE_CONTROL_CONFIG_UPDATE_BIT 9
  354. #define VSE_RESIZE_CONTROL_CROP_ENABLE_BIT 8
  355. #define VSE_RESIZE_CONTROL_SCALE_VCUP_BIT 7
  356. #define VSE_RESIZE_CONTROL_SCALE_VYUP_BIT 6
  357. #define VSE_RESIZE_CONTROL_SCALE_HCUP_BIT 5
  358. #define VSE_RESIZE_CONTROL_SCALE_HYUP_BIT 4
  359. #define VSE_RESIZE_CONTROL_SCALE_VC_ENABLE_BIT 3
  360. #define VSE_RESIZE_CONTROL_SCALE_VY_ENABLE_BIT 2
  361. #define VSE_RESIZE_CONTROL_SCALE_HC_ENABLE_BIT 1
  362. #define VSE_RESIZE_CONTROL_SCALE_HY_ENABLE_BIT 0
  363. /* slice of VSE_REG_MI_FMT */
  364. #define VSE_MI_FORMAT_WR_YUV_NVY_SHIFT 7
  365. #define VSE_MI_FORMAT_WR_YUV_NVY (3 << 7)
  366. #define VSE_MI_FORMAT_WR_YUV_N21_SHIFT 6
  367. #define VSE_MI_FORMAT_WR_YUV_N21 (1 << 6)
  368. #define VSE_MI_FORMAT_WR_FMT_ALIGNED_SHIFT 5
  369. #define VSE_MI_FORMAT_WR_FMT_ALIGNED (1 << 5)
  370. #define VSE_MI_FORMAT_WR_YUV_STR_SHIFT 3
  371. #define VSE_MI_FORMAT_WR_YUV_STR (3 << 3)
  372. #define VSE_MI_FORMAT_WR_YUV_FMT_SHIFT 1
  373. #define VSE_MI_FORMAT_WR_YUV_FMT (3 << 1)
  374. #define VSE_MI_FORMAT_WR_YUV_10BIT_SHIFT 0
  375. #define VSE_MI_FORMAT_WR_YUV_10BIT (1)
  376. /* slice of VSE_REG_MI_CTRL */
  377. #define VSE_MI_CONTROL_RDMA_START_BIT 4
  378. #define VSE_MI_CONTROL_RDMA_ENABLE_BIT 3
  379. #define VSE_MI_CONTROL_MI2_PATH_ENABLE_BIT 2
  380. #define VSE_MI_CONTROL_MI1_PATH_ENABLE_BIT 1
  381. #define VSE_MI_CONTROL_MI0_PATH_ENABLE_BIT 0
  382. /* slice of VSE_REG_MI_PATH */
  383. #define VSE_MI_PATH_INIT_OFFSET_EN_BIT 5
  384. #define VSE_MI_PATH_INIT_BASE_EN_BIT 4
  385. #define VSE_MI_PATH_CONFIG_UPDATE_BIT 3
  386. #define VSE_MI_PATH_ENABLE_SKIP_BIT 2
  387. #define VSE_MI_PATH_AUTO_UPDATE_BIT 1
  388. #define VSE_MI_PATH_ENABLE_PINGPONG_BIT 0
  389. #define VSE_MI_ISR_STATUS_DMA_YCBCR_READY_BIT 12
  390. #define VSE_MI_ISR_STATUS_WRAP_MI2_CR_BIT 11
  391. #define VSE_MI_ISR_STATUS_WRAP_MI2_CB_BIT 10
  392. #define VSE_MI_ISR_STATUS_WRAP_MI2_Y_BIT 9
  393. #define VSE_MI_ISR_STATUS_WRAP_MI1_CR_BIT 8
  394. #define VSE_MI_ISR_STATUS_WRAP_MI1_CB_BIT 7
  395. #define VSE_MI_ISR_STATUS_WRAP_MI1_Y_BIT 6
  396. #define VSE_MI_ISR_STATUS_WRAP_MI0_CR_BIT 5
  397. #define VSE_MI_ISR_STATUS_WRAP_MI0_CB_BIT 4
  398. #define VSE_MI_ISR_STATUS_WRAP_MI0_Y_BIT 3
  399. #define VSE_MI_ISR_STATUS_MI2_FRAME_END_BIT 2
  400. #define VSE_MI_ISR_STATUS_MI1_FRAME_END_BIT 1
  401. #define VSE_MI_ISR_STATUS_MI0_FRAME_END_BIT 0
  402. #define VSE_MI_ISR_ERROR_MI2_BUS_ERROR_BIT 5
  403. #define VSE_MI_ISR_ERROR_MI2_BUS_TIMEOUT_BIT 4
  404. #define VSE_MI_ISR_ERROR_MI1_BUS_ERROR_BIT 3
  405. #define VSE_MI_ISR_ERROR_MI1_BUS_TIMEOUT_BIT 2
  406. #define VSE_MI_ISR_ERROR_MI0_BUS_ERROR_BIT 1
  407. #define VSE_MI_ISR_ERROR_MI0_BUS_TIMEOUT_BIT 0
  408. #define VSE_MI_BUS_CONFIG_WR_SWAP_V_SHIFT 16
  409. #define VSE_MI_BUS_CONFIG_WR_SWAP_V (0XF << 16)
  410. #define VSE_MI_BUS_CONFIG_WR_SWAP_U_SHIFT 12
  411. #define VSE_MI_BUS_CONFIG_WR_SWAP_U (0XF << 12)
  412. #define VSE_MI_BUS_CONFIG_WR_SWAP_Y_SHIFT 8
  413. #define VSE_MI_BUS_CONFIG_WR_SWAP_Y (0XF << 8)
  414. #define VSE_MI_BUS_CONFIG_RD_ISSUE_CAP_SHIFT 6
  415. #define VSE_MI_BUS_CONFIG_RD_ISSUE_CAP (0X3 << 6)
  416. #define VSE_MI_BUS_CONFIG_WR_ISSUE_CAP_SHIFT 4
  417. #define VSE_MI_BUS_CONFIG_WR_ISSUE_CAP (0X3 << 4)
  418. #define VSE_MI_BUS_CONFIG_RD_BURST_LEN_SHIFT 2
  419. #define VSE_MI_BUS_CONFIG_RD_BURST_LEN (0X3 << 2)
  420. #define VSE_MI_BUS_CONFIG_WR_BURST_LEN_SHIFT 0
  421. #define VSE_MI_BUS_CONFIG_WR_BURST_LEN (0X3 << 0)
  422. #ifndef REG_GET_MASK
  423. #define REG_GET_MASK(reg, mask)\
  424. (((reg) & (mask)) >> (mask##_SHIFT))
  425. #define REG_SET_MASK(reg, mask, value)\
  426. {\
  427. ((reg) = (((reg) & ~(mask)) | (((value) << (mask##_SHIFT)) & (mask))));\
  428. }
  429. #define REG_GET_BIT(reg, shift)\
  430. (((reg) & 1) >> shift)
  431. #define REG_SET_BIT(reg, shift, value)\
  432. {\
  433. ((reg) = (((reg) & ~(1 << (shift))) | (((value) & 1) << (shift))));\
  434. }
  435. #endif
  436. #endif /* _VSE_REGS_H_ */