dwe_driver_of.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582
  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. #include <linux/module.h>
  54. #include <linux/pm_runtime.h>
  55. #include <media/v4l2-event.h>
  56. #include "dwe_driver.h"
  57. #include "dwe_ioctl.h"
  58. #define DEWARP_NODE_NUM (2)
  59. static struct dwe_device *pdwe_dev[DEWARP_NODE_NUM] = {NULL};
  60. int dwe_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
  61. struct v4l2_event_subscription *sub)
  62. {
  63. return v4l2_event_subscribe(fh, sub, 2, NULL);
  64. }
  65. int dwe_unsubscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
  66. struct v4l2_event_subscription *sub)
  67. {
  68. return v4l2_event_unsubscribe(fh, sub);
  69. }
  70. #ifdef CONFIG_COMPAT
  71. static long dwe_ioctl_compat(struct v4l2_subdev *sd,
  72. unsigned int cmd, void *arg)
  73. {
  74. return dwe_devcore_ioctl(v4l2_get_subdevdata(sd), cmd, arg);
  75. }
  76. long dwe_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
  77. {
  78. return dwe_ioctl_compat(sd, cmd, arg);
  79. }
  80. #else /* CONFIG_COMPAT */
  81. long dwe_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
  82. {
  83. return dwe_devcore_ioctl(v4l2_get_subdevdata(sd), cmd, arg);
  84. }
  85. #endif /* CONFIG_COMPAT */
  86. static int dwe_enable_clocks(struct dwe_device *dwe_dev)
  87. {
  88. int ret;
  89. ret = clk_prepare_enable(dwe_dev->clk_core);
  90. if (ret)
  91. return ret;
  92. ret = clk_prepare_enable(dwe_dev->clk_axi);
  93. if (ret)
  94. goto disable_clk_core;
  95. ret = clk_prepare_enable(dwe_dev->clk_ahb);
  96. if (ret)
  97. goto disable_clk_axi;
  98. return 0;
  99. disable_clk_axi:
  100. clk_disable_unprepare(dwe_dev->clk_axi);
  101. disable_clk_core:
  102. clk_disable_unprepare(dwe_dev->clk_core);
  103. return ret;
  104. }
  105. static void dwe_disable_clocks(struct dwe_device *dwe_dev)
  106. {
  107. clk_disable_unprepare(dwe_dev->clk_ahb);
  108. clk_disable_unprepare(dwe_dev->clk_axi);
  109. clk_disable_unprepare(dwe_dev->clk_core);
  110. }
  111. int dwe_set_stream(struct v4l2_subdev *sd, int enable)
  112. {
  113. struct dwe_device *dwe_dev = v4l2_get_subdevdata(sd);
  114. struct vvbuf_ctx *ctx;
  115. struct media_pad *pad;
  116. unsigned long flags;
  117. int state;
  118. struct vb2_dc_buf *src_buf = NULL;
  119. if (!enable)
  120. dwe_dev->state &= ~STATE_STREAM_STARTED;
  121. else
  122. dwe_dev->state |= STATE_STREAM_STARTED;
  123. pad = &dwe_dev->pads[DWE_PAD_SINK];
  124. pad = media_entity_remote_pad(pad);
  125. if (pad && is_media_entity_v4l2_subdev(pad->entity)) {
  126. sd = media_entity_to_v4l2_subdev(pad->entity);
  127. v4l2_subdev_call(sd, video, s_stream, enable);
  128. }
  129. if (!enable) {
  130. mutex_lock(&dwe_dev->core->mutex);
  131. state = dwe_dev->core->state;
  132. mutex_unlock(&dwe_dev->core->mutex);
  133. if (state <= 0) {
  134. ctx = &dwe_dev->core->bctx[DWE_PAD_SINK];
  135. spin_lock_irqsave(&ctx->irqlock, flags);
  136. while (!list_empty(&ctx->dmaqueue)){
  137. src_buf = list_first_entry(&ctx->dmaqueue,
  138. struct vb2_dc_buf, irqlist);
  139. if (src_buf != NULL){
  140. list_del(&src_buf->irqlist);
  141. vvbuf_ready(ctx , src_buf->pad, src_buf);
  142. }
  143. }
  144. spin_unlock_irqrestore(&ctx->irqlock, flags);
  145. }
  146. ctx = &dwe_dev->bctx[DWE_PAD_SOURCE];
  147. spin_lock_irqsave(&ctx->irqlock, flags);
  148. if (!list_empty(&ctx->dmaqueue))
  149. list_del_init(&ctx->dmaqueue);
  150. spin_unlock_irqrestore(&ctx->irqlock, flags);
  151. }
  152. return 0;
  153. }
  154. static struct v4l2_subdev_core_ops dwe_v4l2_subdev_core_ops = {
  155. .ioctl = dwe_ioctl,
  156. .subscribe_event = dwe_subscribe_event,
  157. .unsubscribe_event = dwe_unsubscribe_event,
  158. };
  159. static struct v4l2_subdev_video_ops dwe_v4l2_subdev_video_ops = {
  160. .s_stream = dwe_set_stream,
  161. };
  162. static struct v4l2_subdev_ops dwe_v4l2_subdev_ops = {
  163. .core = &dwe_v4l2_subdev_core_ops,
  164. .video = &dwe_v4l2_subdev_video_ops,
  165. };
  166. static int dwe_link_setup(struct media_entity *entity,
  167. const struct media_pad *local,
  168. const struct media_pad *remote, u32 flags)
  169. {
  170. return 0;
  171. }
  172. static const struct media_entity_operations dwe_media_ops = {
  173. .link_setup = dwe_link_setup,
  174. .link_validate = v4l2_subdev_link_validate,
  175. };
  176. static void dwe_src_buf_notify(struct vvbuf_ctx *ctx, struct vb2_dc_buf *buf)
  177. {
  178. struct v4l2_subdev *sd;
  179. struct dwe_device *dwe;
  180. unsigned long flags;
  181. if (unlikely(!ctx || !buf))
  182. return;
  183. sd = media_entity_to_v4l2_subdev(buf->pad->entity);
  184. dwe = container_of(sd, struct dwe_device, sd);
  185. if (!dwe || !(dwe->state & STATE_STREAM_STARTED)) {
  186. vvbuf_ready(ctx, buf->pad, buf);
  187. return;
  188. }
  189. ctx = &dwe->core->bctx[DWE_PAD_SINK];
  190. spin_lock_irqsave(&ctx->irqlock, flags);
  191. list_add_tail(&buf->irqlist, &ctx->dmaqueue);
  192. spin_unlock_irqrestore(&ctx->irqlock, flags);
  193. dwe_on_buf_update(&dwe->core->ic_dev);
  194. }
  195. static const struct vvbuf_ops dwe_src_buf_ops = {
  196. .notify = dwe_src_buf_notify,
  197. };
  198. static void dwe_dst_buf_notify(struct vvbuf_ctx *ctx, struct vb2_dc_buf *buf)
  199. {
  200. struct v4l2_subdev *sd;
  201. struct dwe_device *dwe;
  202. unsigned long flags;
  203. if (unlikely(!ctx || !buf))
  204. return;
  205. sd = media_entity_to_v4l2_subdev(buf->pad->entity);
  206. dwe = container_of(sd, struct dwe_device, sd);
  207. spin_lock_irqsave(&ctx->irqlock, flags);
  208. list_add_tail(&buf->irqlist, &ctx->dmaqueue);
  209. spin_unlock_irqrestore(&ctx->irqlock, flags);
  210. if (dwe)
  211. dwe_on_buf_update(&dwe->core->ic_dev);
  212. }
  213. static const struct vvbuf_ops dwe_dst_buf_ops = {
  214. .notify = dwe_dst_buf_notify,
  215. };
  216. static void fake_pdev_release(struct device *dev)
  217. {
  218. pr_info("enter %s\n", __func__);
  219. }
  220. static struct platform_device fake_pdev = {
  221. .name = "fsl,fake-imx8mp-dwe",
  222. .id = 1,
  223. .dev.release = fake_pdev_release,
  224. };
  225. static int dwe_fake_pdev_creat(void)
  226. {
  227. return platform_device_register(&fake_pdev);
  228. }
  229. static void dwe_fake_pdev_destory(void)
  230. {
  231. platform_device_unregister(&fake_pdev);
  232. }
  233. static int dwe_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
  234. {
  235. struct dwe_device *dwe_dev = v4l2_get_subdevdata(sd);
  236. pm_runtime_get_sync(pdwe_dev[0]->sd.dev);
  237. dwe_dev->refcnt++;
  238. if ((pdwe_dev[0]->refcnt + pdwe_dev[1]->refcnt) == 1){
  239. msleep(1);
  240. dwe_clear_interrupts(&pdwe_dev[0]->core->ic_dev);
  241. if (devm_request_irq(pdwe_dev[0]->sd.dev, pdwe_dev[0]->irq, dwe_hw_isr, IRQF_SHARED,
  242. dev_name(pdwe_dev[0]->sd.dev), &pdwe_dev[0]->core->ic_dev) != 0) {
  243. pr_err("failed to request irq.\n");
  244. pdwe_dev[0]->refcnt = 0;
  245. pm_runtime_put_sync(pdwe_dev[0]->sd.dev);
  246. return -1;
  247. }
  248. }
  249. return 0;
  250. }
  251. static int dwe_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
  252. {
  253. struct dwe_device *dwe_dev = v4l2_get_subdevdata(sd);
  254. struct vvbuf_ctx *ctx;
  255. struct vb2_dc_buf *src_buf = NULL;
  256. unsigned long flags;
  257. dwe_dev->refcnt--;
  258. if (dwe_dev->refcnt < 0) {
  259. dwe_dev->refcnt = 0;
  260. return 0;
  261. }
  262. if (dwe_dev->refcnt == 0)
  263. dwe_dev->state = 0;
  264. if ((pdwe_dev[0]->refcnt + pdwe_dev[1]->refcnt) == 0) {
  265. devm_free_irq(pdwe_dev[0]->sd.dev, pdwe_dev[0]->irq, &pdwe_dev[0]->core->ic_dev);
  266. dwe_clear_interrupts(&pdwe_dev[0]->core->ic_dev);
  267. mutex_lock(&dwe_dev->core->mutex);
  268. pdwe_dev[0]->core->state = 0;
  269. mutex_unlock(&dwe_dev->core->mutex);
  270. ctx = &dwe_dev->core->bctx[DWE_PAD_SINK];
  271. spin_lock_irqsave(&ctx->irqlock, flags);
  272. while (!list_empty(&ctx->dmaqueue)){
  273. src_buf = list_first_entry(&ctx->dmaqueue,
  274. struct vb2_dc_buf, irqlist);
  275. if (src_buf != NULL){
  276. list_del(&src_buf->irqlist);
  277. vvbuf_ready(ctx , src_buf->pad, src_buf);
  278. }
  279. }
  280. spin_unlock_irqrestore(&ctx->irqlock, flags);
  281. msleep(5);
  282. }
  283. pm_runtime_put(pdwe_dev[0]->sd.dev);
  284. return 0;
  285. }
  286. static struct v4l2_subdev_internal_ops dwe_internal_ops = {
  287. .open = dwe_open,
  288. .close = dwe_close,
  289. };
  290. int dwe_hw_probe(struct platform_device *pdev)
  291. {
  292. struct device *dev = &pdev->dev;
  293. struct dwe_device *dwe_dev;
  294. struct resource *mem_res;
  295. int irq;
  296. int rc, i, index;
  297. int dev_id;
  298. pr_info("enter %s\n", __func__);
  299. mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  300. if (!mem_res) {
  301. pr_err("can't fetch device resource info\n");
  302. return -ENODEV;
  303. }
  304. irq = platform_get_irq(pdev, 0);
  305. if (irq < 0) {
  306. pr_err("failed to get irq number.\n");
  307. return -ENODEV;
  308. }
  309. rc = dwe_fake_pdev_creat();
  310. if (rc < 0) {
  311. pr_err("failed to creat fake pdev for dwe1.\n");
  312. goto dewarp_destory_fake_pdev;
  313. }
  314. for (dev_id = 0; dev_id < DEWARP_NODE_NUM; dev_id++) {
  315. pdwe_dev[dev_id] =
  316. kzalloc(sizeof(struct dwe_device), GFP_KERNEL);
  317. if (!pdwe_dev[dev_id]) {
  318. if (dev_id == 0)
  319. goto dewarp_destory_fake_pdev;
  320. else {
  321. dev_id = dev_id - 1;
  322. goto dewarp_entity_pads_deinit;
  323. }
  324. }
  325. dwe_dev = pdwe_dev[dev_id];
  326. dwe_dev->id = dev_id;
  327. if (dev_id == 0){
  328. dwe_dev->clk_core = devm_clk_get(dev, "core");
  329. if (IS_ERR(dwe_dev->clk_core)) {
  330. rc = PTR_ERR(dwe_dev->clk_core);
  331. dev_err(dev, "can't get core clock: %d\n", rc);
  332. return rc;
  333. }
  334. dwe_dev->clk_axi = devm_clk_get(dev, "axi");
  335. if (IS_ERR(dwe_dev->clk_axi)) {
  336. rc = PTR_ERR(dwe_dev->clk_axi);
  337. dev_err(dev, "can't get axi clock: %d\n", rc);
  338. return rc;
  339. }
  340. dwe_dev->clk_ahb = devm_clk_get(dev, "ahb");
  341. if (IS_ERR(dwe_dev->clk_ahb)) {
  342. rc = PTR_ERR(dwe_dev->clk_ahb);
  343. dev_err(dev, "can't get ahb clock: %d\n", rc);
  344. return rc;
  345. }
  346. }
  347. dwe_dev->sd.internal_ops = &dwe_internal_ops;
  348. v4l2_subdev_init(&dwe_dev->sd, &dwe_v4l2_subdev_ops);
  349. snprintf(dwe_dev->sd.name, sizeof(dwe_dev->sd.name),
  350. "%s.%d", DWE_DEVICE_NAME, dwe_dev->id);
  351. dwe_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  352. dwe_dev->sd.flags |= V4L2_SUBDEV_FL_HAS_EVENTS;
  353. dwe_dev->sd.owner = THIS_MODULE;
  354. v4l2_set_subdevdata(&dwe_dev->sd, dwe_dev);
  355. if (dev_id == 0)
  356. dwe_dev->sd.dev = &pdev->dev;
  357. else
  358. dwe_dev->sd.dev = &fake_pdev.dev;
  359. dwe_dev->sd.entity.name = dwe_dev->sd.name;
  360. dwe_dev->sd.entity.obj_type = MEDIA_ENTITY_TYPE_V4L2_SUBDEV;
  361. dwe_dev->sd.entity.function = MEDIA_ENT_F_IO_V4L;
  362. dwe_dev->sd.entity.ops = &dwe_media_ops;
  363. dwe_dev->pads[DWE_PAD_SINK].flags =
  364. MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
  365. dwe_dev->pads[DWE_PAD_SOURCE].flags =
  366. MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT;
  367. rc = media_entity_pads_init(&dwe_dev->sd.entity,
  368. DWE_PADS_NUM, dwe_dev->pads);
  369. if (rc < 0)
  370. goto dewarp_entity_pads_deinit;
  371. }
  372. for (dev_id = 0; dev_id < DEWARP_NODE_NUM; dev_id++) {
  373. dwe_dev = pdwe_dev[dev_id];
  374. for (i = 0; i < DWE_PADS_NUM; ++i)
  375. vvbuf_ctx_init(&dwe_dev->bctx[i]);
  376. dwe_dev->bctx[DWE_PAD_SINK].ops = &dwe_src_buf_ops;
  377. dwe_dev->bctx[DWE_PAD_SOURCE].ops = &dwe_dst_buf_ops;
  378. dwe_dev->irq = irq;
  379. dwe_dev->core = dwe_devcore_init(dwe_dev, mem_res);
  380. dwe_dev->sd.fwnode = of_fwnode_handle(pdev->dev.of_node);
  381. rc = v4l2_async_register_subdev(&dwe_dev->sd);
  382. if (rc < 0)
  383. goto dewarp_core_deinit;
  384. }
  385. pm_runtime_enable(&pdev->dev);
  386. pr_info("vvcam dewarp driver probed\n");
  387. return 0;
  388. dewarp_core_deinit:
  389. dwe_devcore_deinit(pdwe_dev[0]);
  390. for (index = 0; index <= dev_id; index++) {
  391. dwe_dev = pdwe_dev[index];
  392. for (i = 0; i < DWE_PADS_NUM; i++)
  393. vvbuf_ctx_deinit(&dwe_dev->bctx[i]);
  394. }
  395. dev_id = DEWARP_NODE_NUM - 1;
  396. dewarp_entity_pads_deinit:
  397. for (index = 0; index <= dev_id; index++) {
  398. dwe_dev = pdwe_dev[index];
  399. media_entity_cleanup(&dwe_dev->sd.entity);
  400. kfree(dwe_dev);
  401. }
  402. dewarp_destory_fake_pdev:
  403. dwe_fake_pdev_destory();
  404. return rc;
  405. }
  406. int dwe_hw_remove(struct platform_device *pdev)
  407. {
  408. struct dwe_device *dwe_dev;
  409. int dev_id;
  410. int i;
  411. pr_info("enter %s\n", __func__);
  412. pm_runtime_disable(&pdev->dev);
  413. dwe_devcore_deinit(pdwe_dev[0]);
  414. for (dev_id = 0; dev_id < DEWARP_NODE_NUM; dev_id++) {
  415. dwe_dev = pdwe_dev[dev_id];
  416. for (i = 0; i < DWE_PADS_NUM; i++)
  417. vvbuf_ctx_deinit(&dwe_dev->bctx[i]);
  418. media_entity_cleanup(&dwe_dev->sd.entity);
  419. v4l2_async_unregister_subdev(&dwe_dev->sd);
  420. kfree(dwe_dev);
  421. }
  422. dwe_fake_pdev_destory();
  423. pr_info("vvcam dewarp driver removed\n");
  424. return 0;
  425. }
  426. static int dwe_system_suspend(struct device *dev)
  427. {
  428. return pm_runtime_force_suspend(dev);
  429. }
  430. static int dwe_system_resume(struct device *dev)
  431. {
  432. int ret;
  433. ret = pm_runtime_force_resume(dev);
  434. if (ret < 0) {
  435. dev_err(dev, "force resume %s failed!\n", dev_name(dev));
  436. return ret;
  437. }
  438. return 0;
  439. }
  440. static int dwe_runtime_suspend(struct device *dev)
  441. {
  442. struct dwe_device *dwe_dev = pdwe_dev[0];
  443. dwe_disable_clocks(dwe_dev);
  444. return 0;
  445. }
  446. static int dwe_runtime_resume(struct device *dev)
  447. {
  448. struct dwe_device *dwe_dev = pdwe_dev[0];
  449. dwe_enable_clocks(dwe_dev);
  450. return 0;
  451. }
  452. static const struct dev_pm_ops dwe_pm_ops = {
  453. SET_SYSTEM_SLEEP_PM_OPS(dwe_system_suspend, dwe_system_resume)
  454. SET_RUNTIME_PM_OPS(dwe_runtime_suspend, dwe_runtime_resume, NULL)
  455. };
  456. static const struct of_device_id dwe_of_match[] = {
  457. {.compatible = DWE_COMPAT_NAME,},
  458. { /* sentinel */ },
  459. };
  460. MODULE_DEVICE_TABLE(of, dwe_of_match);
  461. static struct platform_driver viv_dwe_driver = {
  462. .probe = dwe_hw_probe,
  463. .remove = dwe_hw_remove,
  464. .driver = {
  465. .name = DWE_DEVICE_NAME,
  466. .owner = THIS_MODULE,
  467. .of_match_table = dwe_of_match,
  468. .pm = &dwe_pm_ops,
  469. }
  470. };
  471. static int __init viv_dwe_init_module(void)
  472. {
  473. int ret = 0;
  474. pr_info("enter %s\n", __func__);
  475. ret = platform_driver_register(&viv_dwe_driver);
  476. if (ret) {
  477. pr_err("register platform driver failed.\n");
  478. return ret;
  479. }
  480. return ret;
  481. }
  482. static void __exit viv_dwe_exit_module(void)
  483. {
  484. pr_info("enter %s\n", __func__);
  485. platform_driver_unregister(&viv_dwe_driver);
  486. }
  487. module_init(viv_dwe_init_module);
  488. module_exit(viv_dwe_exit_module);
  489. MODULE_AUTHOR("zhiye.yin@verisilicon.com");
  490. MODULE_LICENSE("GPL");
  491. MODULE_ALIAS("Dewarp");
  492. MODULE_VERSION("1.0");