dec400_ioctl.c 6.0 KB

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  1. /*
  2. * Copyright (C) 2021 Alibaba Group Holding Limited
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <linux/regmap.h>
  9. #include <linux/of_reserved_mem.h>
  10. #include <linux/io.h>
  11. #include "dec400.h"
  12. #include "dec400_ioctl.h"
  13. //#define DEBUG
  14. static void dec400_write(struct dec400_dev *dec, unsigned int addr, unsigned int val)
  15. {
  16. writel(val, dec->reg_base + addr);
  17. }
  18. static int dec400_mmu_config(struct dec400_dev *dec, void *args)
  19. {
  20. unsigned int val = 0;
  21. struct dec400_mmu_para para = {0};
  22. copy_from_user(&para, args, sizeof(para));
  23. pr_err("%s, entry\n", __func__);
  24. val = 0;
  25. val |= 0x100008c; //need confirm with VSI, no any description
  26. dec400_write(dec, DEC_CONTROL, val); //val 0x100008c
  27. dec400_write(dec, 0x0388, 0x00000001); //0xE2 gcregMMUAHBControlRegAddrs
  28. // table array base address
  29. dec400_write(dec, 0x038C, para.page_bable_addr); // 0xE3 gcregMMUAHBTableArrayBaseAddressLowRegAddrs
  30. //WriteRegister(reg_base, 0x00184, 0x00000001);//gcregMMUConfigurationRegAddrs, flush
  31. dec400_write(dec, 0x01AC, 0x00000000);//dcreMMUConfigRegAddrs
  32. return 0;
  33. }
  34. static int dec400_compress_init(struct dec400_dev *dec, void *args)
  35. {
  36. unsigned int val = 0;
  37. struct dec400_compress_init compress = {0};
  38. copy_from_user(&compress, args, sizeof(compress));
  39. val = 0x100008c;
  40. val |= (compress.enable_global_bypass) << DEC_CONTROL_DISABLE_COMPRESSION_SHIFT;
  41. val |= (!compress.enable_hw_flush) << DEC_CONTROL_DISABLE_HW_FLUSH_SHIFT;
  42. dec400_write(dec, DEC_CONTROL, val); //0x101008c
  43. //info from VSI cmodel, don't modify
  44. dec400_write(dec, DEC_CONTROL_EX, 0xa0000);
  45. //set tile status read/write ID, don't modity
  46. val = 0x3fe840;
  47. dec400_write(dec, DEC_CONTROL_EX2, val);
  48. //enable intr
  49. dec400_write(dec, DEC_INTR_EN, 0xffffffff);
  50. dec400_write(dec, DEC_INTR_EN_EX, 0xffffffff);
  51. dec400_write(dec, DEC_INTR_EN_EX2, 0xffffffff);
  52. return 0;
  53. }
  54. static int dec400_decompress_init(struct dec400_dev *dec, void *args)
  55. {
  56. unsigned int val = 0;
  57. struct dec400_compress_init compress = {0};
  58. copy_from_user(&compress, args, sizeof(compress));
  59. val = 0x100008c;
  60. val |= (compress.enable_global_bypass) << DEC_CONTROL_DISABLE_COMPRESSION_SHIFT;
  61. val |= (!compress.enable_hw_flush) << DEC_CONTROL_DISABLE_HW_FLUSH_SHIFT;
  62. dec400_write(dec, DEC_CONTROL, val); //0x100008c
  63. //info from VSI cmodel, don't modify
  64. dec400_write(dec, DEC_CONTROL_EX, 0xa0000);
  65. //set tile status read/write ID, don't modity
  66. val = 0x3fe840;
  67. dec400_write(dec, DEC_CONTROL_EX2, val);
  68. //enable intr
  69. dec400_write(dec, DEC_INTR_EN, 0xffffffff);
  70. dec400_write(dec, DEC_INTR_EN_EX, 0xffffffff);
  71. dec400_write(dec, DEC_INTR_EN_EX2, 0xffffffff);
  72. return 0;
  73. }
  74. static int dec400_compress_set_buffer(struct dec400_dev *dec, void *args)
  75. {
  76. unsigned int val = 0;
  77. struct dec400_compress_para para = {0};
  78. copy_from_user(&para, args, sizeof(para));
  79. val = 0;
  80. val |= (para.enable) << DEC_WRITE_CONFIG_COMPRESS_ENABLE_SHIFT;
  81. val |= (para.format) << DEC_WRITE_CONFIG_COMPRESS_FORMAT_SHIFT;
  82. val |= (para.align_mode) << DEC_WRITE_CONFIG_COMPRESS_ALIGN_SHIFT;
  83. val |= (para.tile_mode) << DEC_WRITE_CONFIG_COMPRESS_TILE_SHIFT;
  84. dec400_write(dec, DEC_WRITE_CFG_CH(para.channel), val);
  85. dec400_write(dec, DEC_WRITE_EX_CFG_CH(para.channel), 0);
  86. dec400_write(dec, DEC_WRITE_BUF_BASE_CH(para.channel), para.physical_stream_start);
  87. dec400_write(dec, DEC_WRITE_BUF_END_CH(para.channel), para.physical_stream_end);
  88. dec400_write(dec, DEC_WRITE_CACHE_BASE_CH(para.channel), para.physical_tile_start);
  89. dec400_write(dec, DEC_FLUSH_CACHE_CH(para.channel), 0xffffffff);
  90. #ifdef DEBUG
  91. pr_info("%s, dec400 compress0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x\n",
  92. __func__,
  93. DEC_WRITE_CFG_CH(para.channel), val,
  94. DEC_WRITE_EX_CFG_CH(para.channel), 0,
  95. DEC_WRITE_BUF_BASE_CH(para.channel), para.physical_stream_start,
  96. DEC_WRITE_BUF_END_CH(para.channel), para.physical_stream_end,
  97. DEC_WRITE_CACHE_BASE_CH(para.channel), para.physical_tile_start);
  98. #endif
  99. return 0;
  100. }
  101. static int dec400_decompress_set_buffer(struct dec400_dev *dec, void *args)
  102. {
  103. unsigned int val = 0;
  104. struct dec400_decompress_para para = {0};
  105. copy_from_user(&para, args, sizeof(para));
  106. val = 0;
  107. val |= (para.enable) << DEC_READ_CONFIG_DECOMPRESS_ENABLE_SHIFT;
  108. val |= (para.format) << DEC_READ_CONFIG_DECOMPRESS_FORMAT_SHIFT;
  109. val |= (para.align_mode) << DEC_READ_CONFIG_DECOMPRESS_ALIGN_SHIFT;
  110. val |= (para.tile_mode) << DEC_READ_CONFIG_DECOMPRESS_TILE_SHIFT;
  111. dec400_write(dec, DEC_READ_CFG_CH(para.channel), val);
  112. dec400_write(dec, DEC_READ_EX_CFG_CH(para.channel), 0);
  113. dec400_write(dec, DEC_READ_BUF_BASE_CH(para.channel), para.physical_stream_start);
  114. dec400_write(dec, DEC_READ_BUF_END_CH(para.channel), para.physical_stream_end);
  115. dec400_write(dec, DEC_READ_CACHE_BASE_CH(para.channel), para.physical_tile_start);
  116. #ifdef DEBUG
  117. pr_info("%s, dec400 decompress 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x, 0x%x = 0x%x\n",
  118. __func__,
  119. DEC_READ_CFG_CH(para.channel), val,
  120. DEC_READ_EX_CFG_CH(para.channel), 0,
  121. DEC_READ_BUF_BASE_CH(para.channel), para.physical_stream_start,
  122. DEC_READ_BUF_END_CH(para.channel), para.physical_stream_end,
  123. DEC_READ_CACHE_BASE_CH(para.channel), para.physical_tile_start);
  124. #endif
  125. return 0;
  126. }
  127. unsigned int dec400_priv_ioctl(struct dec400_dev *dev, unsigned int cmd, void *args)
  128. {
  129. int ret = -1;
  130. if (!dev) {
  131. pr_err("%s invalid para\n", __func__);
  132. return ret;
  133. }
  134. switch (cmd) {
  135. case DEC400IOC_RESET:
  136. ret = 0;
  137. break;
  138. case DEC400IOC_COMPRESS_INIT:
  139. ret = dec400_compress_init(dev, args);
  140. break;
  141. case DEC400IOC_COMPRESS_SET_BUFFER:
  142. ret = dec400_compress_set_buffer(dev, args);
  143. break;
  144. case DEC400IOC_DECOMPRESS_INIT:
  145. ret = dec400_decompress_init(dev, args);
  146. break;
  147. case DEC400IOC_DECOMPRESS_SET_BUFFER:
  148. ret = dec400_decompress_set_buffer(dev, args);
  149. break;
  150. case DEC400IOC_MMU_CONFIG:
  151. ret = dec400_mmu_config(dev, args);
  152. break;
  153. default:
  154. pr_err("unsupported command %d\n", cmd);
  155. break;
  156. }
  157. return ret;
  158. }