dec400.h 2.7 KB

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  1. /*
  2. * Verisilicon DEC400 Driver for FalconLite.
  3. *
  4. * Author: Wei Weiyu <Weiyu.Wei@verisilicon.com>
  5. *
  6. * Copyright (C) 2020 VeriSilicon Microelectronics (Shanghai) Co., Ltd.
  7. *
  8. */
  9. #ifndef __DEC_H__
  10. #define __DEC_H__
  11. #include <linux/io.h>
  12. #include <linux/of.h>
  13. #include <linux/err.h>
  14. #include <linux/clk.h>
  15. #include <linux/slab.h>
  16. #include <linux/delay.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/of_dma.h>
  21. #include <linux/device.h>
  22. #include <linux/videodev2.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/cdev.h>
  27. #define DEC_DEV_NAME "thead,dec400"
  28. #define DEC400_NAME "dec"
  29. #define DEC400_MAXCNT 3
  30. #define DEC_CHIP_REV 0x00
  31. #define DEC_CHIP_DATA 0x04
  32. #define DEC_CONTROL 0x0800
  33. #define DEC_CONTROL_EX 0x0804
  34. #define DEC_CONTROL_EX2 0x0808
  35. #define DEC_INTR_EN 0x080c
  36. #define DEC_INTR_EN_EX 0x0810
  37. #define DEC_INTR_EN_EX2 0x0814
  38. #define DEC_WRITE_CFG_CH(n) (0x0980 + (n) * 4)
  39. #define DEC_WRITE_EX_CFG_CH(n) (0x0a00 + (n) * 4)
  40. #define DEC_WRITE_BUF_BASE_CH(n) (0x0d80 + (n) * 4)
  41. #define DEC_WRITE_BUF_END_CH(n) (0x0e80 + (n) * 4)
  42. #define DEC_WRITE_CACHE_BASE_CH(n) (0x1180 + (n) * 4)
  43. #define DEC_READ_CFG_CH(n) (0x0880 + (n) * 4)
  44. #define DEC_READ_EX_CFG_CH(n) (0x0900 + (n) * 4)
  45. #define DEC_READ_BUF_BASE_CH(n) (0x0A80 + (n) * 4)
  46. #define DEC_READ_BUF_END_CH(n) (0x0B80 + (n) * 4)
  47. #define DEC_FLUSH_CACHE_CH(n) (0x0F80 + (n) * 4)
  48. #define DEC_READ_CACHE_BASE_CH(n) (0x1080 + (n) * 4)
  49. //gcregAHBDECControl
  50. #define DEC_CONTROL_DISABLE_COMPRESSION_SHIFT 1
  51. #define DEC_CONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT 2
  52. #define DEC_CONTROL_DISABLE_DISABLE_DEBUG_REG_SHIFT 3
  53. #define DEC_CONTROL_DISABLE_HW_FLUSH_SHIFT 16
  54. //gcregAHBDECControlEx2
  55. #define DEC_CONTROLEX2_TILE_STATUS_READ_ID 0
  56. #define DEC_CONTROLEX2_TILE_STATUS_WRITE_ID 7
  57. #define DEC_CONTROLEX2_WR_OT_CNT 14
  58. #define DEC_READ_CONFIG_DECOMPRESS_ENABLE_SHIFT 0
  59. #define DEC_READ_CONFIG_DECOMPRESS_SIZE_SHIFT 1
  60. #define DEC_READ_CONFIG_DECOMPRESS_FORMAT_SHIFT 3
  61. #define DEC_READ_CONFIG_DECOMPRESS_ALIGN_SHIFT 16
  62. #define DEC_READ_CONFIG_DECOMPRESS_TILE_SHIFT 25
  63. #define DEC_WRITE_CONFIG_COMPRESS_ENABLE_SHIFT 0
  64. #define DEC_WRITE_CONFIG_COMPRESS_SIZE_SHIFT 1
  65. #define DEC_WRITE_CONFIG_COMPRESS_FORMAT_SHIFT 3
  66. #define DEC_WRITE_CONFIG_COMPRESS_ALIGN_SHIFT 16
  67. #define DEC_WRITE_CONFIG_COMPRESS_TILE_SHIFT 25
  68. struct dec400_dev {
  69. int id;
  70. //int irq;
  71. dev_t devt;
  72. struct class *class;
  73. struct cdev cdev;
  74. struct mutex mutex;
  75. //enum dec_enable en;
  76. //enum vs_format fmt;
  77. //enum vs_vdieo_resolution res;
  78. //struct device *dev;
  79. void __iomem *reg_base;
  80. //struct v4l2_subdev sd;
  81. //struct vs_video_device *vdev;
  82. //struct workqueue_struct *work_queue;
  83. //struct delayed_work q_buf_wk;
  84. };
  85. #endif