isp_ioctl.c 115 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. /* process public and sample isp command. for complex modules, need new files.*/
  54. #include "mrv_all_bits.h"
  55. #include "isp_ioctl.h"
  56. #include "isp_types.h"
  57. #include "isp_wdr.h"
  58. #include <linux/dma-mapping.h>
  59. #include <linux/dma-buf.h>
  60. #ifdef __KERNEL__
  61. #include <linux/regmap.h>
  62. #include <linux/of_reserved_mem.h>
  63. #endif
  64. #include "isp_ioctl.h"
  65. volatile MrvAllRegister_t *all_regs = NULL;
  66. #ifndef __KERNEL__
  67. #define ISP_REG_SIZE 0x10000
  68. static HalHandle_t hal_handle;
  69. void isp_ic_set_hal(HalHandle_t hal)
  70. {
  71. hal_handle = hal;
  72. }
  73. void isp_write_reg(struct isp_ic_dev *dev, u32 offset, u32 val)
  74. {
  75. //isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);
  76. if (offset >= ISP_REG_SIZE)
  77. return;
  78. HalWriteReg(hal_handle, offset, val);
  79. }
  80. u32 isp_read_reg(struct isp_ic_dev *dev, u32 offset)
  81. {
  82. if (offset >= ISP_REG_SIZE)
  83. return 0;
  84. return HalReadReg(hal_handle, offset);
  85. }
  86. long isp_copy_data(void *dst, void *src, int size)
  87. {
  88. if (dst != src)
  89. memcpy(dst, src, size);
  90. return 0;
  91. }
  92. #else
  93. void isp_write_reg(struct isp_ic_dev *dev, u32 offset, u32 val)
  94. {
  95. // isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);
  96. if (offset >= ISP_REG_SIZE)
  97. return;
  98. __raw_writel(val, dev->base + offset);
  99. /*isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);*/
  100. }
  101. u32 isp_read_reg(struct isp_ic_dev *dev, u32 offset)
  102. {
  103. u32 val = 0;
  104. if (offset >= ISP_REG_SIZE)
  105. return 0;
  106. val = __raw_readl(dev->base + offset);
  107. /*isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);*/
  108. return val;
  109. }
  110. #endif
  111. int isp_reset(struct isp_ic_dev *dev)
  112. {
  113. isp_info("enter %s\n", __func__);
  114. isp_write_reg(dev, REG_ADDR(vi_ircl), 0xFFFFFFBF);
  115. #ifdef __KERNEL__
  116. mdelay(2);
  117. #endif
  118. isp_write_reg(dev, REG_ADDR(vi_ircl), 0x0);
  119. /*clear mis array*/
  120. isp_write_reg(dev, REG_ADDR(isp_ctrl), 0x0); //clear isp_ctrl disable_isp_clk
  121. isp_info("exit %s\n", __func__);
  122. return 0;
  123. }
  124. int isp_enable_tpg(struct isp_ic_dev *dev)
  125. {
  126. u32 addr, isp_tpg_ctrl;
  127. isp_info("enter %s\n", __func__);
  128. addr = REG_ADDR(isp_tpg_ctrl);
  129. isp_tpg_ctrl = isp_read_reg(dev, addr);
  130. //REG_SET_SLICE(isp_tpg_ctrl, TPG_FRAME_NUM, 1);//set tpg frame num
  131. REG_SET_SLICE(isp_tpg_ctrl, TPG_ENABLE, 1);
  132. isp_write_reg(dev, addr, isp_tpg_ctrl);
  133. isp_info("exit %s\n", __func__);
  134. return 0;
  135. }
  136. int isp_disable_tpg(struct isp_ic_dev *dev)
  137. {
  138. u32 addr, isp_tpg_ctrl;
  139. isp_info("enter %s\n", __func__);
  140. addr = REG_ADDR(isp_tpg_ctrl);
  141. isp_tpg_ctrl = isp_read_reg(dev, addr);
  142. REG_SET_SLICE(isp_tpg_ctrl, TPG_ENABLE, 0);
  143. isp_write_reg(dev, addr, isp_tpg_ctrl);
  144. isp_info("exit %s\n", __func__);
  145. return 0;
  146. }
  147. int isp_enable_bls(struct isp_ic_dev *dev)
  148. {
  149. #ifndef ISP_BLS
  150. //isp_err("unsupported function %s", __func__);
  151. return -1;
  152. #else
  153. u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl));
  154. isp_info("enter %s\n", __func__);
  155. REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_ENABLE,
  156. MRV_BLS_BLS_ENABLE_PROCESS);
  157. isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl);
  158. isp_info("exit %s\n", __func__);
  159. return 0;
  160. #endif
  161. }
  162. int isp_disable_bls(struct isp_ic_dev *dev)
  163. {
  164. #ifndef ISP_BLS
  165. //isp_err("unsupported function %s", __func__);
  166. return -1;
  167. #else
  168. u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl));
  169. isp_info("enter %s\n", __func__);
  170. REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_ENABLE,
  171. MRV_BLS_BLS_ENABLE_BYPASS);
  172. isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl);
  173. isp_info("exit %s\n", __func__);
  174. return 0;
  175. #endif
  176. }
  177. int isp_enable(struct isp_ic_dev *dev)
  178. {
  179. u32 isp_ctrl, isp_imsc;
  180. isp_info("enter %s\n", __func__);
  181. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  182. isp_imsc |= (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK);
  183. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  184. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  185. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 1);
  186. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  187. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 1);
  188. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  189. /*Set lsc tbl after isp enable*/
  190. if (dev->update_lsc_tbl) {
  191. isp_s_lsc_tbl(dev);
  192. dev->update_lsc_tbl = false;
  193. }
  194. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1);
  195. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  196. isp_info("exit %s\n", __func__);
  197. return 0;
  198. }
  199. int isp_disable(struct isp_ic_dev *dev)
  200. {
  201. u32 isp_ctrl;
  202. /* #ifndef ENABLE_IRQ
  203. u32 isp_imsc;
  204. #endif*/
  205. isp_info("enter %s\n", __func__);
  206. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  207. /* #ifndef ENABLE_IRQ
  208. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  209. isp_imsc |= (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK);
  210. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  211. #endif*/
  212. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 0);
  213. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  214. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 0);
  215. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  216. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  217. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  218. isp_write_reg(dev, REG_ADDR(isp_isr), MRV_ISP_ISR_ISP_OFF_MASK);
  219. isp_info("exit %s\n", __func__);
  220. return 0;
  221. }
  222. bool is_isp_enable(struct isp_ic_dev *dev)
  223. {
  224. // isp_info("enter %s\n", __func__);
  225. return isp_read_reg(dev, REG_ADDR(isp_ctrl)) & 0x01;
  226. }
  227. int isp_enable_lsc(struct isp_ic_dev *dev)
  228. {
  229. u32 isp_lsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_lsc_ctrl));
  230. isp_info("enter %s\n", __func__);
  231. REG_SET_SLICE(isp_lsc_ctrl, MRV_LSC_LSC_EN, 1U);
  232. isp_write_reg(dev, REG_ADDR(isp_lsc_ctrl), isp_lsc_ctrl);
  233. {
  234. uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  235. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  236. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  237. }
  238. isp_info("exit %s\n", __func__);
  239. return 0;
  240. }
  241. int isp_disable_lsc(struct isp_ic_dev *dev)
  242. {
  243. u32 isp_lsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_lsc_ctrl));
  244. isp_info("enter %s\n", __func__);
  245. REG_SET_SLICE(isp_lsc_ctrl, MRV_LSC_LSC_EN, 0U);
  246. isp_write_reg(dev, REG_ADDR(isp_lsc_ctrl), isp_lsc_ctrl);
  247. {
  248. uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  249. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  250. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  251. }
  252. isp_info("exit %s\n", __func__);
  253. return 0;
  254. }
  255. #if defined(__KERNEL__) && defined(ISP8000NANO_V1802)
  256. static int isp_gpr_input_control(struct isp_ic_dev *dev)
  257. {
  258. struct isp_context isp_ctx = *(&dev->ctx);
  259. unsigned int fmt_offset = 3;
  260. unsigned int isp_dewarp_control_val;
  261. if (dev->mix_gpr == NULL)
  262. return -ENOMEM;
  263. if (dev->id == 0)
  264. fmt_offset = 3;
  265. else
  266. fmt_offset = 13;
  267. regmap_read(dev->mix_gpr, 0x138, &isp_dewarp_control_val);
  268. if (isp_dewarp_control_val == 0)
  269. isp_dewarp_control_val = 0x8d8360;
  270. switch (isp_ctx.input_selection) {
  271. case MRV_ISP_INPUT_SELECTION_12EXT:
  272. isp_dewarp_control_val &= ~(0x3f << fmt_offset);
  273. isp_dewarp_control_val |= (0x2c << fmt_offset);
  274. break;
  275. case MRV_ISP_INPUT_SELECTION_10ZERO:
  276. case MRV_ISP_INPUT_SELECTION_10MSB:
  277. isp_dewarp_control_val &= ~(0x3f << fmt_offset);
  278. isp_dewarp_control_val |= (0x2b << fmt_offset);
  279. break;
  280. case MRV_ISP_INPUT_SELECTION_8ZERO:
  281. case MRV_ISP_INPUT_SELECTION_8MSB:
  282. isp_dewarp_control_val &= ~(0x3f << fmt_offset);
  283. isp_dewarp_control_val |= (0x2a << fmt_offset);
  284. break;
  285. default:
  286. return 0;
  287. }
  288. regmap_write(dev->mix_gpr, 0x138, isp_dewarp_control_val);
  289. return 0;
  290. }
  291. #endif
  292. int isp_s_input(struct isp_ic_dev *dev)
  293. {
  294. struct isp_context isp_ctx = *(&dev->ctx);
  295. u32 isp_ctrl, isp_acq_prop, isp_demosaic;
  296. #ifdef ISP_HDR_STITCH_RY
  297. u32 isp_stitching_ctrl;
  298. #endif //ISP_HDR_STITCH_RY
  299. isp_info("enter %s\n", __func__);
  300. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  301. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_MODE, isp_ctx.mode);
  302. isp_acq_prop = isp_read_reg(dev, REG_ADDR(isp_acq_prop));
  303. REG_SET_SLICE(isp_acq_prop, MRV_ISP_SAMPLE_EDGE, isp_ctx.sample_edge);
  304. REG_SET_SLICE(isp_acq_prop, MRV_ISP_HSYNC_POL,
  305. isp_ctx.hSyncLowPolarity);
  306. REG_SET_SLICE(isp_acq_prop, MRV_ISP_VSYNC_POL,
  307. isp_ctx.vSyncLowPolarity);
  308. REG_SET_SLICE(isp_acq_prop, MRV_ISP_BAYER_PAT, isp_ctx.bayer_pattern);
  309. REG_SET_SLICE(isp_acq_prop, MRV_ISP_CONV_422, isp_ctx.sub_sampling);
  310. REG_SET_SLICE(isp_acq_prop, MRV_ISP_CCIR_SEQ, isp_ctx.seq_ccir);
  311. REG_SET_SLICE(isp_acq_prop, MRV_ISP_FIELD_SELECTION,
  312. isp_ctx.field_selection);
  313. REG_SET_SLICE(isp_acq_prop, MRV_ISP_INPUT_SELECTION,
  314. isp_ctx.input_selection);
  315. REG_SET_SLICE(isp_acq_prop, MRV_ISP_LATENCY_FIFO_SELECTION,
  316. isp_ctx.latency_fifo);
  317. isp_write_reg(dev, REG_ADDR(isp_acq_prop), isp_acq_prop);
  318. isp_write_reg(dev, REG_ADDR(isp_acq_h_offs), isp_ctx.acqWindow.x);
  319. isp_write_reg(dev, REG_ADDR(isp_acq_v_offs), isp_ctx.acqWindow.y);
  320. isp_write_reg(dev, REG_ADDR(isp_acq_h_size), isp_ctx.acqWindow.width);
  321. isp_write_reg(dev, REG_ADDR(isp_acq_v_size), isp_ctx.acqWindow.height);
  322. #ifdef ISP_MI_HDR_RY
  323. isp_write_reg(dev, REG_ADDR(isp_hdr_interval), 0x113);
  324. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_h_blank), 0x30);
  325. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_v_blank), 0x30);
  326. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_h_size), isp_ctx.acqWindow.width);
  327. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_v_size), isp_ctx.acqWindow.height);
  328. #endif
  329. isp_write_reg(dev, REG_ADDR(isp_out_h_offs),
  330. (isp_ctx.ofWindow.x & MRV_ISP_ISP_OUT_H_OFFS_MASK));
  331. isp_write_reg(dev, REG_ADDR(isp_out_v_offs),
  332. (isp_ctx.ofWindow.y & MRV_ISP_ISP_OUT_V_OFFS_MASK));
  333. isp_write_reg(dev, REG_ADDR(isp_out_h_size),
  334. (isp_ctx.ofWindow.width & MRV_ISP_ISP_OUT_H_SIZE_MASK));
  335. isp_write_reg(dev, REG_ADDR(isp_out_v_size),
  336. (isp_ctx.ofWindow.height & MRV_ISP_ISP_OUT_V_SIZE_MASK));
  337. isp_write_reg(dev, REG_ADDR(isp_is_h_offs),
  338. (isp_ctx.isWindow.x & MRV_IS_IS_H_OFFS_MASK));
  339. isp_write_reg(dev, REG_ADDR(isp_is_v_offs),
  340. (isp_ctx.isWindow.y & MRV_IS_IS_V_OFFS_MASK));
  341. isp_write_reg(dev, REG_ADDR(isp_is_h_size),
  342. (isp_ctx.isWindow.width & MRV_IS_IS_H_SIZE_MASK));
  343. isp_write_reg(dev, REG_ADDR(isp_is_v_size),
  344. (isp_ctx.isWindow.height & MRV_IS_IS_V_SIZE_MASK));
  345. isp_demosaic = isp_read_reg(dev, REG_ADDR(isp_demosaic));
  346. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_BYPASS,
  347. isp_ctx.bypass_mode);
  348. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_TH,
  349. isp_ctx.demosaic_threshold);
  350. isp_write_reg(dev, REG_ADDR(isp_demosaic), isp_demosaic);
  351. #ifdef ISP_HDR_STITCH
  352. isp_write_reg(dev, REG_ADDR(isp_stitching_frame_width), isp_ctx.acqWindow.width);
  353. isp_write_reg(dev, REG_ADDR(isp_stitching_frame_height), isp_ctx.acqWindow.height);
  354. isp_write_reg(dev, REG_ADDR(isp_stitching_hdr_mode), isp_ctx.stitching_mode);
  355. isp_stitching_ctrl = isp_read_reg(dev, REG_ADDR(isp_stitching_ctrl));
  356. REG_SET_SLICE(isp_stitching_ctrl, STITCHING_BAYER_PATTERN, isp_ctx.bayer_pattern);
  357. isp_write_reg(dev, REG_ADDR(isp_stitching_ctrl), isp_stitching_ctrl);
  358. #endif
  359. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  360. #if defined(__KERNEL__) && defined(ISP8000NANO_V1802)
  361. isp_gpr_input_control(dev);
  362. #endif
  363. return 0;
  364. }
  365. int isp_s_digital_gain(struct isp_ic_dev *dev)
  366. {
  367. struct isp_digital_gain_cxt dgain = *(&dev->dgain);
  368. u32 isp_dgain_rb = isp_read_reg(dev, REG_ADDR(isp_dgain_rb));
  369. u32 isp_dgain_g = isp_read_reg(dev, REG_ADDR(isp_dgain_g));
  370. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  371. if (!dgain.enable) {
  372. isp_err("%s, Disable isp digital gain", __func__);
  373. REG_SET_SLICE(isp_ctrl, MRV_ISP_DIGITAL_GAIN_EN, 0U);
  374. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  375. return 0;
  376. }
  377. isp_info("enter %s\n", __func__);
  378. REG_SET_SLICE(isp_dgain_rb, ISP_DIGITAL_GAIN_R, dgain.gain_r);
  379. REG_SET_SLICE(isp_dgain_rb, ISP_DIGITAL_GAIN_B, dgain.gain_b);
  380. REG_SET_SLICE(isp_dgain_g, ISP_DIGITAL_GAIN_GR, dgain.gain_gr);
  381. REG_SET_SLICE(isp_dgain_g, ISP_DIGITAL_GAIN_GB, dgain.gain_gb);
  382. REG_SET_SLICE(isp_ctrl, MRV_ISP_DIGITAL_GAIN_EN, 1U);
  383. isp_write_reg(dev, REG_ADDR(isp_dgain_rb), isp_dgain_rb);
  384. isp_write_reg(dev, REG_ADDR(isp_dgain_g), isp_dgain_g);
  385. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  386. isp_info("exit %s\n", __func__);
  387. return 0;
  388. }
  389. int isp_s_demosaic(struct isp_ic_dev *dev)
  390. {
  391. struct isp_context isp_ctx = *(&dev->ctx);
  392. u32 isp_demosaic;
  393. isp_info("enter %s\n", __func__);
  394. isp_demosaic = isp_read_reg(dev, REG_ADDR(isp_demosaic));
  395. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_BYPASS,
  396. isp_ctx.bypass_mode);
  397. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_TH,
  398. isp_ctx.demosaic_threshold);
  399. isp_write_reg(dev, REG_ADDR(isp_demosaic), isp_demosaic);
  400. isp_info("exit %s\n", __func__);
  401. return 0;;
  402. }
  403. int isp_s_tpg(struct isp_ic_dev *dev)
  404. {
  405. struct isp_tpg_context tpg = *(&dev->tpg);
  406. u32 addr, regVal;
  407. isp_info("enter %s\n", __func__);
  408. addr = REG_ADDR(isp_tpg_ctrl);
  409. regVal = isp_read_reg(dev, addr);
  410. REG_SET_SLICE(regVal, TPG_IMG_NUM, tpg.image_type);
  411. REG_SET_SLICE(regVal, TPG_CFA_PAT, tpg.bayer_pattern);
  412. REG_SET_SLICE(regVal, TPG_COLOR_DEPTH, tpg.color_depth);
  413. REG_SET_SLICE(regVal, TPG_RESOLUTION, tpg.resolution);
  414. REG_SET_SLICE(regVal, TPG_FRAME_NUM, tpg.frame_num);
  415. isp_write_reg(dev, addr, regVal);
  416. regVal = 0;
  417. REG_SET_SLICE(regVal, TPG_PIX_GAP_IN, tpg.pixleGap);
  418. REG_SET_SLICE(regVal, TPG_LINE_GAP_IN, tpg.lineGap);
  419. isp_write_reg(dev, REG_ADDR(isp_tpg_gap_in), regVal);
  420. regVal = 0;
  421. REG_SET_SLICE(regVal, TPG_PIX_GAP_STD_IN, tpg.gapStandard);
  422. isp_write_reg(dev, REG_ADDR(isp_tpg_gap_std_in), regVal);
  423. regVal = 0;
  424. REG_SET_SLICE(regVal, TPG_RANDOM_SEED, tpg.randomSeed);
  425. isp_write_reg(dev, REG_ADDR(isp_tpg_random_seed), regVal);
  426. REG_SET_SLICE(regVal, TPG_HTOTAL_IN, tpg.user_mode_h.total);
  427. REG_SET_SLICE(regVal, TPG_VTOTAL_IN, tpg.user_mode_v.total);
  428. isp_write_reg(dev, REG_ADDR(isp_tpg_total_in), regVal);
  429. regVal = 0;
  430. REG_SET_SLICE(regVal, TPG_HACT_IN, tpg.user_mode_h.act);
  431. REG_SET_SLICE(regVal, TPG_VACT_IN, tpg.user_mode_v.act);
  432. isp_write_reg(dev, REG_ADDR(isp_tpg_act_in), regVal);
  433. regVal = 0;
  434. REG_SET_SLICE(regVal, TPG_FP_H_IN, tpg.user_mode_h.fp);
  435. REG_SET_SLICE(regVal, TPG_FP_V_IN, tpg.user_mode_v.fp);
  436. isp_write_reg(dev, REG_ADDR(isp_tpg_fp_in), regVal);
  437. regVal = 0;
  438. REG_SET_SLICE(regVal, TPG_BP_H_IN, tpg.user_mode_h.bp);
  439. REG_SET_SLICE(regVal, TPG_BP_V_IN, tpg.user_mode_v.bp);
  440. isp_write_reg(dev, REG_ADDR(isp_tpg_bp_in), regVal);
  441. regVal = 0;
  442. REG_SET_SLICE(regVal, TPG_HS_W_IN, tpg.user_mode_h.sync);
  443. REG_SET_SLICE(regVal, TPG_VS_W_IN, tpg.user_mode_v.sync);
  444. isp_write_reg(dev, REG_ADDR(isp_tpg_w_in), regVal);
  445. isp_info("exit %s\n", __func__);
  446. return 0;
  447. }
  448. int isp_s_mcm_wr(struct isp_ic_dev *dev)
  449. {
  450. struct isp_mcm_context *mcm = &dev->mcm;
  451. u32 mcm_ctrl;
  452. u32 mcm_hsync_preample_ext;
  453. u32 mcm_size, mcm_rd_fmt;
  454. int i;
  455. isp_info("enter %s\n", __func__);
  456. mcm_ctrl = isp_read_reg(dev, REG_ADDR(mcm_ctrl));
  457. mcm_rd_fmt = isp_read_reg(dev, REG_ADDR(mcm_rd_cfg));
  458. mcm_hsync_preample_ext = isp_read_reg(dev, REG_ADDR(mcm_hsync_preample_ext));
  459. REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_SWITCH, mcm->bypass_switch);
  460. REG_SET_SLICE(mcm_ctrl, MCM_WR0_FMT, mcm->wr_fmt[MCM_INDEX_WR0]);
  461. REG_SET_SLICE(mcm_ctrl, MCM_WR1_FMT, mcm->wr_fmt[MCM_INDEX_WR1]);
  462. REG_SET_SLICE(mcm_ctrl, MCM_G2_WR0_FMT, mcm->wr_fmt[MCM_INDEX_G2_WR0]);
  463. REG_SET_SLICE(mcm_ctrl, MCM_G2_WR1_FMT, mcm->wr_fmt[MCM_INDEX_G2_WR1]);
  464. REG_SET_SLICE(mcm_ctrl, MCM_SENSOR_MEM_BYPASS, mcm->sensor_mem_bypass);
  465. REG_SET_SLICE(mcm_rd_fmt, MCM_RD_FMT, mcm->rd_fmt);
  466. REG_SET_SLICE(mcm_hsync_preample_ext, MCM_HSYNC_PREAMPLE_EXT, mcm->hsync_rpeample_ext);
  467. for (i = MCM_INDEX_WR0 ; i < MCM_INDEX_WR_MAX; i++){
  468. REG_SET_SLICE(mcm_size, MCM_HEIGHT0, mcm->height[i]);
  469. REG_SET_SLICE(mcm_size, MCM_WIDTH0, mcm->width[i]);
  470. isp_write_reg(dev, REG_ADDR(mcm_size0) + i *4, mcm_size);
  471. }
  472. isp_write_reg(dev, REG_ADDR(mcm_hsync_preample_ext), mcm_hsync_preample_ext);
  473. isp_write_reg(dev, REG_ADDR(mcm_rd_cfg), mcm_rd_fmt);
  474. isp_write_reg(dev, REG_ADDR(mcm_ctrl), mcm_ctrl);
  475. isp_info("exit %s\n", __func__);
  476. return 0;
  477. }
  478. int isp_bypass_mcm(struct isp_ic_dev *dev)
  479. {
  480. struct isp_mcm_context *mcm = &dev->mcm;
  481. u32 mcm_ctrl;
  482. u32 mcm_retiming0;
  483. u32 mcm_retiming1;
  484. u32 mcm_wr_retiming0;
  485. u32 mcm_wr_retiming1;
  486. isp_info("enter %s\n", __func__);
  487. mcm_ctrl = isp_read_reg(dev, REG_ADDR(mcm_ctrl));
  488. mcm_retiming0 = isp_read_reg(dev, REG_ADDR(mcm_retiming0));
  489. mcm_retiming1 = isp_read_reg(dev, REG_ADDR(mcm_retiming1));
  490. mcm_wr_retiming0 = isp_read_reg(dev, REG_ADDR(mcm_wr_retiming0));
  491. mcm_wr_retiming1 = isp_read_reg(dev, REG_ADDR(mcm_wr_retiming1));
  492. if (mcm->bypass_enable) {
  493. REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_EN, 1);
  494. } else {
  495. REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_EN, 0);
  496. }
  497. REG_SET_SLICE(mcm_retiming0, MCM_VSYNC_DURATION, mcm->vsync_duration);
  498. REG_SET_SLICE(mcm_retiming0, MCM_VSYNC_BLANK, mcm->vsync_blank);
  499. REG_SET_SLICE(mcm_retiming1, MCM_HSYNC_PREAMPLE, mcm->hsync_preample);
  500. REG_SET_SLICE(mcm_retiming1, MCM_HSYNC_BLANK, mcm->hsync_blank);
  501. REG_SET_SLICE(mcm_wr_retiming0, MCM_VSYNC_DURATION, mcm->vsync_duration);
  502. REG_SET_SLICE(mcm_wr_retiming0, MCM_VSYNC_BLANK, mcm->vsync_blank);
  503. REG_SET_SLICE(mcm_wr_retiming1, MCM_HSYNC_PREAMPLE, mcm->hsync_preample);
  504. REG_SET_SLICE(mcm_wr_retiming1, MCM_HSYNC_BLANK, mcm->hsync_blank);
  505. isp_write_reg(dev, REG_ADDR(mcm_ctrl), mcm_ctrl);
  506. isp_write_reg(dev, REG_ADDR(mcm_retiming0), mcm_retiming0); // 0x01042801);//
  507. isp_write_reg(dev, REG_ADDR(mcm_retiming1), mcm_retiming1); //0x00008478); //
  508. isp_write_reg(dev, REG_ADDR(mcm_wr_retiming0), mcm_wr_retiming0); //0x01042801); //
  509. isp_write_reg(dev, REG_ADDR(mcm_wr_retiming1), mcm_wr_retiming1); //0x000084ec);//
  510. isp_info("exit %s\n", __func__);
  511. return 0;
  512. }
  513. int isp_s_mux(struct isp_ic_dev *dev)
  514. {
  515. struct isp_mux_context mux = *(&dev->mux);
  516. u32 vi_dpcl;
  517. isp_info("enter %s\n", __func__);
  518. vi_dpcl = isp_read_reg(dev, REG_ADDR(vi_dpcl));
  519. REG_SET_SLICE(vi_dpcl, MRV_VI_MP_MUX, mux.mp_mux);
  520. REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_SPMUX, mux.sp_mux);
  521. REG_SET_SLICE(vi_dpcl, MRV_VI_CHAN_MODE, mux.chan_mode);
  522. REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_IEMUX, mux.ie_mux);
  523. REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_SWITCH, mux.dma_read_switch);
  524. REG_SET_SLICE(vi_dpcl, MRV_IF_SELECT, mux.if_select);
  525. isp_write_reg(dev, REG_ADDR(vi_dpcl), vi_dpcl);
  526. isp_info("exit %s\n", __func__);
  527. return 0;
  528. }
  529. int isp_s_bls(struct isp_ic_dev *dev)
  530. {
  531. #ifndef ISP_BLS
  532. //isp_err("unsupported function %s", __func__);
  533. return -1;
  534. #else
  535. struct isp_bls_context bls = *(&dev->bls);
  536. u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl));
  537. isp_info("enter %s\n", __func__);
  538. REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_MODE, bls.mode);
  539. isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl);
  540. isp_write_reg(dev, REG_ADDR(isp_bls_a_fixed), bls.a);
  541. isp_write_reg(dev, REG_ADDR(isp_bls_b_fixed), bls.b);
  542. isp_write_reg(dev, REG_ADDR(isp_bls_c_fixed), bls.c);
  543. isp_write_reg(dev, REG_ADDR(isp_bls_d_fixed), bls.d);
  544. return 0;
  545. #endif
  546. }
  547. int isp_enable_awb(struct isp_ic_dev *dev)
  548. {
  549. u32 isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop));
  550. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  551. isp_info("enter %s\n", __func__);
  552. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MODE, MRV_ISP_AWB_MODE_MEAS);
  553. isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop);
  554. isp_write_reg(dev, REG_ADDR(isp_imsc),
  555. isp_imsc | MRV_ISP_IMSC_AWB_DONE_MASK);
  556. isp_info("exit %s\n", __func__);
  557. return 0;
  558. }
  559. int isp_disable_awb(struct isp_ic_dev *dev)
  560. {
  561. u32 isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop));
  562. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  563. isp_info("enter %s\n", __func__);
  564. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MODE, MRV_ISP_AWB_MODE_NOMEAS);
  565. isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop);
  566. isp_write_reg(dev, REG_ADDR(isp_imsc),
  567. isp_imsc & ~MRV_ISP_IMSC_AWB_DONE_MASK);
  568. isp_info("exit %s\n", __func__);
  569. return 0;
  570. }
  571. int isp_s_awb(struct isp_ic_dev *dev)
  572. {
  573. struct isp_awb_context awb = *(&dev->awb);
  574. u32 gain_data = 0;
  575. u32 isp_awb_thresh = 0;
  576. u32 isp_awb_ref = 0;
  577. u32 isp_awb_prop = 0;
  578. /* isp_info("enter %s\n", __func__); */
  579. isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop));
  580. if (awb.mode == MRV_ISP_AWB_MEAS_MODE_YCBCR) {
  581. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MEAS_MODE,
  582. MRV_ISP_AWB_MEAS_MODE_YCBCR);
  583. if (awb.max_y == 0) {
  584. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN,
  585. MRV_ISP_AWB_MAX_EN_DISABLE);
  586. } else {
  587. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN,
  588. MRV_ISP_AWB_MAX_EN_ENABLE);
  589. }
  590. } else if (awb.mode == MRV_ISP_AWB_MEAS_MODE_RGB) {
  591. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN,
  592. MRV_ISP_AWB_MAX_EN_DISABLE);
  593. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MEAS_MODE,
  594. MRV_ISP_AWB_MEAS_MODE_RGB);
  595. }
  596. isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop);
  597. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MAX_Y, awb.max_y);
  598. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MIN_Y__MAX_G,
  599. awb.min_y_max_g);
  600. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MAX_CSUM, awb.max_c_sum);
  601. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MIN_C, awb.min_c);
  602. isp_write_reg(dev, REG_ADDR(isp_awb_thresh), isp_awb_thresh);
  603. REG_SET_SLICE(isp_awb_ref, MRV_ISP_AWB_REF_CR__MAX_R, awb.refcr_max_r);
  604. REG_SET_SLICE(isp_awb_ref, MRV_ISP_AWB_REF_CB__MAX_B, awb.refcb_max_b);
  605. isp_write_reg(dev, REG_ADDR(isp_awb_ref), isp_awb_ref);
  606. isp_write_reg(dev, REG_ADDR(isp_awb_frames), 0);
  607. isp_write_reg(dev, REG_ADDR(isp_awb_h_offs),
  608. (MRV_ISP_AWB_H_OFFS_MASK & awb.window.x));
  609. isp_write_reg(dev, REG_ADDR(isp_awb_v_offs),
  610. (MRV_ISP_AWB_V_OFFS_MASK & awb.window.y));
  611. isp_write_reg(dev, REG_ADDR(isp_awb_h_size),
  612. (MRV_ISP_AWB_H_SIZE_MASK & awb.window.width));
  613. isp_write_reg(dev, REG_ADDR(isp_awb_v_size),
  614. (MRV_ISP_AWB_V_SIZE_MASK & awb.window.height));
  615. gain_data = 0UL;
  616. #ifdef ISP_AWB_0410 //This is Gain value component 4 bit int part and 10 bit fractional part
  617. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_R, awb.gain_r << 2);
  618. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_B, awb.gain_b << 2) ;
  619. #else //This is Gain value component 2 bit int part and 8 bit fractional part
  620. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_R, awb.gain_r);
  621. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_B, awb.gain_b);
  622. #endif
  623. isp_write_reg(dev, REG_ADDR(isp_awb_gain_rb), gain_data);
  624. gain_data = 0UL;
  625. #ifdef ISP_AWB_0410 //This is Gain value component 4 bit int part and 10 bit fractional part
  626. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GR, awb.gain_gr << 2);
  627. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GB, awb.gain_gb << 2);
  628. #else //This is Gain value component 2 bit int part and 8 bit fractional part
  629. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GR, awb.gain_gr);
  630. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GB, awb.gain_gb);
  631. #endif
  632. isp_write_reg(dev, REG_ADDR(isp_awb_gain_g), gain_data);
  633. return 0;
  634. }
  635. int isp_s_is(struct isp_ic_dev *dev)
  636. {
  637. struct isp_is_context is = *(&dev->is);
  638. u32 isp_is_ctrl;
  639. u32 isp_is_displace;
  640. u32 isp_ctrl;
  641. isp_info("enter %s\n", __func__);
  642. isp_is_ctrl = isp_read_reg(dev, REG_ADDR(isp_is_ctrl));
  643. if (!is.enable) {
  644. REG_SET_SLICE(isp_is_ctrl, MRV_IS_IS_EN, 0);
  645. isp_write_reg(dev, REG_ADDR(isp_is_ctrl), isp_is_ctrl);
  646. return 0;
  647. }
  648. REG_SET_SLICE(isp_is_ctrl, MRV_IS_IS_EN, 1);
  649. isp_write_reg(dev, REG_ADDR(isp_is_h_offs), is.window.x);
  650. isp_write_reg(dev, REG_ADDR(isp_is_v_offs), is.window.y);
  651. isp_write_reg(dev, REG_ADDR(isp_is_h_size), is.window.width);
  652. isp_write_reg(dev, REG_ADDR(isp_is_v_size), is.window.height);
  653. isp_write_reg(dev, REG_ADDR(isp_is_recenter),
  654. is.recenter & MRV_IS_IS_RECENTER_MASK);
  655. isp_write_reg(dev, REG_ADDR(isp_is_max_dx), is.max_dx);
  656. isp_write_reg(dev, REG_ADDR(isp_is_max_dy), is.max_dy);
  657. isp_is_displace = isp_read_reg(dev, REG_ADDR(isp_is_displace));
  658. REG_SET_SLICE(isp_is_displace, MRV_IS_DX, is.displace_x);
  659. REG_SET_SLICE(isp_is_displace, MRV_IS_DY, is.displace_y);
  660. isp_write_reg(dev, REG_ADDR(isp_is_displace), isp_is_displace);
  661. isp_write_reg(dev, REG_ADDR(isp_is_ctrl), isp_is_ctrl);
  662. if (is.update) {
  663. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  664. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  665. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  666. is.update = false;
  667. }
  668. isp_info("exit %s\n", __func__);
  669. return 0;
  670. }
  671. int isp_s_raw_is(struct isp_ic_dev *dev)
  672. {
  673. #ifndef ISP_RAWIS
  674. //isp_err("unsupported funciton: %s\n", __func__);
  675. return -EINVAL;
  676. #else
  677. struct isp_is_context rawis = *(&dev->rawis);
  678. u32 isp_raw_is_ctrl;
  679. u32 isp_raw_is_displace;
  680. // u32 isp_ctrl;
  681. isp_info("enter %s\n", __func__);
  682. isp_raw_is_ctrl = isp_read_reg(dev, REG_ADDR(isp_raw_is_ctrl));
  683. if (!rawis.enable) {
  684. isp_write_reg(dev, REG_ADDR(isp_raw_is_h_size),
  685. rawis.window.width);
  686. isp_write_reg(dev, REG_ADDR(isp_raw_is_v_size),
  687. rawis.window.height);
  688. REG_SET_SLICE(isp_raw_is_ctrl, MRV_ISP_RAW_IS_EN, 0);
  689. isp_write_reg(dev, REG_ADDR(isp_raw_is_ctrl), isp_raw_is_ctrl);
  690. return 0;
  691. }
  692. REG_SET_SLICE(isp_raw_is_ctrl, MRV_ISP_RAW_IS_EN, 1);
  693. isp_write_reg(dev, REG_ADDR(isp_raw_is_h_offs), rawis.window.x);
  694. isp_write_reg(dev, REG_ADDR(isp_raw_is_v_offs), rawis.window.y);
  695. isp_write_reg(dev, REG_ADDR(isp_raw_is_h_size), rawis.window.width);
  696. isp_write_reg(dev, REG_ADDR(isp_raw_is_v_size), rawis.window.height);
  697. isp_write_reg(dev, REG_ADDR(isp_raw_is_recenter),
  698. rawis.recenter & MRV_IS_IS_RECENTER_MASK);
  699. isp_write_reg(dev, REG_ADDR(isp_raw_is_max_dx), rawis.max_dx);
  700. isp_write_reg(dev, REG_ADDR(isp_raw_is_max_dy), rawis.max_dy);
  701. isp_raw_is_displace = isp_read_reg(dev, REG_ADDR(isp_raw_is_displace));
  702. REG_SET_SLICE(isp_raw_is_displace, MRV_ISP_RAW_IS_DX, rawis.displace_x);
  703. REG_SET_SLICE(isp_raw_is_displace, MRV_ISP_RAW_IS_DY, rawis.displace_y);
  704. isp_write_reg(dev, REG_ADDR(isp_raw_is_displace), isp_raw_is_displace);
  705. isp_write_reg(dev, REG_ADDR(isp_raw_is_ctrl), isp_raw_is_ctrl);
  706. /*dont update the configuration at the sub module function*/
  707. #if 0
  708. if (rawis.update) {
  709. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  710. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1);
  711. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  712. rawis.update = false;
  713. }
  714. #endif
  715. return 0;
  716. #endif
  717. }
  718. int isp_s_cnr(struct isp_ic_dev *dev)
  719. {
  720. struct isp_cnr_context *cnr = &dev->cnr;
  721. u32 isp_ctrl;
  722. isp_info("enter %s\n", __func__);
  723. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  724. if (!cnr->enable) {
  725. REG_SET_SLICE(isp_ctrl, MRV_ISP_CNR_EN, 0);
  726. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  727. return 0;
  728. }
  729. REG_SET_SLICE(isp_ctrl, MRV_ISP_CNR_EN, 1);
  730. isp_write_reg(dev, REG_ADDR(isp_cnr_linesize), cnr->line_width);
  731. isp_write_reg(dev, REG_ADDR(isp_cnr_threshold_c1), cnr->threshold_1);
  732. isp_write_reg(dev, REG_ADDR(isp_cnr_threshold_c2), cnr->threshold_2);
  733. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  734. isp_info("exit %s\n", __func__);
  735. return 0;
  736. }
  737. static void isp_test_bt(struct isp_ic_dev *dev)
  738. {
  739. isp_write_reg(dev, 0x00000010, 0x00019f7b);
  740. isp_write_reg(dev, 0x00000014, 0x00020000);
  741. isp_write_reg(dev, 0x00001200, 0x00000000);
  742. isp_write_reg(dev, 0x00001204, 0x01e00280);
  743. isp_write_reg(dev, 0x00001208, 0x01e00280);
  744. isp_write_reg(dev, 0x00001308, 0x6ce60608);
  745. isp_write_reg(dev, 0x00001314, 0x000008c4);
  746. isp_write_reg(dev, 0x00001318, 0x00000001);
  747. isp_write_reg(dev, 0x0000131c, 0x03a2013b);
  748. isp_write_reg(dev, 0x00001320, 0x00000000);
  749. isp_write_reg(dev, 0x00001324, 0xc0000000);
  750. isp_write_reg(dev, 0x00001328, 0x0004B000);
  751. isp_write_reg(dev, 0x0000132c, 0x00000000);
  752. isp_write_reg(dev, 0x00001330, 0x00000280);
  753. isp_write_reg(dev, 0x00001334, 0x00000280);
  754. isp_write_reg(dev, 0x00001338, 0x000001e0);
  755. isp_write_reg(dev, 0x0000133c, 0x0004B000);
  756. isp_write_reg(dev, 0x00001340, 0xc0040000);
  757. isp_write_reg(dev, 0x00001344, 0x0004B000);
  758. isp_write_reg(dev, 0x000016c0, 0x07ffffff);
  759. isp_write_reg(dev, 0x000005bc, 0x00000003);
  760. isp_write_reg(dev, 0x000016c4, 0x052c4e39);
  761. isp_write_reg(dev, 0x00000404, 0x00d00018);
  762. isp_write_reg(dev, 0x00000410, 0x00000280);
  763. isp_write_reg(dev, 0x00000414, 0x000001e0);
  764. isp_write_reg(dev, 0x00000538, 0x01000100);
  765. isp_write_reg(dev, 0x0000053c, 0x02270220);
  766. isp_write_reg(dev, 0x0000059c, 0x00000280);
  767. isp_write_reg(dev, 0x000005a0, 0x000001e0);
  768. isp_write_reg(dev, 0x00002310, 0x00000280);
  769. isp_write_reg(dev, 0x00002314, 0x000001e0);
  770. isp_write_reg(dev, 0x0000295c, 0x00000070);
  771. isp_write_reg(dev, 0x00003e00, 0x040128be);
  772. isp_write_reg(dev, 0x00003e04, 0x00000000);
  773. isp_write_reg(dev, 0x00003e08, 0x00001f08);
  774. isp_write_reg(dev, 0x00003e0c, 0x200003ff);
  775. isp_write_reg(dev, 0x00003e10, 0x0c968628);
  776. isp_write_reg(dev, 0x00003e14, 0x00008008);
  777. isp_write_reg(dev, 0x00003e18, 0x007d07d0);
  778. isp_write_reg(dev, 0x00003e1c, 0x301a3012);
  779. isp_write_reg(dev, 0x00003e20, 0x04010000);
  780. isp_write_reg(dev, 0x00003e24, 0x22018000);
  781. isp_write_reg(dev, 0x00003e28, 0x00020000);
  782. isp_write_reg(dev, 0x00003e2c, 0x0210210a);
  783. isp_write_reg(dev, 0x00003e30, 0x00102102);
  784. isp_write_reg(dev, 0x00003e34, 0x0000388c);
  785. isp_write_reg(dev, 0x00003e38, 0x00000000);
  786. isp_write_reg(dev, 0x00003e3c, 0x00000000);
  787. isp_write_reg(dev, 0x00003e40, 0x00000000);
  788. isp_write_reg(dev, 0x00003e44, 0x00000001);
  789. isp_write_reg(dev, 0x00003e48, 0x10001000);
  790. isp_write_reg(dev, 0x00003e4c, 0x00000000);
  791. isp_write_reg(dev, 0x00003e50, 0x00000000);
  792. isp_write_reg(dev, 0x00003e54, 0x00000000);
  793. isp_write_reg(dev, 0x00003e58, 0x00080010);
  794. isp_write_reg(dev, 0x00003e5c, 0x00080010);
  795. isp_write_reg(dev, 0x00003e60, 0x01300280);
  796. isp_write_reg(dev, 0x00000018, 0x00001000);
  797. isp_write_reg(dev, 0x00001200, 0x00000001); //why
  798. isp_write_reg(dev, 0x00000418, 0x00000001);
  799. isp_write_reg(dev, 0x00000400, 0x80100686);
  800. isp_write_reg(dev, 0x00000400, 0x80100097);
  801. isp_write_reg(dev, 0x00001300, 0x00000001);
  802. isp_write_reg(dev, 0x00001310, 0x00000038);
  803. isp_write_reg(dev, 0x000014e4, 0x00000238);
  804. isp_write_reg(dev, 0x00001600, 0x0000005c);
  805. isp_write_reg(dev, 0x00000704, 0x00c00222);
  806. isp_write_reg(dev, 0x00000708, 0x00a001e0);
  807. isp_write_reg(dev, 0x0000070c, 0x000a4023);
  808. isp_write_reg(dev, 0x00000710, 0x000a401e);
  809. isp_write_reg(dev, 0x00000714, 0x000b8001);
  810. isp_write_reg(dev, 0x00000718, 0x003540a0);
  811. isp_write_reg(dev, 0x0000071c, 0x00000050);
  812. isp_write_reg(dev, 0x00000720, 0x3aca095b);
  813. isp_write_reg(dev, 0x00000700, 0x00000c42);
  814. isp_info("end %s\n", __func__);
  815. }
  816. int isp_start_stream(struct isp_ic_dev *dev, u32 numFrames)
  817. {
  818. u32 isp_imsc, isp_ctrl;
  819. isp_info("enter %s\n", __func__);
  820. #ifdef ISP_PDAF
  821. isp_write_reg(dev, 0x5d00, 0x1);
  822. #endif
  823. isp_write_reg(dev, REG_ADDR(isp_sh_ctrl), 0x10);
  824. isp_write_reg(dev, REG_ADDR(isp_acq_nr_frames),
  825. (MRV_ISP_ACQ_NR_FRAMES_MASK & numFrames));
  826. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  827. isp_imsc |=
  828. (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK |
  829. MRV_ISP_IMSC_FRAME_IN_MASK | MRV_ISP_IMSC_PIC_SIZE_ERR_MASK | MRV_ISP_IMSC_FLASH_ON_MASK | MRV_ISP_IMSC_FLASH_OFF_MASK |
  830. MRV_ISP_IMSC_DATA_LOSS_MASK | MRV_ISP_IMSC_SHUTTER_OFF_MASK | MRV_ISP_MIS_VSM_END_MASK);
  831. /* isp_imsc |= (MRV_ISP_IMSC_FRAME_MASK | MRV_ISP_IMSC_DATA_LOSS_MASK | MRV_ISP_IMSC_FRAME_IN_MASK); */
  832. isp_write_reg(dev, REG_ADDR(isp_icr), 0xFFFFFFFF);
  833. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  834. isp_write_reg(dev, 0x00001320, 1);
  835. isp_write_reg(dev, 0x00001610, 1);
  836. #if 0/*add by shenwuyi for live sensor*/
  837. isp_write_reg(dev, 0x00002200, 0x00000000); //disable lsc
  838. isp_write_reg(dev, 0x000005bc, 0x00000001); //irq_enable
  839. isp_write_reg(dev, 0x00000538, 0x01000100); //awb_gain_gr
  840. isp_write_reg(dev, 0x0000053c, 0x02270220); //awb_gain_gc
  841. #endif
  842. /*isp_test_bt(dev);*/
  843. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  844. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 1);
  845. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 1);
  846. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  847. /*Set lsc tbl after isp enable*/
  848. if (dev->update_lsc_tbl) {
  849. isp_s_lsc_tbl(dev);
  850. dev->update_lsc_tbl = false;
  851. }
  852. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  853. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1);
  854. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  855. isp_info("exit %s\n", __func__);
  856. return 0;
  857. }
  858. int isp_stop_stream(struct isp_ic_dev *dev)
  859. {
  860. isp_info("enter %s\n", __func__);
  861. isp_write_reg(dev, REG_ADDR(isp_imsc), 0);
  862. isp_disable(dev);
  863. isp_info("exit %s\n", __func__);
  864. return 0;
  865. }
  866. void ry_force_stop(struct isp_ic_dev *dev)
  867. {
  868. pr_info("enter %s\n", __func__);
  869. isp_disable(dev);
  870. mdelay(40);
  871. isp_mi_stop(dev);
  872. isp_stop_stream(dev);
  873. isp_reset(dev);
  874. pr_info("exit %s\n", __func__);
  875. return;
  876. }
  877. int isp_s_cc(struct isp_ic_dev *dev)
  878. {
  879. struct isp_cc_context *cc = &dev->cc;
  880. u32 isp_ctrl, addr;
  881. int i;
  882. isp_info("enter %s\n", __func__);
  883. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  884. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CSM_Y_RANGE, cc->conv_range_y_full);
  885. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CSM_C_RANGE, cc->conv_range_c_full);
  886. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  887. if (cc->update_curve) {
  888. addr = REG_ADDR(isp_cc_coeff_0);
  889. for (i = 0; i < 9; i++) {
  890. isp_write_reg(dev, addr + i * 4,
  891. MRV_ISP_CC_COEFF_0_MASK & cc->lCoeff[i]);
  892. }
  893. }
  894. isp_info("exit %s\n", __func__);
  895. return 0;
  896. }
  897. int isp_s_xtalk(struct isp_ic_dev *dev)
  898. {
  899. struct isp_xtalk_context xtalk = *(&dev->xtalk);
  900. int i;
  901. /* isp_info("enter %s\n", __func__); */
  902. for (i = 0; i < 9; i++) {
  903. #ifdef ISP_CTM_0507 // Coefficient for cross talk matrix.Use bit 11,Values are 12-bit signed fixed-point numbers with 5 bit integer and 7 bit fractional part, ranging from -16 (0x800) to +15.992 (0x7FF).
  904. isp_write_reg(dev, REG_ADDR(cross_talk_coef_block_arr[i]),
  905. MRV_ISP_CT_COEFF_MASK & (xtalk.lCoeff[i] << 1));
  906. #else // Coefficient for cross talk matrix.Values are 11-bit signed fixed-point numbers with 4 bit integer and 7 bit fractional part, ranging from -8 (0x400) to +7.992 (0x3FF).
  907. isp_write_reg(dev, REG_ADDR(cross_talk_coef_block_arr[i]),
  908. MRV_ISP_CT_COEFF_MASK & xtalk.lCoeff[i]);
  909. #endif
  910. }
  911. isp_write_reg(dev, REG_ADDR(isp_ct_offset_r),
  912. (MRV_ISP_CT_OFFSET_R_MASK & xtalk.r));
  913. isp_write_reg(dev, REG_ADDR(isp_ct_offset_g),
  914. (MRV_ISP_CT_OFFSET_G_MASK & xtalk.g));
  915. isp_write_reg(dev, REG_ADDR(isp_ct_offset_b),
  916. (MRV_ISP_CT_OFFSET_B_MASK & xtalk.b));
  917. return 0;
  918. }
  919. int isp_enable_wb(struct isp_ic_dev *dev, bool bEnable)
  920. {
  921. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  922. isp_info("enter %s\n", __func__);
  923. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_AWB_ENABLE, bEnable);
  924. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  925. isp_info("exit %s\n", __func__);
  926. return 0;
  927. }
  928. int isp_enable_gamma_out(struct isp_ic_dev *dev, bool bEnable)
  929. {
  930. u32 isp_ctrl;
  931. struct isp_gamma_out_context *gamma = &dev->gamma_out;
  932. isp_info("enter %s\n", __func__);
  933. gamma->enableGamma = bEnable;
  934. if(gamma->changed || !is_isp_enable(dev))
  935. {
  936. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  937. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_OUT_ENABLE, bEnable);
  938. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  939. gamma->changed = false;
  940. } else {
  941. gamma->changed = true;
  942. }
  943. isp_info("exit %s\n", __func__);
  944. return 0;
  945. }
  946. int isp_s_gamma_out(struct isp_ic_dev *dev)
  947. {
  948. u32 isp_gamma_out_mode;
  949. int i;
  950. u32 isp_ctrl;
  951. struct isp_gamma_out_context *gamma = &dev->gamma_out;
  952. if(gamma->changed || !is_isp_enable(dev)) {
  953. isp_gamma_out_mode = isp_read_reg(dev, REG_ADDR(isp_gamma_out_mode));
  954. REG_SET_SLICE(isp_gamma_out_mode, MRV_ISP_EQU_SEGM, gamma->mode);
  955. isp_write_reg(dev, REG_ADDR(isp_gamma_out_mode), isp_gamma_out_mode);
  956. for (i = 0; i < 17; i++) {
  957. isp_write_reg(dev, REG_ADDR(gamma_out_y_block_arr[i]),
  958. MRV_ISP_ISP_GAMMA_OUT_Y_MASK & gamma->curve[i]);
  959. }
  960. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  961. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_OUT_ENABLE, gamma->enableGamma);
  962. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  963. gamma->changed = false;
  964. } else {
  965. gamma->changed = true;
  966. }
  967. return 0;
  968. }
  969. int isp_s_lsc_tbl(struct isp_ic_dev *dev)
  970. {
  971. int i, n;
  972. u32 isp_ctrl;
  973. u32 sram_addr;
  974. u32 isp_lsc_status;
  975. struct isp_lsc_context *lsc = (&dev->lsc);
  976. isp_debug("enter %s\n", __func__);
  977. /*need to set tbl after isp_ctrl enable In ISP8000NANO_V1802*/
  978. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  979. /* Enable isp to enable ram clock for write correct table to ram. */
  980. if (!(isp_ctrl & 0x01)) {
  981. dev->update_lsc_tbl = true;
  982. return 0;
  983. }
  984. isp_lsc_status = isp_read_reg(dev, REG_ADDR(isp_lsc_status));
  985. sram_addr = (isp_lsc_status & 0x2U) ? 0U : 153U;
  986. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_addr), sram_addr);
  987. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_addr), sram_addr);
  988. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_addr), sram_addr);
  989. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_addr), sram_addr);
  990. #ifdef ISP_LSC_V2
  991. for (n = 0; n < ((CAMERIC_MAX_LSC_SECTORS + 1) * (CAMERIC_MAX_LSC_SECTORS + 1)); n += CAMERIC_MAX_LSC_SECTORS + 1) {
  992. for (i = 0; i < (CAMERIC_MAX_LSC_SECTORS); i += 2) {
  993. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), (lsc->r[n + i] & 0xFFF) | ((lsc->r[n + i + 1] & 0xFFF) << 12) | ((lsc->r[n + i] >> 12) << 24) | ((lsc->r[n + i + 1] >> 12) << 28));
  994. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), (lsc->gr[n + i] & 0xFFF) | ((lsc->gr[n + i + 1] & 0xFFF) << 12) | ((lsc->gr[n + i] >> 12) << 24) | ((lsc->gr[n + i + 1] >> 12) << 28));
  995. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), (lsc->gb[n + i] & 0xFFF) | ((lsc->gb[n + i + 1] & 0xFFF) << 12) | ((lsc->gb[n + i] >> 12) << 24) | ((lsc->gb[n + i + 1] >> 12) << 28));
  996. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), (lsc->b[n + i] & 0xFFF) | ((lsc->b[n + i + 1] & 0xFFF) << 12) | ((lsc->b[n + i] >> 12) << 24) | ((lsc->b[n + i + 1] >> 12) << 28));
  997. }
  998. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), (lsc->r[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->r[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  999. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), (lsc->gr[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->gr[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  1000. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), (lsc->gb[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->gb[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  1001. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), (lsc->b[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->b[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  1002. }
  1003. #else
  1004. for (n = 0;
  1005. n <
  1006. ((CAMERIC_MAX_LSC_SECTORS + 1) * (CAMERIC_MAX_LSC_SECTORS + 1));
  1007. n += CAMERIC_MAX_LSC_SECTORS + 1) {
  1008. /* 17 sectors with 2 values in one DWORD = 9 DWORDs (8 steps + 1 outside loop) */
  1009. for (i = 0; i < (CAMERIC_MAX_LSC_SECTORS); i += 2) {
  1010. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data),
  1011. lsc->r[n +
  1012. i] | (lsc->r[n + i + 1] << 12));
  1013. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data),
  1014. lsc->gr[n +
  1015. i] | (lsc->gr[n + i + 1] << 12));
  1016. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data),
  1017. lsc->gb[n +
  1018. i] | (lsc->gb[n + i + 1] << 12));
  1019. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data),
  1020. lsc->b[n +
  1021. i] | (lsc->b[n + i + 1] << 12));
  1022. }
  1023. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data),
  1024. lsc->r[n + CAMERIC_MAX_LSC_SECTORS]);
  1025. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data),
  1026. lsc->gr[n + CAMERIC_MAX_LSC_SECTORS]);
  1027. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data),
  1028. lsc->gb[n + CAMERIC_MAX_LSC_SECTORS]);
  1029. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data),
  1030. lsc->b[n + CAMERIC_MAX_LSC_SECTORS]);
  1031. }
  1032. #endif
  1033. isp_write_reg(dev, REG_ADDR(isp_lsc_table_sel),
  1034. (isp_lsc_status & 0x2U) ? 0U : 1U);
  1035. isp_info("exit %s\n", __func__);
  1036. return 0;
  1037. }
  1038. int isp_s_lsc_sec(struct isp_ic_dev *dev)
  1039. {
  1040. int i;
  1041. struct isp_lsc_context *lsc = (&dev->lsc);
  1042. /* isp_info("enter %s\n", __func__); */
  1043. for (i = 0; i < CAEMRIC_GRAD_TBL_SIZE; i += 2) {
  1044. isp_write_reg(dev, REG_ADDR(isp_lsc_xsize_01) + i * 2,
  1045. (lsc->x_size[i] & MRV_LSC_Y_SECT_SIZE_0_MASK) |
  1046. ((lsc->x_size[i + 1]
  1047. << MRV_LSC_X_SECT_SIZE_1_SHIFT)
  1048. & MRV_LSC_X_SECT_SIZE_1_MASK));
  1049. isp_write_reg(dev, REG_ADDR(isp_lsc_ysize_01) + i * 2,
  1050. (lsc->y_size[i] & MRV_LSC_Y_SECT_SIZE_0_MASK) |
  1051. ((lsc->y_size[i + 1]
  1052. << MRV_LSC_Y_SECT_SIZE_1_SHIFT)
  1053. & MRV_LSC_Y_SECT_SIZE_1_MASK));
  1054. isp_write_reg(dev, REG_ADDR(isp_lsc_xgrad_01) + i * 2,
  1055. (lsc->x_grad[i] & MRV_LSC_XGRAD_0_MASK) |
  1056. ((lsc->x_grad[i + 1]
  1057. << MRV_LSC_XGRAD_1_SHIFT)
  1058. & MRV_LSC_XGRAD_1_MASK));
  1059. isp_write_reg(dev, REG_ADDR(isp_lsc_ygrad_01) + i * 2,
  1060. (lsc->y_grad[i] & MRV_LSC_YGRAD_0_MASK) |
  1061. ((lsc->y_grad[i + 1]
  1062. << MRV_LSC_YGRAD_1_SHIFT)
  1063. & MRV_LSC_YGRAD_1_MASK));
  1064. }
  1065. return 0;
  1066. }
  1067. int isp_ioc_read_mis(struct isp_ic_dev *dev, void __user *args)
  1068. {
  1069. isp_mis_list_t* pCList = &dev->circle_list;
  1070. isp_mis_t mis_data;
  1071. u64 ary[2];
  1072. int ret = -1;
  1073. ret = isp_irq_read_circle_queue(&mis_data, pCList);
  1074. if (ret < 0) {
  1075. /*isp_info("%s can not dequeue mis data\n", __func__);*/
  1076. return ret;
  1077. }
  1078. /*isp_info("%s irq src %d val 0x%lx\n", __func__, mis_data.irq_src, mis_data.val);*/
  1079. ary[0] = mis_data.irq_src;
  1080. ary[1] = mis_data.val;
  1081. viv_check_retval(copy_to_user(args, ary, sizeof( ary)));
  1082. return 0;
  1083. }
  1084. static int isp_ioc_read_reg(struct isp_ic_dev *dev, void __user * args)
  1085. {
  1086. struct isp_reg_t reg;
  1087. viv_check_retval(copy_from_user(&reg, args, sizeof(reg)));
  1088. reg.val = isp_read_reg(dev, reg.offset);
  1089. viv_check_retval(copy_to_user(args, &reg, sizeof(reg)));
  1090. return 0;
  1091. }
  1092. static int isp_ioc_write_reg(struct isp_ic_dev *dev, void __user *args)
  1093. {
  1094. struct isp_reg_t reg;
  1095. viv_check_retval((copy_from_user(&reg, args, sizeof(reg))));
  1096. isp_write_reg(dev, reg.offset, reg.val);
  1097. return 0;
  1098. }
  1099. int isp_ioc_disable_isp_off(struct isp_ic_dev *dev, void __user *args)
  1100. {
  1101. u32 isp_imsc;
  1102. isp_info("enter %s\n", __func__);
  1103. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1104. isp_imsc &= ~MRV_ISP_IMSC_ISP_OFF_MASK;
  1105. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  1106. isp_info("exit %s\n", __func__);
  1107. return 0;
  1108. }
  1109. int isp_g_awbmean(struct isp_ic_dev *dev, struct isp_awb_mean *mean)
  1110. {
  1111. u32 reg = isp_read_reg(dev, REG_ADDR(isp_awb_mean));
  1112. /* isp_info("enter %s\n", __func__); */
  1113. mean->g = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_Y__G);
  1114. mean->b = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_CB__B);
  1115. mean->r = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_CR__R);
  1116. mean->no_white_count = isp_read_reg(dev, REG_ADDR(isp_awb_white_cnt));
  1117. return 0;
  1118. }
  1119. int isp_s_ee(struct isp_ic_dev *dev)
  1120. {
  1121. #ifndef ISP_EE_RY
  1122. //isp_err("unsupported function: %s\n", __func__);
  1123. return -EINVAL;
  1124. #else
  1125. struct isp_ee_context *ee = &dev->ee;
  1126. u32 isp_ee_ctrl = isp_read_reg(dev, REG_ADDR(isp_ee_ctrl));
  1127. u32 gain = 0;
  1128. isp_info("enter %s\n", __func__);
  1129. if (!ee->enable) {
  1130. isp_write_reg(dev, REG_ADDR(isp_ee_ctrl),
  1131. isp_ee_ctrl & ~EE_CTRL_ENABLE_MASK);
  1132. return 0;
  1133. }
  1134. REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_INPUT_SEL, ee->input_sel);
  1135. REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_SOURCE_STRENGTH, ee->src_strength);
  1136. REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_STRENGTH, ee->strength);
  1137. REG_SET_SLICE(gain, EE_UV_GAIN, ee->uv_gain);
  1138. REG_SET_SLICE(gain, EE_EDGE_GAIN, ee->edge_gain);
  1139. isp_write_reg(dev, REG_ADDR(isp_ee_y_gain), ee->y_gain);
  1140. isp_write_reg(dev, REG_ADDR(isp_ee_uv_gain), gain);
  1141. isp_write_reg(dev, REG_ADDR(isp_ee_ctrl),
  1142. isp_ee_ctrl | EE_CTRL_ENABLE_MASK);
  1143. isp_info("exit %s\n", __func__);
  1144. return 0;
  1145. #endif
  1146. }
  1147. int isp_s_exp(struct isp_ic_dev *dev)
  1148. {
  1149. struct isp_exp_context *exp = &dev->exp;
  1150. u32 isp_exp_ctrl = isp_read_reg(dev, REG_ADDR(isp_exp_ctrl));
  1151. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1152. isp_info("enter %s\n", __func__);
  1153. if (!exp->enable) {
  1154. REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_START, 0);
  1155. isp_write_reg(dev, REG_ADDR(isp_exp_ctrl), isp_exp_ctrl);
  1156. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1157. isp_imsc & ~MRV_ISP_IMSC_EXP_END_MASK);
  1158. return 0;
  1159. }
  1160. isp_write_reg(dev, REG_ADDR(isp_exp_h_offset),
  1161. (MRV_AE_ISP_EXP_H_OFFSET_MASK & exp->window.x));
  1162. isp_write_reg(dev, REG_ADDR(isp_exp_v_offset),
  1163. (MRV_AE_ISP_EXP_V_OFFSET_MASK & exp->window.y));
  1164. isp_write_reg(dev, REG_ADDR(isp_exp_h_size),
  1165. (MRV_AE_ISP_EXP_H_SIZE_MASK & exp->window.width));
  1166. isp_write_reg(dev, REG_ADDR(isp_exp_v_size),
  1167. (MRV_AE_ISP_EXP_V_SIZE_MASK & exp->window.height));
  1168. #ifdef ISP_AE_SHADOW_RY
  1169. isp_write_reg(dev, REG_ADDR(isp_exp_h_offset_shd),
  1170. (MRV_AE_ISP_EXP_H_OFFSET_MASK & exp->window.x));
  1171. isp_write_reg(dev, REG_ADDR(isp_exp_v_offset_shd),
  1172. (MRV_AE_ISP_EXP_V_OFFSET_MASK & exp->window.y));
  1173. isp_write_reg(dev, REG_ADDR(isp_exp_h_size_shd),
  1174. (MRV_AE_ISP_EXP_H_SIZE_MASK & exp->window.width));
  1175. isp_write_reg(dev, REG_ADDR(isp_exp_v_size_shd),
  1176. (MRV_AE_ISP_EXP_V_SIZE_MASK & exp->window.height));
  1177. #endif
  1178. REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_MEAS_MODE, exp->mode);
  1179. REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_START, 1);
  1180. isp_write_reg(dev, REG_ADDR(isp_exp_ctrl), isp_exp_ctrl);
  1181. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1182. isp_imsc | MRV_ISP_IMSC_EXP_END_MASK);
  1183. isp_info("exit %s\n", __func__);
  1184. return 0;
  1185. }
  1186. int isp_s_hdrexp(struct isp_ic_dev *dev)
  1187. {
  1188. struct isp_exp_context *hdrexp = &dev->hdrexp;
  1189. u32 isp_hdr_exp_conf = isp_read_reg(dev, REG_ADDR(isp_hdr_exp_conf));
  1190. u32 isp_stitching_imsc = isp_read_reg(dev, REG_ADDR(isp_stitching_imsc));
  1191. isp_info("enter %s\n", __func__);
  1192. if (!dev->hdrexp.enable) {
  1193. isp_info("%s, hdr disabled\n",__func__);
  1194. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_START, 0);
  1195. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_conf), isp_hdr_exp_conf);
  1196. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc & ~0x38);
  1197. return 0;
  1198. }
  1199. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_h_offset),
  1200. (MRV_ISP_HDR_EXP_H_OFFSET_MASK & hdrexp->window.x));
  1201. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_v_offset),
  1202. (MRV_ISP_HDR_EXP_V_OFFSET_MASK & hdrexp->window.y));
  1203. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_h_size),
  1204. (MRV_ISP_HDR_EXP_H_SIZE_MASK & hdrexp->window.width));
  1205. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_v_size),
  1206. (MRV_ISP_HDR_EXP_V_SIZE_MASK & hdrexp->window.height));
  1207. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_MEAS_MODE, hdrexp->mode);
  1208. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_SRC_SEL, 1); //hardware only support 1
  1209. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_START, 1);
  1210. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_conf), isp_hdr_exp_conf);
  1211. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc | 0x38);
  1212. return 0;
  1213. }
  1214. int isp_g_expmean(struct isp_ic_dev *dev, u8 *mean)
  1215. {
  1216. int i = 0;
  1217. /* isp_info("enter %s\n", __func__); */
  1218. if (!dev || !mean)
  1219. return -EINVAL;
  1220. for (; i < 25; i++) {
  1221. mean[i] = isp_read_reg(dev, REG_ADDR(isp_exp_mean_00) + i * 4);
  1222. }
  1223. return 0;
  1224. }
  1225. int isp_g_hdrexpmean(struct isp_ic_dev *dev, u8 * mean)
  1226. {
  1227. int i = 0;
  1228. isp_info("enter %s\n", __func__);
  1229. if (!dev || !mean)
  1230. return -EINVAL;
  1231. for (; i < 75; i++) {
  1232. mean[i] = isp_read_reg(dev, REG_ADDR(isp_hdr_exp_statistics[i]));
  1233. }
  1234. return 0;
  1235. }
  1236. #ifdef ISP_HIST256
  1237. #define HIST_BIN_TOTAL 256
  1238. #else
  1239. #define HIST_BIN_TOTAL 16
  1240. #endif
  1241. int isp_s_hist(struct isp_ic_dev *dev)
  1242. {
  1243. struct isp_hist_context *hist = &dev->hist;
  1244. #ifdef ISP_HIST256_RY
  1245. u32 isp_hist256_prop = isp_read_reg(dev, REG_ADDR(isp_hist256_prop));
  1246. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1247. int i;
  1248. if (!hist->enable) {
  1249. REG_SET_SLICE(isp_hist256_prop, MRV_HIST_MODE,
  1250. MRV_HIST_MODE_NONE);
  1251. isp_write_reg(dev, REG_ADDR(isp_hist256_prop),
  1252. isp_hist256_prop);
  1253. //isp_write_reg(dev, REG_ADDR(isp_imsc),
  1254. // isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1255. return 0;
  1256. }
  1257. isp_write_reg(dev, REG_ADDR(isp_hist256_h_offs),
  1258. (MRV_HIST_H_OFFSET_MASK & hist->window.x));
  1259. isp_write_reg(dev, REG_ADDR(isp_hist256_v_offs),
  1260. (MRV_HIST_V_OFFSET_MASK & hist->window.y));
  1261. isp_write_reg(dev, REG_ADDR(isp_hist256_h_size),
  1262. (MRV_HIST_H_SIZE_MASK & hist->window.width));
  1263. isp_write_reg(dev, REG_ADDR(isp_hist256_v_size),
  1264. (MRV_HIST_V_SIZE_MASK & hist->window.height));
  1265. for (i = 0; i < 24; i += 4) {
  1266. isp_write_reg(dev, REG_ADDR(isp_hist256_weight_00to30) + i,
  1267. hist->weight[i +
  1268. 0] | (hist->weight[i +
  1269. 1] << 8) |
  1270. (hist->weight[i + 2] << 16) | (hist->weight[i +
  1271. 3] <<
  1272. 24));
  1273. }
  1274. isp_write_reg(dev, REG_ADDR(isp_hist256_weight_44), hist->weight[24]);
  1275. REG_SET_SLICE(isp_hist256_prop, MRV_HIST_STEPSIZE, hist->step_size);
  1276. REG_SET_SLICE(isp_hist256_prop, MRV_HIST_MODE, hist->mode);
  1277. isp_write_reg(dev, REG_ADDR(isp_hist256_prop), isp_hist256_prop);
  1278. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1279. isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1280. #else
  1281. u32 isp_hist_prop = isp_read_reg(dev, REG_ADDR(isp_hist_prop));
  1282. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1283. int i;
  1284. isp_info("enter %s\n", __func__);
  1285. if (!hist->enable) {
  1286. REG_SET_SLICE(isp_hist_prop, MRV_HIST_MODE, MRV_HIST_MODE_NONE);
  1287. isp_write_reg(dev, REG_ADDR(isp_hist_prop), isp_hist_prop);
  1288. //isp_write_reg(dev, REG_ADDR(isp_imsc),
  1289. // isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1290. return 0;
  1291. }
  1292. isp_write_reg(dev, REG_ADDR(isp_hist_h_offs),
  1293. (MRV_HIST_H_OFFSET_MASK & hist->window.x));
  1294. isp_write_reg(dev, REG_ADDR(isp_hist_v_offs),
  1295. (MRV_HIST_V_OFFSET_MASK & hist->window.y));
  1296. isp_write_reg(dev, REG_ADDR(isp_hist_h_size),
  1297. (MRV_HIST_H_SIZE_MASK & hist->window.width));
  1298. isp_write_reg(dev, REG_ADDR(isp_hist_v_size),
  1299. (MRV_HIST_V_SIZE_MASK & hist->window.height));
  1300. for (i = 0; i < 24; i += 4) {
  1301. isp_write_reg(dev, REG_ADDR(isp_hist_weight_00to30) + i,
  1302. hist->weight[i + 0] |
  1303. (hist->weight[i + 1] << 8) |
  1304. (hist->weight[i + 2] << 16) |
  1305. (hist->weight[i + 3] << 24));
  1306. }
  1307. isp_write_reg(dev, REG_ADDR(isp_hist_weight_44), hist->weight[24]);
  1308. REG_SET_SLICE(isp_hist_prop, MRV_HIST_STEPSIZE, hist->step_size);
  1309. REG_SET_SLICE(isp_hist_prop, MRV_HIST_MODE, hist->mode);
  1310. isp_write_reg(dev, REG_ADDR(isp_hist_prop), isp_hist_prop);
  1311. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1312. isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1313. isp_info("exit %s\n", __func__);
  1314. #endif
  1315. return 0;
  1316. }
  1317. int isp_s_hdrhist(struct isp_ic_dev *dev)
  1318. {
  1319. struct isp_hist_context *hdrhist = &dev->hdrhist;
  1320. u32 isp_hdr_hist_prop = isp_read_reg(dev, REG_ADDR(isp_hdr_hist_prop));
  1321. u32 isp_stitching_imsc = isp_read_reg(dev, REG_ADDR(isp_stitching_imsc));
  1322. isp_info("enter %s\n", __func__);
  1323. if (!dev->hdrhist.enable) {
  1324. isp_info("%s, hdr disable\n", __func__);
  1325. REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_MODE, MRV_HIST_MODE_NONE);
  1326. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_prop), isp_hdr_hist_prop);
  1327. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc),
  1328. isp_stitching_imsc & ~0x1c0);
  1329. return 0;
  1330. }
  1331. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_h_offs),
  1332. (MRV_HIST_H_OFFSET_MASK & hdrhist->window.x));
  1333. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_v_offs),
  1334. (MRV_HIST_V_OFFSET_MASK & hdrhist->window.y));
  1335. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_h_size),
  1336. (MRV_HIST_H_SIZE_MASK & hdrhist->window.width));
  1337. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_v_size),
  1338. (MRV_HIST_V_SIZE_MASK & hdrhist->window.height));
  1339. REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_STEPSIZE, hdrhist->step_size);
  1340. REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_MODE, hdrhist->mode);
  1341. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_prop), isp_hdr_hist_prop);
  1342. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc | 0x1c0);
  1343. return 0;
  1344. }
  1345. int isp_g_histmean(struct isp_ic_dev *dev, u32 *mean)
  1346. {
  1347. int i = 0;
  1348. /* isp_info("enter %s\n", __func__); */
  1349. if (!dev || !mean)
  1350. return -EINVAL;
  1351. #ifdef ISP_HIST256_RY
  1352. for (; i < HIST_BIN_TOTAL; i++) {
  1353. mean[i] = isp_read_reg(dev, REG_ADDR(isp_hist256_bin_n));
  1354. }
  1355. #else
  1356. for (; i < HIST_BIN_TOTAL; i++) {
  1357. mean[i] = isp_read_reg(dev,
  1358. REG_ADDR(histogram_measurement_result_arr[i]));
  1359. }
  1360. #endif
  1361. return 0;
  1362. }
  1363. int isp_g_hdrhistmean(struct isp_ic_dev *dev, u32 * mean)
  1364. {
  1365. int i = 0;
  1366. isp_info("enter %s\n", __func__);
  1367. if (!dev || !mean)
  1368. return -EINVAL;
  1369. // size is fixed 48 now, contain 3 channels
  1370. for (; i < 48; i++) {
  1371. mean[i] = isp_read_reg(dev, REG_ADDR(isp_hdr_hist_statistics[i]));
  1372. }
  1373. return 0;
  1374. }
  1375. int isp_s_hist64(struct isp_ic_dev *dev)
  1376. {
  1377. #ifndef ISP_HIST64_RY
  1378. //pr_err("Not supported hist64 module\n");
  1379. return -1;
  1380. #else
  1381. struct isp_hist64_context *hist64 = &dev->hist64;
  1382. u32 isp64_hist_prop = isp_read_reg(dev, REG_ADDR(isp64_hist_prop));
  1383. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1384. u32 isp64_hist_subsampling = isp_read_reg(dev, REG_ADDR(isp64_hist_subsampling));
  1385. u32 isp64_hist_sample_range = isp_read_reg(dev, REG_ADDR(isp64_hist_sample_range));
  1386. u32 isp64_hist_coeff_r = 0, isp64_hist_coeff_g = 0, isp64_hist_coeff_b = 0;
  1387. int i;
  1388. if (!hist64->enable) {
  1389. REG_SET_SLICE(isp64_hist_prop, MRV_HIST_MODE,
  1390. MRV_HIST_MODE_NONE);
  1391. isp_write_reg(dev, REG_ADDR(isp64_hist_prop),
  1392. isp64_hist_prop);
  1393. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1394. isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1395. //isp_write_reg(dev, REG_ADDR(isp64_hist_ctrl),
  1396. /// hist64->enable & ~MRV_HIST_UPDATE_ENABLE_MASK);
  1397. return 0;
  1398. }
  1399. isp_write_reg(dev, REG_ADDR(isp64_hist_h_offs),
  1400. (MRV_HIST_H_OFFSET_MASK & hist64->window.x));
  1401. isp_write_reg(dev, REG_ADDR(isp64_hist_v_offs),
  1402. (MRV_HIST_V_OFFSET_MASK & hist64->window.y));
  1403. isp_write_reg(dev, REG_ADDR(isp64_hist_h_size),
  1404. (MRV_HIST_H_SIZE_MASK & hist64->window.width));
  1405. isp_write_reg(dev, REG_ADDR(isp64_hist_v_size),
  1406. (MRV_HIST_V_SIZE_MASK & hist64->window.height));
  1407. for (i = 0; i < 24; i += 4) {
  1408. isp_write_reg(dev, REG_ADDR(isp64_hist_weight_00to30) + i,
  1409. hist64->weight[i +
  1410. 0] | (hist64->weight[i +
  1411. 1] << 8) |
  1412. (hist64->weight[i + 2] << 16) | (hist64->weight[i +
  1413. 3] <<
  1414. 24));
  1415. }
  1416. isp_write_reg(dev, REG_ADDR(isp64_hist_weight_44), hist64->weight[24]);
  1417. REG_SET_SLICE(isp64_hist_prop, MRV_HIST_CHANNEL_SELECT, hist64->channel);
  1418. REG_SET_SLICE(isp64_hist_prop, MRV_HIST_MODE, hist64->mode);
  1419. REG_SET_SLICE(isp64_hist_subsampling, MRV_HIST_V_STEPSIZE, hist64->vStepSize);
  1420. REG_SET_SLICE(isp64_hist_subsampling, MRV_HIST_H_STEP_INC, hist64->hStepInc);
  1421. REG_SET_SLICE(isp64_hist_sample_range, MRV_HIST_SAMPLE_OFFSET, hist64->sample_offset);
  1422. REG_SET_SLICE(isp64_hist_sample_range, MRV_HIST_SAMPLE_SHIFT, hist64->sample_shift);
  1423. REG_SET_SLICE(isp64_hist_coeff_r, MRV_HIST_COEFF_R, hist64->r_coeff);
  1424. REG_SET_SLICE(isp64_hist_coeff_g, MRV_HIST_COEFF_G, hist64->g_coeff);
  1425. REG_SET_SLICE(isp64_hist_coeff_b, MRV_HIST_COEFF_B, hist64->b_coeff);
  1426. isp_write_reg(dev, REG_ADDR(isp64_hist_subsampling), isp64_hist_subsampling);
  1427. isp_write_reg(dev, REG_ADDR(isp64_hist_sample_range), isp64_hist_sample_range);
  1428. isp_write_reg(dev, REG_ADDR(isp64_hist_prop), isp64_hist_prop);
  1429. isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_r), isp64_hist_coeff_r);
  1430. isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_g), isp64_hist_coeff_g);
  1431. isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_b), isp64_hist_coeff_b);
  1432. isp_write_reg(dev, REG_ADDR(isp64_hist_ctrl),
  1433. hist64->enable);
  1434. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1435. isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1436. return 0;
  1437. #endif
  1438. }
  1439. #define HIST64_BIN_TOTAL 32
  1440. int isp_g_hist64mean(struct isp_ic_dev *dev, u32 *mean)
  1441. {
  1442. #ifndef ISP_HIST64_RY
  1443. //pr_err("Not supported hist64 module\n");
  1444. return -1;
  1445. #else
  1446. int i = 0;
  1447. isp_info("enter %s\n", __func__);
  1448. if (!dev || !mean)
  1449. return -EINVAL;
  1450. for (; i < HIST64_BIN_TOTAL; i++) {
  1451. mean[i] = isp_read_reg(dev,
  1452. REG_ADDR(isp64_histogram_measurement_result_arr[i]));
  1453. }
  1454. isp_info("exit %s\n", __func__);
  1455. return 0;
  1456. #endif
  1457. }
  1458. int isp_g_hist64_vstart_status(struct isp_ic_dev *dev, u32 *status)
  1459. {
  1460. #ifndef ISP_HIST64_RY
  1461. //pr_err("Not supported hist64 module\n");
  1462. return -1;
  1463. #else
  1464. /* isp_info("enter %s\n", __func__); */
  1465. if (!dev || !status)
  1466. return -EINVAL;
  1467. *status = isp_read_reg(dev, REG_ADDR(isp64_hist_vstart_status));
  1468. return 0;
  1469. #endif
  1470. }
  1471. int isp_update_hist64(struct isp_ic_dev *dev)
  1472. {
  1473. #ifndef ISP_HIST64_RY
  1474. //pr_err("Not supported hist64\n");
  1475. return -1;
  1476. #else
  1477. struct isp_hist64_context* hist64 =&dev->hist64;
  1478. isp_write_reg(dev, REG_ADDR(isp64_hist_forced_upd_start_line),hist64->forced_upd_start_line);
  1479. isp_write_reg(dev, REG_ADDR(isp64_hist_forced_update), hist64->forced_upd);
  1480. return 0;
  1481. #endif
  1482. }
  1483. int isp_s_ge(struct isp_ic_dev *dev)
  1484. {
  1485. #ifndef ISP_GREENEQUILIBRATE
  1486. //isp_err("unsupported function %s\n", __func__);
  1487. return -1;
  1488. #else
  1489. struct isp_ge_context *ge = &dev->ge;
  1490. u32 green_equilibrate_ctrl =
  1491. isp_read_reg(dev, REG_ADDR(green_equilibrate_ctrl));
  1492. u32 green_equilibrate_hcnt_dummy = 0;
  1493. isp_info("enter %s\n", __func__);
  1494. if (!ge->enable) {
  1495. REG_SET_SLICE(green_equilibrate_ctrl,
  1496. ISP_GREEN_EQUILIBTATE_ENABLE, 0);
  1497. isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl),
  1498. green_equilibrate_ctrl);
  1499. return 0;
  1500. }
  1501. REG_SET_SLICE(green_equilibrate_ctrl, ISP_GREEN_EQUILIBTATE_TH,
  1502. ge->threshold);
  1503. REG_SET_SLICE(green_equilibrate_ctrl, ISP_GREEN_EQUILIBTATE_ENABLE, 1);
  1504. REG_SET_SLICE(green_equilibrate_hcnt_dummy,
  1505. ISP_GREEN_EQUILIBTATE_HCNT_DUMMY, ge->h_dummy);
  1506. isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl),
  1507. green_equilibrate_ctrl);
  1508. isp_write_reg(dev, REG_ADDR(green_equilibrate_hcnt_dummy),
  1509. green_equilibrate_hcnt_dummy);
  1510. isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl_shd),
  1511. green_equilibrate_ctrl);
  1512. isp_info("exit %s\n", __func__);
  1513. return 0;
  1514. #endif
  1515. }
  1516. int isp_s_ca(struct isp_ic_dev *dev)
  1517. {
  1518. #ifndef ISP_CA_RY
  1519. //isp_err("unsupported function %s\n", __func__);
  1520. return -1;
  1521. #else
  1522. struct isp_ca_context *ca = &dev->ca;
  1523. u32 isp_curve_ctrl = isp_read_reg(dev, REG_ADDR(isp_curve_ctrl));
  1524. // u32 isp_curve_lut_x_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_x_addr));
  1525. // u32 isp_curve_lut_luma_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_luma_addr));
  1526. // u32 isp_curve_lut_chroma_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_chroma_addr));
  1527. // u32 isp_curve_lut_shift_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_shift_addr));
  1528. int i = 0;
  1529. isp_info("enter %s\n", __func__);
  1530. if (!ca->enable) {
  1531. REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_ENABLE, 0);
  1532. isp_write_reg(dev, REG_ADDR(isp_curve_ctrl), isp_curve_ctrl);
  1533. return 0;
  1534. }
  1535. isp_write_reg(dev, REG_ADDR(isp_curve_lut_x_addr), 0);
  1536. isp_write_reg(dev, REG_ADDR(isp_curve_lut_luma_addr), 0);
  1537. isp_write_reg(dev, REG_ADDR(isp_curve_lut_chroma_addr), 0);
  1538. isp_write_reg(dev, REG_ADDR(isp_curve_lut_shift_addr), 0);
  1539. for (i = 0; i < CA_CURVE_DATA_TABLE_LEN; i++) {
  1540. isp_write_reg(dev, REG_ADDR(isp_curve_lut_x_write_data),
  1541. dev->ca.lut_x[i]);
  1542. isp_write_reg(dev, REG_ADDR(isp_curve_lut_luma_write_data),
  1543. dev->ca.lut_luma[i]);
  1544. isp_write_reg(dev, REG_ADDR(isp_curve_lut_chroma_write_data),
  1545. dev->ca.lut_chroma[i]);
  1546. isp_write_reg(dev, REG_ADDR(isp_curve_lut_shift_write_data),
  1547. dev->ca.lut_shift[i]);
  1548. }
  1549. REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_MODE, dev->ca.mode);
  1550. REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_ENABLE, 1);
  1551. isp_write_reg(dev, REG_ADDR(isp_curve_ctrl), isp_curve_ctrl);
  1552. isp_info("exit %s\n", __func__);
  1553. return 0;
  1554. #endif
  1555. }
  1556. int isp_s_dpcc(struct isp_ic_dev *dev)
  1557. {
  1558. struct isp_dpcc_context *dpcc = &dev->dpcc;
  1559. const u32 reg_gap = 20;
  1560. int i;
  1561. u32 isp_dpcc_mode = isp_read_reg(dev, REG_ADDR(isp_dpcc_mode));
  1562. isp_info("enter %s\n", __func__);
  1563. if (!dpcc->enable) {
  1564. REG_SET_SLICE(isp_dpcc_mode, MRV_DPCC_ISP_DPCC_ENABLE, 0);
  1565. } else {
  1566. REG_SET_SLICE(isp_dpcc_mode, MRV_DPCC_ISP_DPCC_ENABLE, 1);
  1567. }
  1568. isp_write_reg(dev, REG_ADDR(isp_dpcc_mode), dpcc->mode);
  1569. isp_write_reg(dev, REG_ADDR(isp_dpcc_output_mode), dpcc->outmode);
  1570. isp_write_reg(dev, REG_ADDR(isp_dpcc_set_use), dpcc->set_use);
  1571. for (i = 0; i < 3; i++) {
  1572. isp_write_reg(dev, REG_ADDR(isp_dpcc_methods_set_1) + i * 4,
  1573. 0x1FFF & dpcc->methods_set[i]);
  1574. isp_write_reg(dev,
  1575. REG_ADDR(isp_dpcc_line_thresh_1) + i * reg_gap,
  1576. 0xFFFF & dpcc->params[i].line_thresh);
  1577. isp_write_reg(dev,
  1578. REG_ADDR(isp_dpcc_line_mad_fac_1) + i * reg_gap,
  1579. 0x3F3F & dpcc->params[i].line_mad_fac);
  1580. isp_write_reg(dev, REG_ADDR(isp_dpcc_pg_fac_1) + i * reg_gap,
  1581. 0x3F3F & dpcc->params[i].pg_fac);
  1582. isp_write_reg(dev,
  1583. REG_ADDR(isp_dpcc_rnd_thresh_1) + i * reg_gap,
  1584. 0xFFFF & dpcc->params[i].rnd_thresh);
  1585. isp_write_reg(dev, REG_ADDR(isp_dpcc_rg_fac_1) + i * reg_gap,
  1586. 0x3F3F & dpcc->params[i].rg_fac);
  1587. }
  1588. isp_write_reg(dev, REG_ADDR(isp_dpcc_ro_limits), dpcc->ro_limits);
  1589. isp_write_reg(dev, REG_ADDR(isp_dpcc_rnd_offs), dpcc->rnd_offs);
  1590. isp_write_reg(dev, REG_ADDR(isp_dpcc_mode), isp_dpcc_mode);
  1591. isp_info("exit %s\n", __func__);
  1592. return 0;
  1593. }
  1594. int isp_s_flt(struct isp_ic_dev *dev)
  1595. {
  1596. struct flt_denoise_type {
  1597. u32 thresh_sh0;
  1598. u32 thresh_sh1;
  1599. u32 thresh_bl0;
  1600. u32 thresh_bl1;
  1601. u32 stage_select;
  1602. u32 vmode;
  1603. u32 hmode;
  1604. };
  1605. struct flt_sharpen_type {
  1606. u32 fac_sh0;
  1607. u32 fac_sh1;
  1608. u32 fac_mid;
  1609. u32 fac_bl0;
  1610. u32 fac_bl1;
  1611. };
  1612. static struct flt_denoise_type denoise_tbl[] = {
  1613. {0, 0, 0, 0, 6, MRV_FILT_FILT_CHR_V_MODE_STATIC8,
  1614. MRV_FILT_FILT_CHR_H_MODE_BYPASS},
  1615. {18, 33, 8, 2, 6, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1616. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1617. {26, 44, 13, 5, 4, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1618. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1619. {36, 51, 23, 10, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1620. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1621. {41, 67, 26, 15, 3, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1622. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1623. {75, 10, 50, 20, 3, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1624. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1625. {90, 120, 60, 26, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1626. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1627. {120, 150, 80, 51, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1628. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1629. {170, 200, 140, 100, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1630. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1631. {250, 300, 180, 150, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1632. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1633. {1023, 1023, 1023, 1023, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1634. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1635. {1023, 1023, 1023, 1023, 0, MRV_FILT_FILT_CHR_V_MODE_BYPASS,
  1636. MRV_FILT_FILT_CHR_H_MODE_BYPASS},
  1637. };
  1638. static struct flt_sharpen_type sharpen_tbl[] = {
  1639. {0x4, 0x4, 0x4, 0x2, 0x0},
  1640. {0x7, 0x8, 0x6, 0x2, 0x0},
  1641. {0xA, 0xC, 0x8, 0x4, 0x0},
  1642. {0xC, 0x10, 0xA, 0x6, 0x2},
  1643. {0x16, 0x16, 0xC, 0x8, 0x4},
  1644. {0x14, 0x1B, 0x10, 0xA, 0x4},
  1645. {0x1A, 0x20, 0x13, 0xC, 0x6},
  1646. {0x1E, 0x26, 0x17, 0x10, 0x8},
  1647. {0x24, 0x2C, 0x1D, 0x15, 0x0D},
  1648. {0x2A, 0x30, 0x22, 0x1A, 0x14},
  1649. {0x30, 0x3F, 0x28, 0x24, 0x20},
  1650. };
  1651. // isp_info("enter %s\n", __func__);
  1652. if(dev->flt.changed || !is_isp_enable(dev))
  1653. {
  1654. struct isp_flt_context *flt = &dev->flt;
  1655. u32 isp_flt_mode = isp_read_reg(dev, REG_ADDR(isp_filt_mode));
  1656. if (!flt->enable) {
  1657. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_ENABLE, 0);
  1658. isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode);
  1659. return 0;
  1660. }
  1661. if (flt->denoise >= 0) {
  1662. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_sh0),
  1663. denoise_tbl[flt->denoise].thresh_sh0);
  1664. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_sh1),
  1665. denoise_tbl[flt->denoise].thresh_sh1);
  1666. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_bl0),
  1667. denoise_tbl[flt->denoise].thresh_bl0);
  1668. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_bl1),
  1669. denoise_tbl[flt->denoise].thresh_bl1);
  1670. REG_SET_SLICE(isp_flt_mode, MRV_FILT_STAGE1_SELECT,
  1671. denoise_tbl[flt->denoise].stage_select);
  1672. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_CHR_V_MODE,
  1673. denoise_tbl[flt->denoise].vmode);
  1674. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_CHR_H_MODE,
  1675. denoise_tbl[flt->denoise].hmode);
  1676. }
  1677. if (flt->sharpen >= 0) {
  1678. isp_write_reg(dev, REG_ADDR(isp_filt_fac_sh0),
  1679. sharpen_tbl[flt->sharpen].fac_sh0);
  1680. isp_write_reg(dev, REG_ADDR(isp_filt_fac_sh1),
  1681. sharpen_tbl[flt->sharpen].fac_sh1);
  1682. isp_write_reg(dev, REG_ADDR(isp_filt_fac_mid),
  1683. sharpen_tbl[flt->sharpen].fac_mid);
  1684. isp_write_reg(dev, REG_ADDR(isp_filt_fac_bl0),
  1685. sharpen_tbl[flt->sharpen].fac_bl0);
  1686. isp_write_reg(dev, REG_ADDR(isp_filt_fac_bl1),
  1687. sharpen_tbl[flt->sharpen].fac_bl1);
  1688. }
  1689. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_MODE,
  1690. MRV_FILT_FILT_MODE_DYNAMIC);
  1691. isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode);
  1692. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_ENABLE, 1);
  1693. isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode);
  1694. isp_write_reg(dev, REG_ADDR(isp_filt_lum_weight), 0x00032040);
  1695. dev->flt.changed = false;
  1696. } else {
  1697. dev->flt.changed = true;
  1698. }
  1699. isp_info("exit %s\n", __func__);
  1700. return 0;
  1701. }
  1702. int isp_s_cac(struct isp_ic_dev *dev)
  1703. {
  1704. struct isp_cac_context *cac = &dev->cac;
  1705. u32 val = 0;
  1706. u32 isp_cac_ctrl = isp_read_reg(dev, REG_ADDR(isp_cac_ctrl));
  1707. isp_info("enter %s\n", __func__);
  1708. if (!cac->enable) {
  1709. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_CAC_EN, 0);
  1710. isp_write_reg(dev, REG_ADDR(isp_cac_ctrl), isp_cac_ctrl);
  1711. return 0;
  1712. }
  1713. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_H_CLIP_MODE, cac->hmode);
  1714. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_V_CLIP_MODE, cac->vmode);
  1715. isp_write_reg(dev, REG_ADDR(isp_cac_count_start),
  1716. cac->hstart | (cac->vstart << 16));
  1717. isp_write_reg(dev, REG_ADDR(isp_cac_a), cac->ar | (cac->ab << 16));
  1718. isp_write_reg(dev, REG_ADDR(isp_cac_b), cac->br | (cac->bb << 16));
  1719. isp_write_reg(dev, REG_ADDR(isp_cac_c), cac->cr | (cac->cb << 16));
  1720. REG_SET_SLICE(val, MRV_CAC_X_NS, cac->xns);
  1721. REG_SET_SLICE(val, MRV_CAC_X_NF, cac->xnf);
  1722. isp_write_reg(dev, REG_ADDR(isp_cac_x_norm), val);
  1723. val = 0;
  1724. REG_SET_SLICE(val, MRV_CAC_Y_NS, cac->yns);
  1725. REG_SET_SLICE(val, MRV_CAC_Y_NF, cac->ynf);
  1726. isp_write_reg(dev, REG_ADDR(isp_cac_y_norm), val);
  1727. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_CAC_EN, 1);
  1728. isp_write_reg(dev, REG_ADDR(isp_cac_ctrl), isp_cac_ctrl);
  1729. isp_info("exit %s\n", __func__);
  1730. return 0;
  1731. }
  1732. int isp_s_deg(struct isp_ic_dev *dev)
  1733. {
  1734. struct isp_deg_context *deg = &dev->deg;
  1735. int i;
  1736. u32 isp_gamma_dx_lo = 0;
  1737. u32 isp_gamma_dx_hi = 0;
  1738. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  1739. isp_info("enter %s\n", __func__);
  1740. if (!deg->enable) {
  1741. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_IN_ENABLE, 0);
  1742. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  1743. return 0;
  1744. }
  1745. for (i = 0; i < 8; i++) {
  1746. isp_gamma_dx_lo |= deg->segment[i] << (i * 4);
  1747. isp_gamma_dx_hi |= deg->segment[i + 8] << (i * 4);
  1748. }
  1749. isp_write_reg(dev, REG_ADDR(isp_gamma_dx_lo), isp_gamma_dx_lo);
  1750. isp_write_reg(dev, REG_ADDR(isp_gamma_dx_hi), isp_gamma_dx_hi);
  1751. for (i = 0; i < 17; i++) {
  1752. isp_write_reg(dev, REG_ADDR(degamma_r_y_block_arr[i]),
  1753. deg->r[i]);
  1754. isp_write_reg(dev, REG_ADDR(degamma_g_y_block_arr[i]),
  1755. deg->g[i]);
  1756. isp_write_reg(dev, REG_ADDR(degamma_b_y_block_arr[i]),
  1757. deg->b[i]);
  1758. }
  1759. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_IN_ENABLE, 1);
  1760. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  1761. isp_info("exit %s\n", __func__);
  1762. return 0;
  1763. }
  1764. static u32 get_eff_coeff(int decimal)
  1765. {
  1766. u32 value = 0;
  1767. if (decimal <= -6)
  1768. value = 15;
  1769. else if (decimal <= -3)
  1770. value = 14;
  1771. else if (decimal == -2)
  1772. value = 13;
  1773. else if (decimal == -1)
  1774. value = 12;
  1775. else if (decimal == 0)
  1776. value = 0;
  1777. else if (decimal == 1)
  1778. value = 8;
  1779. else if (decimal == 2)
  1780. value = 9;
  1781. else if (decimal < 6)
  1782. value = 10;
  1783. else
  1784. value = 11;
  1785. return value;
  1786. }
  1787. int isp_s_ie(struct isp_ic_dev *dev)
  1788. {
  1789. struct isp_ie_context *ie = &dev->ie;
  1790. u32 img_eff_ctrl = isp_read_reg(dev, REG_ADDR(img_eff_ctrl));
  1791. u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl));
  1792. u32 vi_ircl = isp_read_reg(dev, REG_ADDR(vi_ircl));
  1793. u32 img_eff_tint = isp_read_reg(dev, REG_ADDR(img_eff_tint));
  1794. u32 img_eff_color_sel = isp_read_reg(dev, REG_ADDR(img_eff_color_sel));
  1795. u32 mat[9];
  1796. u32 sharpen = 0;
  1797. int i;
  1798. isp_info("enter %s\n", __func__);
  1799. REG_SET_SLICE(vi_ircl, MRV_VI_IE_SOFT_RST, 1);
  1800. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  1801. if (!ie->enable) {
  1802. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_CFG_UPD,
  1803. MRV_IMGEFF_CFG_UPD_UPDATE);
  1804. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_BYPASS_MODE,
  1805. MRV_IMGEFF_BYPASS_MODE_BYPASS);
  1806. REG_SET_SLICE(vi_iccl, MRV_VI_IE_CLK_ENABLE, 0);
  1807. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  1808. isp_write_reg(dev, REG_ADDR(img_eff_ctrl), img_eff_ctrl);
  1809. return 0;
  1810. }
  1811. REG_SET_SLICE(vi_ircl, MRV_VI_IE_SOFT_RST, 0);
  1812. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  1813. REG_SET_SLICE(vi_iccl, MRV_VI_IE_CLK_ENABLE, 1);
  1814. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  1815. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_EFFECT_MODE, ie->mode);
  1816. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_FULL_RANGE, ie->full_range);
  1817. for (i = 0; i < 9; i++)
  1818. mat[i] = get_eff_coeff(ie->m[i]);
  1819. if (ie->mode == MRV_IMGEFF_EFFECT_MODE_SEPIA) {
  1820. img_eff_tint = isp_read_reg(dev, REG_ADDR(img_eff_tint));
  1821. REG_SET_SLICE(img_eff_tint, MRV_IMGEFF_INCR_CR, ie->tint_cr);
  1822. REG_SET_SLICE(img_eff_tint, MRV_IMGEFF_INCR_CB, ie->tint_cb);
  1823. isp_write_reg(dev, REG_ADDR(img_eff_tint), img_eff_tint);
  1824. } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_COLOR_SEL) {
  1825. REG_SET_SLICE(img_eff_color_sel, MRV_IMGEFF_COLOR_SELECTION,
  1826. ie->color_sel);
  1827. REG_SET_SLICE(img_eff_color_sel, MRV_IMGEFF_COLOR_THRESHOLD,
  1828. ie->color_thresh);
  1829. isp_write_reg(dev, REG_ADDR(img_eff_color_sel),
  1830. img_eff_color_sel);
  1831. } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_EMBOSS) {
  1832. isp_write_reg(dev, REG_ADDR(img_eff_mat_1),
  1833. mat[0] | (mat[1] << 4) | (mat[2] << 8) | (mat[3]
  1834. << 12));
  1835. isp_write_reg(dev, REG_ADDR(img_eff_mat_2),
  1836. mat[4] | (mat[5] << 4) | (mat[6] << 8) | (mat[7]
  1837. << 12));
  1838. isp_write_reg(dev, REG_ADDR(img_eff_mat_3), mat[8]);
  1839. } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_SKETCH ||
  1840. ie->mode == MRV_IMGEFF_EFFECT_MODE_SHARPEN) {
  1841. isp_write_reg(dev, REG_ADDR(img_eff_mat_3),
  1842. (mat[0] << 4) | (mat[1] << 8) | (mat[2] << 12));
  1843. isp_write_reg(dev, REG_ADDR(img_eff_mat_4),
  1844. mat[3] | (mat[4] << 4) | (mat[5] << 8) | (mat[6]
  1845. << 12));
  1846. isp_write_reg(dev, REG_ADDR(img_eff_mat_5),
  1847. mat[7] | (mat[8] << 4));
  1848. REG_SET_SLICE(sharpen, MRV_IMGEFF_SHARP_FACTOR,
  1849. ie->sharpen_factor);
  1850. REG_SET_SLICE(sharpen, MRV_IMGEFF_CORING_THR,
  1851. ie->sharpen_thresh);
  1852. isp_write_reg(dev, REG_ADDR(img_eff_sharpen), sharpen);
  1853. }
  1854. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_CFG_UPD,
  1855. MRV_IMGEFF_CFG_UPD_UPDATE);
  1856. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_BYPASS_MODE,
  1857. MRV_IMGEFF_BYPASS_MODE_PROCESS);
  1858. isp_write_reg(dev, REG_ADDR(img_eff_ctrl), img_eff_ctrl);
  1859. isp_info("exit %s\n", __func__);
  1860. return 0;
  1861. }
  1862. int isp_s_vsm(struct isp_ic_dev *dev)
  1863. {
  1864. struct isp_vsm_context *vsm = &dev->vsm;
  1865. u32 isp_vsm_mode = isp_read_reg(dev, REG_ADDR(isp_vsm_mode));
  1866. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1867. isp_info("enter %s\n", __func__);
  1868. if (!vsm->enable) {
  1869. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_EN, 0);
  1870. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_IRQ_ENABLE, 0);
  1871. isp_write_reg(dev, REG_ADDR(isp_vsm_mode), isp_vsm_mode);
  1872. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1873. isp_imsc & ~MRV_ISP_IMSC_VSM_END_MASK);
  1874. return 0;
  1875. }
  1876. isp_write_reg(dev, REG_ADDR(isp_vsm_h_offs), vsm->window.x);
  1877. isp_write_reg(dev, REG_ADDR(isp_vsm_v_offs), vsm->window.y);
  1878. isp_write_reg(dev, REG_ADDR(isp_vsm_h_size),
  1879. vsm->window.width & 0xFFFFE);
  1880. isp_write_reg(dev, REG_ADDR(isp_vsm_v_size),
  1881. vsm->window.height & 0xFFFFE);
  1882. isp_write_reg(dev, REG_ADDR(isp_vsm_h_segments), vsm->h_seg);
  1883. isp_write_reg(dev, REG_ADDR(isp_vsm_v_segments), vsm->v_seg);
  1884. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_EN, 1);
  1885. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_IRQ_ENABLE, 1);
  1886. isp_write_reg(dev, REG_ADDR(isp_vsm_mode), isp_vsm_mode);
  1887. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1888. isp_imsc | MRV_ISP_IMSC_VSM_END_MASK);
  1889. isp_info("exit %s\n", __func__);
  1890. return 0;
  1891. }
  1892. int isp_g_vsm(struct isp_ic_dev *dev, struct isp_vsm_result *vsm)
  1893. {
  1894. isp_info("enter %s\n", __func__);
  1895. vsm->x = isp_read_reg(dev, REG_ADDR(isp_vsm_delta_h));
  1896. vsm->y = isp_read_reg(dev, REG_ADDR(isp_vsm_delta_v));
  1897. isp_info("exit %s\n", __func__);
  1898. return 0;
  1899. }
  1900. #if 0
  1901. u32 get_afm_shift(u32 count, u32 thresh)
  1902. {
  1903. u32 grad = count;
  1904. u32 shift = 0;
  1905. while (grad > (thresh)) {
  1906. ++shift;
  1907. grad >>= 1;
  1908. }
  1909. return shift;
  1910. }
  1911. #endif
  1912. int isp_s_afm(struct isp_ic_dev *dev)
  1913. {
  1914. struct isp_afm_context *afm = &dev->afm;
  1915. u32 mask =
  1916. (MRV_ISP_IMSC_AFM_FIN_MASK | MRV_ISP_IMSC_AFM_LUM_OF_MASK |
  1917. MRV_ISP_IMSC_AFM_SUM_OF_MASK);
  1918. u32 shift = 0;
  1919. int i;
  1920. u32 isp_afm_ctrl = isp_read_reg(dev, REG_ADDR(isp_afm_ctrl));
  1921. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1922. isp_info("enter %s\n", __func__);
  1923. if (!afm->enable) {
  1924. REG_SET_SLICE(isp_afm_ctrl, MRV_AFM_AFM_EN, 0);
  1925. isp_imsc &= ~mask;
  1926. isp_write_reg(dev, REG_ADDR(isp_afm_ctrl), isp_afm_ctrl);
  1927. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  1928. return 0;
  1929. }
  1930. for (i = 0; i < 3; i++) {
  1931. isp_write_reg(dev, REG_ADDR(isp_afm_lt_a) + i * 8,
  1932. (afm->window[i].x << 16) | afm->window[i].y);
  1933. isp_write_reg(dev, REG_ADDR(isp_afm_rb_a) + i * 8,
  1934. ((afm->window[i].x + afm->window[i].width -
  1935. 1) << 16) | ((afm->window[i].y +
  1936. afm->window[i].height - 1)));
  1937. }
  1938. REG_SET_SLICE(shift, MRV_AFM_LUM_VAR_SHIFT, afm->lum_shift);
  1939. REG_SET_SLICE(shift, MRV_AFM_AFM_VAR_SHIFT, afm->afm_shift);
  1940. isp_write_reg(dev, REG_ADDR(isp_afm_var_shift), shift);
  1941. isp_write_reg(dev, REG_ADDR(isp_afm_thres), afm->thresh);
  1942. REG_SET_SLICE(isp_afm_ctrl, MRV_AFM_AFM_EN, 1);
  1943. isp_imsc |= mask;
  1944. isp_write_reg(dev, REG_ADDR(isp_afm_ctrl), isp_afm_ctrl);
  1945. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  1946. isp_info("exit %s\n", __func__);
  1947. return 0;
  1948. }
  1949. int isp_g_afm(struct isp_ic_dev *dev, struct isp_afm_result *afm)
  1950. {
  1951. isp_info("enter %s\n", __func__);
  1952. afm->sum_a = isp_read_reg(dev, REG_ADDR(isp_afm_sum_a));
  1953. afm->sum_b = isp_read_reg(dev, REG_ADDR(isp_afm_sum_b));
  1954. afm->sum_c = isp_read_reg(dev, REG_ADDR(isp_afm_sum_c));
  1955. afm->lum_a = isp_read_reg(dev, REG_ADDR(isp_afm_lum_a));
  1956. afm->lum_b = isp_read_reg(dev, REG_ADDR(isp_afm_lum_b));
  1957. afm->lum_c = isp_read_reg(dev, REG_ADDR(isp_afm_lum_c));
  1958. isp_info("exit %s\n", __func__);
  1959. return 0;
  1960. }
  1961. int isp_s_exp2_inputsel(struct isp_ic_dev *dev)
  1962. {
  1963. #ifndef ISP_AEV2_RY
  1964. pr_err("unsupported function: %s\n", __func__);
  1965. return -EINVAL;
  1966. #else
  1967. struct isp_exp2_context *exp2 = &dev->exp2;
  1968. u32 isp_expv2_ctrl = isp_read_reg(dev, REG_ADDR(isp_expv2_ctrl));
  1969. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_INPUT_SELECT, exp2->input_select);
  1970. isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl);
  1971. return 0;
  1972. #endif
  1973. }
  1974. int isp_s_exp2_sizeratio(struct isp_ic_dev *dev, u32 h_size)
  1975. {
  1976. #ifndef ISP_AEV2_RY
  1977. pr_err("unsupported function: %s\n", __func__);
  1978. return -EINVAL;
  1979. #else
  1980. u32 size_inv;
  1981. size_inv = isp_read_reg(dev, REG_ADDR(isp_expv2_size_invert));
  1982. REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_H, h_size);
  1983. isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert), size_inv);
  1984. return 0;
  1985. #endif
  1986. }
  1987. int isp_s_exp2(struct isp_ic_dev *dev)
  1988. {
  1989. #ifndef ISP_AEV2_RY
  1990. //isp_err("unsupported function: %s\n", __func__);
  1991. return -EINVAL;
  1992. #else
  1993. u32 miv2_ctrl;
  1994. struct isp_exp2_context *exp2 = &dev->exp2;
  1995. u32 isp_expv2_ctrl = isp_read_reg(dev, REG_ADDR(isp_expv2_ctrl));
  1996. u32 grid_w, grid_h;
  1997. u32 size, offset, size_inv, weight;
  1998. isp_info("enter %s\n", __func__);
  1999. grid_w = ((exp2->window.width - 1) >> 6) << 1;
  2000. grid_h = ((exp2->window.height - 1) >> 6) << 1;
  2001. if (!exp2->enable) {
  2002. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_ENABLE, 0);
  2003. isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl);
  2004. return 0;
  2005. }
  2006. size = 0;
  2007. REG_SET_SLICE(size, MRV_AE_ISP_EXPV2_SIZE_H, grid_w);
  2008. REG_SET_SLICE(size, MRV_AE_ISP_EXPV2_SIZE_V, grid_h);
  2009. offset = 0;
  2010. REG_SET_SLICE(offset, MRV_AE_ISP_EXPV2_OFFSET_H, exp2->window.x);
  2011. REG_SET_SLICE(offset, MRV_AE_ISP_EXPV2_OFFSET_V, exp2->window.y);
  2012. size_inv = 0;
  2013. REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_H, (65536 + grid_w/2) / grid_w);
  2014. REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_V, (65536 + grid_h/2) / grid_h);
  2015. weight = 0;
  2016. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_R, exp2->r)
  2017. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR, exp2->gr)
  2018. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB, exp2->gb)
  2019. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_B, exp2->b)
  2020. isp_write_reg(dev, REG_ADDR(isp_expv2_offset), offset);
  2021. isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert), size_inv);
  2022. isp_write_reg(dev, REG_ADDR(isp_expv2_size), size);
  2023. #ifdef ISP_AE_SHADOW_RY
  2024. isp_write_reg(dev, REG_ADDR(isp_expv2_offset_shd), offset);
  2025. isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert_shd), size_inv);
  2026. isp_write_reg(dev, REG_ADDR(isp_expv2_size_shd), size);
  2027. #endif
  2028. isp_write_reg(dev, REG_ADDR(isp_expv2_pixel_weight), weight);
  2029. miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl));
  2030. REG_SET_SLICE(miv2_ctrl, MP_JDP_PATH_ENABLE, 1);
  2031. isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl);
  2032. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_base_ad_init), dev->exp2.pa);
  2033. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_size_init), AEV2_DMA_SIZE);
  2034. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_offs_cnt_init), 0);
  2035. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_llength), AEV2_DMA_SIZE);
  2036. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_width), 1024);
  2037. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_height), 1);
  2038. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_size), AEV2_DMA_SIZE);
  2039. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_ENABLE, 1);
  2040. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_INPUT_SELECT, exp2->input_select);
  2041. isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl);
  2042. return 0;
  2043. #endif
  2044. }
  2045. int isp_s_2dnr(struct isp_ic_dev *dev)
  2046. {
  2047. #ifndef ISP_2DNR
  2048. //isp_err("unsupported function: %s\n", __func__);
  2049. return -EINVAL;
  2050. #else
  2051. struct isp_2dnr_context *dnr2 = &dev->dnr2;
  2052. u32 isp_denoise2d_control =
  2053. isp_read_reg(dev, REG_ADDR(isp_denoise2d_control));
  2054. u32 value, addr, strength;
  2055. u32 isp_ctrl;
  2056. int i;
  2057. isp_info("enter %s\n", __func__);
  2058. if (!dnr2->enable) {
  2059. #ifndef ISP_2DNR_V4
  2060. REG_SET_SLICE(isp_denoise2d_control, ISP_2DNR_ENABLE, 0);
  2061. isp_write_reg(dev, REG_ADDR(isp_denoise2d_control),
  2062. isp_denoise2d_control);
  2063. #else
  2064. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  2065. REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 0);
  2066. if((value & DENOISE3D_V20_TNR_ENABLE_MASK) == 0)
  2067. REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 0);
  2068. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl),
  2069. value);
  2070. #endif
  2071. return 0;
  2072. }
  2073. strength = isp_read_reg(dev, REG_ADDR(isp_denoise2d_strength));
  2074. REG_SET_SLICE(strength, ISP_2DNR_PRGAMMA_STRENGTH, dnr2->pre_gamma);
  2075. REG_SET_SLICE(strength, ISP_2DNR_STRENGTH, dnr2->strength);
  2076. isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength), strength);
  2077. addr = REG_ADDR(isp_denoise2d_sigma_y[0]);
  2078. for (i = 0; i < 60; i += 5) {
  2079. value = 0;
  2080. REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i]);
  2081. REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 1]);
  2082. REG_SET_SLICE(value, ISP_2DNR_SIGMAY2A,
  2083. dnr2->sigma[i + 2] >> 6);
  2084. isp_write_reg(dev, addr, value);
  2085. value = 0;
  2086. addr += 4;
  2087. REG_SET_SLICE(value, ISP_2DNR_SIGMAY2B,
  2088. dnr2->sigma[i + 2] & 0x3f);
  2089. REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i + 3]);
  2090. REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 4]);
  2091. isp_write_reg(dev, addr, value);
  2092. addr += 4;
  2093. }
  2094. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  2095. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  2096. REG_SET_SLICE(isp_denoise2d_control, ISP_2DNR_ENABLE, 1);
  2097. #if defined(ISP_2DNR_V2) || defined(ISP_2DNR_V4)
  2098. isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr), dnr2->sigma_sqr);
  2099. isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr_shd),
  2100. dnr2->sigma_sqr);
  2101. isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor),
  2102. dnr2->weight);
  2103. isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor_shd),
  2104. dnr2->weight);
  2105. /* refer to HW spec for HBLANK */
  2106. //isp_write_reg(dev, REG_ADDR(isp_denoise2d_dummy_hblank), 0);
  2107. isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength_shd), strength);
  2108. isp_write_reg(dev, REG_ADDR(isp_denoise2d_control_shd),
  2109. isp_denoise2d_control);
  2110. #endif
  2111. #ifndef ISP_2DNR_V4
  2112. isp_write_reg(dev, REG_ADDR(isp_denoise2d_control),
  2113. isp_denoise2d_control);
  2114. #else
  2115. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_blending));
  2116. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_OFFSET, dnr2->str_off);
  2117. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_MAX, dnr2->str_max);
  2118. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_SLOPE, dnr2->str_slope);
  2119. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_blending), value);
  2120. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  2121. REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 1);
  2122. REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 1);
  2123. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl),
  2124. value);
  2125. #endif
  2126. isp_info("exit %s\n", __func__);
  2127. return 0;
  2128. #endif
  2129. }
  2130. int isp_s_simp(struct isp_ic_dev *dev)
  2131. {
  2132. struct isp_simp_context *simp = &dev->simp;
  2133. u32 vi_ircl = isp_read_reg(dev, REG_ADDR(vi_ircl));
  2134. u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl));
  2135. u32 super_imp_ctrl = isp_read_reg(dev, REG_ADDR(super_imp_ctrl));
  2136. isp_info("enter %s\n", __func__);
  2137. REG_SET_SLICE(vi_ircl, MRV_VI_SIMP_SOFT_RST, 1);
  2138. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2139. if (!simp->enable) {
  2140. REG_SET_SLICE(vi_iccl, MRV_VI_SIMP_CLK_ENABLE, 0);
  2141. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  2142. return 0;
  2143. }
  2144. REG_SET_SLICE(vi_ircl, MRV_VI_SIMP_SOFT_RST, 0);
  2145. isp_write_reg(dev, REG_ADDR(super_imp_offset_x), simp->x);
  2146. isp_write_reg(dev, REG_ADDR(super_imp_offset_y), simp->y);
  2147. isp_write_reg(dev, REG_ADDR(super_imp_color_y), simp->r);
  2148. isp_write_reg(dev, REG_ADDR(super_imp_color_cb), simp->g);
  2149. isp_write_reg(dev, REG_ADDR(super_imp_color_cr), simp->b);
  2150. REG_SET_SLICE(super_imp_ctrl, MRV_SI_TRANSPARENCY_MODE,
  2151. simp->transparency_mode);
  2152. REG_SET_SLICE(super_imp_ctrl, MRV_SI_REF_IMAGE, simp->ref_image);
  2153. isp_write_reg(dev, REG_ADDR(super_imp_ctrl), super_imp_ctrl);
  2154. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2155. REG_SET_SLICE(vi_iccl, MRV_VI_SIMP_CLK_ENABLE, 1);
  2156. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  2157. isp_info("exit %s\n", __func__);
  2158. return 0;
  2159. }
  2160. int isp_s_cproc(struct isp_ic_dev *dev)
  2161. {
  2162. struct isp_cproc_context *cproc = &dev->cproc;
  2163. u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl));
  2164. u32 cproc_ctrl = isp_read_reg(dev, REG_ADDR(cproc_ctrl));
  2165. //REG_SET_SLICE(vi_ircl, MRV_VI_CP_SOFT_RST, 1);
  2166. //isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2167. //if there is no shd register. should update cporc register in isp frame end irq.
  2168. #ifndef ISP_CPROC_SHD_RY
  2169. if(dev->cproc.changed || !is_isp_enable(dev))
  2170. {
  2171. #endif
  2172. isp_info("enter %s %d\n", __func__, cproc->enable);
  2173. if (!cproc->enable) {
  2174. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_ENABLE, 0);
  2175. /* REG_SET_SLICE(vi_iccl, MRV_VI_CP_CLK_ENABLE, 0); */
  2176. /* isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl); */
  2177. isp_write_reg(dev, REG_ADDR(cproc_ctrl), cproc_ctrl);
  2178. return 0;
  2179. }
  2180. //REG_SET_SLICE(vi_ircl, MRV_VI_CP_SOFT_RST, 0);
  2181. //isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2182. isp_write_reg(dev, REG_ADDR(cproc_contrast), cproc->contrast);
  2183. isp_write_reg(dev, REG_ADDR(cproc_brightness), cproc->brightness);
  2184. isp_write_reg(dev, REG_ADDR(cproc_saturation), cproc->saturation);
  2185. isp_write_reg(dev, REG_ADDR(cproc_hue), cproc->hue);
  2186. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_ENABLE, 1);
  2187. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_C_OUT_RANGE,
  2188. cproc->c_out_full);
  2189. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_Y_OUT_RANGE,
  2190. cproc->y_out_full);
  2191. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_Y_IN_RANGE, cproc->y_in_full);
  2192. REG_SET_SLICE(vi_iccl, MRV_VI_CP_CLK_ENABLE, 1);
  2193. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  2194. isp_write_reg(dev, REG_ADDR(cproc_ctrl), cproc_ctrl);
  2195. #ifndef ISP_CPROC_SHD_RY
  2196. dev->cproc.changed = false;
  2197. } else {
  2198. dev->cproc.changed = true;
  2199. }
  2200. #endif
  2201. isp_info("exit %s\n", __func__);
  2202. return 0;
  2203. }
  2204. int isp_s_elawb(struct isp_ic_dev *dev)
  2205. {
  2206. struct isp_elawb_context *elawb = &dev->elawb;
  2207. u32 awb_meas_mode = isp_read_reg(dev, REG_ADDR(awb_meas_mode));
  2208. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  2209. u32 id = elawb->id;
  2210. u32 data;
  2211. if (!elawb->enable) {
  2212. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_IRQ_ENABLE, 0);
  2213. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_EN, 0);
  2214. isp_write_reg(dev, REG_ADDR(awb_meas_mode), awb_meas_mode);
  2215. isp_write_reg(dev, REG_ADDR(isp_imsc),
  2216. isp_imsc & ~MRV_ISP_IMSC_AWB_DONE_MASK);
  2217. return 0;
  2218. }
  2219. isp_write_reg(dev, REG_ADDR(awb_meas_h_offs), elawb->window.x);
  2220. isp_write_reg(dev, REG_ADDR(awb_meas_v_offs), elawb->window.y);
  2221. isp_write_reg(dev, REG_ADDR(awb_meas_h_size), elawb->window.width);
  2222. isp_write_reg(dev, REG_ADDR(awb_meas_v_size), elawb->window.height);
  2223. if (id > 0 && id < 9) {
  2224. isp_write_reg(dev, REG_ADDR(awb_meas_center[id - 1].x),
  2225. elawb->info[id - 1].x);
  2226. isp_write_reg(dev, REG_ADDR(awb_meas_center[id - 1].y),
  2227. elawb->info[id - 1].y);
  2228. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a1),
  2229. elawb->info[id - 1].a1);
  2230. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a2),
  2231. elawb->info[id - 1].a2);
  2232. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a3),
  2233. elawb->info[id - 1].a3);
  2234. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a4),
  2235. elawb->info[id - 1].a4);
  2236. isp_write_reg(dev, REG_ADDR(awb_meas_rmax[id - 1]),
  2237. elawb->info[id - 1].r_max_sqr);
  2238. }
  2239. data = 0;
  2240. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_R, elawb->r);
  2241. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_B, elawb->b);
  2242. isp_write_reg(dev, REG_ADDR(isp_awb_gain_rb), data);
  2243. data = 0;
  2244. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_GR, elawb->gr);
  2245. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_GB, elawb->gb);
  2246. isp_write_reg(dev, REG_ADDR(isp_awb_gain_g), data);
  2247. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_IRQ_ENABLE, 1);
  2248. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_EN, 1);
  2249. isp_write_reg(dev, REG_ADDR(awb_meas_mode), awb_meas_mode);
  2250. isp_write_reg(dev, REG_ADDR(isp_imsc),
  2251. isp_imsc | MRV_ISP_IMSC_AWB_DONE_MASK);
  2252. return 0;
  2253. }
  2254. int isp_ioc_qcap(struct isp_ic_dev *dev, void __user *args)
  2255. {
  2256. /* use public VIDIOC_QUERYCAP to query the type of v4l-subdevs. */
  2257. #ifdef __KERNEL__
  2258. #ifndef USE_FPGA
  2259. struct v4l2_capability *cap = (struct v4l2_capability *)args;
  2260. strcpy((char *)cap->driver, "viv_isp_subdev");
  2261. cap->bus_info[0] = (__u8)dev->id;//isp channel id
  2262. #else
  2263. struct v4l2_capability cap;
  2264. strcpy((char *)cap.driver, "viv_isp_subdev");
  2265. cap.bus_info[0] = (__u8)dev->id;//isp channel id
  2266. isp_info("enter %s viv_isp_subdev\n", __func__);
  2267. viv_check_retval(copy_to_user
  2268. ((struct v4l2_capability *)args, &cap, sizeof(cap)));
  2269. #endif
  2270. #endif
  2271. return 0;
  2272. }
  2273. int isp_ioc_g_status(struct isp_ic_dev *dev, void __user *args)
  2274. {
  2275. u32 val = 0;
  2276. /* val = isp_read_reg(REG_ADDR(isp_feature_version)); */
  2277. viv_check_retval(copy_to_user(args, &val, sizeof(val)));
  2278. return 0;
  2279. }
  2280. static u32 getScaleFactor(u32 src, u32 dst)
  2281. {
  2282. if (dst > src) {
  2283. return ((65536 * (src - 1)) / (dst - 1));
  2284. } else if (dst < src) {
  2285. return ((65536 * (dst - 1)) / (src - 1)) + 1;
  2286. }
  2287. return 65536;
  2288. }
  2289. int isp_set_scaling(int id, struct isp_ic_dev *dev, bool stabilization, bool crop)
  2290. {
  2291. u32 addr, ctrl;
  2292. u32 iw, ih, ow, oh;
  2293. u32 inputWidth, inputHeight, outputWidth, outputHeight;
  2294. u32 scale_hy, scale_hcb, scale_hcr, scale_vy, scale_vc;
  2295. struct isp_mi_data_path_context *path = &dev->mi.path[id];
  2296. if (crop) { //enabled crop.Do not need to scaler.
  2297. isp_info("%s:The crop enabled ,So does not need to do scaler.\n", __func__);
  2298. return 0;
  2299. }
  2300. if (id == IC_MI_PATH_MAIN) { /* mp */
  2301. addr = REG_ADDR(mrsz_ctrl);
  2302. } else if (id == IC_MI_PATH_SELF) { /* sp */
  2303. addr = REG_ADDR(srsz_ctrl);
  2304. } else if (id == IC_MI_PATH_SELF2) { /* sp2 */
  2305. addr = REG_ADDR(srsz2_ctrl);
  2306. } else {
  2307. return -EFAULT;
  2308. }
  2309. inputWidth = path->in_width;
  2310. inputHeight = path->in_height;
  2311. outputWidth = path->out_width;
  2312. outputHeight = path->out_height;
  2313. if (stabilization) { /* enabled image stabilization. */
  2314. inputWidth = isp_read_reg(dev, REG_ADDR(isp_is_h_size));
  2315. inputHeight = isp_read_reg(dev, REG_ADDR(isp_is_v_size));
  2316. }
  2317. ctrl = isp_read_reg(dev, addr);
  2318. iw = inputWidth / 2;
  2319. ih = inputHeight;
  2320. ow = outputWidth / 2;
  2321. oh = outputHeight;
  2322. switch (path->in_mode) {
  2323. case IC_MI_DATAMODE_YUV422:
  2324. oh = outputHeight;
  2325. break;
  2326. case IC_MI_DATAMODE_YUV420:
  2327. oh = outputHeight / 2; /* scale cbcr */
  2328. break;
  2329. case IC_MI_DATAMODE_YUV444:
  2330. oh = outputHeight;
  2331. break;
  2332. case IC_MI_DATAMODE_RGB888:
  2333. oh = outputHeight;
  2334. break;
  2335. default:
  2336. return -EFAULT;
  2337. }
  2338. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_ENABLE,
  2339. inputWidth != outputWidth);
  2340. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_ENABLE,
  2341. inputHeight != outputHeight);
  2342. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_UP, inputWidth < outputWidth);
  2343. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_UP, inputHeight < outputHeight);
  2344. scale_hy = getScaleFactor(inputWidth, outputWidth);
  2345. scale_vy = getScaleFactor(inputHeight, outputHeight);
  2346. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_ENABLE, iw != ow);
  2347. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_ENABLE, ih != oh);
  2348. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_UP, iw < ow);
  2349. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_UP, ih < oh);
  2350. scale_hcr = getScaleFactor(iw, ow);
  2351. scale_hcb = getScaleFactor(iw, ow);
  2352. scale_vc = getScaleFactor(ih, oh);
  2353. /*Need to update immediately*/
  2354. REG_SET_SLICE(ctrl, MRV_MRSZ_CFG_UPD, 1);
  2355. if (id == IC_MI_PATH_MAIN) {
  2356. isp_write_reg(dev, REG_ADDR(mrsz_scale_vc), scale_vc);
  2357. isp_write_reg(dev, REG_ADDR(mrsz_scale_vy), scale_vy);
  2358. isp_write_reg(dev, REG_ADDR(mrsz_scale_hcr), scale_hcr);
  2359. isp_write_reg(dev, REG_ADDR(mrsz_scale_hcb), scale_hcb);
  2360. isp_write_reg(dev, REG_ADDR(mrsz_scale_hy), scale_hy);
  2361. isp_write_reg(dev, REG_ADDR(mrsz_ctrl), ctrl);
  2362. } else if (id == IC_MI_PATH_SELF) {
  2363. isp_write_reg(dev, REG_ADDR(srsz_scale_vc), scale_vc);
  2364. isp_write_reg(dev, REG_ADDR(srsz_scale_vy), scale_vy);
  2365. isp_write_reg(dev, REG_ADDR(srsz_scale_hcr), scale_hcr);
  2366. isp_write_reg(dev, REG_ADDR(srsz_scale_hcb), scale_hcb);
  2367. isp_write_reg(dev, REG_ADDR(srsz_scale_hy), scale_hy);
  2368. isp_write_reg(dev, REG_ADDR(srsz_ctrl), ctrl);
  2369. } else if (id == IC_MI_PATH_SELF2) {
  2370. isp_write_reg(dev, REG_ADDR(srsz2_scale_vc), scale_vc);
  2371. isp_write_reg(dev, REG_ADDR(srsz2_scale_vy), scale_vy);
  2372. isp_write_reg(dev, REG_ADDR(srsz2_scale_hcr), scale_hcr);
  2373. isp_write_reg(dev, REG_ADDR(srsz2_scale_hcb), scale_hcb);
  2374. isp_write_reg(dev, REG_ADDR(srsz2_scale_hy), scale_hy);
  2375. isp_write_reg(dev, REG_ADDR(srsz2_ctrl), ctrl);
  2376. }
  2377. return 0;
  2378. }
  2379. typedef struct isp_crop_reg_s {
  2380. u32 crop_ctrl_addr;
  2381. u32 crop_x_dir_addr;
  2382. u32 crop_y_dir_addr;
  2383. } isp_crop_reg_t;
  2384. int isp_set_crop(struct isp_ic_dev *dev)
  2385. {
  2386. long ret = 0;
  2387. u32 crop_ctrl, crop_x_dir, crop_y_dir;
  2388. u8 i;
  2389. isp_crop_reg_t crop_reg[ISP_MI_PATH_SP2_BP + 1] = {
  2390. {
  2391. REG_ADDR(mrsz_ctrl),
  2392. REG_ADDR(mrsz_phase_crop_x),
  2393. REG_ADDR(mrsz_phase_crop_y)
  2394. },
  2395. {
  2396. REG_ADDR(srsz_ctrl),
  2397. REG_ADDR(srsz_phase_crop_x),
  2398. REG_ADDR(srsz_phase_crop_y)
  2399. },
  2400. {
  2401. REG_ADDR(srsz2_ctrl),
  2402. REG_ADDR(srsz2_phase_crop_x),
  2403. REG_ADDR(srsz2_phase_crop_y)
  2404. }
  2405. };
  2406. struct isp_crop_context *crop = dev->crop;
  2407. for ( i = 0; i <= ISP_MI_PATH_SP2_BP; i++) {
  2408. crop_ctrl = isp_read_reg(dev, crop_reg[i].crop_ctrl_addr);
  2409. crop_x_dir = isp_read_reg(dev, crop_reg[i].crop_x_dir_addr);
  2410. crop_y_dir = isp_read_reg(dev, crop_reg[i].crop_y_dir_addr);
  2411. if (!crop[i].enabled) {
  2412. #ifndef ISP8000NANO_BASE
  2413. REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CROP_ENABLE, 0);
  2414. #endif
  2415. isp_write_reg(dev, crop_reg[i].crop_ctrl_addr, crop_ctrl);
  2416. continue;
  2417. }
  2418. REG_SET_SLICE(crop_x_dir, MRV_MRSZ_PHASE_H_START, crop[i].window.x);
  2419. REG_SET_SLICE(crop_y_dir, MRV_MRSZ_PHASE_V_START, crop[i].window.y);
  2420. REG_SET_SLICE(crop_x_dir, MRV_MRSZ_PHASE_H_END, crop[i].window.width + crop[i].window.x - 1); //x_end = x + width -1
  2421. REG_SET_SLICE(crop_y_dir, MRV_MRSZ_PHASE_V_END, crop[i].window.height + crop[i].window.y - 1); //y_end = y + height -1
  2422. #ifndef ISP8000NANO_BASE
  2423. REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CROP_ENABLE, 1);
  2424. /*Need to update immediately*/
  2425. REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CFG_UPD, 1);
  2426. #endif
  2427. isp_write_reg(dev, crop_reg[i].crop_x_dir_addr, crop_x_dir);
  2428. isp_write_reg(dev, crop_reg[i].crop_y_dir_addr, crop_y_dir);
  2429. isp_write_reg(dev, crop_reg[i].crop_ctrl_addr, crop_ctrl);
  2430. }
  2431. return ret;
  2432. }
  2433. int isp_ioc_g_feature(struct isp_ic_dev *dev, void __user *args)
  2434. {
  2435. u32 val = 0;
  2436. #ifdef ISP_EE_RY
  2437. val |= ISP_EE_SUPPORT;
  2438. #endif
  2439. #ifdef ISP_WDR3
  2440. val |= ISP_WDR3_SUPPORT;
  2441. #endif
  2442. #ifdef ISP_2DNR
  2443. val |= ISP_2DNR_SUPPORT;
  2444. #endif
  2445. #ifdef ISP_3DNR
  2446. val |= ISP_3DNR_SUPPORT;
  2447. #endif
  2448. #ifdef ISP_WDR_V3
  2449. val |= ISP_WDR3_SUPPORT;
  2450. #endif
  2451. #ifdef ISP_MIV2_RY
  2452. val |= ISP_MIV2_SUPPORT;
  2453. #endif
  2454. #ifdef ISP_AEV2_RY
  2455. val |= ISP_AEV2_SUPPORT;
  2456. #endif
  2457. #ifdef ISP_HDR_STITCH_RY
  2458. val |= ISP_HDR_STITCH_SUPPORT;
  2459. #endif
  2460. viv_check_retval(copy_to_user(args, &val, sizeof(val)));
  2461. return 0;
  2462. }
  2463. int isp_ioc_g_feature_veresion(struct isp_ic_dev *dev, void __user *args)
  2464. {
  2465. u32 val = 0;
  2466. /* val = isp_read_reg(REG_ADDR(isp_feature_version)); */
  2467. viv_check_retval(copy_to_user(args, &val, sizeof(val)));
  2468. return 0;
  2469. }
  2470. static long isp_get_extmem(struct isp_ic_dev *dev, void __user *args)
  2471. {
  2472. #define UT_USED_SIZE 0x01000000
  2473. long ret = 0;
  2474. struct isp_extmem_info ext_mem;
  2475. dev->ut_addr = dma_alloc_coherent(dev->device, UT_USED_SIZE, &dev->ut_phy_addr, GFP_KERNEL);
  2476. if (dev->ut_addr != NULL) {
  2477. ext_mem.addr = dev->ut_phy_addr;
  2478. ext_mem.size = UT_USED_SIZE;
  2479. } else {
  2480. return -1;
  2481. }
  2482. ret = copy_to_user(args, &ext_mem, sizeof(struct isp_extmem_info));
  2483. return ret;
  2484. }
  2485. long isp_priv_ioctl(struct isp_ic_dev *dev, unsigned int cmd, void __user *args)
  2486. {
  2487. int ret = -1;
  2488. if (!dev) {
  2489. return ret;
  2490. }
  2491. /*isp_info("ry [%s:%d]cmd 0x%08x\n", __func__, __LINE__, cmd);*/
  2492. switch (cmd) {
  2493. case ISPIOC_RESET:
  2494. if((ret = isp_mi_stop(dev)) != 0 )
  2495. {
  2496. pr_err("[%s:%d]stop mi error before resetting!\n", __func__, __LINE__);
  2497. break;
  2498. }
  2499. if((ret = isp_stop_stream(dev)) != 0)
  2500. {
  2501. pr_err("[%s:%d]stop isp stream before resetting!\n", __func__, __LINE__);
  2502. break;
  2503. }
  2504. ret = isp_reset(dev);
  2505. break;
  2506. case ISPIOC_WRITE_REG:
  2507. ret = isp_ioc_write_reg(dev, args);
  2508. break;
  2509. case ISPIOC_READ_REG:
  2510. ret = isp_ioc_read_reg(dev, args);
  2511. break;
  2512. case ISPIOC_GET_MIS:
  2513. ret = isp_ioc_read_mis(dev, args);
  2514. break;
  2515. case ISPIOC_ENABLE_TPG:
  2516. ret = isp_enable_tpg(dev);
  2517. break;
  2518. case ISPIOC_DISABLE_TPG:
  2519. ret = isp_disable_tpg(dev);
  2520. break;
  2521. case ISPIOC_ENABLE_BLS:
  2522. ret = isp_enable_bls(dev);
  2523. break;
  2524. case ISPIOC_DISABLE_BLS:
  2525. ret = isp_disable_bls(dev);
  2526. break;
  2527. case ISPIOC_START_DMA_READ:
  2528. ret = isp_ioc_start_dma_read(dev, args);
  2529. break;
  2530. case ISPIOC_CFG_DMA:
  2531. ret = isp_ioc_cfg_dma(dev, args);
  2532. break;
  2533. case ISPIOC_MI_STOP:
  2534. ret = isp_mi_stop(dev);
  2535. break;
  2536. case ISPIOC_DISABLE_ISP_OFF:
  2537. ret = isp_ioc_disable_isp_off(dev, args);
  2538. break;
  2539. case ISPIOC_ISP_STOP:
  2540. ret = isp_stop_stream(dev);
  2541. if(!ret) {
  2542. dev->streaming = false;
  2543. }
  2544. break;
  2545. case ISPIOC_ENABLE:
  2546. ret = isp_enable(dev);
  2547. break;
  2548. case ISPIOC_DISABLE:
  2549. ret = isp_disable(dev);
  2550. break;
  2551. case ISPIOC_ISP_STATUS:{
  2552. bool enable = is_isp_enable(dev);
  2553. viv_check_retval(copy_to_user
  2554. (args, &enable, sizeof(bool)));
  2555. ret = 0;
  2556. break;
  2557. }
  2558. case ISPIOC_ENABLE_LSC:
  2559. ret = isp_enable_lsc(dev);
  2560. break;
  2561. case ISPIOC_DISABLE_LSC:
  2562. ret = isp_disable_lsc(dev);
  2563. break;
  2564. case ISPIOC_S_DIGITAL_GAIN:
  2565. viv_check_retval(copy_from_user
  2566. (&dev->dgain, args, sizeof(dev->dgain)));
  2567. ret = isp_s_digital_gain(dev);
  2568. break;
  2569. #ifdef ISP_DEMOSAIC2_RY
  2570. case ISPIOC_S_DMSC_INTP:
  2571. viv_check_retval(copy_from_user
  2572. (&dev->demosaic.intp, args,
  2573. sizeof(dev->demosaic.intp)));
  2574. ret = isp_set_dmsc_intp(dev);
  2575. break;
  2576. case ISPIOC_S_DMSC_DMOI:
  2577. viv_check_retval(copy_from_user
  2578. (&dev->demosaic.demoire, args,
  2579. sizeof(dev->demosaic.demoire)));
  2580. ret = isp_set_dmsc_dmoi(dev);
  2581. break;
  2582. case ISPIOC_S_DMSC_SKIN:
  2583. viv_check_retval(copy_from_user
  2584. (&dev->demosaic.skin, args,
  2585. sizeof(dev->demosaic.skin)));
  2586. ret = isp_set_dmsc_skin(dev);
  2587. break;
  2588. case ISPIOC_S_DMSC_SHAP:
  2589. viv_check_retval(copy_from_user
  2590. (&dev->demosaic.sharpen, args,
  2591. sizeof(dev->demosaic.sharpen)));
  2592. ret = isp_set_dmsc_sharpen(dev);
  2593. break;
  2594. case ISPIOC_S_DMSC_SHAP_LINE:
  2595. viv_check_retval(copy_from_user
  2596. (&dev->demosaic.sharpenLine, args,
  2597. sizeof(dev->demosaic.sharpenLine)));
  2598. ret = isp_set_dmsc_sharpen_line(dev);
  2599. break;
  2600. case ISPIOC_S_DMSC_CAC:
  2601. viv_check_retval(copy_from_user
  2602. (&dev->cac, args, sizeof(dev->cac)));
  2603. ret = isp_set_dmsc_cac(dev);
  2604. break;
  2605. case ISPIOC_S_DMSC_DEPURPLE:
  2606. viv_check_retval(copy_from_user
  2607. (&dev->demosaic.depurple, args,
  2608. sizeof(dev->demosaic.depurple)));
  2609. ret = isp_set_dmsc_depurple(dev);
  2610. break;
  2611. case ISPIOC_S_DMSC_GFILTER:
  2612. viv_check_retval(copy_from_user
  2613. (&dev->demosaic.gFilter, args,
  2614. sizeof(dev->demosaic.gFilter)));
  2615. ret = isp_set_dmsc_gfilter(dev);
  2616. break;
  2617. case ISPIOC_S_DMSC:
  2618. viv_check_retval(copy_from_user
  2619. (&dev->demosaic, args, sizeof(dev->demosaic)));
  2620. ret = isp_s_dmsc(dev);
  2621. break;
  2622. #endif
  2623. case ISPIOC_ENABLE_AWB:
  2624. ret = isp_enable_awb(dev);
  2625. break;
  2626. case ISPIOC_DISABLE_AWB:
  2627. ret = isp_disable_awb(dev);
  2628. break;
  2629. case ISPIOC_ENABLE_WB:
  2630. ret = isp_enable_wb(dev, 1);
  2631. break;
  2632. case ISPIOC_DISABLE_WB:
  2633. ret = isp_enable_wb(dev, 0);
  2634. break;
  2635. case ISPIOC_ENABLE_GAMMA_OUT:
  2636. ret = isp_enable_gamma_out(dev, 1);
  2637. break;
  2638. case ISPIOC_DISABLE_GAMMA_OUT:
  2639. ret = isp_enable_gamma_out(dev, 0);
  2640. break;
  2641. #if defined(ISP_3DNR) || defined(ISP_3DNR_V2_V1)
  2642. case ISPIOC_R_3DNR:
  2643. viv_check_retval(copy_from_user
  2644. (&dev->dnr3, args, sizeof(dev->dnr3)));
  2645. ret = isp_r_3dnr(dev);
  2646. break;
  2647. #endif
  2648. case ISPIOC_S_IS:
  2649. viv_check_retval(copy_from_user
  2650. (&dev->is, args, sizeof(dev->is)));
  2651. ret = isp_s_is(dev);
  2652. break;
  2653. case ISPIOC_S_RAW_IS:
  2654. viv_check_retval(copy_from_user
  2655. (&dev->rawis, args, sizeof(dev->rawis)));
  2656. ret = isp_s_raw_is(dev);
  2657. break;
  2658. case ISPIOC_S_CC:
  2659. viv_check_retval(copy_from_user
  2660. (&dev->cc, args, sizeof(dev->cc)));
  2661. ret = isp_s_cc(dev);
  2662. break;
  2663. case ISPIOC_S_EE:
  2664. viv_check_retval(copy_from_user
  2665. (&dev->ee, args, sizeof(dev->ee)));
  2666. ret = isp_s_ee(dev);
  2667. break;
  2668. case ISPIOC_S_IE:
  2669. viv_check_retval(copy_from_user
  2670. (&dev->ie, args, sizeof(dev->ie)));
  2671. ret = isp_s_ie(dev);
  2672. break;
  2673. case ISPIOC_S_TPG:
  2674. viv_check_retval(copy_from_user
  2675. (&dev->tpg, args, sizeof(dev->tpg)));
  2676. ret = isp_s_tpg(dev);
  2677. break;
  2678. case ISPIOC_S_BLS:
  2679. viv_check_retval(copy_from_user
  2680. (&dev->bls, args, sizeof(dev->bls)));
  2681. ret = isp_s_bls(dev);
  2682. break;
  2683. case ISPIOC_BYPASS_MCM:
  2684. viv_check_retval(copy_from_user
  2685. (&dev->mcm, args, sizeof(dev->mcm)));
  2686. ret = isp_bypass_mcm(dev);
  2687. break;
  2688. case ISPIOC_S_MCM_WR:
  2689. viv_check_retval(copy_from_user
  2690. (&dev->mcm, args, sizeof(dev->mcm)));
  2691. ret = isp_s_mcm_wr(dev);
  2692. break;
  2693. case ISPIOC_S_MUX:
  2694. viv_check_retval(copy_from_user
  2695. (&dev->mux, args, sizeof(dev->mux)));
  2696. ret = isp_s_mux(dev);
  2697. break;
  2698. case ISPIOC_S_AWB:
  2699. viv_check_retval(copy_from_user
  2700. (&dev->awb, args, sizeof(dev->awb)));
  2701. ret = isp_s_awb(dev);
  2702. break;
  2703. case ISPIOC_S_LSC_TBL:
  2704. viv_check_retval(copy_from_user
  2705. (&dev->lsc, args, sizeof(dev->lsc)));
  2706. ret = isp_s_lsc_tbl(dev);
  2707. break;
  2708. case ISPIOC_S_LSC_SEC:
  2709. viv_check_retval(copy_from_user
  2710. (&dev->lsc, args, sizeof(dev->lsc)));
  2711. ret = isp_s_lsc_sec(dev);
  2712. break;
  2713. case ISPIOC_S_DPF:
  2714. viv_check_retval(copy_from_user
  2715. (&dev->dpf, args, sizeof(dev->dpf)));
  2716. ret = isp_s_dpf(dev);
  2717. break;
  2718. case ISPIOC_S_EXP:
  2719. viv_check_retval(copy_from_user
  2720. (&dev->exp, args, sizeof(dev->exp)));
  2721. ret = isp_s_exp(dev);
  2722. break;
  2723. case ISPIOC_S_HDREXP:
  2724. viv_check_retval(copy_from_user
  2725. (&dev->hdrexp, args, sizeof(dev->hdrexp)));
  2726. ret = isp_s_hdrexp(dev);
  2727. break;
  2728. case ISPIOC_S_CNR:
  2729. viv_check_retval(copy_from_user
  2730. (&dev->cnr, args, sizeof(dev->cnr)));
  2731. ret = isp_s_cnr(dev);
  2732. break;
  2733. case ISPIOC_S_FLT:
  2734. {
  2735. viv_check_retval(copy_from_user
  2736. (&dev->flt, args, sizeof(dev->flt)));
  2737. ret = isp_s_flt(dev);
  2738. break;
  2739. }
  2740. case ISPIOC_S_CAC:
  2741. viv_check_retval(copy_from_user
  2742. (&dev->cac, args, sizeof(dev->cac)));
  2743. ret = isp_s_cac(dev);
  2744. break;
  2745. case ISPIOC_S_DEG:
  2746. viv_check_retval(copy_from_user
  2747. (&dev->deg, args, sizeof(dev->deg)));
  2748. ret = isp_s_deg(dev);
  2749. break;
  2750. case ISPIOC_S_VSM:
  2751. viv_check_retval(copy_from_user
  2752. (&dev->vsm, args, sizeof(dev->vsm)));
  2753. ret = isp_s_vsm(dev);
  2754. break;
  2755. case ISPIOC_S_AFM:
  2756. viv_check_retval(copy_from_user
  2757. (&dev->afm, args, sizeof(dev->afm)));
  2758. ret = isp_s_afm(dev);
  2759. break;
  2760. case ISPIOC_S_HDR:
  2761. viv_check_retval(copy_from_user
  2762. (&dev->hdr, args, sizeof(dev->hdr)));
  2763. ret = isp_s_hdr(dev);
  2764. break;
  2765. case ISPIOC_ENABLE_HDR:
  2766. viv_check_retval(copy_from_user
  2767. (&dev->hdr, args, sizeof(dev->hdr)));
  2768. ret = isp_enable_hdr(dev);
  2769. break;
  2770. case ISPIOC_DISABLE_HDR:
  2771. viv_check_retval(copy_from_user
  2772. (&dev->hdr, args, sizeof(dev->hdr)));
  2773. ret = isp_disable_hdr(dev);
  2774. break;
  2775. case ISPIOC_S_HIST:
  2776. viv_check_retval(copy_from_user
  2777. (&dev->hist, args, sizeof(dev->hist)));
  2778. ret = isp_s_hist(dev);
  2779. break;
  2780. case ISPIOC_S_HDRHIST:
  2781. viv_check_retval(copy_from_user
  2782. (&dev->hdrhist, args, sizeof(dev->hdrhist)));
  2783. ret = isp_s_hdrhist(dev);
  2784. break;
  2785. #ifdef ISP_HIST64_RY
  2786. case ISPIOC_S_HIST64:
  2787. viv_check_retval(copy_from_user
  2788. (&dev->hist64, args, sizeof(dev->hist64)));
  2789. ret = isp_s_hist64(dev);
  2790. break;
  2791. case ISPIOC_U_HIST64:
  2792. viv_check_retval(copy_from_user
  2793. (&dev->hist64, args, sizeof(dev->hist64)));
  2794. ret = isp_update_hist64(dev);
  2795. break;
  2796. #endif
  2797. case ISPIOC_S_DPCC:
  2798. viv_check_retval(copy_from_user
  2799. (&dev->dpcc, args, sizeof(dev->dpcc)));
  2800. ret = isp_s_dpcc(dev);
  2801. break;
  2802. case ISPIOC_ENABLE_WDR3:
  2803. ret = isp_enable_wdr3(dev);
  2804. break;
  2805. case ISPIOC_DISABLE_WDR3:
  2806. ret = isp_disable_wdr3(dev);
  2807. break;
  2808. case ISPIOC_U_WDR3:
  2809. viv_check_retval(copy_from_user
  2810. (&dev->wdr3, args, sizeof(dev->wdr3)));
  2811. ret = isp_u_wdr3(dev);
  2812. break;
  2813. case ISPIOC_S_WDR3:
  2814. viv_check_retval(copy_from_user
  2815. (&dev->wdr3, args, sizeof(dev->wdr3)));
  2816. ret = isp_s_wdr3(dev);
  2817. break;
  2818. #ifdef ISP_WDR_V4
  2819. case ISPIOC_ENABLE_WDR4:
  2820. ret = isp_enable_wdr4(dev);
  2821. break;
  2822. case ISPIOC_DISABLE_WDR4:
  2823. ret = isp_disable_wdr4(dev);
  2824. break;
  2825. case ISPIOC_U_WDR4:
  2826. viv_check_retval(copy_from_user
  2827. (&dev->wdr4, args, sizeof(dev->wdr4)));
  2828. ret = isp_u_wdr4(dev);
  2829. break;
  2830. case ISPIOC_S_WDR4:
  2831. viv_check_retval(copy_from_user
  2832. (&dev->wdr4, args, sizeof(dev->wdr4)));
  2833. ret = isp_s_wdr4(dev);
  2834. break;
  2835. #endif
  2836. case ISPIOC_S_EXP2:
  2837. viv_check_retval(copy_from_user
  2838. (&dev->exp2, args, sizeof(dev->exp2)));
  2839. ret = isp_s_exp2(dev);
  2840. break;
  2841. case ISPIOC_S_EXP2_INPUTSEL:
  2842. viv_check_retval(copy_from_user
  2843. (&dev->exp2.input_select, args,
  2844. sizeof(dev->exp2.input_select)));
  2845. ret = isp_s_exp2_inputsel(dev);
  2846. break;
  2847. case ISPIOC_S_EXP2_SIZERATIO: {
  2848. u32 ratio;
  2849. viv_check_retval(copy_from_user(&ratio, args, sizeof(ratio)));
  2850. ret = isp_s_exp2_sizeratio(dev, ratio);
  2851. break;
  2852. }
  2853. case ISPIOC_S_2DNR:
  2854. viv_check_retval(copy_from_user
  2855. (&dev->dnr2, args, sizeof(dev->dnr2)));
  2856. ret = isp_s_2dnr(dev);
  2857. break;
  2858. case ISPIOC_S_SIMP:
  2859. viv_check_retval(copy_from_user
  2860. (&dev->simp, args, sizeof(dev->simp)));
  2861. ret = isp_s_simp(dev);
  2862. break;
  2863. case ISPIOC_S_COMP:
  2864. viv_check_retval(copy_from_user
  2865. (&dev->comp, args, sizeof(dev->comp)));
  2866. ret = isp_s_comp(dev);
  2867. break;
  2868. case ISPIOC_S_CPROC:
  2869. viv_check_retval(copy_from_user
  2870. (&dev->cproc, args, sizeof(dev->cproc)));
  2871. ret = isp_s_cproc(dev);
  2872. break;
  2873. case ISPIOC_S_XTALK:
  2874. viv_check_retval(copy_from_user
  2875. (&dev->xtalk, args, sizeof(dev->xtalk)));
  2876. ret = isp_s_xtalk(dev);
  2877. break;
  2878. case ISPIOC_S_ELAWB:
  2879. viv_check_retval(copy_from_user
  2880. (&dev->elawb, args, sizeof(dev->elawb)));
  2881. ret = isp_s_elawb(dev);
  2882. break;
  2883. case ISPIOC_S_INPUT:
  2884. viv_check_retval(copy_from_user
  2885. (&dev->ctx, args, sizeof(dev->ctx)));
  2886. ret = isp_s_input(dev);
  2887. break;
  2888. case ISPIOC_S_DEMOSAIC:
  2889. viv_check_retval(copy_from_user
  2890. (&dev->ctx, args, sizeof(dev->ctx)));
  2891. ret = isp_s_demosaic(dev);
  2892. break;
  2893. case ISPIOC_MI_START:
  2894. viv_check_retval(copy_from_user
  2895. (&dev->mi, args, sizeof(dev->mi)));
  2896. ret = isp_mi_start(dev);
  2897. break;
  2898. case ISPIOC_S_HDR_WB:
  2899. viv_check_retval(copy_from_user
  2900. (&dev->hdr, args, sizeof(dev->hdr)));
  2901. ret = isp_s_hdr_wb(dev);
  2902. break;
  2903. case ISPIOC_S_HDR_BLS:
  2904. viv_check_retval(copy_from_user
  2905. (&dev->hdr, args, sizeof(dev->hdr)));
  2906. ret = isp_s_hdr_bls(dev);
  2907. break;
  2908. case ISPIOC_S_HDR_DIGITAL_GAIN:
  2909. viv_check_retval(copy_from_user
  2910. (&dev->hdr, args, sizeof(dev->hdr)));
  2911. // ret = isp_s_hdr_digal_gain(dev);
  2912. break;
  2913. case ISPIOC_S_GAMMA_OUT:{
  2914. viv_check_retval(copy_from_user
  2915. (&dev->gamma_out, args,
  2916. sizeof(dev->gamma_out)));
  2917. ret = isp_s_gamma_out(dev);
  2918. break;
  2919. }
  2920. case ISPIOC_SET_BUFFER:{
  2921. struct isp_buffer_context buf;
  2922. viv_check_retval(copy_from_user
  2923. (&buf, args, sizeof(buf)));
  2924. #if defined(__KERNEL__) && defined(ENABLE_IRQ)
  2925. if (dev->alloc)
  2926. ret = dev->alloc(dev, &buf);
  2927. #else
  2928. ret = isp_set_buffer(dev, &buf);
  2929. #endif
  2930. break;
  2931. }
  2932. case ISPIOC_SET_BP_BUFFER:{
  2933. struct isp_bp_buffer_context buf;
  2934. viv_check_retval(copy_from_user
  2935. (&buf, args, sizeof(buf)));
  2936. ret = isp_set_bp_buffer(dev, &buf);
  2937. break;
  2938. }
  2939. case ISPIOC_START_CAPTURE:{
  2940. u32 num;
  2941. viv_check_retval(copy_from_user
  2942. (&num, args, sizeof(num)));
  2943. ret = isp_start_stream(dev, num);
  2944. if(!ret) {
  2945. dev->streaming = true;
  2946. }
  2947. break;
  2948. }
  2949. #if defined(ISP_3DNR_V2) || defined(ISP_3DNR_V2_V1)
  2950. case ISPIOC_S_3DNR_CMP: {
  2951. viv_check_retval(
  2952. copy_from_user(&dev->dnr3.compress, args, sizeof(dev->dnr3.compress)));
  2953. ret = isp_s_3dnr_cmp(dev);
  2954. break;
  2955. }
  2956. #endif
  2957. #if defined(ISP_3DNR) || defined(ISP_3DNR_V2)
  2958. case ISPIOC_U_3DNR:{
  2959. struct isp_3dnr_update param;
  2960. viv_check_retval(copy_from_user
  2961. (&param, args, sizeof(param)));
  2962. ret = isp_u_3dnr(dev, &param);
  2963. break;
  2964. }
  2965. case ISPIOC_S_3DNR:
  2966. viv_check_retval(copy_from_user
  2967. (&dev->dnr3, args, sizeof(dev->dnr3)));
  2968. ret = isp_s_3dnr(dev);
  2969. break;
  2970. case ISPIOC_U_3DNR_STRENGTH: {
  2971. viv_check_retval(
  2972. copy_from_user(&dev->dnr3, args, sizeof(dev->dnr3)));
  2973. ret = isp_u_3dnr_strength(dev);
  2974. break;
  2975. }
  2976. case ISPIOC_S_3DNR_MOT:{
  2977. viv_check_retval(copy_from_user
  2978. (&dev->dnr3, args, sizeof(dev->dnr3)));
  2979. ret = isp_s_3dnr_motion(dev);
  2980. break;
  2981. }
  2982. case ISPIOC_S_3DNR_DLT:{
  2983. viv_check_retval(copy_from_user
  2984. (&dev->dnr3, args, sizeof(dev->dnr3)));
  2985. ret = isp_s_3dnr_delta(dev);
  2986. break;
  2987. }
  2988. case ISPIOC_G_3DNR:{
  2989. u32 avg;
  2990. ret = isp_g_3dnr(dev, &avg);
  2991. viv_check_retval(copy_to_user(args, &avg, sizeof(avg)));
  2992. break;
  2993. }
  2994. #endif
  2995. case ISPIOC_G_AWBMEAN:{
  2996. struct isp_awb_mean mean;
  2997. ret = isp_g_awbmean(dev, &mean);
  2998. viv_check_retval(copy_to_user
  2999. (args, &mean, sizeof(mean)));
  3000. break;
  3001. }
  3002. case ISPIOC_G_EXPMEAN:{
  3003. u8 mean[25];
  3004. ret = isp_g_expmean(dev, mean);
  3005. viv_check_retval(copy_to_user
  3006. (args, mean, sizeof(mean)));
  3007. break;
  3008. }
  3009. case ISPIOC_G_HDREXPMEAN:{
  3010. u8 mean[75];
  3011. ret = isp_g_hdrexpmean(dev, mean);
  3012. viv_check_retval(copy_to_user
  3013. (args, mean, sizeof(mean)));
  3014. break;
  3015. }
  3016. case ISPIOC_G_HISTMEAN:{
  3017. u32 mean[HIST_BIN_TOTAL];
  3018. ret = isp_g_histmean(dev, mean);
  3019. viv_check_retval(copy_to_user
  3020. (args, mean, sizeof(mean)));
  3021. break;
  3022. }
  3023. case ISPIOC_G_HDRHISTMEAN:{
  3024. u32 mean[48];
  3025. ret = isp_g_hdrhistmean(dev, mean);
  3026. viv_check_retval(copy_to_user
  3027. (args, mean, sizeof(mean)));
  3028. break;
  3029. }
  3030. #ifdef ISP_HIST64_RY
  3031. case ISPIOC_G_HIST64MEAN:{
  3032. u32 mean[HIST64_BIN_TOTAL];
  3033. ret = isp_g_hist64mean(dev, mean);
  3034. viv_check_retval(copy_to_user
  3035. (args, mean, sizeof(mean)));
  3036. break;
  3037. }
  3038. case ISPIOC_G_HIST64VSTART_STATUS:{
  3039. u32 status = 0;
  3040. ret = isp_g_hist64_vstart_status(dev, &status);
  3041. viv_check_retval(copy_to_user
  3042. (args, &status, sizeof(status)));
  3043. break;
  3044. }
  3045. #endif
  3046. case ISPIOC_G_VSM:{
  3047. struct isp_vsm_result vsm;
  3048. ret = isp_g_vsm(dev, &vsm);
  3049. viv_check_retval(copy_to_user(args, &vsm, sizeof(vsm)));
  3050. break;
  3051. }
  3052. case ISPIOC_G_AFM:{
  3053. struct isp_afm_result afm;
  3054. ret = isp_g_afm(dev, &afm);
  3055. viv_check_retval(copy_to_user(args, &afm, sizeof(afm)));
  3056. break;
  3057. }
  3058. case ISPIOC_G_STATUS:
  3059. ret = isp_ioc_g_status(dev, args);
  3060. break;
  3061. case ISPIOC_G_FEATURE:
  3062. ret = isp_ioc_g_feature(dev, args);
  3063. break;
  3064. case ISPIOC_G_FEATURE_VERSION:
  3065. ret = isp_ioc_g_feature_veresion(dev, args);
  3066. break;
  3067. case ISPIOC_WDR_CONFIG:
  3068. viv_check_retval(copy_from_user
  3069. (&dev->wdr, args, sizeof(dev->wdr)));
  3070. ret = isp_s_wdr(dev);
  3071. break;
  3072. case ISPIOC_S_WDR_CURVE:
  3073. viv_check_retval(copy_from_user
  3074. (&dev->wdr, args, sizeof(dev->wdr)));
  3075. ret = isp_s_wdr_curve(dev);
  3076. break;
  3077. case ISPIOC_ENABLE_GCMONO:
  3078. viv_check_retval(copy_from_user
  3079. (&dev->gcmono.mode, args, sizeof(u32)));
  3080. ret = isp_enable_gcmono(dev);
  3081. break;
  3082. case ISPIOC_DISABLE_GCMONO:
  3083. ret = isp_disable_gcmono(dev);
  3084. break;
  3085. case ISPIOC_S_GCMONO:{
  3086. struct isp_gcmono_data *data;
  3087. #ifdef __KERNEL__
  3088. data = (struct isp_gcmono_data *)
  3089. kmalloc(sizeof(struct isp_gcmono_data), GFP_KERNEL);
  3090. #else
  3091. data = (struct isp_gcmono_data *)
  3092. malloc(sizeof(struct isp_gcmono_data));
  3093. #endif
  3094. if (data == NULL) {
  3095. isp_err("%s, malloc mem for rgb gamma failed.", __func__);
  3096. ret = -1;
  3097. } else {
  3098. viv_check_retval(copy_from_user
  3099. (data, args,
  3100. sizeof(struct
  3101. isp_gcmono_data)));
  3102. ret = isp_s_gcmono(dev, data);
  3103. #ifdef __KERNEL__
  3104. kfree(data);
  3105. #else
  3106. free(data);
  3107. #endif
  3108. }
  3109. break;
  3110. }
  3111. case ISPIOC_ENABLE_RGBGAMMA:
  3112. ret = isp_enable_rgbgamma(dev);
  3113. break;
  3114. case ISPIOC_DISABLE_RGBGAMMA:
  3115. ret = isp_disable_rgbgamma(dev);
  3116. break;
  3117. case ISPIOC_S_RGBGAMMA:{
  3118. struct isp_rgbgamma_data *data;
  3119. #ifdef __KERNEL__
  3120. data = (struct isp_rgbgamma_data *)
  3121. kmalloc(sizeof(struct isp_rgbgamma_data),
  3122. GFP_KERNEL);
  3123. #else
  3124. data = (struct isp_rgbgamma_data *)
  3125. malloc(sizeof(struct isp_rgbgamma_data));
  3126. #endif
  3127. if (data == NULL) {
  3128. isp_err("%s, malloc mem for rgb gamma failed.", __func__);
  3129. ret = -1;
  3130. } else {
  3131. viv_check_retval(copy_from_user
  3132. (data, args,
  3133. sizeof(struct
  3134. isp_rgbgamma_data)));
  3135. dev->rgbgamma.data = data;
  3136. ret = isp_s_rgbgamma(dev);
  3137. }
  3138. break;
  3139. }
  3140. case ISPIOC_S_GREENEQUILIBRATE:
  3141. viv_check_retval(copy_from_user
  3142. (&dev->ge, args, sizeof(dev->ge)));
  3143. ret = isp_s_ge(dev);
  3144. break;
  3145. case ISPIOC_S_COLOR_ADJUST:
  3146. viv_check_retval(copy_from_user
  3147. (&dev->ca, args, sizeof(dev->ca)));
  3148. ret = isp_s_ca(dev);
  3149. break;
  3150. #ifdef __KERNEL__
  3151. case VIDIOC_QUERYCAP:
  3152. ret = isp_ioc_qcap(dev, args);
  3153. break;
  3154. #endif
  3155. case ISPIOC_G_QUERY_EXTMEM:
  3156. ret = isp_get_extmem(dev, args);
  3157. break;
  3158. case ISPIOC_ENABLE_RGBIR:
  3159. viv_check_retval(copy_from_user
  3160. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3161. ret = isp_enable_rgbir(dev);
  3162. break;
  3163. case ISPIOC_S_RGBIR:
  3164. viv_check_retval(copy_from_user
  3165. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3166. ret = isp_s_rgbir(dev);
  3167. break;
  3168. case ISPIOC_RGBIR_HW_INIT:
  3169. viv_check_retval(copy_from_user
  3170. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3171. ret = isp_rgbir_hw_init(dev);
  3172. break;
  3173. case ISPIOC_RGBIR_S_IR_DNR:
  3174. viv_check_retval(copy_from_user
  3175. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3176. ret = isp_rgbir_s_ir_dnr(dev);
  3177. break;
  3178. case ISPIOC_RGBIR_S_SHARPEN:
  3179. viv_check_retval(copy_from_user
  3180. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3181. ret = isp_rgbir_s_sharpen(dev);
  3182. break;
  3183. case ISPIOC_RGBIR_S_DES:
  3184. viv_check_retval(copy_from_user
  3185. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3186. ret = isp_rgbir_s_des(dev);
  3187. break;
  3188. case ISPIOC_RGBIR_S_CC_MATRIX:
  3189. viv_check_retval(copy_from_user
  3190. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3191. ret = isp_rgbir_s_cc_matrix(dev);
  3192. break;
  3193. case ISPIOC_RGBIR_S_DPCC:
  3194. viv_check_retval(copy_from_user
  3195. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3196. ret = isp_rgbir_s_dpcc(dev);
  3197. break;
  3198. case ISPIOC_RGBIR_S_GAIN:
  3199. viv_check_retval(copy_from_user
  3200. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3201. ret = isp_rgbir_s_gain(dev);
  3202. break;
  3203. case ISPIOC_RGBIR_S_BLS:
  3204. viv_check_retval(copy_from_user
  3205. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3206. ret = isp_rgbir_s_bls(dev);
  3207. break;
  3208. case ISPIOC_RGBIR_S_IR_RAW_OUT:
  3209. viv_check_retval(copy_from_user
  3210. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3211. ret = isp_rgbir_out_ir_raw(dev);
  3212. break;
  3213. case ISPIOC_S_CROP:
  3214. viv_check_retval(copy_from_user
  3215. (&dev->crop, args, sizeof(struct isp_crop_context) * 3));
  3216. ret = isp_set_crop(dev);
  3217. break;
  3218. #ifdef ISP_3DNR_V3
  3219. case ISPIOC_S_TDNR:
  3220. viv_check_retval(copy_from_user
  3221. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3222. ret = isp_s_tdnr(dev);
  3223. break;
  3224. case ISPIOC_TDNR_ENABLE:
  3225. ret = isp_tdnr_enable(dev);
  3226. break;
  3227. case ISPIOC_TDNR_DISABLE:
  3228. ret = isp_tdnr_disable(dev);
  3229. break;
  3230. case ISPIOC_TDNR_ENABLE_TDNR:
  3231. ret = isp_tdnr_enable_tdnr(dev);
  3232. break;
  3233. case ISPIOC_TDNR_DISABLE_TDNR:
  3234. ret = isp_tdnr_disable_tdnr(dev);
  3235. break;
  3236. case ISPIOC_TDNR_ENABLE_2DNR:
  3237. ret = isp_tdnr_enable_2dnr(dev);
  3238. break;
  3239. case ISPIOC_TDNR_DISABLE_2DNR:
  3240. ret = isp_tdnr_disable_2dnr(dev);
  3241. break;
  3242. case ISPIOC_S_TDNR_CURVE:
  3243. viv_check_retval(copy_from_user
  3244. (&dev->tdnr.curve, args, sizeof(dev->tdnr.curve)));
  3245. ret = isp_tdnr_cfg_gamma(dev);
  3246. break;
  3247. case ISPIOC_G_TDNR: {
  3248. struct isp_tdnr_stats stats;
  3249. ret = isp_tdnr_g_stats(dev, &stats);
  3250. viv_check_retval(copy_to_user(args, &stats, sizeof(stats)));
  3251. }
  3252. break;
  3253. case ISPIOC_S_TDNR_STRENGTH:
  3254. viv_check_retval(copy_from_user
  3255. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3256. ret = isp_tdnr_set_strength(dev);
  3257. break;
  3258. case ISPIOC_U_TDNR_NOISE:
  3259. viv_check_retval(copy_from_user
  3260. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3261. ret = isp_tdnr_u_noise(dev);
  3262. break;
  3263. case ISPIOC_U_TDNR_THR:
  3264. viv_check_retval(copy_from_user
  3265. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3266. ret = isp_tdnr_u_thr(dev);
  3267. break;
  3268. case ISPIOC_R_TDNR_REFER:
  3269. ret = isp_r_tdnr_refer(dev);
  3270. break;
  3271. case ISPIOC_R_TDNR_MOTION:
  3272. ret = isp_r_tdnr_motion(dev);
  3273. break;
  3274. case ISPIOC_S_TDNR_BUF:
  3275. viv_check_retval(copy_from_user
  3276. (&dev->tdnr.buf, args, sizeof(dev->tdnr.buf)));
  3277. ret = isp_tdnr_s_buf(dev);
  3278. break;
  3279. #endif
  3280. #ifdef ISP_MI_PP_WRITE_RY
  3281. case ISPIOC_GET_PPW_LINE_CNT:
  3282. {
  3283. u16 ppw_pic_cnt;
  3284. ret = isp_get_ppw_pic_cnt(dev, &ppw_pic_cnt);
  3285. viv_check_retval(copy_to_user
  3286. (args, &ppw_pic_cnt, sizeof(ppw_pic_cnt)));
  3287. break;
  3288. }
  3289. case ISPIOC_SET_PPW_LINE_NUM:
  3290. {
  3291. viv_check_retval(copy_from_user
  3292. (&dev->pp_write, args, sizeof(dev->pp_write)));
  3293. ret = isp_set_ppw_line_num(dev);
  3294. break;
  3295. }
  3296. #endif
  3297. #ifdef ISP_MI_PP_READ_RY
  3298. case ISPIOC_CFG_DMA_LINE_ENTRY:
  3299. viv_check_retval(copy_from_user
  3300. (&dev->pp_dma_line_entry, args, sizeof(dev->pp_dma_line_entry)));
  3301. ret = isp_cfg_pp_dma_line_entry(dev);
  3302. break;
  3303. #endif
  3304. default:
  3305. isp_err("unsupported command %d", cmd);
  3306. break;
  3307. }
  3308. if (cmd != ISPIOC_WRITE_REG) //frame end isp update shd registers.
  3309. ISP_GEN_CFG_UPDATE(dev);
  3310. return ret;
  3311. }