ic_dev.h 23 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. #ifndef _ISP_DEV_H_
  54. #define _ISP_DEV_H_
  55. #ifndef __KERNEL__
  56. #include <stdlib.h>
  57. #include <stdint.h>
  58. #include <stdbool.h>
  59. #include <errno.h>
  60. #define copy_from_user(a, b, c) isp_copy_data(a, b, c)
  61. #define copy_to_user(a, b, c) isp_copy_data(a, b, c)
  62. #if defined(HAL_CMODEL) || defined(HAL_ALTERA) || defined ( HAL_LIGHT_FPGA )
  63. #include <hal/hal_api_ry.h>
  64. void isp_ic_set_hal(HalHandle_t hal);
  65. #endif
  66. #endif
  67. #include "isp_irq_queue.h"
  68. #include "isp_version.h"
  69. #include "vvdefs.h"
  70. #define REG_ADDR(x) ((uint32_t)(uintptr_t)&all_regs->x)
  71. #ifdef ISP_MIV1
  72. #define ISP_BUF_GAP (1024)
  73. #elif defined ISP_MIV2_RY
  74. #define ISP_BUF_GAP (0)
  75. #endif
  76. #ifdef ISP_MI_BP
  77. # define MI_PATH_NUM (3)
  78. #else
  79. # define MI_PATH_NUM (2)
  80. #endif
  81. struct isp_reg_t {
  82. u32 offset;
  83. u32 val;
  84. };
  85. struct ic_window {
  86. u16 x;
  87. u16 y;
  88. u16 width;
  89. u16 height;
  90. };
  91. struct isp_context {
  92. u32 mode;
  93. u32 sample_edge;
  94. bool hSyncLowPolarity, vSyncLowPolarity;
  95. u32 bayer_pattern;
  96. u32 sub_sampling;
  97. u32 seq_ccir;
  98. u32 field_selection;
  99. u32 input_selection;
  100. u32 latency_fifo;
  101. struct ic_window acqWindow; /**< acquisition window */
  102. struct ic_window ofWindow; /**< output formatter window */
  103. struct ic_window isWindow; /**< image stabilization output window */
  104. u32 bypass_mode;
  105. u8 demosaic_threshold;
  106. u32 stitching_mode;
  107. };
  108. typedef struct isp_wdr_context
  109. {
  110. bool enabled;
  111. bool changed; //the wdr ctrl && reb shift does not have shandow
  112. //register,need to change after frame end irq.
  113. u16 LumOffset;
  114. u16 RgbOffset;
  115. u16 Ym[33];
  116. u8 dY[33];
  117. } isp_wdr_context_t;
  118. struct isp_digital_gain_cxt {
  119. /* data */
  120. bool enable;
  121. u16 gain_r;
  122. u16 gain_b;
  123. u16 gain_gr;
  124. u16 gain_gb;
  125. };
  126. struct isp_mi_data_path_context {
  127. bool enable;
  128. u32 out_mode; /**< output format */
  129. u32 in_mode; /**< input format */
  130. u32 data_layout; /**< layout of data */
  131. u32 data_alignMode; /**< align mode of data */
  132. u32 in_width;
  133. u32 in_height;
  134. u32 out_width;
  135. u32 out_height;
  136. bool hscale;
  137. bool vscale;
  138. int pixelformat;
  139. bool yuv_bit;
  140. };
  141. struct isp_dummy_hblank_cxt {
  142. u8 bp, fp, w, in_hsize;
  143. };
  144. enum MIV2_PATH_ID {
  145. ISP_MI_PATH_MP = 0,
  146. ISP_MI_PATH_SP,
  147. ISP_MI_PATH_SP2_BP,
  148. #ifdef ISP_MI_MCM_WR_RY
  149. ISP_MI_MCM_WR0,
  150. ISP_MI_MCM_WR1,
  151. #endif
  152. ISP_MI_PATH_PP,
  153. #ifdef ISP_MI_HDR_RY
  154. ISP_MI_HDR_L,
  155. ISP_MI_HDR_S,
  156. ISP_MI_HDR_VS,
  157. #endif
  158. ISP_MI_PATH_ID_MAX
  159. };
  160. enum DMA_ID {
  161. ISP_MI_DMA_ID_MCM_PP = 0,
  162. ISP_MI_DMA_ID_HDR_L,
  163. ISP_MI_DMA_ID_HDR_S,
  164. ISP_MI_DMA_ID_HDR_VS,
  165. ISP_MI_DMA_ID_MAX
  166. };
  167. typedef enum start_dma_path_e{
  168. ISP_MI_DMA_PATH_MCM_PP = 0,
  169. ISP_MI_DMA_PATH_HDR,
  170. ISP_MI_DMA_PATH_MAX,
  171. }start_dma_path_t;
  172. struct isp_mi_context {
  173. struct isp_mi_data_path_context path[ISP_MI_PATH_ID_MAX];
  174. u32 burst_len;
  175. };
  176. struct isp_bls_context {
  177. bool enabled;
  178. u32 mode;
  179. u16 a, b, c, d;
  180. };
  181. struct isp_tpg_userdefine_mode {
  182. u16 total, fp, sync, bp, act;
  183. };
  184. struct isp_tpg_context {
  185. bool enabled;
  186. u32 image_type;
  187. u32 frame_num;
  188. u32 bayer_pattern;
  189. u32 color_depth;
  190. u32 resolution;
  191. u16 pixleGap;
  192. u16 lineGap;
  193. u16 gapStandard;
  194. u32 randomSeed;
  195. struct isp_tpg_userdefine_mode user_mode_h, user_mode_v;
  196. };
  197. typedef enum mcm_fmt_e{
  198. MCM_FMT_RAW8 = 0,
  199. MCM_FMT_RAW10,
  200. MCM_FMT_RAW12,
  201. MCM_FMT_RAW14,
  202. MCM_FMT_RAW16,
  203. MCM_FMT_RAW20,
  204. MCM_FMT_MAX,
  205. }mcm_fmt_t;
  206. typedef enum mcm_wr_index_e{
  207. MCM_INDEX_WR0 = 0, //write channel 0
  208. MCM_INDEX_WR1, //write channel 1
  209. MCM_INDEX_G2_WR0, //MCM_G2 writec channel 0
  210. MCM_INDEX_G2_WR1, //MCM_G2 writec channel 1
  211. MCM_INDEX_WR_MAX,
  212. }mcm_wr_fmt_t;
  213. struct isp_mcm_context {
  214. bool sensor_mem_bypass; //0: use sensor latency memory in MCM
  215. mcm_fmt_t wr_fmt[MCM_INDEX_WR_MAX];
  216. u8 bypass_switch; //Bypass switch 0000: sensor0 bypass 0001:sensor1 bypass .. 1111:sensor15 bypass if any
  217. u16 height[MCM_INDEX_WR_MAX];
  218. u16 width[MCM_INDEX_WR_MAX];
  219. mcm_fmt_t rd_fmt;
  220. u32 hsync_rpeample_ext;
  221. bool bypass_enable;
  222. u32 vsync_blank;
  223. u32 vsync_duration;
  224. u32 hsync_blank;
  225. u32 hsync_preample;
  226. };
  227. struct isp_mux_context {
  228. u32 mp_mux; /**< main path muxer (vi_mp_mux) */
  229. u32 sp_mux; /**< self path muxer (vi_dma_spmux) */
  230. u32 chan_mode; /**< 1-mp, 2-sp, 4-sp2 */
  231. u32 ie_mux; /**< image effects muxer (vi_dma_iemux) */
  232. u32 dma_read_switch; /**< dma read switch (vi_dma_switch) */
  233. u32 if_select; /**< interface selector (if_select) */
  234. };
  235. struct isp_awb_context {
  236. bool enable;
  237. u8 mode;
  238. u16 gain_r, gain_gr, gain_gb, gain_b;
  239. struct ic_window window;
  240. u16 refcb_max_b;
  241. u16 refcr_max_r;
  242. u16 max_y;
  243. u16 max_c_sum;
  244. u16 min_y_max_g;
  245. u16 min_c;
  246. };
  247. struct isp_awb_mean {
  248. u32 r, g, b;
  249. u32 no_white_count;
  250. };
  251. struct isp_cnr_context {
  252. bool enable;
  253. u32 line_width;
  254. u32 threshold_1;
  255. u32 threshold_2;
  256. };
  257. struct isp_cc_context {
  258. u32 lCoeff[9];
  259. bool update_curve;
  260. bool conv_range_y_full, conv_range_c_full;
  261. };
  262. struct isp_xtalk_context {
  263. u32 lCoeff[9];
  264. u32 r, g, b;
  265. };
  266. struct isp_gamma_out_context {
  267. bool enableWB, enableGamma;
  268. bool changed;
  269. u32 mode;
  270. u32 curve[17];
  271. };
  272. #define CAEMRIC_GRAD_TBL_SIZE 8
  273. #define CAMERIC_DATA_TBL_SIZE 289
  274. #define CAMERIC_MAX_LSC_SECTORS 16
  275. #define CA_CURVE_DATA_TABLE_LEN 65
  276. struct isp_lsc_context {
  277. /**< correction values of R color part */
  278. u16 r[CAMERIC_DATA_TBL_SIZE];
  279. /**< correction values of G (red lines) color part */
  280. u16 gr[CAMERIC_DATA_TBL_SIZE];
  281. /**< correction values of G (blue lines) color part */
  282. u16 gb[CAMERIC_DATA_TBL_SIZE];
  283. /**< correction values of B color part */
  284. u16 b[CAMERIC_DATA_TBL_SIZE];
  285. /**< multiplication factors of x direction */
  286. u16 x_grad[CAEMRIC_GRAD_TBL_SIZE];
  287. /**< multiplication factors of y direction */
  288. u16 y_grad[CAEMRIC_GRAD_TBL_SIZE];
  289. /**< sector sizes of x direction */
  290. u16 x_size[CAEMRIC_GRAD_TBL_SIZE];
  291. /**< sector sizes of y direction */
  292. u16 y_size[CAEMRIC_GRAD_TBL_SIZE];
  293. };
  294. struct isp_dmoi_context {
  295. bool enable;
  296. uint8_t demoire_area_thr;
  297. uint8_t demoire_sat_shrink;
  298. uint16_t demoire_r2;
  299. uint16_t demoire_r1;
  300. uint8_t demoire_t2_shift;
  301. uint8_t demoire_t1;
  302. uint16_t demoire_edge_r2;
  303. uint16_t demoire_edge_r1;
  304. uint8_t demoire_edge_t2_shift;
  305. uint16_t demoire_edge_t1;
  306. };
  307. struct isp_shap_context {
  308. bool enable;
  309. uint16_t sharpen_factor_black;
  310. uint16_t sharpen_factor_white;
  311. uint16_t sharpen_clip_black;
  312. uint16_t sharpen_clip_white;
  313. uint16_t sharpen_t4_shift;
  314. uint16_t sharpen_t3;
  315. uint8_t sharpen_t2_shift;
  316. uint16_t sharpen_t1;
  317. uint16_t sharpen_r3;
  318. uint16_t sharpen_r2;
  319. uint16_t sharpen_r1;
  320. };
  321. struct isp_shap_line_context {
  322. bool enable;
  323. uint8_t sharpen_line_shift2;
  324. uint8_t sharpen_line_shift1;
  325. uint16_t sharpen_line_t1;
  326. uint16_t sharpen_line_strength;
  327. uint16_t sharpen_line_r2;
  328. uint16_t sharpen_line_r1;
  329. };
  330. struct isp_gfilter_context {
  331. uint8_t sharpen_size;
  332. uint8_t hf_filt_00;
  333. uint8_t hf_filt_01;
  334. uint8_t hf_filt_02;
  335. uint8_t hf_filt_10;
  336. uint8_t hf_filt_11;
  337. uint8_t hf_filt_12;
  338. uint8_t hf_filt_20;
  339. uint8_t hf_filt_21;
  340. uint8_t hf_filt_22;
  341. };
  342. struct isp_skin_context {
  343. bool enable;
  344. uint16_t cb_thr_max_2047;
  345. uint16_t cb_thr_min_2047;
  346. uint16_t cr_thr_max_2047;
  347. uint16_t cr_thr_min_2047;
  348. uint16_t y_thr_max_2047;
  349. uint16_t y_thr_min_2047;
  350. };
  351. struct isp_depurple_context {
  352. bool enable;
  353. bool red_sat, blue_sat;
  354. uint8_t depurple_sat_shrink;
  355. uint8_t depurple_thr;
  356. };
  357. struct isp_intp_thr_cxt {
  358. u16 intp_dir_thr_min;
  359. u16 intp_dir_thr_max;
  360. };
  361. struct isp_dmsc_context {
  362. bool enable;
  363. uint8_t demosaic_thr;
  364. uint8_t denoise_stren;
  365. struct isp_intp_thr_cxt intp;
  366. struct isp_dmoi_context demoire;
  367. struct isp_shap_context sharpen;
  368. struct isp_gfilter_context gFilter;
  369. struct isp_shap_line_context sharpenLine;
  370. struct isp_skin_context skin;
  371. struct isp_depurple_context depurple;
  372. };
  373. struct isp_ge_context {
  374. bool enable;
  375. u16 threshold;
  376. u16 h_dummy;
  377. };
  378. struct isp_ca_context {
  379. bool enable;
  380. u8 mode;
  381. u16 lut_x[CA_CURVE_DATA_TABLE_LEN];
  382. u16 lut_luma[CA_CURVE_DATA_TABLE_LEN];
  383. u16 lut_chroma[CA_CURVE_DATA_TABLE_LEN];
  384. u16 lut_shift[CA_CURVE_DATA_TABLE_LEN];
  385. };
  386. struct isp_buffer_context {
  387. u32 type;
  388. u32 path;
  389. u32 addr_y, addr_cb, addr_cr;
  390. u32 size_y, size_cb, size_cr;
  391. };
  392. struct isp_bp_buffer_context {
  393. u32 addr_r;
  394. u32 addr_gr;
  395. u32 addr_gb;
  396. u32 addr_b;
  397. };
  398. struct isp_dma_context {
  399. u32 type;
  400. u32 base;
  401. u32 width;
  402. u32 height;
  403. u32 burst_y;
  404. u32 burst_c;
  405. u8 align;
  406. u8 id;
  407. #ifdef ISP_MI_HDR_RY
  408. u8 rd_wr_str;
  409. #endif
  410. };
  411. struct isp_dpf_context {
  412. bool enable;
  413. u32 filter_type;
  414. u32 gain_usage;
  415. u32 strength_r;
  416. u32 strength_g;
  417. u32 strength_b;
  418. u8 weight_g[6];
  419. u8 weight_rb[6];
  420. u16 denoise_talbe[17];
  421. u32 x_scale;
  422. u32 nf_gain_r;
  423. u32 nf_gain_gr;
  424. u32 nf_gain_gb;
  425. u32 nf_gain_b;
  426. bool filter_r_off;
  427. bool filter_gr_off;
  428. bool filter_gb_off;
  429. bool filter_b_off;
  430. };
  431. struct isp_is_context {
  432. bool enable;
  433. bool update;
  434. struct ic_window window;
  435. u32 recenter;
  436. u32 max_dx, max_dy;
  437. u32 displace_x, displace_y;
  438. };
  439. struct isp_ee_context {
  440. bool enable;
  441. u8 src_strength;
  442. u8 strength;
  443. u8 input_sel;
  444. u32 y_gain, uv_gain, edge_gain;
  445. };
  446. struct isp_exp_context {
  447. bool enable;
  448. u32 mode;
  449. struct ic_window window;
  450. };
  451. struct isp_hist_context {
  452. bool enable;
  453. u32 mode;
  454. u32 step_size;
  455. struct ic_window window;
  456. u8 weight[25];
  457. };
  458. struct isp_hist64_context {
  459. bool enable;
  460. u8 channel;
  461. u32 mode;
  462. u8 vStepSize;
  463. u32 hStepInc;
  464. u8 r_coeff, g_coeff, b_coeff;
  465. u8 sample_shift;
  466. u16 sample_offset;
  467. u16 forced_upd_start_line;
  468. bool forced_upd;
  469. struct ic_window window;
  470. u8 weight[25];
  471. };
  472. struct isp_dpcc_params {
  473. u32 line_thresh;
  474. u32 line_mad_fac;
  475. u32 pg_fac;
  476. u32 rnd_thresh;
  477. u32 rg_fac;
  478. };
  479. struct isp_dpcc_context {
  480. bool enable;
  481. u32 mode;
  482. u32 outmode;
  483. u32 set_use;
  484. u32 methods_set[3];
  485. struct isp_dpcc_params params[3];
  486. u32 ro_limits;
  487. u32 rnd_offs;
  488. };
  489. struct isp_flt_context {
  490. bool enable;
  491. bool changed;
  492. u32 denoise;
  493. u32 sharpen;
  494. };
  495. struct isp_cac_context {
  496. bool enable;
  497. u32 hmode, vmode;
  498. u32 ab, ar, bb, br, cb, cr;
  499. u32 xns, xnf, yns, ynf;
  500. u32 hstart, vstart;
  501. };
  502. /* degamma */
  503. struct isp_deg_context {
  504. bool enable;
  505. u8 segment[16];
  506. u16 r[17];
  507. u16 g[17];
  508. u16 b[17];
  509. };
  510. struct isp_ie_context {
  511. bool enable;
  512. u32 mode;
  513. u32 color_sel;
  514. u32 color_thresh;
  515. u32 sharpen_factor;
  516. u32 sharpen_thresh;
  517. int32_t m[9];
  518. u32 tint_cr;
  519. u32 tint_cb;
  520. bool full_range;
  521. };
  522. struct isp_afm_result {
  523. u32 sum_a, sum_b, sum_c;
  524. u32 lum_a, lum_b, lum_c;
  525. };
  526. struct isp_afm_context {
  527. bool enable;
  528. u32 thresh;
  529. struct ic_window window[3];
  530. u32 pixCnt[3];
  531. bool enableWinId[3];
  532. u32 lum_shift;
  533. u32 afm_shift;
  534. u32 max_pix_cnt;
  535. };
  536. struct isp_vsm_result {
  537. u32 x, y;
  538. };
  539. struct isp_vsm_context {
  540. bool enable;
  541. struct ic_window window;
  542. u32 h_seg, v_seg;
  543. };
  544. #ifndef WDR3_BIN
  545. #define WDR3_BIN 14
  546. #endif
  547. struct isp_wdr3_context {
  548. bool enable;
  549. bool changed;
  550. bool inited;
  551. u32 strength;
  552. u32 max_gain;
  553. u32 global_strength;
  554. u32 histogram[WDR3_BIN];
  555. u32 shift[WDR3_BIN];
  556. u32 invert_linear[WDR3_BIN];
  557. u32 invert_curve[WDR3_BIN];
  558. u32 gamma_pre[WDR3_BIN];
  559. u32 gamma_up[WDR3_BIN];
  560. u32 gamma_down[WDR3_BIN];
  561. u32 entropy[WDR3_BIN];
  562. u32 distance_weight[WDR3_BIN];
  563. u32 difference_weight[WDR3_BIN];
  564. };
  565. #ifdef ISP_WDR_V4
  566. #ifndef WDR4_BIN
  567. #define WDR4_BIN 20
  568. #endif
  569. struct isp_wdr4_context {
  570. bool enable;
  571. bool changed;
  572. bool inited;
  573. u8 ratioLSVS, ratioLS;
  574. u8 drc_bayer_ratio, drc_bayer_ratioLSVS;
  575. u32 strength;
  576. u32 high_strength;
  577. u32 low_strength;
  578. u32 low_gain;
  579. u32 global_strength;
  580. int contrast;
  581. u32 flat_strength;
  582. u32 flat_threshold;
  583. u32 histogram[WDR4_BIN];
  584. u32 shift[WDR4_BIN];
  585. u32 shift0[WDR4_BIN];
  586. u32 invert_linear[WDR4_BIN];
  587. u32 invert_curve[WDR4_BIN];
  588. u32 gamma_pre[WDR4_BIN];
  589. u32 gamma_up[WDR4_BIN];
  590. u32 gamma_down[WDR4_BIN];
  591. u32 entropy[WDR4_BIN];
  592. u32 distance_weight[WDR4_BIN];
  593. u32 difference_weight[WDR4_BIN];
  594. u32 smooth_invert[WDR4_BIN];
  595. };
  596. #endif
  597. #ifndef ISP_AEV2_V2_RY
  598. #define AEV2_DMA_SIZE 4096
  599. #else
  600. #define AEV2_DMA_SIZE (4096 *2)
  601. #endif
  602. struct isp_exp2_context {
  603. bool enable;
  604. struct ic_window window;
  605. /* weight; */
  606. u8 r, gr, gb, b;
  607. u8 input_select; //00: degamma output, 01: awb_gain output 10: WDR3 output
  608. /* write 4096/8192 EXPV2 mean value to dma by MI MP-JDP path. */
  609. /* physical address, alloacte by user */
  610. u64 pa;
  611. uint8_t* va;
  612. };
  613. #define ISP_2DNR_SIGMA_BIN 60
  614. struct isp_2dnr_context {
  615. bool enable;
  616. u32 pre_gamma;
  617. u32 strength;
  618. u16 sigma[ISP_2DNR_SIGMA_BIN];
  619. #if defined(ISP_2DNR_V2) || defined(ISP_2DNR_V4)
  620. u32 sigma_sqr;
  621. u32 weight;
  622. #endif
  623. #ifdef ISP_2DNR_V4
  624. u16 str_off;
  625. u16 str_max;
  626. u8 str_slope;
  627. #endif
  628. };
  629. struct isp_3dnr_compress_context {
  630. u8 weight_up_y[2];
  631. u8 weight_down[4];
  632. u8 weight_up[8];
  633. };
  634. struct isp_3dnr_context {
  635. bool enable;
  636. bool update_bin;
  637. bool enable_h, enable_v;
  638. bool enable_temperal;
  639. bool enable_dilate;
  640. bool init;
  641. u32 spacial_curve[17];
  642. u32 temperal_curve[17];
  643. u32 strength;
  644. u16 motion_factor;
  645. u16 delta_factor;
  646. /* write full denoise3d reference raw image to dma by MI SP2. */
  647. /* physical address, alloacte by user */
  648. u64 pa;
  649. u32 size;
  650. struct isp_3dnr_compress_context compress;
  651. };
  652. struct isp_3dnr_update {
  653. u32 thr_edge_h_inv;
  654. u32 thr_edge_v_inv;
  655. u32 thr_motion_inv;
  656. u32 thr_range_s_inv;
  657. u32 range_t_h;
  658. u32 range_t_v;
  659. u32 range_d;
  660. u32 thr_range_t_inv;
  661. u32 thr_delta_h_inv;
  662. u32 thr_delta_v_inv;
  663. u32 thr_delta_t_inv;
  664. };
  665. #ifdef ISP_3DNR_V3
  666. #define DENOISE3D_GAMMA_BIN 33
  667. struct isp_tdnr_stats {
  668. u32 bg_sum;
  669. u32 motion_sum;
  670. u32 bg_pixel_cnt;
  671. u32 motion_pixel_cnt;
  672. u32 frame_avg;
  673. };
  674. struct isp_tdnr_curve {
  675. u16 preGamma_y[DENOISE3D_GAMMA_BIN];
  676. u16 invGamma_y[DENOISE3D_GAMMA_BIN];
  677. };
  678. struct isp_tdnr_buffer {
  679. /* write full denoise3d reference raw image to dma by MI SP2. */
  680. /* physical address, alloacte by user */
  681. u64 pa_refer;
  682. u32 size_refer;
  683. u64 pa_motion;
  684. u32 size_motion;
  685. };
  686. struct isp_tdnr_context {
  687. bool enable;
  688. bool enable_inv_gamma;
  689. bool enable_pre_gamma;
  690. bool enable_motion_erosion;
  691. bool enable_motion_converage;
  692. bool enable_motion_dilation;
  693. bool enable_tnr;
  694. bool enable_2dnr;
  695. u8 strength;
  696. u16 noise_level;
  697. u16 noise_mean;
  698. u16 noise_threshold;
  699. u16 motion_mean;
  700. u8 range_h;
  701. u8 range_v;
  702. u8 dilate_range_h;
  703. u8 dilate_range_v;
  704. u32 motion_inv_factor;
  705. u16 update_factor;
  706. u16 motion_update_factor;
  707. u16 pre_motion_weight;
  708. u16 motion_slope;
  709. u16 motion_converage_shift;
  710. u16 motion_converage_max;
  711. u16 tnr_val_shift_bit;
  712. u16 tnr_diff_shift_bit;
  713. u16 sad_weight;
  714. u16 luma_pixel_val_shift;
  715. u16 luma_pixel_slope;
  716. u16 luma_pixel_slope_shift;
  717. u16 luma_pixel_slope_min;
  718. u16 dmy_hblank;
  719. u32 fn;
  720. struct isp_tdnr_curve curve;
  721. struct isp_tdnr_buffer buf;
  722. u8 frames; //skip the first frame before clear reset.
  723. //keep the 3dnr enable in register to avoid scrolling screen when repeat enable
  724. };
  725. #endif
  726. struct isp_hdr_context {
  727. bool enable;
  728. /* hdr bls */
  729. u16 width;
  730. u16 height;
  731. u8 l_bit_dep, s_bit_dep, vs_bit_dep, ls_bit_dep;
  732. u8 weight0, weight1, weight2;
  733. u16 start_linear, norm_factor_mul_linear;
  734. u16 start_nonlinear, norm_factor_mul_nonlinear;
  735. u16 dummy_hblank, out_hblank;
  736. u16 out_vblank;
  737. u16 long_exp, short_exp, very_short_exp;
  738. u16 bls[4];
  739. u16 digal_gain[4];
  740. u32 reg;
  741. /* hdr awb */
  742. u32 r, gr, gb, b;
  743. /* hdr exp */
  744. u32 compress_lut[15];
  745. /* long short, very short */
  746. u32 ls0, ls1, vs0, vs1;
  747. u32 ext_bit;
  748. u32 valid_thresh;
  749. u32 offset_val;
  750. u32 sat_thresh;
  751. u32 combine_weight;
  752. };
  753. struct isp_simp_context {
  754. bool enable;
  755. u32 x, y;
  756. u32 r, g, b;
  757. u32 transparency_mode;
  758. u32 ref_image;
  759. };
  760. struct isp_compand_curve_context {
  761. bool enable;
  762. bool update_curve;
  763. uint8_t in_bit;
  764. uint8_t out_bit;
  765. uint32_t px[64];
  766. uint32_t x_data[63];
  767. uint32_t y_data[64];
  768. };
  769. struct isp_compand_bls_context_ry {
  770. uint8_t bit_width;
  771. bool enable;
  772. uint32_t a;
  773. uint32_t b;
  774. uint32_t c;
  775. uint32_t d;
  776. };
  777. /* COMPAND */
  778. struct isp_comp_context {
  779. bool enable;
  780. struct isp_compand_curve_context expand;
  781. struct isp_compand_bls_context_ry bls;
  782. struct isp_compand_curve_context compress;
  783. };
  784. struct isp_cproc_context {
  785. bool enable;
  786. bool changed;
  787. u32 contrast;
  788. u32 brightness;
  789. u32 saturation;
  790. u32 hue;
  791. bool y_out_full;
  792. bool c_out_full;
  793. bool y_in_full;
  794. };
  795. struct elawb_ellipse_info {
  796. u32 x, y; /* ellipse center */
  797. u32 a1, a2, a3, a4; /* ellipse axis */
  798. u32 r_max_sqr;
  799. };
  800. struct isp_elawb_context {
  801. bool enable;
  802. u32 id; /* ellipse id, 1-8, 0 means update all. */
  803. struct elawb_ellipse_info info[8];
  804. struct ic_window window;
  805. u32 r, gr, gb, b; /* gain */
  806. };
  807. struct isp_gcmono_data {
  808. u8 basePara[1024];
  809. u32 px[64];
  810. u32 dataX[63];
  811. u32 dataY[64];
  812. };
  813. struct isp_gcmono_context {
  814. u32 enable;
  815. u32 mode;
  816. };
  817. struct isp_rgbgamma_data {
  818. u32 rgbgc_r_px[64];
  819. u32 rgbgc_r_datax[63];
  820. u32 rgbgc_r_datay[64];
  821. u32 rgbgc_g_px[64];
  822. u32 rgbgc_g_datax[63];
  823. u32 rgbgc_g_datay[64];
  824. u32 rgbgc_b_px[64];
  825. u32 rgbgc_b_datax[63];
  826. u32 rgbgc_b_datay[64];
  827. };
  828. struct isp_rgbgamma_context {
  829. bool enable;
  830. struct isp_rgbgamma_data *data;
  831. bool data_changed;
  832. bool changed;
  833. };
  834. struct isp_irq_data {
  835. uint32_t addr;
  836. uint32_t val;
  837. uint32_t nop[14];
  838. };
  839. struct isp_rgbir_bls_context {
  840. u16 a;
  841. u16 b;
  842. u16 c;
  843. u16 d;
  844. };
  845. struct isp_rgbir_rgb_gain_context {
  846. u16 r;
  847. u16 g;
  848. u16 b;
  849. };
  850. struct isp_rgbir_dpcc_context {
  851. u16 median_thr[4];
  852. u16 avg_thr[4];
  853. };
  854. struct isp_rgbir_cc_context {
  855. u16 mtx[3][4];
  856. };
  857. struct isp_rgbir_des_context {
  858. u32 ir_px1, ir_py[16];
  859. u32 ir_pd[16], l_pd[16];
  860. u32 l_px1, l_py[16];
  861. };
  862. struct isp_rgbir_sharpen_context {
  863. u8 sharpen_lvl, middle;
  864. u16 thresh_bl0, thresh_bl1;
  865. u16 thresh_sh0, thresh_sh1;
  866. u8 lum_weight_min, lum_weight_kink, lum_weight_gain;
  867. };
  868. struct isp_rgbir_ir_dnr_context {
  869. u16 ir_sigmaS;
  870. u8 winweight[6];
  871. u16 width, height;
  872. };
  873. struct isp_rgbir_context{
  874. bool prefilt_enable, green_filt_mode, green_filt_enable;
  875. u8 rgbirPattern, out_rgb_pattern, green_filt_stage1_select;
  876. u8 demosaic_threshold;
  877. bool part1_enable, part2_enable;
  878. bool enable_ir_raw_out;
  879. struct isp_rgbir_bls_context bls;
  880. struct isp_rgbir_rgb_gain_context rgb_gain;
  881. struct isp_rgbir_dpcc_context dpcc;
  882. struct isp_rgbir_cc_context cc;
  883. struct isp_rgbir_des_context des;
  884. struct isp_rgbir_sharpen_context sharpen;
  885. struct isp_rgbir_ir_dnr_context ir_dnr;
  886. };
  887. struct isp_crop_context {
  888. bool enabled;
  889. struct ic_window window;
  890. };
  891. #if 1 // def ISP_MI_PP_READ_RY
  892. typedef struct pp_dma_line_entry_s {
  893. u32 width;
  894. u32 height;
  895. u32 stride;
  896. u32 buf_size;/**/
  897. u32 data_format;
  898. u16 entry_line_num;
  899. u32 buf_line_num;
  900. u64 buf_addr;
  901. } pp_dma_line_entry_t;
  902. #endif
  903. typedef struct pp_wr_line_entry_ry_s {
  904. u16 entry_line_num;
  905. u16 buf_line_num;
  906. u32 buf_addr;
  907. u32 buf_size;
  908. } pp_wr_line_entry_ry_t;
  909. struct isp_ic_dev {
  910. void __iomem *base;
  911. void __iomem *reset;
  912. int id;
  913. #ifdef ISP8000NANO_V1802
  914. struct regmap *mix_gpr;
  915. #endif
  916. #if defined(__KERNEL__) && defined(ENABLE_IRQ)
  917. struct vvbuf_ctx *bctx;
  918. struct vb2_dc_buf *mi_buf[MI_PATH_NUM];
  919. struct vb2_dc_buf *mi_buf_shd[MI_PATH_NUM];
  920. int (*alloc)(struct isp_ic_dev *dev, struct isp_buffer_context *buf);
  921. int (*free)(struct isp_ic_dev *dev, struct vb2_dc_buf *buf);
  922. int *state;
  923. #endif
  924. void (*post_event)(struct isp_ic_dev *dev, void *data, size_t size);
  925. struct isp_context ctx;
  926. struct isp_digital_gain_cxt dgain;
  927. struct isp_bls_context bls;
  928. struct isp_tpg_context tpg;
  929. struct isp_mcm_context mcm;
  930. struct isp_mux_context mux;
  931. struct isp_awb_context awb;
  932. struct isp_lsc_context lsc;
  933. struct isp_gamma_out_context gamma_out;
  934. struct isp_xtalk_context xtalk;
  935. struct isp_cc_context cc;
  936. struct isp_cnr_context cnr;
  937. struct isp_is_context is;
  938. struct isp_is_context rawis;
  939. struct isp_mi_context mi;
  940. struct isp_dpf_context dpf;
  941. struct isp_ee_context ee;
  942. struct isp_exp_context exp;
  943. struct isp_hist_context hist;
  944. #ifdef ISP_HIST64_RY
  945. struct isp_hist64_context hist64;
  946. #endif
  947. struct isp_dpcc_context dpcc;
  948. struct isp_flt_context flt;
  949. struct isp_cac_context cac;
  950. struct isp_deg_context deg;
  951. struct isp_ie_context ie;
  952. struct isp_vsm_context vsm;
  953. struct isp_afm_context afm;
  954. struct isp_wdr3_context wdr3;
  955. struct isp_exp2_context exp2;
  956. struct isp_hdr_context hdr;
  957. struct isp_exp_context hdrexp;
  958. struct isp_hist_context hdrhist;
  959. struct isp_2dnr_context dnr2;
  960. struct isp_3dnr_context dnr3;
  961. struct isp_comp_context comp;
  962. struct isp_simp_context simp;
  963. struct isp_cproc_context cproc;
  964. struct isp_elawb_context elawb;
  965. struct isp_gcmono_context gcmono;
  966. struct isp_rgbgamma_context rgbgamma;
  967. struct isp_dmsc_context demosaic;
  968. struct isp_ge_context ge;
  969. struct isp_ca_context ca;
  970. struct isp_dummy_hblank_cxt hblank;
  971. isp_wdr_context_t wdr;
  972. bool streaming;
  973. bool update_lsc_tbl;
  974. bool update_gamma_en;
  975. #ifdef ISP_WDR_V4
  976. struct isp_wdr4_context wdr4;
  977. #endif
  978. #ifdef ISP_3DNR_V3
  979. struct isp_tdnr_context tdnr;
  980. #endif
  981. struct isp_rgbir_context rgbir;
  982. u32 isp_mis;
  983. #ifdef ISP_MI_PP_READ_RY
  984. pp_dma_line_entry_t pp_dma_line_entry;
  985. #endif
  986. struct isp_crop_context crop[ISP_MI_PATH_SP2_BP + 1];
  987. pp_wr_line_entry_ry_t pp_write;
  988. isp_mis_list_t circle_list; //The irq circle list
  989. long long unsigned int ut_phy_addr; //for units test
  990. void *ut_addr;
  991. struct device *device;
  992. };
  993. struct isp_extmem_info {
  994. u64 addr;
  995. u64 size;
  996. };
  997. void isp_write_reg(struct isp_ic_dev *dev, u32 offset, u32 val);
  998. u32 isp_read_reg(struct isp_ic_dev *dev, u32 offset);
  999. #endif /* _ISP_DEV_H_ */