isp_ioctl.c 117 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707
  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. /* process public and sample isp command. for complex modules, need new files.*/
  54. #include "mrv_all_bits.h"
  55. #include "isp_ioctl.h"
  56. #include "isp_types.h"
  57. #include "isp_wdr.h"
  58. #include <linux/dma-mapping.h>
  59. #include <linux/dma-buf.h>
  60. #ifdef __KERNEL__
  61. #include <linux/regmap.h>
  62. #include <linux/of_reserved_mem.h>
  63. #endif
  64. #include "isp_ioctl.h"
  65. volatile MrvAllRegister_t *all_regs = NULL;
  66. #ifndef __KERNEL__
  67. #define ISP_REG_SIZE 0x10000
  68. static HalHandle_t hal_handle;
  69. void isp_ic_set_hal(HalHandle_t hal)
  70. {
  71. hal_handle = hal;
  72. }
  73. void isp_write_reg(struct isp_ic_dev *dev, u32 offset, u32 val)
  74. {
  75. //isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);
  76. if (offset >= ISP_REG_SIZE)
  77. return;
  78. HalWriteReg(hal_handle, offset, val);
  79. }
  80. u32 isp_read_reg(struct isp_ic_dev *dev, u32 offset)
  81. {
  82. if (offset >= ISP_REG_SIZE)
  83. return 0;
  84. return HalReadReg(hal_handle, offset);
  85. }
  86. long isp_copy_data(void *dst, void *src, int size)
  87. {
  88. if (dst != src)
  89. memcpy(dst, src, size);
  90. return 0;
  91. }
  92. #else
  93. void isp_write_reg(struct isp_ic_dev *dev, u32 offset, u32 val)
  94. {
  95. // isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);
  96. if (offset >= ISP_REG_SIZE)
  97. return;
  98. __raw_writel(val, dev->base + offset);
  99. /*isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);*/
  100. }
  101. u32 isp_read_reg(struct isp_ic_dev *dev, u32 offset)
  102. {
  103. u32 val = 0;
  104. if (offset >= ISP_REG_SIZE)
  105. return 0;
  106. val = __raw_readl(dev->base + offset);
  107. /*isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);*/
  108. return val;
  109. }
  110. #endif
  111. int isp_reset(struct isp_ic_dev *dev)
  112. {
  113. isp_info("enter %s\n", __func__);
  114. isp_write_reg(dev, REG_ADDR(vi_ircl), 0xFFFFFFBF);
  115. #ifdef __KERNEL__
  116. mdelay(2);
  117. #endif
  118. isp_write_reg(dev, REG_ADDR(vi_ircl), 0x0);
  119. /*clear mis array*/
  120. isp_write_reg(dev, REG_ADDR(isp_ctrl), 0x0); //clear isp_ctrl disable_isp_clk
  121. isp_info("exit %s\n", __func__);
  122. return 0;
  123. }
  124. int isp_enable_tpg(struct isp_ic_dev *dev)
  125. {
  126. u32 addr, isp_tpg_ctrl;
  127. isp_info("enter %s\n", __func__);
  128. addr = REG_ADDR(isp_tpg_ctrl);
  129. isp_tpg_ctrl = isp_read_reg(dev, addr);
  130. //REG_SET_SLICE(isp_tpg_ctrl, TPG_FRAME_NUM, 1);//set tpg frame num
  131. REG_SET_SLICE(isp_tpg_ctrl, TPG_ENABLE, 1);
  132. isp_write_reg(dev, addr, isp_tpg_ctrl);
  133. isp_info("exit %s\n", __func__);
  134. return 0;
  135. }
  136. int isp_disable_tpg(struct isp_ic_dev *dev)
  137. {
  138. u32 addr, isp_tpg_ctrl;
  139. isp_info("enter %s\n", __func__);
  140. addr = REG_ADDR(isp_tpg_ctrl);
  141. isp_tpg_ctrl = isp_read_reg(dev, addr);
  142. REG_SET_SLICE(isp_tpg_ctrl, TPG_ENABLE, 0);
  143. isp_write_reg(dev, addr, isp_tpg_ctrl);
  144. isp_info("exit %s\n", __func__);
  145. return 0;
  146. }
  147. int isp_enable_bls(struct isp_ic_dev *dev)
  148. {
  149. #ifndef ISP_BLS
  150. //isp_err("unsupported function %s", __func__);
  151. return -1;
  152. #else
  153. u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl));
  154. isp_info("enter %s\n", __func__);
  155. REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_ENABLE,
  156. MRV_BLS_BLS_ENABLE_PROCESS);
  157. isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl);
  158. isp_info("exit %s\n", __func__);
  159. return 0;
  160. #endif
  161. }
  162. int isp_disable_bls(struct isp_ic_dev *dev)
  163. {
  164. #ifndef ISP_BLS
  165. //isp_err("unsupported function %s", __func__);
  166. return -1;
  167. #else
  168. u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl));
  169. isp_info("enter %s\n", __func__);
  170. REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_ENABLE,
  171. MRV_BLS_BLS_ENABLE_BYPASS);
  172. isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl);
  173. isp_info("exit %s\n", __func__);
  174. return 0;
  175. #endif
  176. }
  177. int isp_enable(struct isp_ic_dev *dev)
  178. {
  179. u32 isp_ctrl, isp_imsc;
  180. isp_info("enter %s\n", __func__);
  181. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  182. isp_imsc |= (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK);
  183. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  184. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  185. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 1);
  186. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  187. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 1);
  188. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  189. /*Set lsc tbl after isp enable*/
  190. if (dev->update_lsc_tbl) {
  191. isp_s_lsc_tbl(dev);
  192. dev->update_lsc_tbl = false;
  193. }
  194. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1);
  195. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  196. isp_info("exit %s\n", __func__);
  197. return 0;
  198. }
  199. int isp_disable(struct isp_ic_dev *dev)
  200. {
  201. u32 isp_ctrl;
  202. /* #ifndef ENABLE_IRQ
  203. u32 isp_imsc;
  204. #endif*/
  205. isp_info("enter %s\n", __func__);
  206. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  207. /* #ifndef ENABLE_IRQ
  208. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  209. isp_imsc |= (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK);
  210. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  211. #endif*/
  212. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 0);
  213. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  214. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 0);
  215. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  216. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  217. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  218. isp_write_reg(dev, REG_ADDR(isp_isr), MRV_ISP_ISR_ISP_OFF_MASK);
  219. isp_info("exit %s\n", __func__);
  220. return 0;
  221. }
  222. bool is_isp_enable(struct isp_ic_dev *dev)
  223. {
  224. // isp_info("enter %s\n", __func__);
  225. return isp_read_reg(dev, REG_ADDR(isp_ctrl)) & 0x01;
  226. }
  227. int isp_enable_lsc(struct isp_ic_dev *dev)
  228. {
  229. u32 isp_lsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_lsc_ctrl));
  230. isp_info("enter %s\n", __func__);
  231. REG_SET_SLICE(isp_lsc_ctrl, MRV_LSC_LSC_EN, 1U);
  232. isp_write_reg(dev, REG_ADDR(isp_lsc_ctrl), isp_lsc_ctrl);
  233. {
  234. uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  235. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  236. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  237. }
  238. isp_info("exit %s\n", __func__);
  239. return 0;
  240. }
  241. int isp_disable_lsc(struct isp_ic_dev *dev)
  242. {
  243. u32 isp_lsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_lsc_ctrl));
  244. isp_info("enter %s\n", __func__);
  245. REG_SET_SLICE(isp_lsc_ctrl, MRV_LSC_LSC_EN, 0U);
  246. isp_write_reg(dev, REG_ADDR(isp_lsc_ctrl), isp_lsc_ctrl);
  247. {
  248. uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  249. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  250. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  251. }
  252. isp_info("exit %s\n", __func__);
  253. return 0;
  254. }
  255. #if defined(__KERNEL__) && defined(ISP8000NANO_V1802)
  256. static int isp_gpr_input_control(struct isp_ic_dev *dev)
  257. {
  258. struct isp_context isp_ctx = *(&dev->ctx);
  259. unsigned int fmt_offset = 3;
  260. unsigned int isp_dewarp_control_val;
  261. if (dev->mix_gpr == NULL)
  262. return -ENOMEM;
  263. if (dev->id == 0)
  264. fmt_offset = 3;
  265. else
  266. fmt_offset = 13;
  267. regmap_read(dev->mix_gpr, 0x138, &isp_dewarp_control_val);
  268. if (isp_dewarp_control_val == 0)
  269. isp_dewarp_control_val = 0x8d8360;
  270. switch (isp_ctx.input_selection) {
  271. case MRV_ISP_INPUT_SELECTION_12EXT:
  272. isp_dewarp_control_val &= ~(0x3f << fmt_offset);
  273. isp_dewarp_control_val |= (0x2c << fmt_offset);
  274. break;
  275. case MRV_ISP_INPUT_SELECTION_10ZERO:
  276. case MRV_ISP_INPUT_SELECTION_10MSB:
  277. isp_dewarp_control_val &= ~(0x3f << fmt_offset);
  278. isp_dewarp_control_val |= (0x2b << fmt_offset);
  279. break;
  280. case MRV_ISP_INPUT_SELECTION_8ZERO:
  281. case MRV_ISP_INPUT_SELECTION_8MSB:
  282. isp_dewarp_control_val &= ~(0x3f << fmt_offset);
  283. isp_dewarp_control_val |= (0x2a << fmt_offset);
  284. break;
  285. default:
  286. return 0;
  287. }
  288. regmap_write(dev->mix_gpr, 0x138, isp_dewarp_control_val);
  289. return 0;
  290. }
  291. #endif
  292. int isp_s_input(struct isp_ic_dev *dev)
  293. {
  294. struct isp_context isp_ctx = *(&dev->ctx);
  295. u32 isp_ctrl, isp_acq_prop, isp_demosaic;
  296. #ifdef ISP_HDR_STITCH
  297. u32 isp_stitching_ctrl;
  298. #endif //ISP_HDR_STITCH
  299. isp_info("enter %s\n", __func__);
  300. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  301. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_MODE, isp_ctx.mode);
  302. isp_acq_prop = isp_read_reg(dev, REG_ADDR(isp_acq_prop));
  303. REG_SET_SLICE(isp_acq_prop, MRV_ISP_SAMPLE_EDGE, isp_ctx.sample_edge);
  304. REG_SET_SLICE(isp_acq_prop, MRV_ISP_HSYNC_POL,
  305. isp_ctx.hSyncLowPolarity);
  306. REG_SET_SLICE(isp_acq_prop, MRV_ISP_VSYNC_POL,
  307. isp_ctx.vSyncLowPolarity);
  308. REG_SET_SLICE(isp_acq_prop, MRV_ISP_BAYER_PAT, isp_ctx.bayer_pattern);
  309. REG_SET_SLICE(isp_acq_prop, MRV_ISP_CONV_422, isp_ctx.sub_sampling);
  310. REG_SET_SLICE(isp_acq_prop, MRV_ISP_CCIR_SEQ, isp_ctx.seq_ccir);
  311. REG_SET_SLICE(isp_acq_prop, MRV_ISP_FIELD_SELECTION,
  312. isp_ctx.field_selection);
  313. REG_SET_SLICE(isp_acq_prop, MRV_ISP_INPUT_SELECTION,
  314. isp_ctx.input_selection);
  315. REG_SET_SLICE(isp_acq_prop, MRV_ISP_LATENCY_FIFO_SELECTION,
  316. isp_ctx.latency_fifo);
  317. isp_write_reg(dev, REG_ADDR(isp_acq_prop), isp_acq_prop);
  318. isp_write_reg(dev, REG_ADDR(isp_acq_h_offs), isp_ctx.acqWindow.x);
  319. isp_write_reg(dev, REG_ADDR(isp_acq_v_offs), isp_ctx.acqWindow.y);
  320. isp_write_reg(dev, REG_ADDR(isp_acq_h_size), isp_ctx.acqWindow.width);
  321. isp_write_reg(dev, REG_ADDR(isp_acq_v_size), isp_ctx.acqWindow.height);
  322. #ifdef ISP_MI_HDR
  323. isp_write_reg(dev, REG_ADDR(isp_hdr_interval), 0x113);
  324. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_h_blank), 0x200);
  325. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_v_blank), 0x30);
  326. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_h_size), isp_ctx.acqWindow.width);
  327. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_v_size), isp_ctx.acqWindow.height);
  328. #endif
  329. isp_write_reg(dev, REG_ADDR(isp_out_h_offs),
  330. (isp_ctx.ofWindow.x & MRV_ISP_ISP_OUT_H_OFFS_MASK));
  331. isp_write_reg(dev, REG_ADDR(isp_out_v_offs),
  332. (isp_ctx.ofWindow.y & MRV_ISP_ISP_OUT_V_OFFS_MASK));
  333. isp_write_reg(dev, REG_ADDR(isp_out_h_size),
  334. (isp_ctx.ofWindow.width & MRV_ISP_ISP_OUT_H_SIZE_MASK));
  335. isp_write_reg(dev, REG_ADDR(isp_out_v_size),
  336. (isp_ctx.ofWindow.height & MRV_ISP_ISP_OUT_V_SIZE_MASK));
  337. isp_write_reg(dev, REG_ADDR(isp_is_h_offs),
  338. (isp_ctx.isWindow.x & MRV_IS_IS_H_OFFS_MASK));
  339. isp_write_reg(dev, REG_ADDR(isp_is_v_offs),
  340. (isp_ctx.isWindow.y & MRV_IS_IS_V_OFFS_MASK));
  341. isp_write_reg(dev, REG_ADDR(isp_is_h_size),
  342. (isp_ctx.isWindow.width & MRV_IS_IS_H_SIZE_MASK));
  343. isp_write_reg(dev, REG_ADDR(isp_is_v_size),
  344. (isp_ctx.isWindow.height & MRV_IS_IS_V_SIZE_MASK));
  345. isp_demosaic = isp_read_reg(dev, REG_ADDR(isp_demosaic));
  346. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_BYPASS,
  347. isp_ctx.bypass_mode);
  348. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_TH,
  349. isp_ctx.demosaic_threshold);
  350. isp_write_reg(dev, REG_ADDR(isp_demosaic), isp_demosaic);
  351. #ifdef ISP_HDR_STITCH
  352. isp_write_reg(dev, REG_ADDR(isp_stitching_frame_width), isp_ctx.acqWindow.width);
  353. isp_write_reg(dev, REG_ADDR(isp_stitching_frame_height), isp_ctx.acqWindow.height);
  354. isp_write_reg(dev, REG_ADDR(isp_stitching_hdr_mode), isp_ctx.stitching_mode);
  355. isp_stitching_ctrl = isp_read_reg(dev, REG_ADDR(isp_stitching_ctrl));
  356. REG_SET_SLICE(isp_stitching_ctrl, STITCHING_BAYER_PATTERN, isp_ctx.bayer_pattern);
  357. isp_write_reg(dev, REG_ADDR(isp_stitching_ctrl), isp_stitching_ctrl);
  358. #endif
  359. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  360. #if defined(__KERNEL__) && defined(ISP8000NANO_V1802)
  361. isp_gpr_input_control(dev);
  362. #endif
  363. return 0;
  364. }
  365. int isp_s_digital_gain(struct isp_ic_dev *dev)
  366. {
  367. if (dev->dgain.changed) {
  368. u32 isp_dgain_rb = isp_read_reg(dev, REG_ADDR(isp_dgain_rb));
  369. u32 isp_dgain_g = isp_read_reg(dev, REG_ADDR(isp_dgain_g));
  370. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  371. if (!dev->dgain.enable) {
  372. isp_err("%s, Disable isp digital gain", __func__);
  373. REG_SET_SLICE(isp_ctrl, MRV_ISP_DIGITAL_GAIN_EN, 0U);
  374. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  375. return 0;
  376. }
  377. //isp_info("enter %s\n", __func__);
  378. REG_SET_SLICE(isp_dgain_rb, ISP_DIGITAL_GAIN_R, dev->dgain.gain_r);
  379. REG_SET_SLICE(isp_dgain_rb, ISP_DIGITAL_GAIN_B, dev->dgain.gain_b);
  380. REG_SET_SLICE(isp_dgain_g, ISP_DIGITAL_GAIN_GR, dev->dgain.gain_gr);
  381. REG_SET_SLICE(isp_dgain_g, ISP_DIGITAL_GAIN_GB, dev->dgain.gain_gb);
  382. REG_SET_SLICE(isp_ctrl, MRV_ISP_DIGITAL_GAIN_EN, 1U);
  383. isp_write_reg(dev, REG_ADDR(isp_dgain_rb), isp_dgain_rb);
  384. isp_write_reg(dev, REG_ADDR(isp_dgain_g), isp_dgain_g);
  385. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  386. //isp_info("exit %s\n", __func__);
  387. dev->dgain.changed = false;
  388. } else {
  389. dev->dgain.changed = true;
  390. }
  391. return 0;
  392. }
  393. int isp_s_demosaic(struct isp_ic_dev *dev)
  394. {
  395. struct isp_context isp_ctx = *(&dev->ctx);
  396. u32 isp_demosaic;
  397. isp_info("enter %s\n", __func__);
  398. isp_demosaic = isp_read_reg(dev, REG_ADDR(isp_demosaic));
  399. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_BYPASS,
  400. isp_ctx.bypass_mode);
  401. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_TH,
  402. isp_ctx.demosaic_threshold);
  403. isp_write_reg(dev, REG_ADDR(isp_demosaic), isp_demosaic);
  404. isp_info("exit %s\n", __func__);
  405. return 0;;
  406. }
  407. int isp_s_tpg(struct isp_ic_dev *dev)
  408. {
  409. struct isp_tpg_context tpg = *(&dev->tpg);
  410. u32 addr, regVal;
  411. isp_info("enter %s\n", __func__);
  412. addr = REG_ADDR(isp_tpg_ctrl);
  413. regVal = isp_read_reg(dev, addr);
  414. REG_SET_SLICE(regVal, TPG_IMG_NUM, tpg.image_type);
  415. REG_SET_SLICE(regVal, TPG_CFA_PAT, tpg.bayer_pattern);
  416. REG_SET_SLICE(regVal, TPG_COLOR_DEPTH, tpg.color_depth);
  417. REG_SET_SLICE(regVal, TPG_RESOLUTION, tpg.resolution);
  418. REG_SET_SLICE(regVal, TPG_FRAME_NUM, tpg.frame_num);
  419. isp_write_reg(dev, addr, regVal);
  420. regVal = 0;
  421. REG_SET_SLICE(regVal, TPG_PIX_GAP_IN, tpg.pixleGap);
  422. REG_SET_SLICE(regVal, TPG_LINE_GAP_IN, tpg.lineGap);
  423. isp_write_reg(dev, REG_ADDR(isp_tpg_gap_in), regVal);
  424. regVal = 0;
  425. REG_SET_SLICE(regVal, TPG_PIX_GAP_STD_IN, tpg.gapStandard);
  426. isp_write_reg(dev, REG_ADDR(isp_tpg_gap_std_in), regVal);
  427. regVal = 0;
  428. REG_SET_SLICE(regVal, TPG_RANDOM_SEED, tpg.randomSeed);
  429. isp_write_reg(dev, REG_ADDR(isp_tpg_random_seed), regVal);
  430. REG_SET_SLICE(regVal, TPG_HTOTAL_IN, tpg.user_mode_h.total);
  431. REG_SET_SLICE(regVal, TPG_VTOTAL_IN, tpg.user_mode_v.total);
  432. isp_write_reg(dev, REG_ADDR(isp_tpg_total_in), regVal);
  433. regVal = 0;
  434. REG_SET_SLICE(regVal, TPG_HACT_IN, tpg.user_mode_h.act);
  435. REG_SET_SLICE(regVal, TPG_VACT_IN, tpg.user_mode_v.act);
  436. isp_write_reg(dev, REG_ADDR(isp_tpg_act_in), regVal);
  437. regVal = 0;
  438. REG_SET_SLICE(regVal, TPG_FP_H_IN, tpg.user_mode_h.fp);
  439. REG_SET_SLICE(regVal, TPG_FP_V_IN, tpg.user_mode_v.fp);
  440. isp_write_reg(dev, REG_ADDR(isp_tpg_fp_in), regVal);
  441. regVal = 0;
  442. REG_SET_SLICE(regVal, TPG_BP_H_IN, tpg.user_mode_h.bp);
  443. REG_SET_SLICE(regVal, TPG_BP_V_IN, tpg.user_mode_v.bp);
  444. isp_write_reg(dev, REG_ADDR(isp_tpg_bp_in), regVal);
  445. regVal = 0;
  446. REG_SET_SLICE(regVal, TPG_HS_W_IN, tpg.user_mode_h.sync);
  447. REG_SET_SLICE(regVal, TPG_VS_W_IN, tpg.user_mode_v.sync);
  448. isp_write_reg(dev, REG_ADDR(isp_tpg_w_in), regVal);
  449. isp_info("exit %s\n", __func__);
  450. return 0;
  451. }
  452. int isp_s_mcm_wr(struct isp_ic_dev *dev)
  453. {
  454. struct isp_mcm_context *mcm = &dev->mcm;
  455. u32 mcm_ctrl;
  456. u32 mcm_hsync_preample_ext;
  457. u32 mcm_size, mcm_rd_fmt;
  458. int i;
  459. isp_info("enter %s\n", __func__);
  460. mcm_ctrl = isp_read_reg(dev, REG_ADDR(mcm_ctrl));
  461. mcm_rd_fmt = isp_read_reg(dev, REG_ADDR(mcm_rd_cfg));
  462. mcm_hsync_preample_ext = isp_read_reg(dev, REG_ADDR(mcm_hsync_preample_ext));
  463. REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_SWITCH, mcm->bypass_switch);
  464. REG_SET_SLICE(mcm_ctrl, MCM_WR0_FMT, mcm->wr_fmt[MCM_INDEX_WR0]);
  465. REG_SET_SLICE(mcm_ctrl, MCM_WR1_FMT, mcm->wr_fmt[MCM_INDEX_WR1]);
  466. REG_SET_SLICE(mcm_ctrl, MCM_G2_WR0_FMT, mcm->wr_fmt[MCM_INDEX_G2_WR0]);
  467. REG_SET_SLICE(mcm_ctrl, MCM_G2_WR1_FMT, mcm->wr_fmt[MCM_INDEX_G2_WR1]);
  468. REG_SET_SLICE(mcm_ctrl, MCM_SENSOR_MEM_BYPASS, mcm->sensor_mem_bypass);
  469. REG_SET_SLICE(mcm_rd_fmt, MCM_RD_FMT, mcm->rd_fmt);
  470. REG_SET_SLICE(mcm_hsync_preample_ext, MCM_HSYNC_PREAMPLE_EXT, mcm->hsync_rpeample_ext);
  471. for (i = MCM_INDEX_WR0 ; i < MCM_INDEX_WR_MAX; i++){
  472. REG_SET_SLICE(mcm_size, MCM_HEIGHT0, mcm->height[i]);
  473. REG_SET_SLICE(mcm_size, MCM_WIDTH0, mcm->width[i]);
  474. isp_write_reg(dev, REG_ADDR(mcm_size0) + i *4, mcm_size);
  475. }
  476. isp_write_reg(dev, REG_ADDR(mcm_hsync_preample_ext), mcm_hsync_preample_ext);
  477. isp_write_reg(dev, REG_ADDR(mcm_rd_cfg), mcm_rd_fmt);
  478. isp_write_reg(dev, REG_ADDR(mcm_ctrl), mcm_ctrl);
  479. isp_info("exit %s\n", __func__);
  480. return 0;
  481. }
  482. int isp_bypass_mcm(struct isp_ic_dev *dev)
  483. {
  484. struct isp_mcm_context *mcm = &dev->mcm;
  485. u32 mcm_ctrl;
  486. u32 mcm_retiming0;
  487. u32 mcm_retiming1;
  488. u32 mcm_wr_retiming0;
  489. u32 mcm_wr_retiming1;
  490. isp_info("enter %s\n", __func__);
  491. mcm_ctrl = isp_read_reg(dev, REG_ADDR(mcm_ctrl));
  492. mcm_retiming0 = isp_read_reg(dev, REG_ADDR(mcm_retiming0));
  493. mcm_retiming1 = isp_read_reg(dev, REG_ADDR(mcm_retiming1));
  494. mcm_wr_retiming0 = isp_read_reg(dev, REG_ADDR(mcm_wr_retiming0));
  495. mcm_wr_retiming1 = isp_read_reg(dev, REG_ADDR(mcm_wr_retiming1));
  496. if (mcm->bypass_enable) {
  497. REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_EN, 1);
  498. } else {
  499. REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_EN, 0);
  500. }
  501. REG_SET_SLICE(mcm_retiming0, MCM_VSYNC_DURATION, mcm->vsync_duration);
  502. REG_SET_SLICE(mcm_retiming0, MCM_VSYNC_BLANK, mcm->vsync_blank);
  503. REG_SET_SLICE(mcm_retiming1, MCM_HSYNC_PREAMPLE, mcm->hsync_preample);
  504. REG_SET_SLICE(mcm_retiming1, MCM_HSYNC_BLANK, mcm->hsync_blank);
  505. REG_SET_SLICE(mcm_wr_retiming0, MCM_VSYNC_DURATION, mcm->vsync_duration);
  506. REG_SET_SLICE(mcm_wr_retiming0, MCM_VSYNC_BLANK, mcm->vsync_blank);
  507. REG_SET_SLICE(mcm_wr_retiming1, MCM_HSYNC_PREAMPLE, mcm->hsync_preample);
  508. REG_SET_SLICE(mcm_wr_retiming1, MCM_HSYNC_BLANK, mcm->hsync_blank);
  509. isp_write_reg(dev, REG_ADDR(mcm_ctrl), mcm_ctrl);
  510. isp_write_reg(dev, REG_ADDR(mcm_retiming0), mcm_retiming0); // 0x01042801);//
  511. isp_write_reg(dev, REG_ADDR(mcm_retiming1), mcm_retiming1); //0x00008478); //
  512. isp_write_reg(dev, REG_ADDR(mcm_wr_retiming0), mcm_wr_retiming0); //0x01042801); //
  513. isp_write_reg(dev, REG_ADDR(mcm_wr_retiming1), mcm_wr_retiming1); //0x000084ec);//
  514. isp_info("exit %s\n", __func__);
  515. return 0;
  516. }
  517. int isp_s_mux(struct isp_ic_dev *dev)
  518. {
  519. struct isp_mux_context mux = *(&dev->mux);
  520. u32 vi_dpcl;
  521. isp_info("enter %s\n", __func__);
  522. vi_dpcl = isp_read_reg(dev, REG_ADDR(vi_dpcl));
  523. REG_SET_SLICE(vi_dpcl, MRV_VI_MP_MUX, mux.mp_mux);
  524. REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_SPMUX, mux.sp_mux);
  525. REG_SET_SLICE(vi_dpcl, MRV_VI_CHAN_MODE, mux.chan_mode);
  526. REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_IEMUX, mux.ie_mux);
  527. REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_SWITCH, mux.dma_read_switch);
  528. REG_SET_SLICE(vi_dpcl, MRV_IF_SELECT, mux.if_select);
  529. isp_write_reg(dev, REG_ADDR(vi_dpcl), vi_dpcl);
  530. isp_info("exit %s\n", __func__);
  531. return 0;
  532. }
  533. int isp_s_bls(struct isp_ic_dev *dev)
  534. {
  535. #ifndef ISP_BLS
  536. //isp_err("unsupported function %s", __func__);
  537. return -1;
  538. #else
  539. struct isp_bls_context bls = *(&dev->bls);
  540. u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl));
  541. isp_info("enter %s\n", __func__);
  542. REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_MODE, bls.mode);
  543. isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl);
  544. isp_write_reg(dev, REG_ADDR(isp_bls_a_fixed), bls.a);
  545. isp_write_reg(dev, REG_ADDR(isp_bls_b_fixed), bls.b);
  546. isp_write_reg(dev, REG_ADDR(isp_bls_c_fixed), bls.c);
  547. isp_write_reg(dev, REG_ADDR(isp_bls_d_fixed), bls.d);
  548. return 0;
  549. #endif
  550. }
  551. int isp_enable_awb(struct isp_ic_dev *dev)
  552. {
  553. u32 isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop));
  554. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  555. isp_info("enter %s\n", __func__);
  556. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MODE, MRV_ISP_AWB_MODE_MEAS);
  557. isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop);
  558. isp_write_reg(dev, REG_ADDR(isp_imsc),
  559. isp_imsc | MRV_ISP_IMSC_AWB_DONE_MASK);
  560. isp_info("exit %s\n", __func__);
  561. return 0;
  562. }
  563. int isp_disable_awb(struct isp_ic_dev *dev)
  564. {
  565. u32 isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop));
  566. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  567. isp_info("enter %s\n", __func__);
  568. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MODE, MRV_ISP_AWB_MODE_NOMEAS);
  569. isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop);
  570. isp_write_reg(dev, REG_ADDR(isp_imsc),
  571. isp_imsc & ~MRV_ISP_IMSC_AWB_DONE_MASK);
  572. isp_info("exit %s\n", __func__);
  573. return 0;
  574. }
  575. int isp_s_awb(struct isp_ic_dev *dev)
  576. {
  577. struct isp_awb_context awb = *(&dev->awb);
  578. u32 gain_data = 0;
  579. u32 isp_awb_thresh = 0;
  580. u32 isp_awb_ref = 0;
  581. u32 isp_awb_prop = 0;
  582. /* isp_info("enter %s\n", __func__); */
  583. isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop));
  584. if (awb.mode == MRV_ISP_AWB_MEAS_MODE_YCBCR) {
  585. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MEAS_MODE,
  586. MRV_ISP_AWB_MEAS_MODE_YCBCR);
  587. if (awb.max_y == 0) {
  588. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN,
  589. MRV_ISP_AWB_MAX_EN_DISABLE);
  590. } else {
  591. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN,
  592. MRV_ISP_AWB_MAX_EN_ENABLE);
  593. }
  594. } else if (awb.mode == MRV_ISP_AWB_MEAS_MODE_RGB) {
  595. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN,
  596. MRV_ISP_AWB_MAX_EN_DISABLE);
  597. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MEAS_MODE,
  598. MRV_ISP_AWB_MEAS_MODE_RGB);
  599. }
  600. isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop);
  601. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MAX_Y, awb.max_y);
  602. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MIN_Y__MAX_G,
  603. awb.min_y_max_g);
  604. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MAX_CSUM, awb.max_c_sum);
  605. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MIN_C, awb.min_c);
  606. isp_write_reg(dev, REG_ADDR(isp_awb_thresh), isp_awb_thresh);
  607. REG_SET_SLICE(isp_awb_ref, MRV_ISP_AWB_REF_CR__MAX_R, awb.refcr_max_r);
  608. REG_SET_SLICE(isp_awb_ref, MRV_ISP_AWB_REF_CB__MAX_B, awb.refcb_max_b);
  609. isp_write_reg(dev, REG_ADDR(isp_awb_ref), isp_awb_ref);
  610. isp_write_reg(dev, REG_ADDR(isp_awb_frames), 0);
  611. isp_write_reg(dev, REG_ADDR(isp_awb_h_offs),
  612. (MRV_ISP_AWB_H_OFFS_MASK & awb.window.x));
  613. isp_write_reg(dev, REG_ADDR(isp_awb_v_offs),
  614. (MRV_ISP_AWB_V_OFFS_MASK & awb.window.y));
  615. isp_write_reg(dev, REG_ADDR(isp_awb_h_size),
  616. (MRV_ISP_AWB_H_SIZE_MASK & awb.window.width));
  617. isp_write_reg(dev, REG_ADDR(isp_awb_v_size),
  618. (MRV_ISP_AWB_V_SIZE_MASK & awb.window.height));
  619. gain_data = 0UL;
  620. #ifdef ISP_AWB_0410 //This is Gain value component 4 bit int part and 10 bit fractional part
  621. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_R, awb.gain_r << 2);
  622. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_B, awb.gain_b << 2) ;
  623. #else //This is Gain value component 2 bit int part and 8 bit fractional part
  624. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_R, awb.gain_r);
  625. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_B, awb.gain_b);
  626. #endif
  627. isp_write_reg(dev, REG_ADDR(isp_awb_gain_rb), gain_data);
  628. gain_data = 0UL;
  629. #ifdef ISP_AWB_0410 //This is Gain value component 4 bit int part and 10 bit fractional part
  630. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GR, awb.gain_gr << 2);
  631. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GB, awb.gain_gb << 2);
  632. #else //This is Gain value component 2 bit int part and 8 bit fractional part
  633. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GR, awb.gain_gr);
  634. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GB, awb.gain_gb);
  635. #endif
  636. isp_write_reg(dev, REG_ADDR(isp_awb_gain_g), gain_data);
  637. return 0;
  638. }
  639. int isp_s_is(struct isp_ic_dev *dev)
  640. {
  641. struct isp_is_context is = *(&dev->is);
  642. u32 isp_is_ctrl;
  643. u32 isp_is_displace;
  644. u32 isp_ctrl;
  645. isp_info("enter %s\n", __func__);
  646. isp_is_ctrl = isp_read_reg(dev, REG_ADDR(isp_is_ctrl));
  647. if (!is.enable) {
  648. REG_SET_SLICE(isp_is_ctrl, MRV_IS_IS_EN, 0);
  649. isp_write_reg(dev, REG_ADDR(isp_is_ctrl), isp_is_ctrl);
  650. return 0;
  651. }
  652. REG_SET_SLICE(isp_is_ctrl, MRV_IS_IS_EN, 1);
  653. isp_write_reg(dev, REG_ADDR(isp_is_h_offs), is.window.x);
  654. isp_write_reg(dev, REG_ADDR(isp_is_v_offs), is.window.y);
  655. isp_write_reg(dev, REG_ADDR(isp_is_h_size), is.window.width);
  656. isp_write_reg(dev, REG_ADDR(isp_is_v_size), is.window.height);
  657. isp_write_reg(dev, REG_ADDR(isp_is_recenter),
  658. is.recenter & MRV_IS_IS_RECENTER_MASK);
  659. isp_write_reg(dev, REG_ADDR(isp_is_max_dx), is.max_dx);
  660. isp_write_reg(dev, REG_ADDR(isp_is_max_dy), is.max_dy);
  661. isp_is_displace = isp_read_reg(dev, REG_ADDR(isp_is_displace));
  662. REG_SET_SLICE(isp_is_displace, MRV_IS_DX, is.displace_x);
  663. REG_SET_SLICE(isp_is_displace, MRV_IS_DY, is.displace_y);
  664. isp_write_reg(dev, REG_ADDR(isp_is_displace), isp_is_displace);
  665. isp_write_reg(dev, REG_ADDR(isp_is_ctrl), isp_is_ctrl);
  666. if (is.update) {
  667. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  668. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  669. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  670. is.update = false;
  671. }
  672. isp_info("exit %s\n", __func__);
  673. return 0;
  674. }
  675. int isp_s_raw_is(struct isp_ic_dev *dev)
  676. {
  677. #ifndef ISP_RAWIS
  678. //isp_err("unsupported funciton: %s\n", __func__);
  679. return -EINVAL;
  680. #else
  681. struct isp_is_context rawis = *(&dev->rawis);
  682. u32 isp_raw_is_ctrl;
  683. u32 isp_raw_is_displace;
  684. // u32 isp_ctrl;
  685. isp_info("enter %s\n", __func__);
  686. isp_raw_is_ctrl = isp_read_reg(dev, REG_ADDR(isp_raw_is_ctrl));
  687. if (!rawis.enable) {
  688. isp_write_reg(dev, REG_ADDR(isp_raw_is_h_size),
  689. rawis.window.width);
  690. isp_write_reg(dev, REG_ADDR(isp_raw_is_v_size),
  691. rawis.window.height);
  692. REG_SET_SLICE(isp_raw_is_ctrl, MRV_ISP_RAW_IS_EN, 0);
  693. isp_write_reg(dev, REG_ADDR(isp_raw_is_ctrl), isp_raw_is_ctrl);
  694. return 0;
  695. }
  696. REG_SET_SLICE(isp_raw_is_ctrl, MRV_ISP_RAW_IS_EN, 1);
  697. isp_write_reg(dev, REG_ADDR(isp_raw_is_h_offs), rawis.window.x);
  698. isp_write_reg(dev, REG_ADDR(isp_raw_is_v_offs), rawis.window.y);
  699. isp_write_reg(dev, REG_ADDR(isp_raw_is_h_size), rawis.window.width);
  700. isp_write_reg(dev, REG_ADDR(isp_raw_is_v_size), rawis.window.height);
  701. isp_write_reg(dev, REG_ADDR(isp_raw_is_recenter),
  702. rawis.recenter & MRV_IS_IS_RECENTER_MASK);
  703. isp_write_reg(dev, REG_ADDR(isp_raw_is_max_dx), rawis.max_dx);
  704. isp_write_reg(dev, REG_ADDR(isp_raw_is_max_dy), rawis.max_dy);
  705. isp_raw_is_displace = isp_read_reg(dev, REG_ADDR(isp_raw_is_displace));
  706. REG_SET_SLICE(isp_raw_is_displace, MRV_ISP_RAW_IS_DX, rawis.displace_x);
  707. REG_SET_SLICE(isp_raw_is_displace, MRV_ISP_RAW_IS_DY, rawis.displace_y);
  708. isp_write_reg(dev, REG_ADDR(isp_raw_is_displace), isp_raw_is_displace);
  709. isp_write_reg(dev, REG_ADDR(isp_raw_is_ctrl), isp_raw_is_ctrl);
  710. /*dont update the configuration at the sub module function*/
  711. #if 0
  712. if (rawis.update) {
  713. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  714. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1);
  715. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  716. rawis.update = false;
  717. }
  718. #endif
  719. return 0;
  720. #endif
  721. }
  722. int isp_s_cnr(struct isp_ic_dev *dev)
  723. {
  724. struct isp_cnr_context *cnr = &dev->cnr;
  725. u32 isp_ctrl;
  726. isp_info("enter %s\n", __func__);
  727. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  728. if (!cnr->enable) {
  729. REG_SET_SLICE(isp_ctrl, MRV_ISP_CNR_EN, 0);
  730. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  731. return 0;
  732. }
  733. REG_SET_SLICE(isp_ctrl, MRV_ISP_CNR_EN, 1);
  734. isp_write_reg(dev, REG_ADDR(isp_cnr_linesize), cnr->line_width);
  735. isp_write_reg(dev, REG_ADDR(isp_cnr_threshold_c1), cnr->threshold_1);
  736. isp_write_reg(dev, REG_ADDR(isp_cnr_threshold_c2), cnr->threshold_2);
  737. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  738. isp_info("exit %s\n", __func__);
  739. return 0;
  740. }
  741. void isp_test_bt(struct isp_ic_dev *dev)
  742. {
  743. isp_write_reg(dev, 0x00000010, 0x00019f7b);
  744. isp_write_reg(dev, 0x00000014, 0x00020000);
  745. isp_write_reg(dev, 0x00001200, 0x00000000);
  746. isp_write_reg(dev, 0x00001204, 0x01e00280);
  747. isp_write_reg(dev, 0x00001208, 0x01e00280);
  748. isp_write_reg(dev, 0x00001308, 0x6ce60608);
  749. isp_write_reg(dev, 0x00001314, 0x000008c4);
  750. isp_write_reg(dev, 0x00001318, 0x00000001);
  751. isp_write_reg(dev, 0x0000131c, 0x03a2013b);
  752. isp_write_reg(dev, 0x00001320, 0x00000000);
  753. isp_write_reg(dev, 0x00001324, 0xc0000000);
  754. isp_write_reg(dev, 0x00001328, 0x0004B000);
  755. isp_write_reg(dev, 0x0000132c, 0x00000000);
  756. isp_write_reg(dev, 0x00001330, 0x00000280);
  757. isp_write_reg(dev, 0x00001334, 0x00000280);
  758. isp_write_reg(dev, 0x00001338, 0x000001e0);
  759. isp_write_reg(dev, 0x0000133c, 0x0004B000);
  760. isp_write_reg(dev, 0x00001340, 0xc0040000);
  761. isp_write_reg(dev, 0x00001344, 0x0004B000);
  762. isp_write_reg(dev, 0x000016c0, 0x07ffffff);
  763. isp_write_reg(dev, 0x000005bc, 0x00000003);
  764. isp_write_reg(dev, 0x000016c4, 0x052c4e39);
  765. isp_write_reg(dev, 0x00000404, 0x00d00018);
  766. isp_write_reg(dev, 0x00000410, 0x00000280);
  767. isp_write_reg(dev, 0x00000414, 0x000001e0);
  768. isp_write_reg(dev, 0x00000538, 0x01000100);
  769. isp_write_reg(dev, 0x0000053c, 0x02270220);
  770. isp_write_reg(dev, 0x0000059c, 0x00000280);
  771. isp_write_reg(dev, 0x000005a0, 0x000001e0);
  772. isp_write_reg(dev, 0x00002310, 0x00000280);
  773. isp_write_reg(dev, 0x00002314, 0x000001e0);
  774. isp_write_reg(dev, 0x0000295c, 0x00000070);
  775. isp_write_reg(dev, 0x00003e00, 0x040128be);
  776. isp_write_reg(dev, 0x00003e04, 0x00000000);
  777. isp_write_reg(dev, 0x00003e08, 0x00001f08);
  778. isp_write_reg(dev, 0x00003e0c, 0x200003ff);
  779. isp_write_reg(dev, 0x00003e10, 0x0c968628);
  780. isp_write_reg(dev, 0x00003e14, 0x00008008);
  781. isp_write_reg(dev, 0x00003e18, 0x007d07d0);
  782. isp_write_reg(dev, 0x00003e1c, 0x301a3012);
  783. isp_write_reg(dev, 0x00003e20, 0x04010000);
  784. isp_write_reg(dev, 0x00003e24, 0x22018000);
  785. isp_write_reg(dev, 0x00003e28, 0x00020000);
  786. isp_write_reg(dev, 0x00003e2c, 0x0210210a);
  787. isp_write_reg(dev, 0x00003e30, 0x00102102);
  788. isp_write_reg(dev, 0x00003e34, 0x0000388c);
  789. isp_write_reg(dev, 0x00003e38, 0x00000000);
  790. isp_write_reg(dev, 0x00003e3c, 0x00000000);
  791. isp_write_reg(dev, 0x00003e40, 0x00000000);
  792. isp_write_reg(dev, 0x00003e44, 0x00000001);
  793. isp_write_reg(dev, 0x00003e48, 0x10001000);
  794. isp_write_reg(dev, 0x00003e4c, 0x00000000);
  795. isp_write_reg(dev, 0x00003e50, 0x00000000);
  796. isp_write_reg(dev, 0x00003e54, 0x00000000);
  797. isp_write_reg(dev, 0x00003e58, 0x00080010);
  798. isp_write_reg(dev, 0x00003e5c, 0x00080010);
  799. isp_write_reg(dev, 0x00003e60, 0x01300280);
  800. isp_write_reg(dev, 0x00000018, 0x00001000);
  801. isp_write_reg(dev, 0x00001200, 0x00000001); //why
  802. isp_write_reg(dev, 0x00000418, 0x00000001);
  803. isp_write_reg(dev, 0x00000400, 0x80100686);
  804. isp_write_reg(dev, 0x00000400, 0x80100097);
  805. isp_write_reg(dev, 0x00001300, 0x00000001);
  806. isp_write_reg(dev, 0x00001310, 0x00000038);
  807. isp_write_reg(dev, 0x000014e4, 0x00000238);
  808. isp_write_reg(dev, 0x00001600, 0x0000005c);
  809. isp_write_reg(dev, 0x00000704, 0x00c00222);
  810. isp_write_reg(dev, 0x00000708, 0x00a001e0);
  811. isp_write_reg(dev, 0x0000070c, 0x000a4023);
  812. isp_write_reg(dev, 0x00000710, 0x000a401e);
  813. isp_write_reg(dev, 0x00000714, 0x000b8001);
  814. isp_write_reg(dev, 0x00000718, 0x003540a0);
  815. isp_write_reg(dev, 0x0000071c, 0x00000050);
  816. isp_write_reg(dev, 0x00000720, 0x3aca095b);
  817. isp_write_reg(dev, 0x00000700, 0x00000c42);
  818. isp_info("end %s\n", __func__);
  819. }
  820. int isp_start_stream(struct isp_ic_dev *dev, u32 numFrames)
  821. {
  822. u32 isp_imsc, isp_ctrl;
  823. isp_info("enter %s\n", __func__);
  824. #ifdef ISP_PDAF
  825. isp_write_reg(dev, 0x5d00, 0x1);
  826. #endif
  827. isp_write_reg(dev, REG_ADDR(isp_sh_ctrl), 0x10);
  828. isp_write_reg(dev, REG_ADDR(isp_acq_nr_frames),
  829. (MRV_ISP_ACQ_NR_FRAMES_MASK & numFrames));
  830. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  831. isp_imsc |=
  832. (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK |
  833. MRV_ISP_IMSC_FRAME_IN_MASK | MRV_ISP_IMSC_PIC_SIZE_ERR_MASK | MRV_ISP_IMSC_FLASH_ON_MASK |
  834. MRV_ISP_IMSC_DATA_LOSS_MASK);
  835. /* isp_imsc |= (MRV_ISP_IMSC_FRAME_MASK | MRV_ISP_IMSC_DATA_LOSS_MASK | MRV_ISP_IMSC_FRAME_IN_MASK); */
  836. isp_write_reg(dev, REG_ADDR(isp_icr), 0xFFFFFFFF);
  837. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  838. isp_write_reg(dev, 0x00001320, 1);
  839. isp_write_reg(dev, 0x00001610, 1);
  840. #if 0/*add by shenwuyi for live sensor*/
  841. isp_write_reg(dev, 0x00000c68, 10);/*fream_rete_ctrl*/
  842. isp_write_reg(dev, 0x00002200, 0x00000000); //disable lsc
  843. isp_write_reg(dev, 0x000005bc, 0x00000001); //irq_enable
  844. isp_write_reg(dev, 0x00000538, 0x01000100); //awb_gain_gr
  845. isp_write_reg(dev, 0x0000053c, 0x02270220); //awb_gain_gc
  846. #endif
  847. /*isp_test_bt(dev);*/
  848. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  849. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 1);
  850. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 1);
  851. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  852. /*Set lsc tbl after isp enable*/
  853. if (dev->update_lsc_tbl) {
  854. isp_s_lsc_tbl(dev);
  855. dev->update_lsc_tbl = false;
  856. }
  857. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  858. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1);
  859. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  860. isp_info("exit %s\n", __func__);
  861. return 0;
  862. }
  863. int isp_stop_stream(struct isp_ic_dev *dev)
  864. {
  865. isp_info("enter %s\n", __func__);
  866. isp_write_reg(dev, REG_ADDR(isp_imsc), 0);
  867. isp_disable(dev);
  868. isp_info("exit %s\n", __func__);
  869. return 0;
  870. }
  871. void isp_force_stop(struct isp_ic_dev *dev)
  872. {
  873. pr_info("enter %s\n", __func__);
  874. isp_disable(dev);
  875. mdelay(40);
  876. isp_mi_stop(dev);
  877. isp_stop_stream(dev);
  878. isp_reset(dev);
  879. pr_info("exit %s\n", __func__);
  880. return;
  881. }
  882. int isp_s_cc(struct isp_ic_dev *dev)
  883. {
  884. struct isp_cc_context *cc = &dev->cc;
  885. u32 isp_ctrl, addr;
  886. int i;
  887. isp_info("enter %s\n", __func__);
  888. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  889. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CSM_Y_RANGE, cc->conv_range_y_full);
  890. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CSM_C_RANGE, cc->conv_range_c_full);
  891. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  892. if (cc->update_curve) {
  893. addr = REG_ADDR(isp_cc_coeff_0);
  894. for (i = 0; i < 9; i++) {
  895. isp_write_reg(dev, addr + i * 4,
  896. MRV_ISP_CC_COEFF_0_MASK & cc->lCoeff[i]);
  897. }
  898. }
  899. isp_info("exit %s\n", __func__);
  900. return 0;
  901. }
  902. int isp_s_xtalk(struct isp_ic_dev *dev)
  903. {
  904. struct isp_xtalk_context xtalk = *(&dev->xtalk);
  905. int i;
  906. /* isp_info("enter %s\n", __func__); */
  907. for (i = 0; i < 9; i++) {
  908. #ifdef ISP_CTM_0507 // Coefficient for cross talk matrix.Use bit 11,Values are 12-bit signed fixed-point numbers with 5 bit integer and 7 bit fractional part, ranging from -16 (0x800) to +15.992 (0x7FF).
  909. isp_write_reg(dev, REG_ADDR(cross_talk_coef_block_arr[i]),
  910. MRV_ISP_CT_COEFF_MASK & (xtalk.lCoeff[i] << 1));
  911. #else // Coefficient for cross talk matrix.Values are 11-bit signed fixed-point numbers with 4 bit integer and 7 bit fractional part, ranging from -8 (0x400) to +7.992 (0x3FF).
  912. isp_write_reg(dev, REG_ADDR(cross_talk_coef_block_arr[i]),
  913. MRV_ISP_CT_COEFF_MASK & xtalk.lCoeff[i]);
  914. #endif
  915. }
  916. isp_write_reg(dev, REG_ADDR(isp_ct_offset_r),
  917. (MRV_ISP_CT_OFFSET_R_MASK & xtalk.r));
  918. isp_write_reg(dev, REG_ADDR(isp_ct_offset_g),
  919. (MRV_ISP_CT_OFFSET_G_MASK & xtalk.g));
  920. isp_write_reg(dev, REG_ADDR(isp_ct_offset_b),
  921. (MRV_ISP_CT_OFFSET_B_MASK & xtalk.b));
  922. return 0;
  923. }
  924. int isp_enable_wb(struct isp_ic_dev *dev, bool bEnable)
  925. {
  926. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  927. isp_info("enter %s\n", __func__);
  928. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_AWB_ENABLE, bEnable);
  929. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  930. isp_info("exit %s\n", __func__);
  931. return 0;
  932. }
  933. int isp_enable_gamma_out(struct isp_ic_dev *dev, bool bEnable)
  934. {
  935. u32 isp_ctrl;
  936. struct isp_gamma_out_context *gamma = &dev->gamma_out;
  937. isp_info("enter %s\n", __func__);
  938. gamma->enableGamma = bEnable;
  939. if(gamma->changed || !is_isp_enable(dev))
  940. {
  941. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  942. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_OUT_ENABLE, bEnable);
  943. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  944. gamma->changed = false;
  945. } else {
  946. gamma->changed = true;
  947. }
  948. isp_info("exit %s\n", __func__);
  949. return 0;
  950. }
  951. int isp_s_gamma_out(struct isp_ic_dev *dev)
  952. {
  953. u32 isp_gamma_out_mode;
  954. int i;
  955. u32 isp_ctrl;
  956. struct isp_gamma_out_context *gamma = &dev->gamma_out;
  957. if(gamma->changed || !is_isp_enable(dev)) {
  958. isp_gamma_out_mode = isp_read_reg(dev, REG_ADDR(isp_gamma_out_mode));
  959. REG_SET_SLICE(isp_gamma_out_mode, MRV_ISP_EQU_SEGM, gamma->mode);
  960. isp_write_reg(dev, REG_ADDR(isp_gamma_out_mode), isp_gamma_out_mode);
  961. for (i = 0; i < 17; i++) {
  962. isp_write_reg(dev, REG_ADDR(gamma_out_y_block_arr[i]),
  963. MRV_ISP_ISP_GAMMA_OUT_Y_MASK & gamma->curve[i]);
  964. }
  965. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  966. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_OUT_ENABLE, gamma->enableGamma);
  967. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  968. gamma->changed = false;
  969. } else {
  970. gamma->changed = true;
  971. }
  972. return 0;
  973. }
  974. int isp_s_lsc_tbl(struct isp_ic_dev *dev)
  975. {
  976. int i, n;
  977. u32 isp_ctrl;
  978. u32 sram_addr;
  979. u32 isp_lsc_status;
  980. struct isp_lsc_context *lsc = (&dev->lsc);
  981. //isp_debug("enter %s\n", __func__);
  982. /*need to set tbl after isp_ctrl enable In ISP8000NANO_V1802*/
  983. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  984. /* Enable isp to enable ram clock for write correct table to ram. */
  985. if (!(isp_ctrl & 0x01)) {
  986. dev->update_lsc_tbl = true;
  987. return 0;
  988. }
  989. isp_lsc_status = isp_read_reg(dev, REG_ADDR(isp_lsc_status));
  990. sram_addr = (isp_lsc_status & 0x2U) ? 0U : 153U;
  991. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_addr), sram_addr);
  992. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_addr), sram_addr);
  993. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_addr), sram_addr);
  994. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_addr), sram_addr);
  995. #ifdef ISP_LSC_V2
  996. for (n = 0; n < ((CAMERIC_MAX_LSC_SECTORS + 1) * (CAMERIC_MAX_LSC_SECTORS + 1)); n += CAMERIC_MAX_LSC_SECTORS + 1) {
  997. for (i = 0; i < (CAMERIC_MAX_LSC_SECTORS); i += 2) {
  998. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), (lsc->r[n + i] & 0xFFF) | ((lsc->r[n + i + 1] & 0xFFF) << 12) | ((lsc->r[n + i] >> 12) << 24) | ((lsc->r[n + i + 1] >> 12) << 28));
  999. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), (lsc->gr[n + i] & 0xFFF) | ((lsc->gr[n + i + 1] & 0xFFF) << 12) | ((lsc->gr[n + i] >> 12) << 24) | ((lsc->gr[n + i + 1] >> 12) << 28));
  1000. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), (lsc->gb[n + i] & 0xFFF) | ((lsc->gb[n + i + 1] & 0xFFF) << 12) | ((lsc->gb[n + i] >> 12) << 24) | ((lsc->gb[n + i + 1] >> 12) << 28));
  1001. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), (lsc->b[n + i] & 0xFFF) | ((lsc->b[n + i + 1] & 0xFFF) << 12) | ((lsc->b[n + i] >> 12) << 24) | ((lsc->b[n + i + 1] >> 12) << 28));
  1002. }
  1003. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), (lsc->r[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->r[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  1004. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), (lsc->gr[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->gr[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  1005. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), (lsc->gb[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->gb[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  1006. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), (lsc->b[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->b[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  1007. }
  1008. #else
  1009. for (n = 0;
  1010. n <
  1011. ((CAMERIC_MAX_LSC_SECTORS + 1) * (CAMERIC_MAX_LSC_SECTORS + 1));
  1012. n += CAMERIC_MAX_LSC_SECTORS + 1) {
  1013. /* 17 sectors with 2 values in one DWORD = 9 DWORDs (8 steps + 1 outside loop) */
  1014. for (i = 0; i < (CAMERIC_MAX_LSC_SECTORS); i += 2) {
  1015. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data),
  1016. lsc->r[n +
  1017. i] | (lsc->r[n + i + 1] << 12));
  1018. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data),
  1019. lsc->gr[n +
  1020. i] | (lsc->gr[n + i + 1] << 12));
  1021. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data),
  1022. lsc->gb[n +
  1023. i] | (lsc->gb[n + i + 1] << 12));
  1024. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data),
  1025. lsc->b[n +
  1026. i] | (lsc->b[n + i + 1] << 12));
  1027. }
  1028. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data),
  1029. lsc->r[n + CAMERIC_MAX_LSC_SECTORS]);
  1030. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data),
  1031. lsc->gr[n + CAMERIC_MAX_LSC_SECTORS]);
  1032. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data),
  1033. lsc->gb[n + CAMERIC_MAX_LSC_SECTORS]);
  1034. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data),
  1035. lsc->b[n + CAMERIC_MAX_LSC_SECTORS]);
  1036. }
  1037. #endif
  1038. isp_write_reg(dev, REG_ADDR(isp_lsc_table_sel),
  1039. (isp_lsc_status & 0x2U) ? 0U : 1U);
  1040. //isp_info("exit %s\n", __func__);
  1041. return 0;
  1042. }
  1043. int isp_s_lsc_sec(struct isp_ic_dev *dev)
  1044. {
  1045. int i;
  1046. struct isp_lsc_context *lsc = (&dev->lsc);
  1047. /* isp_info("enter %s\n", __func__); */
  1048. for (i = 0; i < CAEMRIC_GRAD_TBL_SIZE; i += 2) {
  1049. isp_write_reg(dev, REG_ADDR(isp_lsc_xsize_01) + i * 2,
  1050. (lsc->x_size[i] & MRV_LSC_Y_SECT_SIZE_0_MASK) |
  1051. ((lsc->x_size[i + 1]
  1052. << MRV_LSC_X_SECT_SIZE_1_SHIFT)
  1053. & MRV_LSC_X_SECT_SIZE_1_MASK));
  1054. isp_write_reg(dev, REG_ADDR(isp_lsc_ysize_01) + i * 2,
  1055. (lsc->y_size[i] & MRV_LSC_Y_SECT_SIZE_0_MASK) |
  1056. ((lsc->y_size[i + 1]
  1057. << MRV_LSC_Y_SECT_SIZE_1_SHIFT)
  1058. & MRV_LSC_Y_SECT_SIZE_1_MASK));
  1059. isp_write_reg(dev, REG_ADDR(isp_lsc_xgrad_01) + i * 2,
  1060. (lsc->x_grad[i] & MRV_LSC_XGRAD_0_MASK) |
  1061. ((lsc->x_grad[i + 1]
  1062. << MRV_LSC_XGRAD_1_SHIFT)
  1063. & MRV_LSC_XGRAD_1_MASK));
  1064. isp_write_reg(dev, REG_ADDR(isp_lsc_ygrad_01) + i * 2,
  1065. (lsc->y_grad[i] & MRV_LSC_YGRAD_0_MASK) |
  1066. ((lsc->y_grad[i + 1]
  1067. << MRV_LSC_YGRAD_1_SHIFT)
  1068. & MRV_LSC_YGRAD_1_MASK));
  1069. }
  1070. return 0;
  1071. }
  1072. int isp_ioc_read_mis(struct isp_ic_dev *dev, void __user *args)
  1073. {
  1074. isp_mis_list_t* pCList = &dev->circle_list;
  1075. isp_mis_t mis_data;
  1076. u64 ary[2];
  1077. int ret = -1;
  1078. ret = isp_irq_read_circle_queue(&mis_data, pCList);
  1079. if (ret < 0) {
  1080. /*isp_info("%s can not dequeue mis data\n", __func__);*/
  1081. return ret;
  1082. }
  1083. /*isp_info("%s irq src %d val 0x%08x\n", __func__, mis_data.irq_src, mis_data.val);*/
  1084. ary[0] = mis_data.irq_src;
  1085. ary[1] = mis_data.val;
  1086. viv_check_retval(copy_to_user(args, ary, sizeof( ary)));
  1087. return 0;
  1088. }
  1089. static int isp_ioc_read_reg(struct isp_ic_dev *dev, void __user * args)
  1090. {
  1091. struct isp_reg_t reg;
  1092. viv_check_retval(copy_from_user(&reg, args, sizeof(reg)));
  1093. reg.val = isp_read_reg(dev, reg.offset);
  1094. viv_check_retval(copy_to_user(args, &reg, sizeof(reg)));
  1095. return 0;
  1096. }
  1097. static int isp_ioc_write_reg(struct isp_ic_dev *dev, void __user *args)
  1098. {
  1099. struct isp_reg_t reg;
  1100. viv_check_retval((copy_from_user(&reg, args, sizeof(reg))));
  1101. isp_write_reg(dev, reg.offset, reg.val);
  1102. return 0;
  1103. }
  1104. int isp_ioc_disable_isp_off(struct isp_ic_dev *dev, void __user *args)
  1105. {
  1106. u32 isp_imsc;
  1107. isp_info("enter %s\n", __func__);
  1108. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1109. isp_imsc &= ~MRV_ISP_IMSC_ISP_OFF_MASK;
  1110. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  1111. isp_info("exit %s\n", __func__);
  1112. return 0;
  1113. }
  1114. int isp_g_awbmean(struct isp_ic_dev *dev, struct isp_awb_mean *mean)
  1115. {
  1116. u32 reg = isp_read_reg(dev, REG_ADDR(isp_awb_mean));
  1117. /* isp_info("enter %s\n", __func__); */
  1118. mean->g = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_Y__G);
  1119. mean->b = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_CB__B);
  1120. mean->r = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_CR__R);
  1121. mean->no_white_count = isp_read_reg(dev, REG_ADDR(isp_awb_white_cnt));
  1122. return 0;
  1123. }
  1124. int isp_s_ee(struct isp_ic_dev *dev)
  1125. {
  1126. #ifndef ISP_EE
  1127. //isp_err("unsupported function: %s\n", __func__);
  1128. return -EINVAL;
  1129. #else
  1130. struct isp_ee_context *ee = &dev->ee;
  1131. u32 isp_ee_ctrl = isp_read_reg(dev, REG_ADDR(isp_ee_ctrl));
  1132. u32 gain = 0;
  1133. //isp_info("enter %s\n", __func__);
  1134. if (!ee->enable) {
  1135. isp_write_reg(dev, REG_ADDR(isp_ee_ctrl),
  1136. isp_ee_ctrl & ~EE_CTRL_ENABLE_MASK);
  1137. return 0;
  1138. }
  1139. REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_INPUT_SEL, ee->input_sel);
  1140. REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_SOURCE_STRENGTH, ee->src_strength);
  1141. REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_STRENGTH, ee->strength);
  1142. REG_SET_SLICE(gain, EE_UV_GAIN, ee->uv_gain);
  1143. REG_SET_SLICE(gain, EE_EDGE_GAIN, ee->edge_gain);
  1144. isp_write_reg(dev, REG_ADDR(isp_ee_y_gain), ee->y_gain);
  1145. isp_write_reg(dev, REG_ADDR(isp_ee_uv_gain), gain);
  1146. isp_write_reg(dev, REG_ADDR(isp_ee_ctrl),
  1147. isp_ee_ctrl | EE_CTRL_ENABLE_MASK);
  1148. //isp_info("exit %s\n", __func__);
  1149. return 0;
  1150. #endif
  1151. }
  1152. int isp_s_exp(struct isp_ic_dev *dev)
  1153. {
  1154. struct isp_exp_context *exp = &dev->exp;
  1155. u32 isp_exp_ctrl = isp_read_reg(dev, REG_ADDR(isp_exp_ctrl));
  1156. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1157. isp_info("enter %s\n", __func__);
  1158. if (!exp->enable) {
  1159. REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_START, 0);
  1160. isp_write_reg(dev, REG_ADDR(isp_exp_ctrl), isp_exp_ctrl);
  1161. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1162. isp_imsc & ~MRV_ISP_IMSC_EXP_END_MASK);
  1163. return 0;
  1164. }
  1165. isp_write_reg(dev, REG_ADDR(isp_exp_h_offset),
  1166. (MRV_AE_ISP_EXP_H_OFFSET_MASK & exp->window.x));
  1167. isp_write_reg(dev, REG_ADDR(isp_exp_v_offset),
  1168. (MRV_AE_ISP_EXP_V_OFFSET_MASK & exp->window.y));
  1169. isp_write_reg(dev, REG_ADDR(isp_exp_h_size),
  1170. (MRV_AE_ISP_EXP_H_SIZE_MASK & exp->window.width));
  1171. isp_write_reg(dev, REG_ADDR(isp_exp_v_size),
  1172. (MRV_AE_ISP_EXP_V_SIZE_MASK & exp->window.height));
  1173. #ifdef ISP_AE_SHADOW
  1174. isp_write_reg(dev, REG_ADDR(isp_exp_h_offset_shd),
  1175. (MRV_AE_ISP_EXP_H_OFFSET_MASK & exp->window.x));
  1176. isp_write_reg(dev, REG_ADDR(isp_exp_v_offset_shd),
  1177. (MRV_AE_ISP_EXP_V_OFFSET_MASK & exp->window.y));
  1178. isp_write_reg(dev, REG_ADDR(isp_exp_h_size_shd),
  1179. (MRV_AE_ISP_EXP_H_SIZE_MASK & exp->window.width));
  1180. isp_write_reg(dev, REG_ADDR(isp_exp_v_size_shd),
  1181. (MRV_AE_ISP_EXP_V_SIZE_MASK & exp->window.height));
  1182. #endif
  1183. REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_MEAS_MODE, exp->mode);
  1184. REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_START, 1);
  1185. isp_write_reg(dev, REG_ADDR(isp_exp_ctrl), isp_exp_ctrl);
  1186. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1187. isp_imsc | MRV_ISP_IMSC_EXP_END_MASK);
  1188. isp_info("exit %s\n", __func__);
  1189. return 0;
  1190. }
  1191. int isp_s_hdrexp(struct isp_ic_dev *dev)
  1192. {
  1193. struct isp_exp_context *hdrexp = &dev->hdrexp;
  1194. u32 isp_hdr_exp_conf = isp_read_reg(dev, REG_ADDR(isp_hdr_exp_conf));
  1195. u32 isp_stitching_imsc = isp_read_reg(dev, REG_ADDR(isp_stitching_imsc));
  1196. isp_info("enter %s\n", __func__);
  1197. if (!dev->hdrexp.enable) {
  1198. isp_info("%s, hdr disabled\n",__func__);
  1199. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_START, 0);
  1200. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_conf), isp_hdr_exp_conf);
  1201. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc & ~0x38);
  1202. return 0;
  1203. }
  1204. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_h_offset),
  1205. (MRV_ISP_HDR_EXP_H_OFFSET_MASK & hdrexp->window.x));
  1206. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_v_offset),
  1207. (MRV_ISP_HDR_EXP_V_OFFSET_MASK & hdrexp->window.y));
  1208. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_h_size),
  1209. (MRV_ISP_HDR_EXP_H_SIZE_MASK & hdrexp->window.width));
  1210. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_v_size),
  1211. (MRV_ISP_HDR_EXP_V_SIZE_MASK & hdrexp->window.height));
  1212. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_MEAS_MODE, hdrexp->mode);
  1213. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_SRC_SEL, 1); //hardware only support 1
  1214. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_START, 1);
  1215. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_conf), isp_hdr_exp_conf);
  1216. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc | 0x38);
  1217. return 0;
  1218. }
  1219. int isp_g_expmean(struct isp_ic_dev *dev, u8 *mean)
  1220. {
  1221. int i = 0;
  1222. /* isp_info("enter %s\n", __func__); */
  1223. if (!dev || !mean)
  1224. return -EINVAL;
  1225. for (; i < 25; i++) {
  1226. mean[i] = isp_read_reg(dev, REG_ADDR(isp_exp_mean_00) + i * 4);
  1227. }
  1228. return 0;
  1229. }
  1230. int isp_g_hdrexpmean(struct isp_ic_dev *dev, u8 * mean)
  1231. {
  1232. int i = 0;
  1233. isp_info("enter %s\n", __func__);
  1234. if (!dev || !mean)
  1235. return -EINVAL;
  1236. for (; i < 75; i++) {
  1237. mean[i] = isp_read_reg(dev, REG_ADDR(isp_hdr_exp_statistics[i]));
  1238. }
  1239. return 0;
  1240. }
  1241. #ifdef ISP_HIST256
  1242. #define HIST_BIN_TOTAL 256
  1243. #else
  1244. #define HIST_BIN_TOTAL 16
  1245. #endif
  1246. int isp_s_hist(struct isp_ic_dev *dev)
  1247. {
  1248. struct isp_hist_context *hist = &dev->hist;
  1249. #ifdef ISP_HIST256
  1250. u32 isp_hist256_prop = isp_read_reg(dev, REG_ADDR(isp_hist256_prop));
  1251. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1252. int i;
  1253. if (!hist->enable) {
  1254. REG_SET_SLICE(isp_hist256_prop, MRV_HIST_MODE,
  1255. MRV_HIST_MODE_NONE);
  1256. isp_write_reg(dev, REG_ADDR(isp_hist256_prop),
  1257. isp_hist256_prop);
  1258. //isp_write_reg(dev, REG_ADDR(isp_imsc),
  1259. // isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1260. return 0;
  1261. }
  1262. isp_write_reg(dev, REG_ADDR(isp_hist256_h_offs),
  1263. (MRV_HIST_H_OFFSET_MASK & hist->window.x));
  1264. isp_write_reg(dev, REG_ADDR(isp_hist256_v_offs),
  1265. (MRV_HIST_V_OFFSET_MASK & hist->window.y));
  1266. isp_write_reg(dev, REG_ADDR(isp_hist256_h_size),
  1267. (MRV_HIST_H_SIZE_MASK & hist->window.width));
  1268. isp_write_reg(dev, REG_ADDR(isp_hist256_v_size),
  1269. (MRV_HIST_V_SIZE_MASK & hist->window.height));
  1270. for (i = 0; i < 24; i += 4) {
  1271. isp_write_reg(dev, REG_ADDR(isp_hist256_weight_00to30) + i,
  1272. hist->weight[i +
  1273. 0] | (hist->weight[i +
  1274. 1] << 8) |
  1275. (hist->weight[i + 2] << 16) | (hist->weight[i +
  1276. 3] <<
  1277. 24));
  1278. }
  1279. isp_write_reg(dev, REG_ADDR(isp_hist256_weight_44), hist->weight[24]);
  1280. REG_SET_SLICE(isp_hist256_prop, MRV_HIST_STEPSIZE, hist->step_size);
  1281. REG_SET_SLICE(isp_hist256_prop, MRV_HIST_MODE, hist->mode);
  1282. isp_write_reg(dev, REG_ADDR(isp_hist256_prop), isp_hist256_prop);
  1283. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1284. isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1285. #else
  1286. u32 isp_hist_prop = isp_read_reg(dev, REG_ADDR(isp_hist_prop));
  1287. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1288. int i;
  1289. isp_info("enter %s\n", __func__);
  1290. if (!hist->enable) {
  1291. REG_SET_SLICE(isp_hist_prop, MRV_HIST_MODE, MRV_HIST_MODE_NONE);
  1292. isp_write_reg(dev, REG_ADDR(isp_hist_prop), isp_hist_prop);
  1293. //isp_write_reg(dev, REG_ADDR(isp_imsc),
  1294. // isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1295. return 0;
  1296. }
  1297. isp_write_reg(dev, REG_ADDR(isp_hist_h_offs),
  1298. (MRV_HIST_H_OFFSET_MASK & hist->window.x));
  1299. isp_write_reg(dev, REG_ADDR(isp_hist_v_offs),
  1300. (MRV_HIST_V_OFFSET_MASK & hist->window.y));
  1301. isp_write_reg(dev, REG_ADDR(isp_hist_h_size),
  1302. (MRV_HIST_H_SIZE_MASK & hist->window.width));
  1303. isp_write_reg(dev, REG_ADDR(isp_hist_v_size),
  1304. (MRV_HIST_V_SIZE_MASK & hist->window.height));
  1305. for (i = 0; i < 24; i += 4) {
  1306. isp_write_reg(dev, REG_ADDR(isp_hist_weight_00to30) + i,
  1307. hist->weight[i + 0] |
  1308. (hist->weight[i + 1] << 8) |
  1309. (hist->weight[i + 2] << 16) |
  1310. (hist->weight[i + 3] << 24));
  1311. }
  1312. isp_write_reg(dev, REG_ADDR(isp_hist_weight_44), hist->weight[24]);
  1313. REG_SET_SLICE(isp_hist_prop, MRV_HIST_STEPSIZE, hist->step_size);
  1314. REG_SET_SLICE(isp_hist_prop, MRV_HIST_MODE, hist->mode);
  1315. isp_write_reg(dev, REG_ADDR(isp_hist_prop), isp_hist_prop);
  1316. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1317. isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1318. isp_info("exit %s\n", __func__);
  1319. #endif
  1320. return 0;
  1321. }
  1322. int isp_s_hdrhist(struct isp_ic_dev *dev)
  1323. {
  1324. struct isp_hist_context *hdrhist = &dev->hdrhist;
  1325. u32 isp_hdr_hist_prop = isp_read_reg(dev, REG_ADDR(isp_hdr_hist_prop));
  1326. u32 isp_stitching_imsc = isp_read_reg(dev, REG_ADDR(isp_stitching_imsc));
  1327. isp_info("enter %s\n", __func__);
  1328. if (!dev->hdrhist.enable) {
  1329. isp_info("%s, hdr disable\n", __func__);
  1330. REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_MODE, MRV_HIST_MODE_NONE);
  1331. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_prop), isp_hdr_hist_prop);
  1332. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc),
  1333. isp_stitching_imsc & ~0x1c0);
  1334. return 0;
  1335. }
  1336. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_h_offs),
  1337. (MRV_HIST_H_OFFSET_MASK & hdrhist->window.x));
  1338. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_v_offs),
  1339. (MRV_HIST_V_OFFSET_MASK & hdrhist->window.y));
  1340. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_h_size),
  1341. (MRV_HIST_H_SIZE_MASK & hdrhist->window.width));
  1342. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_v_size),
  1343. (MRV_HIST_V_SIZE_MASK & hdrhist->window.height));
  1344. REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_STEPSIZE, hdrhist->step_size);
  1345. REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_MODE, hdrhist->mode);
  1346. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_prop), isp_hdr_hist_prop);
  1347. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc | 0x1c0);
  1348. return 0;
  1349. }
  1350. int isp_g_histmean(struct isp_ic_dev *dev, u32 *mean)
  1351. {
  1352. int i = 0;
  1353. /* isp_info("enter %s\n", __func__); */
  1354. if (!dev || !mean)
  1355. return -EINVAL;
  1356. #ifdef ISP_HIST256
  1357. for (; i < HIST_BIN_TOTAL; i++) {
  1358. mean[i] = isp_read_reg(dev, REG_ADDR(isp_hist256_bin_n));
  1359. }
  1360. #else
  1361. for (; i < HIST_BIN_TOTAL; i++) {
  1362. mean[i] = isp_read_reg(dev,
  1363. REG_ADDR(histogram_measurement_result_arr[i]));
  1364. }
  1365. #endif
  1366. return 0;
  1367. }
  1368. int isp_g_hdrhistmean(struct isp_ic_dev *dev, u32 * mean)
  1369. {
  1370. int i = 0;
  1371. isp_info("enter %s\n", __func__);
  1372. if (!dev || !mean)
  1373. return -EINVAL;
  1374. // size is fixed 48 now, contain 3 channels
  1375. for (; i < 48; i++) {
  1376. mean[i] = isp_read_reg(dev, REG_ADDR(isp_hdr_hist_statistics[i]));
  1377. }
  1378. return 0;
  1379. }
  1380. int isp_s_hist64(struct isp_ic_dev *dev)
  1381. {
  1382. #ifndef ISP_HIST64
  1383. //isp_err("Not supported hist64 module\n");
  1384. return -1;
  1385. #else
  1386. struct isp_hist64_context *hist64 = &dev->hist64;
  1387. u32 isp64_hist_prop = isp_read_reg(dev, REG_ADDR(isp64_hist_prop));
  1388. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1389. u32 isp64_hist_subsampling = isp_read_reg(dev, REG_ADDR(isp64_hist_subsampling));
  1390. u32 isp64_hist_sample_range = isp_read_reg(dev, REG_ADDR(isp64_hist_sample_range));
  1391. u32 isp64_hist_coeff_r = 0, isp64_hist_coeff_g = 0, isp64_hist_coeff_b = 0;
  1392. int i;
  1393. if (!hist64->enable) {
  1394. REG_SET_SLICE(isp64_hist_prop, MRV_HIST_MODE,
  1395. MRV_HIST_MODE_NONE);
  1396. isp_write_reg(dev, REG_ADDR(isp64_hist_prop),
  1397. isp64_hist_prop);
  1398. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1399. isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1400. //isp_write_reg(dev, REG_ADDR(isp64_hist_ctrl),
  1401. /// hist64->enable & ~MRV_HIST_UPDATE_ENABLE_MASK);
  1402. return 0;
  1403. }
  1404. isp_write_reg(dev, REG_ADDR(isp64_hist_h_offs),
  1405. (MRV_HIST_H_OFFSET_MASK & hist64->window.x));
  1406. isp_write_reg(dev, REG_ADDR(isp64_hist_v_offs),
  1407. (MRV_HIST_V_OFFSET_MASK & hist64->window.y));
  1408. isp_write_reg(dev, REG_ADDR(isp64_hist_h_size),
  1409. (MRV_HIST_H_SIZE_MASK & hist64->window.width));
  1410. isp_write_reg(dev, REG_ADDR(isp64_hist_v_size),
  1411. (MRV_HIST_V_SIZE_MASK & hist64->window.height));
  1412. for (i = 0; i < 24; i += 4) {
  1413. isp_write_reg(dev, REG_ADDR(isp64_hist_weight_00to30) + i,
  1414. hist64->weight[i +
  1415. 0] | (hist64->weight[i +
  1416. 1] << 8) |
  1417. (hist64->weight[i + 2] << 16) | (hist64->weight[i +
  1418. 3] <<
  1419. 24));
  1420. }
  1421. isp_write_reg(dev, REG_ADDR(isp64_hist_weight_44), hist64->weight[24]);
  1422. REG_SET_SLICE(isp64_hist_prop, MRV_HIST_CHANNEL_SELECT, hist64->channel);
  1423. REG_SET_SLICE(isp64_hist_prop, MRV_HIST_MODE, hist64->mode);
  1424. REG_SET_SLICE(isp64_hist_subsampling, MRV_HIST_V_STEPSIZE, hist64->vStepSize);
  1425. REG_SET_SLICE(isp64_hist_subsampling, MRV_HIST_H_STEP_INC, hist64->hStepInc);
  1426. REG_SET_SLICE(isp64_hist_sample_range, MRV_HIST_SAMPLE_OFFSET, hist64->sample_offset);
  1427. REG_SET_SLICE(isp64_hist_sample_range, MRV_HIST_SAMPLE_SHIFT, hist64->sample_shift);
  1428. REG_SET_SLICE(isp64_hist_coeff_r, MRV_HIST_COEFF_R, hist64->r_coeff);
  1429. REG_SET_SLICE(isp64_hist_coeff_g, MRV_HIST_COEFF_G, hist64->g_coeff);
  1430. REG_SET_SLICE(isp64_hist_coeff_b, MRV_HIST_COEFF_B, hist64->b_coeff);
  1431. isp_write_reg(dev, REG_ADDR(isp64_hist_subsampling), isp64_hist_subsampling);
  1432. isp_write_reg(dev, REG_ADDR(isp64_hist_sample_range), isp64_hist_sample_range);
  1433. isp_write_reg(dev, REG_ADDR(isp64_hist_prop), isp64_hist_prop);
  1434. isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_r), isp64_hist_coeff_r);
  1435. isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_g), isp64_hist_coeff_g);
  1436. isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_b), isp64_hist_coeff_b);
  1437. isp_write_reg(dev, REG_ADDR(isp64_hist_ctrl),
  1438. hist64->enable);
  1439. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1440. isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1441. return 0;
  1442. #endif
  1443. }
  1444. #define HIST64_BIN_TOTAL 32
  1445. int isp_g_hist64mean(struct isp_ic_dev *dev, u32 *mean)
  1446. {
  1447. #ifndef ISP_HIST64
  1448. //isp_err("Not supported hist64 module\n");
  1449. return -1;
  1450. #else
  1451. int i = 0;
  1452. isp_info("enter %s\n", __func__);
  1453. if (!dev || !mean)
  1454. return -EINVAL;
  1455. for (; i < HIST64_BIN_TOTAL; i++) {
  1456. mean[i] = isp_read_reg(dev,
  1457. REG_ADDR(isp64_histogram_measurement_result_arr[i]));
  1458. }
  1459. isp_info("exit %s\n", __func__);
  1460. return 0;
  1461. #endif
  1462. }
  1463. int isp_g_hist64_vstart_status(struct isp_ic_dev *dev, u32 *status)
  1464. {
  1465. #ifndef ISP_HIST64
  1466. //isp_err("Not supported hist64 module\n");
  1467. return -1;
  1468. #else
  1469. /* isp_info("enter %s\n", __func__); */
  1470. if (!dev || !status)
  1471. return -EINVAL;
  1472. *status = isp_read_reg(dev, REG_ADDR(isp64_hist_vstart_status));
  1473. return 0;
  1474. #endif
  1475. }
  1476. int isp_update_hist64(struct isp_ic_dev *dev)
  1477. {
  1478. #ifndef ISP_HIST64
  1479. //isp_err("Not supported hist64\n");
  1480. return -1;
  1481. #else
  1482. struct isp_hist64_context* hist64 =&dev->hist64;
  1483. isp_write_reg(dev, REG_ADDR(isp64_hist_forced_upd_start_line),hist64->forced_upd_start_line);
  1484. isp_write_reg(dev, REG_ADDR(isp64_hist_forced_update), hist64->forced_upd);
  1485. return 0;
  1486. #endif
  1487. }
  1488. int isp_s_ge(struct isp_ic_dev *dev)
  1489. {
  1490. #ifndef ISP_GREENEQUILIBRATE
  1491. //isp_err("unsupported function %s\n", __func__);
  1492. return -1;
  1493. #else
  1494. struct isp_ge_context *ge = &dev->ge;
  1495. u32 green_equilibrate_ctrl =
  1496. isp_read_reg(dev, REG_ADDR(green_equilibrate_ctrl));
  1497. u32 green_equilibrate_hcnt_dummy = 0;
  1498. isp_info("enter %s\n", __func__);
  1499. if (!ge->enable) {
  1500. REG_SET_SLICE(green_equilibrate_ctrl,
  1501. ISP_GREEN_EQUILIBTATE_ENABLE, 0);
  1502. isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl),
  1503. green_equilibrate_ctrl);
  1504. return 0;
  1505. }
  1506. REG_SET_SLICE(green_equilibrate_ctrl, ISP_GREEN_EQUILIBTATE_TH,
  1507. ge->threshold);
  1508. REG_SET_SLICE(green_equilibrate_ctrl, ISP_GREEN_EQUILIBTATE_ENABLE, 1);
  1509. REG_SET_SLICE(green_equilibrate_hcnt_dummy,
  1510. ISP_GREEN_EQUILIBTATE_HCNT_DUMMY, ge->h_dummy);
  1511. isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl),
  1512. green_equilibrate_ctrl);
  1513. isp_write_reg(dev, REG_ADDR(green_equilibrate_hcnt_dummy),
  1514. green_equilibrate_hcnt_dummy);
  1515. isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl_shd),
  1516. green_equilibrate_ctrl);
  1517. isp_info("exit %s\n", __func__);
  1518. return 0;
  1519. #endif
  1520. }
  1521. int isp_s_ca(struct isp_ic_dev *dev)
  1522. {
  1523. #ifndef ISP_CA
  1524. //isp_err("unsupported function %s\n", __func__);
  1525. return -1;
  1526. #else
  1527. struct isp_ca_context *ca = &dev->ca;
  1528. u32 isp_curve_ctrl = isp_read_reg(dev, REG_ADDR(isp_curve_ctrl));
  1529. // u32 isp_curve_lut_x_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_x_addr));
  1530. // u32 isp_curve_lut_luma_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_luma_addr));
  1531. // u32 isp_curve_lut_chroma_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_chroma_addr));
  1532. // u32 isp_curve_lut_shift_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_shift_addr));
  1533. int i = 0;
  1534. /*isp_info("enter %s\n", __func__);*/
  1535. if (!ca->enable) {
  1536. REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_ENABLE, 0);
  1537. isp_write_reg(dev, REG_ADDR(isp_curve_ctrl), isp_curve_ctrl);
  1538. return 0;
  1539. }
  1540. isp_write_reg(dev, REG_ADDR(isp_curve_lut_x_addr), 0);
  1541. isp_write_reg(dev, REG_ADDR(isp_curve_lut_luma_addr), 0);
  1542. isp_write_reg(dev, REG_ADDR(isp_curve_lut_chroma_addr), 0);
  1543. isp_write_reg(dev, REG_ADDR(isp_curve_lut_shift_addr), 0);
  1544. for (i = 0; i < CA_CURVE_DATA_TABLE_LEN; i++) {
  1545. isp_write_reg(dev, REG_ADDR(isp_curve_lut_x_write_data),
  1546. dev->ca.lut_x[i]);
  1547. isp_write_reg(dev, REG_ADDR(isp_curve_lut_luma_write_data),
  1548. dev->ca.lut_luma[i]);
  1549. isp_write_reg(dev, REG_ADDR(isp_curve_lut_chroma_write_data),
  1550. dev->ca.lut_chroma[i]);
  1551. isp_write_reg(dev, REG_ADDR(isp_curve_lut_shift_write_data),
  1552. dev->ca.lut_shift[i]);
  1553. }
  1554. REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_MODE, dev->ca.mode);
  1555. REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_ENABLE, 1);
  1556. isp_write_reg(dev, REG_ADDR(isp_curve_ctrl), isp_curve_ctrl);
  1557. /*isp_info("exit %s\n", __func__);*/
  1558. return 0;
  1559. #endif
  1560. }
  1561. int isp_s_dpcc(struct isp_ic_dev *dev)
  1562. {
  1563. struct isp_dpcc_context *dpcc = &dev->dpcc;
  1564. const u32 reg_gap = 20;
  1565. int i;
  1566. u32 isp_dpcc_mode = isp_read_reg(dev, REG_ADDR(isp_dpcc_mode));
  1567. isp_info("enter %s\n", __func__);
  1568. if (!dpcc->enable) {
  1569. REG_SET_SLICE(isp_dpcc_mode, MRV_DPCC_ISP_DPCC_ENABLE, 0);
  1570. } else {
  1571. REG_SET_SLICE(isp_dpcc_mode, MRV_DPCC_ISP_DPCC_ENABLE, 1);
  1572. }
  1573. isp_write_reg(dev, REG_ADDR(isp_dpcc_mode), dpcc->mode);
  1574. isp_write_reg(dev, REG_ADDR(isp_dpcc_output_mode), dpcc->outmode);
  1575. isp_write_reg(dev, REG_ADDR(isp_dpcc_set_use), dpcc->set_use);
  1576. for (i = 0; i < 3; i++) {
  1577. isp_write_reg(dev, REG_ADDR(isp_dpcc_methods_set_1) + i * 4,
  1578. 0x1FFF & dpcc->methods_set[i]);
  1579. isp_write_reg(dev,
  1580. REG_ADDR(isp_dpcc_line_thresh_1) + i * reg_gap,
  1581. 0xFFFF & dpcc->params[i].line_thresh);
  1582. isp_write_reg(dev,
  1583. REG_ADDR(isp_dpcc_line_mad_fac_1) + i * reg_gap,
  1584. 0x3F3F & dpcc->params[i].line_mad_fac);
  1585. isp_write_reg(dev, REG_ADDR(isp_dpcc_pg_fac_1) + i * reg_gap,
  1586. 0x3F3F & dpcc->params[i].pg_fac);
  1587. isp_write_reg(dev,
  1588. REG_ADDR(isp_dpcc_rnd_thresh_1) + i * reg_gap,
  1589. 0xFFFF & dpcc->params[i].rnd_thresh);
  1590. isp_write_reg(dev, REG_ADDR(isp_dpcc_rg_fac_1) + i * reg_gap,
  1591. 0x3F3F & dpcc->params[i].rg_fac);
  1592. }
  1593. isp_write_reg(dev, REG_ADDR(isp_dpcc_ro_limits), dpcc->ro_limits);
  1594. isp_write_reg(dev, REG_ADDR(isp_dpcc_rnd_offs), dpcc->rnd_offs);
  1595. isp_write_reg(dev, REG_ADDR(isp_dpcc_mode), isp_dpcc_mode);
  1596. isp_info("exit %s\n", __func__);
  1597. return 0;
  1598. }
  1599. int isp_s_flt(struct isp_ic_dev *dev)
  1600. {
  1601. struct flt_denoise_type {
  1602. u32 thresh_sh0;
  1603. u32 thresh_sh1;
  1604. u32 thresh_bl0;
  1605. u32 thresh_bl1;
  1606. u32 stage_select;
  1607. u32 vmode;
  1608. u32 hmode;
  1609. };
  1610. struct flt_sharpen_type {
  1611. u32 fac_sh0;
  1612. u32 fac_sh1;
  1613. u32 fac_mid;
  1614. u32 fac_bl0;
  1615. u32 fac_bl1;
  1616. };
  1617. static struct flt_denoise_type denoise_tbl[] = {
  1618. {0, 0, 0, 0, 6, MRV_FILT_FILT_CHR_V_MODE_STATIC8,
  1619. MRV_FILT_FILT_CHR_H_MODE_BYPASS},
  1620. {18, 33, 8, 2, 6, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1621. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1622. {26, 44, 13, 5, 4, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1623. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1624. {36, 51, 23, 10, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1625. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1626. {41, 67, 26, 15, 3, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1627. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1628. {75, 10, 50, 20, 3, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1629. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1630. {90, 120, 60, 26, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1631. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1632. {120, 150, 80, 51, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1633. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1634. {170, 200, 140, 100, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1635. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1636. {250, 300, 180, 150, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1637. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1638. {1023, 1023, 1023, 1023, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1639. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1640. {1023, 1023, 1023, 1023, 0, MRV_FILT_FILT_CHR_V_MODE_BYPASS,
  1641. MRV_FILT_FILT_CHR_H_MODE_BYPASS},
  1642. };
  1643. static struct flt_sharpen_type sharpen_tbl[] = {
  1644. {0x4, 0x4, 0x4, 0x2, 0x0},
  1645. {0x7, 0x8, 0x6, 0x2, 0x0},
  1646. {0xA, 0xC, 0x8, 0x4, 0x0},
  1647. {0xC, 0x10, 0xA, 0x6, 0x2},
  1648. {0x16, 0x16, 0xC, 0x8, 0x4},
  1649. {0x14, 0x1B, 0x10, 0xA, 0x4},
  1650. {0x1A, 0x20, 0x13, 0xC, 0x6},
  1651. {0x1E, 0x26, 0x17, 0x10, 0x8},
  1652. {0x24, 0x2C, 0x1D, 0x15, 0x0D},
  1653. {0x2A, 0x30, 0x22, 0x1A, 0x14},
  1654. {0x30, 0x3F, 0x28, 0x24, 0x20},
  1655. };
  1656. // isp_info("enter %s\n", __func__);
  1657. if(dev->flt.changed || !is_isp_enable(dev))
  1658. {
  1659. struct isp_flt_context *flt = &dev->flt;
  1660. u32 isp_flt_mode = isp_read_reg(dev, REG_ADDR(isp_filt_mode));
  1661. if (!flt->enable) {
  1662. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_ENABLE, 0);
  1663. isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode);
  1664. return 0;
  1665. }
  1666. if (flt->denoise >= 0) {
  1667. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_sh0),
  1668. denoise_tbl[flt->denoise].thresh_sh0);
  1669. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_sh1),
  1670. denoise_tbl[flt->denoise].thresh_sh1);
  1671. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_bl0),
  1672. denoise_tbl[flt->denoise].thresh_bl0);
  1673. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_bl1),
  1674. denoise_tbl[flt->denoise].thresh_bl1);
  1675. REG_SET_SLICE(isp_flt_mode, MRV_FILT_STAGE1_SELECT,
  1676. denoise_tbl[flt->denoise].stage_select);
  1677. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_CHR_V_MODE,
  1678. denoise_tbl[flt->denoise].vmode);
  1679. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_CHR_H_MODE,
  1680. denoise_tbl[flt->denoise].hmode);
  1681. }
  1682. if (flt->sharpen >= 0) {
  1683. isp_write_reg(dev, REG_ADDR(isp_filt_fac_sh0),
  1684. sharpen_tbl[flt->sharpen].fac_sh0);
  1685. isp_write_reg(dev, REG_ADDR(isp_filt_fac_sh1),
  1686. sharpen_tbl[flt->sharpen].fac_sh1);
  1687. isp_write_reg(dev, REG_ADDR(isp_filt_fac_mid),
  1688. sharpen_tbl[flt->sharpen].fac_mid);
  1689. isp_write_reg(dev, REG_ADDR(isp_filt_fac_bl0),
  1690. sharpen_tbl[flt->sharpen].fac_bl0);
  1691. isp_write_reg(dev, REG_ADDR(isp_filt_fac_bl1),
  1692. sharpen_tbl[flt->sharpen].fac_bl1);
  1693. }
  1694. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_MODE,
  1695. MRV_FILT_FILT_MODE_DYNAMIC);
  1696. isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode);
  1697. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_ENABLE, 1);
  1698. isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode);
  1699. isp_write_reg(dev, REG_ADDR(isp_filt_lum_weight), 0x00032040);
  1700. dev->flt.changed = false;
  1701. } else {
  1702. dev->flt.changed = true;
  1703. }
  1704. isp_info("exit %s\n", __func__);
  1705. return 0;
  1706. }
  1707. int isp_s_cac(struct isp_ic_dev *dev)
  1708. {
  1709. struct isp_cac_context *cac = &dev->cac;
  1710. u32 val = 0;
  1711. u32 isp_cac_ctrl = isp_read_reg(dev, REG_ADDR(isp_cac_ctrl));
  1712. isp_info("enter %s\n", __func__);
  1713. if (!cac->enable) {
  1714. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_CAC_EN, 0);
  1715. isp_write_reg(dev, REG_ADDR(isp_cac_ctrl), isp_cac_ctrl);
  1716. return 0;
  1717. }
  1718. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_H_CLIP_MODE, cac->hmode);
  1719. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_V_CLIP_MODE, cac->vmode);
  1720. isp_write_reg(dev, REG_ADDR(isp_cac_count_start),
  1721. cac->hstart | (cac->vstart << 16));
  1722. isp_write_reg(dev, REG_ADDR(isp_cac_a), cac->ar | (cac->ab << 16));
  1723. isp_write_reg(dev, REG_ADDR(isp_cac_b), cac->br | (cac->bb << 16));
  1724. isp_write_reg(dev, REG_ADDR(isp_cac_c), cac->cr | (cac->cb << 16));
  1725. REG_SET_SLICE(val, MRV_CAC_X_NS, cac->xns);
  1726. REG_SET_SLICE(val, MRV_CAC_X_NF, cac->xnf);
  1727. isp_write_reg(dev, REG_ADDR(isp_cac_x_norm), val);
  1728. val = 0;
  1729. REG_SET_SLICE(val, MRV_CAC_Y_NS, cac->yns);
  1730. REG_SET_SLICE(val, MRV_CAC_Y_NF, cac->ynf);
  1731. isp_write_reg(dev, REG_ADDR(isp_cac_y_norm), val);
  1732. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_CAC_EN, 1);
  1733. isp_write_reg(dev, REG_ADDR(isp_cac_ctrl), isp_cac_ctrl);
  1734. isp_info("exit %s\n", __func__);
  1735. return 0;
  1736. }
  1737. int isp_s_deg(struct isp_ic_dev *dev)
  1738. {
  1739. struct isp_deg_context *deg = &dev->deg;
  1740. int i;
  1741. u32 isp_gamma_dx_lo = 0;
  1742. u32 isp_gamma_dx_hi = 0;
  1743. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  1744. isp_info("enter %s\n", __func__);
  1745. if (!deg->enable) {
  1746. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_IN_ENABLE, 0);
  1747. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  1748. return 0;
  1749. }
  1750. for (i = 0; i < 8; i++) {
  1751. isp_gamma_dx_lo |= deg->segment[i] << (i * 4);
  1752. isp_gamma_dx_hi |= deg->segment[i + 8] << (i * 4);
  1753. }
  1754. isp_write_reg(dev, REG_ADDR(isp_gamma_dx_lo), isp_gamma_dx_lo);
  1755. isp_write_reg(dev, REG_ADDR(isp_gamma_dx_hi), isp_gamma_dx_hi);
  1756. for (i = 0; i < 17; i++) {
  1757. isp_write_reg(dev, REG_ADDR(degamma_r_y_block_arr[i]),
  1758. deg->r[i]);
  1759. isp_write_reg(dev, REG_ADDR(degamma_g_y_block_arr[i]),
  1760. deg->g[i]);
  1761. isp_write_reg(dev, REG_ADDR(degamma_b_y_block_arr[i]),
  1762. deg->b[i]);
  1763. }
  1764. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_IN_ENABLE, 1);
  1765. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  1766. isp_info("exit %s\n", __func__);
  1767. return 0;
  1768. }
  1769. static u32 get_eff_coeff(int decimal)
  1770. {
  1771. u32 value = 0;
  1772. if (decimal <= -6)
  1773. value = 15;
  1774. else if (decimal <= -3)
  1775. value = 14;
  1776. else if (decimal == -2)
  1777. value = 13;
  1778. else if (decimal == -1)
  1779. value = 12;
  1780. else if (decimal == 0)
  1781. value = 0;
  1782. else if (decimal == 1)
  1783. value = 8;
  1784. else if (decimal == 2)
  1785. value = 9;
  1786. else if (decimal < 6)
  1787. value = 10;
  1788. else
  1789. value = 11;
  1790. return value;
  1791. }
  1792. int isp_s_ie(struct isp_ic_dev *dev)
  1793. {
  1794. struct isp_ie_context *ie = &dev->ie;
  1795. u32 img_eff_ctrl = isp_read_reg(dev, REG_ADDR(img_eff_ctrl));
  1796. u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl));
  1797. u32 vi_ircl = isp_read_reg(dev, REG_ADDR(vi_ircl));
  1798. u32 img_eff_tint = isp_read_reg(dev, REG_ADDR(img_eff_tint));
  1799. u32 img_eff_color_sel = isp_read_reg(dev, REG_ADDR(img_eff_color_sel));
  1800. u32 mat[9];
  1801. u32 sharpen = 0;
  1802. int i;
  1803. isp_info("enter %s\n", __func__);
  1804. REG_SET_SLICE(vi_ircl, MRV_VI_IE_SOFT_RST, 1);
  1805. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  1806. if (!ie->enable) {
  1807. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_CFG_UPD,
  1808. MRV_IMGEFF_CFG_UPD_UPDATE);
  1809. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_BYPASS_MODE,
  1810. MRV_IMGEFF_BYPASS_MODE_BYPASS);
  1811. REG_SET_SLICE(vi_iccl, MRV_VI_IE_CLK_ENABLE, 0);
  1812. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  1813. isp_write_reg(dev, REG_ADDR(img_eff_ctrl), img_eff_ctrl);
  1814. return 0;
  1815. }
  1816. REG_SET_SLICE(vi_ircl, MRV_VI_IE_SOFT_RST, 0);
  1817. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  1818. REG_SET_SLICE(vi_iccl, MRV_VI_IE_CLK_ENABLE, 1);
  1819. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  1820. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_EFFECT_MODE, ie->mode);
  1821. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_FULL_RANGE, ie->full_range);
  1822. for (i = 0; i < 9; i++)
  1823. mat[i] = get_eff_coeff(ie->m[i]);
  1824. if (ie->mode == MRV_IMGEFF_EFFECT_MODE_SEPIA) {
  1825. img_eff_tint = isp_read_reg(dev, REG_ADDR(img_eff_tint));
  1826. REG_SET_SLICE(img_eff_tint, MRV_IMGEFF_INCR_CR, ie->tint_cr);
  1827. REG_SET_SLICE(img_eff_tint, MRV_IMGEFF_INCR_CB, ie->tint_cb);
  1828. isp_write_reg(dev, REG_ADDR(img_eff_tint), img_eff_tint);
  1829. } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_COLOR_SEL) {
  1830. REG_SET_SLICE(img_eff_color_sel, MRV_IMGEFF_COLOR_SELECTION,
  1831. ie->color_sel);
  1832. REG_SET_SLICE(img_eff_color_sel, MRV_IMGEFF_COLOR_THRESHOLD,
  1833. ie->color_thresh);
  1834. isp_write_reg(dev, REG_ADDR(img_eff_color_sel),
  1835. img_eff_color_sel);
  1836. } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_EMBOSS) {
  1837. isp_write_reg(dev, REG_ADDR(img_eff_mat_1),
  1838. mat[0] | (mat[1] << 4) | (mat[2] << 8) | (mat[3]
  1839. << 12));
  1840. isp_write_reg(dev, REG_ADDR(img_eff_mat_2),
  1841. mat[4] | (mat[5] << 4) | (mat[6] << 8) | (mat[7]
  1842. << 12));
  1843. isp_write_reg(dev, REG_ADDR(img_eff_mat_3), mat[8]);
  1844. } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_SKETCH ||
  1845. ie->mode == MRV_IMGEFF_EFFECT_MODE_SHARPEN) {
  1846. isp_write_reg(dev, REG_ADDR(img_eff_mat_3),
  1847. (mat[0] << 4) | (mat[1] << 8) | (mat[2] << 12));
  1848. isp_write_reg(dev, REG_ADDR(img_eff_mat_4),
  1849. mat[3] | (mat[4] << 4) | (mat[5] << 8) | (mat[6]
  1850. << 12));
  1851. isp_write_reg(dev, REG_ADDR(img_eff_mat_5),
  1852. mat[7] | (mat[8] << 4));
  1853. REG_SET_SLICE(sharpen, MRV_IMGEFF_SHARP_FACTOR,
  1854. ie->sharpen_factor);
  1855. REG_SET_SLICE(sharpen, MRV_IMGEFF_CORING_THR,
  1856. ie->sharpen_thresh);
  1857. isp_write_reg(dev, REG_ADDR(img_eff_sharpen), sharpen);
  1858. }
  1859. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_CFG_UPD,
  1860. MRV_IMGEFF_CFG_UPD_UPDATE);
  1861. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_BYPASS_MODE,
  1862. MRV_IMGEFF_BYPASS_MODE_PROCESS);
  1863. isp_write_reg(dev, REG_ADDR(img_eff_ctrl), img_eff_ctrl);
  1864. isp_info("exit %s\n", __func__);
  1865. return 0;
  1866. }
  1867. int isp_s_vsm(struct isp_ic_dev *dev)
  1868. {
  1869. struct isp_vsm_context *vsm = &dev->vsm;
  1870. u32 isp_vsm_mode = isp_read_reg(dev, REG_ADDR(isp_vsm_mode));
  1871. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1872. isp_info("enter %s\n", __func__);
  1873. if (!vsm->enable) {
  1874. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_EN, 0);
  1875. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_IRQ_ENABLE, 0);
  1876. isp_write_reg(dev, REG_ADDR(isp_vsm_mode), isp_vsm_mode);
  1877. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1878. isp_imsc & ~MRV_ISP_IMSC_VSM_END_MASK);
  1879. return 0;
  1880. }
  1881. isp_write_reg(dev, REG_ADDR(isp_vsm_h_offs), vsm->window.x);
  1882. isp_write_reg(dev, REG_ADDR(isp_vsm_v_offs), vsm->window.y);
  1883. isp_write_reg(dev, REG_ADDR(isp_vsm_h_size),
  1884. vsm->window.width & 0xFFFFE);
  1885. isp_write_reg(dev, REG_ADDR(isp_vsm_v_size),
  1886. vsm->window.height & 0xFFFFE);
  1887. isp_write_reg(dev, REG_ADDR(isp_vsm_h_segments), vsm->h_seg);
  1888. isp_write_reg(dev, REG_ADDR(isp_vsm_v_segments), vsm->v_seg);
  1889. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_EN, 1);
  1890. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_IRQ_ENABLE, 1);
  1891. isp_write_reg(dev, REG_ADDR(isp_vsm_mode), isp_vsm_mode);
  1892. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1893. isp_imsc | MRV_ISP_IMSC_VSM_END_MASK);
  1894. isp_info("exit %s\n", __func__);
  1895. return 0;
  1896. }
  1897. int isp_g_vsm(struct isp_ic_dev *dev, struct isp_vsm_result *vsm)
  1898. {
  1899. isp_info("enter %s\n", __func__);
  1900. vsm->x = isp_read_reg(dev, REG_ADDR(isp_vsm_delta_h));
  1901. vsm->y = isp_read_reg(dev, REG_ADDR(isp_vsm_delta_v));
  1902. isp_info("exit %s\n", __func__);
  1903. return 0;
  1904. }
  1905. #if 0
  1906. u32 get_afm_shift(u32 count, u32 thresh)
  1907. {
  1908. u32 grad = count;
  1909. u32 shift = 0;
  1910. while (grad > (thresh)) {
  1911. ++shift;
  1912. grad >>= 1;
  1913. }
  1914. return shift;
  1915. }
  1916. #endif
  1917. int isp_s_afm(struct isp_ic_dev *dev)
  1918. {
  1919. struct isp_afm_context *afm = &dev->afm;
  1920. u32 mask =
  1921. (MRV_ISP_IMSC_AFM_FIN_MASK | MRV_ISP_IMSC_AFM_LUM_OF_MASK |
  1922. MRV_ISP_IMSC_AFM_SUM_OF_MASK);
  1923. u32 shift = 0;
  1924. int i;
  1925. u32 isp_afm_ctrl = isp_read_reg(dev, REG_ADDR(isp_afm_ctrl));
  1926. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1927. if (!afm->enable) {
  1928. REG_SET_SLICE(isp_afm_ctrl, MRV_AFM_AFM_EN, 0);
  1929. isp_imsc &= ~mask;
  1930. isp_write_reg(dev, REG_ADDR(isp_afm_ctrl), isp_afm_ctrl);
  1931. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  1932. return 0;
  1933. }
  1934. for (i = 0; i < 3; i++) {
  1935. isp_write_reg(dev, REG_ADDR(isp_afm_lt_a) + i * 8,
  1936. (afm->window[i].x << 16) | afm->window[i].y);
  1937. isp_write_reg(dev, REG_ADDR(isp_afm_rb_a) + i * 8,
  1938. ((afm->window[i].x + afm->window[i].width -
  1939. 1) << 16) | ((afm->window[i].y +
  1940. afm->window[i].height - 1)));
  1941. }
  1942. REG_SET_SLICE(shift, MRV_AFM_LUM_VAR_SHIFT, afm->lum_shift);
  1943. REG_SET_SLICE(shift, MRV_AFM_AFM_VAR_SHIFT, afm->afm_shift);
  1944. isp_write_reg(dev, REG_ADDR(isp_afm_var_shift), shift);
  1945. isp_write_reg(dev, REG_ADDR(isp_afm_thres), afm->thresh);
  1946. REG_SET_SLICE(isp_afm_ctrl, MRV_AFM_AFM_EN, 1);
  1947. isp_imsc |= mask;
  1948. isp_write_reg(dev, REG_ADDR(isp_afm_ctrl), isp_afm_ctrl);
  1949. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  1950. return 0;
  1951. }
  1952. int isp_g_afm(struct isp_ic_dev *dev, struct isp_afm_result *afm)
  1953. {
  1954. afm->sum_a = isp_read_reg(dev, REG_ADDR(isp_afm_sum_a));
  1955. afm->sum_b = isp_read_reg(dev, REG_ADDR(isp_afm_sum_b));
  1956. afm->sum_c = isp_read_reg(dev, REG_ADDR(isp_afm_sum_c));
  1957. afm->lum_a = isp_read_reg(dev, REG_ADDR(isp_afm_lum_a));
  1958. afm->lum_b = isp_read_reg(dev, REG_ADDR(isp_afm_lum_b));
  1959. afm->lum_c = isp_read_reg(dev, REG_ADDR(isp_afm_lum_c));
  1960. return 0;
  1961. }
  1962. int isp_s_exp2_inputsel(struct isp_ic_dev *dev)
  1963. {
  1964. #ifndef ISP_AEV2
  1965. isp_err("unsupported function: %s\n", __func__);
  1966. return -EINVAL;
  1967. #else
  1968. struct isp_exp2_context *exp2 = &dev->exp2;
  1969. u32 isp_expv2_ctrl = isp_read_reg(dev, REG_ADDR(isp_expv2_ctrl));
  1970. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_INPUT_SELECT, exp2->input_select);
  1971. isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl);
  1972. return 0;
  1973. #endif
  1974. }
  1975. int isp_s_exp2_sizeratio(struct isp_ic_dev *dev, u32 h_size)
  1976. {
  1977. #ifndef ISP_AEV2
  1978. isp_err("unsupported function: %s\n", __func__);
  1979. return -EINVAL;
  1980. #else
  1981. u32 size_inv;
  1982. size_inv = isp_read_reg(dev, REG_ADDR(isp_expv2_size_invert));
  1983. REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_H, h_size);
  1984. isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert), size_inv);
  1985. return 0;
  1986. #endif
  1987. }
  1988. int isp_s_exp2(struct isp_ic_dev *dev)
  1989. {
  1990. #ifndef ISP_AEV2
  1991. //isp_err("unsupported function: %s\n", __func__);
  1992. return -EINVAL;
  1993. #else
  1994. u32 miv2_ctrl, miv2_mp_fmt, miv2_mp_bus_id, miv2_mp_ctrl, miv2_ctrl_shd;
  1995. struct isp_exp2_context *exp2 = &dev->exp2;
  1996. u32 isp_expv2_ctrl = isp_read_reg(dev, REG_ADDR(isp_expv2_ctrl));
  1997. u32 grid_w, grid_h;
  1998. u32 size, offset, size_inv, weight;
  1999. isp_info("enter %s\n", __func__);
  2000. grid_w = ((exp2->window.width - 1) >> 6) << 1;
  2001. grid_h = ((exp2->window.height - 1) >> 6) << 1;
  2002. if (!exp2->enable) {
  2003. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_ENABLE, 0);
  2004. isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl);
  2005. return 0;
  2006. }
  2007. size = 0;
  2008. REG_SET_SLICE(size, MRV_AE_ISP_EXPV2_SIZE_H, grid_w);
  2009. REG_SET_SLICE(size, MRV_AE_ISP_EXPV2_SIZE_V, grid_h);
  2010. offset = 0;
  2011. REG_SET_SLICE(offset, MRV_AE_ISP_EXPV2_OFFSET_H, exp2->window.x);
  2012. REG_SET_SLICE(offset, MRV_AE_ISP_EXPV2_OFFSET_V, exp2->window.y);
  2013. size_inv = 0;
  2014. REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_H, (65536 + grid_w/2) / grid_w);
  2015. REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_V, (65536 + grid_h/2) / grid_h);
  2016. weight = 0;
  2017. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_R, exp2->r)
  2018. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR, exp2->gr)
  2019. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB, exp2->gb)
  2020. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_B, exp2->b)
  2021. isp_write_reg(dev, REG_ADDR(isp_expv2_offset), offset);
  2022. isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert), size_inv);
  2023. isp_write_reg(dev, REG_ADDR(isp_expv2_size), size);
  2024. #ifdef ISP_AE_SHADOW
  2025. isp_write_reg(dev, REG_ADDR(isp_expv2_offset_shd), offset);
  2026. isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert_shd), size_inv);
  2027. isp_write_reg(dev, REG_ADDR(isp_expv2_size_shd), size);
  2028. #endif
  2029. isp_write_reg(dev, REG_ADDR(isp_expv2_pixel_weight), weight);
  2030. miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl));
  2031. REG_SET_SLICE(miv2_ctrl, MP_JDP_PATH_ENABLE, 1);
  2032. isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl);
  2033. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_base_ad_init), dev->exp2.pa);
  2034. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_size_init), AEV2_DMA_SIZE);
  2035. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_offs_cnt_init), 0);
  2036. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_llength), AEV2_DMA_SIZE);
  2037. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_width), 1024);
  2038. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_height), 1);
  2039. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_size), AEV2_DMA_SIZE);
  2040. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_ENABLE, 1);
  2041. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_INPUT_SELECT, exp2->input_select);
  2042. isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl);
  2043. miv2_ctrl_shd = isp_read_reg(dev, REG_ADDR(miv2_ctrl_shd));
  2044. if (!(miv2_ctrl_shd && MP_YCBCR_PATH_ENABLE_MASK) && !(miv2_ctrl_shd && MP_RAW_PATH_ENABLE_MASK)) {
  2045. miv2_mp_fmt = isp_read_reg(dev, REG_ADDR(miv2_mp_fmt));
  2046. #ifdef ISP_AEV2_V2
  2047. REG_SET_SLICE(miv2_mp_fmt, MP_WR_JDP_DP_BIT, 1);
  2048. #endif
  2049. REG_SET_SLICE(miv2_mp_fmt, MP_WR_JDP_FMT, 0);
  2050. isp_write_reg(dev, REG_ADDR(miv2_mp_fmt), miv2_mp_fmt);
  2051. miv2_mp_bus_id = isp_read_reg(dev, REG_ADDR(miv2_mp_bus_id));
  2052. REG_SET_SLICE(miv2_mp_bus_id, MP_BUS_SW_EN, 1);
  2053. REG_SET_SLICE(miv2_mp_bus_id, MP_WR_ID_EN, 1);
  2054. isp_write_reg(dev, REG_ADDR(miv2_mp_bus_id), miv2_mp_bus_id);
  2055. miv2_mp_ctrl = isp_read_reg(dev, REG_ADDR(miv2_mp_ctrl));
  2056. REG_SET_SLICE(miv2_mp_ctrl, MP_AUTO_UPDATE, 1);
  2057. REG_SET_SLICE(miv2_mp_ctrl, MP_INIT_BASE_EN, 1);
  2058. REG_SET_SLICE(miv2_mp_ctrl, MP_INIT_OFFSET_EN, 1);
  2059. isp_write_reg(dev, REG_ADDR(miv2_mp_ctrl), miv2_mp_ctrl);
  2060. }
  2061. isp_info("exit %s\n", __func__);
  2062. return 0;
  2063. #endif
  2064. }
  2065. int isp_s_2dnr(struct isp_ic_dev *dev)
  2066. {
  2067. #ifndef ISP_2DNR
  2068. //isp_err("unsupported function: %s\n", __func__);
  2069. return -EINVAL;
  2070. #else
  2071. struct isp_2dnr_context *dnr2 = &dev->dnr2;
  2072. u32 isp_denoise2d_control =
  2073. isp_read_reg(dev, REG_ADDR(isp_denoise2d_control));
  2074. u32 value, addr, strength;
  2075. u32 isp_ctrl;
  2076. int i;
  2077. /*isp_info("enter %s\n", __func__);*/
  2078. if (!dnr2->enable) {
  2079. #ifndef ISP_2DNR_V4
  2080. REG_SET_SLICE(isp_denoise2d_control, ISP_2DNR_ENABLE, 0);
  2081. isp_write_reg(dev, REG_ADDR(isp_denoise2d_control),
  2082. isp_denoise2d_control);
  2083. #else
  2084. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  2085. REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 0);
  2086. if((value & DENOISE3D_V20_TNR_ENABLE_MASK) == 0)
  2087. REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 0);
  2088. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl),
  2089. value);
  2090. #endif
  2091. return 0;
  2092. }
  2093. strength = isp_read_reg(dev, REG_ADDR(isp_denoise2d_strength));
  2094. REG_SET_SLICE(strength, ISP_2DNR_PRGAMMA_STRENGTH, dnr2->pre_gamma);
  2095. REG_SET_SLICE(strength, ISP_2DNR_STRENGTH, dnr2->strength);
  2096. isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength), strength);
  2097. addr = REG_ADDR(isp_denoise2d_sigma_y[0]);
  2098. for (i = 0; i < 60; i += 5) {
  2099. value = 0;
  2100. REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i]);
  2101. REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 1]);
  2102. REG_SET_SLICE(value, ISP_2DNR_SIGMAY2A,
  2103. dnr2->sigma[i + 2] >> 6);
  2104. isp_write_reg(dev, addr, value);
  2105. value = 0;
  2106. addr += 4;
  2107. REG_SET_SLICE(value, ISP_2DNR_SIGMAY2B,
  2108. dnr2->sigma[i + 2] & 0x3f);
  2109. REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i + 3]);
  2110. REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 4]);
  2111. isp_write_reg(dev, addr, value);
  2112. addr += 4;
  2113. }
  2114. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  2115. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  2116. REG_SET_SLICE(isp_denoise2d_control, ISP_2DNR_ENABLE, 1);
  2117. #if defined(ISP_2DNR_V2) || defined(ISP_2DNR_V4)
  2118. isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr), dnr2->sigma_sqr);
  2119. isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr_shd),
  2120. dnr2->sigma_sqr);
  2121. isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor),
  2122. dnr2->weight);
  2123. isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor_shd),
  2124. dnr2->weight);
  2125. /* refer to HW spec for HBLANK */
  2126. //isp_write_reg(dev, REG_ADDR(isp_denoise2d_dummy_hblank), 0);
  2127. isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength_shd), strength);
  2128. isp_write_reg(dev, REG_ADDR(isp_denoise2d_control_shd),
  2129. isp_denoise2d_control);
  2130. #endif
  2131. #ifndef ISP_2DNR_V4
  2132. isp_write_reg(dev, REG_ADDR(isp_denoise2d_control),
  2133. isp_denoise2d_control);
  2134. #else
  2135. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_blending));
  2136. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_OFFSET, dnr2->str_off);
  2137. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_MAX, dnr2->str_max);
  2138. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_SLOPE, dnr2->str_slope);
  2139. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_blending), value);
  2140. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  2141. REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 1);
  2142. REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 1);
  2143. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl),
  2144. value);
  2145. #endif
  2146. /*isp_info("exit %s\n", __func__);*/
  2147. return 0;
  2148. #endif
  2149. }
  2150. int isp_s_simp(struct isp_ic_dev *dev)
  2151. {
  2152. struct isp_simp_context *simp = &dev->simp;
  2153. u32 vi_ircl = isp_read_reg(dev, REG_ADDR(vi_ircl));
  2154. u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl));
  2155. u32 super_imp_ctrl = isp_read_reg(dev, REG_ADDR(super_imp_ctrl));
  2156. isp_info("enter %s\n", __func__);
  2157. REG_SET_SLICE(vi_ircl, MRV_VI_SIMP_SOFT_RST, 1);
  2158. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2159. if (!simp->enable) {
  2160. REG_SET_SLICE(vi_iccl, MRV_VI_SIMP_CLK_ENABLE, 0);
  2161. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  2162. return 0;
  2163. }
  2164. REG_SET_SLICE(vi_ircl, MRV_VI_SIMP_SOFT_RST, 0);
  2165. isp_write_reg(dev, REG_ADDR(super_imp_offset_x), simp->x);
  2166. isp_write_reg(dev, REG_ADDR(super_imp_offset_y), simp->y);
  2167. isp_write_reg(dev, REG_ADDR(super_imp_color_y), simp->r);
  2168. isp_write_reg(dev, REG_ADDR(super_imp_color_cb), simp->g);
  2169. isp_write_reg(dev, REG_ADDR(super_imp_color_cr), simp->b);
  2170. REG_SET_SLICE(super_imp_ctrl, MRV_SI_TRANSPARENCY_MODE,
  2171. simp->transparency_mode);
  2172. REG_SET_SLICE(super_imp_ctrl, MRV_SI_REF_IMAGE, simp->ref_image);
  2173. isp_write_reg(dev, REG_ADDR(super_imp_ctrl), super_imp_ctrl);
  2174. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2175. REG_SET_SLICE(vi_iccl, MRV_VI_SIMP_CLK_ENABLE, 1);
  2176. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  2177. isp_info("exit %s\n", __func__);
  2178. return 0;
  2179. }
  2180. int isp_s_cproc(struct isp_ic_dev *dev)
  2181. {
  2182. struct isp_cproc_context *cproc = &dev->cproc;
  2183. u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl));
  2184. u32 cproc_ctrl = isp_read_reg(dev, REG_ADDR(cproc_ctrl));
  2185. //REG_SET_SLICE(vi_ircl, MRV_VI_CP_SOFT_RST, 1);
  2186. //isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2187. //if there is no shd register. should update cporc register in isp frame end irq.
  2188. #ifndef ISP_CPROC_SHD
  2189. if(dev->cproc.changed || !is_isp_enable(dev))
  2190. {
  2191. #endif
  2192. /*isp_info("enter %s %d\n", __func__, cproc->enable);*/
  2193. if (!cproc->enable) {
  2194. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_ENABLE, 0);
  2195. /* REG_SET_SLICE(vi_iccl, MRV_VI_CP_CLK_ENABLE, 0); */
  2196. /* isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl); */
  2197. isp_write_reg(dev, REG_ADDR(cproc_ctrl), cproc_ctrl);
  2198. return 0;
  2199. }
  2200. //REG_SET_SLICE(vi_ircl, MRV_VI_CP_SOFT_RST, 0);
  2201. //isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2202. isp_write_reg(dev, REG_ADDR(cproc_contrast), cproc->contrast);
  2203. isp_write_reg(dev, REG_ADDR(cproc_brightness), cproc->brightness);
  2204. isp_write_reg(dev, REG_ADDR(cproc_saturation), cproc->saturation);
  2205. isp_write_reg(dev, REG_ADDR(cproc_hue), cproc->hue);
  2206. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_ENABLE, 1);
  2207. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_C_OUT_RANGE,
  2208. cproc->c_out_full);
  2209. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_Y_OUT_RANGE,
  2210. cproc->y_out_full);
  2211. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_Y_IN_RANGE, cproc->y_in_full);
  2212. REG_SET_SLICE(vi_iccl, MRV_VI_CP_CLK_ENABLE, 1);
  2213. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  2214. isp_write_reg(dev, REG_ADDR(cproc_ctrl), cproc_ctrl);
  2215. #ifndef ISP_CPROC_SHD
  2216. dev->cproc.changed = false;
  2217. } else {
  2218. dev->cproc.changed = true;
  2219. }
  2220. #endif
  2221. /*isp_info("exit %s\n", __func__);*/
  2222. return 0;
  2223. }
  2224. int isp_s_elawb(struct isp_ic_dev *dev)
  2225. {
  2226. struct isp_elawb_context *elawb = &dev->elawb;
  2227. u32 awb_meas_mode = isp_read_reg(dev, REG_ADDR(awb_meas_mode));
  2228. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  2229. u32 id = elawb->id;
  2230. u32 data;
  2231. if (!elawb->enable) {
  2232. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_IRQ_ENABLE, 0);
  2233. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_EN, 0);
  2234. isp_write_reg(dev, REG_ADDR(awb_meas_mode), awb_meas_mode);
  2235. isp_write_reg(dev, REG_ADDR(isp_imsc),
  2236. isp_imsc & ~MRV_ISP_IMSC_AWB_DONE_MASK);
  2237. return 0;
  2238. }
  2239. isp_write_reg(dev, REG_ADDR(awb_meas_h_offs), elawb->window.x);
  2240. isp_write_reg(dev, REG_ADDR(awb_meas_v_offs), elawb->window.y);
  2241. isp_write_reg(dev, REG_ADDR(awb_meas_h_size), elawb->window.width);
  2242. isp_write_reg(dev, REG_ADDR(awb_meas_v_size), elawb->window.height);
  2243. if (id > 0 && id < 9) {
  2244. isp_write_reg(dev, REG_ADDR(awb_meas_center[id - 1].x),
  2245. elawb->info[id - 1].x);
  2246. isp_write_reg(dev, REG_ADDR(awb_meas_center[id - 1].y),
  2247. elawb->info[id - 1].y);
  2248. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a1),
  2249. elawb->info[id - 1].a1);
  2250. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a2),
  2251. elawb->info[id - 1].a2);
  2252. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a3),
  2253. elawb->info[id - 1].a3);
  2254. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a4),
  2255. elawb->info[id - 1].a4);
  2256. isp_write_reg(dev, REG_ADDR(awb_meas_rmax[id - 1]),
  2257. elawb->info[id - 1].r_max_sqr);
  2258. }
  2259. data = 0;
  2260. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_R, elawb->r);
  2261. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_B, elawb->b);
  2262. isp_write_reg(dev, REG_ADDR(isp_awb_gain_rb), data);
  2263. data = 0;
  2264. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_GR, elawb->gr);
  2265. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_GB, elawb->gb);
  2266. isp_write_reg(dev, REG_ADDR(isp_awb_gain_g), data);
  2267. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_IRQ_ENABLE, 1);
  2268. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_EN, 1);
  2269. isp_write_reg(dev, REG_ADDR(awb_meas_mode), awb_meas_mode);
  2270. isp_write_reg(dev, REG_ADDR(isp_imsc),
  2271. isp_imsc | MRV_ISP_IMSC_AWB_DONE_MASK);
  2272. return 0;
  2273. }
  2274. int isp_ioc_qcap(struct isp_ic_dev *dev, void __user *args)
  2275. {
  2276. /* use public VIDIOC_QUERYCAP to query the type of v4l-subdevs. */
  2277. #ifdef __KERNEL__
  2278. #ifndef USE_FPGA
  2279. struct v4l2_capability *cap = (struct v4l2_capability *)args;
  2280. strcpy((char *)cap->driver, "viv_isp_subdev");
  2281. cap->bus_info[0] = (__u8)dev->id;//isp channel id
  2282. #else
  2283. struct v4l2_capability cap;
  2284. strcpy((char *)cap.driver, "viv_isp_subdev");
  2285. cap.bus_info[0] = (__u8)dev->id;//isp channel id
  2286. isp_info("enter %s viv_isp_subdev\n", __func__);
  2287. viv_check_retval(copy_to_user
  2288. ((struct v4l2_capability *)args, &cap, sizeof(cap)));
  2289. #endif
  2290. #endif
  2291. return 0;
  2292. }
  2293. int isp_ioc_g_status(struct isp_ic_dev *dev, void __user *args)
  2294. {
  2295. u32 val = 0;
  2296. /* val = isp_read_reg(REG_ADDR(isp_feature_version)); */
  2297. viv_check_retval(copy_to_user(args, &val, sizeof(val)));
  2298. return 0;
  2299. }
  2300. static u32 getScaleFactor(u32 src, u32 dst)
  2301. {
  2302. if (dst > src) {
  2303. return ((65536 * (src - 1)) / (dst - 1));
  2304. } else if (dst < src) {
  2305. return ((65536 * (dst - 1)) / (src - 1)) + 1;
  2306. }
  2307. return 65536;
  2308. }
  2309. int isp_set_scaling(int id, struct isp_ic_dev *dev, bool stabilization, bool crop)
  2310. {
  2311. u32 addr, ctrl;
  2312. u32 iw, ih, ow, oh;
  2313. u32 inputWidth, inputHeight, outputWidth, outputHeight;
  2314. u32 scale_hy, scale_hcb, scale_hcr, scale_vy, scale_vc;
  2315. struct isp_mi_data_path_context *path = &dev->mi.path[id];
  2316. if (crop) { //enabled crop.Do not need to scaler.
  2317. isp_info("%s:The crop enabled ,So does not need to do scaler.\n", __func__);
  2318. return 0;
  2319. }
  2320. if (id == IC_MI_PATH_MAIN) { /* mp */
  2321. addr = REG_ADDR(mrsz_ctrl);
  2322. } else if (id == IC_MI_PATH_SELF) { /* sp */
  2323. addr = REG_ADDR(srsz_ctrl);
  2324. } else if (id == IC_MI_PATH_SELF2) { /* sp2 */
  2325. addr = REG_ADDR(srsz2_ctrl);
  2326. } else {
  2327. return -EFAULT;
  2328. }
  2329. inputWidth = path->in_width;
  2330. inputHeight = path->in_height;
  2331. outputWidth = path->out_width;
  2332. outputHeight = path->out_height;
  2333. if (stabilization) { /* enabled image stabilization. */
  2334. inputWidth = isp_read_reg(dev, REG_ADDR(isp_is_h_size));
  2335. inputHeight = isp_read_reg(dev, REG_ADDR(isp_is_v_size));
  2336. }
  2337. ctrl = isp_read_reg(dev, addr);
  2338. iw = inputWidth / 2;
  2339. ih = inputHeight;
  2340. ow = outputWidth / 2;
  2341. oh = outputHeight;
  2342. switch (path->in_mode) {
  2343. case IC_MI_DATAMODE_YUV422:
  2344. oh = outputHeight;
  2345. break;
  2346. case IC_MI_DATAMODE_YUV420:
  2347. oh = outputHeight / 2; /* scale cbcr */
  2348. break;
  2349. case IC_MI_DATAMODE_YUV444:
  2350. oh = outputHeight;
  2351. break;
  2352. case IC_MI_DATAMODE_RGB888:
  2353. oh = outputHeight;
  2354. break;
  2355. default:
  2356. return -EFAULT;
  2357. }
  2358. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_ENABLE,
  2359. inputWidth != outputWidth);
  2360. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_ENABLE,
  2361. inputHeight != outputHeight);
  2362. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_UP, inputWidth < outputWidth);
  2363. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_UP, inputHeight < outputHeight);
  2364. scale_hy = getScaleFactor(inputWidth, outputWidth);
  2365. scale_vy = getScaleFactor(inputHeight, outputHeight);
  2366. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_ENABLE, iw != ow);
  2367. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_ENABLE, ih != oh);
  2368. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_UP, iw < ow);
  2369. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_UP, ih < oh);
  2370. scale_hcr = getScaleFactor(iw, ow);
  2371. scale_hcb = getScaleFactor(iw, ow);
  2372. scale_vc = getScaleFactor(ih, oh);
  2373. /*Need to update immediately*/
  2374. REG_SET_SLICE(ctrl, MRV_MRSZ_CFG_UPD, 1);
  2375. if (id == IC_MI_PATH_MAIN) {
  2376. isp_write_reg(dev, REG_ADDR(mrsz_scale_vc), scale_vc);
  2377. isp_write_reg(dev, REG_ADDR(mrsz_scale_vy), scale_vy);
  2378. isp_write_reg(dev, REG_ADDR(mrsz_scale_hcr), scale_hcr);
  2379. isp_write_reg(dev, REG_ADDR(mrsz_scale_hcb), scale_hcb);
  2380. isp_write_reg(dev, REG_ADDR(mrsz_scale_hy), scale_hy);
  2381. isp_write_reg(dev, REG_ADDR(mrsz_ctrl), ctrl);
  2382. } else if (id == IC_MI_PATH_SELF) {
  2383. isp_write_reg(dev, REG_ADDR(srsz_scale_vc), scale_vc);
  2384. isp_write_reg(dev, REG_ADDR(srsz_scale_vy), scale_vy);
  2385. isp_write_reg(dev, REG_ADDR(srsz_scale_hcr), scale_hcr);
  2386. isp_write_reg(dev, REG_ADDR(srsz_scale_hcb), scale_hcb);
  2387. isp_write_reg(dev, REG_ADDR(srsz_scale_hy), scale_hy);
  2388. isp_write_reg(dev, REG_ADDR(srsz_ctrl), ctrl);
  2389. } else if (id == IC_MI_PATH_SELF2) {
  2390. isp_write_reg(dev, REG_ADDR(srsz2_scale_vc), scale_vc);
  2391. isp_write_reg(dev, REG_ADDR(srsz2_scale_vy), scale_vy);
  2392. isp_write_reg(dev, REG_ADDR(srsz2_scale_hcr), scale_hcr);
  2393. isp_write_reg(dev, REG_ADDR(srsz2_scale_hcb), scale_hcb);
  2394. isp_write_reg(dev, REG_ADDR(srsz2_scale_hy), scale_hy);
  2395. isp_write_reg(dev, REG_ADDR(srsz2_ctrl), ctrl);
  2396. }
  2397. return 0;
  2398. }
  2399. typedef struct isp_crop_reg_s {
  2400. u32 crop_ctrl_addr;
  2401. u32 crop_x_dir_addr;
  2402. u32 crop_y_dir_addr;
  2403. } isp_crop_reg_t;
  2404. int isp_set_crop(struct isp_ic_dev *dev)
  2405. {
  2406. long ret = 0;
  2407. u32 crop_ctrl, crop_x_dir, crop_y_dir;
  2408. u8 i;
  2409. isp_crop_reg_t crop_reg[ISP_MI_PATH_SP2_BP + 1] = {
  2410. {
  2411. REG_ADDR(mrsz_ctrl),
  2412. REG_ADDR(mrsz_phase_crop_x),
  2413. REG_ADDR(mrsz_phase_crop_y)
  2414. },
  2415. {
  2416. REG_ADDR(srsz_ctrl),
  2417. REG_ADDR(srsz_phase_crop_x),
  2418. REG_ADDR(srsz_phase_crop_y)
  2419. },
  2420. {
  2421. REG_ADDR(srsz2_ctrl),
  2422. REG_ADDR(srsz2_phase_crop_x),
  2423. REG_ADDR(srsz2_phase_crop_y)
  2424. }
  2425. };
  2426. struct isp_crop_context *crop = dev->crop;
  2427. for ( i = 0; i <= ISP_MI_PATH_SP2_BP; i++) {
  2428. crop_ctrl = isp_read_reg(dev, crop_reg[i].crop_ctrl_addr);
  2429. crop_x_dir = isp_read_reg(dev, crop_reg[i].crop_x_dir_addr);
  2430. crop_y_dir = isp_read_reg(dev, crop_reg[i].crop_y_dir_addr);
  2431. if (!crop[i].enabled) {
  2432. #ifndef ISP8000NANO_BASE
  2433. REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CROP_ENABLE, 0);
  2434. #endif
  2435. isp_write_reg(dev, crop_reg[i].crop_ctrl_addr, crop_ctrl);
  2436. continue;
  2437. }
  2438. REG_SET_SLICE(crop_x_dir, MRV_MRSZ_PHASE_H_START, crop[i].window.x);
  2439. REG_SET_SLICE(crop_y_dir, MRV_MRSZ_PHASE_V_START, crop[i].window.y);
  2440. REG_SET_SLICE(crop_x_dir, MRV_MRSZ_PHASE_H_END, crop[i].window.width + crop[i].window.x - 1); //x_end = x + width -1
  2441. REG_SET_SLICE(crop_y_dir, MRV_MRSZ_PHASE_V_END, crop[i].window.height + crop[i].window.y - 1); //y_end = y + height -1
  2442. #ifndef ISP8000NANO_BASE
  2443. REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CROP_ENABLE, 1);
  2444. /*Need to update immediately*/
  2445. REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CFG_UPD, 1);
  2446. #endif
  2447. isp_write_reg(dev, crop_reg[i].crop_x_dir_addr, crop_x_dir);
  2448. isp_write_reg(dev, crop_reg[i].crop_y_dir_addr, crop_y_dir);
  2449. isp_write_reg(dev, crop_reg[i].crop_ctrl_addr, crop_ctrl);
  2450. }
  2451. return ret;
  2452. }
  2453. int isp_ioc_g_feature(struct isp_ic_dev *dev, void __user *args)
  2454. {
  2455. u32 val = 0;
  2456. #ifdef ISP_EE
  2457. val |= ISP_EE_SUPPORT;
  2458. #endif
  2459. #ifdef ISP_WDR3
  2460. val |= ISP_WDR3_SUPPORT;
  2461. #endif
  2462. #ifdef ISP_2DNR
  2463. val |= ISP_2DNR_SUPPORT;
  2464. #endif
  2465. #ifdef ISP_3DNR
  2466. val |= ISP_3DNR_SUPPORT;
  2467. #endif
  2468. #ifdef ISP_WDR_V3
  2469. val |= ISP_WDR3_SUPPORT;
  2470. #endif
  2471. #ifdef ISP_MIV2
  2472. val |= ISP_MIV2_SUPPORT;
  2473. #endif
  2474. #ifdef ISP_AEV2
  2475. val |= ISP_AEV2_SUPPORT;
  2476. #endif
  2477. #ifdef ISP_HDR_STITCH
  2478. val |= ISP_HDR_STITCH_SUPPORT;
  2479. #endif
  2480. viv_check_retval(copy_to_user(args, &val, sizeof(val)));
  2481. return 0;
  2482. }
  2483. int isp_ioc_g_feature_veresion(struct isp_ic_dev *dev, void __user *args)
  2484. {
  2485. u32 val = 0;
  2486. /* val = isp_read_reg(REG_ADDR(isp_feature_version)); */
  2487. viv_check_retval(copy_to_user(args, &val, sizeof(val)));
  2488. return 0;
  2489. }
  2490. static long isp_get_extmem(struct isp_ic_dev *dev, void __user *args)
  2491. {
  2492. #define UT_USED_SIZE 0x01000000
  2493. long ret = 0;
  2494. struct isp_extmem_info ext_mem;
  2495. dev->ut_addr = dma_alloc_coherent(dev->device, UT_USED_SIZE, &dev->ut_phy_addr, GFP_KERNEL);
  2496. if (dev->ut_addr != NULL) {
  2497. ext_mem.addr = dev->ut_phy_addr;
  2498. ext_mem.size = UT_USED_SIZE;
  2499. } else {
  2500. return -1;
  2501. }
  2502. ret = copy_to_user(args, &ext_mem, sizeof(struct isp_extmem_info));
  2503. return ret;
  2504. }
  2505. int vvcam_free_isp_irq(struct isp_ic_dev *dev);
  2506. int vvcam_request_isp_irq(struct isp_ic_dev *dev);
  2507. long isp_priv_ioctl(struct isp_ic_dev *dev, unsigned int cmd, void __user *args)
  2508. {
  2509. int ret = -1;
  2510. if (!dev) {
  2511. return ret;
  2512. }
  2513. /*isp_info("[%s:%d]cmd 0x%08x\n", __func__, __LINE__, cmd);*/
  2514. switch (cmd) {
  2515. case ISPIOC_RESET:
  2516. if((ret = isp_mi_stop(dev)) != 0 )
  2517. {
  2518. isp_err("[%s:%d]stop mi error before resetting!\n", __func__, __LINE__);
  2519. break;
  2520. }
  2521. if((ret = isp_stop_stream(dev)) != 0)
  2522. {
  2523. isp_err("[%s:%d]stop isp stream before resetting!\n", __func__, __LINE__);
  2524. break;
  2525. }
  2526. ret = isp_reset(dev);
  2527. break;
  2528. case ISPIOC_WRITE_REG:
  2529. ret = isp_ioc_write_reg(dev, args);
  2530. break;
  2531. case ISPIOC_READ_REG:
  2532. ret = isp_ioc_read_reg(dev, args);
  2533. break;
  2534. case ISPIOC_GET_MIS:
  2535. ret = isp_ioc_read_mis(dev, args);
  2536. break;
  2537. case ISPIOC_ENABLE_TPG:
  2538. ret = isp_enable_tpg(dev);
  2539. break;
  2540. case ISPIOC_DISABLE_TPG:
  2541. ret = isp_disable_tpg(dev);
  2542. break;
  2543. case ISPIOC_ENABLE_BLS:
  2544. ret = isp_enable_bls(dev);
  2545. break;
  2546. case ISPIOC_DISABLE_BLS:
  2547. ret = isp_disable_bls(dev);
  2548. break;
  2549. case ISPIOC_START_DMA_READ:
  2550. ret = isp_ioc_start_dma_read(dev, args);
  2551. break;
  2552. case ISPIOC_CFG_DMA:
  2553. ret = isp_ioc_cfg_dma(dev, args);
  2554. break;
  2555. case ISPIOC_MI_STOP:
  2556. ret = isp_mi_stop(dev);
  2557. break;
  2558. case ISPIOC_DISABLE_ISP_OFF:
  2559. ret = isp_ioc_disable_isp_off(dev, args);
  2560. break;
  2561. case ISPIOC_ISP_STOP:
  2562. ret = isp_stop_stream(dev);
  2563. if(!ret) {
  2564. dev->streaming = false;
  2565. }
  2566. break;
  2567. case ISPIOC_ENABLE:
  2568. ret = isp_enable(dev);
  2569. break;
  2570. case ISPIOC_DISABLE:
  2571. ret = isp_disable(dev);
  2572. break;
  2573. case ISPIOC_ISP_STATUS:{
  2574. bool enable = is_isp_enable(dev);
  2575. viv_check_retval(copy_to_user
  2576. (args, &enable, sizeof(bool)));
  2577. ret = 0;
  2578. break;
  2579. }
  2580. case ISPIOC_ENABLE_LSC:
  2581. ret = isp_enable_lsc(dev);
  2582. break;
  2583. case ISPIOC_DISABLE_LSC:
  2584. ret = isp_disable_lsc(dev);
  2585. break;
  2586. case ISPIOC_S_DIGITAL_GAIN:
  2587. viv_check_retval(copy_from_user
  2588. (&dev->dgain, args, sizeof(dev->dgain)));
  2589. ret = isp_s_digital_gain(dev);
  2590. break;
  2591. #ifdef ISP_DEMOSAIC2
  2592. case ISPIOC_S_DMSC_INTP:
  2593. viv_check_retval(copy_from_user
  2594. (&dev->demosaic.intp, args,
  2595. sizeof(dev->demosaic.intp)));
  2596. ret = isp_set_dmsc_intp(dev);
  2597. break;
  2598. case ISPIOC_S_DMSC_DMOI:
  2599. viv_check_retval(copy_from_user
  2600. (&dev->demosaic.demoire, args,
  2601. sizeof(dev->demosaic.demoire)));
  2602. ret = isp_set_dmsc_dmoi(dev);
  2603. break;
  2604. case ISPIOC_S_DMSC_SKIN:
  2605. viv_check_retval(copy_from_user
  2606. (&dev->demosaic.skin, args,
  2607. sizeof(dev->demosaic.skin)));
  2608. ret = isp_set_dmsc_skin(dev);
  2609. break;
  2610. case ISPIOC_S_DMSC_SHAP:
  2611. viv_check_retval(copy_from_user
  2612. (&dev->demosaic.sharpen, args,
  2613. sizeof(dev->demosaic.sharpen)));
  2614. ret = isp_set_dmsc_sharpen(dev);
  2615. break;
  2616. case ISPIOC_S_DMSC_SHAP_LINE:
  2617. viv_check_retval(copy_from_user
  2618. (&dev->demosaic.sharpenLine, args,
  2619. sizeof(dev->demosaic.sharpenLine)));
  2620. ret = isp_set_dmsc_sharpen_line(dev);
  2621. break;
  2622. case ISPIOC_S_DMSC_CAC:
  2623. viv_check_retval(copy_from_user
  2624. (&dev->cac, args, sizeof(dev->cac)));
  2625. ret = isp_set_dmsc_cac(dev);
  2626. break;
  2627. case ISPIOC_S_DMSC_DEPURPLE:
  2628. viv_check_retval(copy_from_user
  2629. (&dev->demosaic.depurple, args,
  2630. sizeof(dev->demosaic.depurple)));
  2631. ret = isp_set_dmsc_depurple(dev);
  2632. break;
  2633. case ISPIOC_S_DMSC_GFILTER:
  2634. viv_check_retval(copy_from_user
  2635. (&dev->demosaic.gFilter, args,
  2636. sizeof(dev->demosaic.gFilter)));
  2637. ret = isp_set_dmsc_gfilter(dev);
  2638. break;
  2639. case ISPIOC_S_DMSC:
  2640. viv_check_retval(copy_from_user
  2641. (&dev->demosaic, args, sizeof(dev->demosaic)));
  2642. ret = isp_s_dmsc(dev);
  2643. break;
  2644. #endif
  2645. case ISPIOC_ENABLE_AWB:
  2646. ret = isp_enable_awb(dev);
  2647. break;
  2648. case ISPIOC_DISABLE_AWB:
  2649. ret = isp_disable_awb(dev);
  2650. break;
  2651. case ISPIOC_ENABLE_WB:
  2652. ret = isp_enable_wb(dev, 1);
  2653. break;
  2654. case ISPIOC_DISABLE_WB:
  2655. ret = isp_enable_wb(dev, 0);
  2656. break;
  2657. case ISPIOC_ENABLE_GAMMA_OUT:
  2658. ret = isp_enable_gamma_out(dev, 1);
  2659. break;
  2660. case ISPIOC_DISABLE_GAMMA_OUT:
  2661. ret = isp_enable_gamma_out(dev, 0);
  2662. break;
  2663. #if defined(ISP_3DNR) || defined(ISP_3DNR_V2_V1)
  2664. case ISPIOC_R_3DNR:
  2665. viv_check_retval(copy_from_user
  2666. (&dev->dnr3, args, sizeof(dev->dnr3)));
  2667. ret = isp_r_3dnr(dev);
  2668. break;
  2669. #endif
  2670. case ISPIOC_S_IS:
  2671. viv_check_retval(copy_from_user
  2672. (&dev->is, args, sizeof(dev->is)));
  2673. ret = isp_s_is(dev);
  2674. break;
  2675. case ISPIOC_S_RAW_IS:
  2676. viv_check_retval(copy_from_user
  2677. (&dev->rawis, args, sizeof(dev->rawis)));
  2678. ret = isp_s_raw_is(dev);
  2679. break;
  2680. case ISPIOC_S_CC:
  2681. viv_check_retval(copy_from_user
  2682. (&dev->cc, args, sizeof(dev->cc)));
  2683. ret = isp_s_cc(dev);
  2684. break;
  2685. case ISPIOC_S_EE:
  2686. viv_check_retval(copy_from_user
  2687. (&dev->ee, args, sizeof(dev->ee)));
  2688. ret = isp_s_ee(dev);
  2689. break;
  2690. case ISPIOC_S_IE:
  2691. viv_check_retval(copy_from_user
  2692. (&dev->ie, args, sizeof(dev->ie)));
  2693. ret = isp_s_ie(dev);
  2694. break;
  2695. case ISPIOC_S_TPG:
  2696. viv_check_retval(copy_from_user
  2697. (&dev->tpg, args, sizeof(dev->tpg)));
  2698. ret = isp_s_tpg(dev);
  2699. break;
  2700. case ISPIOC_S_BLS:
  2701. viv_check_retval(copy_from_user
  2702. (&dev->bls, args, sizeof(dev->bls)));
  2703. ret = isp_s_bls(dev);
  2704. break;
  2705. case ISPIOC_BYPASS_MCM:
  2706. viv_check_retval(copy_from_user
  2707. (&dev->mcm, args, sizeof(dev->mcm)));
  2708. ret = isp_bypass_mcm(dev);
  2709. break;
  2710. case ISPIOC_S_MCM_WR:
  2711. viv_check_retval(copy_from_user
  2712. (&dev->mcm, args, sizeof(dev->mcm)));
  2713. ret = isp_s_mcm_wr(dev);
  2714. break;
  2715. case ISPIOC_S_MUX:
  2716. viv_check_retval(copy_from_user
  2717. (&dev->mux, args, sizeof(dev->mux)));
  2718. ret = isp_s_mux(dev);
  2719. break;
  2720. case ISPIOC_S_AWB:
  2721. viv_check_retval(copy_from_user
  2722. (&dev->awb, args, sizeof(dev->awb)));
  2723. ret = isp_s_awb(dev);
  2724. break;
  2725. case ISPIOC_S_LSC_TBL:
  2726. viv_check_retval(copy_from_user
  2727. (&dev->lsc, args, sizeof(dev->lsc)));
  2728. ret = isp_s_lsc_tbl(dev);
  2729. break;
  2730. case ISPIOC_S_LSC_SEC:
  2731. viv_check_retval(copy_from_user
  2732. (&dev->lsc, args, sizeof(dev->lsc)));
  2733. ret = isp_s_lsc_sec(dev);
  2734. break;
  2735. case ISPIOC_S_DPF:
  2736. viv_check_retval(copy_from_user
  2737. (&dev->dpf, args, sizeof(dev->dpf)));
  2738. ret = isp_s_dpf(dev);
  2739. break;
  2740. case ISPIOC_S_EXP:
  2741. viv_check_retval(copy_from_user
  2742. (&dev->exp, args, sizeof(dev->exp)));
  2743. ret = isp_s_exp(dev);
  2744. break;
  2745. case ISPIOC_S_HDREXP:
  2746. viv_check_retval(copy_from_user
  2747. (&dev->hdrexp, args, sizeof(dev->hdrexp)));
  2748. ret = isp_s_hdrexp(dev);
  2749. break;
  2750. case ISPIOC_S_CNR:
  2751. viv_check_retval(copy_from_user
  2752. (&dev->cnr, args, sizeof(dev->cnr)));
  2753. ret = isp_s_cnr(dev);
  2754. break;
  2755. case ISPIOC_S_FLT:
  2756. {
  2757. viv_check_retval(copy_from_user
  2758. (&dev->flt, args, sizeof(dev->flt)));
  2759. ret = isp_s_flt(dev);
  2760. break;
  2761. }
  2762. case ISPIOC_S_CAC:
  2763. viv_check_retval(copy_from_user
  2764. (&dev->cac, args, sizeof(dev->cac)));
  2765. ret = isp_s_cac(dev);
  2766. break;
  2767. case ISPIOC_S_DEG:
  2768. viv_check_retval(copy_from_user
  2769. (&dev->deg, args, sizeof(dev->deg)));
  2770. ret = isp_s_deg(dev);
  2771. break;
  2772. case ISPIOC_S_VSM:
  2773. viv_check_retval(copy_from_user
  2774. (&dev->vsm, args, sizeof(dev->vsm)));
  2775. ret = isp_s_vsm(dev);
  2776. break;
  2777. case ISPIOC_S_AFM:
  2778. viv_check_retval(copy_from_user
  2779. (&dev->afm, args, sizeof(dev->afm)));
  2780. ret = isp_s_afm(dev);
  2781. break;
  2782. case ISPIOC_S_HDR:
  2783. viv_check_retval(copy_from_user
  2784. (&dev->hdr, args, sizeof(dev->hdr)));
  2785. ret = isp_s_hdr(dev);
  2786. break;
  2787. case ISPIOC_ENABLE_HDR:
  2788. viv_check_retval(copy_from_user
  2789. (&dev->hdr, args, sizeof(dev->hdr)));
  2790. ret = isp_enable_hdr(dev);
  2791. break;
  2792. case ISPIOC_DISABLE_HDR:
  2793. viv_check_retval(copy_from_user
  2794. (&dev->hdr, args, sizeof(dev->hdr)));
  2795. ret = isp_disable_hdr(dev);
  2796. break;
  2797. case ISPIOC_S_HIST:
  2798. viv_check_retval(copy_from_user
  2799. (&dev->hist, args, sizeof(dev->hist)));
  2800. ret = isp_s_hist(dev);
  2801. break;
  2802. case ISPIOC_S_HDRHIST:
  2803. viv_check_retval(copy_from_user
  2804. (&dev->hdrhist, args, sizeof(dev->hdrhist)));
  2805. ret = isp_s_hdrhist(dev);
  2806. break;
  2807. #ifdef ISP_HIST64
  2808. case ISPIOC_S_HIST64:
  2809. viv_check_retval(copy_from_user
  2810. (&dev->hist64, args, sizeof(dev->hist64)));
  2811. ret = isp_s_hist64(dev);
  2812. break;
  2813. case ISPIOC_U_HIST64:
  2814. viv_check_retval(copy_from_user
  2815. (&dev->hist64, args, sizeof(dev->hist64)));
  2816. ret = isp_update_hist64(dev);
  2817. break;
  2818. #endif
  2819. case ISPIOC_S_DPCC:
  2820. viv_check_retval(copy_from_user
  2821. (&dev->dpcc, args, sizeof(dev->dpcc)));
  2822. ret = isp_s_dpcc(dev);
  2823. break;
  2824. case ISPIOC_ENABLE_WDR3:
  2825. ret = isp_enable_wdr3(dev);
  2826. break;
  2827. case ISPIOC_DISABLE_WDR3:
  2828. ret = isp_disable_wdr3(dev);
  2829. break;
  2830. case ISPIOC_U_WDR3:
  2831. viv_check_retval(copy_from_user
  2832. (&dev->wdr3, args, sizeof(dev->wdr3)));
  2833. ret = isp_u_wdr3(dev);
  2834. break;
  2835. case ISPIOC_S_WDR3:
  2836. viv_check_retval(copy_from_user
  2837. (&dev->wdr3, args, sizeof(dev->wdr3)));
  2838. ret = isp_s_wdr3(dev);
  2839. break;
  2840. #ifdef ISP_WDR_V4
  2841. case ISPIOC_ENABLE_WDR4:
  2842. ret = isp_enable_wdr4(dev);
  2843. break;
  2844. case ISPIOC_DISABLE_WDR4:
  2845. ret = isp_disable_wdr4(dev);
  2846. break;
  2847. case ISPIOC_U_WDR4:
  2848. viv_check_retval(copy_from_user
  2849. (&dev->wdr4, args, sizeof(dev->wdr4)));
  2850. ret = isp_u_wdr4(dev);
  2851. break;
  2852. case ISPIOC_S_WDR4:
  2853. viv_check_retval(copy_from_user
  2854. (&dev->wdr4, args, sizeof(dev->wdr4)));
  2855. ret = isp_s_wdr4(dev);
  2856. break;
  2857. #endif
  2858. case ISPIOC_S_EXP2:
  2859. viv_check_retval(copy_from_user
  2860. (&dev->exp2, args, sizeof(dev->exp2)));
  2861. ret = isp_s_exp2(dev);
  2862. break;
  2863. case ISPIOC_S_EXP2_INPUTSEL:
  2864. viv_check_retval(copy_from_user
  2865. (&dev->exp2.input_select, args,
  2866. sizeof(dev->exp2.input_select)));
  2867. ret = isp_s_exp2_inputsel(dev);
  2868. break;
  2869. case ISPIOC_S_EXP2_SIZERATIO: {
  2870. u32 ratio;
  2871. viv_check_retval(copy_from_user(&ratio, args, sizeof(ratio)));
  2872. ret = isp_s_exp2_sizeratio(dev, ratio);
  2873. break;
  2874. }
  2875. case ISPIOC_S_2DNR:
  2876. viv_check_retval(copy_from_user
  2877. (&dev->dnr2, args, sizeof(dev->dnr2)));
  2878. #ifdef ISP_2DNR_V5
  2879. ret = isp_tdnr_s_2dnr(dev);
  2880. #else
  2881. ret = isp_s_2dnr(dev);
  2882. #endif
  2883. break;
  2884. case ISPIOC_S_SIMP:
  2885. viv_check_retval(copy_from_user
  2886. (&dev->simp, args, sizeof(dev->simp)));
  2887. ret = isp_s_simp(dev);
  2888. break;
  2889. case ISPIOC_S_COMP:
  2890. viv_check_retval(copy_from_user
  2891. (&dev->comp, args, sizeof(dev->comp)));
  2892. ret = isp_s_comp(dev);
  2893. break;
  2894. case ISPIOC_S_CPROC:
  2895. viv_check_retval(copy_from_user
  2896. (&dev->cproc, args, sizeof(dev->cproc)));
  2897. ret = isp_s_cproc(dev);
  2898. break;
  2899. case ISPIOC_S_XTALK:
  2900. viv_check_retval(copy_from_user
  2901. (&dev->xtalk, args, sizeof(dev->xtalk)));
  2902. ret = isp_s_xtalk(dev);
  2903. break;
  2904. case ISPIOC_S_ELAWB:
  2905. viv_check_retval(copy_from_user
  2906. (&dev->elawb, args, sizeof(dev->elawb)));
  2907. ret = isp_s_elawb(dev);
  2908. break;
  2909. case ISPIOC_S_INPUT:
  2910. viv_check_retval(copy_from_user
  2911. (&dev->ctx, args, sizeof(dev->ctx)));
  2912. ret = isp_s_input(dev);
  2913. break;
  2914. case ISPIOC_S_DEMOSAIC:
  2915. viv_check_retval(copy_from_user
  2916. (&dev->ctx, args, sizeof(dev->ctx)));
  2917. ret = isp_s_demosaic(dev);
  2918. break;
  2919. case ISPIOC_MI_START:
  2920. viv_check_retval(copy_from_user
  2921. (&dev->mi, args, sizeof(dev->mi)));
  2922. ret = isp_mi_start(dev);
  2923. break;
  2924. case ISPIOC_S_HDR_WB:
  2925. viv_check_retval(copy_from_user
  2926. (&dev->hdr, args, sizeof(dev->hdr)));
  2927. ret = isp_s_hdr_wb(dev);
  2928. break;
  2929. case ISPIOC_S_HDR_BLS:
  2930. viv_check_retval(copy_from_user
  2931. (&dev->hdr, args, sizeof(dev->hdr)));
  2932. ret = isp_s_hdr_bls(dev);
  2933. break;
  2934. case ISPIOC_S_HDR_DIGITAL_GAIN:
  2935. viv_check_retval(copy_from_user
  2936. (&dev->hdr, args, sizeof(dev->hdr)));
  2937. // ret = isp_s_hdr_digal_gain(dev);
  2938. break;
  2939. case ISPIOC_S_GAMMA_OUT:{
  2940. viv_check_retval(copy_from_user
  2941. (&dev->gamma_out, args,
  2942. sizeof(dev->gamma_out)));
  2943. ret = isp_s_gamma_out(dev);
  2944. break;
  2945. }
  2946. case ISPIOC_SET_BUFFER:{
  2947. struct isp_buffer_context buf;
  2948. viv_check_retval(copy_from_user
  2949. (&buf, args, sizeof(buf)));
  2950. #if defined(__KERNEL__) && defined(ENABLE_IRQ)
  2951. if (dev->alloc)
  2952. ret = dev->alloc(dev, &buf);
  2953. #else
  2954. ret = isp_set_buffer(dev, &buf);
  2955. #endif
  2956. break;
  2957. }
  2958. case ISPIOC_SET_BP_BUFFER:{
  2959. struct isp_bp_buffer_context buf;
  2960. viv_check_retval(copy_from_user
  2961. (&buf, args, sizeof(buf)));
  2962. ret = isp_set_bp_buffer(dev, &buf);
  2963. break;
  2964. }
  2965. case ISPIOC_START_CAPTURE:{
  2966. u32 num;
  2967. viv_check_retval(copy_from_user
  2968. (&num, args, sizeof(num)));
  2969. ret = isp_start_stream(dev, num);
  2970. if(!ret) {
  2971. dev->streaming = true;
  2972. }
  2973. break;
  2974. }
  2975. #if defined(ISP_3DNR_V2) || defined(ISP_3DNR_V2_V1)
  2976. case ISPIOC_S_3DNR_CMP: {
  2977. viv_check_retval(
  2978. copy_from_user(&dev->dnr3.compress, args, sizeof(dev->dnr3.compress)));
  2979. ret = isp_s_3dnr_cmp(dev);
  2980. break;
  2981. }
  2982. #endif
  2983. #if defined(ISP_3DNR) || defined(ISP_3DNR_V2)
  2984. case ISPIOC_U_3DNR:{
  2985. struct isp_3dnr_update param;
  2986. viv_check_retval(copy_from_user
  2987. (&param, args, sizeof(param)));
  2988. ret = isp_u_3dnr(dev, &param);
  2989. break;
  2990. }
  2991. case ISPIOC_S_3DNR:
  2992. viv_check_retval(copy_from_user
  2993. (&dev->dnr3, args, sizeof(dev->dnr3)));
  2994. ret = isp_s_3dnr(dev);
  2995. break;
  2996. case ISPIOC_U_3DNR_STRENGTH: {
  2997. viv_check_retval(
  2998. copy_from_user(&dev->dnr3, args, sizeof(dev->dnr3)));
  2999. ret = isp_u_3dnr_strength(dev);
  3000. break;
  3001. }
  3002. case ISPIOC_S_3DNR_MOT:{
  3003. viv_check_retval(copy_from_user
  3004. (&dev->dnr3, args, sizeof(dev->dnr3)));
  3005. ret = isp_s_3dnr_motion(dev);
  3006. break;
  3007. }
  3008. case ISPIOC_S_3DNR_DLT:{
  3009. viv_check_retval(copy_from_user
  3010. (&dev->dnr3, args, sizeof(dev->dnr3)));
  3011. ret = isp_s_3dnr_delta(dev);
  3012. break;
  3013. }
  3014. case ISPIOC_G_3DNR:{
  3015. u32 avg;
  3016. ret = isp_g_3dnr(dev, &avg);
  3017. viv_check_retval(copy_to_user(args, &avg, sizeof(avg)));
  3018. break;
  3019. }
  3020. #endif
  3021. case ISPIOC_G_AWBMEAN:{
  3022. struct isp_awb_mean mean;
  3023. ret = isp_g_awbmean(dev, &mean);
  3024. viv_check_retval(copy_to_user
  3025. (args, &mean, sizeof(mean)));
  3026. break;
  3027. }
  3028. case ISPIOC_G_EXPMEAN:{
  3029. u8 mean[25];
  3030. ret = isp_g_expmean(dev, mean);
  3031. viv_check_retval(copy_to_user
  3032. (args, mean, sizeof(mean)));
  3033. break;
  3034. }
  3035. case ISPIOC_G_HDREXPMEAN:{
  3036. u8 mean[75];
  3037. ret = isp_g_hdrexpmean(dev, mean);
  3038. viv_check_retval(copy_to_user
  3039. (args, mean, sizeof(mean)));
  3040. break;
  3041. }
  3042. case ISPIOC_G_HISTMEAN:{
  3043. u32 mean[HIST_BIN_TOTAL];
  3044. ret = isp_g_histmean(dev, mean);
  3045. viv_check_retval(copy_to_user
  3046. (args, mean, sizeof(mean)));
  3047. break;
  3048. }
  3049. case ISPIOC_G_HDRHISTMEAN:{
  3050. u32 mean[48];
  3051. ret = isp_g_hdrhistmean(dev, mean);
  3052. viv_check_retval(copy_to_user
  3053. (args, mean, sizeof(mean)));
  3054. break;
  3055. }
  3056. #ifdef ISP_HIST64
  3057. case ISPIOC_G_HIST64MEAN:{
  3058. u32 mean[HIST64_BIN_TOTAL];
  3059. ret = isp_g_hist64mean(dev, mean);
  3060. viv_check_retval(copy_to_user
  3061. (args, mean, sizeof(mean)));
  3062. break;
  3063. }
  3064. case ISPIOC_G_HIST64VSTART_STATUS:{
  3065. u32 status = 0;
  3066. ret = isp_g_hist64_vstart_status(dev, &status);
  3067. viv_check_retval(copy_to_user
  3068. (args, &status, sizeof(status)));
  3069. break;
  3070. }
  3071. #endif
  3072. case ISPIOC_G_VSM:{
  3073. struct isp_vsm_result vsm;
  3074. ret = isp_g_vsm(dev, &vsm);
  3075. viv_check_retval(copy_to_user(args, &vsm, sizeof(vsm)));
  3076. break;
  3077. }
  3078. case ISPIOC_G_AFM:{
  3079. struct isp_afm_result afm;
  3080. ret = isp_g_afm(dev, &afm);
  3081. viv_check_retval(copy_to_user(args, &afm, sizeof(afm)));
  3082. break;
  3083. }
  3084. case ISPIOC_G_STATUS:
  3085. ret = isp_ioc_g_status(dev, args);
  3086. break;
  3087. case ISPIOC_G_FEATURE:
  3088. ret = isp_ioc_g_feature(dev, args);
  3089. break;
  3090. case ISPIOC_G_FEATURE_VERSION:
  3091. ret = isp_ioc_g_feature_veresion(dev, args);
  3092. break;
  3093. case ISPIOC_WDR_CONFIG:
  3094. viv_check_retval(copy_from_user
  3095. (&dev->wdr, args, sizeof(dev->wdr)));
  3096. ret = isp_s_wdr(dev);
  3097. break;
  3098. case ISPIOC_S_WDR_CURVE:
  3099. viv_check_retval(copy_from_user
  3100. (&dev->wdr, args, sizeof(dev->wdr)));
  3101. ret = isp_s_wdr_curve(dev);
  3102. break;
  3103. case ISPIOC_ENABLE_GCMONO:
  3104. viv_check_retval(copy_from_user
  3105. (&dev->gcmono.mode, args, sizeof(u32)));
  3106. ret = isp_enable_gcmono(dev);
  3107. break;
  3108. case ISPIOC_DISABLE_GCMONO:
  3109. ret = isp_disable_gcmono(dev);
  3110. break;
  3111. case ISPIOC_S_GCMONO:{
  3112. struct isp_gcmono_data *data;
  3113. #ifdef __KERNEL__
  3114. data = (struct isp_gcmono_data *)
  3115. kmalloc(sizeof(struct isp_gcmono_data), GFP_KERNEL);
  3116. #else
  3117. data = (struct isp_gcmono_data *)
  3118. malloc(sizeof(struct isp_gcmono_data));
  3119. #endif
  3120. if (data == NULL) {
  3121. isp_err("%s, malloc mem for rgb gamma failed.", __func__);
  3122. ret = -1;
  3123. } else {
  3124. viv_check_retval(copy_from_user
  3125. (data, args,
  3126. sizeof(struct
  3127. isp_gcmono_data)));
  3128. ret = isp_s_gcmono(dev, data);
  3129. #ifdef __KERNEL__
  3130. kfree(data);
  3131. #else
  3132. free(data);
  3133. #endif
  3134. }
  3135. break;
  3136. }
  3137. case ISPIOC_ENABLE_RGBGAMMA:
  3138. ret = isp_enable_rgbgamma(dev);
  3139. break;
  3140. case ISPIOC_DISABLE_RGBGAMMA:
  3141. ret = isp_disable_rgbgamma(dev);
  3142. break;
  3143. case ISPIOC_S_RGBGAMMA:{
  3144. struct isp_rgbgamma_data *data;
  3145. #ifdef __KERNEL__
  3146. data = (struct isp_rgbgamma_data *)
  3147. kmalloc(sizeof(struct isp_rgbgamma_data),
  3148. GFP_KERNEL);
  3149. #else
  3150. data = (struct isp_rgbgamma_data *)
  3151. malloc(sizeof(struct isp_rgbgamma_data));
  3152. #endif
  3153. if (data == NULL) {
  3154. isp_err("%s, malloc mem for rgb gamma failed.", __func__);
  3155. ret = -1;
  3156. } else {
  3157. viv_check_retval(copy_from_user
  3158. (data, args,
  3159. sizeof(struct
  3160. isp_rgbgamma_data)));
  3161. dev->rgbgamma.data = data;
  3162. ret = isp_s_rgbgamma(dev);
  3163. //#ifdef __KERNEL__
  3164. // kfree(data);
  3165. //#else
  3166. // free(data);
  3167. //#endif
  3168. }
  3169. break;
  3170. }
  3171. case ISPIOC_S_GREENEQUILIBRATE:
  3172. viv_check_retval(copy_from_user
  3173. (&dev->ge, args, sizeof(dev->ge)));
  3174. ret = isp_s_ge(dev);
  3175. break;
  3176. case ISPIOC_S_COLOR_ADJUST:
  3177. viv_check_retval(copy_from_user
  3178. (&dev->ca, args, sizeof(dev->ca)));
  3179. ret = isp_s_ca(dev);
  3180. break;
  3181. #ifdef __KERNEL__
  3182. case VIDIOC_QUERYCAP:
  3183. ret = isp_ioc_qcap(dev, args);
  3184. break;
  3185. #endif
  3186. case ISPIOC_G_QUERY_EXTMEM:
  3187. ret = isp_get_extmem(dev, args);
  3188. break;
  3189. case ISPIOC_ENABLE_RGBIR:
  3190. viv_check_retval(copy_from_user
  3191. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3192. ret = isp_enable_rgbir(dev);
  3193. break;
  3194. case ISPIOC_S_RGBIR:
  3195. viv_check_retval(copy_from_user
  3196. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3197. ret = isp_s_rgbir(dev);
  3198. break;
  3199. case ISPIOC_RGBIR_HW_INIT:
  3200. viv_check_retval(copy_from_user
  3201. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3202. ret = isp_rgbir_hw_init(dev);
  3203. break;
  3204. case ISPIOC_RGBIR_S_IR_DNR:
  3205. viv_check_retval(copy_from_user
  3206. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3207. ret = isp_rgbir_s_ir_dnr(dev);
  3208. break;
  3209. case ISPIOC_RGBIR_S_SHARPEN:
  3210. viv_check_retval(copy_from_user
  3211. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3212. ret = isp_rgbir_s_sharpen(dev);
  3213. break;
  3214. case ISPIOC_RGBIR_S_DES:
  3215. viv_check_retval(copy_from_user
  3216. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3217. ret = isp_rgbir_s_des(dev);
  3218. break;
  3219. case ISPIOC_RGBIR_S_CC_MATRIX:
  3220. viv_check_retval(copy_from_user
  3221. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3222. ret = isp_rgbir_s_cc_matrix(dev);
  3223. break;
  3224. case ISPIOC_RGBIR_S_DPCC:
  3225. viv_check_retval(copy_from_user
  3226. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3227. ret = isp_rgbir_s_dpcc(dev);
  3228. break;
  3229. case ISPIOC_RGBIR_S_GAIN:
  3230. viv_check_retval(copy_from_user
  3231. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3232. ret = isp_rgbir_s_gain(dev);
  3233. break;
  3234. case ISPIOC_RGBIR_S_BLS:
  3235. viv_check_retval(copy_from_user
  3236. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3237. ret = isp_rgbir_s_bls(dev);
  3238. break;
  3239. case ISPIOC_RGBIR_S_IR_RAW_OUT:
  3240. viv_check_retval(copy_from_user
  3241. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3242. ret = isp_rgbir_out_ir_raw(dev);
  3243. break;
  3244. case ISPIOC_S_CROP:
  3245. viv_check_retval(copy_from_user
  3246. (&dev->crop, args, sizeof(struct isp_crop_context) * 3));
  3247. ret = isp_set_crop(dev);
  3248. break;
  3249. #ifdef ISP_3DNR_V3
  3250. case ISPIOC_S_TDNR:
  3251. viv_check_retval(copy_from_user
  3252. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3253. ret = isp_s_tdnr(dev);
  3254. break;
  3255. case ISPIOC_TDNR_ENABLE:
  3256. ret = isp_tdnr_enable(dev);
  3257. break;
  3258. case ISPIOC_TDNR_DISABLE:
  3259. ret = isp_tdnr_disable(dev);
  3260. break;
  3261. case ISPIOC_TDNR_ENABLE_TDNR:
  3262. ret = isp_tdnr_enable_tdnr(dev);
  3263. break;
  3264. case ISPIOC_TDNR_DISABLE_TDNR:
  3265. ret = isp_tdnr_disable_tdnr(dev);
  3266. break;
  3267. case ISPIOC_TDNR_ENABLE_2DNR:
  3268. ret = isp_tdnr_enable_2dnr(dev);
  3269. break;
  3270. case ISPIOC_TDNR_DISABLE_2DNR:
  3271. ret = isp_tdnr_disable_2dnr(dev);
  3272. break;
  3273. case ISPIOC_S_TDNR_CURVE:
  3274. viv_check_retval(copy_from_user
  3275. (&dev->tdnr.curve, args, sizeof(dev->tdnr.curve)));
  3276. ret = isp_tdnr_cfg_gamma(dev);
  3277. break;
  3278. case ISPIOC_G_TDNR: {
  3279. struct isp_tdnr_stats stats;
  3280. ret = isp_tdnr_g_stats(dev, &stats);
  3281. viv_check_retval(copy_to_user(args, &stats, sizeof(stats)));
  3282. }
  3283. break;
  3284. case ISPIOC_S_TDNR_STRENGTH:
  3285. viv_check_retval(copy_from_user
  3286. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3287. ret = isp_tdnr_set_strength(dev);
  3288. break;
  3289. case ISPIOC_U_TDNR_NOISE:
  3290. viv_check_retval(copy_from_user
  3291. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3292. ret = isp_tdnr_u_noise(dev);
  3293. break;
  3294. case ISPIOC_U_TDNR_THR:
  3295. viv_check_retval(copy_from_user
  3296. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3297. ret = isp_tdnr_u_thr(dev);
  3298. break;
  3299. case ISPIOC_R_TDNR_REFER:
  3300. ret = isp_r_tdnr_refer(dev);
  3301. break;
  3302. case ISPIOC_R_TDNR_MOTION:
  3303. ret = isp_r_tdnr_motion(dev);
  3304. break;
  3305. case ISPIOC_S_TDNR_BUF:
  3306. viv_check_retval(copy_from_user
  3307. (&dev->tdnr.buf, args, sizeof(dev->tdnr.buf)));
  3308. ret = isp_tdnr_s_buf(dev);
  3309. break;
  3310. #endif
  3311. #ifdef ISP_MI_PP_WRITE
  3312. case ISPIOC_GET_PPW_LINE_CNT:
  3313. {
  3314. u16 ppw_pic_cnt;
  3315. ret = isp_get_ppw_pic_cnt(dev, &ppw_pic_cnt);
  3316. viv_check_retval(copy_to_user
  3317. (args, &ppw_pic_cnt, sizeof(ppw_pic_cnt)));
  3318. break;
  3319. }
  3320. case ISPIOC_SET_PPW_LINE_NUM:
  3321. {
  3322. viv_check_retval(copy_from_user
  3323. (&dev->pp_write, args, sizeof(dev->pp_write)));
  3324. ret = isp_set_ppw_line_num(dev);
  3325. break;
  3326. }
  3327. #endif
  3328. #ifdef ISP_MI_PP_READ
  3329. case ISPIOC_CFG_DMA_LINE_ENTRY:
  3330. viv_check_retval(copy_from_user
  3331. (&dev->pp_dma_line_entry, args, sizeof(dev->pp_dma_line_entry)));
  3332. ret = isp_cfg_pp_dma_line_entry(dev);
  3333. break;
  3334. #endif
  3335. case ISPIOC_GET_FRAME_MASK_INFO_ADDR: {
  3336. unsigned long addr;
  3337. addr = dev->frame_mark_info_addr;
  3338. isp_info("ISPIOC_GET_FRAME_MASK_INFO_ADDR %lx\n", addr);
  3339. viv_check_retval(copy_to_user(args, &addr, sizeof(addr)));
  3340. ret = 0;
  3341. }
  3342. break;
  3343. case ISPIOC_FREE_IRQ:
  3344. ret = vvcam_free_isp_irq(dev);
  3345. break;
  3346. case ISPIOC_REQUEST_IRQ:
  3347. ret = vvcam_request_isp_irq(dev);
  3348. break;
  3349. default:
  3350. isp_err("unsupported command %d", cmd);
  3351. break;
  3352. }
  3353. if (cmd != ISPIOC_WRITE_REG) //frame end isp update shd registers.
  3354. ISP_GEN_CFG_UPDATE(dev);
  3355. return ret;
  3356. }