mrv_all_bits.h 449 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright 2010, Dream Chip Technologies GmbH. All rights reserved.
  4. *
  5. ****************************************************************************
  6. *
  7. * The MIT License (MIT)
  8. *
  9. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  10. *
  11. * Permission is hereby granted, free of charge, to any person obtaining a
  12. * copy of this software and associated documentation files (the "Software"),
  13. * to deal in the Software without restriction, including without limitation
  14. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  15. * and/or sell copies of the Software, and to permit persons to whom the
  16. * Software is furnished to do so, subject to the following conditions:
  17. *
  18. * The above copyright notice and this permission notice shall be included in
  19. * all copies or substantial portions of the Software.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  22. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  23. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  24. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  25. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  26. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  27. * DEALINGS IN THE SOFTWARE.
  28. *
  29. *****************************************************************************
  30. *
  31. * The GPL License (GPL)
  32. *
  33. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  34. *
  35. * This program is free software; you can redistribute it and/or
  36. * modify it under the terms of the GNU General Public License
  37. * as published by the Free Software Foundation; either version 2
  38. * of the License, or (at your option) any later version.
  39. *
  40. * This program is distributed in the hope that it will be useful,
  41. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  42. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  43. * GNU General Public License for more details.
  44. *
  45. * You should have received a copy of the GNU General Public License
  46. * along with this program;
  47. *
  48. *****************************************************************************
  49. *
  50. * Note: This software is released under dual MIT and GPL licenses. A
  51. * recipient may use this file under the terms of either the MIT license or
  52. * GPL License. If you wish to use only one license not the other, you can
  53. * indicate your decision by deleting one of the above license notices in your
  54. * version of this file.
  55. *
  56. *****************************************************************************/
  57. #ifndef __MRV_ALL_BITS_H__
  58. #define __MRV_ALL_BITS_H__
  59. /*****************************************************************************/
  60. /* this includes the registermap generated by SIG-flow */
  61. /*****************************************************************************/
  62. #ifndef __KERNEL__
  63. #include <stdint.h>
  64. #else
  65. #include <linux/types.h>
  66. #endif
  67. #include "mrv_all_regs.h"
  68. /*****************************************************************************/
  69. /* this includes the hw version information */
  70. /*****************************************************************************/
  71. #include "isp_version.h"
  72. /*****************************************************************************/
  73. /* Marvin Main Control Registers */
  74. /*****************************************************************************/
  75. #define ALIGN_16BYTE(width) (((width) + (0xF - 1)) & (~(0xF - 1)))
  76. /*****************************************************************************/
  77. /**
  78. * register: vi_ccl: Data path control register (0x0000)
  79. *
  80. *****************************************************************************/
  81. /* Slice: vi_ccl_dis:*/
  82. /* Clock Control Logic disable */
  83. /* 0: processing/cfg-clocks for all marvin sub modules enabled */
  84. /* 1: processing/cfg-clocks for all marvin sub modules disabled w/o access to ID and VI_CCL register */
  85. #ifdef MRV_VI_CCL_DIS
  86. #define MRV_VI_CCL_ENABLE_CLOCKS 0
  87. #define MRV_VI_CCL_DISABLE_CLOCKS 1
  88. #endif /* MRV_VI_CCL_DIS */
  89. /*****************************************************************************/
  90. /**
  91. * register: vi_id: Revision identification register (0x0008)
  92. *
  93. *****************************************************************************/
  94. /* Slice: rev_id:*/
  95. /* MARVIN5 revision IDs */
  96. #ifdef MRV_REV_ID
  97. #endif /* MRV_REV_ID */
  98. /*****************************************************************************/
  99. /**
  100. * register: vi_iccl: Internal clock control register (0x0010)
  101. *
  102. *****************************************************************************/
  103. /* Slice: vi_mipi_clk_enable: */
  104. /* MIPI interface clock enable */
  105. /* 1: processing mode */
  106. /* 0: power safe */
  107. #ifdef MRV_VI_MIPI_CLK_ENABLE
  108. #endif /* MRV_VI_MIPI_CLK_ENABLE */
  109. /* Slice: vi_smia_clk_enable:*/
  110. /* SMIA interface clock enable */
  111. /* 1: processing mode */
  112. /* 0: power safe */
  113. #ifdef MRV_VI_SMIA_CLK_ENABLE
  114. #endif /* MRV_VI_SMIA_CLK_ENABLE */
  115. /* Slice: vi_simp_clk_enable:*/
  116. /* Superimpose clock enable */
  117. /* 1: processing mode */
  118. /* 0: power safe */
  119. #ifdef MRV_VI_SIMP_CLK_ENABLE
  120. #endif /* MRV_VI_SIMP_CLK_ENABLE */
  121. /* Slice: vi_ie_clk_enable:*/
  122. /* Image effect clock enable */
  123. /* 1: processing mode */
  124. /* 0: power safe */
  125. #ifdef MRV_VI_IE_CLK_ENABLE
  126. #endif /* MRV_VI_IE_CLK_ENABLE */
  127. /* Slice: vi_mi_clk_enable:*/
  128. /* memory interface clock enable */
  129. /* 1: processing mode */
  130. /* 0: power safe */
  131. #ifdef MRV_VI_MI_CLK_ENABLE
  132. #endif /* MRV_VI_MI_CLK_ENABLE */
  133. /* Slice: vi_jpeg_clk_enable:*/
  134. /* JPEG encoder clock enable */
  135. /* 1: processing mode */
  136. /* 0: power safe */
  137. #ifdef MRV_VI_JPEG_CLK_ENABLE
  138. #endif /* MRV_VI_JPEG_CLK_ENABLE */
  139. /* Slice: vi_srsz_clk_enable:*/
  140. /* main resize clock enable */
  141. /* 1: processing mode */
  142. /* 0: power safe */
  143. #ifdef MRV_VI_SRSZ_CLK_ENABLE
  144. #endif /* MRV_VI_SRSZ_CLK_ENABLE */
  145. /* Slice: vi_mrsz_clk_enable:*/
  146. /* main resize clock enable */
  147. /* 1: processing mode */
  148. /* 0: power safe */
  149. #ifdef MRV_VI_MRSZ_CLK_ENABLE
  150. #endif /* MRV_VI_MRSZ_CLK_ENABLE */
  151. /* Slice: vi_cp_clk_enable:*/
  152. /* color processing clock enable */
  153. /* 1: processing mode */
  154. /* 0: power safe */
  155. #ifdef MRV_VI_CP_CLK_ENABLE
  156. #endif /* MRV_VI_CP_CLK_ENABLE */
  157. /* Slice: vi_isp_clk_enable:*/
  158. /* isp processing clock enable */
  159. /* 1: processing mode */
  160. /* 0: power safe */
  161. #ifdef MRV_VI_ISP_CLK_ENABLE
  162. #endif /* MRV_VI_ISP_CLK_ENABLE */
  163. /*****************************************************************************/
  164. /**
  165. * register: vi_ircl: Internal reset control register (0x0014)
  166. *
  167. *****************************************************************************/
  168. /* Slice: vi_mipi_soft_rst:*/
  169. /* MIPI Interface software reset */
  170. /* 0: processing mode */
  171. /* 1: reset state */
  172. #ifdef MRV_VI_MIPI_SOFT_RST
  173. #endif /* MRV_VI_MIPI_SOFT_RST */
  174. /* Slice: vi_smia_soft_rst:*/
  175. /* SMIA Interface software reset */
  176. /* 0: processing mode */
  177. /* 1: reset state */
  178. #ifdef MRV_VI_SMIA_SOFT_RST
  179. #endif /* MRV_VI_SMIA_SOFT_RST */
  180. /* Slice: vi_simp_soft_rst:*/
  181. /* Superimpose software reset */
  182. /* 0: processing mode */
  183. /* 1: reset state */
  184. #ifdef MRV_VI_SIMP_SOFT_RST
  185. #endif /* MRV_VI_SIMP_SOFT_RST */
  186. /* Slice: vi_ie_soft_rst:*/
  187. /* Image effect software reset */
  188. /* 0: processing mode */
  189. /* 1: reset state */
  190. #ifdef MRV_VI_IE_SOFT_RST
  191. #endif /* MRV_VI_IE_SOFT_RST */
  192. /* Slice: vi_marvin_rst:*/
  193. /* Soft reset of entire marvin */
  194. /* 0: processing mode */
  195. /* 1: reset state */
  196. #ifdef MRV_VI_MARVIN_RST
  197. #endif /* MRV_VI_MARVIN_RST */
  198. /* Slice: vi_mi_soft_rst:*/
  199. /* memory interface software reset */
  200. /* 0: processing mode */
  201. /* 1: reset state */
  202. #ifdef MRV_VI_MI_SOFT_RST
  203. #endif /* MRV_VI_MI_SOFT_RST */
  204. /* Slice: vi_jpeg_soft_rst:*/
  205. /* JPEG encoder software reset */
  206. /* 0: processing mode */
  207. /* 1: reset state */
  208. #ifdef MRV_VI_JPEG_SOFT_RST
  209. #endif /* MRV_VI_JPEG_SOFT_RST */
  210. /* Slice: vi_srsz_soft_rst:*/
  211. /* Self-picture resize software reset */
  212. /* 0: processing mode */
  213. /* 1: reset state */
  214. #ifdef MRV_VI_SRSZ_SOFT_RST
  215. #endif /* MRV_VI_SRSZ_SOFT_RST */
  216. /* Slice: vi_mrsz_soft_rst:*/
  217. /* Main-picture resize software reset */
  218. /* 0: processing mode */
  219. /* 1: reset state */
  220. #ifdef MRV_VI_MRSZ_SOFT_RST
  221. #endif /* MRV_VI_MRSZ_SOFT_RST */
  222. /* Slice: vi_ycs_soft_rst:*/
  223. /* y/c splitter software reset */
  224. /* 0: processing mode */
  225. /* 1: reset state */
  226. #ifdef MRV_VI_YCS_SOFT_RST
  227. #endif /* MRV_VI_YCS_SOFT_RST */
  228. /* Slice: vi_cp_soft_rst:*/
  229. /* color processing software reset */
  230. /* 0: processing mode */
  231. /* 1: reset state */
  232. #ifdef MRV_VI_CP_SOFT_RST
  233. #endif /* MRV_VI_CP_SOFT_RST */
  234. /* Slice: vi_isp_soft_rst:*/
  235. /* isp software reset */
  236. /* 0: processing mode */
  237. /* 1: reset state */
  238. #ifdef MRV_VI_ISP_SOFT_RST
  239. #endif /* MRV_VI_ISP_SOFT_RST */
  240. /*****************************************************************************/
  241. /**
  242. * register: vi_dpcl: Data path control register (0x0018)
  243. *
  244. *****************************************************************************/
  245. /* Slice: vi_dma_spmux:*/
  246. /* 0: data from camera interface to self resize */
  247. /* 1: data from DMA read port to self resize */
  248. #ifdef MRV_VI_DMA_SPMUX
  249. #define MRV_VI_DMA_SPMUX_CAM 0 /* 0: data from camera interface to self resize */
  250. #define MRV_VI_DMA_SPMUX_DMA 1 /* 1: data from DMA read port to self resize */
  251. #endif /* MRV_VI_DMA_SPMUX */
  252. /* Slice: vi_dma_iemux:*/
  253. /* 0: data from camera interface to image effects */
  254. /* 1: data from DMA read port to image effects */
  255. #ifdef MRV_VI_DMA_IEMUX
  256. #define MRV_VI_DMA_IEMUX_CAM 0 /* 0: data from camera interface to image effects */
  257. #define MRV_VI_DMA_IEMUX_DMA 1 /* 1: data from DMA read port to image effects */
  258. #endif /* MRV_VI_DMA_IEMUX */
  259. /* Slice: if_select:*/
  260. /* selects input interface */
  261. /* 0: parallel interface */
  262. /* 1: SMIA-interface */
  263. /* 2: MIPI-interface */
  264. #ifdef MRV_IF_SELECT
  265. #define MRV_IF_SELECT_PAR 0 /* 0: parallel interface */
  266. #define MRV_IF_SELECT_SMIA 1 /* 1: SMIA-interface */
  267. #define MRV_IF_SELECT_MIPI 2 /* 2: MIPI-interface */
  268. #define MRV_IF_SELECT_HDR 3 /* 2: HDR-interface */
  269. #endif /* MRV_IF_SELECT */
  270. /* Slice: vi_dma_switch:*/
  271. /* DMA read data path selector */
  272. /* 0: path to SPMUX */
  273. /* 1: path to Superimpose */
  274. /* 2: path to Image Effects */
  275. /* 3: reserved (for path to JPEG)*/
  276. /* 4..7: reserved */
  277. #ifdef MRV_VI_DMA_SWITCH
  278. #define MRV_VI_DMA_SWITCH_SELF 0 /* 0: path to SPMUX */
  279. #define MRV_VI_DMA_SWITCH_SIMP 1 /* 1: path to Superimpose */
  280. #define MRV_VI_DMA_SWITCH_IE 2 /* 2: path to Image Effects */
  281. #define MRV_VI_DMA_SWITCH_JPG 3 /* 3: path to JPEG */
  282. #define MRV_VI_DMA_SWITCH_ISP 4 /* 4: path to ISP */
  283. #endif /* MRV_VI_DMA_SWITCH */
  284. /* Slice: vi_chan_mode:*/
  285. /* Y/C splitter channel mode */
  286. /* 0: disabled */
  287. /* 1: main path and raw data mode */
  288. /* 2: self path mode */
  289. /* 3: main and self path mode */
  290. #ifdef MRV_VI_CHAN_MODE
  291. #define MRV_VI_CHAN_MODE_OFF 0x00 /* 0: disabled */
  292. #define MRV_VI_CHAN_MODE_Y 0xFF /* not supported */
  293. #define MRV_VI_CHAN_MODE_MP_RAW 0x01 /* 1: main path and raw data mode */
  294. #define MRV_VI_CHAN_MODE_MP 0x01 /* 1: main path and raw data mode */
  295. #define MRV_VI_CHAN_MODE_SP 0x02 /* 2: self path mode */
  296. #define MRV_VI_CHAN_MODE_MP_SP 0x03 /* 3: main and self path mode */
  297. #define MRV_VI_CHAN_MODE_SP2 0x04 /* 4: self2 path mode */
  298. #define MRV_VI_CHAN_MODE_MP_SP2 0x05 /* 5: main and self2 path mode */
  299. #define MRV_VI_CHAN_MODE_SP_SP2 0x06 /* 6: self and self2 path mode */
  300. #define MRV_VI_CHAN_MODE_MP_SP_SP2 0x07 /* 7: main self and self2 path mode */
  301. #endif /* MRV_VI_CHAN_MODE */
  302. /* Slice: vi_mp_mux:*/
  303. /* data path selector for main path */
  304. /* 00: reserved (future: data from DMA read port to JPEG encoder)*/
  305. /* 01: data from main resize to MI, uncompressed */
  306. /* 10: data from main resize to JPEG encoder */
  307. /* 11: reserved */
  308. #ifdef MRV_VI_MP_MUX
  309. #define MRV_VI_MP_MUX_JPGDIRECT 0x00 /* 00: reserved (future: data from DMA read port to JPEG encoder) */
  310. #define MRV_VI_MP_MUX_MP 0x01 /* 01: data from main resize to MI, uncompressed */
  311. #define MRV_VI_MP_MUX_RAW 0x01 /* (now also used for RAW data bypass) */
  312. #define MRV_VI_MP_MUX_JPEG 0x02 /* 10: data from main resize to JPEG encoder */
  313. #endif /* MRV_VI_MP_MUX */
  314. /*****************************************************************************/
  315. /* Image Effects Registers */
  316. /*****************************************************************************/
  317. /*****************************************************************************/
  318. /**
  319. * register: img_eff_ctrl: Global control register (0x0000)
  320. *
  321. *****************************************************************************/
  322. /* Slice: full_range:*/
  323. /* write 0: pixel value range according to BT.601 */
  324. /* write 1: YCbCr full range 0...255 */
  325. #ifdef MRV_IMGEFF_FULL_RANGE
  326. #define MRV_IMGEFF_FULL_RANGE_FULL 1 /* 1: YCbCr full range 0...255 */
  327. #define MRV_IMGEFF_FULL_RANGE_BT601 0 /* 0: pixel value range according to BT.601 */
  328. #endif /* MRV_IMGEFF_FULL_RANGE */
  329. /* Slice: cfg_upd:*/
  330. /* write 0: nothing happens */
  331. /* write 1: update shadow registers */
  332. /* read: always 0 */
  333. #ifdef MRV_IMGEFF_CFG_UPD
  334. #define MRV_IMGEFF_CFG_UPD_NOTHING 0 /* 0: nothing happens */
  335. #define MRV_IMGEFF_CFG_UPD_UPDATE 1 /* 1: update shadow registers */
  336. #endif /* MRV_IMGEFF_CFG_UPD */
  337. /* Slice: effect_mode:*/
  338. /* effect mode */
  339. /* 000: black & white effect (grayscale)*/
  340. /* 001: negative effect */
  341. /* 010: sepia effect */
  342. /* 011: color selection effect */
  343. /* 100: emboss effect */
  344. /* 101: sketch effect */
  345. /* 110: sharpen effect */
  346. /* 111: reserved */
  347. #ifdef MRV_IMGEFF_EFFECT_MODE
  348. #define MRV_IMGEFF_EFFECT_MODE_GRAY 0 /* 000: black & white effect (grayscale) */
  349. #define MRV_IMGEFF_EFFECT_MODE_NEGATIVE 1 /* 001: negative effect */
  350. #define MRV_IMGEFF_EFFECT_MODE_SEPIA 2 /* 010: sepia effect */
  351. #define MRV_IMGEFF_EFFECT_MODE_COLOR_SEL 3 /* 011: color selection effect */
  352. #define MRV_IMGEFF_EFFECT_MODE_EMBOSS 4 /* 100: emboss effect */
  353. #define MRV_IMGEFF_EFFECT_MODE_SKETCH 5 /* 101: sketch effect */
  354. #define MRV_IMGEFF_EFFECT_MODE_SHARPEN 6 /* 110: sharpen effect */
  355. #endif /* MRV_IMGEFF_EFFECT_MODE */
  356. /* Slice: bypass_mode:*/
  357. /* bypass mode */
  358. /* 1: processing is activated */
  359. /* 0: processing is deactivated, bypass mode is selected */
  360. #ifdef MRV_IMGEFF_BYPASS_MODE
  361. #define MRV_IMGEFF_BYPASS_MODE_PROCESS 1 /* 1: processing is activated */
  362. #define MRV_IMGEFF_BYPASS_MODE_BYPASS 0 /* 0: processing is deactivated, bypass mode is selected */
  363. #endif /* MRV_IMGEFF_BYPASS_MODE */
  364. /*****************************************************************************/
  365. /**
  366. * register: img_eff_color_sel: Color selection register (for
  367. * color selection effect) (0x0004)
  368. *
  369. *****************************************************************************/
  370. /* Slice: color_threshold:*/
  371. /* Threshold value of the RGB colors for the color selection effect.*/
  372. #ifdef MRV_IMGEFF_COLOR_THRESHOLD
  373. #endif /* MRV_IMGEFF_COLOR_THRESHOLD */
  374. /* Slice: color_selection:*/
  375. /* Defining the maintained color:*/
  376. /* 000: red green and blue */
  377. /* 001: blue */
  378. /* 010: green */
  379. /* 011: green and blue */
  380. /* 100: red */
  381. /* 101: red and blue */
  382. /* 110: red and green */
  383. /* 111: red green and blue */
  384. #ifdef MRV_IMGEFF_COLOR_SELECTION
  385. #define MRV_IMGEFF_COLOR_SELECTION_RGB 0 /* 000: red green and blue */
  386. #define MRV_IMGEFF_COLOR_SELECTION_B 1 /* 001: blue */
  387. #define MRV_IMGEFF_COLOR_SELECTION_G 2 /* 010: green */
  388. #define MRV_IMGEFF_COLOR_SELECTION_BG 3 /* 011: green and blue */
  389. #define MRV_IMGEFF_COLOR_SELECTION_R 4 /* 100: red */
  390. #define MRV_IMGEFF_COLOR_SELECTION_RB 5 /* 101: red and blue */
  391. #define MRV_IMGEFF_COLOR_SELECTION_RG 6 /* 110: red and green */
  392. #define MRV_IMGEFF_COLOR_SELECTION_BGR 7 /* 111: red green and blue */
  393. #endif /* MRV_IMGEFF_COLOR_SELECTION */
  394. /* Slice: emb_coef_21_en:*/
  395. /* 0: entry not used (coefficient is zero)*/
  396. /* 1: entry used */
  397. #ifdef MRV_IMGEFF_EMB_COEF_21_EN
  398. #endif /* MRV_IMGEFF_EMB_COEF_21_EN */
  399. /* Slice: emb_coef_21:*/
  400. /* second line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  401. /* coefficients:*/
  402. /* 000 (1), 001(2), 010(4), 011(8)*/
  403. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  404. #ifdef MRV_IMGEFF_EMB_COEF_21
  405. #define MRV_IMGEFF_EMB_COEF_21_ONE 0 /* 000 (1) */
  406. #define MRV_IMGEFF_EMB_COEF_21_TWO 1 /* 001 (2) */
  407. #define MRV_IMGEFF_EMB_COEF_21_FOUR 2 /* 010 (4) */
  408. #define MRV_IMGEFF_EMB_COEF_21_EIGHT 3 /* 011 (8) */
  409. #define MRV_IMGEFF_EMB_COEF_21_MIN_ONE 4 /* 100 (-1) */
  410. #define MRV_IMGEFF_EMB_COEF_21_MIN_TWO 5 /* 101 (-2) */
  411. #define MRV_IMGEFF_EMB_COEF_21_MIN_FOUR 6 /* 110 (-4) */
  412. #define MRV_IMGEFF_EMB_COEF_21_MIN_EIGHT 8 /* 111 (-8) */
  413. #endif /* MRV_IMGEFF_EMB_COEF_21 */
  414. /* combination of value and enable bit */
  415. #define MRV_IMGEFF_EMB_COEF_21_4
  416. #define MRV_IMGEFF_EMB_COEF_21_4_MASK 0x0000F000
  417. #define MRV_IMGEFF_EMB_COEF_21_4_SHIFT 12
  418. /* Slice: emb_coef_13_en:*/
  419. /* 0: entry not used (coefficient is zero)*/
  420. /* 1: entry used */
  421. #ifdef MRV_IMGEFF_EMB_COEF_13_EN
  422. #endif /* MRV_IMGEFF_EMB_COEF_13_EN */
  423. /* Slice: emb_coef_13:*/
  424. /* first line, right entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  425. /* coefficients:*/
  426. /* 000 (1), 001(2), 010(4), 011(8)*/
  427. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  428. #ifdef MRV_IMGEFF_EMB_COEF_13
  429. #define MRV_IMGEFF_EMB_COEF_13_ONE 0 /* 000 (1) */
  430. #define MRV_IMGEFF_EMB_COEF_13_TWO 1 /* 001 (2) */
  431. #define MRV_IMGEFF_EMB_COEF_13_FOUR 2 /* 010 (4) */
  432. #define MRV_IMGEFF_EMB_COEF_13_EIGHT 3 /* 011 (8) */
  433. #define MRV_IMGEFF_EMB_COEF_13_MIN_ONE 4 /* 100 (-1) */
  434. #define MRV_IMGEFF_EMB_COEF_13_MIN_TWO 5 /* 101 (-2) */
  435. #define MRV_IMGEFF_EMB_COEF_13_MIN_FOUR 6 /* 110 (-4) */
  436. #define MRV_IMGEFF_EMB_COEF_13_MIN_EIGHT 8 /* 111 (-8) */
  437. #endif /* MRV_IMGEFF_EMB_COEF_13 */
  438. /* combination of value and enable bit */
  439. #define MRV_IMGEFF_EMB_COEF_13_4
  440. #define MRV_IMGEFF_EMB_COEF_13_4_MASK 0x00000F00
  441. #define MRV_IMGEFF_EMB_COEF_13_4_SHIFT 8
  442. /* Slice: emb_coef_12_en:*/
  443. /* 0: entry not used (coefficient is zero)*/
  444. /* 1: entry used */
  445. #ifdef MRV_IMGEFF_EMB_COEF_12_EN
  446. #endif /* MRV_IMGEFF_EMB_COEF_12_EN */
  447. /* Slice: emb_coef_12:*/
  448. /* first line, middle entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  449. /* coefficients:*/
  450. /* 000 (1), 001(2), 010(4), 011(8)*/
  451. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  452. #ifdef MRV_IMGEFF_EMB_COEF_12
  453. #define MRV_IMGEFF_EMB_COEF_12_ONE 0 /* 000 (1) */
  454. #define MRV_IMGEFF_EMB_COEF_12_TWO 1 /* 001 (2) */
  455. #define MRV_IMGEFF_EMB_COEF_12_FOUR 2 /* 010 (4) */
  456. #define MRV_IMGEFF_EMB_COEF_12_EIGHT 3 /* 011 (8) */
  457. #define MRV_IMGEFF_EMB_COEF_12_MIN_ONE 4 /* 100 (-1) */
  458. #define MRV_IMGEFF_EMB_COEF_12_MIN_TWO 5 /* 101 (-2) */
  459. #define MRV_IMGEFF_EMB_COEF_12_MIN_FOUR 6 /* 110 (-4) */
  460. #define MRV_IMGEFF_EMB_COEF_12_MIN_EIGHT 8 /* 111 (-8) */
  461. #endif /* MRV_IMGEFF_EMB_COEF_12 */
  462. /* combination of value and enable bit */
  463. #define MRV_IMGEFF_EMB_COEF_12_4
  464. #define MRV_IMGEFF_EMB_COEF_12_4_MASK 0x000000F0
  465. #define MRV_IMGEFF_EMB_COEF_12_4_SHIFT 4
  466. /* Slice: emb_coef_11_en:*/
  467. /* 0: entry not used (coefficient is zero)*/
  468. /* 1: entry used */
  469. #ifdef MRV_IMGEFF_EMB_COEF_11_EN
  470. #define MRV_IMGEFF_EMB_COEF_11_EN_ON 1
  471. #define MRV_IMGEFF_EMB_COEF_11_EN_OFF 0
  472. #endif /* MRV_IMGEFF_EMB_COEF_11_EN */
  473. /* Slice: emb_coef_11:*/
  474. /* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  475. /* coefficients:*/
  476. /* 000 (1), 001(2), 010(4), 011(8)*/
  477. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  478. #ifdef MRV_IMGEFF_EMB_COEF_11
  479. #define MRV_IMGEFF_EMB_COEF_11_ONE 0 /* 000 (1) */
  480. #define MRV_IMGEFF_EMB_COEF_11_TWO 1 /* 001 (2) */
  481. #define MRV_IMGEFF_EMB_COEF_11_FOUR 2 /* 010 (4) */
  482. #define MRV_IMGEFF_EMB_COEF_11_EIGHT 3 /* 011 (8) */
  483. #define MRV_IMGEFF_EMB_COEF_11_MIN_ONE 4 /* 100 (-1) */
  484. #define MRV_IMGEFF_EMB_COEF_11_MIN_TWO 5 /* 101 (-2) */
  485. #define MRV_IMGEFF_EMB_COEF_11_MIN_FOUR 6 /* 110 (-4) */
  486. #define MRV_IMGEFF_EMB_COEF_11_MIN_EIGHT 8 /* 111 (-8) */
  487. #endif /* MRV_IMGEFF_EMB_COEF_11 */
  488. /* combination of value and enable bit */
  489. #define MRV_IMGEFF_EMB_COEF_11_4
  490. #define MRV_IMGEFF_EMB_COEF_11_4_MASK 0x0000000F
  491. #define MRV_IMGEFF_EMB_COEF_11_4_SHIFT 0
  492. /* Slice: emb_coef_32_en:*/
  493. /* 0: entry not used (coefficient is zero)*/
  494. /* 1: entry used */
  495. #ifdef MRV_IMGEFF_EMB_COEF_32_EN
  496. #endif /* MRV_IMGEFF_EMB_COEF_32_EN */
  497. /* Slice: emb_coef_32:*/
  498. /* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  499. /* coefficients:*/
  500. /* 000 (1), 001(2), 010(4), 011(8)*/
  501. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  502. #ifdef MRV_IMGEFF_EMB_COEF_32
  503. #define MRV_IMGEFF_EMB_COEF_32_ONE 0 /* 000 (1) */
  504. #define MRV_IMGEFF_EMB_COEF_32_TWO 1 /* 001 (2) */
  505. #define MRV_IMGEFF_EMB_COEF_32_FOUR 2 /* 010 (4) */
  506. #define MRV_IMGEFF_EMB_COEF_32_EIGHT 3 /* 011 (8) */
  507. #define MRV_IMGEFF_EMB_COEF_32_MIN_ONE 4 /* 100 (-1) */
  508. #define MRV_IMGEFF_EMB_COEF_32_MIN_TWO 5 /* 101 (-2) */
  509. #define MRV_IMGEFF_EMB_COEF_32_MIN_FOUR 6 /* 110 (-4) */
  510. #define MRV_IMGEFF_EMB_COEF_32_MIN_EIGHT 8 /* 111 (-8) */
  511. #endif /* MRV_IMGEFF_EMB_COEF_32 */
  512. /* combination of value and enable bit */
  513. #define MRV_IMGEFF_EMB_COEF_32_4
  514. #define MRV_IMGEFF_EMB_COEF_32_4_MASK 0x0000F000
  515. #define MRV_IMGEFF_EMB_COEF_32_4_SHIFT 12
  516. /* Slice: emb_coef_31_en:*/
  517. /* 0: entry not used (coefficient is zero)*/
  518. /* 1: entry used */
  519. #ifdef MRV_IMGEFF_EMB_COEF_31_EN
  520. #endif /* MRV_IMGEFF_EMB_COEF_31_EN */
  521. /* Slice: emb_coef_31:*/
  522. /* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  523. /* coefficients:*/
  524. /* 000 (1), 001(2), 010(4), 011(8)*/
  525. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  526. #ifdef MRV_IMGEFF_EMB_COEF_31
  527. #define MRV_IMGEFF_EMB_COEF_31_ONE 0 /* 000 (1) */
  528. #define MRV_IMGEFF_EMB_COEF_31_TWO 1 /* 001 (2) */
  529. #define MRV_IMGEFF_EMB_COEF_31_FOUR 2 /* 010 (4) */
  530. #define MRV_IMGEFF_EMB_COEF_31_EIGHT 3 /* 011 (8) */
  531. #define MRV_IMGEFF_EMB_COEF_31_MIN_ONE 4 /* 100 (-1) */
  532. #define MRV_IMGEFF_EMB_COEF_31_MIN_TWO 5 /* 101 (-2) */
  533. #define MRV_IMGEFF_EMB_COEF_31_MIN_FOUR 6 /* 110 (-4) */
  534. #define MRV_IMGEFF_EMB_COEF_31_MIN_EIGHT 8 /* 111 (-8) */
  535. #endif /* MRV_IMGEFF_EMB_COEF_31 */
  536. /* combination of value and enable bit */
  537. #define MRV_IMGEFF_EMB_COEF_31_4
  538. #define MRV_IMGEFF_EMB_COEF_31_4_MASK 0x00000F00
  539. #define MRV_IMGEFF_EMB_COEF_31_4_SHIFT 8
  540. /* Slice: emb_coef_23_en:*/
  541. /* 0: entry not used (coefficient is zero)*/
  542. /* 1: entry used */
  543. #ifdef MRV_IMGEFF_EMB_COEF_23_EN
  544. #endif /* MRV_IMGEFF_EMB_COEF_23_EN */
  545. /* Slice: emb_coef_23:*/
  546. /* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  547. /* coefficients:*/
  548. /* 000 (1), 001(2), 010(4), 011(8)*/
  549. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  550. #ifdef MRV_IMGEFF_EMB_COEF_23
  551. #define MRV_IMGEFF_EMB_COEF_23_ONE 0 /* 000 (1) */
  552. #define MRV_IMGEFF_EMB_COEF_23_TWO 1 /* 001 (2) */
  553. #define MRV_IMGEFF_EMB_COEF_23_FOUR 2 /* 010 (4) */
  554. #define MRV_IMGEFF_EMB_COEF_23_EIGHT 3 /* 011 (8) */
  555. #define MRV_IMGEFF_EMB_COEF_23_MIN_ONE 4 /* 100 (-1) */
  556. #define MRV_IMGEFF_EMB_COEF_23_MIN_TWO 5 /* 101 (-2) */
  557. #define MRV_IMGEFF_EMB_COEF_23_MIN_FOUR 6 /* 110 (-4) */
  558. #define MRV_IMGEFF_EMB_COEF_23_MIN_EIGHT 8 /* 111 (-8) */
  559. #endif /* MRV_IMGEFF_EMB_COEF_23 */
  560. /* combination of value and enable bit */
  561. #define MRV_IMGEFF_EMB_COEF_23_4
  562. #define MRV_IMGEFF_EMB_COEF_23_4_MASK 0x000000F0
  563. #define MRV_IMGEFF_EMB_COEF_23_4_SHIFT 4
  564. /* Slice: emb_coef_22_en:*/
  565. /* 0: entry not used (coefficient is zero)*/
  566. /* 1: entry used */
  567. #ifdef MRV_IMGEFF_EMB_COEF_22_EN
  568. #endif /* MRV_IMGEFF_EMB_COEF_22_EN */
  569. /* Slice: emb_coef_22:*/
  570. /* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  571. /* coefficients:*/
  572. /* 000 (1), 001(2), 010(4), 011(8)*/
  573. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  574. #ifdef MRV_IMGEFF_EMB_COEF_22
  575. #define MRV_IMGEFF_EMB_COEF_22_ONE 0 /* 000 (1) */
  576. #define MRV_IMGEFF_EMB_COEF_22_TWO 1 /* 001 (2) */
  577. #define MRV_IMGEFF_EMB_COEF_22_FOUR 2 /* 010 (4) */
  578. #define MRV_IMGEFF_EMB_COEF_22_EIGHT 3 /* 011 (8) */
  579. #define MRV_IMGEFF_EMB_COEF_22_MIN_ONE 4 /* 100 (-1) */
  580. #define MRV_IMGEFF_EMB_COEF_22_MIN_TWO 5 /* 101 (-2) */
  581. #define MRV_IMGEFF_EMB_COEF_22_MIN_FOUR 6 /* 110 (-4) */
  582. #define MRV_IMGEFF_EMB_COEF_22_MIN_EIGHT 8 /* 111 (-8) */
  583. #endif /* MRV_IMGEFF_EMB_COEF_22 */
  584. /* combination of value and enable bit */
  585. #define MRV_IMGEFF_EMB_COEF_22_4
  586. #define MRV_IMGEFF_EMB_COEF_22_4_MASK 0x0000000F
  587. #define MRV_IMGEFF_EMB_COEF_22_4_SHIFT 0
  588. /*****************************************************************************/
  589. /**
  590. * register: img_eff_mat_3: 3x3 matrix coefficients for emboss(3) effect /
  591. * sketch(1) effect (0x0010)
  592. *
  593. *****************************************************************************/
  594. /* Slice: sket_coef_13_en:*/
  595. /* 0: entry not used (coefficient is zero)*/
  596. /* 1: entry used */
  597. #ifdef MRV_IMGEFF_SKET_COEF_13_EN
  598. #endif /* MRV_IMGEFF_SKET_COEF_13_EN */
  599. /* Slice: sket_coef_13:*/
  600. /* first line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  601. /* coefficients:*/
  602. /* 000 (1), 001(2), 010(4), 011(8)*/
  603. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  604. #ifdef MRV_IMGEFF_SKET_COEF_13
  605. #define MRV_IMGEFF_SKET_COEF_13_ONE 0 /* 000 (1) */
  606. #define MRV_IMGEFF_SKET_COEF_13_TWO 1 /* 001 (2) */
  607. #define MRV_IMGEFF_SKET_COEF_13_FOUR 2 /* 010 (4) */
  608. #define MRV_IMGEFF_SKET_COEF_13_EIGHT 3 /* 011 (8) */
  609. #define MRV_IMGEFF_SKET_COEF_13_MIN_ONE 4 /* 100 (-1) */
  610. #define MRV_IMGEFF_SKET_COEF_13_MIN_TWO 5 /* 101 (-2) */
  611. #define MRV_IMGEFF_SKET_COEF_13_MIN_FOUR 6 /* 110 (-4) */
  612. #define MRV_IMGEFF_SKET_COEF_13_MIN_EIGHT 8 /* 111 (-8) */
  613. #endif /* MRV_IMGEFF_SKET_COEF_13 */
  614. /* combination of value and enable bit */
  615. #define MRV_IMGEFF_SKET_COEF_13_4
  616. #define MRV_IMGEFF_SKET_COEF_13_4_MASK 0x0000F000
  617. #define MRV_IMGEFF_SKET_COEF_13_4_SHIFT 12
  618. /* Slice: sket_coef_12_en:*/
  619. /* 0: entry not used (coefficient is zero)*/
  620. /* 1: entry used */
  621. #ifdef MRV_IMGEFF_SKET_COEF_12_EN
  622. #endif /* MRV_IMGEFF_SKET_COEF_13_EN */
  623. /* Slice: sket_coef_12:*/
  624. /* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  625. /* coefficients:*/
  626. /* 000 (1), 001(2), 010(4), 011(8)*/
  627. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  628. #ifdef MRV_IMGEFF_SKET_COEF_12
  629. #define MRV_IMGEFF_SKET_COEF_12_ONE 0 /* 000 (1) */
  630. #define MRV_IMGEFF_SKET_COEF_12_TWO 1 /* 001 (2) */
  631. #define MRV_IMGEFF_SKET_COEF_12_FOUR 2 /* 010 (4) */
  632. #define MRV_IMGEFF_SKET_COEF_12_EIGHT 3 /* 011 (8) */
  633. #define MRV_IMGEFF_SKET_COEF_12_MIN_ONE 4 /* 100 (-1) */
  634. #define MRV_IMGEFF_SKET_COEF_12_MIN_TWO 5 /* 101 (-2) */
  635. #define MRV_IMGEFF_SKET_COEF_12_MIN_FOUR 6 /* 110 (-4) */
  636. #define MRV_IMGEFF_SKET_COEF_12_MIN_EIGHT 8 /* 111 (-8) */
  637. #endif /* MRV_IMGEFF_SKET_COEF_12 */
  638. /* combination of value and enable bit */
  639. #define MRV_IMGEFF_SKET_COEF_12_4
  640. #define MRV_IMGEFF_SKET_COEF_12_4_MASK 0x00000F00
  641. #define MRV_IMGEFF_SKET_COEF_12_4_SHIFT 8
  642. /* Slice: sket_coef_11_en:*/
  643. /* 0: entry not used (coefficient is zero)*/
  644. /* 1: entry used */
  645. #ifdef MRV_IMGEFF_SKET_COEF_11_EN
  646. #endif /* MRV_IMGEFF_SKET_COEF_13_EN */
  647. /* Slice: sket_coef_11:*/
  648. /* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  649. /* coefficients:*/
  650. /* 000 (1), 001(2), 010(4), 011(8)*/
  651. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  652. #ifdef MRV_IMGEFF_SKET_COEF_11
  653. #define MRV_IMGEFF_SKET_COEF_11_ONE 0 /* 000 (1) */
  654. #define MRV_IMGEFF_SKET_COEF_11_TWO 1 /* 001 (2) */
  655. #define MRV_IMGEFF_SKET_COEF_11_FOUR 2 /* 010 (4) */
  656. #define MRV_IMGEFF_SKET_COEF_11_EIGHT 3 /* 011 (8) */
  657. #define MRV_IMGEFF_SKET_COEF_11_MIN_ONE 4 /* 100 (-1) */
  658. #define MRV_IMGEFF_SKET_COEF_11_MIN_TWO 5 /* 101 (-2) */
  659. #define MRV_IMGEFF_SKET_COEF_11_MIN_FOUR 6 /* 110 (-4) */
  660. #define MRV_IMGEFF_SKET_COEF_11_MIN_EIGHT 8 /* 111 (-8) */
  661. #endif /* MRV_IMGEFF_SKET_COEF_11 */
  662. /* combination of value and enable bit */
  663. #define MRV_IMGEFF_SKET_COEF_11_4
  664. #define MRV_IMGEFF_SKET_COEF_11_4_MASK 0x000000F0
  665. #define MRV_IMGEFF_SKET_COEF_11_4_SHIFT 4
  666. /* Slice: emb_coef_33_en:*/
  667. /* 0: entry not used (coefficient is zero)*/
  668. /* 1: entry used */
  669. #ifdef MRV_IMGEFF_EMB_COEF_33_EN
  670. #endif /* MRV_IMGEFF_EMB_COEF_33_EN */
  671. /* Slice: emb_coef_33:*/
  672. /* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  673. /* coefficients:*/
  674. /* 000 (1), 001(2), 010(4), 011(8)*/
  675. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  676. #ifdef MRV_IMGEFF_EMB_COEF_3
  677. #define MRV_IMGEFF_EMB_COEF_33_ONE 0 /* 000 (1) */
  678. #define MRV_IMGEFF_EMB_COEF_33_TWO 1 /* 001 (2) */
  679. #define MRV_IMGEFF_EMB_COEF_33_FOUR 2 /* 010 (4) */
  680. #define MRV_IMGEFF_EMB_COEF_33_EIGHT 3 /* 011 (8) */
  681. #define MRV_IMGEFF_EMB_COEF_33_MIN_ONE 4 /* 100 (-1) */
  682. #define MRV_IMGEFF_EMB_COEF_33_MIN_TWO 5 /* 101 (-2) */
  683. #define MRV_IMGEFF_EMB_COEF_33_MIN_FOUR 6 /* 110 (-4) */
  684. #define MRV_IMGEFF_EMB_COEF_33_MIN_EIGHT 8 /* 111 (-8) */
  685. #endif /* MRV_IMGEFF_EMB_COEF_33 */
  686. /* combination of value and enable bit */
  687. #define MRV_IMGEFF_EMB_COEF_33_4
  688. #define MRV_IMGEFF_EMB_COEF_33_4_MASK 0x0000000F
  689. #define MRV_IMGEFF_EMB_COEF_33_4_SHIFT 0
  690. /*****************************************************************************/
  691. /**
  692. * register: img_eff_mat_4: 3x3 matrix coefficients for sketch effect (2)
  693. * (0x0014)
  694. *
  695. *****************************************************************************/
  696. /* Slice: sket_coef_31_en:*/
  697. /* 0: entry not used (coefficient is zero)*/
  698. /* 1: entry used */
  699. #ifdef MRV_IMGEFF_SKET_COEF_31_EN
  700. #endif /* MRV_IMGEFF_SKET_COEF_31_EN */
  701. /* Slice: sket_coef_31:*/
  702. /* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  703. /* coefficients:*/
  704. /* 000 (1), 001(2), 010(4), 011(8)*/
  705. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  706. #ifdef MRV_IMGEFF_SKET_COEF_31
  707. #define MRV_IMGEFF_SKET_COEF_31_ONE 0 /* 000 (1) */
  708. #define MRV_IMGEFF_SKET_COEF_31_TWO 1 /* 001 (2) */
  709. #define MRV_IMGEFF_SKET_COEF_31_FOUR 2 /* 010 (4) */
  710. #define MRV_IMGEFF_SKET_COEF_31_EIGHT 3 /* 011 (8) */
  711. #define MRV_IMGEFF_SKET_COEF_31_MIN_ONE 4 /* 100 (-1) */
  712. #define MRV_IMGEFF_SKET_COEF_31_MIN_TWO 5 /* 101 (-2) */
  713. #define MRV_IMGEFF_SKET_COEF_31_MIN_FOUR 6 /* 110 (-4) */
  714. #define MRV_IMGEFF_SKET_COEF_31_MIN_EIGHT 8 /* 111 (-8) */
  715. #endif /* MRV_IMGEFF_SKET_COEF_31 */
  716. /* combination of value and enable bit */
  717. #define MRV_IMGEFF_SKET_COEF_31_4
  718. #define MRV_IMGEFF_SKET_COEF_31_4_MASK 0x0000F000
  719. #define MRV_IMGEFF_SKET_COEF_31_4_SHIFT 12
  720. /* Slice: sket_coef_23_en:*/
  721. /* 0: entry not used (coefficient is zero)*/
  722. /* 1: entry used */
  723. #ifdef MRV_IMGEFF_SKET_COEF_23_EN
  724. #endif /* MRV_IMGEFF_SKET_COEF_23_EN */
  725. /* Slice: sket_coef_23:*/
  726. /* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  727. /* coefficients:*/
  728. /* 000 (1), 001(2), 010(4), 011(8)*/
  729. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  730. #ifdef MRV_IMGEFF_SKET_COEF_23
  731. #define MRV_IMGEFF_SKET_COEF_23_ONE 0 /* 000 (1) */
  732. #define MRV_IMGEFF_SKET_COEF_23_TWO 1 /* 001 (2) */
  733. #define MRV_IMGEFF_SKET_COEF_23_FOUR 2 /* 010 (4) */
  734. #define MRV_IMGEFF_SKET_COEF_23_EIGHT 3 /* 011 (8) */
  735. #define MRV_IMGEFF_SKET_COEF_23_MIN_ONE 4 /* 100 (-1) */
  736. #define MRV_IMGEFF_SKET_COEF_23_MIN_TWO 5 /* 101 (-2) */
  737. #define MRV_IMGEFF_SKET_COEF_23_MIN_FOUR 6 /* 110 (-4) */
  738. #define MRV_IMGEFF_SKET_COEF_23_MIN_EIGHT 8 /* 111 (-8) */
  739. #endif /* MRV_IMGEFF_SKET_COEF_23 */
  740. /* combination of value and enable bit */
  741. #define MRV_IMGEFF_SKET_COEF_23_4
  742. #define MRV_IMGEFF_SKET_COEF_23_4_MASK 0x00000F00
  743. #define MRV_IMGEFF_SKET_COEF_23_4_SHIFT 8
  744. /* Slice: sket_coef_22_en:*/
  745. /* 0: entry not used (coefficient is zero)*/
  746. /* 1: entry used */
  747. #ifdef MRV_IMGEFF_SKET_COEF_22_EN
  748. #endif /* MRV_IMGEFF_SKET_COEF_22_EN */
  749. /* Slice: sket_coef_22:*/
  750. /* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  751. /* coefficients:*/
  752. /* 000 (1), 001(2), 010(4), 011(8)*/
  753. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  754. #ifdef MRV_IMGEFF_SKET_COEF_22
  755. #define MRV_IMGEFF_SKET_COEF_22_ONE 0 /* 000 (1) */
  756. #define MRV_IMGEFF_SKET_COEF_22_TWO 1 /* 001 (2) */
  757. #define MRV_IMGEFF_SKET_COEF_22_FOUR 2 /* 010 (4) */
  758. #define MRV_IMGEFF_SKET_COEF_22_EIGHT 3 /* 011 (8) */
  759. #define MRV_IMGEFF_SKET_COEF_22_MIN_ONE 4 /* 100 (-1) */
  760. #define MRV_IMGEFF_SKET_COEF_22_MIN_TWO 5 /* 101 (-2) */
  761. #define MRV_IMGEFF_SKET_COEF_22_MIN_FOUR 6 /* 110 (-4) */
  762. #define MRV_IMGEFF_SKET_COEF_22_MIN_EIGHT 8 /* 111 (-8) */
  763. #endif /* MRV_IMGEFF_SKET_COEF_22 */
  764. /* combination of value and enable bit */
  765. #define MRV_IMGEFF_SKET_COEF_22_4
  766. #define MRV_IMGEFF_SKET_COEF_22_4_MASK 0x000000F0
  767. #define MRV_IMGEFF_SKET_COEF_22_4_SHIFT 4
  768. /* Slice: sket_coef_21_en:*/
  769. /* 0: entry not used (coefficient is zero)*/
  770. /* 1: entry used */
  771. #ifdef MRV_IMGEFF_SKET_COEF_21_EN
  772. #endif /* MRV_IMGEFF_SKET_COEF_21_EN */
  773. /* Slice: sket_coef_21:*/
  774. /* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  775. /* coefficients:*/
  776. /* 000 (1), 001(2), 010(4), 011(8)*/
  777. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  778. #ifdef MRV_IMGEFF_SKET_COEF_21
  779. #define MRV_IMGEFF_SKET_COEF_21_ONE 0 /* 000 (1) */
  780. #define MRV_IMGEFF_SKET_COEF_21_TWO 1 /* 001 (2) */
  781. #define MRV_IMGEFF_SKET_COEF_21_FOUR 2 /* 010 (4) */
  782. #define MRV_IMGEFF_SKET_COEF_21_EIGHT 3 /* 011 (8) */
  783. #define MRV_IMGEFF_SKET_COEF_21_MIN_ONE 4 /* 100 (-1) */
  784. #define MRV_IMGEFF_SKET_COEF_21_MIN_TWO 5 /* 101 (-2) */
  785. #define MRV_IMGEFF_SKET_COEF_21_MIN_FOUR 6 /* 110 (-4) */
  786. #define MRV_IMGEFF_SKET_COEF_21_MIN_EIGHT 8 /* 111 (-8) */
  787. #endif /* MRV_IMGEFF_SKET_COEF_21 */
  788. /* combination of value and enable bit */
  789. #define MRV_IMGEFF_SKET_COEF_21_4
  790. #define MRV_IMGEFF_SKET_COEF_21_4_MASK 0x0000000F
  791. #define MRV_IMGEFF_SKET_COEF_21_4_SHIFT 0
  792. /*****************************************************************************/
  793. /**
  794. * register: img_eff_mat_5: 3x3 matrix coefficients for sketch effect (3)
  795. * (0x0018)
  796. *
  797. *****************************************************************************/
  798. /* Slice: sket_coef_33_en:*/
  799. /* 0: entry not used (coefficient is zero)*/
  800. /* 1: entry used */
  801. #ifdef MRV_IMGEFF_SKET_COEF_33_EN
  802. #endif /* MRV_IMGEFF_SKET_COEF_33_EN */
  803. /* Slice: sket_coef_33:*/
  804. /* third line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  805. /* coefficients:*/
  806. /* 000 (1), 001(2), 010(4), 011(8)*/
  807. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  808. #ifdef MRV_IMGEFF_SKET_COEF_33
  809. #define MRV_IMGEFF_SKET_COEF_33_ONE 0 /* 000 (1) */
  810. #define MRV_IMGEFF_SKET_COEF_33_TWO 1 /* 001 (2) */
  811. #define MRV_IMGEFF_SKET_COEF_33_FOUR 2 /* 010 (4) */
  812. #define MRV_IMGEFF_SKET_COEF_33_EIGHT 3 /* 011 (8) */
  813. #define MRV_IMGEFF_SKET_COEF_33_MIN_ONE 4 /* 100 (-1) */
  814. #define MRV_IMGEFF_SKET_COEF_33_MIN_TWO 5 /* 101 (-2) */
  815. #define MRV_IMGEFF_SKET_COEF_33_MIN_FOUR 6 /* 110 (-4) */
  816. #define MRV_IMGEFF_SKET_COEF_33_MIN_EIGHT 8 /* 111 (-8) */
  817. #endif /* MRV_IMGEFF_SKET_COEF_33 */
  818. /* combination of value and enable bit */
  819. #define MRV_IMGEFF_SKET_COEF_33_4
  820. #define MRV_IMGEFF_SKET_COEF_33_4_MASK 0x000000F0
  821. #define MRV_IMGEFF_SKET_COEF_33_4_SHIFT 4
  822. /* Slice: sket_coef_32_en:*/
  823. /* 0: entry not used (coefficient is zero)*/
  824. /* 1: entry used */
  825. #ifdef MRV_IMGEFF_SKET_COEF_32_EN
  826. #endif /* MRV_IMGEFF_SKET_COEF_32_EN */
  827. /* Slice: sket_coef_32:*/
  828. /* third line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  829. /* coefficients:*/
  830. /* 000 (1), 001(2), 010(4), 011(8)*/
  831. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  832. #ifdef MRV_IMGEFF_SKET_COEF_32
  833. #define MRV_IMGEFF_SKET_COEF_32_ONE 0 /* 000 (1) */
  834. #define MRV_IMGEFF_SKET_COEF_32_TWO 1 /* 001 (2) */
  835. #define MRV_IMGEFF_SKET_COEF_32_FOUR 2 /* 010 (4) */
  836. #define MRV_IMGEFF_SKET_COEF_32_EIGHT 3 /* 011 (8) */
  837. #define MRV_IMGEFF_SKET_COEF_32_MIN_ONE 4 /* 100 (-1) */
  838. #define MRV_IMGEFF_SKET_COEF_32_MIN_TWO 5 /* 101 (-2) */
  839. #define MRV_IMGEFF_SKET_COEF_32_MIN_FOUR 6 /* 110 (-4) */
  840. #define MRV_IMGEFF_SKET_COEF_32_MIN_EIGHT 8 /* 111 (-8) */
  841. #endif /* MRV_IMGEFF_SKET_COEF_32 */
  842. /* combination of value and enable bit */
  843. #define MRV_IMGEFF_SKET_COEF_32_4
  844. #define MRV_IMGEFF_SKET_COEF_32_4_MASK 0x0000000F
  845. #define MRV_IMGEFF_SKET_COEF_32_4_SHIFT 0
  846. /* valid for all coeffiecient definitions */
  847. #define MRV_IMGEFF_COEF
  848. #define MRV_IMGEFF_COEF_ONE 0U
  849. #define MRV_IMGEFF_COEF_TWO 1U /* 001: (2) */
  850. #define MRV_IMGEFF_COEF_FOUR 2U /* 010: (4) */
  851. #define MRV_IMGEFF_COEF_EIGHT 3U /* 011: (8) */
  852. #define MRV_IMGEFF_COEF_MIN_ONE 4U /* 100: (-1) */
  853. #define MRV_IMGEFF_COEF_MIN_TWO 5U /* 101: (-2) */
  854. #define MRV_IMGEFF_COEF_MIN_FOUR 6U /* 110: (-4) */
  855. #define MRV_IMGEFF_COEF_MIN_EIGHT 7U /* 111: (-8) */
  856. #define MRV_IMGEFF_COEF_ON 1U /* 1: coefficient enabled */
  857. #define MRV_IMGEFF_COEF_OFF 0U /* 0: coefficient disabled */
  858. #define MRV_IMGEFF_COEF_SHIFT 3U /* shift for enable bit */
  859. /*****************************************************************************/
  860. /**
  861. * register: img_eff_tint: Chrominance increment values of a tint
  862. * (used for sepia effect) (0x001c)
  863. *
  864. *****************************************************************************/
  865. /* Slice: incr_cr:*/
  866. /* Cr increment value of a tint. 7 bits for value, 1 sign bit.*/
  867. /* Default tint is R=162 G=138 B=101, which is used for the sepia effect. See below for the calculation of the entries.*/
  868. #ifdef MRV_IMGEFF_INCR_CR
  869. #endif /* MRV_IMGEFF_INCR_CR */
  870. /* Slice: incr_cb:*/
  871. /* Cb increment value of a tint. 7 bits for value, 1 sign bit.*/
  872. /* Default tint is R=162 G=138 B=101, which is used for the sepia effect. See below for the calculation of the entries.*/
  873. #ifdef MRV_IMGEFF_INCR_CB
  874. #endif /* MRV_IMGEFF_INCR_CB */
  875. /*****************************************************************************/
  876. /**
  877. * register: img_eff_ctrl_shd: Shadow register for control register (0x0020)
  878. *
  879. *****************************************************************************/
  880. /* Slice: effect_mode_shd:*/
  881. /* effect mode */
  882. /* 000: black & white effect (grayscale)*/
  883. /* 001: negative effect */
  884. /* 010: sepia effect */
  885. /* 011: color selection effect */
  886. /* 100: emboss effect */
  887. /* 101: sketch effect */
  888. /* 110-111: not used */
  889. #ifdef MRV_IMGEFF_EFFECT_MODE_SHD
  890. #define MRV_IMGEFF_EFFECT_MODE_SHD_GRAY 0 /* 000: black & white effect (grayscale) */
  891. #define MRV_IMGEFF_EFFECT_MODE_SHD_NEGATIVE 1 /* 001: negative effect */
  892. #define MRV_IMGEFF_EFFECT_MODE_SHD_SEPIA 2 /* 010: sepia effect */
  893. #define MRV_IMGEFF_EFFECT_MODE_SHD_COLOR_SEL 3 /* 011: color selection effect */
  894. #define MRV_IMGEFF_EFFECT_MODE_SHD_EMBOSS 4 /* 100: emboss effect */
  895. #define MRV_IMGEFF_EFFECT_MODE_SHD_SKETCH 5 /* 101: sketch effect */
  896. #define MRV_IMGEFF_EFFECT_MODE_SHD_SHARPEN 6 /* 110: sharpen effect */
  897. #endif /* MRV_IMGEFF_EFFECT_MODE_SHD */
  898. /*****************************************************************************/
  899. /* Super Impose Registers */
  900. /*****************************************************************************/
  901. /*****************************************************************************/
  902. /**
  903. * register: super_imp_ctrl: Global control register (0x0000)
  904. *
  905. *****************************************************************************/
  906. /* Slice: transparency_mode:*/
  907. /* transparency mode */
  908. /* 1: transparency mode disabled */
  909. /* 0: transparency mode enabled */
  910. #ifdef MRV_SI_TRANSPARENCY_MODE
  911. #define MRV_SI_TRANSPARENCY_MODE_DISABLED 1 /* 1: transparency mode disabled */
  912. #define MRV_SI_TRANSPARENCY_MODE_ENABLED 0 /* 0: transparency mode enabled */
  913. #endif /* MRV_SI_TRANSPARENCY_MODE */
  914. /* Slice: ref_image:*/
  915. /* Define the reference image */
  916. /* 1: superimpose bitmap from main memory */
  917. /* 0: image from the Image Effect module */
  918. /* Note: the reference image defines the size of the output image */
  919. #ifdef MRV_SI_REF_IMAGE
  920. #define MRV_SI_REF_IMAGE_MEM 1 /* 1: superimpose bitmap from main memory */
  921. #define MRV_SI_REF_IMAGE_IE 0 /* 0: image from the Image Effect module */
  922. #endif /* MRV_SI_REF_IMAGE */
  923. /* Slice: bypass_mode:*/
  924. /* bypass mode */
  925. /* 1: processing is activated */
  926. /* 0: processing is deactivated, bypass mode is selected */
  927. #ifdef MRV_SI_BYPASS_MODE
  928. #define MRV_SI_BYPASS_MODE_PROCESS 1 /* 1: processing is activated */
  929. #define MRV_SI_BYPASS_MODE_BYPASS 0 /* 0: processing is deactivated, bypass mode is selected */
  930. #endif /* MRV_IMGEFF_BYPASS_MODE */
  931. /*****************************************************************************/
  932. /**
  933. * register: super_imp_offset_x: Offset x register (0x0004)
  934. *
  935. *****************************************************************************/
  936. /* Slice: offset_x:*/
  937. /* Offset X */
  938. /* Note: the bit 0 is don't care (write 1 doesn't have any effect, the read access always gives 0)*/
  939. /* Note: the offset_x is positive and refers to the reference image */
  940. #ifdef MRV_SI_OFFSET_X
  941. #endif /* MRV_SI_OFFSET_X */
  942. /*****************************************************************************/
  943. /**
  944. * register: super_imp_offset_y: Offset y register (0x0008)
  945. *
  946. *****************************************************************************/
  947. /* Slice: offset_y:*/
  948. /* Offset Y */
  949. /* Note: the offset_y is positive and refers to the reference image */
  950. #ifdef MRV_SI_OFFSET_Y
  951. #endif /* MRV_SI_OFFSET_Y */
  952. /*****************************************************************************/
  953. /**
  954. * register: super_imp_color_y: Y component of transparent key color (0x000c)
  955. *
  956. *****************************************************************************/
  957. /* Slice: y_comp:*/
  958. /* Y component of transparent key color */
  959. #ifdef MRV_SI_Y_COMP
  960. #endif /* MRV_SI_Y_COMP */
  961. /*****************************************************************************/
  962. /**
  963. * register: super_imp_color_cb: Cb component of transparent key color (0x0010)
  964. *
  965. *****************************************************************************/
  966. /* Slice: cb_comp:*/
  967. /* Cb component of transparent key color */
  968. #ifdef MRV_SI_CB_COMP
  969. #endif /* MRV_SI_CB_COMP */
  970. /*****************************************************************************/
  971. /**
  972. * register: super_imp_color_cr: Cr component of transparent key color (0x0014)
  973. *
  974. *****************************************************************************/
  975. /* Slice: cr_comp:*/
  976. /* Cr component of transparent key color */
  977. #ifdef MRV_SI_CR_COMP
  978. #endif /* MRV_SI_CR_COMP */
  979. /*****************************************************************************/
  980. /* ISP Registers */
  981. /*****************************************************************************/
  982. /*****************************************************************************/
  983. /**
  984. * register: isp_ctrl: global control register (0x0000)
  985. *
  986. *****************************************************************************/
  987. /* Slice: ISP_DPF_RAW_OUT */
  988. /*! Slice MRV_ISP_DPF_RAW_OUT:*/
  989. /*! 0: DPF RAW OUT is disable */
  990. /*! 1: DPF RAW OUT is enable */
  991. #ifdef ISP_DPF_RAW
  992. #ifdef MRV_ISP_DPF_RAW_OUT
  993. #define MRV_ISP_DPF_RAW_OUT_DISABLE 0 /* 0: DPF raw out is disable */
  994. #define MRV_ISP_DPF_RAW_OUT_ENABLE 1 /* 1: DPF raw out is enable */
  995. #endif
  996. #endif
  997. /* Slice: ISP_CSM_C_RANGE:*/
  998. /* Color Space Matrix chrominance clipping range for ISP output */
  999. /* 0: CbCr range 64..960 (16..240) according to ITU-R BT.601 standard */
  1000. /* 1: full UV range 0..1023 (0..255)*/
  1001. /* Numbers in brackets are for 8 bit resolution.*/
  1002. #ifdef MRV_ISP_ISP_CSM_C_RANGE
  1003. #define MRV_ISP_ISP_CSM_C_RANGE_BT601 0 /* 0: CbCr range 64..960 (16..240) according to ITU-R BT.601 standard */
  1004. #define MRV_ISP_ISP_CSM_C_RANGE_FULL 1 /* 1: full UV range 0..1023 (0..255) */
  1005. #endif /* MRV_ISP_ISP_CSM_C_RANGE */
  1006. /* Slice: ISP_CSM_Y_RANGE:*/
  1007. /* Color Space Matrix luminance clipping range for ISP output */
  1008. /* 0: Y range 64..940 (16..235) according to ITU-R BT.601 standard */
  1009. /* 1: full Y range 0..1023 (0..255)*/
  1010. /* Numbers in brackets are for 8 bit resolution.*/
  1011. #ifdef MRV_ISP_ISP_CSM_Y_RANGE
  1012. #define MRV_ISP_ISP_CSM_Y_RANGE_BT601 0 /* 0: Y range 64..940 (16..235) according to ITU-R BT.601 standard */
  1013. #define MRV_ISP_ISP_CSM_Y_RANGE_FULL 1 /* 1: full Y range 0..1023 (0..255) */
  1014. #endif /* MRV_ISP_ISP_CSM_Y_RANGE */
  1015. /* Slice: ISP_FLASH_MODE:*/
  1016. /* 0: sensor interface works independently from flash control unit */
  1017. /* 1: one frame is captured when signaled by flash control unit */
  1018. #ifdef MRV_ISP_ISP_FLASH_MODE
  1019. #define MRV_ISP_ISP_FLASH_MODE_INDEP 0 /* 0: sensor interface works independently from flash control unit */
  1020. #define MRV_ISP_ISP_FLASH_MODE_SYNC 1 /* 1: one frame is captured when signaled by flash control unit */
  1021. #endif /* MRV_ISP_ISP_FLASH_MODE */
  1022. /* Slice: ISP_GAMMA_OUT_ENABLE:*/
  1023. /* gamma ON/OFF */
  1024. #ifdef MRV_ISP_ISP_GAMMA_OUT_ENABLE
  1025. #endif /* MRV_ISP_ISP_GAMMA_OUT_ENABLE */
  1026. /* Slice: ISP_GEN_CFG_UPD:*/
  1027. /* generate vsynced config shadow signal at the output, write only */
  1028. #ifdef MRV_ISP_ISP_GEN_CFG_UPD
  1029. #endif /* MRV_ISP_ISP_GEN_CFG_UPD */
  1030. /* Slice: ISP_CFG_UPD:*/
  1031. /* immediate configure internal shadow registers, write only */
  1032. #ifdef MRV_ISP_ISP_CFG_UPD
  1033. #endif /* MRV_ISP_ISP_CFG_UPD */
  1034. /* Slice: ISP_AE_ENABLE:*/
  1035. /* auto exposure ON/OFF */
  1036. #ifdef MRV_ISP_ISP_AE_ENABLE
  1037. #endif /* MRV_ISP_ISP_AE_ENABLE */
  1038. /* Slice: ISP_AWB_ENABLE:*/
  1039. /* auto white balance ON/OFF */
  1040. #ifdef MRV_ISP_ISP_AWB_ENABLE
  1041. #endif /* MRV_ISP_ISP_AWB_ENABLE */
  1042. /* Slice: ISP_GAMMA_IN_ENABLE:*/
  1043. /* Sensor De-gamma ON/OFF */
  1044. #ifdef MRV_ISP_ISP_GAMMA_IN_ENABLE
  1045. #define MRV_ISP_ISP_GAMMA_IN_ENABLE_ON 1U
  1046. #define MRV_ISP_ISP_GAMMA_IN_ENABLE_OFF 0U
  1047. #endif /* MRV_ISP_ISP_GAMMA_IN_ENABLE */
  1048. /* Slice: ISP_INFORM_ENABLE:*/
  1049. /* input block ON/OFF (frame-synced on)*/
  1050. #ifdef MRV_ISP_ISP_INFORM_ENABLE
  1051. #endif /* MRV_ISP_ISP_INFORM_ENABLE */
  1052. /* Slice: ISP_MODE:*/
  1053. /* 000: RAW picture with BT.601 sync (ISP bypass)*/
  1054. /* 001: ITU-R BT.656 (YUV with embedded sync)*/
  1055. /* 010: ITU-R BT.601 (YUV input with H and Vsync signals)*/
  1056. /* 011: Bayer RGB processing with H and Vsync signals */
  1057. /* 100: data mode (ISP bypass, sync signals interpreted as data enable)*/
  1058. /* 101: Bayer RGB processing with BT.656 synchronization */
  1059. /* 110: RAW picture with ITU-R BT.656 synchronization (ISP bypass)*/
  1060. /* 111: reserved */
  1061. /**/
  1062. /* Side effect:*/
  1063. /* If RAW, BT.601, BT.656, or data mode is selected, the clock of the */
  1064. /* ISP SRAMs (ISP line buffer, Lens Shading, Bad Pixel) is switched off.*/
  1065. /* Only in Bayer RGB mode the clock to the SRAMs is enabled. This */
  1066. /* further reduces power consumption.*/
  1067. #ifdef MRV_ISP_ISP_MODE
  1068. #define MRV_ISP_ISP_MODE_RAW 0 /* 000 - RAW picture with BT.601 sync (ISP bypass) */
  1069. #define MRV_ISP_ISP_MODE_656 1 /* 001 - ITU-R BT.656 (YUV with embedded sync) */
  1070. #define MRV_ISP_ISP_MODE_601 2 /* 010 - ITU-R BT.601 (YUV input with H and Vsync signals) */
  1071. #define MRV_ISP_ISP_MODE_RGB 3 /* 011 - Bayer RGB processing with H and Vsync signals */
  1072. #define MRV_ISP_ISP_MODE_DATA 4 /* 100 - data mode (ISP bypass, sync signals interpreted as data enable) */
  1073. #define MRV_ISP_ISP_MODE_RGB656 5 /* 101 - Bayer RGB processing with BT.656 synchronization */
  1074. #define MRV_ISP_ISP_MODE_RAW656 6 /* 110 - RAW picture with ITU-R BT.656 synchronization (ISP bypass) */
  1075. #endif /* MRV_ISP_ISP_MODE */
  1076. /* Slice: ISP_ENABLE:*/
  1077. /* MANUAL ON/OFF (controls output formatter, framesynced)*/
  1078. #ifdef MRV_ISP_ISP_ENABLE
  1079. #endif /* MRV_ISP_ISP_ENABLE */
  1080. /*****************************************************************************/
  1081. /**
  1082. * register: isp_acq_prop: ISP acquisition properties (0x0004)
  1083. *
  1084. *****************************************************************************/
  1085. #ifdef ISP_DVP_PINMAPPING
  1086. /*! Slice: MRV_ISP_DVP_INPUT_PIN_MAPPING */
  1087. /*! Bit Mapping for LSB to MSP for ISPNano.*/
  1088. /*! 3'b000: normal 12-bit external interface */
  1089. /*! 3'b001: mapping low 10 bit to high 10 bits, append 2 zeros as LSBs.*/
  1090. /*! 3'b010: mapping low 8 bit to high 8 bits, append 4 zeros as LSBs.*/
  1091. /*! 3'b011: mapping middle 8 bit to high 8 bits, append 4 zeros as LSBs.*/
  1092. /*! 3'b100..3'b111: rsvd */
  1093. #ifdef MRV_ISP_DVP_INPUT_PIN_MAPPING
  1094. #define MRV_ISP_DVP_INPUT_PIN_MAPPING_12TO12 0
  1095. #define MRV_ISP_DVP_INPUT_PIN_MAPPING_L10TOH10 1
  1096. #define MRV_ISP_DVP_INPUT_PIN_MAPPING_L8TOH8 2
  1097. #define MRV_ISP_DVP_INPUT_PIN_MAPPING_M8TOH8 3
  1098. #endif
  1099. #endif
  1100. /*! Slice: DMA_YUV_SELECTION */
  1101. /*! 0: use align or conversion data for isp_is input */
  1102. /*! 1: use dma yuv read data for isp_is input */
  1103. #ifdef MRV_ISP_DMA_YUV_SELECTION
  1104. #define MRV_ISP_DMA_YUV_SELECTION_ALIGNED_CONV 0
  1105. #define MRV_ISP_DMA_YUV_SELECTION_DMA_YUV 1
  1106. #endif
  1107. /* Slice: LATENCY_FIFO_SELECTION:*/
  1108. /* 0: use input formatter input for latency fifo.*/
  1109. /* 1: use dma rgb read input for latency fifo.*/
  1110. #ifdef MRV_ISP_LATENCY_FIFO_SELECTION
  1111. #define MRV_ISP_LATENCY_FIFO_SELECTION_INPUT_FORMATTER 0
  1112. #define MRV_ISP_LATENCY_FIFO_SELECTION_DMA_READ 1
  1113. #endif /* MRV_ISP_LATENCY_FIFO_SELECTION */
  1114. /* Slice: INPUT_SELECTION:*/
  1115. /* 000: 12Bit external Interface */
  1116. /* 001: 10Bit Interface, append 2 zeroes as LSBs */
  1117. /* 010: 10Bit Interface, append 2 MSBs as LSBs */
  1118. /* 011: 8Bit Interface, append 4 zeroes as LSBs */
  1119. /* 100: 8Bit Interface, append 4 MSBs as LSBs */
  1120. /* 101...111: reserved */
  1121. #ifdef MRV_ISP_INPUT_SELECTION
  1122. #define MRV_ISP_INPUT_SELECTION_12EXT 0 /* 000- 12Bit external Interface */
  1123. #define MRV_ISP_INPUT_SELECTION_10ZERO 1 /* 001- 10Bit Interface, append 2 zeroes as LSBs */
  1124. #define MRV_ISP_INPUT_SELECTION_10MSB 2 /* 010- 10Bit Interface, append 2 MSBs as LSBs */
  1125. #define MRV_ISP_INPUT_SELECTION_8ZERO 3 /* 011- 8Bit Interface, append 4 zeroes as LSBs */
  1126. #define MRV_ISP_INPUT_SELECTION_8MSB 4 /* 100- 8Bit Interface, append 4 MSBs as LSBs */
  1127. #endif /* MRV_ISP_INPUT_SELECTION */
  1128. /* Slice: FIELD_SELECTION:*/
  1129. /* 00: sample all fields (don't care about fields)*/
  1130. /* 01: sample only even fields */
  1131. /* 10: sample only odd fields */
  1132. /* 11: reserved */
  1133. #ifdef MRV_ISP_FIELD_SELECTION
  1134. #define MRV_ISP_FIELD_SELECTION_BOTH 0 /* 00- sample all fields (don't care about fields) */
  1135. #define MRV_ISP_FIELD_SELECTION_EVEN 1 /* 01- sample only even fields */
  1136. #define MRV_ISP_FIELD_SELECTION_ODD 2 /* 10- sample only odd fields */
  1137. #endif /* MRV_ISP_FIELD_SELECTION */
  1138. /* Slice: CCIR_SEQ:*/
  1139. /* 00: YCbYCr */
  1140. /* 01: YCrYCb */
  1141. /* 10: CbYCrY */
  1142. /* 11: CrYCbY */
  1143. #ifdef MRV_ISP_CCIR_SEQ
  1144. #define MRV_ISP_CCIR_SEQ_YCBYCR 0 /* 00 - YCbYCr */
  1145. #define MRV_ISP_CCIR_SEQ_YCRYCB 1 /* 01 - YCrYCb */
  1146. #define MRV_ISP_CCIR_SEQ_CBYCRY 2 /* 10 - CbYCrY */
  1147. #define MRV_ISP_CCIR_SEQ_CRYCBY 3 /* 11 - CrYCbY */
  1148. #endif /* MRV_ISP_CCIR_SEQ */
  1149. /* Slice: CONV_422:*/
  1150. /* 00- co-sited color subsampling Y0Cb0Cr0 - Y1 */
  1151. /* 01- interleaved color subsampling Y0Cb0 - Y1Cr1 (not recommended)*/
  1152. /* 10- non-cosited color subsampling Y0Cb(0+1)/2 - Y1Cr(0+1)/2 */
  1153. /* 11- reserved */
  1154. #ifdef MRV_ISP_CONV_422
  1155. #define MRV_ISP_CONV_422_CO 0 /* 00- co-sited color subsampling Y0Cb0Cr0 - Y1 */
  1156. #define MRV_ISP_CONV_422_INTER 1 /* 01- interleaved color subsampling Y0Cb0 - Y1Cr1 (not recommended) */
  1157. #define MRV_ISP_CONV_422_NONCO 2 /* 10- non-cosited color subsampling Y0Cb(0+1)/2 - Y1Cr(0+1)/2 */
  1158. #endif /* MRV_ISP_CONV_422 */
  1159. /* Slice: BAYER_PAT:*/
  1160. /* color components from sensor, starting with top left position in sampled frame */
  1161. /* (reprogram with ISP_ACQ_H_OFFS, ISP_ACQ_V_OFFS)*/
  1162. /**/
  1163. /* 00: first line: RGRG, second line: GBGB, etc.*/
  1164. /* 01: first line: GRGR, second line: BGBG, etc.*/
  1165. /* 10: first line: GBGB, second line: RGRG, etc.*/
  1166. /* 11: first line: BGBG, second line: GRGR, etc.*/
  1167. /* This configuration applies for the black level area after cropping by the input formatter.*/
  1168. #ifdef MRV_ISP_BAYER_PAT
  1169. #define MRV_ISP_BAYER_PAT_RG 0 /* 00 - first line: RGRG, second line: GBGB, etc. */
  1170. #define MRV_ISP_BAYER_PAT_GR 1 /* 01 - first line: GRGR, second line: BGBG, etc. */
  1171. #define MRV_ISP_BAYER_PAT_GB 2 /* 10 - first line: GBGB, second line: RGRG, etc. */
  1172. #define MRV_ISP_BAYER_PAT_BG 3 /* 11 - first line: BGBG, second line: GRGR, etc. */
  1173. #endif /* MRV_ISP_BAYER_PAT */
  1174. /* Slice: VSYNC_POL:*/
  1175. /* vertical sync polarity */
  1176. /* 0: high active */
  1177. /* 1: low active */
  1178. #ifdef MRV_ISP_VSYNC_POL
  1179. #endif /* MRV_ISP_VSYNC_POL */
  1180. /* Slice: HSYNC_POL:*/
  1181. /* horizontal sync polarity */
  1182. /* 0: high active */
  1183. /* 1: low active */
  1184. #ifdef MRV_ISP_HSYNC_POL
  1185. #endif /* MRV_ISP_HSYNC_POL */
  1186. /* Slice: SAMPLE_EDGE:*/
  1187. /* 0: negative edge sampling */
  1188. /* 1: positive edge sampling */
  1189. #ifdef MRV_ISP_SAMPLE_EDGE
  1190. #endif /* MRV_ISP_SAMPLE_EDGE */
  1191. /*****************************************************************************/
  1192. /**
  1193. * register: isp_acq_h_offs: horizontal input offset (0x0008)
  1194. *
  1195. *****************************************************************************/
  1196. /* Slice: ACQ_H_OFFS:*/
  1197. /* horizontal sample offset in 8-bit samples (yuv: 4 samples=2pix)*/
  1198. #ifdef MRV_ISP_ACQ_H_OFFS
  1199. #endif /* MRV_ISP_ACQ_H_OFFS */
  1200. /*****************************************************************************/
  1201. /**
  1202. * register: isp_acq_v_offs: vertical input offset (0x000c)
  1203. *
  1204. *****************************************************************************/
  1205. /* Slice: ACQ_V_OFFS:*/
  1206. /* vertical sample offset in lines */
  1207. #ifdef MRV_ISP_ACQ_V_OFFS
  1208. #endif /* MRV_ISP_ACQ_V_OFFS */
  1209. /*****************************************************************************/
  1210. /**
  1211. * register: isp_acq_h_size: horizontal input size (0x0010)
  1212. *
  1213. *****************************************************************************/
  1214. /* Slice: ACQ_H_SIZE:*/
  1215. /* horizontal sample size in 12-bit samples */
  1216. /* YUV input: 2 samples = 1 pixel, else 1 sample = 1 pixel; So in YUV mode ACQ_H_SIZE must be twice as large as horizontal image size */
  1217. /* horizontal image size must always be even exept in raw picture mode; if an odd size is programmed the value will be truncated to even size */
  1218. #ifdef MRV_ISP_ACQ_H_SIZE
  1219. #endif /* MRV_ISP_ACQ_H_SIZE */
  1220. /*****************************************************************************/
  1221. /**
  1222. * register: isp_acq_v_size: vertical input size (0x0014)
  1223. *
  1224. *****************************************************************************/
  1225. /* Slice: ACQ_V_SIZE:*/
  1226. /* vertical sample size in lines */
  1227. #ifdef MRV_ISP_ACQ_V_SIZE
  1228. #endif /* MRV_ISP_ACQ_V_SIZE */
  1229. /*****************************************************************************/
  1230. /**
  1231. * register: isp_acq_nr_frames: Number of frames to be captured (0x0018)
  1232. *
  1233. *****************************************************************************/
  1234. /* Slice: ACQ_NR_FRAMES:*/
  1235. /* number of input frames to be sampled (0 = continuous)*/
  1236. #ifdef MRV_ISP_ACQ_NR_FRAMES
  1237. #endif /* MRV_ISP_ACQ_NR_FRAMES */
  1238. /*****************************************************************************/
  1239. /**
  1240. * register: isp_gamma_dx_lo: De-Gamma Curve definition lower x increments
  1241. * (sampling points) (0x001c)
  1242. *
  1243. *****************************************************************************/
  1244. /* Slice: GAMMA_DX_8:*/
  1245. /* gamma curve sample point definition x-axis (input)*/
  1246. #ifdef MRV_ISP_GAMMA_DX_8
  1247. #endif /* MRV_ISP_GAMMA_DX_8 */
  1248. /* Slice: GAMMA_DX_7:*/
  1249. /* gamma curve sample point definition x-axis (input)*/
  1250. #ifdef MRV_ISP_GAMMA_DX_7
  1251. #endif /* MRV_ISP_GAMMA_DX_7 */
  1252. /* Slice: GAMMA_DX_6:*/
  1253. /* gamma curve sample point definition x-axis (input)*/
  1254. #ifdef MRV_ISP_GAMMA_DX_6
  1255. #endif /* MRV_ISP_GAMMA_DX_6 */
  1256. /* Slice: GAMMA_DX_5:*/
  1257. /* gamma curve sample point definition x-axis (input)*/
  1258. #ifdef MRV_ISP_GAMMA_DX_5
  1259. #endif /* MRV_ISP_GAMMA_DX_5 */
  1260. /* Slice: GAMMA_DX_4:*/
  1261. /* gamma curve sample point definition x-axis (input)*/
  1262. #ifdef MRV_ISP_GAMMA_DX_4
  1263. #endif /* MRV_ISP_GAMMA_DX_4 */
  1264. /* Slice: GAMMA_DX_3:*/
  1265. /* gamma curve sample point definition x-axis (input)*/
  1266. #ifdef MRV_ISP_GAMMA_DX_3
  1267. #endif /* MRV_ISP_GAMMA_DX_3 */
  1268. /* Slice: GAMMA_DX_2:*/
  1269. /* gamma curve sample point definition x-axis (input)*/
  1270. #ifdef MRV_ISP_GAMMA_DX_2
  1271. #endif /* MRV_ISP_GAMMA_DX_2 */
  1272. /* Slice: GAMMA_DX_1:*/
  1273. /* gamma curve sample point definition x-axis (input)*/
  1274. #ifdef MRV_ISP_GAMMA_DX_1
  1275. #endif /* MRV_ISP_GAMMA_DX_1 */
  1276. /*****************************************************************************/
  1277. /**
  1278. * register: isp_gamma_dx_hi: De-Gamma Curve definition higher x increments
  1279. * (sampling points) (0x0020)
  1280. *
  1281. *****************************************************************************/
  1282. /* Slice: GAMMA_DX_16:*/
  1283. /* gamma curve sample point definition x-axis (input)*/
  1284. #ifdef MRV_ISP_GAMMA_DX_16
  1285. #endif /* MRV_ISP_GAMMA_DX_16 */
  1286. /* Slice: GAMMA_DX_15:*/
  1287. /* gamma curve sample point definition x-axis (input)*/
  1288. #ifdef MRV_ISP_GAMMA_DX_15
  1289. #endif /* MRV_ISP_GAMMA_DX_15 */
  1290. /* Slice: GAMMA_DX_14:*/
  1291. /* gamma curve sample point definition x-axis (input)*/
  1292. #ifdef MRV_ISP_GAMMA_DX_14
  1293. #endif /* MRV_ISP_GAMMA_DX_14 */
  1294. /* Slice: GAMMA_DX_13:*/
  1295. /* gamma curve sample point definition x-axis (input)*/
  1296. #ifdef MRV_ISP_GAMMA_DX_13
  1297. #endif /* MRV_ISP_GAMMA_DX_13 */
  1298. /* Slice: GAMMA_DX_12:*/
  1299. /* gamma curve sample point definition x-axis (input)*/
  1300. #ifdef MRV_ISP_GAMMA_DX_12
  1301. #endif /* MRV_ISP_GAMMA_DX_12 */
  1302. /* Slice: GAMMA_DX_11:*/
  1303. /* gamma curve sample point definition x-axis (input)*/
  1304. #ifdef MRV_ISP_GAMMA_DX_11
  1305. #endif /* MRV_ISP_GAMMA_DX_11 */
  1306. /* Slice: GAMMA_DX_10:*/
  1307. /* gamma curve sample point definition x-axis (input)*/
  1308. #ifdef MRV_ISP_GAMMA_DX_10
  1309. #endif /* MRV_ISP_GAMMA_DX_10 */
  1310. /* Slice: GAMMA_DX_9:*/
  1311. /* gamma curve sample point definition x-axis (input)*/
  1312. #ifdef MRV_ISP_GAMMA_DX_9
  1313. #endif /* MRV_ISP_GAMMA_DX_9 */
  1314. /*****************************************************************************/
  1315. /**
  1316. * register array: isp_gamma_r_y: De-Gamma Curve definition y red (0x0024+n (n=0..16))
  1317. *
  1318. *****************************************************************************/
  1319. /* Slice: GAMMA_R_Y:*/
  1320. /* gamma curve point definition y-axis (output) for red */
  1321. /* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that dy is 12-bit signed !)*/
  1322. #ifdef MRV_ISP_GAMMA_R_Y
  1323. #endif /* MRV_ISP_GAMMA_R_Y */
  1324. /*****************************************************************************/
  1325. /**
  1326. * register array: isp_gamma_g_y: De-Gamma Curve definition y green (0x0068+n (n=0..16))
  1327. *
  1328. *****************************************************************************/
  1329. /* Slice: GAMMA_G_Y:*/
  1330. /* gamma curve point definition y-axis (output) for green */
  1331. /* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that dy is 12-bit signed !)*/
  1332. #ifdef MRV_ISP_GAMMA_G_Y
  1333. #endif /* MRV_ISP_GAMMA_G_Y */
  1334. /*****************************************************************************/
  1335. /**
  1336. * register array: isp_gamma_b_y: De-Gamma Curve definition y blue (0x00AC+n (n=0..16))
  1337. *
  1338. *****************************************************************************/
  1339. /* Slice: GAMMA_B_Y:*/
  1340. /* gamma curve point definition y-axis (output) for blue */
  1341. /* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that dy is 12-bit signed !)*/
  1342. #ifdef MRV_ISP_GAMMA_B_Y
  1343. #endif /* MRV_ISP_GAMMA_B_Y */
  1344. /*****************************************************************************/
  1345. /* ISP Auto White Balance Registers */
  1346. /*****************************************************************************/
  1347. /*****************************************************************************/
  1348. /**
  1349. * register: isp_awb_prop: Auto white balance properties (0x0110)
  1350. *
  1351. *****************************************************************************/
  1352. /* Slice: AWB_MEAS_MODE:*/
  1353. /* 1: RGB based measurement mode */
  1354. /* 0: near white discrimination mode using YCbCr color space */
  1355. #ifdef MRV_ISP_AWB_MEAS_MODE
  1356. #define MRV_ISP_AWB_MEAS_MODE_RGB 1U /* 1: RGB based measurement mode */
  1357. #define MRV_ISP_AWB_MEAS_MODE_YCBCR 0U /* 0: near white discrimination mode using YCbCr color space */
  1358. #endif /* MRV_ISP_AWB_MEAS_MODE */
  1359. /* Slice: AWB_MAX_EN:*/
  1360. /* 1: enable Y_MAX compare */
  1361. /* 0: disable Y_MAX compare */
  1362. /* ignored if RGB measurement mode is enabled */
  1363. #ifdef MRV_ISP_AWB_MAX_EN
  1364. #define MRV_ISP_AWB_MAX_EN_ENABLE 1U /* 1: enable Y_MAX compare */
  1365. #define MRV_ISP_AWB_MAX_EN_DISABLE 0U /* 0: disable Y_MAX compare */
  1366. #endif /* MRV_ISP_AWB_MAX_EN */
  1367. /* Slice: AWB_MODE:*/
  1368. /* AWB_MODE(1:0):*/
  1369. /* 11: reserved */
  1370. /* 10: white balance measurement of YCbCr means */
  1371. /* 01: reserved */
  1372. /* 00: manual white balance (gain adjust possible), no measurement */
  1373. #ifdef MRV_ISP_AWB_MODE
  1374. #define MRV_ISP_AWB_MODE_MEAS 2U /* 10: white balance measurement of YCbCr or RGB means (dependent on MRV_ISP_AWB_MEAS_MODE) */
  1375. #define MRV_ISP_AWB_MODE_NOMEAS 0U /* 00: manual white balance (gain adjust possible), no measurement */
  1376. #endif /* MRV_ISP_AWB_MODE */
  1377. /*****************************************************************************/
  1378. /**
  1379. * register: isp_awb_h_offs: Auto white balance horizontal offset of measure
  1380. * window (0x0114)
  1381. *
  1382. *****************************************************************************/
  1383. /* Slice: AWB_H_OFFS:*/
  1384. /* horizontal window offset in pixel */
  1385. #ifdef MRV_ISP_AWB_H_OFFS
  1386. #define MRV_ISP_AWB_H_OFFS_MIN 0U
  1387. #define MRV_ISP_AWB_H_OFFS_MAX (MRV_ISP_AWB_H_OFFS_MASK >> MRV_ISP_AWB_H_OFFS_SHIFT)
  1388. #endif /* MRV_ISP_AWB_H_OFFS */
  1389. /*****************************************************************************/
  1390. /**
  1391. * register: isp_awb_v_offs: Auto white balance vertical offset of measure
  1392. * window (0x0118)
  1393. *
  1394. *****************************************************************************/
  1395. /* Slice: AWB_V_OFFS:*/
  1396. /* vertical window offset in lines */
  1397. #ifdef MRV_ISP_AWB_V_OFFS
  1398. #define MRV_ISP_AWB_V_OFFS_MIN 0U
  1399. #define MRV_ISP_AWB_V_OFFS_MAX (MRV_ISP_AWB_V_OFFS_MASK >> MRV_ISP_AWB_V_OFFS_SHIFT)
  1400. #endif /* MRV_ISP_AWB_V_OFFS */
  1401. /*****************************************************************************/
  1402. /**
  1403. * register: isp_awb_h_size: Auto white balance horizontal window size (0x011c)
  1404. *
  1405. *****************************************************************************/
  1406. /* Slice: AWB_H_SIZE:*/
  1407. /* horizontal measurement window size in pixel */
  1408. #ifdef MRV_ISP_AWB_H_SIZE
  1409. #define MRV_ISP_AWB_H_SIZE_MIN 0U
  1410. #define MRV_ISP_AWB_H_SIZE_MAX (MRV_ISP_AWB_H_SIZE_MASK >> MRV_ISP_AWB_H_SIZE_SHIFT)
  1411. #endif /* MRV_ISP_AWB_H_SIZE */
  1412. /*****************************************************************************/
  1413. /**
  1414. * register: isp_awb_v_size: Auto white balance vertical window size (0x0120)
  1415. *
  1416. *****************************************************************************/
  1417. /* Slice: AWB_V_SIZE:*/
  1418. /* vertical measurement window size in lines */
  1419. #ifdef MRV_ISP_AWB_V_SIZE
  1420. #define MRV_ISP_AWB_V_SIZE_MIN 0U
  1421. #define MRV_ISP_AWB_V_SIZE_MAX (MRV_ISP_AWB_V_SIZE_MASK >> MRV_ISP_AWB_V_SIZE_SHIFT)
  1422. #endif /* MRV_ISP_AWB_V_SIZE */
  1423. /*****************************************************************************/
  1424. /**
  1425. * register: isp_awb_frames: Auto white balance mean value over multiple frames (0x0124)
  1426. *
  1427. *****************************************************************************/
  1428. /* Slice: AWB_FRAMES:*/
  1429. /* number of frames-1 used for mean value calculation (value of 0 means 1 frame, value of 7 means 8 frames)*/
  1430. #ifdef MRV_ISP_AWB_FRAMES
  1431. #endif /* MRV_ISP_AWB_FRAMES */
  1432. /*****************************************************************************/
  1433. /**
  1434. * register: isp_awb_ref: Auto white balance reference Cb/Cr values (0x0128)
  1435. * or maximum red/blue values
  1436. *
  1437. *****************************************************************************/
  1438. /* Slice: AWB_REF_CR__MAX_R:*/
  1439. /* - reference Cr value for AWB regulation, target for AWB */
  1440. /* - maximum red value, if RGB measurement mode is selected */
  1441. #ifdef MRV_ISP_AWB_REF_CR__MAX_R
  1442. #endif /* MRV_ISP_AWB_REF_CR__MAX_R */
  1443. /* Slice: AWB_REF_CB__MAX_B:*/
  1444. /* - reference Cb value for AWB regulation, target for AWB */
  1445. /* - maximum blue value, if RGB measurement mode is selected */
  1446. #ifdef MRV_ISP_AWB_REF_CB__MAX_B
  1447. #endif /* MRV_ISP_AWB_REF_CB__MAX_B */
  1448. /*****************************************************************************/
  1449. /**
  1450. * register: isp_awb_thresh: Auto white balance threshold values (0x012c)
  1451. *
  1452. *****************************************************************************/
  1453. /* Slice: AWB_MAX_Y:*/
  1454. /* - Luminance maximum value, only consider pixels with luminance smaller than threshold for the WB measurement (must be enabled by AWB_MODE(2)),*/
  1455. /* - ignored if RGB measurement mode is enabled */
  1456. #ifdef MRV_ISP_AWB_MAX_Y
  1457. #endif /* MRV_ISP_AWB_MAX_Y */
  1458. /* Slice: AWB_MIN_Y__MAX_G:*/
  1459. /* - Luminance minimum value, only consider pixels with luminance greater than threshold for the WB measurement */
  1460. /* - maximum green value, if RGB measurement mode is selected */
  1461. #ifdef MRV_ISP_AWB_MIN_Y__MAX_G
  1462. #endif /* MRV_ISP_AWB_MIN_Y__MAX_G */
  1463. /* Slice: AWB_MAX_CSUM:*/
  1464. /* - Chrominance sum maximum value, only consider pixels with Cb+Cr smaller than threshold for WB measurements */
  1465. /* - ignored if RGB measurement mode is enabled */
  1466. #ifdef MRV_ISP_AWB_MAX_CSUM
  1467. #endif /* MRV_ISP_AWB_MAX_CSUM */
  1468. /* Slice: AWB_MIN_C:*/
  1469. /* - Chrominance minimum value, only consider pixels with Cb/Cr each greater than threshold value for WB measurements */
  1470. /* - ignored if RGB measurement mode is enabled */
  1471. #ifdef MRV_ISP_AWB_MIN_C
  1472. #endif /* MRV_ISP_AWB_MIN_C */
  1473. /*****************************************************************************/
  1474. /**
  1475. * register: isp_awb_gain_g: Auto white balance gain green (0x0138)
  1476. *
  1477. *****************************************************************************/
  1478. /* Slice: AWB_GAIN_GR:*/
  1479. /* gain value for green component in red line 100h = 1 */
  1480. #ifdef MRV_ISP_AWB_GAIN_GR
  1481. #define MRV_ISP_AWB_GAIN_GR_DEFAULT (0x100U)
  1482. #define MRV_ISP_AWB_GAIN_GR_MAX (MRV_ISP_AWB_GAIN_GR_MASK >> MRV_ISP_AWB_GAIN_GR_SHIFT)
  1483. #endif /* MRV_ISP_AWB_GAIN_GR */
  1484. /* Slice: AWB_GAIN_GB:*/
  1485. /* gain value for green component in blue line 100h = 1 */
  1486. #ifdef MRV_ISP_AWB_GAIN_GB
  1487. #define MRV_ISP_AWB_GAIN_GB_DEFAULT (0x100U)
  1488. #define MRV_ISP_AWB_GAIN_GB_MAX (MRV_ISP_AWB_GAIN_GB_MASK >> MRV_ISP_AWB_GAIN_GB_SHIFT)
  1489. #endif /* MRV_ISP_AWB_GAIN_GB */
  1490. /*****************************************************************************/
  1491. /**
  1492. * register: isp_awb_gain_rb: Auto white balance gain red and blue (0x013c)
  1493. *
  1494. *****************************************************************************/
  1495. /* Slice: AWB_GAIN_R:*/
  1496. /* gain value for red component 100h = 1 */
  1497. #ifdef MRV_ISP_AWB_GAIN_R
  1498. #define MRV_ISP_AWB_GAIN_R_DEFAULT (0x100U)
  1499. #define MRV_ISP_AWB_GAIN_R_MAX (MRV_ISP_AWB_GAIN_R_MASK >> MRV_ISP_AWB_GAIN_R_SHIFT)
  1500. #endif /* MRV_ISP_AWB_GAIN_R */
  1501. /* Slice: AWB_GAIN_B:*/
  1502. /* gain value for blue component 100h = 1 */
  1503. #ifdef MRV_ISP_AWB_GAIN_B
  1504. #define MRV_ISP_AWB_GAIN_B_DEFAULT (0x100U)
  1505. #define MRV_ISP_AWB_GAIN_B_MAX (MRV_ISP_AWB_GAIN_B_MASK >> MRV_ISP_AWB_GAIN_B_SHIFT)
  1506. #endif /* MRV_ISP_AWB_GAIN_B */
  1507. /*****************************************************************************/
  1508. /**
  1509. * register: isp_awb_white_cnt: Auto white balance white pixel count (0x0140)
  1510. *
  1511. *****************************************************************************/
  1512. /* Slice: AWB_WHITE_CNT:*/
  1513. /* White pixel count, number of "white pixels" found during last measurement, i.e. pixels included in mean value calculation */
  1514. #ifdef MRV_ISP_AWB_WHITE_CNT
  1515. #endif /* MRV_ISP_AWB_WHITE_CNT */
  1516. /*****************************************************************************/
  1517. /**
  1518. * register: isp_awb_mean: Auto white balance measured mean value (0x0144)
  1519. *
  1520. *****************************************************************************/
  1521. /* Slice: AWB_MEAN_Y_G:*/
  1522. /* - mean value of Y within window and frames */
  1523. /* - mean value of green within window and frames if RGB measurement is enabled */
  1524. #ifdef MRV_ISP_AWB_MEAN_Y__G
  1525. #endif /* MRV_ISP_AWB_MEAN_Y__G */
  1526. /* Slice: AWB_MEAN_CB_B:*/
  1527. /* - mean value of Cb within window and frames */
  1528. /* - mean value of blue within window and frames if RGB measurement is enabled */
  1529. #ifdef MRV_ISP_AWB_MEAN_CB__B
  1530. #endif /* MRV_ISP_AWB_MEAN_CB__B */
  1531. /* Slice: AWB_MEAN_CR_R:*/
  1532. /* - mean value of Cr within window and frames */
  1533. /* - mean value of red within window and frames if RGB measurement is enabled */
  1534. #ifdef MRV_ISP_AWB_MEAN_CR__R
  1535. #endif /* MRV_ISP_AWB_MEAN_CR__R */
  1536. /*****************************************************************************/
  1537. /**
  1538. * register: isp_cc_coeff_0: Color conversion coefficient 0 (0x0170)
  1539. *
  1540. *****************************************************************************/
  1541. /* Slice: cc_coeff_0:*/
  1542. /* coefficient 0 for color space conversion */
  1543. #ifdef MRV_ISP_CC_COEFF_0
  1544. #endif /* MRV_ISP_CC_COEFF_0 */
  1545. /*****************************************************************************/
  1546. /**
  1547. * register: isp_cc_coeff_1: Color conversion coefficient 1 (0x0174)
  1548. *
  1549. *****************************************************************************/
  1550. /* Slice: cc_coeff_1:*/
  1551. /* coefficient 1 for color space conversion */
  1552. #ifdef MRV_ISP_CC_COEFF_1
  1553. #endif /* MRV_ISP_CC_COEFF_1 */
  1554. /*****************************************************************************/
  1555. /**
  1556. * register: isp_cc_coeff_2: Color conversion coefficient 2 (0x0178)
  1557. *
  1558. *****************************************************************************/
  1559. /* Slice: cc_coeff_2:*/
  1560. /* coefficient 2 for color space conversion */
  1561. #ifdef MRV_ISP_CC_COEFF_2
  1562. #endif /* MRV_ISP_CC_COEFF_2 */
  1563. /*****************************************************************************/
  1564. /**
  1565. * register: isp_cc_coeff_3: Color conversion coefficient 3 (0x017c)
  1566. *
  1567. *****************************************************************************/
  1568. /* Slice: cc_coeff_3:*/
  1569. /* coefficient 3 for color space conversion */
  1570. #ifdef MRV_ISP_CC_COEFF_3
  1571. #endif /* MRV_ISP_CC_COEFF_3 */
  1572. /*****************************************************************************/
  1573. /**
  1574. * register: isp_cc_coeff_4: Color conversion coefficient 4 (0x0180)
  1575. *
  1576. *****************************************************************************/
  1577. /* Slice: cc_coeff_4:*/
  1578. /* coefficient 4 for color space conversion */
  1579. #ifdef MRV_ISP_CC_COEFF_4
  1580. #endif /* MRV_ISP_CC_COEFF_4 */
  1581. /*****************************************************************************/
  1582. /**
  1583. * register: isp_cc_coeff_5: Color conversion coefficient 5 (0x0184)
  1584. *
  1585. *****************************************************************************/
  1586. /* Slice: cc_coeff_5:*/
  1587. /* coefficient 5 for color space conversion */
  1588. #ifdef MRV_ISP_CC_COEFF_5
  1589. #endif /* MRV_ISP_CC_COEFF_5 */
  1590. /*****************************************************************************/
  1591. /**
  1592. * register: isp_cc_coeff_6: Color conversion coefficient 6 (0x0188)
  1593. *
  1594. *****************************************************************************/
  1595. /* Slice: cc_coeff_6:*/
  1596. /* coefficient 6 for color space conversion */
  1597. #ifdef MRV_ISP_CC_COEFF_6
  1598. #endif /* MRV_ISP_CC_COEFF_6 */
  1599. /*****************************************************************************/
  1600. /**
  1601. * register: isp_cc_coeff_7: Color conversion coefficient 7 (0x018c)
  1602. *
  1603. *****************************************************************************/
  1604. /* Slice: cc_coeff_7:*/
  1605. /* coefficient 7 for color space conversion */
  1606. #ifdef MRV_ISP_CC_COEFF_7
  1607. #endif /* MRV_ISP_CC_COEFF_7 */
  1608. /*****************************************************************************/
  1609. /**
  1610. * register: isp_cc_coeff_8: Color conversion coefficient 8 (0x0190)
  1611. *
  1612. *****************************************************************************/
  1613. /* Slice: cc_coeff_8:*/
  1614. /* coefficient 8 for color space conversion */
  1615. #ifdef MRV_ISP_CC_COEFF_8
  1616. #endif /* MRV_ISP_CC_COEFF_8 */
  1617. /*****************************************************************************/
  1618. /**
  1619. * register: isp_out_h_offs: Horizontal offset of output window (0x0194)
  1620. *
  1621. *****************************************************************************/
  1622. /* Slice: ISP_OUT_H_OFFS:*/
  1623. /* vertical pic offset in lines */
  1624. #ifdef MRV_ISP_ISP_OUT_H_OFFS
  1625. #endif /* MRV_ISP_ISP_OUT_H_OFFS */
  1626. /*****************************************************************************/
  1627. /**
  1628. * register: isp_out_v_offs: Vertical offset of output window (0x0198)
  1629. *
  1630. *****************************************************************************/
  1631. /* Slice: ISP_OUT_V_OFFS:*/
  1632. /* vertical pic offset in lines */
  1633. #ifdef MRV_ISP_ISP_OUT_V_OFFS
  1634. #endif /* MRV_ISP_ISP_OUT_V_OFFS */
  1635. /*****************************************************************************/
  1636. /**
  1637. * register: isp_out_h_size: Output horizontal picture size (0x019c)
  1638. *
  1639. *****************************************************************************/
  1640. /* Slice: ISP_OUT_H_SIZE:*/
  1641. /* horizontal picture size in pixel */
  1642. /* if ISP_MODE is set to */
  1643. /* 001: (ITU-R BT.656 YUV),*/
  1644. /* 010: (ITU-R BT.601 YUV),*/
  1645. /* 011: (ITU-R BT.601 Bayer RGB),*/
  1646. /* 101: (ITU-R BT.656 Bayer RGB)*/
  1647. /* only even numbers are accepted, because complete quadruples of YUYV(YCbYCr)*/
  1648. /* are needed for the 422 output. (if an odd size is programmed the value will */
  1649. /* be truncated to an even size)*/
  1650. #ifdef MRV_ISP_ISP_OUT_H_SIZE
  1651. #define MRV_ISP_ISP_OUT_H_SIZE_IS_EVEN(x) (!(x & 0x01U)) /* check is even value */
  1652. #define MRV_ISP_ISP_OUT_H_SIZE_IS_ODD(x) (x & 0x01U) /* check is odd value */
  1653. #endif /* MRV_ISP_ISP_OUT_H_SIZE */
  1654. /*****************************************************************************/
  1655. /**
  1656. * register: isp_out_v_size: Output vertical picture size (0x01a0)
  1657. *
  1658. *****************************************************************************/
  1659. /* Slice: ISP_OUT_V_SIZE:*/
  1660. /* vertical pic size in lines */
  1661. #ifdef MRV_ISP_ISP_OUT_V_SIZE
  1662. #endif /* MRV_ISP_ISP_OUT_V_SIZE */
  1663. /*****************************************************************************/
  1664. /**
  1665. * register: isp_demosaic: Demosaic parameters (0x000001a4)
  1666. *
  1667. *****************************************************************************/
  1668. /* Slice: DEMOSAIC_BYPASS:*/
  1669. /* 0: normal operation for RGB Bayer Pattern input */
  1670. /* 1: demosaicing bypass for Black&White input data */
  1671. #ifdef MRV_ISP_DEMOSAIC_BYPASS
  1672. #define MRV_ISP_DEMOSAIC_MODE_STD 0 /* "0": standard */
  1673. #define MRV_ISP_DEMOSAIC_MODE_ENH 1 /* "1": enhanced mode */
  1674. #endif /* MRV_ISP_DEMOSAIC_BYPASS */
  1675. /* Slice: DEMOSAIC_TH:*/
  1676. /* Threshold for Bayer demosaicing texture detection. This value shifted left */
  1677. /* 4bit is compared with the difference of the vertical and horizontal 12Bit */
  1678. /* wide texture indicators, to decide if the vertical or horizontal texture */
  1679. /* flag must be set.*/
  1680. /* 0xFF: no texture detection */
  1681. /* 0x00: maximum edge sensitivity */
  1682. #ifdef MRV_ISP_DEMOSAIC_TH
  1683. #define MRV_ISP_DEMOSAIC_TH_MAX_TEXTURE_DETECTION 0xFFU /* 0xFF: no texture detection */
  1684. #define MRV_ISP_DEMOSAIC_TH_MAX_EDGE_SENSITIVITY 0x00U /* 0x00: maximum edge sensitivity */
  1685. #endif /* MRV_ISP_DEMOSAIC_TH */
  1686. /*****************************************************************************/
  1687. /**
  1688. * register: isp_flags_shd: Flags (current status) of certain signals and
  1689. * Shadow regs for enable signals (0x000001a8)
  1690. *
  1691. *****************************************************************************/
  1692. /* Slice: S_HSYNC:*/
  1693. /* state of ISP input port s_hsync, for test purposes */
  1694. #ifdef MRV_ISP_S_HSYNC
  1695. #endif /* MRV_ISP_S_HSYNC */
  1696. /* Slice: S_VSYNC:*/
  1697. /* state of ISP input port s_vsync, for test purposes */
  1698. #ifdef MRV_ISP_S_VSYNC
  1699. #endif /* MRV_ISP_S_VSYNC */
  1700. /* Slice: S_DATA:*/
  1701. /* state of ISP input port s_data, for test purposes */
  1702. #ifdef MRV_ISP_S_DATA
  1703. #endif /* MRV_ISP_S_DATA */
  1704. /* Slice: INFORM_FIELD:*/
  1705. /* current field information */
  1706. /* 0: odd */
  1707. /* 1: even */
  1708. #ifdef MRV_ISP_INFORM_FIELD
  1709. #define MRV_ISP_INFORM_FIELD_ODD 0 /* 0: odd field is sampled */
  1710. #define MRV_ISP_INFORM_FIELD_EVEN 1 /* 1: even field is sampled */
  1711. #endif /* MRV_ISP_INFORM_FIELD */
  1712. /* Slice: INFORM_EN_SHD:*/
  1713. /* Input formatter enable shadow register */
  1714. #ifdef MRV_ISP_INFORM_EN_SHD
  1715. #endif /* MRV_ISP_INFORM_EN_SHD */
  1716. /* Slice: ISP_ENABLE_SHD:*/
  1717. /* ISP enable shadow register */
  1718. /* shows, if ISP currently outputs data (1) or not (0)*/
  1719. #ifdef MRV_ISP_ISP_ENABLE_SHD
  1720. #endif /* MRV_ISP_ISP_ENABLE_SHD */
  1721. /*****************************************************************************/
  1722. /**
  1723. * register: isp_out_h_offs_shd: current horizontal offset of output window
  1724. * (shadow register) (0x000001ac)
  1725. *
  1726. *****************************************************************************/
  1727. /* Slice: ISP_OUT_H_OFFS_SHD:*/
  1728. /* current vertical pic offset in lines */
  1729. #ifdef MRV_ISP_ISP_OUT_H_OFFS_SHD
  1730. #endif /* MRV_ISP_ISP_OUT_H_OFFS_SHD */
  1731. /*****************************************************************************/
  1732. /**
  1733. * register: isp_out_v_offs_shd: current vertical offset of output window
  1734. * (shadow register) (0x000001b0)
  1735. *
  1736. *****************************************************************************/
  1737. /* Slice: ISP_OUT_V_OFFS_SHD:*/
  1738. /* current vertical pic offset in lines */
  1739. #ifdef MRV_ISP_ISP_OUT_V_OFFS_SHD
  1740. #endif /* MRV_ISP_ISP_OUT_V_OFFS_SHD */
  1741. /*****************************************************************************/
  1742. /**
  1743. * register: isp_out_h_size_shd: current output horizontal picture size
  1744. * (shadow register) (0x000001b4)
  1745. *
  1746. *****************************************************************************/
  1747. /* Slice: ISP_OUT_H_SIZE_SHD:*/
  1748. /* current horizontal pic size in pixel */
  1749. #ifdef MRV_ISP_ISP_OUT_H_SIZE_SHD
  1750. #endif /* MRV_ISP_ISP_OUT_H_SIZE_SHD */
  1751. /*****************************************************************************/
  1752. /**
  1753. * register: isp_out_v_size_shd: current output vertical picture size
  1754. * (shadow register) (0x000001b8)
  1755. *
  1756. *****************************************************************************/
  1757. /* Slice: ISP_OUT_V_SIZE_SHD:*/
  1758. /* vertical pic size in lines */
  1759. #ifdef MRV_ISP_ISP_OUT_V_SIZE_SHD
  1760. #endif /* MRV_ISP_ISP_OUT_V_SIZE_SHD */
  1761. /*****************************************************************************/
  1762. /**
  1763. * register: isp_imsc: Interrupt mask (0x000001bc)
  1764. *
  1765. *****************************************************************************/
  1766. /*! Slice: IMSC_VSM_END:*/
  1767. /*! enable interrupt (1) or mask out (0)*/
  1768. #ifndef MRV_ISP_IMSC_VSM_END
  1769. #define MRV_ISP_IMSC_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1770. #endif /* !MRV_ISP_IMSC_VSM_END */
  1771. /* Slice: IMSC_EXP_END:*/
  1772. /* enable interrupt (1) or mask out (0)*/
  1773. #ifndef MRV_ISP_IMSC_EXP_END
  1774. #define MRV_ISP_IMSC_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1775. #endif /* !MRV_ISP_IMSC_EXP_END */
  1776. /* Slice: IMSC_FLASH_CAP:*/
  1777. /* enable interrupt (1) or mask out (0)*/
  1778. #ifndef MRV_ISP_IMSC_FLASH_CAP
  1779. #define MRV_ISP_IMSC_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1780. #endif /* !MRV_ISP_IMSC_FLASH_CAP */
  1781. /* Slice: IMSC_BP_DET:*/
  1782. /* enable interrupt (1) or mask out (0)*/
  1783. #ifndef MRV_ISP_IMSC_BP_DET
  1784. #define MRV_ISP_IMSC_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1785. #endif /* !MRV_ISP_IMSC_BP_DET */
  1786. /* Slice: IMSC_HIST_MEASURE_RDY:*/
  1787. /* enable interrupt (1) or mask out (0)*/
  1788. #ifndef MRV_ISP_IMSC_HIST_MEASURE_RDY
  1789. #define MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1790. #endif /* !MRV_ISP_IMSC_HIST_MEASURE_RDY */
  1791. /* Slice: IMSC_AFM_FIN:*/
  1792. /* enable interrupt (1) or mask out (0)*/
  1793. #ifndef MRV_ISP_IMSC_AFM_FIN
  1794. #define MRV_ISP_IMSC_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1795. #endif /* !IMSC_AFM_FIN */
  1796. /* Slice: IMSC_AFM_LUM_OF:*/
  1797. /* enable interrupt (1) or mask out (0)*/
  1798. #ifndef MRV_ISP_IMSC_AFM_LUM_OF
  1799. #define MRV_ISP_IMSC_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1800. #endif /* !MRV_ISP_IMSC_AFM_LUM_OF */
  1801. /* Slice: IMSC_AFM_SUM_OF:*/
  1802. /* enable interrupt (1) or mask out (0)*/
  1803. #ifndef MRV_ISP_IMSC_AFM_SUM_OF
  1804. #define MRV_ISP_IMSC_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1805. #endif /* !MRV_ISP_IMSC_AFM_SUM_OF */
  1806. /* Slice: IMSC_SHUTTER_OFF:*/
  1807. /* enable interrupt (1) or mask out (0)*/
  1808. #ifndef MRV_ISP_IMSC_SHUTTER_OFF
  1809. #define MRV_ISP_IMSC_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1810. #endif /* !MRV_ISP_IMSC_SHUTTER_OFF */
  1811. /* Slice: IMSC_SHUTTER_ON:*/
  1812. /* enable interrupt (1) or mask out (0)*/
  1813. #ifndef MRV_ISP_IMSC_SHUTTER_ON
  1814. #define MRV_ISP_IMSC_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1815. #endif /* !MRV_ISP_IMSC_SHUTTER_ON */
  1816. /* Slice: IMSC_FLASH_OFF:*/
  1817. /* enable interrupt (1) or mask out (0)*/
  1818. #ifndef MRV_ISP_IMSC_FLASH_OFF
  1819. #define MRV_ISP_IMSC_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1820. #endif /* !MRV_ISP_IMSC_FLASH_OFF */
  1821. /* Slice: IMSC_FLASH_ON:*/
  1822. /* enable interrupt (1) or mask out (0)*/
  1823. #ifndef MRV_ISP_IMSC_FLASH_ON
  1824. #define MRV_ISP_IMSC_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1825. #endif /* !MRV_ISP_IMSC_FLASH_ON */
  1826. /* Slice: IMSC_H_START:*/
  1827. /* enable interrupt (1) or mask out (0)*/
  1828. #ifndef MRV_ISP_IMSC_H_START
  1829. #define MRV_ISP_IMSC_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1830. #endif /* !MRV_ISP_IMSC_H_START */
  1831. /* Slice: IMSC_V_START:*/
  1832. /* enable interrupt (1) or mask out (0)*/
  1833. #ifndef MRV_ISP_IMSC_V_START
  1834. #define MRV_ISP_IMSC_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1835. #endif /* !MRV_ISP_IMSC_V_START */
  1836. /* Slice: IMSC_FRAME_IN:*/
  1837. /* enable interrupt (1) or mask out (0)*/
  1838. #ifndef MRV_ISP_IMSC_FRAME_IN
  1839. #define MRV_ISP_IMSC_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1840. #endif /* !MRV_ISP_IMSC_FRAME_IN */
  1841. /* Slice: IMSC_AWB_DONE:*/
  1842. /* enable interrupt (1) or mask out (0)*/
  1843. #ifndef MRV_ISP_IMSC_AWB_DONE
  1844. #define MRV_ISP_IMSC_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1845. #endif /* !MRV_ISP_IMSC_AWB_DONE */
  1846. /* Slice: IMSC_PIC_SIZE_ERR:*/
  1847. /* enable interrupt (1) or mask out (0)*/
  1848. #ifndef MRV_ISP_IMSC_PIC_SIZE_ERR
  1849. #define MRV_ISP_IMSC_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1850. #endif /* !MRV_ISP_IMSC_PIC_SIZE_ERR */
  1851. /* Slice: IMSC_DATA_LOSS:*/
  1852. /* enable interrupt (1) or mask out (0)*/
  1853. #ifndef MRV_ISP_IMSC_DATA_LOSS
  1854. #define MRV_ISP_IMSC_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1855. #endif /* !MRV_ISP_IMSC_DATA_LOSS */
  1856. /* Slice: IMSC_FRAME:*/
  1857. /* enable interrupt (1) or mask out (0)*/
  1858. #ifndef MRV_ISP_IMSC_FRAME
  1859. #define MRV_ISP_IMSC_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1860. #endif /* !MRV_ISP_IMSC_FRAME */
  1861. /* Slice: IMSC_ISP_OFF:*/
  1862. /* enable interrupt (1) or mask out (0)*/
  1863. #ifndef MRV_ISP_IMSC_ISP_OFF
  1864. #define MRV_ISP_IMSC_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1865. #endif /* !MRV_ISP_IMSC_ISP_OFF */
  1866. /* combination of all interrupt lines */
  1867. #define MRV_ISP_IMSC_ALL_IRQS
  1868. #define MRV_ISP_IMSC_ALL_IRQS_MASK \
  1869. (0 \
  1870. | MRV_ISP_IMSC_VSM_END_MASK \
  1871. | MRV_ISP_IMSC_EXP_END_MASK \
  1872. | MRV_ISP_IMSC_FLASH_CAP_MASK \
  1873. | MRV_ISP_IMSC_BP_DET_MASK \
  1874. | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK \
  1875. | MRV_ISP_IMSC_AFM_FIN_MASK \
  1876. | MRV_ISP_IMSC_AFM_LUM_OF_MASK \
  1877. | MRV_ISP_IMSC_AFM_SUM_OF_MASK \
  1878. | MRV_ISP_IMSC_SHUTTER_OFF_MASK \
  1879. | MRV_ISP_IMSC_SHUTTER_ON_MASK \
  1880. | MRV_ISP_IMSC_FLASH_OFF_MASK \
  1881. | MRV_ISP_IMSC_FLASH_ON_MASK \
  1882. | MRV_ISP_IMSC_H_START_MASK \
  1883. | MRV_ISP_IMSC_V_START_MASK \
  1884. | MRV_ISP_IMSC_FRAME_IN_MASK \
  1885. | MRV_ISP_IMSC_AWB_DONE_MASK \
  1886. | MRV_ISP_IMSC_PIC_SIZE_ERR_MASK \
  1887. | MRV_ISP_IMSC_DATA_LOSS_MASK \
  1888. | MRV_ISP_IMSC_FRAME_MASK \
  1889. | MRV_ISP_IMSC_ISP_OFF_MASK \
  1890. )
  1891. #define MRV_ISP_IMSC_ALL_IRQS_SHIFT 0U
  1892. /*****************************************************************************/
  1893. /**
  1894. * register: isp_ris: Raw interrupt status (0x000001c0)
  1895. *
  1896. *****************************************************************************/
  1897. /*! Slice: RIS_VSM_END:*/
  1898. /*! VSM measurement complete */
  1899. #ifndef MRV_ISP_RIS_VSM_END
  1900. #define MRV_ISP_RIS_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1901. #endif /* !MRV_ISP_RIS_VSM_END */
  1902. /* Slice: RIS_EXP_END:*/
  1903. /* enable interrupt (1) or mask out (0)*/
  1904. #ifndef MRV_ISP_RIS_EXP_END
  1905. #define MRV_ISP_RIS_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1906. #endif /* !MRV_ISP_RIS_EXP_END */
  1907. /* Slice: RIS_FLASH_CAP:*/
  1908. /* enable interrupt (1) or mask out (0)*/
  1909. #ifndef MRV_ISP_RIS_FLASH_CAP
  1910. #define MRV_ISP_RIS_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1911. #endif /* !MRV_ISP_RIS_FLASH_CAP */
  1912. /* Slice: RIS_BP_DET:*/
  1913. /* enable interrupt (1) or mask out (0)*/
  1914. #ifndef MRV_ISP_RIS_BP_DET
  1915. #define MRV_ISP_RIS_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1916. #endif /* !MRV_ISP_RIS_BP_DET */
  1917. /* Slice: RIS_HIST_MEASURE_RDY:*/
  1918. /* enable interrupt (1) or mask out (0)*/
  1919. #ifndef MRV_ISP_RIS_HIST_MEASURE_RDY
  1920. #define MRV_ISP_RIS_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1921. #endif /* !MRV_ISP_RIS_HIST_MEASURE_RDY */
  1922. /* Slice: RIS_AFM_FIN:*/
  1923. /* enable interrupt (1) or mask out (0)*/
  1924. #ifndef MRV_ISP_RIS_AFM_FIN
  1925. #define MRV_ISP_RIS_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1926. #endif /* !RIS_AFM_FIN */
  1927. /* Slice: RIS_AFM_LUM_OF:*/
  1928. /* enable interrupt (1) or mask out (0)*/
  1929. #ifndef MRV_ISP_RIS_AFM_LUM_OF
  1930. #define MRV_ISP_RIS_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1931. #endif /* !MRV_ISP_RIS_AFM_LUM_OF */
  1932. /* Slice: RIS_AFM_SUM_OF:*/
  1933. /* enable interrupt (1) or mask out (0)*/
  1934. #ifndef MRV_ISP_RIS_AFM_SUM_OF
  1935. #define MRV_ISP_RIS_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1936. #endif /* !MRV_ISP_RIS_AFM_SUM_OF */
  1937. /* Slice: RIS_SHUTTER_OFF:*/
  1938. /* enable interrupt (1) or mask out (0)*/
  1939. #ifndef MRV_ISP_RIS_SHUTTER_OFF
  1940. #define MRV_ISP_RIS_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1941. #endif /* !MRV_ISP_RIS_SHUTTER_OFF */
  1942. /* Slice: RIS_SHUTTER_ON:*/
  1943. /* enable interrupt (1) or mask out (0)*/
  1944. #ifndef MRV_ISP_RIS_SHUTTER_ON
  1945. #define MRV_ISP_RIS_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1946. #endif /* !MRV_ISP_RIS_SHUTTER_ON */
  1947. /* Slice: RIS_FLASH_OFF:*/
  1948. /* enable interrupt (1) or mask out (0)*/
  1949. #ifndef MRV_ISP_RIS_FLASH_OFF
  1950. #define MRV_ISP_RIS_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1951. #endif /* !MRV_ISP_RIS_FLASH_OFF */
  1952. /* Slice: RIS_FLASH_ON:*/
  1953. /* enable interrupt (1) or mask out (0)*/
  1954. #ifndef MRV_ISP_RIS_FLASH_ON
  1955. #define MRV_ISP_RIS_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1956. #endif /* !MRV_ISP_RIS_FLASH_ON */
  1957. /* Slice: RIS_H_START:*/
  1958. /* enable interrupt (1) or mask out (0)*/
  1959. #ifndef MRV_ISP_RIS_H_START
  1960. #define MRV_ISP_RIS_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1961. #endif /* !MRV_ISP_RIS_H_START */
  1962. /* Slice: RIS_V_START:*/
  1963. /* enable interrupt (1) or mask out (0)*/
  1964. #ifndef MRV_ISP_RIS_V_START
  1965. #define MRV_ISP_RIS_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1966. #endif /* !MRV_ISP_RIS_V_START */
  1967. /* Slice: RIS_FRAME_IN:*/
  1968. /* enable interrupt (1) or mask out (0)*/
  1969. #ifndef MRV_ISP_RIS_FRAME_IN
  1970. #define MRV_ISP_RIS_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1971. #endif /* !MRV_ISP_RIS_FRAME_IN */
  1972. /* Slice: RIS_AWB_DONE:*/
  1973. /* enable interrupt (1) or mask out (0)*/
  1974. #ifndef MRV_ISP_RIS_AWB_DONE
  1975. #define MRV_ISP_RIS_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1976. #endif /* !MRV_ISP_RIS_AWB_DONE */
  1977. /* Slice: RIS_PIC_SIZE_ERR:*/
  1978. /* enable interrupt (1) or mask out (0)*/
  1979. #ifndef MRV_ISP_RIS_PIC_SIZE_ERR
  1980. #define MRV_ISP_RIS_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1981. #endif /* !MRV_ISP_RIS_PIC_SIZE_ERR */
  1982. /* Slice: RIS_DATA_LOSS:*/
  1983. /* enable interrupt (1) or mask out (0)*/
  1984. #ifndef MRV_ISP_RIS_DATA_LOSS
  1985. #define MRV_ISP_RIS_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1986. #endif /* !MRV_ISP_RIS_DATA_LOSS */
  1987. /* Slice: RIS_FRAME:*/
  1988. /* enable interrupt (1) or mask out (0)*/
  1989. #ifndef MRV_ISP_RIS_FRAME
  1990. #define MRV_ISP_RIS_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1991. #endif /* !MRV_ISP_RIS_FRAME */
  1992. /* Slice: RIS_ISP_OFF:*/
  1993. /* enable interrupt (1) or mask out (0)*/
  1994. #ifndef MRV_ISP_RIS_ISP_OFF
  1995. #define MRV_ISP_RIS_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1996. #endif /* !MRV_ISP_RIS_ISP_OFF */
  1997. /* combination of all interrupt lines */
  1998. #define MRV_ISP_RIS_ALL_IRQS
  1999. #define MRV_ISP_RIS_ALL_IRQS_MASK \
  2000. (0 \
  2001. | MRV_ISP_RIS_VSM_END_MASK \
  2002. | MRV_ISP_RIS_EXP_END_MASK \
  2003. | MRV_ISP_RIS_FLASH_CAP_MASK \
  2004. | MRV_ISP_RIS_BP_DET_MASK \
  2005. | MRV_ISP_RIS_HIST_MEASURE_RDY_MASK \
  2006. | MRV_ISP_RIS_AFM_FIN_MASK \
  2007. | MRV_ISP_RIS_AFM_LUM_OF_MASK \
  2008. | MRV_ISP_RIS_AFM_SUM_OF_MASK \
  2009. | MRV_ISP_RIS_SHUTTER_OFF_MASK \
  2010. | MRV_ISP_RIS_SHUTTER_ON_MASK \
  2011. | MRV_ISP_RIS_FLASH_OFF_MASK \
  2012. | MRV_ISP_RIS_FLASH_ON_MASK \
  2013. | MRV_ISP_RIS_H_START_MASK \
  2014. | MRV_ISP_RIS_V_START_MASK \
  2015. | MRV_ISP_RIS_FRAME_IN_MASK \
  2016. | MRV_ISP_RIS_AWB_DONE_MASK \
  2017. | MRV_ISP_RIS_PIC_SIZE_ERR_MASK \
  2018. | MRV_ISP_RIS_DATA_LOSS_MASK \
  2019. | MRV_ISP_RIS_FRAME_MASK \
  2020. | MRV_ISP_RIS_ISP_OFF_MASK \
  2021. )
  2022. #define MRV_ISP_RIS_ALL_IRQS_SHIFT 0U
  2023. /*****************************************************************************/
  2024. /**
  2025. * register: isp_mis: Masked interrupt status (0x000001c4)
  2026. *
  2027. *****************************************************************************/
  2028. /*! Slice: MIS_VSM_END:*/
  2029. /*! VSM measurement complete */
  2030. #ifndef MRV_ISP_MIS_VSM_END
  2031. #define MRV_ISP_MIS_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2032. #endif /* !MRV_ISP_MIS_VSM_END_MASK */
  2033. /* Slice: MIS_EXP_END:*/
  2034. /* enable interrupt (1) or mask out (0)*/
  2035. #ifndef MRV_ISP_MIS_EXP_END
  2036. #define MRV_ISP_MIS_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2037. #endif /* !MRV_ISP_MIS_EXP_END */
  2038. /* Slice: MIS_FLASH_CAP:*/
  2039. /* enable interrupt (1) or mask out (0)*/
  2040. #ifndef MRV_ISP_MIS_FLASH_CAP
  2041. #define MRV_ISP_MIS_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2042. #endif /* !MRV_ISP_MIS_FLASH_CAP */
  2043. /* Slice: MIS_BP_DET:*/
  2044. /* enable interrupt (1) or mask out (0)*/
  2045. #ifndef MRV_ISP_MIS_BP_DET
  2046. #define MRV_ISP_MIS_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2047. #endif /* !MRV_ISP_MIS_BP_DET */
  2048. /* Slice: MIS_HIST_MEASURE_RDY:*/
  2049. /* enable interrupt (1) or mask out (0)*/
  2050. #ifndef MRV_ISP_MIS_HIST_MEASURE_RDY
  2051. #define MRV_ISP_MIS_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2052. #endif /* !MRV_ISP_MIS_HIST_MEASURE_RDY */
  2053. /* Slice: MIS_AFM_FIN:*/
  2054. /* enable interrupt (1) or mask out (0)*/
  2055. #ifndef MRV_ISP_MIS_AFM_FIN
  2056. #define MRV_ISP_MIS_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2057. #endif /* !MIS_AFM_FIN */
  2058. /* Slice: MIS_AFM_LUM_OF:*/
  2059. /* enable interrupt (1) or mask out (0)*/
  2060. #ifndef MRV_ISP_MIS_AFM_LUM_OF
  2061. #define MRV_ISP_MIS_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2062. #endif /* !MRV_ISP_MIS_AFM_LUM_OF */
  2063. /* Slice: MIS_AFM_SUM_OF:*/
  2064. /* enable interrupt (1) or mask out (0)*/
  2065. #ifndef MRV_ISP_MIS_AFM_SUM_OF
  2066. #define MRV_ISP_MIS_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2067. #endif /* !MRV_ISP_MIS_AFM_SUM_OF */
  2068. /* Slice: MIS_SHUTTER_OFF:*/
  2069. /* enable interrupt (1) or mask out (0)*/
  2070. #ifndef MRV_ISP_MIS_SHUTTER_OFF
  2071. #define MRV_ISP_MIS_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2072. #endif /* !MRV_ISP_MIS_SHUTTER_OFF */
  2073. /* Slice: MIS_SHUTTER_ON:*/
  2074. /* enable interrupt (1) or mask out (0)*/
  2075. #ifndef MRV_ISP_MIS_SHUTTER_ON
  2076. #define MRV_ISP_MIS_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2077. #endif /* !MRV_ISP_MIS_SHUTTER_ON */
  2078. /* Slice: MIS_FLASH_OFF:*/
  2079. /* enable interrupt (1) or mask out (0)*/
  2080. #ifndef MRV_ISP_MIS_FLASH_OFF
  2081. #define MRV_ISP_MIS_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2082. #endif /* !MRV_ISP_MIS_FLASH_OFF */
  2083. /* Slice: MIS_FLASH_ON:*/
  2084. /* enable interrupt (1) or mask out (0)*/
  2085. #ifndef MRV_ISP_MIS_FLASH_ON
  2086. #define MRV_ISP_MIS_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2087. #endif /* !MRV_ISP_MIS_FLASH_ON */
  2088. /* Slice: MIS_H_START:*/
  2089. /* enable interrupt (1) or mask out (0)*/
  2090. #ifndef MRV_ISP_MIS_H_START
  2091. #define MRV_ISP_MIS_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2092. #endif /* !MRV_ISP_MIS_H_START */
  2093. /* Slice: MIS_V_START:*/
  2094. /* enable interrupt (1) or mask out (0)*/
  2095. #ifndef MRV_ISP_MIS_V_START
  2096. #define MRV_ISP_MIS_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2097. #endif /* !MRV_ISP_MIS_V_START */
  2098. /* Slice: MIS_FRAME_IN:*/
  2099. /* enable interrupt (1) or mask out (0)*/
  2100. #ifndef MRV_ISP_MIS_FRAME_IN
  2101. #define MRV_ISP_MIS_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2102. #endif /* !MRV_ISP_MIS_FRAME_IN */
  2103. /* Slice: MIS_AWB_DONE:*/
  2104. /* enable interrupt (1) or mask out (0)*/
  2105. #ifndef MRV_ISP_MIS_AWB_DONE
  2106. #define MRV_ISP_MIS_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2107. #endif /* !MRV_ISP_MIS_AWB_DONE */
  2108. /* Slice: MIS_PIC_SIZE_ERR:*/
  2109. /* enable interrupt (1) or mask out (0)*/
  2110. #ifndef MRV_ISP_MIS_PIC_SIZE_ERR
  2111. #define MRV_ISP_MIS_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2112. #endif /* !MRV_ISP_MIS_PIC_SIZE_ERR */
  2113. /* Slice: MIS_DATA_LOSS:*/
  2114. /* enable interrupt (1) or mask out (0)*/
  2115. #ifndef MRV_ISP_MIS_DATA_LOSS
  2116. #define MRV_ISP_MIS_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2117. #endif /* !MRV_ISP_MIS_DATA_LOSS */
  2118. /* Slice: MIS_FRAME:*/
  2119. /* enable interrupt (1) or mask out (0)*/
  2120. #ifndef MRV_ISP_MIS_FRAME
  2121. #define MRV_ISP_MIS_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2122. #endif /* !MRV_ISP_MIS_FRAME */
  2123. /* Slice: MIS_ISP_OFF:*/
  2124. /* enable interrupt (1) or mask out (0)*/
  2125. #ifndef MRV_ISP_MIS_ISP_OFF
  2126. #define MRV_ISP_MIS_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2127. #endif /* !MRV_ISP_MIS_ISP_OFF */
  2128. /* combination of all interrupt lines */
  2129. #define MRV_ISP_MIS_ALL_IRQS
  2130. #define MRV_ISP_MIS_ALL_IRQS_MASK \
  2131. (0 \
  2132. | MRV_ISP_MIS_VSM_END_MASK \
  2133. | MRV_ISP_MIS_EXP_END_MASK \
  2134. | MRV_ISP_MIS_FLASH_CAP_MASK \
  2135. | MRV_ISP_MIS_BP_DET_MASK \
  2136. | MRV_ISP_MIS_HIST_MEASURE_RDY_MASK \
  2137. | MRV_ISP_MIS_AFM_FIN_MASK \
  2138. | MRV_ISP_MIS_AFM_LUM_OF_MASK \
  2139. | MRV_ISP_MIS_AFM_SUM_OF_MASK \
  2140. | MRV_ISP_MIS_SHUTTER_OFF_MASK \
  2141. | MRV_ISP_MIS_SHUTTER_ON_MASK \
  2142. | MRV_ISP_MIS_FLASH_OFF_MASK \
  2143. | MRV_ISP_MIS_FLASH_ON_MASK \
  2144. | MRV_ISP_MIS_H_START_MASK \
  2145. | MRV_ISP_MIS_V_START_MASK \
  2146. | MRV_ISP_MIS_FRAME_IN_MASK \
  2147. | MRV_ISP_MIS_AWB_DONE_MASK \
  2148. | MRV_ISP_MIS_PIC_SIZE_ERR_MASK \
  2149. | MRV_ISP_MIS_DATA_LOSS_MASK \
  2150. | MRV_ISP_MIS_FRAME_MASK \
  2151. | MRV_ISP_MIS_ISP_OFF_MASK \
  2152. )
  2153. #define MRV_ISP_MIS_ALL_IRQS_SHIFT 0U
  2154. /*****************************************************************************/
  2155. /**
  2156. * register: isp_icr: Interrupt clear register (0x000001c8)
  2157. *
  2158. *****************************************************************************/
  2159. /*! Slice: ICR_VSM_END:*/
  2160. /*! clear interrupt */
  2161. #ifndef MRV_ISP_ICR_VSM_END
  2162. #define MRV_ISP_ICR_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2163. #endif /* !MRV_ISP_ICR_VSM_END */
  2164. /* Slice: ICR_EXP_END:*/
  2165. /* enable interrupt (1) or mask out (0)*/
  2166. #ifndef MRV_ISP_ICR_EXP_END
  2167. #define MRV_ISP_ICR_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2168. #endif /* !MRV_ISP_ICR_EXP_END */
  2169. /* Slice: ICR_FLASH_CAP:*/
  2170. /* enable interrupt (1) or mask out (0)*/
  2171. #ifndef MRV_ISP_ICR_FLASH_CAP
  2172. #define MRV_ISP_ICR_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2173. #endif /* !MRV_ISP_ICR_FLASH_CAP */
  2174. /* Slice: ICR_BP_DET:*/
  2175. /* enable interrupt (1) or mask out (0)*/
  2176. #ifndef MRV_ISP_ICR_BP_DET
  2177. #define MRV_ISP_ICR_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2178. #endif /* !MRV_ISP_ICR_BP_DET */
  2179. /* Slice: ICR_HIST_MEASURE_RDY:*/
  2180. /* enable interrupt (1) or mask out (0)*/
  2181. #ifndef MRV_ISP_ICR_HIST_MEASURE_RDY
  2182. #define MRV_ISP_ICR_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2183. #endif /* !MRV_ISP_ICR_HIST_MEASURE_RDY */
  2184. /* Slice: ICR_AFM_FIN:*/
  2185. /* enable interrupt (1) or mask out (0)*/
  2186. #ifndef MRV_ISP_ICR_AFM_FIN
  2187. #define MRV_ISP_ICR_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2188. #endif /* !ICR_AFM_FIN */
  2189. /* Slice: ICR_AFM_LUM_OF:*/
  2190. /* enable interrupt (1) or mask out (0)*/
  2191. #ifndef MRV_ISP_ICR_AFM_LUM_OF
  2192. #define MRV_ISP_ICR_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2193. #endif /* !MRV_ISP_ICR_AFM_LUM_OF */
  2194. /* Slice: ICR_AFM_SUM_OF:*/
  2195. /* enable interrupt (1) or mask out (0)*/
  2196. #ifndef MRV_ISP_ICR_AFM_SUM_OF
  2197. #define MRV_ISP_ICR_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2198. #endif /* !MRV_ISP_ICR_AFM_SUM_OF */
  2199. /* Slice: ICR_SHUTTER_OFF:*/
  2200. /* enable interrupt (1) or mask out (0)*/
  2201. #ifndef MRV_ISP_ICR_SHUTTER_OFF
  2202. #define MRV_ISP_ICR_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2203. #endif /* !MRV_ISP_ICR_SHUTTER_OFF */
  2204. /* Slice: ICR_SHUTTER_ON:*/
  2205. /* enable interrupt (1) or mask out (0)*/
  2206. #ifndef MRV_ISP_ICR_SHUTTER_ON
  2207. #define MRV_ISP_ICR_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2208. #endif /* !MRV_ISP_ICR_SHUTTER_ON */
  2209. /* Slice: ICR_FLASH_OFF:*/
  2210. /* enable interrupt (1) or mask out (0)*/
  2211. #ifndef MRV_ISP_ICR_FLASH_OFF
  2212. #define MRV_ISP_ICR_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2213. #endif /* !MRV_ISP_ICR_FLASH_OFF */
  2214. /* Slice: ICR_FLASH_ON:*/
  2215. /* enable interrupt (1) or mask out (0)*/
  2216. #ifndef MRV_ISP_ICR_FLASH_ON
  2217. #define MRV_ISP_ICR_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2218. #endif /* !MRV_ISP_ICR_FLASH_ON */
  2219. /* Slice: ICR_H_START:*/
  2220. /* enable interrupt (1) or mask out (0)*/
  2221. #ifndef MRV_ISP_ICR_H_START
  2222. #define MRV_ISP_ICR_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2223. #endif /* !MRV_ISP_ICR_H_START */
  2224. /* Slice: ICR_V_START:*/
  2225. /* enable interrupt (1) or mask out (0)*/
  2226. #ifndef MRV_ISP_ICR_V_START
  2227. #define MRV_ISP_ICR_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2228. #endif /* !MRV_ISP_ICR_V_START */
  2229. /* Slice: ICR_FRAME_IN:*/
  2230. /* enable interrupt (1) or mask out (0)*/
  2231. #ifndef MRV_ISP_ICR_FRAME_IN
  2232. #define MRV_ISP_ICR_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2233. #endif /* !MRV_ISP_ICR_FRAME_IN */
  2234. /* Slice: ICR_AWB_DONE:*/
  2235. /* enable interrupt (1) or mask out (0)*/
  2236. #ifndef MRV_ISP_ICR_AWB_DONE
  2237. #define MRV_ISP_ICR_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2238. #endif /* !MRV_ISP_ICR_AWB_DONE */
  2239. /* Slice: ICR_PIC_SIZE_ERR:*/
  2240. /* enable interrupt (1) or mask out (0)*/
  2241. #ifndef MRV_ISP_ICR_PIC_SIZE_ERR
  2242. #define MRV_ISP_ICR_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2243. #endif /* !MRV_ISP_ICR_PIC_SIZE_ERR */
  2244. /* Slice: ICR_DATA_LOSS:*/
  2245. /* enable interrupt (1) or mask out (0)*/
  2246. #ifndef MRV_ISP_ICR_DATA_LOSS
  2247. #define MRV_ISP_ICR_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2248. #endif /* !MRV_ISP_ICR_DATA_LOSS */
  2249. /* Slice: ICR_FRAME:*/
  2250. /* enable interrupt (1) or mask out (0)*/
  2251. #ifndef MRV_ISP_ICR_FRAME
  2252. #define MRV_ISP_ICR_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2253. #endif /* !MRV_ISP_ICR_FRAME */
  2254. /* Slice: ICR_ISP_OFF:*/
  2255. /* enable interrupt (1) or mask out (0)*/
  2256. #ifndef MRV_ISP_ICR_ISP_OFF
  2257. #define MRV_ISP_ICR_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2258. #endif /* !MRV_ISP_ICR_ISP_OFF */
  2259. /* combination of all interrupt lines */
  2260. #define MRV_ISP_ICR_ALL_IRQS
  2261. #define MRV_ISP_ICR_ALL_IRQS_MASK \
  2262. (0 \
  2263. | MRV_ISP_ICR_VSM_END_MASK \
  2264. | MRV_ISP_ICR_EXP_END_MASK \
  2265. | MRV_ISP_ICR_FLASH_CAP_MASK \
  2266. | MRV_ISP_ICR_BP_DET_MASK \
  2267. | MRV_ISP_ICR_HIST_MEASURE_RDY_MASK \
  2268. | MRV_ISP_ICR_AFM_FIN_MASK \
  2269. | MRV_ISP_ICR_AFM_LUM_OF_MASK \
  2270. | MRV_ISP_ICR_AFM_SUM_OF_MASK \
  2271. | MRV_ISP_ICR_SHUTTER_OFF_MASK \
  2272. | MRV_ISP_ICR_SHUTTER_ON_MASK \
  2273. | MRV_ISP_ICR_FLASH_OFF_MASK \
  2274. | MRV_ISP_ICR_FLASH_ON_MASK \
  2275. | MRV_ISP_ICR_H_START_MASK \
  2276. | MRV_ISP_ICR_V_START_MASK \
  2277. | MRV_ISP_ICR_FRAME_IN_MASK \
  2278. | MRV_ISP_ICR_AWB_DONE_MASK \
  2279. | MRV_ISP_ICR_PIC_SIZE_ERR_MASK \
  2280. | MRV_ISP_ICR_DATA_LOSS_MASK \
  2281. | MRV_ISP_ICR_FRAME_MASK \
  2282. | MRV_ISP_ICR_ISP_OFF_MASK \
  2283. )
  2284. #define MRV_ISP_ICR_ALL_IRQS_SHIFT 0U
  2285. /*****************************************************************************/
  2286. /**
  2287. * register: isp_isr: Interrupt set register (0x000001cc)
  2288. *
  2289. *****************************************************************************/
  2290. /*! Register: isp_isr: Interrupt set register (0x000001cc)*/
  2291. /*! Slice: ISR_VSM_END:*/
  2292. /*! set interrupt */
  2293. #ifndef MRV_ISP_ISR_VSM_END
  2294. #define MRV_ISP_ISR_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2295. #endif /* !MRV_ISP_ISR_VSM_END */
  2296. /* Slice: ISR_EXP_END:*/
  2297. /* enable interrupt (1) or mask out (0)*/
  2298. #ifndef MRV_ISP_ISR_EXP_END
  2299. #define MRV_ISP_ISR_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2300. #endif /* !MRV_ISP_ISR_EXP_END */
  2301. /* Slice: ISR_FLASH_CAP:*/
  2302. /* enable interrupt (1) or mask out (0)*/
  2303. #ifndef MRV_ISP_ISR_FLASH_CAP
  2304. #define MRV_ISP_ISR_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2305. #endif /* !MRV_ISP_ISR_FLASH_CAP */
  2306. /* Slice: ISR_BP_DET:*/
  2307. /* enable interrupt (1) or mask out (0)*/
  2308. #ifndef MRV_ISP_ISR_BP_DET
  2309. #define MRV_ISP_ISR_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2310. #endif /* !MRV_ISP_ISR_BP_DET */
  2311. /* Slice: ISR_HIST_MEASURE_RDY:*/
  2312. /* enable interrupt (1) or mask out (0)*/
  2313. #ifndef MRV_ISP_ISR_HIST_MEASURE_RDY
  2314. #define MRV_ISP_ISR_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2315. #endif /* !MRV_ISP_ISR_HIST_MEASURE_RDY */
  2316. /* Slice: ISR_AFM_FIN:*/
  2317. /* enable interrupt (1) or mask out (0)*/
  2318. #ifndef MRV_ISP_ISR_AFM_FIN
  2319. #define MRV_ISP_ISR_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2320. #endif /* !ISR_AFM_FIN */
  2321. /* Slice: ISR_AFM_LUM_OF:*/
  2322. /* enable interrupt (1) or mask out (0)*/
  2323. #ifndef MRV_ISP_ISR_AFM_LUM_OF
  2324. #define MRV_ISP_ISR_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2325. #endif /* !MRV_ISP_ISR_AFM_LUM_OF */
  2326. /* Slice: ISR_AFM_SUM_OF:*/
  2327. /* enable interrupt (1) or mask out (0)*/
  2328. #ifndef MRV_ISP_ISR_AFM_SUM_OF
  2329. #define MRV_ISP_ISR_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2330. #endif /* !MRV_ISP_ISR_AFM_SUM_OF */
  2331. /* Slice: ISR_SHUTTER_OFF:*/
  2332. /* enable interrupt (1) or mask out (0)*/
  2333. #ifndef MRV_ISP_ISR_SHUTTER_OFF
  2334. #define MRV_ISP_ISR_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2335. #endif /* !MRV_ISP_ISR_SHUTTER_OFF */
  2336. /* Slice: ISR_SHUTTER_ON:*/
  2337. /* enable interrupt (1) or mask out (0)*/
  2338. #ifndef MRV_ISP_ISR_SHUTTER_ON
  2339. #define MRV_ISP_ISR_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2340. #endif /* !MRV_ISP_ISR_SHUTTER_ON */
  2341. /* Slice: ISR_FLASH_OFF:*/
  2342. /* enable interrupt (1) or mask out (0)*/
  2343. #ifndef MRV_ISP_ISR_FLASH_OFF
  2344. #define MRV_ISP_ISR_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2345. #endif /* !MRV_ISP_ISR_FLASH_OFF */
  2346. /* Slice: ISR_FLASH_ON:*/
  2347. /* enable interrupt (1) or mask out (0)*/
  2348. #ifndef MRV_ISP_ISR_FLASH_ON
  2349. #define MRV_ISP_ISR_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2350. #endif /* !MRV_ISP_ISR_FLASH_ON */
  2351. /* Slice: ISR_H_START:*/
  2352. /* enable interrupt (1) or mask out (0)*/
  2353. #ifndef MRV_ISP_ISR_H_START
  2354. #define MRV_ISP_ISR_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2355. #endif /* !MRV_ISP_ISR_H_START */
  2356. /* Slice: ISR_V_START:*/
  2357. /* enable interrupt (1) or mask out (0)*/
  2358. #ifndef MRV_ISP_ISR_V_START
  2359. #define MRV_ISP_ISR_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2360. #endif /* !MRV_ISP_ISR_V_START */
  2361. /* Slice: ISR_FRAME_IN:*/
  2362. /* enable interrupt (1) or mask out (0)*/
  2363. #ifndef MRV_ISP_ISR_FRAME_IN
  2364. #define MRV_ISP_ISR_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2365. #endif /* !MRV_ISP_ISR_FRAME_IN */
  2366. /* Slice: ISR_AWB_DONE:*/
  2367. /* enable interrupt (1) or mask out (0)*/
  2368. #ifndef MRV_ISP_ISR_AWB_DONE
  2369. #define MRV_ISP_ISR_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2370. #endif /* !MRV_ISP_ISR_AWB_DONE */
  2371. /* Slice: ISR_PIC_SIZE_ERR:*/
  2372. /* enable interrupt (1) or mask out (0)*/
  2373. #ifndef MRV_ISP_ISR_PIC_SIZE_ERR
  2374. #define MRV_ISP_ISR_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2375. #endif /* !MRV_ISP_ISR_PIC_SIZE_ERR */
  2376. /* Slice: ISR_DATA_LOSS:*/
  2377. /* enable interrupt (1) or mask out (0)*/
  2378. #ifndef MRV_ISP_ISR_DATA_LOSS
  2379. #define MRV_ISP_ISR_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2380. #endif /* !MRV_ISP_ISR_DATA_LOSS */
  2381. /* Slice: ISR_FRAME:*/
  2382. /* enable interrupt (1) or mask out (0)*/
  2383. #ifndef MRV_ISP_ISR_FRAME
  2384. #define MRV_ISP_ISR_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2385. #endif /* !MRV_ISP_ISR_FRAME */
  2386. /* Slice: ISR_ISP_OFF:*/
  2387. /* enable interrupt (1) or mask out (0)*/
  2388. #ifndef MRV_ISP_ISR_ISP_OFF
  2389. #define MRV_ISP_ISR_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2390. #endif /* !MRV_ISP_ISR_ISP_OFF */
  2391. /* combination of all interrupt lines */
  2392. #define MRV_ISP_ISR_ALL_IRQS
  2393. #define MRV_ISP_ISR_ALL_IRQS_MASK \
  2394. (0 \
  2395. | MRV_ISP_ISR_VSM_END_MASK \
  2396. | MRV_ISP_ISR_EXP_END_MASK \
  2397. | MRV_ISP_ISR_FLASH_CAP_MASK \
  2398. | MRV_ISP_ISR_BP_DET_MASK \
  2399. | MRV_ISP_ISR_HIST_MEASURE_RDY_MASK \
  2400. | MRV_ISP_ISR_AFM_FIN_MASK \
  2401. | MRV_ISP_ISR_AFM_LUM_OF_MASK \
  2402. | MRV_ISP_ISR_AFM_SUM_OF_MASK \
  2403. | MRV_ISP_ISR_SHUTTER_OFF_MASK \
  2404. | MRV_ISP_ISR_SHUTTER_ON_MASK \
  2405. | MRV_ISP_ISR_FLASH_OFF_MASK \
  2406. | MRV_ISP_ISR_FLASH_ON_MASK \
  2407. | MRV_ISP_ISR_H_START_MASK \
  2408. | MRV_ISP_ISR_V_START_MASK \
  2409. | MRV_ISP_ISR_FRAME_IN_MASK \
  2410. | MRV_ISP_ISR_AWB_DONE_MASK \
  2411. | MRV_ISP_ISR_PIC_SIZE_ERR_MASK \
  2412. | MRV_ISP_ISR_DATA_LOSS_MASK \
  2413. | MRV_ISP_ISR_FRAME_MASK \
  2414. | MRV_ISP_ISR_ISP_OFF_MASK \
  2415. )
  2416. #define MRV_ISP_ISR_ALL_IRQS_SHIFT 0U
  2417. /*****************************************************************************/
  2418. /**
  2419. * register array: isp_ct_coeff: cross-talk configuration register (color
  2420. * correction matrix) (0x03A0 + n*0x4 (n=0..8))
  2421. *
  2422. *****************************************************************************/
  2423. /* Slice: ct_coeff:*/
  2424. /* Coefficient n for cross talk matrix.*/
  2425. /**/
  2426. /* Values are 11-bit signed fixed-point numbers with 4 bit integer and */
  2427. /* 7 bit fractional part, ranging from -8 (0x400) to +7.992 (0x3FF).*/
  2428. /* 0 is reprsented by 0x000 and a coefficient value of 1 as 0x080.*/
  2429. #ifdef MRV_ISP_CT_COEFF
  2430. #define MRV_ISP_CT_COEFF_DEFAULT 0x080U /* default value */
  2431. #endif /* MRV_ISP_CT_COEFF */
  2432. /*****************************************************************************/
  2433. /**
  2434. * register: isp_gamma_out_mode: gamma segmentation mode register for output
  2435. * gamma (0x000001f4)
  2436. *
  2437. *****************************************************************************/
  2438. /* Slice: equ_segm:*/
  2439. /* 0: logarithmic like segmentation of gamma curve (default after reset)*/
  2440. /* segmentation from 0 to 4095: 64 64 64 64 128 128 128 128 256 256 256 512 512 512 512 512 */
  2441. /* 1: equidistant segmentation (all 16 segments are 256)*/
  2442. #ifdef MRV_ISP_EQU_SEGM
  2443. #define MRV_ISP_EQU_SEGM_LOG 0 /* 0: logarithmic like segmentation of gamma curve (default after reset) */
  2444. #define MRV_ISP_EQU_SEGM_EQU 1 /* 1: equidistant segmentation (all 16 segments are 256) */
  2445. #endif /* MRV_ISP_EQU_SEGM */
  2446. /*****************************************************************************/
  2447. /**
  2448. * register array: isp_gamma_out_y: Gamma Out Curve definition y (0x03F0 + n*0x4 (n=0..16))
  2449. *
  2450. *****************************************************************************/
  2451. /* Slice: isp_gamma_out_y:*/
  2452. /* Gamma_out curve point definition y-axis (output) for all color */
  2453. /* components (red, green, blue)*/
  2454. /* RESTRICTION: each Y_n must be in the +511/-512 range compared */
  2455. /* to its predecessor (so that dy is 10-bit signed !)*/
  2456. #ifdef MRV_ISP_ISP_GAMMA_OUT_Y
  2457. #endif /* MRV_ISP_ISP_GAMMA_OUT_Y */
  2458. /*****************************************************************************/
  2459. /**
  2460. * register: isp_err: ISP error register (0x0000023c)
  2461. *
  2462. *****************************************************************************/
  2463. /* Slice: outform_size_err:*/
  2464. /* size error is generated in outmux submodule */
  2465. #ifdef MRV_ISP_OUTFORM_SIZE_ERR
  2466. #endif /* MRV_ISP_OUTFORM_SIZE_ERR */
  2467. /* Slice: is_size_err:*/
  2468. /* size error is generated in image stabilization submodule */
  2469. #ifdef MRV_ISP_IS_SIZE_ERR
  2470. #endif /* MRV_ISP_IS_SIZE_ERR */
  2471. /* Slice: inform_size_err:*/
  2472. /* size error is generated in inform submodule */
  2473. #ifdef MRV_ISP_INFORM_SIZE_ERR
  2474. #endif /* MRV_ISP_INFORM_SIZE_ERR */
  2475. /*****************************************************************************/
  2476. /**
  2477. * register: isp_err_clr: ISP error clear register (0x00000240)
  2478. *
  2479. *****************************************************************************/
  2480. /* Slice: outform_size_err_clr:*/
  2481. /* size error is cleared */
  2482. #ifdef MRV_ISP_OUTFORM_SIZE_ERR_CLR
  2483. #endif /* MRV_ISP_OUTFORM_SIZE_ERR_CLR */
  2484. /* Slice: is_size_err_clr:*/
  2485. /* size error is cleared */
  2486. #ifdef MRV_ISP_IS_SIZE_ERR_CLR
  2487. #endif /* MRV_ISP_IS_SIZE_ERR_CLR */
  2488. /* Slice: inform_size_err_clr:*/
  2489. /* size error is cleared */
  2490. #ifdef MRV_ISP_INFORM_SIZE_ERR_CLR
  2491. #endif /* MRV_ISP_INFORM_SIZE_ERR_CLR */
  2492. /*****************************************************************************/
  2493. /**
  2494. * register: isp_frame_count: Frame counter (0x00000244)
  2495. *
  2496. *****************************************************************************/
  2497. /* Slice: frame_counter:*/
  2498. /* Current frame count of processing */
  2499. #ifdef MRV_ISP_FRAME_COUNTER
  2500. #endif /* MRV_ISP_FRAME_COUNTER */
  2501. /*****************************************************************************/
  2502. /**
  2503. * register: isp_ct_offset_r: cross-talk offset red (0x00000248)
  2504. *
  2505. *****************************************************************************/
  2506. /* Slice: ct_offset_r:*/
  2507. /* Offset red for cross talk matrix. Two's complement integer number ranging */
  2508. /* from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/
  2509. #ifdef MRV_ISP_CT_OFFSET_R
  2510. #define MRV_ISP_CT_OFFSET_R_DEFAULT 0x000U /* default value */
  2511. #endif /* MRV_ISP_CT_OFFSET_R */
  2512. /*****************************************************************************/
  2513. /**
  2514. * register: isp_ct_offset_g: cross-talk offset green (0x0000024c)
  2515. *
  2516. *****************************************************************************/
  2517. /* Slice: ct_offset_g:*/
  2518. /* Offset green for cross talk matrix. Two's complement integer number ranging */
  2519. /* from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/
  2520. #ifdef MRV_ISP_CT_OFFSET_G
  2521. #define MRV_ISP_CT_OFFSET_G_DEFAULT 0x000U /* default value */
  2522. #endif /* MRV_ISP_CT_OFFSET_G */
  2523. /*****************************************************************************/
  2524. /**
  2525. * register: isp_ct_offset_b: cross-talk offset blue (0x00000250)
  2526. *
  2527. *****************************************************************************/
  2528. /* Slice: ct_offset_b:*/
  2529. /* Offset blue for cross talk matrix. Two's complement integer number ranging */
  2530. /* from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/
  2531. #ifdef MRV_ISP_CT_OFFSET_B
  2532. #define MRV_ISP_CT_OFFSET_B_DEFAULT 0x000U /* default value */
  2533. #endif /* MRV_ISP_CT_OFFSET_B */
  2534. /*****************************************************************************/
  2535. /* ISP Flash Module Registers */
  2536. /*****************************************************************************/
  2537. /*****************************************************************************/
  2538. /**
  2539. * register: isp_flash_cmd: Flash command (0x0000)
  2540. *
  2541. *****************************************************************************/
  2542. /* Slice: preflash_on:*/
  2543. /* preflash on */
  2544. /* 0: no effect */
  2545. /* 1: flash delay counter is started at next trigger event */
  2546. /* No capture event is signaled to the sensor interface block.*/
  2547. #ifdef MRV_FLASH_PREFLASH_ON
  2548. #endif /* MRV_FLASH_PREFLASH_ON */
  2549. /* Slice: flash_on:*/
  2550. /* flash on */
  2551. /* 0: no effect */
  2552. /* 1: flash delay counter is started at next trigger event */
  2553. /* A capture event is signaled to the sensor interface block.*/
  2554. #ifdef MRV_FLASH_FLASH_ON
  2555. #endif /* MRV_FLASH_FLASH_ON */
  2556. /* Slice: prelight_on:*/
  2557. /* prelight on */
  2558. /* 0: prelight is switched off at next trigger event */
  2559. /* 1: prelight is switched on at next trigger event */
  2560. #ifdef MRV_FLASH_PRELIGHT_ON
  2561. #endif /* MRV_FLASH_PRELIGHT_ON */
  2562. /*****************************************************************************/
  2563. /**
  2564. * register: isp_flash_config: Flash config (0x0004)
  2565. *
  2566. *****************************************************************************/
  2567. /* Slice: fl_cap_del:*/
  2568. /* capture delay */
  2569. /* frame number (0 to 15) to be captured after trigger event */
  2570. #ifdef MRV_FLASH_FL_CAP_DEL
  2571. #endif /* MRV_FLASH_FL_CAP_DEL */
  2572. /* Slice: fl_trig_src:*/
  2573. /* trigger source for flash and prelight */
  2574. /* 0: use "vds_vsync" for trigger event (with evaluation of vs_in_edge)*/
  2575. /* 1: use "fl_trig" for trigger event (positive edge)*/
  2576. #ifdef MRV_FLASH_FL_TRIG_SRC
  2577. #define MRV_FLASH_FL_TRIG_SRC_VDS 0 /* 0: use "vds_vsync" for trigger event (with evaluation of vs_in_edge) */
  2578. #define MRV_FLASH_FL_TRIG_SRC_FL 1 /* 1: use "fl_trig" for trigger event (positive edge) */
  2579. #endif /* MRV_FLASH_FL_TRIG_SRC */
  2580. /* Slice: fl_pol:*/
  2581. /* polarity of flash related signals */
  2582. /* 0: flash_trig, prelight_trig are high active */
  2583. /* 1: flash_trig, prelight_trig are low active */
  2584. #ifdef MRV_FLASH_FL_POL
  2585. #define MRV_FLASH_FL_POL_HIGH 0 /* 0: flash_trig, prelight_trig are high active */
  2586. #define MRV_FLASH_FL_POL_LOW 1 /* 1: flash_trig, prelight_trig are low active */
  2587. #endif /* MRV_FLASH_FL_POL */
  2588. /* Slice: vs_in_edge:*/
  2589. /* VSYNC edge */
  2590. /* 0: use negative edge of "vds_vsync" if generating a trigger event */
  2591. /* 1: use positive edge of "vds_vsync" if generating a trigger event */
  2592. #ifdef MRV_FLASH_VS_IN_EDGE
  2593. #define MRV_FLASH_VS_IN_EDGE_NEG 0 /* 0: use negative edge of "vds_vsync" if generating a trigger event */
  2594. #define MRV_FLASH_VS_IN_EDGE_POS 1 /* 1: use positive edge of "vds_vsync" if generating a trigger event */
  2595. #endif /* MRV_FLASH_VS_IN_EDGE */
  2596. /* Slice: prelight_mode:*/
  2597. /* prelight mode */
  2598. /* 0: prelight is switched off at begin of flash */
  2599. /* 1: prelight is switched off at end of flash */
  2600. #ifdef MRV_FLASH_PRELIGHT_MODE
  2601. #define MRV_FLASH_PRELIGHT_MODE_OASF 0 /* 0: prelight is switched off at begin of flash */
  2602. #define MRV_FLASH_PRELIGHT_MODE_OAEF 1 /* 1: prelight is switched off at end of flash */
  2603. #endif /* MRV_FLASH_PRELIGHT_MODE */
  2604. /*****************************************************************************/
  2605. /**
  2606. * register: isp_flash_prediv: Flash Counter Pre-Divider (0x00000008)
  2607. *
  2608. *****************************************************************************/
  2609. /* Slice: fl_pre_div:*/
  2610. /* pre-divider for flush/preflash counter */
  2611. #ifdef MRV_FLASH_FL_PRE_DIV
  2612. #endif /* MRV_FLASH_FL_PRE_DIV */
  2613. /*****************************************************************************/
  2614. /**
  2615. * register: isp_flash_delay: Flash Delay (0x000c)
  2616. *
  2617. *****************************************************************************/
  2618. /* Slice: fl_delay:*/
  2619. /* counter value for flash/preflash delay */
  2620. /* open_delay = (fl_delay + 1) * (fl_pre_div+1) / clk_isp */
  2621. /* fl_delay = (open_delay * clk_isp) / (fl_pre_div+1) - 1 */
  2622. #ifdef MRV_FLASH_FL_DELAY
  2623. #endif /* MRV_FLASH_FL_DELAY */
  2624. /*****************************************************************************/
  2625. /**
  2626. * register: isp_flash_time: Flash time (0x00000010)
  2627. *
  2628. *****************************************************************************/
  2629. /* Slice: fl_time:*/
  2630. /* counter value for flash/preflash time */
  2631. /* open_time = (fl_time + 1) * (fl_pre_div+1) / clk_isp */
  2632. /* fl_time = (open_time * clk_isp) / (fl_pre_div+1) - 1 */
  2633. #ifdef MRV_FLASH_FL_TIME
  2634. #endif /* MRV_FLASH_FL_TIME */
  2635. /*****************************************************************************/
  2636. /**
  2637. * register: isp_flash_maxp: Maximum value for flash or preflash (0x00000014)
  2638. *
  2639. *****************************************************************************/
  2640. /* Slice: fl_maxp:*/
  2641. /* maximum period value for flash or preflash */
  2642. /* max. flash/preflash period = 214 * (fl_maxp + 1) / clk_isp */
  2643. /* fl_maxp = (max_period * clk_isp) / 214 - 1 */
  2644. #ifdef MRV_FLASH_FL_MAXP
  2645. #endif /* MRV_FLASH_FL_MAXP */
  2646. /*****************************************************************************/
  2647. /* ISP Shutter Module Registers */
  2648. /*****************************************************************************/
  2649. /*****************************************************************************/
  2650. /**
  2651. * register: isp_sh_ctrl: mechanical shutter control (0x0000)
  2652. *
  2653. *****************************************************************************/
  2654. /* Slice: sh_open_pol:*/
  2655. /* shutter_open polarity */
  2656. /* 0: shutter_open is high active */
  2657. /* 1: shutter_open is low active */
  2658. #ifdef MRV_SHUT_SH_OPEN_POL
  2659. #define MRV_SHUT_SH_OPEN_POL_HIGH 0 /* 0: shutter_open is high active */
  2660. #define MRV_SHUT_SH_OPEN_POL_LOW 1 /* 1: shutter_open is low active */
  2661. #endif /* MRV_SHUT_SH_OPEN_POL */
  2662. /* Slice: sh_trig_en:*/
  2663. /* mechanical shutter trigger edge */
  2664. /* 0: use negative edge of trigger signal */
  2665. /* 1: use positive edge of trigger signal */
  2666. #ifdef MRV_SHUT_SH_TRIG_EN
  2667. #define MRV_SHUT_SH_TRIG_EN_NEG 0 /* 0: use negative edge of trigger signal */
  2668. #define MRV_SHUT_SH_TRIG_EN_POS 1 /* 1: use positive edge of trigger signal */
  2669. #endif /* MRV_SHUT_SH_TRIG_EN */
  2670. /* Slice: sh_trig_src:*/
  2671. /* mechanical shutter trigger source */
  2672. /* 0: use "vds_vsync" for trigger event */
  2673. /* 1: use "shutter_trig" for trigger event */
  2674. #ifdef MRV_SHUT_SH_TRIG_SRC
  2675. #define MRV_SHUT_SH_TRIG_SRC_VDS 0 /* 0: use "vds_vsync" for trigger event */
  2676. #define MRV_SHUT_SH_TRIG_SRC_SHUT 1 /* 1: use "shutter_trig" for trigger event */
  2677. #endif /* MRV_SHUT_SH_TRIG_SRC */
  2678. /* Slice: sh_rep_en:*/
  2679. /* mechanical shutter repetition enable */
  2680. /* 0: shutter is opened only once */
  2681. /* 1: shutter is opened with the repetition rate of the trigger signal */
  2682. #ifdef MRV_SHUT_SH_REP_EN
  2683. #define MRV_SHUT_SH_REP_EN_ONCE 0 /* 0: shutter is opened only once */
  2684. #define MRV_SHUT_SH_REP_EN_REP 1 /* 1: shutter is opened with the repetition rate of the trigger signal */
  2685. #endif /* MRV_SHUT_SH_REP_EN */
  2686. /* Slice: sh_en:*/
  2687. /* mechanical shutter enable */
  2688. /* 0: mechanical shutter function is disabled */
  2689. /* 1: mechanical shutter function is enabled */
  2690. #ifdef MRV_SHUT_SH_EN
  2691. #endif /* MRV_SHUT_SH_EN */
  2692. /*****************************************************************************/
  2693. /**
  2694. * register: isp_sh_prediv: Mech. Shutter Counter Pre-Divider (0x0004)
  2695. *
  2696. *****************************************************************************/
  2697. /* Slice: sh_pre_div:*/
  2698. /* pre-divider for mechanical shutter open_delay and open_time counter */
  2699. #ifdef MRV_SHUT_SH_PRE_DIV
  2700. #endif /* MRV_SHUT_SH_PRE_DIV */
  2701. /*****************************************************************************/
  2702. /**
  2703. * register: isp_sh_delay: Delay register (0x00000008)
  2704. *
  2705. *****************************************************************************/
  2706. /* Slice: sh_delay:*/
  2707. /* counter value for delay */
  2708. /* open_delay = (sh_delay + 1) * (fl_pre_div+1) / clk_isp */
  2709. /* sh_delay = (open_delay * clk_isp) / (sh_pre_div+1) – 1 */
  2710. #ifdef MRV_SHUT_SH_DELAY
  2711. #endif /* MRV_SHUT_SH_DELAY */
  2712. /*****************************************************************************/
  2713. /**
  2714. * register: isp_sh_time: Time register (0x0000000c)
  2715. *
  2716. *****************************************************************************/
  2717. /* Slice: sh_time:*/
  2718. /* counter value for time */
  2719. /* open_time = (sh_time + 1) * (fl_pre_div+1) / clk_isp */
  2720. /* sh_time = (open_time * clk_isp) / (sh_pre_div+1) - 1 */
  2721. #ifndef MRV_SHUT_SH_TIME
  2722. #endif /* MRV_SHUT_SH_TIME */
  2723. /*****************************************************************************/
  2724. /* Color Processing Module Registers */
  2725. /*****************************************************************************/
  2726. /*****************************************************************************/
  2727. /**
  2728. * register: c_proc_ctrl: Global control register (0x0000)
  2729. *
  2730. *****************************************************************************/
  2731. /* Slice: cproc_c_out_range:*/
  2732. /* Color processing chrominance pixel clipping range at output */
  2733. /* 0: CbCr_out clipping range 16..240 according to ITU-R BT.601 standard */
  2734. /* 1: full UV_out clipping range 0..255 */
  2735. #ifdef MRV_CPROC_CPROC_C_OUT_RANGE
  2736. #define MRV_CPROC_CPROC_C_OUT_RANGE_BT601 0 /* 0: CbCr_out clipping range 16..240 according to ITU-R BT.601 standard */
  2737. #define MRV_CPROC_CPROC_C_OUT_RANGE_FULL 1 /* 1: full UV_out clipping range 0..255 */
  2738. #endif /* MRV_CPROC_CPROC_C_OUT_RANGE */
  2739. /* Slice: cproc_y_in_range:*/
  2740. /* Color processing luminance input range (offset processing)*/
  2741. /* 0: Y_in range 64..940 according to ITU-R BT.601 standard;*/
  2742. /* offset of 64 will be subtracted from Y_in */
  2743. /* 1: Y_in full range 0..1023; no offset will be subtracted from Y_in */
  2744. #ifdef MRV_CPROC_CPROC_Y_IN_RANGE
  2745. #define MRV_CPROC_CPROC_Y_IN_RANGE_BT601 0 /* 0: Y_in range 64..940 according to ITU-R BT.601 standard */
  2746. #define MRV_CPROC_CPROC_Y_IN_RANGE_FULL 1 /* 1: Y_in full range 0..1023 */
  2747. #endif /* MRV_CPROC_CPROC_Y_IN_RANGE */
  2748. /* Slice: cproc_y_out_range:*/
  2749. /* Color processing luminance output clipping range */
  2750. /* 0: Y_out clipping range 16..235; offset of 16 is added to Y_out according to ITU-R BT.601 standard */
  2751. /* 1: Y_out clipping range 0..255; no offset is added to Y_out */
  2752. #ifdef MRV_CPROC_CPROC_Y_OUT_RANGE
  2753. #define MRV_CPROC_CPROC_Y_OUT_RANGE_BT601 0 /* 0: Y_out clipping range 16..235; offset of 16 is added to Y_out according to ITU-R BT.601 standard */
  2754. #define MRV_CPROC_CPROC_Y_OUT_RANGE_FULL 1 /* 1: Y_out clipping range 0..255; no offset is added to Y_out */
  2755. #endif /* MRV_CPROC_CPROC_Y_OUT_RANGE */
  2756. /* Slice: cproc_enable:*/
  2757. /* color processing enable */
  2758. /* 0: color processing is bypassed */
  2759. /* 2 * 10 Bit input data are truncated to 2 * 8Bit output data */
  2760. /* 1: color processing is active */
  2761. /* output data are rounded to 2 * 8Bit and clipping is active */
  2762. #ifdef MRV_CPROC_CPROC_ENABLE
  2763. #define MRV_CPROC_CPROC_ENABLE_PROCESS 1 /* 1: processing is activated */
  2764. #define MRV_CPROC_CPROC_ENABLE_BYPASS 0 /* 0: processing is deactivated, bypass mode is selected */
  2765. #endif /* MRV_CPROC_CPROC_ENABLE */
  2766. /*****************************************************************************/
  2767. /**
  2768. * register: c_proc_contrast: Color Processing contrast register (0x0004)
  2769. *
  2770. *****************************************************************************/
  2771. /* Slice: cproc_contrast:*/
  2772. /* contrast adjustment value */
  2773. /* 00H equals x 0.0 */
  2774. /* ...*/
  2775. /* 80H equals x 1.0 */
  2776. /* ...*/
  2777. /* FFH equals x 1.992 */
  2778. #ifdef MRV_CPROC_CPROC_CONTRAST
  2779. #endif /* MRV_CPROC_CPROC_CONTRAST */
  2780. /*****************************************************************************/
  2781. /**
  2782. * register: c_proc_brightness: Color Processing brightness register (0x0008)
  2783. *
  2784. *****************************************************************************/
  2785. /* Slice: cproc_brightness:*/
  2786. /* brightness adjustment value */
  2787. /* 80H equals -128 */
  2788. /* ...*/
  2789. /* 00H equals +0 */
  2790. /* ...*/
  2791. /* 7FH equals +127 */
  2792. #ifdef MRV_CPROC_CPROC_BRIGHTNESS
  2793. #endif /* MRV_CPROC_CPROC_BRIGHTNESS */
  2794. /*****************************************************************************/
  2795. /**
  2796. * register: c_proc_saturation: Color Processing saturation register (0x000c)
  2797. *
  2798. *****************************************************************************/
  2799. /* Slice: cproc_saturation:*/
  2800. /* saturation adjustment value */
  2801. /* 00H equals x 0.0 */
  2802. /* ...*/
  2803. /* 80H equals x 1.0 */
  2804. /* ...*/
  2805. /* FFH equals x 1.992 */
  2806. #ifdef MRV_CPROC_CPROC_SATURATION
  2807. #endif /* MRV_CPROC_CPROC_SATURATION */
  2808. /*****************************************************************************/
  2809. /**
  2810. * register: c_proc_hue: Color Processing hue register (0x0010)
  2811. *
  2812. *****************************************************************************/
  2813. /* Slice: cproc_hue:*/
  2814. /* hue adjustment value */
  2815. /* 80H equals -90 deg */
  2816. /* ...*/
  2817. /* 00H equals 0 deg */
  2818. /* ...*/
  2819. /* 7FH equals +87.188 deg */
  2820. #ifdef MRV_CPROC_CPROC_HUE
  2821. #endif /* MRV_CPROC_CPROC_HUE */
  2822. /*****************************************************************************/
  2823. /* Main Resizer/Scaler Registers */
  2824. /*****************************************************************************/
  2825. /*****************************************************************************/
  2826. /**
  2827. * register: mrsz_ctrl: global control register (0x00000000)
  2828. *
  2829. *****************************************************************************/
  2830. /* Slice: cfg_upd:*/
  2831. /* write 0: nothing happens */
  2832. /* write 1: update shadow registers */
  2833. /* read: always 0 */
  2834. #ifdef MRV_MRSZ_CFG_UPD
  2835. #endif /* MRV_MRSZ_CFG_UPD */
  2836. /* Slice: scale_vc_up:*/
  2837. /* 1: vertical chrominance upscaling selected */
  2838. /* 0: vertical chrominance downscaling selected */
  2839. #ifdef MRV_MRSZ_SCALE_VC_UP
  2840. #define MRV_MRSZ_SCALE_VC_UP_UPSCALE 1 /* 1: vertical chrominance upscaling selected */
  2841. #define MRV_MRSZ_SCALE_VC_UP_DOWNSCALE 0 /* 0: vertical chrominance downscaling selected */
  2842. #endif /* MRV_MRSZ_SCALE_VC_UP */
  2843. /* Slice: scale_vy_up:*/
  2844. /* 1: vertical luminance upscaling selected */
  2845. /* 0: vertical luminance downscaling selected */
  2846. #ifdef MRV_MRSZ_SCALE_VY_UP
  2847. #define MRV_MRSZ_SCALE_VY_UP_UPSCALE 1 /* 1: vertical luminance upscaling selected */
  2848. #define MRV_MRSZ_SCALE_VY_UP_DOWNSCALE 0 /* 0: vertical luminance downscaling selected */
  2849. #endif /* MRV_MRSZ_SCALE_VY_UP */
  2850. /* Slice: scale_hc_up:*/
  2851. /* 1: horizontal chrominance upscaling selected */
  2852. /* 0: horizontal chrominance downscaling selected */
  2853. #ifdef MRV_MRSZ_SCALE_HC_UP
  2854. #define MRV_MRSZ_SCALE_HC_UP_UPSCALE 1 /* 1: horizontal chrominance upscaling selected */
  2855. #define MRV_MRSZ_SCALE_HC_UP_DOWNSCALE 0 /* 0: horizontal chrominance downscaling selected */
  2856. #endif /* MRV_MRSZ_SCALE_HC_UP */
  2857. /* Slice: scale_hy_up:*/
  2858. /* 1: horizontal luminance upscaling selected */
  2859. /* 0: horizontal luminance downscaling selected */
  2860. #ifdef MRV_MRSZ_SCALE_HY_UP
  2861. #define MRV_MRSZ_SCALE_HY_UP_UPSCALE 1 /* 1: horizontal luminance upscaling selected */
  2862. #define MRV_MRSZ_SCALE_HY_UP_DOWNSCALE 0 /* 0: horizontal luminance downscaling selected */
  2863. #endif /* MRV_MRSZ_SCALE_HY_UP */
  2864. /* Slice: scale_vc_enable:*/
  2865. /* 0: bypass vertical chrominance scaling unit */
  2866. /* 1: enable vertical chrominance scaling unit */
  2867. #ifdef MRV_MRSZ_SCALE_VC_ENABLE
  2868. #define MRV_MRSZ_SCALE_VC_ENABLE_PROCESS 1 /* 1: enable vertical chrominance scaling unit */
  2869. #define MRV_MRSZ_SCALE_VC_ENABLE_BYPASS 0 /* 0: bypass vertical chrominance scaling unit */
  2870. #endif /* MRV_MRSZ_SCALE_VC_ENABLE */
  2871. /* Slice: scale_vy_enable:*/
  2872. /* 0: bypass vertical luminance scaling unit */
  2873. /* 1: enable vertical luminance scaling unit */
  2874. #ifdef MRV_MRSZ_SCALE_VY_ENABLE
  2875. #define MRV_MRSZ_SCALE_VY_ENABLE_PROCESS 1 /* 1: enable vertical luminance scaling unit */
  2876. #define MRV_MRSZ_SCALE_VY_ENABLE_BYPASS 0 /* 0: bypass vertical luminance scaling unit */
  2877. #endif /* MRV_MRSZ_SCALE_VY_ENABLE */
  2878. /* Slice: scale_hc_enable:*/
  2879. /* 0: bypass horizontal chrominance scaling unit */
  2880. /* 1: enable horizontal chrominance scaling unit */
  2881. #ifdef MRV_MRSZ_SCALE_HC_ENABLE
  2882. #define MRV_MRSZ_SCALE_HC_ENABLE_PROCESS 1 /* 1: enable horizontal chrominance scaling unit */
  2883. #define MRV_MRSZ_SCALE_HC_ENABLE_BYPASS 0 /* 0: bypass horizontal chrominance scaling unit */
  2884. #endif /* MRV_MRSZ_SCALE_HC_ENABLE */
  2885. /* Slice: scale_hy_enable:*/
  2886. /* 0: bypass horizontal luminance scaling unit */
  2887. /* 1: enable horizontal luminance scaling unit */
  2888. #ifdef MRV_MRSZ_SCALE_HY_ENABLE
  2889. #define MRV_MRSZ_SCALE_HY_ENABLE_PROCESS 1 /* 1: enable horizontal luminance scaling unit */
  2890. #define MRV_MRSZ_SCALE_HY_ENABLE_BYPASS 0 /* 0: bypass horizontal luminance scaling unit */
  2891. #endif /* MRV_MRSZ_SCALE_HY_ENABLE */
  2892. /*****************************************************************************/
  2893. /**
  2894. * register: mrsz_scale_hy: horizontal luminance scale factor register
  2895. * (0x00000004)
  2896. *
  2897. *****************************************************************************/
  2898. /* Slice: scale_hy:*/
  2899. /* This register is set to the horizontal luminance downscale factor or to */
  2900. /* the reciprocal of the horizontal luminance upscale factor */
  2901. #ifdef MRV_MRSZ_SCALE_HY
  2902. #endif /* MRV_MRSZ_SCALE_HY */
  2903. /*****************************************************************************/
  2904. /**
  2905. * register: mrsz_scale_hcb: horizontal Cb scale factor register (0x00000008)
  2906. *
  2907. *****************************************************************************/
  2908. /* Slice: scale_hcb:*/
  2909. /* This register is set to the horizontal Cb downscale factor or to the */
  2910. /* reciprocal of the horizontal Cb upscale factor */
  2911. #ifdef MRV_MRSZ_SCALE_HCB
  2912. #endif /* MRV_MRSZ_SCALE_HCB */
  2913. /*****************************************************************************/
  2914. /**
  2915. * register: mrsz_scale_hcr: horizontal Cr scale factor register (0x0000000c)
  2916. *
  2917. *****************************************************************************/
  2918. /* Slice: scale_hcr:*/
  2919. /* This register is set to the horizontal Cr downscale factor or to the */
  2920. /* reciprocal of the horizontal Cr upscale factor */
  2921. #ifdef MRV_MRSZ_SCALE_HCR
  2922. #endif /* MRV_MRSZ_SCALE_HCR */
  2923. /*****************************************************************************/
  2924. /**
  2925. * register: mrsz_scale_vy: vertical luminance scale factor register (0x00000010)
  2926. *
  2927. *****************************************************************************/
  2928. /* Slice: scale_vy:*/
  2929. /* This register is set to the vertical luminance downscale factor or to the */
  2930. /* reciprocal of the vertical luminance upscale factor */
  2931. #ifdef MRV_MRSZ_SCALE_VY
  2932. #endif /* MRV_MRSZ_SCALE_VY */
  2933. /*****************************************************************************/
  2934. /**
  2935. * register: mrsz_scale_vc: vertical chrominance scale factor register (0x00000014)
  2936. *
  2937. *****************************************************************************/
  2938. /* Slice: scale_vc:*/
  2939. /* This register is set to the vertical chrominance downscale factor or to the */
  2940. /* reciprocal of the vertical chrominance upscale factor */
  2941. #ifdef MRV_MRSZ_SCALE_VC
  2942. #endif /* MRV_MRSZ_SCALE_VC */
  2943. /*****************************************************************************/
  2944. /**
  2945. * register: mrsz_phase_hy: horizontal luminance phase register (0x00000018)
  2946. *
  2947. *****************************************************************************/
  2948. /* Slice: phase_hy:*/
  2949. /* This register is set to the horizontal luminance phase offset */
  2950. #ifdef MRV_MRSZ_PHASE_HY
  2951. #endif /* MRV_MRSZ_PHASE_HY */
  2952. /*****************************************************************************/
  2953. /**
  2954. * register: mrsz_phase_hc: horizontal chrominance phase register (0x0000001c)
  2955. *
  2956. *****************************************************************************/
  2957. /* Slice: phase_hc:*/
  2958. /* This register is set to the horizontal chrominance phase offset */
  2959. #ifdef MRV_MRSZ_PHASE_HC
  2960. #endif /* MRV_MRSZ_PHASE_HC */
  2961. /*****************************************************************************/
  2962. /**
  2963. * register: mrsz_phase_vy: vertical luminance phase register (0x00000020)
  2964. *
  2965. *****************************************************************************/
  2966. /* Slice: phase_vy:*/
  2967. /* This register is set to the vertical luminance phase offset */
  2968. #ifdef MRV_MRSZ_PHASE_VY
  2969. #endif /* MRV_MRSZ_PHASE_VY */
  2970. /*****************************************************************************/
  2971. /**
  2972. * register: mrsz_phase_vc: vertical chrominance phase register (0x00000024)
  2973. *
  2974. *****************************************************************************/
  2975. /* Slice: phase_vc:*/
  2976. /* This register is set to the vertical chrominance phase offset */
  2977. #ifdef MRV_MRSZ_PHASE_VC
  2978. #endif /* MRV_MRSZ_PHASE_VC */
  2979. /*****************************************************************************/
  2980. /**
  2981. * register: mrsz_scale_lut_addr: Address pointer of up-scaling look up table
  2982. * (0x00000028)
  2983. *
  2984. *****************************************************************************/
  2985. /* Slice: scale_lut_addr:*/
  2986. /* Pointer to entry of lookup table */
  2987. #ifdef MRV_MRSZ_SCALE_LUT_ADDR
  2988. #endif /* MRV_MRSZ_SCALE_LUT_ADDR */
  2989. /*****************************************************************************/
  2990. /**
  2991. * register: mrsz_scale_lut: Entry of up-scaling look up table (0x0000002c)
  2992. *
  2993. *****************************************************************************/
  2994. /* Slice: scale_lut:*/
  2995. /* Entry of lookup table at position scale_lut_addr. The lookup table must be */
  2996. /* filled with appropriate values before the up-scaling functionality can be */
  2997. /* used.*/
  2998. #ifdef MRV_MRSZ_SCALE_LUT
  2999. #endif /* MRV_MRSZ_SCALE_LUT */
  3000. /*****************************************************************************/
  3001. /**
  3002. * register: mrsz_ctrl_shd: global control shadow register (0x0030)
  3003. *
  3004. *****************************************************************************/
  3005. /* Slice: scale_vc_up_shd:*/
  3006. /* 1: vertical chrominance upscaling selected */
  3007. /* 0: vertical chrominance downscaling selected */
  3008. #ifdef MRV_MRSZ_SCALE_VC_UP_SHD
  3009. #define MRV_MRSZ_SCALE_VC_UP_SHD_UPSCALE 1 /* 1: vertical chrominance upscaling selected */
  3010. #define MRV_MRSZ_SCALE_VC_UP_SHD_DOWNSCALE 0 /* 0: vertical chrominance downscaling selected */
  3011. #endif /* MRV_MRSZ_SCALE_VC_UP_SHD */
  3012. /* Slice: scale_vy_up_shd:*/
  3013. /* 1: vertical luminance upscaling selected */
  3014. /* 0: vertical luminance downscaling selected */
  3015. #ifdef MRV_MRSZ_SCALE_VY_UP_SHD
  3016. #define MRV_MRSZ_SCALE_VY_UP_SHD_UPSCALE 1 /* 1: vertical luminance upscaling selected */
  3017. #define MRV_MRSZ_SCALE_VY_UP_SHD_DOWNSCALE 0 /* 0: vertical luminance downscaling selected */
  3018. #endif /* MRV_MRSZ_SCALE_VY_UP_SHD */
  3019. /* Slice: scale_hc_up_shd:*/
  3020. /* 1: horizontal chrominance upscaling selected */
  3021. /* 0: horizontal chrominance downscaling selected */
  3022. #ifdef MRV_MRSZ_SCALE_HC_UP_SHD
  3023. #define MRV_MRSZ_SCALE_HC_UP_SHD_UPSCALE 1 /* 1: horizontal chrominance upscaling selected */
  3024. #define MRV_MRSZ_SCALE_HC_UP_SHD_DOWNSCALE 0 /* 0: horizontal chrominance downscaling selected */
  3025. #endif /* MRV_MRSZ_SCALE_HC_UP_SHD */
  3026. /* Slice: scale_hy_up_shd:*/
  3027. /* 1: horizontal luminance upscaling selected */
  3028. /* 0: horizontal luminance downscaling selected */
  3029. #ifdef MRV_MRSZ_SCALE_HY_UP_SHD
  3030. #define MRV_MRSZ_SCALE_HY_UP_SHD_UPSCALE 1 /* 1: horizontal luminance upscaling selected */
  3031. #define MRV_MRSZ_SCALE_HY_UP_SHD_DOWNSCALE 0 /* 0: horizontal luminance downscaling selected */
  3032. #endif /* MRV_MRSZ_SCALE_HY_UP_SHD */
  3033. /* Slice: scale_vc_enable_shd:*/
  3034. /* 0: bypass vertical chrominance scaling unit */
  3035. /* 1: enable vertical chrominance scaling unit */
  3036. #ifdef MRV_MRSZ_SCALE_VC_ENABLE_SHD
  3037. #define MRV_MRSZ_SCALE_VC_ENABLE_SHD_PROCESS 1 /* 1: enable vertical chrominance scaling unit */
  3038. #define MRV_MRSZ_SCALE_VC_ENABLE_SHD_BYPASS 0 /* 0: bypass vertical chrominance scaling unit */
  3039. #endif /* MRV_MRSZ_SCALE_VC_ENABLE_SHD */
  3040. /* Slice: scale_vy_enable_shd:*/
  3041. /* 0: bypass vertical luminance scaling unit */
  3042. /* 1: enable vertical luminance scaling unit */
  3043. #ifdef MRV_MRSZ_SCALE_VY_ENABLE_SHD
  3044. #define MRV_MRSZ_SCALE_VY_ENABLE_SHD_PROCESS 1 /* 1: enable vertical luminance scaling unit */
  3045. #define MRV_MRSZ_SCALE_VY_ENABLE_SHD_BYPASS 0 /* 0: bypass vertical luminance scaling unit */
  3046. #endif /* MRV_MRSZ_SCALE_VY_ENABLE_SHD */
  3047. /* Slice: scale_hc_enable_shd:*/
  3048. /* 0: bypass horizontal chrominance scaling unit */
  3049. /* 1: enable horizontal chrominance scaling unit */
  3050. #ifdef MRV_MRSZ_SCALE_HC_ENABLE_SHD
  3051. #define MRV_MRSZ_SCALE_HC_ENABLE_SHD_PROCESS 1 /* 1: enable horizontal chrominance scaling unit */
  3052. #define MRV_MRSZ_SCALE_HC_ENABLE_SHD_BYPASS 0 /* 0: bypass horizontal chrominance scaling unit */
  3053. #endif /* MRV_MRSZ_SCALE_HC_ENABLE_SHD */
  3054. /* Slice: scale_hy_enable_shd:*/
  3055. /* 0: bypass horizontal luminance scaling unit */
  3056. /* 1: enable horizontal luminance scaling unit */
  3057. #ifdef MRV_MRSZ_SCALE_HY_ENABLE_SHD
  3058. #define MRV_MRSZ_SCALE_HY_ENABLE_SHD_PROCESS 1 /* 1: enable horizontal luminance scaling unit */
  3059. #define MRV_MRSZ_SCALE_HY_ENABLE_SHD_BYPASS 0 /* 0: bypass horizontal luminance scaling unit */
  3060. #endif /* MRV_MRSZ_SCALE_HY_ENABLE_SHD */
  3061. /*****************************************************************************/
  3062. /**
  3063. * register: mrsz_scale_hy_shd: horizontal luminance scale factor shadow
  3064. * register (0x00000034)
  3065. *
  3066. *****************************************************************************/
  3067. /* Slice: scale_hy_shd:*/
  3068. /* This register is set to the horizontal luminance downscale factor or to the */
  3069. /* reciprocal of the horizontal luminance upscale factor */
  3070. #ifdef MRV_MRSZ_SCALE_HY_SHD
  3071. #endif /* MRV_MRSZ_SCALE_HY_SHD */
  3072. /*****************************************************************************/
  3073. /**
  3074. * register: mrsz_scale_hcb_shd: horizontal Cb scale factor shadow register
  3075. * (0x00000038)
  3076. *
  3077. *****************************************************************************/
  3078. /* Slice: scale_hcb_shd:*/
  3079. /* This register is set to the horizontal Cb downscale factor or to the */
  3080. /* reciprocal of the horizontal Cb upscale factor */
  3081. #ifdef MRV_MRSZ_SCALE_HCB_SHD
  3082. #endif /* MRV_MRSZ_SCALE_HCB_SHD */
  3083. /*****************************************************************************/
  3084. /**
  3085. * register: mrsz_scale_hcr_shd: horizontal Cr scale factor shadow register
  3086. * (0x0000003c)
  3087. *
  3088. *****************************************************************************/
  3089. /* Slice: scale_hcr_shd:*/
  3090. /* This register is set to the horizontal Cr downscale factor or to the */
  3091. /* reciprocal of the horizontal Cr upscale factor */
  3092. #ifdef MRV_MRSZ_SCALE_HCR_SHD
  3093. #endif /* MRV_MRSZ_SCALE_HCR_SHD */
  3094. /*****************************************************************************/
  3095. /**
  3096. * register: mrsz_scale_vy_shd: vertical luminance scale factor shadow register
  3097. * (0x00000040)
  3098. *
  3099. *****************************************************************************/
  3100. /* Slice: scale_vy_shd:*/
  3101. /* This register is set to the vertical luminance downscale factor or to the */
  3102. /* reciprocal of the vertical luminance upscale factor */
  3103. #ifdef MRV_MRSZ_SCALE_VY_SHD
  3104. #endif /* MRV_MRSZ_SCALE_VY_SHD */
  3105. /*****************************************************************************/
  3106. /**
  3107. * register: mrsz_scale_vc_shd: vertical chrominance scale factor shadow
  3108. * register (0x00000044)
  3109. *
  3110. *****************************************************************************/
  3111. /* Slice: scale_vc_shd:*/
  3112. /* This register is set to the vertical chrominance downscale factor or to */
  3113. /* the reciprocal of the vertical chrominance upscale factor */
  3114. #ifdef MRV_MRSZ_SCALE_VC_SHD
  3115. #endif /* MRV_MRSZ_SCALE_VC_SHD */
  3116. /*****************************************************************************/
  3117. /**
  3118. * register: mrsz_phase_hy_shd: horizontal luminance phase shadow register
  3119. * (0x00000048)
  3120. *
  3121. *****************************************************************************/
  3122. /* Slice: phase_hy_shd:*/
  3123. /* This register is set to the horizontal luminance phase offset */
  3124. #ifdef MRV_MRSZ_PHASE_HY_SHD
  3125. #endif /* MRV_MRSZ_PHASE_HY_SHD */
  3126. /*****************************************************************************/
  3127. /**
  3128. * register: mrsz_phase_hc_shd: horizontal chrominance phase shadow register
  3129. * (0x0000004c)
  3130. *
  3131. *****************************************************************************/
  3132. /* Slice: phase_hc_shd:*/
  3133. /* This register is set to the horizontal chrominance phase offset */
  3134. #ifdef MRV_MRSZ_PHASE_HC_SHD
  3135. #endif /* MRV_MRSZ_PHASE_HC_SHD */
  3136. /*****************************************************************************/
  3137. /**
  3138. * register: mrsz_phase_vy_shd: vertical luminance phase shadow register
  3139. * (0x00000050)
  3140. *
  3141. *****************************************************************************/
  3142. /* Slice: phase_vy_shd:*/
  3143. /* This register is set to the vertical luminance phase offset */
  3144. #ifdef MRV_MRSZ_PHASE_VY_SHD
  3145. #endif /* MRV_MRSZ_PHASE_VY_SHD */
  3146. /*****************************************************************************/
  3147. /**
  3148. * register: mrsz_phase_vc_shd: vertical chrominance phase shadow register
  3149. * (0x00000054)
  3150. *
  3151. *****************************************************************************/
  3152. /* Slice: phase_vc_shd:*/
  3153. /* This register is set to the vertical chrominance phase offset */
  3154. #ifdef MRV_MRSZ_PHASE_VC_SHD
  3155. #endif /* MRV_MRSZ_PHASE_VC_SHD */
  3156. /*****************************************************************************/
  3157. /* Self Resizer/Scaler Registers */
  3158. /*****************************************************************************/
  3159. /*****************************************************************************/
  3160. /**
  3161. * register: srsz_ctrl: global control register (0x00000000)
  3162. *
  3163. *****************************************************************************/
  3164. /* Slice: cfg_upd:*/
  3165. /* write 0: nothing happens */
  3166. /* write 1: update shadow registers */
  3167. /* read: always 0 */
  3168. #ifdef MRV_SRSZ_CFG_UPD
  3169. #endif /* MRV_SRSZ_CFG_UPD */
  3170. /* Slice: scale_vc_up:*/
  3171. /* 1: vertical chrominance upscaling selected */
  3172. /* 0: vertical chrominance downscaling selected */
  3173. #ifdef MRV_SRSZ_SCALE_VC_UP
  3174. #define MRV_SRSZ_SCALE_VC_UP_UPSCALE 1 /* 1: vertical chrominance upscaling selected */
  3175. #define MRV_SRSZ_SCALE_VC_UP_DOWNSCALE 0 /* 0: vertical chrominance downscaling selected */
  3176. #endif /* MRV_SRSZ_SCALE_VC_UP */
  3177. /* Slice: scale_vy_up:*/
  3178. /* 1: vertical luminance upscaling selected */
  3179. /* 0: vertical luminance downscaling selected */
  3180. #ifdef MRV_SRSZ_SCALE_VY_UP
  3181. #define MRV_SRSZ_SCALE_VY_UP_UPSCALE 1 /* 1: vertical luminance upscaling selected */
  3182. #define MRV_SRSZ_SCALE_VY_UP_DOWNSCALE 0 /* 0: vertical luminance downscaling selected */
  3183. #endif /* MRV_SRSZ_SCALE_VY_UP */
  3184. /* Slice: scale_hc_up:*/
  3185. /* 1: horizontal chrominance upscaling selected */
  3186. /* 0: horizontal chrominance downscaling selected */
  3187. #ifdef MRV_SRSZ_SCALE_HC_UP
  3188. #define MRV_SRSZ_SCALE_HC_UP_UPSCALE 1 /* 1: horizontal chrominance upscaling selected */
  3189. #define MRV_SRSZ_SCALE_HC_UP_DOWNSCALE 0 /* 0: horizontal chrominance downscaling selected */
  3190. #endif /* MRV_SRSZ_SCALE_HC_UP */
  3191. /* Slice: scale_hy_up:*/
  3192. /* 1: horizontal luminance upscaling selected */
  3193. /* 0: horizontal luminance downscaling selected */
  3194. #ifdef MRV_SRSZ_SCALE_HY_UP
  3195. #define MRV_SRSZ_SCALE_HY_UP_UPSCALE 1 /* 1: horizontal luminance upscaling selected */
  3196. #define MRV_SRSZ_SCALE_HY_UP_DOWNSCALE 0 /* 0: horizontal luminance downscaling selected */
  3197. #endif /* MRV_SRSZ_SCALE_HY_UP */
  3198. /* Slice: scale_vc_enable:*/
  3199. /* 0: bypass vertical chrominance scaling unit */
  3200. /* 1: enable vertical chrominance scaling unit */
  3201. #ifdef MRV_SRSZ_SCALE_VC_ENABLE
  3202. #define MRV_SRSZ_SCALE_VC_ENABLE_PROCESS 1 /* 1: enable vertical chrominance scaling unit */
  3203. #define MRV_SRSZ_SCALE_VC_ENABLE_BYPASS 0 /* 0: bypass vertical chrominance scaling unit */
  3204. #endif /* MRV_SRSZ_SCALE_VC_ENABLE */
  3205. /* Slice: scale_vy_enable:*/
  3206. /* 0: bypass vertical luminance scaling unit */
  3207. /* 1: enable vertical luminance scaling unit */
  3208. #ifdef MRV_SRSZ_SCALE_VY_ENABLE
  3209. #define MRV_SRSZ_SCALE_VY_ENABLE_PROCESS 1 /* 1: enable vertical luminance scaling unit */
  3210. #define MRV_SRSZ_SCALE_VY_ENABLE_BYPASS 0 /* 0: bypass vertical luminance scaling unit */
  3211. #endif /* MRV_SRSZ_SCALE_VY_ENABLE */
  3212. /* Slice: scale_hc_enable:*/
  3213. /* 0: bypass horizontal chrominance scaling unit */
  3214. /* 1: enable horizontal chrominance scaling unit */
  3215. #ifdef MRV_SRSZ_SCALE_HC_ENABLE
  3216. #define MRV_SRSZ_SCALE_HC_ENABLE_PROCESS 1 /* 1: enable horizontal chrominance scaling unit */
  3217. #define MRV_SRSZ_SCALE_HC_ENABLE_BYPASS 0 /* 0: bypass horizontal chrominance scaling unit */
  3218. #endif /* MRV_SRSZ_SCALE_HC_ENABLE */
  3219. /* Slice: scale_hy_enable:*/
  3220. /* 0: bypass horizontal luminance scaling unit */
  3221. /* 1: enable horizontal luminance scaling unit */
  3222. #ifdef MRV_SRSZ_SCALE_HY_ENABLE
  3223. #define MRV_SRSZ_SCALE_HY_ENABLE_PROCESS 1 /* 1: enable horizontal luminance scaling unit */
  3224. #define MRV_SRSZ_SCALE_HY_ENABLE_BYPASS 0 /* 0: bypass horizontal luminance scaling unit */
  3225. #endif /* MRV_SRSZ_SCALE_HY_ENABLE */
  3226. /*****************************************************************************/
  3227. /**
  3228. * register: srsz_scale_hy: horizontal luminance scale factor register
  3229. * (0x00000004)
  3230. *
  3231. *****************************************************************************/
  3232. /* Slice: scale_hy:*/
  3233. /* This register is set to the horizontal luminance downscale factor or to */
  3234. /* the reciprocal of the horizontal luminance upscale factor */
  3235. #ifdef MRV_SRSZ_SCALE_HY
  3236. #endif /* MRV_SRSZ_SCALE_HY */
  3237. /*****************************************************************************/
  3238. /**
  3239. * register: srsz_scale_hcb: horizontal Cb scale factor register (0x00000008)
  3240. *
  3241. *****************************************************************************/
  3242. /* Slice: scale_hcb:*/
  3243. /* This register is set to the horizontal Cb downscale factor or to the */
  3244. /* reciprocal of the horizontal Cb upscale factor */
  3245. #ifdef MRV_SRSZ_SCALE_HCB
  3246. #endif /* MRV_SRSZ_SCALE_HCB */
  3247. /*****************************************************************************/
  3248. /**
  3249. * register: srsz_scale_hcr: horizontal Cr scale factor register (0x0000000c)
  3250. *
  3251. *****************************************************************************/
  3252. /* Slice: scale_hcr:*/
  3253. /* This register is set to the horizontal Cr downscale factor or to the */
  3254. /* reciprocal of the horizontal Cr upscale factor */
  3255. #ifdef MRV_SRSZ_SCALE_HCR
  3256. #endif /* MRV_SRSZ_SCALE_HCR */
  3257. /*****************************************************************************/
  3258. /**
  3259. * register: srsz_scale_vy: vertical luminance scale factor register (0x00000010)
  3260. *
  3261. *****************************************************************************/
  3262. /* Slice: scale_vy:*/
  3263. /* This register is set to the vertical luminance downscale factor or to the */
  3264. /* reciprocal of the vertical luminance upscale factor */
  3265. #ifdef MRV_SRSZ_SCALE_VY
  3266. #endif /* MRV_SRSZ_SCALE_VY */
  3267. /*****************************************************************************/
  3268. /**
  3269. * register: srsz_scale_vc: vertical chrominance scale factor register (0x00000014)
  3270. *
  3271. *****************************************************************************/
  3272. /* Slice: scale_vc:*/
  3273. /* This register is set to the vertical chrominance downscale factor or to the */
  3274. /* reciprocal of the vertical chrominance upscale factor */
  3275. #ifdef MRV_SRSZ_SCALE_VC
  3276. #endif /* MRV_SRSZ_SCALE_VC */
  3277. /*****************************************************************************/
  3278. /**
  3279. * register: srsz_phase_hy: horizontal luminance phase register (0x00000018)
  3280. *
  3281. *****************************************************************************/
  3282. /* Slice: phase_hy:*/
  3283. /* This register is set to the horizontal luminance phase offset */
  3284. #ifdef MRV_SRSZ_PHASE_HY
  3285. #endif /* MRV_SRSZ_PHASE_HY */
  3286. /*****************************************************************************/
  3287. /**
  3288. * register: srsz_phase_hc: horizontal chrominance phase register (0x0000001c)
  3289. *
  3290. *****************************************************************************/
  3291. /* Slice: phase_hc:*/
  3292. /* This register is set to the horizontal chrominance phase offset */
  3293. #ifdef MRV_SRSZ_PHASE_HC
  3294. #endif /* MRV_SRSZ_PHASE_HC */
  3295. /*****************************************************************************/
  3296. /**
  3297. * register: srsz_phase_vy: vertical luminance phase register (0x00000020)
  3298. *
  3299. *****************************************************************************/
  3300. /* Slice: phase_vy:*/
  3301. /* This register is set to the vertical luminance phase offset */
  3302. #ifdef MRV_SRSZ_PHASE_VY
  3303. #endif /* MRV_SRSZ_PHASE_VY */
  3304. /*****************************************************************************/
  3305. /**
  3306. * register: srsz_phase_vc: vertical chrominance phase register (0x00000024)
  3307. *
  3308. *****************************************************************************/
  3309. /* Slice: phase_vc:*/
  3310. /* This register is set to the vertical chrominance phase offset */
  3311. #ifdef MRV_SRSZ_PHASE_VC
  3312. #endif /* MRV_SRSZ_PHASE_VC */
  3313. /*****************************************************************************/
  3314. /**
  3315. * register: srsz_scale_lut_addr: Address pointer of up-scaling look up table
  3316. * (0x00000028)
  3317. *
  3318. *****************************************************************************/
  3319. /* Slice: scale_lut_addr:*/
  3320. /* Pointer to entry of lookup table */
  3321. #ifdef MRV_SRSZ_SCALE_LUT_ADDR
  3322. #endif /* MRV_SRSZ_SCALE_LUT_ADDR */
  3323. /*****************************************************************************/
  3324. /**
  3325. * register: srsz_scale_lut: Entry of up-scaling look up table (0x0000002c)
  3326. *
  3327. *****************************************************************************/
  3328. /* Slice: scale_lut:*/
  3329. /* Entry of lookup table at position scale_lut_addr. The lookup table must be */
  3330. /* filled with appropriate values before the up-scaling functionality can be */
  3331. /* used.*/
  3332. #ifdef MRV_SRSZ_SCALE_LUT
  3333. #endif /* MRV_SRSZ_SCALE_LUT */
  3334. /*****************************************************************************/
  3335. /**
  3336. * register: srsz_ctrl_shd: global control shadow register (0x0030)
  3337. *
  3338. *****************************************************************************/
  3339. /* Slice: scale_vc_up_shd:*/
  3340. /* 1: vertical chrominance upscaling selected */
  3341. /* 0: vertical chrominance downscaling selected */
  3342. #ifdef MRV_SRSZ_SCALE_VC_UP_SHD
  3343. #define MRV_SRSZ_SCALE_VC_UP_SHD_UPSCALE 1 /* 1: vertical chrominance upscaling selected */
  3344. #define MRV_SRSZ_SCALE_VC_UP_SHD_DOWNSCALE 0 /* 0: vertical chrominance downscaling selected */
  3345. #endif /* MRV_SRSZ_SCALE_VC_UP_SHD */
  3346. /* Slice: scale_vy_up_shd:*/
  3347. /* 1: vertical luminance upscaling selected */
  3348. /* 0: vertical luminance downscaling selected */
  3349. #ifdef MRV_SRSZ_SCALE_VY_UP_SHD
  3350. #define MRV_SRSZ_SCALE_VY_UP_SHD_UPSCALE 1 /* 1: vertical luminance upscaling selected */
  3351. #define MRV_SRSZ_SCALE_VY_UP_SHD_DOWNSCALE 0 /* 0: vertical luminance downscaling selected */
  3352. #endif /* MRV_SRSZ_SCALE_VY_UP_SHD */
  3353. /* Slice: scale_hc_up_shd:*/
  3354. /* 1: horizontal chrominance upscaling selected */
  3355. /* 0: horizontal chrominance downscaling selected */
  3356. #ifdef MRV_SRSZ_SCALE_HC_UP_SHD
  3357. #define MRV_SRSZ_SCALE_HC_UP_SHD_UPSCALE 1 /* 1: horizontal chrominance upscaling selected */
  3358. #define MRV_SRSZ_SCALE_HC_UP_SHD_DOWNSCALE 0 /* 0: horizontal chrominance downscaling selected */
  3359. #endif /* MRV_SRSZ_SCALE_HC_UP_SHD */
  3360. /* Slice: scale_hy_up_shd:*/
  3361. /* 1: horizontal luminance upscaling selected */
  3362. /* 0: horizontal luminance downscaling selected */
  3363. #ifdef MRV_SRSZ_SCALE_HY_UP_SHD
  3364. #define MRV_SRSZ_SCALE_HY_UP_SHD_UPSCALE 1 /* 1: horizontal luminance upscaling selected */
  3365. #define MRV_SRSZ_SCALE_HY_UP_SHD_DOWNSCALE 0 /* 0: horizontal luminance downscaling selected */
  3366. #endif /* MRV_SRSZ_SCALE_HY_UP_SHD */
  3367. /* Slice: scale_vc_enable_shd:*/
  3368. /* 0: bypass vertical chrominance scaling unit */
  3369. /* 1: enable vertical chrominance scaling unit */
  3370. #ifdef MRV_SRSZ_SCALE_VC_ENABLE_SHD
  3371. #define MRV_SRSZ_SCALE_VC_ENABLE_SHD_PROCESS 1 /* 1: enable vertical chrominance scaling unit */
  3372. #define MRV_SRSZ_SCALE_VC_ENABLE_SHD_BYPASS 0 /* 0: bypass vertical chrominance scaling unit */
  3373. #endif /* MRV_SRSZ_SCALE_VC_ENABLE_SHD */
  3374. /* Slice: scale_vy_enable_shd:*/
  3375. /* 0: bypass vertical luminance scaling unit */
  3376. /* 1: enable vertical luminance scaling unit */
  3377. #ifdef MRV_SRSZ_SCALE_VY_ENABLE_SHD
  3378. #define MRV_SRSZ_SCALE_VY_ENABLE_SHD_PROCESS 1 /* 1: enable vertical luminance scaling unit */
  3379. #define MRV_SRSZ_SCALE_VY_ENABLE_SHD_BYPASS 0 /* 0: bypass vertical luminance scaling unit */
  3380. #endif /* MRV_SRSZ_SCALE_VY_ENABLE_SHD */
  3381. /* Slice: scale_hc_enable_shd:*/
  3382. /* 0: bypass horizontal chrominance scaling unit */
  3383. /* 1: enable horizontal chrominance scaling unit */
  3384. #ifdef MRV_SRSZ_SCALE_HC_ENABLE_SHD
  3385. #define MRV_SRSZ_SCALE_HC_ENABLE_SHD_PROCESS 1 /* 1: enable horizontal chrominance scaling unit */
  3386. #define MRV_SRSZ_SCALE_HC_ENABLE_SHD_BYPASS 0 /* 0: bypass horizontal chrominance scaling unit */
  3387. #endif /* MRV_SRSZ_SCALE_HC_ENABLE_SHD */
  3388. /* Slice: scale_hy_enable_shd:*/
  3389. /* 0: bypass horizontal luminance scaling unit */
  3390. /* 1: enable horizontal luminance scaling unit */
  3391. #ifdef MRV_SRSZ_SCALE_HY_ENABLE_SHD
  3392. #define MRV_SRSZ_SCALE_HY_ENABLE_SHD_PROCESS 1 /* 1: enable horizontal luminance scaling unit */
  3393. #define MRV_SRSZ_SCALE_HY_ENABLE_SHD_BYPASS 0 /* 0: bypass horizontal luminance scaling unit */
  3394. #endif /* MRV_SRSZ_SCALE_HY_ENABLE_SHD */
  3395. /*****************************************************************************/
  3396. /**
  3397. * register: srsz_scale_hy_shd: horizontal luminance scale factor shadow
  3398. * register (0x00000034)
  3399. *
  3400. *****************************************************************************/
  3401. /* Slice: scale_hy_shd:*/
  3402. /* This register is set to the horizontal luminance downscale factor or to the */
  3403. /* reciprocal of the horizontal luminance upscale factor */
  3404. #ifdef MRV_SRSZ_SCALE_HY_SHD
  3405. #endif /* MRV_SRSZ_SCALE_HY_SHD */
  3406. /*****************************************************************************/
  3407. /**
  3408. * register: srsz_scale_hcb_shd: horizontal Cb scale factor shadow register
  3409. * (0x00000038)
  3410. *
  3411. *****************************************************************************/
  3412. /* Slice: scale_hcb_shd:*/
  3413. /* This register is set to the horizontal Cb downscale factor or to the */
  3414. /* reciprocal of the horizontal Cb upscale factor */
  3415. #ifdef MRV_SRSZ_SCALE_HCB_SHD
  3416. #endif /* MRV_SRSZ_SCALE_HCB_SHD */
  3417. /*****************************************************************************/
  3418. /**
  3419. * register: srsz_scale_hcr_shd: horizontal Cr scale factor shadow register
  3420. * (0x0000003c)
  3421. *
  3422. *****************************************************************************/
  3423. /* Slice: scale_hcr_shd:*/
  3424. /* This register is set to the horizontal Cr downscale factor or to the */
  3425. /* reciprocal of the horizontal Cr upscale factor */
  3426. #ifdef MRV_SRSZ_SCALE_HCR_SHD
  3427. #endif /* MRV_SRSZ_SCALE_HCR_SHD */
  3428. /*****************************************************************************/
  3429. /**
  3430. * register: srsz_scale_vy_shd: vertical luminance scale factor shadow register
  3431. * (0x00000040)
  3432. *
  3433. *****************************************************************************/
  3434. /* Slice: scale_vy_shd:*/
  3435. /* This register is set to the vertical luminance downscale factor or to the */
  3436. /* reciprocal of the vertical luminance upscale factor */
  3437. #ifdef MRV_SRSZ_SCALE_VY_SHD
  3438. #endif /* MRV_SRSZ_SCALE_VY_SHD */
  3439. /*****************************************************************************/
  3440. /**
  3441. * register: srsz_scale_vc_shd: vertical chrominance scale factor shadow
  3442. * register (0x00000044)
  3443. *
  3444. *****************************************************************************/
  3445. /* Slice: scale_vc_shd:*/
  3446. /* This register is set to the vertical chrominance downscale factor or to */
  3447. /* the reciprocal of the vertical chrominance upscale factor */
  3448. #ifdef MRV_SRSZ_SCALE_VC_SHD
  3449. #endif /* MRV_SRSZ_SCALE_VC_SHD */
  3450. /*****************************************************************************/
  3451. /**
  3452. * register: srsz_phase_hy_shd: horizontal luminance phase shadow register
  3453. * (0x00000048)
  3454. *
  3455. *****************************************************************************/
  3456. /* Slice: phase_hy_shd:*/
  3457. /* This register is set to the horizontal luminance phase offset */
  3458. #ifdef MRV_SRSZ_PHASE_HY_SHD
  3459. #endif /* MRV_SRSZ_PHASE_HY_SHD */
  3460. /*****************************************************************************/
  3461. /**
  3462. * register: srsz_phase_hc_shd: horizontal chrominance phase shadow register
  3463. * (0x0000004c)
  3464. *
  3465. *****************************************************************************/
  3466. /* Slice: phase_hc_shd:*/
  3467. /* This register is set to the horizontal chrominance phase offset */
  3468. #ifdef MRV_SRSZ_PHASE_HC_SHD
  3469. #endif /* MRV_SRSZ_PHASE_HC_SHD */
  3470. /*****************************************************************************/
  3471. /**
  3472. * register: srsz_phase_vy_shd: vertical luminance phase shadow register
  3473. * (0x00000050)
  3474. *
  3475. *****************************************************************************/
  3476. /* Slice: phase_vy_shd:*/
  3477. /* This register is set to the vertical luminance phase offset */
  3478. #ifdef MRV_SRSZ_PHASE_VY_SHD
  3479. #endif /* MRV_SRSZ_PHASE_VY_SHD */
  3480. /*****************************************************************************/
  3481. /**
  3482. * register: srsz_phase_vc_shd: vertical chrominance phase shadow register
  3483. * (0x00000054)
  3484. *
  3485. *****************************************************************************/
  3486. /* Slice: phase_vc_shd:*/
  3487. /* This register is set to the vertical chrominance phase offset */
  3488. #ifdef MRV_SRSZ_PHASE_VC_SHD
  3489. #endif /* MRV_SRSZ_PHASE_VC_SHD */
  3490. /*****************************************************************************/
  3491. /* Memory Interface Registers */
  3492. /*****************************************************************************/
  3493. /*****************************************************************************/
  3494. /**
  3495. * register: mi_ctrl: Global control register (0x0000)
  3496. *
  3497. *****************************************************************************/
  3498. /* Slice: sp_output_format:*/
  3499. /* Selects output format of self picture. For possible restrictions see sub-*/
  3500. /* chapter "Picture Orientation" in chapter "Self Path Output Programming".*/
  3501. /**/
  3502. /* 111: reserved */
  3503. /* 110: RGB 888 */
  3504. /* 101: RGB 666 */
  3505. /* 100: RGB 565 */
  3506. /**/
  3507. /* 011: YCbCr 4:4:4 */
  3508. /* 010: YCbCr 4:2:2 */
  3509. /* 001: YCbCr 4:2:0 */
  3510. /* 000: YCbCr 4:0:0 */
  3511. /**/
  3512. /* Note:*/
  3513. /* - Programmed value becomes effective immediately. So write to the */
  3514. /* register only if no picture data is sent to the self path.*/
  3515. /* - for RGB output format the SP input format must be YCbCr 4:2:2 */
  3516. #ifdef MRV_MI_SP_OUTPUT_FORMAT
  3517. #define MRV_MI_SP_OUTPUT_FORMAT_RGB888 6 /* 110: RGB 888 */
  3518. #define MRV_MI_SP_OUTPUT_FORMAT_RGB666 5 /* 101: RGB 666 */
  3519. #define MRV_MI_SP_OUTPUT_FORMAT_RGB565 4 /* 100: RGB 565 */
  3520. #define MRV_MI_SP_OUTPUT_FORMAT_YUV444 3 /* 011: YCbCr 4:4:4 */
  3521. #define MRV_MI_SP_OUTPUT_FORMAT_YUV422 2 /* 010: YCbCr 4:2:2 */
  3522. #define MRV_MI_SP_OUTPUT_FORMAT_YUV420 1 /* 001: YCbCr 4:2:0 */
  3523. #define MRV_MI_SP_OUTPUT_FORMAT_YUV400 0 /* 000: YCbCr 4:0:0 */
  3524. #endif /* MRV_MI_SP_OUTPUT_FORMAT */
  3525. /* Slice: sp_input_format:*/
  3526. /* Selects input format of self picture. For possible restrictions see sub-*/
  3527. /* chapter "Picture Orientation" in chapter "Self Path Output Programming".*/
  3528. /**/
  3529. /* 11: YCbCr 4:4:4 */
  3530. /* 10: YCbCr 4:2:2 */
  3531. /* 01: YCbCr 4:2:0 */
  3532. /* 00: YCbCr 4:0:0 */
  3533. /**/
  3534. /* Note:*/
  3535. /* - Programmed value becomes effective immediately. So write to the */
  3536. /* register only if no picture data is sent to the self path.*/
  3537. #ifdef MRV_MI_SP_INPUT_FORMAT
  3538. #define MRV_MI_SP_INPUT_FORMAT_YUV444 3 /* 11: YCbCr 4:4:4 */
  3539. #define MRV_MI_SP_INPUT_FORMAT_YUV422 2 /* 10: YCbCr 4:2:2 */
  3540. #define MRV_MI_SP_INPUT_FORMAT_YUV420 1 /* 01: YCbCr 4:2:0 */
  3541. #define MRV_MI_SP_INPUT_FORMAT_YUV400 0 /* 00: YCbCr 4:0:0 */
  3542. #endif /* MRV_MI_SP_INPUT_FORMAT */
  3543. /* Slice: sp_write_format:*/
  3544. /* Defines how YCbCr self picture data is written to memory. Ignored if */
  3545. /* RGB conversion is chosen. With RGB conversion active the output format */
  3546. /* is always interleaved.*/
  3547. /**/
  3548. /* 00: planar */
  3549. /* 01: semi planar, for YCbCr 4:2:x */
  3550. /* 10: interleaved (combined), for YCbCr 4:2:2 only */
  3551. /* 11: reserved */
  3552. /**/
  3553. /* Note:*/
  3554. /* - Programmed value becomes effective immediately. So write to the */
  3555. /* register only if no picture data is sent to the self path.*/
  3556. #ifdef MRV_MI_SP_WRITE_FORMAT
  3557. #define MRV_MI_SP_WRITE_FORMAT_PLANAR 0 /* 00: planar */
  3558. #define MRV_MI_SP_WRITE_FORMAT_SEMIPLANAR 1 /* 01: semi planar, for YCbCr 4:2:x */
  3559. #define MRV_MI_SP_WRITE_FORMAT_INTERLEAVED 2 /* 10: interleaved (combined), for YCbCr 4:2:2 only */
  3560. #define MRV_MI_SP_WRITE_FORMAT_RGB_INTERLEAVED 0 /* 00: hw expects a 0 in RGB mode */
  3561. #endif /* MRV_MI_SP_WRITE_FORMAT */
  3562. /* Slice: mp_write_format:*/
  3563. /* Defines how YCbCr main picture data is written to memory.*/
  3564. /* Ignored if JPEG data is chosen.*/
  3565. /* In YCbCr mode the following meaning is applicable */
  3566. /* 00: planar */
  3567. /* 01: semi planar, for YCbCr 4:2:x */
  3568. /* 10: interleaved (combined), for YCbCr 4:2:2 only */
  3569. /* 11: reserved */
  3570. /* In RAW data mode the following meaning is applicable */
  3571. /* 00: RAW 8 bit */
  3572. /* 01: reserved */
  3573. /* 10: RAW 12 bit */
  3574. /* 11: reserved */
  3575. /* Note:*/
  3576. /* - Programmed value becomes effective immediately. So write to the */
  3577. /* register only if no picture data is sent to the main path.*/
  3578. #ifdef MRV_MI_MP_WRITE_FORMAT
  3579. #define MRV_MI_MP_WRITE_FORMAT_PLANAR 0 /* 00: planar */
  3580. #define MRV_MI_MP_WRITE_FORMAT_SEMIPLANAR 1 /* 01: semi planar, for YCbCr 4:2:x */
  3581. #define MRV_MI_MP_WRITE_FORMAT_INTERLEAVED 2 /* 10: interleaved (combined), for YCbCr 4:2:2 only */
  3582. #define MRV_MI_MP_WRITE_FORMAT_RAW_8 0 /* 0x: RAW 8 bit */
  3583. #define MRV_MI_MP_WRITE_FORMAT_RAW_12 2 /* 1x: RAW 12 bit */
  3584. #endif /* MRV_MI_MP_WRITE_FORMAT */
  3585. /* Slice: bp_write_format:*/
  3586. /* In RAW data mode the following meaning is applicable */
  3587. /* 00: RAW 8 bit */
  3588. /* 01: RAW 10 bit */
  3589. /* 10: RAW 12 bit */
  3590. /* 11: reserved */
  3591. /* Note:*/
  3592. /* - Programmed value becomes effective immediately. So write to the */
  3593. /* register only if no picture data is sent to the main path.*/
  3594. #ifdef MRV_MI_BP_WRITE_RAWBIT
  3595. #define MRV_MI_BP_WRITE_RAWBIT_RAW_8 0 /* 0x: RAW 8 bit */
  3596. #define MRV_MI_BP_WRITE_RAWBIT_RAW_10 1 /* 01x: RAW 10 bit */
  3597. #define MRV_MI_BP_WRITE_RAWBIT_RAW_12 2 /* 10x: RAW 12 bit */
  3598. #endif /* MRV_MI_BP_WRITE_RAWBIT */
  3599. /* Slice: init_offset_en:*/
  3600. /* Enables updating of the offset counters shadow registers for */
  3601. /* main and self picture to the programmed register init values.*/
  3602. /**/
  3603. /* MI_MP/SP_Y/CB/CR_OFFS_CNT_INIT */
  3604. /* -> MI_MP/SP_Y/CB/CR_OFFS_CNT_SHD */
  3605. /**/
  3606. /* The update will be executed either when a forced software */
  3607. /* update occurs (in register MI_INIT bit cfg_upd = 1) or when */
  3608. /* an automatic config update signal arrives at the MI input port.*/
  3609. /* The latter is split into main and self picture. So only the */
  3610. /* corresponding main/self shadow registers are affected.*/
  3611. /* After a picture skip has been performed init_offset_en selects */
  3612. /* between skip restart and skip init mode (see bit skip in */
  3613. /* register MI_INIT).*/
  3614. #ifdef MRV_MI_INIT_OFFSET_EN
  3615. #endif /* MRV_MI_INIT_OFFSET_EN */
  3616. /* Slice: init_base_en:*/
  3617. /* Enables updating of the base address and buffer size shadow */
  3618. /* registers for main and self picture to the programmed register */
  3619. /* init values.*/
  3620. /**/
  3621. /* MI_MP/SP_Y/CB/CR_BASE_AD_INIT */
  3622. /* -> MI_MP/SP_Y/CB/CR_BASE_AD_SHD */
  3623. /**/
  3624. /* MI_MP/SP_Y/CB/CR_SIZE_INIT */
  3625. /* -> MI_MP/SP_Y/CB/CR_SIZE_SHD */
  3626. /**/
  3627. /* The update will be executed either when a forced software */
  3628. /* update occurs (in register MI_INIT bit cfg_upd = 1) or when */
  3629. /* an automatic config update signal arrives at the MI input port.*/
  3630. /* The latter is split into main and self picture. So only the */
  3631. /* corresponding main/self shadow registers are affected.*/
  3632. #ifdef MRV_MI_INIT_BASE_EN
  3633. #endif /* MRV_MI_INIT_BASE_EN */
  3634. /* Slice: burst_len_chrom:*/
  3635. /* Burst length for Cb or Cr data affecting write port.*/
  3636. /* 00: 4-beat bursts */
  3637. /* 01: 8-beat bursts */
  3638. /* 10: 16-beat bursts */
  3639. /* 11: reserved */
  3640. /* Ignored if 8- or 16-beat bursts are not supported. If rotation */
  3641. /* is active, then only 4-beat bursts will be generated in self path,*/
  3642. /* regardless of the setting here.*/
  3643. /**/
  3644. /* Note:*/
  3645. /* - Programmed value becomes effective immediately. So write to the */
  3646. /* register only if no picture data is sent to the main and self path.*/
  3647. #ifdef MRV_MI_BURST_LEN_CHROM
  3648. #define MRV_MI_BURST_LEN_CHROM_4 0 /* 0: 4-beat bursts */
  3649. #define MRV_MI_BURST_LEN_CHROM_8 1 /* 1: 8-beat bursts */
  3650. #define MRV_MI_BURST_LEN_CHROM_16 2 /* 2: 16-beat bursts */
  3651. #endif /* MRV_MI_BURST_LEN_CHROM */
  3652. /* Slice: burst_len_lum:*/
  3653. /* Burst length for Y, JPEG, or raw data affecting write port.*/
  3654. /* 00: 4-beat bursts */
  3655. /* 01: 8-beat bursts */
  3656. /* 10: 16-beat bursts */
  3657. /* 11: reserved */
  3658. /* Ignored if 8- or 16-beat bursts are not supported.*/
  3659. /**/
  3660. /* Note: Programmed value becomes effective immediately. So write to */
  3661. /* the register only if no picture data is sent to the main and self path.*/
  3662. #ifdef MRV_MI_BURST_LEN_LUM
  3663. #define MRV_MI_BURST_LEN_LUM_4 0 /* 0: 4-beat bursts */
  3664. #define MRV_MI_BURST_LEN_LUM_8 1 /* 1: 8-beat bursts */
  3665. #define MRV_MI_BURST_LEN_LUM_16 2 /* 2: 16-beat bursts */
  3666. #endif /* MRV_MI_BURST_LEN_LUM */
  3667. /* Slice: last_pixel_sig_en:*/
  3668. /* enables the last pixel signalization */
  3669. /* 1: enabled */
  3670. /* 0: disabled */
  3671. #ifdef MRV_MI_LAST_PIXEL_SIG_EN
  3672. #define MRV_MI_LAST_PIXEL_SIG_EN_ENABLE 1 /* 1: enable last pixel signalization */
  3673. #define MRV_MI_LAST_PIXEL_SIG_EN_DISABLE 0 /* 0: disable last pixel signalization */
  3674. #endif /* MRV_MI_LAST_PIXEL_SIG_EN */
  3675. /* Slice: 422noncosited:*/
  3676. /* Enables self path YCbCr422non-co-sited -> YCbCr444 interpolation */
  3677. /* 1: YCbCr422 data are non_co-sited (Cb and Cr samples */
  3678. /* are centered between Y samples) so modified interpolation */
  3679. /* is activated */
  3680. /* 0: YCbCr422 data are co-sited (Y0 Cb0 and Cr0 are */
  3681. /* sampled at the same position)*/
  3682. /**/
  3683. /* Note:*/
  3684. /* - Programmed value becomes effective immediately. So write to the */
  3685. /* register only if no picture data is sent to the self path.*/
  3686. #ifdef MRV_MI_422NONCOSITED
  3687. #endif /* MRV_MI_422NONCOSITED */
  3688. /* Slice: cbcr_full_range:*/
  3689. /* Enables CbCr full range for self path YCbCr -> RGB conversion */
  3690. /* 1: CbCr have full range (0..255)*/
  3691. /* 0: CbCr have compressed range range (16..240)*/
  3692. /**/
  3693. /* Note:*/
  3694. /* - Programmed value becomes effective immediately. So write to the */
  3695. /* register only if no picture data is sent to the self path.*/
  3696. #ifdef MRV_MI_CBCR_FULL_RANGE
  3697. #endif /* MRV_MI_CBCR_FULL_RANGE */
  3698. /* Slice: y_full_range:*/
  3699. /* Enables Y full range for self path YCbCr -> RGB conversion */
  3700. /* 1: Y has full range (0..255)*/
  3701. /* 0: Y has compressed range (16..235)*/
  3702. /**/
  3703. /* Note:*/
  3704. /* - Programmed value becomes effective immediately. So write to the */
  3705. /* register only if no picture data is sent to the self path.*/
  3706. #ifdef MRV_MI_Y_FULL_RANGE
  3707. #endif /* MRV_MI_Y_FULL_RANGE */
  3708. /* Slice: byte_swap:*/
  3709. /* Enables change of byte order of the 32 bit output word at write port */
  3710. /* 1: byte order is mirrored but the bit order within one byte doesn't */
  3711. /* change */
  3712. /* 0: no byte mirroring */
  3713. /**/
  3714. /* Note: Programmed value becomes effective immediately. So write to the */
  3715. /* register only if no picture data is sent to the main and self path.*/
  3716. #ifdef MRV_MI_BYTE_SWAP
  3717. #endif /* MRV_MI_BYTE_SWAP */
  3718. /* Slice: rot:*/
  3719. /* Rotation 90 degree counter clockwise of self picture, only in RGB */
  3720. /* mode. For picture orientation and operation modes see sub-chapter */
  3721. /* "Picture Orientation" in chapter "Self Path Output Programming".*/
  3722. /**/
  3723. /* For RGB 565 format the line length must be a multiple of 2. There */
  3724. /* are no restrictions for RGB 888/666.*/
  3725. /* 1: enabled */
  3726. /* 0: disabled */
  3727. /**/
  3728. /* Note:*/
  3729. /* - Programmed value becomes effective immediately. So write to the */
  3730. /* register only if no picture data is sent to the self path. In */
  3731. /* rotation mode only 4-beat bursts are supported for self-path.*/
  3732. #ifdef MRV_MI_ROT
  3733. #endif /* MRV_MI_ROT */
  3734. /* Slice: v_flip:*/
  3735. /* Vertical flipping of self picture. For picture orientation and */
  3736. /* operation modes see sub-chapter "Picture Orientation" in chapter */
  3737. /* "Self Path Output Programming". For Y component the line length */
  3738. /* in 4:2:x planar mode must be a multiple of 8, for all other component */
  3739. /* modes a multiple of 4 and for RGB 565 a multiple of 2. There are */
  3740. /* no restrictions for RGB 888/666.*/
  3741. /**/
  3742. /* 1: enabled */
  3743. /* 0: disabled */
  3744. /**/
  3745. /* Note:*/
  3746. /* - Programmed value becomes effective immediately. So write to the */
  3747. /* register only if no picture data is sent to the self path.*/
  3748. #ifdef MRV_MI_V_FLIP
  3749. #endif /* MRV_MI_V_FLIP */
  3750. /* Slice: h_flip:*/
  3751. /* Horizontal flipping of self picture. For picture orientation and */
  3752. /* operation modes see sub-chapter "Picture Orientation" in chapter */
  3753. /* "Self Path Output Programming".*/
  3754. /**/
  3755. /* For Y component the line length in 4:2:x planar mode must be a */
  3756. /* multiple of 8, for all other component modes a multiple of 4 and */
  3757. /* for RGB 565 a multiple of 2. There are no restrictions for RGB 888/666.*/
  3758. /**/
  3759. /* 1: enabled */
  3760. /* 0: disabled */
  3761. /**/
  3762. /* Note:*/
  3763. /* - Programmed value becomes effective immediately. So write to the */
  3764. /* register only if no picture data is sent to the self path.*/
  3765. #ifdef MRV_MI_H_FLIP
  3766. #endif /* MRV_MI_H_FLIP */
  3767. /* Programmed value becomes effective (visible in shadow register)*/
  3768. /* after a soft reset, a forced software update or an automatic */
  3769. /* config update. Affects MI_IN and MI_OUT module.*/
  3770. /* Slice: raw_enable:*/
  3771. /* Enables raw data */
  3772. /* Programmed value becomes effective (visible in control shadow register) after a soft reset or a forced software update.*/
  3773. /* Affects MI_IN and MI_OUT module.*/
  3774. #ifndef MRV_MI_RAW_ENABLE
  3775. #define MRV_MI_RAW_ENABLE
  3776. #define MRV_MI_RAW_ENABLE_MASK 0x00000008
  3777. #define MRV_MI_RAW_ENABLE_SHIFT 3
  3778. #endif /* MRV_MI_RAW_ENABLE */
  3779. /* Slice: dpcc_enable:*/
  3780. /* Enables DPCC data */
  3781. /* Programmed value becomes effective (visible in control shadow register) after a soft reset or a forced software.*/
  3782. /* Affects MI_IN and MI_OUT module.*/
  3783. #ifndef MRV_MI_DPCC_ENABLE
  3784. #define MRV_MI_DPCC_ENABLE
  3785. #define MRV_MI_DPCC_ENABLE_MASK 0x0000000C
  3786. #define MRV_MI_DPCC_ENABLE_SHIFT 2
  3787. #endif /* MRV_MI_JPEG_ENABLE */
  3788. /* Slice: jpeg_enable:*/
  3789. /* Enables JPEG data */
  3790. /* Programmed value becomes effective (visible in control shadow register) after a soft reset or a forced software.*/
  3791. /* Affects MI_IN and MI_OUT module.*/
  3792. #ifndef MRV_MI_JPEG_ENABLE
  3793. #define MRV_MI_JPEG_ENABLE
  3794. #define MRV_MI_JPEG_ENABLE_MASK 0x00000004
  3795. #define MRV_MI_JPEG_ENABLE_SHIFT 2
  3796. #endif /* MRV_MI_JPEG_ENABLE */
  3797. /* Slice: sp_enable:*/
  3798. /* Enables self picture data path.*/
  3799. /* Programmed value becomes effective (visible in control shadow register) after a soft reset, a forced software update or an automatic config update.*/
  3800. /* Affects MI_IN and MI_OUT module.*/
  3801. #ifndef MRV_MI_SP_ENABLE
  3802. #define MRV_MI_SP_ENABLE
  3803. #define MRV_MI_SP_ENABLE_MASK 0x00000002
  3804. #define MRV_MI_SP_ENABLE_SHIFT 1
  3805. #endif /* MRV_MI_SP_ENABLE */
  3806. /* Slice: mp_enable:*/
  3807. /* Enables main picture data path */
  3808. /* Programmed value becomes effective (visible in control shadow register) after a soft reset, a forced software update or an automatic config update.*/
  3809. /* Affects MI_IN and MI_OUT module.*/
  3810. #ifndef MRV_MI_MP_ENABLE
  3811. #define MRV_MI_MP_ENABLE
  3812. #define MRV_MI_MP_ENABLE_MASK 0x00000001
  3813. #define MRV_MI_MP_ENABLE_SHIFT 0
  3814. #endif /* MRV_MI_MP_ENABLE */
  3815. /* Slice: path_enable:*/
  3816. /* Enables data pathes of MI according to the following table:*/
  3817. /**/
  3818. /* 0000: disabled, no data is transferred */
  3819. /* 0001: YUV data output, mainpath only (mp_enable only)*/
  3820. /* 0010: self-path only, output data format depending on other settings (sp_enable only)*/
  3821. /* 0011: YUV data output in mainpath and self-path image data active */
  3822. /* 0100: JPEG data output, mainpath only (jpeg_enable only)*/
  3823. /* 0101: not allowed */
  3824. /* 0110: JPEG data output in mainpath and self-path image data active */
  3825. /* 0111: not allowed */
  3826. /* 1000: RAW data output, mainpath only (raw_enable only)*/
  3827. /* 1001: defect pixel data on self-path, image data on mainpath */
  3828. /* 1010: defect pixel data on mainpath, image data on self-path */
  3829. /* 1011: not allowed */
  3830. /* 1100: defect pixel data on self-path, JPEG data on mainpath */
  3831. /* 1101: defect pixel data on mainpath only */
  3832. /* 1110: defect pixel data on self-path only */
  3833. /* 1111: defect pixel data on self-path, RAW data on mainpath */
  3834. #ifdef MRV_MI_PATH_ENABLE
  3835. #endif /* MRV_MI_PATH_ENABLE */
  3836. /*****************************************************************************/
  3837. /**
  3838. * register: mi_init: Control register for address init and skip function
  3839. * (0x00000004)
  3840. *
  3841. *****************************************************************************/
  3842. /* Slice: mi_cfg_upd:*/
  3843. /* Forced configuration update. Leads to an immediate update of the shadow registers.*/
  3844. /* Depending on the two init enable bits in the MI_CTRL register (init_offset_en and */
  3845. /* init_base_en) the offset counter, base address and buffer size shadow registers */
  3846. /* are also updated.*/
  3847. #ifdef MRV_MI_MI_CFG_UPD
  3848. #endif /* MRV_MI_MI_CFG_UPD */
  3849. /* Slice: mp_output_format:*/
  3850. /* Selects output format of main picture.*/
  3851. /* 1xxx: Reserved */
  3852. /* 0111: RAW10 */
  3853. /* 0110: JPEG */
  3854. /* 0101: RAW8 */
  3855. /* 0100: RAW12 */
  3856. /**/
  3857. /* 0011: YCbCr 4:4:4 */
  3858. /* 0010: YCbCr 4:2:2 */
  3859. /* 0001: YCbCr 4:2:0 */
  3860. /* 0000: YCbCr 4:0:0 */
  3861. /**/
  3862. #ifdef MRV_MI_MP_OUTPUT_FORMAT
  3863. #define MRV_MI_MP_OUTPUT_FORMAT_RAW10 7 /* 0111: RAW10 */
  3864. #define MRV_MI_MP_OUTPUT_FORMAT_JPEG 6 /* 0110: JPEG */
  3865. #define MRV_MI_MP_OUTPUT_FORMAT_RAW8 5 /* 0101: RAW8 */
  3866. #define MRV_MI_MP_OUTPUT_FORMAT_RAW12 4 /* 0100: RAW12 */
  3867. #define MRV_MI_MP_OUTPUT_FORMAT_YUV444 3 /* 0011: YCbCr 4:4:4 */
  3868. #define MRV_MI_MP_OUTPUT_FORMAT_YUV422 2 /* 0010: YCbCr 4:2:2 */
  3869. #define MRV_MI_MP_OUTPUT_FORMAT_YUV420 1 /* 0001: YCbCr 4:2:0 */
  3870. #define MRV_MI_MP_OUTPUT_FORMAT_YUV400 0 /* 0000: YCbCr 4:0:0 */
  3871. #endif /* MRV_MI_MP_OUTPUT_FORMAT */
  3872. /* Slice: mi_skip:*/
  3873. /* Skip of current or next starting main picture:*/
  3874. /* Aborts writing of main picture image data of the current frame to RAM (after the */
  3875. /* current burst transmission has been completed). Further main picture data up to */
  3876. /* the end of the current frame are discarded.*/
  3877. /**/
  3878. /* No further makroblock line interrupt (mblk_line), no wrap around interrupt for */
  3879. /* main picture (wrap_mp_y/cb/cr) and no fill level interrupt (fill_mp_y) are generated.*/
  3880. /**/
  3881. /* Skip does not affect the generation of the main path frame end interrupt (mp_frame_end).*/
  3882. /* Skip does not affect the processing of self picture and its corresponding interrupts */
  3883. /* namely the self path frame end interrupt (sp_frame_end).*/
  3884. /**/
  3885. /* The byte counter (register MI_BYTE_CNT) is not affected. It produces the correct */
  3886. /* number of JPEG or RAW data bytes at the end of the current (skipped) frame.*/
  3887. /**/
  3888. /* After a skip has been performed the offset counter for the main picture at the start */
  3889. /* of the following frame are set depending on the bit init_offset_en in register MI_CTRL:*/
  3890. /**/
  3891. /* - Skip restart mode (init_offset_en = 0)*/
  3892. /* The offset counters of the main picture are restarted at the old start values of */
  3893. /* the previous skipped frame.*/
  3894. /**/
  3895. /* - Skip init mode (init_offset_en = 1)*/
  3896. /* The offset counters of the main picture are initialized with the register contents */
  3897. /* of the offset counter init registers without any additional forced software update */
  3898. /* or automatic config update.*/
  3899. #ifdef MRV_MI_MI_SKIP
  3900. #endif /* MRV_MI_MI_SKIP */
  3901. /*****************************************************************************/
  3902. /**
  3903. * register: mi_mp_y_base_ad_init: Base address for main picture Y component,
  3904. * JPEG or raw data (0x00000008)
  3905. *
  3906. *****************************************************************************/
  3907. /* Slice: mp_y_base_ad_init:*/
  3908. /* Base address of main picture Y component ring buffer, JPEG ring buffer or raw */
  3909. /* data ring buffer.*/
  3910. /**/
  3911. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  3912. /* after a soft reset, a forced software update or an automatic config update.*/
  3913. /**/
  3914. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  3915. #ifdef MRV_MI_MP_Y_BASE_AD_INIT
  3916. #define MRV_MI_MP_Y_BASE_AD_INIT_VALID_MASK (MRV_MI_MP_Y_BASE_AD_INIT_MASK & ~0x00000007)
  3917. #endif /* MRV_MI_MP_Y_BASE_AD_INIT */
  3918. /*****************************************************************************/
  3919. /**
  3920. * register: mi_mp_y_size_init: Size of main picture Y component, JPEG or raw
  3921. * data (0x0000000c)
  3922. *
  3923. *****************************************************************************/
  3924. /* Slice: mp_y_size_init:*/
  3925. /* Size of main picture Y component ring buffer, JPEG ring buffer or raw data */
  3926. /* ring buffer.*/
  3927. /**/
  3928. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  3929. /* after a soft reset, a forced software update or an automatic config update.*/
  3930. /**/
  3931. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  3932. #ifdef MRV_MI_MP_Y_SIZE_INIT
  3933. #define MRV_MI_MP_Y_SIZE_INIT_VALID_MASK (MRV_MI_MP_Y_SIZE_INIT_MASK & ~0x00000007)
  3934. #endif /* MRV_MI_MP_Y_SIZE_INIT */
  3935. /*****************************************************************************/
  3936. /**
  3937. * register: mi_mp_y_offs_cnt_init: Offset counter init value for main picture
  3938. * Y, JPEG or raw data (0x00000010)
  3939. *
  3940. *****************************************************************************/
  3941. /* Slice: mp_y_offs_cnt_init:*/
  3942. /* Offset counter init value of main picture Y component ring buffer, JPEG ring */
  3943. /* buffer or raw data ring buffer.*/
  3944. /**/
  3945. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  3946. /* after a soft reset, a forced software update or an automatic config update.*/
  3947. /**/
  3948. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  3949. #ifdef MRV_MI_MP_Y_OFFS_CNT_INIT
  3950. #define MRV_MI_MP_Y_OFFS_CNT_INIT_VALID_MASK (MRV_MI_MP_Y_OFFS_CNT_INIT_MASK & ~0x00000007)
  3951. #endif /* MRV_MI_MP_Y_OFFS_CNT_INIT */
  3952. /*****************************************************************************/
  3953. /**
  3954. * register: mi_mp_y_offs_cnt_start: Offset counter start value for main picture
  3955. * Y, JPEG or raw data (0x00000014)
  3956. *
  3957. *****************************************************************************/
  3958. /* Slice: mp_y_offs_cnt_start:*/
  3959. /* Offset counter value which points to the start address of the previously */
  3960. /* processed picture (main picture Y component, JPEG or raw data). Updated at */
  3961. /* frame end.*/
  3962. /**/
  3963. /* Note: A soft reset resets the contents to the reset value.*/
  3964. /**/
  3965. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  3966. #ifdef MRV_MI_MP_Y_OFFS_CNT_START
  3967. #define MRV_MI_MP_Y_OFFS_CNT_START_VALID_MASK (MRV_MI_MP_Y_OFFS_CNT_START_MASK & ~0x00000007)
  3968. #endif /* MRV_MI_MP_Y_OFFS_CNT_START */
  3969. /*****************************************************************************/
  3970. /**
  3971. * register: mi_mp_y_irq_offs_init: Fill level interrupt offset value for main
  3972. * picture Y, JPEG or raw data (0x00000018)
  3973. *
  3974. *****************************************************************************/
  3975. /* Slice: mp_y_irq_offs_init:*/
  3976. /* Reaching this programmed value by the current offset counter for addressing */
  3977. /* main picture Y component, JPEG or raw data leads to generation of fill level */
  3978. /* interrupt fill_mp_y.*/
  3979. /**/
  3980. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  3981. /* after a soft reset, a forced software update or an automatic config update.*/
  3982. /**/
  3983. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  3984. #ifdef MRV_MI_MP_Y_IRQ_OFFS_INIT
  3985. #define MRV_MI_MP_Y_IRQ_OFFS_INIT_VALID_MASK (MRV_MI_MP_Y_IRQ_OFFS_INIT_MASK & ~0x00000007)
  3986. #endif /* MRV_MI_MP_Y_IRQ_OFFS_INIT */
  3987. /*****************************************************************************/
  3988. /**
  3989. * register: mi_mp_cb_base_ad_init: Base address for main picture Cb component
  3990. * ring buffer (0x0000001c)
  3991. *
  3992. *****************************************************************************/
  3993. /* Slice: mp_cb_base_ad_init:*/
  3994. /* Base address of main picture Cb component ring buffer.*/
  3995. /**/
  3996. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  3997. /* after a soft reset, a forced software update or an automatic config update.*/
  3998. /**/
  3999. /* Note: Set control bit init_base_en before updating so that a forced or */
  4000. /* automatic update can take effect.*/
  4001. /**/
  4002. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4003. #ifdef MRV_MI_MP_CB_BASE_AD_INIT
  4004. #define MRV_MI_MP_CB_BASE_AD_INIT_VALID_MASK (MRV_MI_MP_CB_BASE_AD_INIT_MASK & ~0x00000007)
  4005. #endif /* MRV_MI_MP_CB_BASE_AD_INIT */
  4006. /*****************************************************************************/
  4007. /**
  4008. * register: mi_mp_cb_size_init: Size of main picture Cb component ring buffer
  4009. * (0x00000020)
  4010. *
  4011. *****************************************************************************/
  4012. /* Slice: mp_cb_size_init:*/
  4013. /* Size of main picture Cb component ring buffer.*/
  4014. /**/
  4015. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4016. /* after a soft reset, a forced software update or an automatic config update.*/
  4017. /**/
  4018. /* Note: Set control bit init_base_en before updating so that a forced or */
  4019. /* automatic update can take effect.*/
  4020. /**/
  4021. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4022. #ifdef MRV_MI_MP_CB_SIZE_INIT
  4023. #define MRV_MI_MP_CB_SIZE_INIT_VALID_MASK (MRV_MI_MP_CB_SIZE_INIT_MASK & ~0x00000007)
  4024. #endif /* MRV_MI_MP_CB_SIZE_INIT */
  4025. /*****************************************************************************/
  4026. /**
  4027. * register: mi_mp_cb_offs_cnt_init: Offset counter init value for main picture
  4028. * Cb component ring buffer (0x00000024)
  4029. *
  4030. *****************************************************************************/
  4031. /* Slice: mp_cb_offs_cnt_init:*/
  4032. /* Offset counter init value of main picture Cb component ring buffer.*/
  4033. /**/
  4034. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4035. /* after a soft reset, a forced software update or an automatic config update.*/
  4036. /**/
  4037. /* Note: Set control bit init_base_en before updating so that a forced or automatic */
  4038. /* update can take effect. Check exceptional handling in skip modes.*/
  4039. /**/
  4040. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4041. #ifdef MRV_MI_MP_CB_OFFS_CNT_INIT
  4042. #define MRV_MI_MP_CB_OFFS_CNT_INIT_VALID_MASK (MRV_MI_MP_CB_OFFS_CNT_INIT_MASK & ~0x00000007)
  4043. #endif /* MRV_MI_MP_CB_OFFS_CNT_INIT */
  4044. /*****************************************************************************/
  4045. /**
  4046. * register: mi_mp_cb_offs_cnt_start: Offset counter start value for main
  4047. * picture Cb component ring buffer (0x00000028)
  4048. *
  4049. *****************************************************************************/
  4050. /* Slice: mp_cb_offs_cnt_start:*/
  4051. /* Offset counter value which points to the start address of the previously */
  4052. /* processed picture (main picture Cb component). Updated at frame end.*/
  4053. /**/
  4054. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4055. #ifdef MRV_MI_MP_CB_OFFS_CNT_START
  4056. #define MRV_MI_MP_CB_OFFS_CNT_START_VALID_MASK (MRV_MI_MP_CB_OFFS_CNT_START_MASK & ~0x00000007)
  4057. #endif /* MRV_MI_MP_CB_OFFS_CNT_START */
  4058. /*****************************************************************************/
  4059. /**
  4060. * register: mi_mp_cr_base_ad_init: Base address for main picture Cr component
  4061. * ring buffer (0x0000002c)
  4062. *
  4063. *****************************************************************************/
  4064. /* Slice: mp_cr_base_ad_init:*/
  4065. /* Base address of main picture Cr component ring buffer.*/
  4066. /**/
  4067. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4068. /* after a soft reset, a forced software update or an automatic config update.*/
  4069. /**/
  4070. /* Note:*/
  4071. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4072. /* update can take effect.*/
  4073. /**/
  4074. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4075. #ifdef MRV_MI_MP_CR_BASE_AD_INIT
  4076. #define MRV_MI_MP_CR_BASE_AD_INIT_VALID_MASK (MRV_MI_MP_CR_BASE_AD_INIT_MASK & ~0x00000007)
  4077. #endif /* MRV_MI_MP_CR_BASE_AD_INIT */
  4078. /*****************************************************************************/
  4079. /**
  4080. * register: mi_mp_cr_size_init: Size of main picture Cr component ring buffer
  4081. * (0x00000030)
  4082. *
  4083. *****************************************************************************/
  4084. /* Slice: mp_cr_size_init:*/
  4085. /* Size of main picture Cr component ring buffer.*/
  4086. /**/
  4087. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4088. /* after a soft reset, a forced software update or an automatic config update.*/
  4089. /**/
  4090. /* Note:*/
  4091. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4092. /* update can take effect.*/
  4093. /**/
  4094. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4095. #ifdef MRV_MI_MP_CR_SIZE_INIT
  4096. #define MRV_MI_MP_CR_SIZE_INIT_VALID_MASK (MRV_MI_MP_CR_SIZE_INIT_MASK & ~0x00000007)
  4097. #endif /* MRV_MI_MP_CR_SIZE_INIT */
  4098. /*****************************************************************************/
  4099. /**
  4100. * register: mi_mp_cr_offs_cnt_init: Offset counter init value for main
  4101. * picture Cr component ring buffer (0x00000034)
  4102. *
  4103. *****************************************************************************/
  4104. /* Slice: mp_cr_offs_cnt_init:*/
  4105. /* Offset counter init value of main picture Cr component ring buffer.*/
  4106. /**/
  4107. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4108. /* after a soft reset, a forced software update or an automatic config update.*/
  4109. /**/
  4110. /* Note:*/
  4111. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4112. /* update can take effect. Check exceptional handling in skip modes.*/
  4113. /**/
  4114. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4115. #ifdef MRV_MI_MP_CR_OFFS_CNT_INIT
  4116. #define MRV_MI_MP_CR_OFFS_CNT_INIT_VALID_MASK (MRV_MI_MP_CR_OFFS_CNT_INIT_MASK & ~0x00000007)
  4117. #endif /* MRV_MI_MP_CR_OFFS_CNT_INIT */
  4118. /*****************************************************************************/
  4119. /**
  4120. * register: mi_mp_cr_offs_cnt_start: Offset counter start value for main
  4121. * picture Cr component ring buffer (0x00000038)
  4122. *
  4123. *****************************************************************************/
  4124. /* Slice: mp_cr_offs_cnt_start:*/
  4125. /* Offset counter value which points to the start address of the previously */
  4126. /* processed picture (main picture Cr component). Updated at frame end.*/
  4127. /**/
  4128. /* Note:*/
  4129. /* - Soft reset will reset the contents to reset value.*/
  4130. /**/
  4131. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4132. #ifdef MRV_MI_MP_CR_OFFS_CNT_START
  4133. #define MRV_MI_MP_CR_OFFS_CNT_START_VALID_MASK (MRV_MI_MP_CR_OFFS_CNT_START_MASK & ~0x00000007)
  4134. #endif /* MRV_MI_MP_CR_OFFS_CNT_START */
  4135. /*****************************************************************************/
  4136. /**
  4137. * register: mi_sp_y_base_ad_init: Base address for self picture Y component
  4138. * ring buffer (0x0000003c)
  4139. *
  4140. *****************************************************************************/
  4141. /* Slice: sp_y_base_ad_init:*/
  4142. /* Base address of self picture Y component ring buffer.*/
  4143. /**/
  4144. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4145. /* after a soft reset, a forced software update or an automatic config update.*/
  4146. /**/
  4147. /* Note:*/
  4148. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4149. /* update can take effect.*/
  4150. /**/
  4151. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4152. #ifdef MRV_MI_SP_Y_BASE_AD_INIT
  4153. #define MRV_MI_SP_Y_BASE_AD_INIT_VALID_MASK (MRV_MI_SP_Y_BASE_AD_INIT_MASK & ~0x00000007)
  4154. #endif /* MRV_MI_SP_Y_BASE_AD_INIT */
  4155. /*****************************************************************************/
  4156. /**
  4157. * register: mi_sp_y_size_init: Size of self picture Y component ring buffer
  4158. * (0x00000040)
  4159. *
  4160. *****************************************************************************/
  4161. /* Slice: sp_y_size_init:*/
  4162. /* Size of self picture Y component ring buffer.*/
  4163. /**/
  4164. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4165. /* after a soft reset, a forced software update or an automatic config update.*/
  4166. /**/
  4167. /* Note: Set control bit init_base_en before updating so that a forced or */
  4168. /* automatic update can take effect.*/
  4169. /**/
  4170. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4171. #ifdef MRV_MI_SP_Y_SIZE_INIT
  4172. #define MRV_MI_SP_Y_SIZE_INIT_VALID_MASK (MRV_MI_SP_Y_SIZE_INIT_MASK & ~0x00000007)
  4173. #endif /* MRV_MI_SP_Y_SIZE_INIT */
  4174. /*****************************************************************************/
  4175. /**
  4176. * register: mi_sp_y_offs_cnt_init: Offset counter init value for self
  4177. * picture Y component ring buffer (0x00000044)
  4178. *
  4179. *****************************************************************************/
  4180. /* Slice: sp_y_offs_cnt_init:*/
  4181. /* Offset counter init value of self picture Y component ring buffer.*/
  4182. /**/
  4183. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4184. /* after a soft reset, a forced software update or an automatic config update.*/
  4185. /**/
  4186. /* Note: Set control bit init_base_en before updating so that a forced or */
  4187. /* automatic update can take effect.*/
  4188. /**/
  4189. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4190. #ifdef MRV_MI_SP_Y_OFFS_CNT_INIT
  4191. #define MRV_MI_SP_Y_OFFS_CNT_INIT_VALID_MASK (MRV_MI_SP_Y_OFFS_CNT_INIT_MASK & ~0x00000007)
  4192. #endif /* MRV_MI_SP_Y_OFFS_CNT_INIT */
  4193. /*****************************************************************************/
  4194. /**
  4195. * register: mi_sp_y_offs_cnt_start: Offset counter start value for self
  4196. * picture Y component ring buffer (0x00000048)
  4197. *
  4198. *****************************************************************************/
  4199. /* Slice: sp_y_offs_cnt_start:*/
  4200. /* Offset counter value which points to the start address of the previously */
  4201. /* processed picture (self picture Y component). Updated at frame end.*/
  4202. /**/
  4203. /* Note:*/
  4204. /* - Soft reset will reset the contents to reset value.*/
  4205. /**/
  4206. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4207. #ifdef MRV_MI_SP_Y_OFFS_CNT_START
  4208. #define MRV_MI_SP_Y_OFFS_CNT_START_VALID_MASK (MRV_MI_SP_Y_OFFS_CNT_START_MASK & ~0x00000007)
  4209. #endif /* MRV_MI_SP_Y_OFFS_CNT_START */
  4210. /*****************************************************************************/
  4211. /**
  4212. * register: mi_sp_y_llength: Line length of self picture Y component (0x0000004c)
  4213. *
  4214. *****************************************************************************/
  4215. /* Slice: sp_y_llength:*/
  4216. /* Line length of self picture Y component or RGB picture in pixel, also */
  4217. /* known as line stride.*/
  4218. /**/
  4219. /* If no line stride is used, line length must match image width.*/
  4220. /**/
  4221. /* For Y component the line length in 4:2:x planar mode must be a multiple of 8,*/
  4222. /* for all other component modes a multiple of 4 and for RGB 565 a multiple of 2.*/
  4223. /* There are no restrictions for RGB 888/666.*/
  4224. /**/
  4225. /* In planar mode the line length of the Cb and Cr component is assumed according */
  4226. /* to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi */
  4227. /* planar 4:2:x mode the line length of the Cb and Cr component is assumed the */
  4228. /* same size.*/
  4229. /**/
  4230. /* Note:*/
  4231. /* - Line length always refers to the line length of the output image. This */
  4232. /* is particularly important when rotating.*/
  4233. /**/
  4234. /* Note:*/
  4235. /* - Programmed value becomes effective immediately. So write to the register */
  4236. /* only if no picture data is sent to the self path.*/
  4237. #ifdef MRV_MI_SP_Y_LLENGTH
  4238. #define MRV_MI_SP_Y_LLENGTH_VALID_MASK (MRV_MI_SP_Y_LLENGTH_MASK & ~0x00000000)
  4239. #endif /* MRV_MI_SP_Y_LLENGTH */
  4240. /*****************************************************************************/
  4241. /**
  4242. * register: mi_sp_cb_base_ad_init: Base address for self picture Cb component
  4243. * ring buffer (0x00000050)
  4244. *
  4245. *****************************************************************************/
  4246. /* Slice: sp_cb_base_ad_init:*/
  4247. /* Base address of self picture Cb component ring buffer.*/
  4248. /**/
  4249. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4250. /* after a soft reset, a forced software update or an automatic config update.*/
  4251. /**/
  4252. /* Note: Set control bit init_base_en before updating so that a forced or */
  4253. /* automatic update can take effect.*/
  4254. /**/
  4255. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4256. #ifdef MRV_MI_SP_CB_BASE_AD_INIT
  4257. #define MRV_MI_SP_CB_BASE_AD_INIT_VALID_MASK (MRV_MI_SP_CB_BASE_AD_INIT_MASK & ~0x00000007)
  4258. #endif /* MRV_MI_SP_CB_BASE_AD_INIT */
  4259. /*****************************************************************************/
  4260. /**
  4261. * register: mi_sp_cb_size_init: Size of self picture Cb component ring buffer
  4262. * (0x00000054)
  4263. *
  4264. *****************************************************************************/
  4265. /* Slice: sp_cb_size_init:*/
  4266. /* Size of self picture Cb component ring buffer.*/
  4267. /**/
  4268. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4269. /* after a soft reset, a forced software update or an automatic config update.*/
  4270. /**/
  4271. /* Note:*/
  4272. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4273. /* update can take effect.*/
  4274. /**/
  4275. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4276. #ifdef MRV_MI_SP_CB_SIZE_INIT
  4277. #define MRV_MI_SP_CB_SIZE_INIT_VALID_MASK (MRV_MI_SP_CB_SIZE_INIT_MASK & ~0x00000007)
  4278. #endif /* MRV_MI_SP_CB_SIZE_INIT */
  4279. /*****************************************************************************/
  4280. /**
  4281. * register: mi_sp_cb_offs_cnt_init: Offset counter init value for self picture
  4282. * Cb component ring buffer (0x00000058)
  4283. *
  4284. *****************************************************************************/
  4285. /* Slice: sp_cb_offs_cnt_init:*/
  4286. /* Offset counter init value of self picture Cb component ring buffer.*/
  4287. /**/
  4288. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4289. /* after a soft reset, a forced software update or an automatic config update.*/
  4290. /**/
  4291. /* Note:*/
  4292. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4293. /* update can take effect.*/
  4294. /**/
  4295. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4296. #ifdef MRV_MI_SP_CB_OFFS_CNT_INIT
  4297. #define MRV_MI_SP_CB_OFFS_CNT_INIT_VALID_MASK (MRV_MI_SP_CB_OFFS_CNT_INIT_MASK & ~0x00000007)
  4298. #endif /* MRV_MI_SP_CB_OFFS_CNT_INIT */
  4299. /*****************************************************************************/
  4300. /**
  4301. * register: mi_sp_cb_offs_cnt_start: Offset counter start value for self
  4302. * picture Cb component ring buffer (0x0000005c)
  4303. *
  4304. *****************************************************************************/
  4305. /* Slice: sp_cb_offs_cnt_start:*/
  4306. /**/
  4307. /* Offset counter value which points to the start address of the previously */
  4308. /* processed picture (self picture Cb component). Updated at frame end.*/
  4309. /**/
  4310. /* Note:*/
  4311. /* - Soft reset will reset the contents to reset value.*/
  4312. /**/
  4313. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4314. #ifdef MRV_MI_SP_CB_OFFS_CNT_START
  4315. #define MRV_MI_SP_CB_OFFS_CNT_START_VALID_MASK (MRV_MI_SP_CB_OFFS_CNT_START_MASK & ~0x00000007)
  4316. #endif /* MRV_MI_SP_CB_OFFS_CNT_START */
  4317. /*****************************************************************************/
  4318. /**
  4319. * register: mi_sp_cr_base_ad_init: Base address for self picture Cr component
  4320. * ring buffer (0x00000060)
  4321. *
  4322. *****************************************************************************/
  4323. /* Slice: sp_cr_base_ad_init:*/
  4324. /* Base address of self picture Cr component ring buffer.*/
  4325. /**/
  4326. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4327. /* after a soft reset, a forced software update or an automatic config update.*/
  4328. /**/
  4329. /* Note:*/
  4330. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4331. /* update can take effect.*/
  4332. /**/
  4333. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4334. #ifdef MRV_MI_SP_CR_BASE_AD_INIT
  4335. #define MRV_MI_SP_CR_BASE_AD_INIT_VALID_MASK (MRV_MI_SP_CR_BASE_AD_INIT_MASK & ~0x00000007)
  4336. #endif /* MRV_MI_SP_CR_BASE_AD_INIT */
  4337. /*****************************************************************************/
  4338. /**
  4339. * register: mi_sp_cr_size_init: Size of self picture Cr component ring buffer
  4340. * (0x00000064)
  4341. *
  4342. *****************************************************************************/
  4343. /* Slice: sp_cr_size_init:*/
  4344. /* Size of self picture Cr component ring buffer.*/
  4345. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4346. /* after a soft reset, a forced software update or an automatic config update.*/
  4347. /**/
  4348. /* Note:*/
  4349. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4350. /* update can take effect.*/
  4351. /**/
  4352. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4353. #ifdef MRV_MI_SP_CR_SIZE_INIT
  4354. #define MRV_MI_SP_CR_SIZE_INIT_VALID_MASK (MRV_MI_SP_CR_SIZE_INIT_MASK & ~0x00000007)
  4355. #endif /* MRV_MI_SP_CR_SIZE_INIT */
  4356. /*****************************************************************************/
  4357. /**
  4358. * register: mi_sp_cr_offs_cnt_init: Offset counter init value for self
  4359. * picture Cr component ring buffer (0x00000068)
  4360. *
  4361. *****************************************************************************/
  4362. /* Slice: sp_cr_offs_cnt_init:*/
  4363. /* Offset counter init value of self picture Cr component ring buffer.*/
  4364. /**/
  4365. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4366. /* after a soft reset, a forced software update or an automatic config update.*/
  4367. /**/
  4368. /* Note:*/
  4369. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4370. /* update can take effect.*/
  4371. /**/
  4372. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4373. #ifdef MRV_MI_SP_CR_OFFS_CNT_INIT
  4374. #define MRV_MI_SP_CR_OFFS_CNT_INIT_VALID_MASK (MRV_MI_SP_CR_OFFS_CNT_INIT_MASK & ~0x00000007)
  4375. #endif /* MRV_MI_SP_CR_OFFS_CNT_INIT */
  4376. /*****************************************************************************/
  4377. /**
  4378. * register: mi_sp_cr_offs_cnt_start: Offset counter start value for self
  4379. * picture Cr component ring buffer (0x0000006c)
  4380. *
  4381. *****************************************************************************/
  4382. /* Slice: sp_cr_offs_cnt_start:*/
  4383. /* Offset counter value which points to the start address of the previously */
  4384. /* processed picture (self picture Cr component). Updated at frame end.*/
  4385. /**/
  4386. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4387. #ifdef MRV_MI_SP_CR_OFFS_CNT_START
  4388. #define MRV_MI_SP_CR_OFFS_CNT_START_VALID_MASK (MRV_MI_SP_CR_OFFS_CNT_START_MASK & ~0x00000007)
  4389. #endif /* MRV_MI_SP_CR_OFFS_CNT_START */
  4390. /*****************************************************************************/
  4391. /**
  4392. * register: mi_byte_cnt: Counter value of JPEG or RAW data bytes (0x00000070)
  4393. *
  4394. *****************************************************************************/
  4395. /* Slice: byte_cnt:*/
  4396. /* Counter value specifies the number of JPEG or RAW data bytes of the last */
  4397. /* transmitted frame. Updated at frame end.*/
  4398. /**/
  4399. /* A soft reset will set the byte counter to zero.*/
  4400. #ifdef MRV_MI_BYTE_CNT
  4401. #endif /* MRV_MI_BYTE_CNT */
  4402. /*****************************************************************************/
  4403. /**
  4404. * register: mi_ctrl_shd: global control internal shadow register (0x00000074)
  4405. *
  4406. *****************************************************************************/
  4407. /* Slice: path_enable_out:*/
  4408. /* path_enable shadow register for module MI_OUT (former raw_enable_out,*/
  4409. /* jpeg_enable_out, sp_enable_out, mp_enable_out)*/
  4410. #ifdef MRV_MI_PATH_ENABLE_OUT
  4411. #endif /* MRV_MI_PATH_ENABLE_OUT */
  4412. /* Slice: path_enable_in:*/
  4413. /* path_enable shadow register for module MI_IN (former raw_enable_in,*/
  4414. /* jpeg_enable_in, sp_enable_in, mp_enable_in)*/
  4415. #ifdef MRV_MI_PATH_ENABLE_IN
  4416. #endif /* MRV_MI_PATH_ENABLE_IN */
  4417. /*****************************************************************************/
  4418. /**
  4419. * register: mi_mp_y_base_ad_shd: Base address shadow register for main
  4420. * picture Y component, JPEG or raw data ring buffer (0x00000078)
  4421. *
  4422. *****************************************************************************/
  4423. /* Slice: mp_y_base_ad:*/
  4424. /* Base address of main picture Y component ring buffer, JPEG ring buffer or */
  4425. /* raw data ring buffer.*/
  4426. /**/
  4427. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4428. #ifdef MRV_MI_MP_Y_BASE_AD
  4429. #define MRV_MI_MP_Y_BASE_AD_VALID_MASK (MRV_MI_MP_Y_BASE_AD_MASK & ~0x00000007)
  4430. #endif /* MRV_MI_MP_Y_BASE_AD */
  4431. /*****************************************************************************/
  4432. /**
  4433. * register: mi_mp_y_size_shd: Size shadow register of main picture Y component,
  4434. * JPEG or raw data (0x0000007c)
  4435. *
  4436. *****************************************************************************/
  4437. /* Slice: mp_y_size:*/
  4438. /* Size of main picture Y component ring buffer, JPEG ring buffer or raw data */
  4439. /* ring buffer.*/
  4440. /**/
  4441. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4442. #ifdef MRV_MI_MP_Y_SIZE
  4443. #define MRV_MI_MP_Y_SIZE_VALID_MASK (MRV_MI_MP_Y_SIZE_MASK & ~0x00000007)
  4444. #endif /* MRV_MI_MP_Y_SIZE */
  4445. /*****************************************************************************/
  4446. /**
  4447. * register: mi_mp_y_offs_cnt_shd: Current offset counter of main picture Y
  4448. * component, JPEG or raw data ring buffer (0x00000080)
  4449. *
  4450. *****************************************************************************/
  4451. /* Slice: mp_y_offs_cnt:*/
  4452. /* Current offset counter of main picture Y component, JPEG or raw data ring */
  4453. /* buffer for address generation */
  4454. /**/
  4455. /* Note:*/
  4456. /* - Soft reset will reset the contents to reset value.*/
  4457. /**/
  4458. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4459. #ifdef MRV_MI_MP_Y_OFFS_CNT
  4460. #define MRV_MI_MP_Y_OFFS_CNT_VALID_MASK (MRV_MI_MP_Y_OFFS_CNT_MASK & ~0x00000007)
  4461. #endif /* MRV_MI_MP_Y_OFFS_CNT */
  4462. /*****************************************************************************/
  4463. /**
  4464. * register: mi_mp_y_irq_offs_shd: Shadow register of fill level interrupt
  4465. * offset value for main picture Y component, JPEG or raw data
  4466. * (0x00000084)
  4467. *
  4468. *****************************************************************************/
  4469. /* Slice: mp_y_irq_offs:*/
  4470. /* Reaching this offset value by the current offset counter for addressing */
  4471. /* main picture Y component, JPEG or raw data leads to generation of fill */
  4472. /* level interrupt fill_mp_y.*/
  4473. /**/
  4474. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4475. #ifdef MRV_MI_MP_Y_IRQ_OFFS
  4476. #endif /* MRV_MI_MP_Y_IRQ_OFFS */
  4477. /*****************************************************************************/
  4478. /**
  4479. * register: mi_mp_cb_base_ad_shd: Base address shadow register for main
  4480. * picture Cb component ring buffer (0x00000088)
  4481. *
  4482. *****************************************************************************/
  4483. /* Slice: mp_cb_base_ad:*/
  4484. /* Base address of main picture Cb component ring buffer.*/
  4485. /**/
  4486. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4487. #ifdef MRV_MI_MP_CB_BASE_AD
  4488. #endif /* MRV_MI_MP_CB_BASE_AD */
  4489. /*****************************************************************************/
  4490. /**
  4491. * register: mi_mp_cb_size_shd: Size shadow register of main picture Cb
  4492. * component ring buffer (0x0000008c)
  4493. *
  4494. *****************************************************************************/
  4495. /* Slice: mp_cb_size:*/
  4496. /* Size of main picture Cb component ring buffer.*/
  4497. /**/
  4498. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4499. #ifdef MRV_MI_MP_CB_SIZE
  4500. #endif /* MRV_MI_MP_CB_SIZE */
  4501. /*****************************************************************************/
  4502. /**
  4503. * register: mi_mp_cb_offs_cnt_shd: Current offset counter of main picture Cb
  4504. * component ring buffer (0x00000090)
  4505. *
  4506. *****************************************************************************/
  4507. /* Slice: mp_cb_offs_cnt:*/
  4508. /* Current offset counter of main picture Cb component ring buffer for address */
  4509. /* generation */
  4510. /**/
  4511. /* Note:*/
  4512. /* - Soft reset will reset the contents to reset value.*/
  4513. /**/
  4514. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4515. #ifdef MRV_MI_MP_CB_OFFS_CNT
  4516. #endif /* MRV_MI_MP_CB_OFFS_CNT */
  4517. /*****************************************************************************/
  4518. /**
  4519. * register: mi_mp_cr_base_ad_shd: Base address shadow register for main
  4520. * picture Cr component ring buffer (0x00000094)
  4521. *
  4522. *****************************************************************************/
  4523. /* Slice: mp_cr_base_ad:*/
  4524. /* Base address of main picture Cr component ring buffer.*/
  4525. /**/
  4526. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4527. #ifdef MRV_MI_MP_CR_BASE_AD
  4528. #endif /* MRV_MI_MP_CR_BASE_AD */
  4529. /*****************************************************************************/
  4530. /**
  4531. * register: mi_mp_cr_size_shd: Size shadow register of main picture Cr
  4532. * component ring buffer (0x00000098)
  4533. *
  4534. *****************************************************************************/
  4535. /* Slice: mp_cr_size:*/
  4536. /* Size of main picture Cr component ring buffer.*/
  4537. /**/
  4538. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4539. #ifdef MRV_MI_MP_CR_SIZE
  4540. #endif /* MRV_MI_MP_CR_SIZE */
  4541. /*****************************************************************************/
  4542. /**
  4543. * register: mi_mp_cr_offs_cnt_shd: Current offset counter of main picture Cr
  4544. * component ring buffer (0x0000009c)
  4545. *
  4546. *****************************************************************************/
  4547. /* Slice: mp_cr_offs_cnt:*/
  4548. /* Current offset counter of main picture Cr component ring buffer for */
  4549. /* address generation */
  4550. /**/
  4551. /* Note:*/
  4552. /* - Soft reset will reset the contents to reset value.*/
  4553. /**/
  4554. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4555. #ifdef MRV_MI_MP_CR_OFFS_CNT
  4556. #endif /* MRV_MI_MP_CR_OFFS_CNT */
  4557. /*****************************************************************************/
  4558. /**
  4559. * register: mi_sp_y_base_ad_shd: Base address shadow register for self
  4560. * picture Y component ring buffer (0x000000a0)
  4561. *
  4562. *****************************************************************************/
  4563. /* Slice: sp_y_base_ad:*/
  4564. /* Base address of self picture Y component ring buffer.*/
  4565. /**/
  4566. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4567. #ifdef MRV_MI_SP_Y_BASE_AD
  4568. #endif /* MRV_MI_SP_Y_BASE_AD */
  4569. /*****************************************************************************/
  4570. /**
  4571. * register: mi_sp_y_size_shd: Size shadow register of self picture Y
  4572. * component ring buffer (0x000000a4)
  4573. *
  4574. *****************************************************************************/
  4575. /* Slice: sp_y_size:*/
  4576. /* Size of self picture Y component ring buffer.*/
  4577. /**/
  4578. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4579. #ifdef MRV_MI_SP_Y_SIZE
  4580. #endif /* MRV_MI_SP_Y_SIZE */
  4581. /*****************************************************************************/
  4582. /**
  4583. * register: mi_sp_y_offs_cnt_shd: Current offset counter of self picture Y
  4584. * component ring buffer (0x000000a8)
  4585. *
  4586. *****************************************************************************/
  4587. /* Slice: sp_y_offs_cnt:*/
  4588. /* Current offset counter of self picture Y component ring buffer for address generation */
  4589. /**/
  4590. /* Note:*/
  4591. /* - Soft reset will reset the contents to reset value.*/
  4592. /**/
  4593. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4594. #ifdef MRV_MI_SP_Y_OFFS_CNT
  4595. #endif /* MRV_MI_SP_Y_OFFS_CNT */
  4596. /*****************************************************************************/
  4597. /**
  4598. * register: mi_sp_cb_base_ad_shd: Base address shadow register for self
  4599. * picture Cb component ring buffer (0x000000b0)
  4600. *
  4601. *****************************************************************************/
  4602. /* Slice: sp_cb_base_ad:*/
  4603. /* Base address of self picture Cb component ring buffer.*/
  4604. /**/
  4605. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4606. #ifdef MRV_MI_SP_CB_BASE_AD
  4607. #endif /* MRV_MI_SP_CB_BASE_AD */
  4608. /*****************************************************************************/
  4609. /**
  4610. * register: mi_sp_cb_size_shd: Size shadow register of self picture Cb
  4611. * component ring buffer (0x000000b4)
  4612. *
  4613. *****************************************************************************/
  4614. /* Slice: sp_cb_size:*/
  4615. /* Size of self picture Cb component ring buffer.*/
  4616. /**/
  4617. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4618. #ifdef MRV_MI_SP_CB_SIZE
  4619. #endif /* MRV_MI_SP_CB_SIZE */
  4620. /*****************************************************************************/
  4621. /**
  4622. * register: mi_sp_cb_offs_cnt_shd: Current offset counter of self picture
  4623. * Cb component ring buffer (0x000000b8)
  4624. *
  4625. *****************************************************************************/
  4626. /* Slice: sp_cb_offs_cnt:*/
  4627. /* Current offset counter of self picture Cb component ring buffer for */
  4628. /* address generation */
  4629. /**/
  4630. /* Note:*/
  4631. /* - Soft reset will reset the contents to reset value.*/
  4632. /**/
  4633. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4634. #ifdef MRV_MI_SP_CB_OFFS_CNT
  4635. #endif /* MRV_MI_SP_CB_OFFS_CNT */
  4636. /*****************************************************************************/
  4637. /**
  4638. * register: mi_sp_cr_base_ad_shd: Base address shadow register for self
  4639. * picture Cr component ring buffer (0x000000bc)
  4640. *
  4641. *****************************************************************************/
  4642. /* Slice: sp_cr_base_ad:*/
  4643. /* Base address of self picture Cr component ring buffer.*/
  4644. /**/
  4645. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4646. #ifdef MRV_MI_SP_CR_BASE_AD
  4647. #endif /* MRV_MI_SP_CR_BASE_AD */
  4648. /*****************************************************************************/
  4649. /**
  4650. * register: mi_sp_cr_size_shd: Size shadow register of self picture Cr
  4651. * component ring buffer (0x000000c0)
  4652. *
  4653. *****************************************************************************/
  4654. /* Slice: sp_cr_size:*/
  4655. /* Size of self picture Cr component ring buffer.*/
  4656. /**/
  4657. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4658. #ifdef MRV_MI_SP_CR_SIZE
  4659. #endif /* MRV_MI_SP_CR_SIZE */
  4660. /*****************************************************************************/
  4661. /**
  4662. * register: mi_sp_cr_offs_cnt_shd: Current offset counter of self picture Cr
  4663. * component ring buffer (0x000000c4)
  4664. *
  4665. *****************************************************************************/
  4666. /* Slice: sp_cr_offs_cnt:*/
  4667. /* Current offset counter of self picture Cr component ring buffer for */
  4668. /* address generation */
  4669. /**/
  4670. /* Note:*/
  4671. /* - Soft reset will reset the contents to reset value.*/
  4672. /**/
  4673. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4674. #ifdef MRV_MI_SP_CR_OFFS_CNT
  4675. #endif /* MRV_MI_SP_CR_OFFS_CNT */
  4676. /*****************************************************************************/
  4677. /**
  4678. * register: mi_dma_y_pic_start_ad: Y component image start address (0x000000c8)
  4679. *
  4680. *****************************************************************************/
  4681. /* Slice: dma_y_pic_start_ad:*/
  4682. /* Image start address of the y component */
  4683. /**/
  4684. /* Note:*/
  4685. /* - Must be multiple of 4 in interleaved mode.*/
  4686. #ifdef MRV_MI_DMA_Y_PIC_START_AD
  4687. #endif /* MRV_MI_DMA_Y_PIC_START_AD */
  4688. /*****************************************************************************/
  4689. /**
  4690. * register: mi_dma_y_pic_width: Y component image width (0x000000cc)
  4691. *
  4692. *****************************************************************************/
  4693. /* Slice: dma_y_pic_width:*/
  4694. /* Image width of the Y component in pixel.*/
  4695. /**/
  4696. /* For YCbCr 4:2:x the image width must be a multiple of 2.*/
  4697. /**/
  4698. /* In planar mode the image width of the Cb and Cr component is assumed */
  4699. /* according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4.*/
  4700. /**/
  4701. /* In semi planar 4:2:x mode the image width of the Cb component (which includes Cr)*/
  4702. /* is assumed the same size.*/
  4703. /**/
  4704. /* In interleave mode no Cb/Cr image width is used.*/
  4705. #ifdef MRV_MI_DMA_Y_PIC_WIDTH
  4706. #endif /* MRV_MI_DMA_Y_PIC_WIDTH */
  4707. /*****************************************************************************/
  4708. /**
  4709. * register: mi_dma_y_llength: Y component original line length (0x000000d0)
  4710. *
  4711. *****************************************************************************/
  4712. /* Slice: dma_y_llength:*/
  4713. /* Line length of the Y component of the original image in memory */
  4714. /**/
  4715. /* For an uncropped image, where lines follow each other without offset */
  4716. /* (no line stride), line length must match image width.*/
  4717. /**/
  4718. /* For Y component the line length in 4:2:x planar mode must be a multiple of 8,*/
  4719. /* for all other component modes a multiple of 4.*/
  4720. /**/
  4721. /* In planar mode the line length of the Cb and Cr component is assumed according */
  4722. /* to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4.*/
  4723. /**/
  4724. /* In semi planar 4:2:x mode the line length of the Cb component (which includes Cr)*/
  4725. /* is assumed the same size.*/
  4726. /**/
  4727. /* In interleave mode no Cb/Cr line length is used.*/
  4728. #ifdef MRV_MI_DMA_Y_LLENGTH
  4729. #endif /* MRV_MI_DMA_Y_LLENGTH */
  4730. /*****************************************************************************/
  4731. /**
  4732. * register: mi_dma_y_pic_size: Y component image size (0x000000d4)
  4733. *
  4734. *****************************************************************************/
  4735. /* Slice: dma_y_pic_size:*/
  4736. /* Image size of the Y component in pixel which has to be the Y line length */
  4737. /* multiplied by the Y image height (dma_y_llength * dma_y_pic_height).*/
  4738. /**/
  4739. /* In planar mode the image size of the Cb and Cr component is assumed according */
  4740. /* to the YCbCr format, i.e. a quarter for 4:2:0, half for 4:2:2 and the same */
  4741. /* for 4:4:4.*/
  4742. /**/
  4743. /* In semi planar mode the image size of the Cb component (which includes Cr)*/
  4744. /* is assumed half for 4:2:0 and the same size for 4:2:2.*/
  4745. /**/
  4746. /* In interleave mode no Cb/Cr image size is used.*/
  4747. #ifdef MRV_MI_DMA_Y_PIC_SIZE
  4748. #endif /* MRV_MI_DMA_Y_PIC_SIZE */
  4749. /*****************************************************************************/
  4750. /**
  4751. * register: mi_dma_cb_pic_start_ad: Cb component image start address (0x000000d8)
  4752. *
  4753. *****************************************************************************/
  4754. /* Slice: dma_cb_pic_start_ad:*/
  4755. /* Image start address of the Cb component */
  4756. /**/
  4757. /* Note:*/
  4758. /* - Must be multiple of 2 in semi-planar mode.*/
  4759. #ifdef MRV_MI_DMA_CB_PIC_START_AD
  4760. #endif /* MRV_MI_DMA_CB_PIC_START_AD */
  4761. /*****************************************************************************/
  4762. /**
  4763. * register: mi_dma_cr_pic_start_ad: Cr component image start address (0x000000e8)
  4764. *
  4765. *****************************************************************************/
  4766. /* Slice: dma_cr_pic_start_ad:*/
  4767. /* Image start address of the Cr component */
  4768. #ifdef MRV_MI_DMA_CR_PIC_START_AD
  4769. #endif /* MRV_MI_DMA_CR_PIC_START_AD */
  4770. /*****************************************************************************/
  4771. /**
  4772. * register: mi_imsc: Interrupt Mask Register (0x000000f8)
  4773. * mi_ris : Raw Interrupt Status Register (0x000000fc)
  4774. * mi_mis : Masked Interrupt Status Register (0x00000100)
  4775. * mi_icr : Interrupt Clear Register (0x00000104)
  4776. * mi_isr : Interrupt Set Register (0x00000108)
  4777. *
  4778. * ('1': interrupt active, '0': interrupt masked)
  4779. *
  4780. *****************************************************************************/
  4781. /* Slice: dma_ready:*/
  4782. /* Mask bit for dma ready interrupt */
  4783. #ifndef MRV_MI_DMA_READY
  4784. #define MRV_MI_DMA_READY_MASK 0
  4785. #endif /* MRV_MI_DMA_READY */
  4786. /* Slice: wrap_sp_cr:*/
  4787. /* Mask bit for self picture Cr address wrap interrupt */
  4788. #ifndef MRV_MI_WRAP_SP_CR
  4789. #define MRV_MI_WRAP_SP_CR_MASK 0
  4790. #endif /* MRV_MI_WRAP_SP_CR */
  4791. /* Slice: wrap_sp_cb:*/
  4792. /* Mask bit for self picture Cb address wrap interrupt */
  4793. #ifndef MRV_MI_WRAP_SP_CB
  4794. #define MRV_MI_WRAP_SP_CB_MASK 0
  4795. #endif /* MRV_MI_WRAP_SP_CB */
  4796. /* Slice: wrap_sp_y:*/
  4797. /* Mask bit for self picture Y address wrap interrupt */
  4798. #ifndef MRV_MI_WRAP_SP_Y
  4799. #define MRV_MI_WRAP_SP_Y_MASK 0
  4800. #endif /* MRV_MI_WRAP_SP_Y */
  4801. /* Slice: wrap_mp_cr:*/
  4802. /* Mask bit for main picture Cr address wrap interrupt */
  4803. #ifndef MRV_MI_WRAP_MP_CR
  4804. #define MRV_MI_WRAP_MP_CR_MASK 0
  4805. #endif /* MRV_MI_WRAP_MP_CR */
  4806. /* Slice: wrap_mp_cb:*/
  4807. /* Mask bit for main picture Cb address wrap interrupt */
  4808. #ifndef MRV_MI_WRAP_MP_CB
  4809. #define MRV_MI_WRAP_MP_CB_MASK 0
  4810. #endif /* MRV_MI_WRAP_MP_CB */
  4811. /* Slice: wrap_mp_y:*/
  4812. /* Mask bit for main picture Y address wrap interrupt */
  4813. #ifndef MRV_MI_WRAP_MP_Y
  4814. #define MRV_MI_WRAP_MP_Y_MASK 0
  4815. #endif /* MRV_MI_WRAP_MP_Y */
  4816. /* Slice: fill_mp_y:*/
  4817. /* Mask bit for fill level interrupt of main picture Y,*/
  4818. /* JPEG or raw data */
  4819. #ifndef MRV_MI_FILL_MP_Y
  4820. #define MRV_MI_FILL_MP_Y_MASK 0
  4821. #endif /* MRV_MI_FILL_MP_Y */
  4822. /* Slice: mblk_line:*/
  4823. /* Mask bit for makroblock line interrupt of main picture */
  4824. /* (16 lines of Y, 8 lines of Cb and 8 lines of Cr are written */
  4825. /* into RAM)*/
  4826. #ifndef MRV_MI_MBLK_LINE
  4827. #define MRV_MI_MBLK_LINE_MASK 0
  4828. #endif /* MRV_MI_MBLK_LINE */
  4829. /* Slice: sp_frame_end:*/
  4830. /* Mask self picture end of frame interrupt */
  4831. #ifndef MRV_MI_SP_FRAME_END
  4832. #define MRV_MI_SP_FRAME_END_MASK 0
  4833. #endif /* MRV_MI_SP_FRAME_END */
  4834. /* Slice: mp_frame_end:*/
  4835. /* Mask main picture end of frame interrupt */
  4836. #ifndef MRV_MI_MP_FRAME_END
  4837. #define MRV_MI_MP_FRAME_END_MASK 0
  4838. #endif /* MRV_MI_MP_FRAME_END */
  4839. /* combination of all interrupt lines */
  4840. #define MRV_MI_ALL_IRQS
  4841. #define MRV_MI_ALL_IRQS_MASK \
  4842. (0 \
  4843. | MRV_MI_DMA_READY_MASK \
  4844. | MRV_MI_AHB_ERROR_MASK \
  4845. | MRV_MI_WRAP_SP_CR_MASK \
  4846. | MRV_MI_WRAP_SP_CB_MASK \
  4847. | MRV_MI_WRAP_SP_Y_MASK \
  4848. | MRV_MI_WRAP_MP_CR_MASK \
  4849. | MRV_MI_WRAP_MP_CB_MASK \
  4850. | MRV_MI_WRAP_MP_Y_MASK \
  4851. | MRV_MI_FILL_MP_Y_MASK \
  4852. | MRV_MI_MBLK_LINE_MASK \
  4853. | MRV_MI_SP_FRAME_END_MASK \
  4854. | MRV_MI_DMA_FRAME_END_MASK \
  4855. | MRV_MI_MP_FRAME_END_MASK \
  4856. )
  4857. #define MRV_MI_ALL_IRQS_SHIFT 0U
  4858. /*****************************************************************************/
  4859. /**
  4860. * register: mi_status : MI Status Register (0x0000010c)
  4861. * mi_status_clr: MI Status Clear Register (0x00000110)
  4862. *
  4863. *****************************************************************************/
  4864. /* Slice: sp_cr_fifo_full:*/
  4865. /* FIFO full flag of Cr FIFO in self path asserted since last clear */
  4866. #ifndef MRV_MI_SP_CR_FIFO_FULL
  4867. #define MRV_MI_SP_CR_FIFO_FULL_MASK 0U
  4868. #endif /* MRV_MI_SP_CR_FIFO_FULL */
  4869. /* Slice: sp_cb_fifo_full:*/
  4870. /* FIFO full flag of Cb FIFO in self path asserted since last clear */
  4871. #ifndef MRV_MI_SP_CB_FIFO_FULL
  4872. #define MRV_MI_SP_CB_FIFO_FULL_MASK 0U
  4873. #endif /* MRV_MI_SP_CB_FIFO_FULL */
  4874. /* Slice: sp_y_fifo_full:*/
  4875. /* FIFO full flag of Y FIFO in self path asserted since last clear */
  4876. #ifndef MRV_MI_SP_Y_FIFO_FULL
  4877. #define MRV_MI_SP_Y_FIFO_FULL_MASK 0U
  4878. #endif /* MRV_MI_SP_Y_FIFO_FULL */
  4879. /* Slice: mp_cr_fifo_full:*/
  4880. /* FIFO full flag of Cr FIFO in main path asserted since last clear */
  4881. #ifndef MRV_MI_MP_CR_FIFO_FULL
  4882. #define MRV_MI_MP_CR_FIFO_FULL_MASK 0U
  4883. #endif /* MRV_MI_MP_CR_FIFO_FULL */
  4884. /* Slice: mp_cb_fifo_full:*/
  4885. /* FIFO full flag of Cb FIFO in main path asserted since last clear */
  4886. #ifndef MRV_MI_MP_CB_FIFO_FULL
  4887. #define MRV_MI_MP_CB_FIFO_FULL_MASK 0U
  4888. #endif /* MRV_MI_MP_CB_FIFO_FULL */
  4889. /* Slice: mp_y_fifo_full:*/
  4890. /* FIFO full flag of Y FIFO in main path asserted since last clear */
  4891. #ifndef MRV_MI_MP_Y_FIFO_FULL
  4892. #define MRV_MI_MP_Y_FIFO_FULL_MASK 0U
  4893. #endif /* MRV_MI_MP_Y_FIFO_FULL */
  4894. /* combination of all MI status lines */
  4895. #define MRV_MI_ALL_STAT
  4896. #define MRV_MI_ALL_STAT_MASK \
  4897. (0 \
  4898. | MRV_MI_SP_CR_FIFO_FULL_MASK \
  4899. | MRV_MI_SP_CB_FIFO_FULL_MASK \
  4900. | MRV_MI_SP_Y_FIFO_FULL_MASK \
  4901. | MRV_MI_MP_CR_FIFO_FULL_MASK \
  4902. | MRV_MI_MP_CB_FIFO_FULL_MASK \
  4903. | MRV_MI_MP_Y_FIFO_FULL_MASK \
  4904. )
  4905. #define MRV_MI_ALL_STAT_SHIFT 0U
  4906. /*****************************************************************************/
  4907. /**
  4908. * register: mi_sp_y_pic_width: Y component image width (0x00000114)
  4909. *
  4910. *****************************************************************************/
  4911. /* Slice: sp_y_pic_width:*/
  4912. /* Image width of the self picture Y component or RGB picture in pixel.*/
  4913. /**/
  4914. /* For YCbCr 4:2:x and RGB 565 the image width must be a multiple of 2.*/
  4915. /* If no line stride is used but flipping required, the image width must be */
  4916. /* a multiple of 8 for 4:2:x planar or 4 for 4:4:4 planar/4:2:x semi planar.*/
  4917. /**/
  4918. /* There are no restrictions for RGB 888/666.*/
  4919. /**/
  4920. /* In planar mode the image width of the Cb and Cr component is assumed according */
  4921. /* to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4.*/
  4922. /**/
  4923. /* In semi planar 4:2:x mode the image width of the Cb component (which includes Cr)*/
  4924. /* is assumed the same size.*/
  4925. /**/
  4926. /* In interleave mode no Cb/Cr image width is used.*/
  4927. /* Note:*/
  4928. /* - Image width always refers to the picture width of the output image. This is */
  4929. /* particularly important when rotating.*/
  4930. /**/
  4931. /* Note:*/
  4932. /* - Programmed value becomes effective immediately. So write to the register */
  4933. /* only if no picture data is sent to the self path.*/
  4934. #ifdef MRV_MI_SP_Y_PIC_WIDTH
  4935. #endif /* MRV_MI_SP_Y_PIC_WIDTH */
  4936. /*****************************************************************************/
  4937. /**
  4938. * register: mi_sp_y_pic_height: Y component image height (0x00000118)
  4939. *
  4940. *****************************************************************************/
  4941. /* Slice: sp_y_pic_height:*/
  4942. /* Image height of the y component or RGB picture in pixel.*/
  4943. /**/
  4944. /* In planar and semi planar mode the image width of the cb and cr component */
  4945. /* is assumed according to the YCbCr format, i.e. half for 4:2:0 and the same */
  4946. /* for 4:2:2 and 4:4:4.*/
  4947. /**/
  4948. /* Note:*/
  4949. /* - Image height always refers to the picture height of the output image.*/
  4950. /* This is particularly important when rotating.*/
  4951. /**/
  4952. /* Note:*/
  4953. /* - Programmed value becomes effective immediately. So write to the register */
  4954. /* only if no picture data is sent to the self path.*/
  4955. #ifdef MRV_MI_SP_Y_PIC_HEIGHT
  4956. #endif /* MRV_MI_SP_Y_PIC_HEIGHT */
  4957. /*****************************************************************************/
  4958. /**
  4959. * register: mi_sp_y_pic_size: Y component image size (0x0000011c)
  4960. *
  4961. *****************************************************************************/
  4962. /* Slice: sp_y_pic_size:*/
  4963. /* Image size of the Y component or RGB picture in pixel which has to be the */
  4964. /* Y line length multiplied by the Y image height (sp_y_llength * sp_y_pic_height).*/
  4965. /**/
  4966. /* In planar mode the image size of the Cb and Cr component is assumed according */
  4967. /* to the YCbCr format, i.e. a quarter for 4:2:0, half for 4:2:2 and the same for */
  4968. /* 4:4:4.*/
  4969. /**/
  4970. /* In semi planar mode the image size of the Cb and Cr component is assumed half */
  4971. /* for 4:2:0 and the same size for 4:2:2.*/
  4972. /**/
  4973. /* Note:*/
  4974. /* - Programmed value becomes effective immediately. So write to the register only */
  4975. /* if no picture data is sent to the self path.*/
  4976. #ifdef MRV_MI_SP_Y_PIC_SIZE
  4977. #endif /* MRV_MI_SP_Y_PIC_SIZE */
  4978. /*****************************************************************************/
  4979. /**
  4980. * register: mi_dma_ctrl: DMA control register (0x00000120)
  4981. *
  4982. *****************************************************************************/
  4983. /* Slice: dma_rgb_format:*/
  4984. /* Selects RGB Bayer data of read DMA picture */
  4985. /**/
  4986. /* 00: no DMA RGB Bayer data */
  4987. /* 01: 8 bit RGB Bayer data */
  4988. /* 10: 16 bit RGB Bayer data (12 bit used)*/
  4989. /**/
  4990. /* bytes are organized MSB first and 4 lower bits of LSB remain unused:*/
  4991. /* byte_even -> bayer[11:4], byte_odd[7:4] -> bayer[3:0]*/
  4992. /**/
  4993. /* 11: reserved.*/
  4994. #ifdef MRV_MI_DMA_RGB_FORMAT
  4995. #define MRV_MI_DMA_RGB_FORMAT_NO_DATA 0
  4996. #define MRV_MI_DMA_RGB_FORMAT_8BIT_BAYER 1
  4997. #define MRV_MI_DMA_RGB_FORMAT_16BIT_BAYER 2
  4998. #endif /* MRV_MI_DMA_RGB_FORMAT */
  4999. /* Slice: dma_frame_end_disable:*/
  5000. /* Suppresses v_end so that no frame end can be detected by following */
  5001. /* instances. Note: The dma_ready interrupt is raised as usual, but the */
  5002. /* dma_frame_end interrupt will not be generated until v_end has been */
  5003. /* enabled again.*/
  5004. #ifdef MRV_MI_DMA_FRAME_END_DISABLE
  5005. #endif /* MRV_MI_DMA_FRAME_END_DISABLE */
  5006. /* Slice: dma_continuous_en:*/
  5007. /* Enables continuous mode. If set the same frame is read back over and */
  5008. /* over. A start pulse on dma_start is needed only for the first time.*/
  5009. /* To stop continuous mode reset this bit (takes effect after the next */
  5010. /* frame end) or execute a soft reset. This bit is intended to be used */
  5011. /* in conjunction with the Superimpose feature.*/
  5012. #ifdef MRV_MI_DMA_CONTINUOUS_EN
  5013. #endif /* MRV_MI_DMA_CONTINUOUS_EN */
  5014. /* Slice: dma_byte_swap:*/
  5015. /* Enables change of DMA byte order of the 32 bit input word at read port */
  5016. /* 1: byte order is mirrored but the bit order within one byte doesn’t change */
  5017. /* 0: no byte mirroring */
  5018. #ifdef MRV_MI_DMA_BYTE_SWAP
  5019. #endif /* MRV_MI_DMA_BYTE_SWAP */
  5020. /* Slice: dma_inout_format:*/
  5021. /* Selects input/output format of DMA picture.*/
  5022. /* 11: YCbCr 4:4:4 */
  5023. /* 10: YCbCr 4:2:2 */
  5024. /* 01: YCbCr 4:2:0 */
  5025. /* 00: YCbCr 4:0:0 */
  5026. #ifdef MRV_MI_DMA_INOUT_FORMAT
  5027. #define MRV_MI_DMA_INOUT_FORMAT_YUV444 3 /* 11: YCbCr 4:4:4 */
  5028. #define MRV_MI_DMA_INOUT_FORMAT_YUV422 2 /* 10: YCbCr 4:2:2 */
  5029. #define MRV_MI_DMA_INOUT_FORMAT_YUV420 1 /* 01: YCbCr 4:2:0 */
  5030. #define MRV_MI_DMA_INOUT_FORMAT_YUV400 0 /* 00: YCbCr 4:0:0 */
  5031. #endif /* MRV_MI_DMA_INOUT_FORMAT */
  5032. /* Slice: dma_read_format:*/
  5033. /* Defines how YCbCr picture data is read from memory.*/
  5034. /* 00: planar */
  5035. /* 01: semi planar, for YCbCr 4:2:x */
  5036. /* 10: interleaved (combined), for YCbCr 4:2:2 and RGB only */
  5037. /* 11: reserved */
  5038. #ifdef MRV_MI_DMA_READ_FORMAT
  5039. #define MRV_MI_DMA_READ_FORMAT_PLANAR 0 /* 00: planar */
  5040. #define MRV_MI_DMA_READ_FORMAT_SEMIPLANAR 1 /* 01: semi planar, for YCbCr 4:2:x */
  5041. #define MRV_MI_DMA_READ_FORMAT_INTERLEAVED 2 /* 10: interleaved (combined), for YCbCr 4:2:2 only */
  5042. #endif /* MRV_MI_DMA_READ_FORMAT */
  5043. /* Slice: dma_burst_len_chrom:*/
  5044. /* Burst length for Cb or Cr data affecting DMA read port.*/
  5045. /* 00: 4-beat bursts */
  5046. /* 01: 8-beat bursts */
  5047. /* 10: 16-beat bursts */
  5048. /* 11: reserved */
  5049. /* Ignored if 8- or 16-beat bursts are not supported.*/
  5050. #ifdef MRV_MI_DMA_BURST_LEN_CHROM
  5051. #define MRV_MI_DMA_BURST_LEN_CHROM_4 0 /* 0: 4-beat bursts */
  5052. #define MRV_MI_DMA_BURST_LEN_CHROM_8 1 /* 1: 8-beat bursts */
  5053. #define MRV_MI_DMA_BURST_LEN_CHROM_16 2 /* 2: 16-beat bursts */
  5054. #endif /* MRV_MI_DMA_BURST_LEN_CHROM */
  5055. /* Slice: dma_burst_len_lum:*/
  5056. /* Burst length for Y data affecting DMA read port.*/
  5057. /* 00: 4-beat bursts */
  5058. /* 01: 8-beat bursts */
  5059. /* 10: 16-beat bursts */
  5060. /* 11: reserved */
  5061. /* Ignored if 8- or 16-beat bursts are not supported.*/
  5062. #ifdef MRV_MI_DMA_BURST_LEN_LUM
  5063. #define MRV_MI_DMA_BURST_LEN_LUM_4 0 /* 0: 4-beat bursts */
  5064. #define MRV_MI_DMA_BURST_LEN_LUM_8 1 /* 1: 8-beat bursts */
  5065. #define MRV_MI_DMA_BURST_LEN_LUM_16 2 /* 2: 16-beat bursts */
  5066. #endif /* MRV_MI_DMA_BURST_LEN_LUM */
  5067. /*****************************************************************************/
  5068. /**
  5069. * register: mi_dma_start: DMA start register (0x00000124)
  5070. *
  5071. *****************************************************************************/
  5072. /* Slice: dma_start:*/
  5073. /* Enables DMA access. Additionally main or self path has to be enabled separately.*/
  5074. #ifdef MRV_MI_DMA_START
  5075. #endif /* MRV_MI_DMA_START */
  5076. /*****************************************************************************/
  5077. /**
  5078. * register: mi_dma_status: DMA status register (0x00000128)
  5079. *
  5080. *****************************************************************************/
  5081. /* Slice: dma_active:*/
  5082. /* If set DMA access is active.*/
  5083. #ifdef MRV_MI_DMA_ACTIVE
  5084. #endif /* MRV_MI_DMA_ACTIVE */
  5085. /*****************************************************************************/
  5086. /**
  5087. * register: mi_pixel_cnt: Counter value for defect pixel list (0x0000012c)
  5088. *
  5089. *****************************************************************************/
  5090. /* Slice: pix_cnt:*/
  5091. /* Counter value specifies the number of pixels of the defect pixel list */
  5092. /* generated by DPCC of the last transmitted frame. Updated at frame end.*/
  5093. /**/
  5094. /* A soft reset will set the counter to zero.*/
  5095. #ifdef MRV_MI_PIX_CNT
  5096. #endif /* MRV_MI_PIX_CNT */
  5097. #ifdef ISP_MI_HANDSHAKE_NANO
  5098. /* Nano handshake */
  5099. /*****************************************************************************/
  5100. /**
  5101. * register: isp_handshake_ctrl_0: Nano handshake functions (0x0000014C)
  5102. *
  5103. *****************************************************************************/
  5104. /*! Slice: mp_handshake_en: */
  5105. /*! Enable mp handshake function for MI MP */
  5106. #ifdef MRV_MI_MP_HANDSHK_EN
  5107. #define MRV_MI_MP_HANDSHK_EN_DISABLE 0 /* HANDSHAKE disable */
  5108. #define MRV_MI_MP_HANDSHK_EN_ENABLE 1 /* HANDSHAKE enable, active high */
  5109. #endif
  5110. /*! Slice: mp_handshk_storage_format */
  5111. /*! Define how YCbCr picture data is stored in memory */
  5112. /*! 00: Planar */
  5113. /*! 01: Semi planar, for YCbCr4:2:x */
  5114. /*! 10: Interleaved(combiled), for YCbCr 4:2:2 only or RAW format.*/
  5115. /*! 11: not support */
  5116. #ifdef MRV_MI_MP_HANDSHK_STORAGE_FORMAT
  5117. #define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_PLANAR 0 /* 00: Planar */
  5118. #define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_SEMIPLANAR 1 /* 01: Semi-Planar */
  5119. #define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_INTERLEAVED 2 /* 10: Interleaved */
  5120. #endif
  5121. /*! Slice: mp_handshk_data_format */
  5122. /*! Defines the video format */
  5123. /*! 00: RAW format */
  5124. /*! 01: reserved */
  5125. /*! 10: YUV 422 */
  5126. /*! 11: YUV 420 */
  5127. #ifdef MRV_MI_MP_HANDSHK_DATA_FORMAT
  5128. #define MRV_MI_MP_HANDSHK_DATA_FORMAT_RAW 0 /* 00: raw format */
  5129. #define MRV_MI_MP_HANDSHK_DATA_FORMAT_YUV422 2 /* 10: YUV422 */
  5130. #define MRV_MI_MP_HANDSHK_DATA_FORMAT_YUV420 3 /* 11: YUV420 */
  5131. #endif
  5132. /*! Slice: mp_handshk_slice_size */
  5133. /*! Defines the slice size to generate handshake signals, minus 1 is used */
  5134. #ifdef MRV_MI_MP_HANDSHK_SLICE_SIZE
  5135. #endif
  5136. /*! Slice: mp_handshk_slice_buf_size */
  5137. /*! Defines the circular buffer size in number of defined slices per buffer, minus 1 is used */
  5138. #ifdef MRV_MI_MP_HANDSHK_SLICE_BUF_SIZE
  5139. #endif
  5140. /*! Slice: mp_handshk_ack_count */
  5141. /*! Defines the acknowledage is not received in the defined cycles, it will generate handshake interrupt.*/
  5142. #ifdef MRV_MI_MP_HANDSHK_ACK_COUNT
  5143. #endif
  5144. #endif
  5145. #ifdef ISP_MI_ALIGN_NANO
  5146. /* MI output Alignment */
  5147. /*****************************************************************************/
  5148. /**
  5149. * register: mi_output_alignment: Nano MI output alignment (0x0000015C)
  5150. *
  5151. *****************************************************************************/
  5152. /* Slice: mp_lsb_alignment:*/
  5153. /*! msb/lsb align for raw 10 and raw 12 formats control */
  5154. /*! 0: MSB aligned for RAW10 and RAW12 formats */
  5155. /*! 1: LSB aligned for RAW10 and RAW12 formats */
  5156. #ifdef MRV_MI_LSB_ALIGNMENT
  5157. #define MRV_MI_LSB_ALIGNMENT_MSB 0 /* MSB aligned for raw 10 and raw 12 formats */
  5158. #define MRV_MI_LSB_ALIGNMENT_LSB 1 /* LSB aligned for raw 10 and raw 12 formats */
  5159. #endif
  5160. #endif
  5161. #ifdef ISP_MI_BYTESWAP
  5162. /*! Slice mp_byte_swap:*/
  5163. /*! swap bytes for ISP Nano */
  5164. /*! bit 0 to swap bytes */
  5165. /*! bit 1 to swap words */
  5166. /*! bit 2 to swap dwords */
  5167. /*! 3'b001: ABCDEFGH => BADCFEHG */
  5168. /*! 3'b000: ABCDEFGH => ABCDEFGH */
  5169. /*! 3'b010: ABCDEFGH => CDABGHEF */
  5170. /*! 3'b011: ABCDEFGH => DCBAHGFE */
  5171. /*! 3'b100: ABCDEFGH => EFGHABCD */
  5172. /*! 3'b101: ABCDEFGH => FEHGBADC */
  5173. /*! 3'b110: ABCDEFGH => GHEFCDAB */
  5174. /*! 3'b111: ABCDEFGH => HGFEDCBA */
  5175. #ifdef MRV_MI_MP_BYTE_SWAP
  5176. #define MRV_MI_MP_BYTE_SWAP_NORMAL 0x0 /* normal mode */
  5177. #define MRV_MI_MP_BYTE_SWAP_BYTE 0x1 /* bit 0 to swap bytes */
  5178. #define MRV_MI_MP_BYTE_SWAP_WORD 0x2 /* bit 1 to swap words */
  5179. #define MRV_MI_MP_BYTE_SWAP_DWORD 0x4 /* bit 2 to swap dwords */
  5180. #endif
  5181. #endif
  5182. #ifdef ISP_MI_FIFO_DEPTH_NANO
  5183. /*****************************************************************************/
  5184. /**
  5185. * register: mi_mp_output_fifo_size: Nano MI fifo control (0x00000160)
  5186. *
  5187. *****************************************************************************/
  5188. /*! Slice output_fifo_depth:*/
  5189. /*! Select output FIFO depth setting */
  5190. /*! 00: FULL(2KBytes)*/
  5191. /*! 01: HALF(1KBytes)*/
  5192. /*! 10: 1/4(512Bytes)*/
  5193. /*! 11: 1/8(256Bytes)*/
  5194. #ifdef MRV_MI_OUTOUT_FIFO_DEPTH
  5195. #define MRV_MI_OUTOUT_FIFO_DEPTH_FULL 0 /* FULL(2KBytes) */
  5196. #define MRV_MI_OUTOUT_FIFO_DEPTH_HALF 1 /* HALF(1KBytes) */
  5197. #define MRV_MI_OUTOUT_FIFO_DEPTH_1_4 2 /* 1/4(512Bytes) */
  5198. #define MRV_MI_OUTOUT_FIFO_DEPTH_1_8 3 /* 1/8(256Bytes) */
  5199. #endif
  5200. #endif
  5201. /*****************************************************************************/
  5202. /* JPEG Encoder Registers */
  5203. /*****************************************************************************/
  5204. /*****************************************************************************/
  5205. /**
  5206. * register: jpe_gen_header: command to start stream header generation (0x0000)
  5207. *
  5208. *****************************************************************************/
  5209. /* Slice: gen_header:*/
  5210. /* "1" = Start command to generate stream header */
  5211. /* auto reset to zero after one clock cycle */
  5212. #ifdef MRV_JPE_GEN_HEADER
  5213. #endif /* MRV_JPE_GEN_HEADER */
  5214. /*****************************************************************************/
  5215. /**
  5216. * register: jpe_encode: Start command to start JFIF stream encoding (0x0004)
  5217. *
  5218. *****************************************************************************/
  5219. /* Slice: encode:*/
  5220. /* "1" = Start command to start JFIF stream encoding;*/
  5221. /* auto reset to zero after one clock cycle.*/
  5222. /* This bit is write-only: reading result is always zero!*/
  5223. #ifdef MRV_JPE_ENCODE
  5224. #endif /* MRV_JPE_ENCODE */
  5225. /*****************************************************************************/
  5226. /**
  5227. * register: jpe_init: Automatic configuration update (INIT) (0x0008)
  5228. *
  5229. *****************************************************************************/
  5230. /* Slice: JP_INIT:*/
  5231. /* "1" = Immediate start of JPEG encoder.*/
  5232. /**/
  5233. /* This bit has to be set after "Encode" to start the JPEG encoder. The "Encode"*/
  5234. /* command becomes active either with JP_INIT or with the input signal "CFG_UPD".*/
  5235. /* auto reset to zero after one clock cycle !!!*/
  5236. #ifdef MRV_JPE_JP_INIT
  5237. #endif /* MRV_JPE_JP_INIT */
  5238. /*****************************************************************************/
  5239. /**
  5240. * register: jpe_y_scale_en: Y value scaling control register (0x0000000c)
  5241. *
  5242. *****************************************************************************/
  5243. /* Slice: y_scale_en:*/
  5244. /* Y scale flag */
  5245. /* 1: scaling Y input from [16..235] to [0..255]*/
  5246. /* 0: no Y input scaling */
  5247. #ifdef MRV_JPE_Y_SCALE_EN
  5248. #endif /* MRV_JPE_Y_SCALE_EN */
  5249. /*****************************************************************************/
  5250. /**
  5251. * register: jpe_cbcr_scale_en: Cb/Cr value scaling control register (0x00000010)
  5252. *
  5253. *****************************************************************************/
  5254. /* Slice: cbcr_scale_en:*/
  5255. /* Cb/Cr scale flag */
  5256. /* 1: scaling Cb/Cr input from [16..240] to [0..255]*/
  5257. /* 0: no Cb/Cr input scaling */
  5258. #ifdef MRV_JPE_CBCR_SCALE_EN
  5259. #endif /* MRV_JPE_CBCR_SCALE_EN */
  5260. /*****************************************************************************/
  5261. /**
  5262. * register: jpe_table_flush: header generation debug register (0x00000014)
  5263. *
  5264. *****************************************************************************/
  5265. /* Slice: table_flush:*/
  5266. /* header generation debug control flag */
  5267. /* (controls transmission of last header bytes if the 64 bit output buffer */
  5268. /* is not completely filled)*/
  5269. /* 1: immediately transmit last header bytes */
  5270. /* 0: wait for encoded image data to fill output buffer */
  5271. #ifdef MRV_JPE_TABLE_FLUSH
  5272. #endif /* MRV_JPE_TABLE_FLUSH */
  5273. /*****************************************************************************/
  5274. /**
  5275. * register: jpe_enc_hsize: JPEG codec horizontal image size for encoding
  5276. * (0x00000018)
  5277. *
  5278. *****************************************************************************/
  5279. /* Slice: enc_hsize:*/
  5280. /* JPEG codec horizontal image size for R2B and SGEN blocks */
  5281. #ifdef MRV_JPE_ENC_HSIZE
  5282. #endif /* MRV_JPE_ENC_HSIZE */
  5283. /*****************************************************************************/
  5284. /**
  5285. * register: jpe_enc_vsize: JPEG codec vertical image size for encoding
  5286. * (0x0000001c)
  5287. *
  5288. *****************************************************************************/
  5289. /* Slice: enc_vsize:*/
  5290. /* JPEG codec vertical image size for R2B and SGEN blocks */
  5291. #ifdef MRV_JPE_ENC_VSIZE
  5292. #endif /* MRV_JPE_ENC_VSIZE */
  5293. /*****************************************************************************/
  5294. /**
  5295. * register: jpe_pic_format: JPEG picture encoding format (0x00000020)
  5296. *
  5297. *****************************************************************************/
  5298. /* Slice: enc_pic_format:*/
  5299. /* "0:0:1" = 4:2:2 format */
  5300. /* "1:x:x" = 4:0:0 format */
  5301. #ifdef MRV_JPE_ENC_PIC_FORMAT
  5302. #define MRV_JPE_ENC_PIC_FORMAT_422 1 /* "0:0:1" = 4:2:2 format */
  5303. #define MRV_JPE_ENC_PIC_FORMAT_400 4 /* "1:x:x" = 4:0:0 format */
  5304. #endif /* MRV_JPE_ENC_PIC_FORMAT */
  5305. /*****************************************************************************/
  5306. /**
  5307. * register: jpe_restart_interval: restart marker insertion register (0x0024)
  5308. *
  5309. *****************************************************************************/
  5310. /* Slice: restart_interval:*/
  5311. /* No of MCU in reset interval via host */
  5312. #ifdef MRV_JPE_RESTART_INTERVAL
  5313. #endif /* MRV_JPE_RESTART_INTERVAL */
  5314. /*****************************************************************************/
  5315. /**
  5316. * register: jpe_tq_y_select: Q- table selector 0, quant. table for Y
  5317. * component (0x00000028)
  5318. *
  5319. *****************************************************************************/
  5320. /* Slice: tq0_select:*/
  5321. /* "00" = qtable 0 */
  5322. /* "01" = qtable 1 */
  5323. /* "10" = qtable 2 */
  5324. /* "11" = qtable 3 */
  5325. #ifdef MRV_JPE_TQ0_SELECT
  5326. #endif /* MRV_JPE_TQ0_SELECT */
  5327. /*****************************************************************************/
  5328. /**
  5329. * register: jpe_tq_u_select: Q- table selector 1, quant. table for U
  5330. * component (0x0000002c)
  5331. *
  5332. *****************************************************************************/
  5333. /* Slice: tq1_select:*/
  5334. /* "00" = qtable 0 */
  5335. /* "01" = qtable 1 */
  5336. /* "10" = qtable 2 */
  5337. /* "11" = qtable 3 */
  5338. #ifdef MRV_JPE_TQ1_SELECT
  5339. #endif /* MRV_JPE_TQ1_SELECT */
  5340. /*****************************************************************************/
  5341. /**
  5342. * register: jpe_tq_v_select: Q- table selector 2, quant. table for V
  5343. * component (0x00000030)
  5344. *
  5345. *****************************************************************************/
  5346. /* Slice: tq2_select:*/
  5347. /* "00" = qtable 0 */
  5348. /* "01" = qtable 1 */
  5349. /* "10" = qtable 2 */
  5350. /* "11" = qtable 3 */
  5351. #ifdef MRV_JPE_TQ2_SELECT
  5352. #endif /* MRV_JPE_TQ2_SELECT */
  5353. #define MRV_JPE_TQ_SELECT_TAB3 3 /* "11": qtable 3 */
  5354. #define MRV_JPE_TQ_SELECT_TAB2 2 /* "10": qtable 2 */
  5355. #define MRV_JPE_TQ_SELECT_TAB1 1 /* "01": qtable 1 */
  5356. #define MRV_JPE_TQ_SELECT_TAB0 0 /* "00": qtable 0 */
  5357. /*****************************************************************************/
  5358. /**
  5359. * register: jpe_dc_table_select: Huffman table selector for DC values
  5360. * (0x00000034)
  5361. *
  5362. *****************************************************************************/
  5363. /* Slice: dc_table_select_v:*/
  5364. /* "0" = dc table 0; color component 2 (V)*/
  5365. /* "1" = dc table 1; color component 2 (V)*/
  5366. #ifdef MRV_JPE_DC_TABLE_SELECT_V
  5367. #endif /* MRV_JPE_DC_TABLE_SELECT_V */
  5368. /* Slice: dc_table_select_u:*/
  5369. /* "0" = dc table 0; color component 1 (U)*/
  5370. /* "1" = dc table 1; color component 1 (U)*/
  5371. #ifdef MRV_JPE_DC_TABLE_SELECT_U
  5372. #endif /* MRV_JPE_DC_TABLE_SELECT_U */
  5373. /* Slice: dc_table_select_y:*/
  5374. /* "0" = dc table 0; color component 0 (Y)*/
  5375. /* "1" = dc table 1; color component 0 (Y)*/
  5376. #ifdef MRV_JPE_DC_TABLE_SELECT_Y
  5377. #endif /* MRV_JPE_DC_TABLE_SELECT_Y */
  5378. /*****************************************************************************/
  5379. /**
  5380. * register: jpe_ac_table_select: Huffman table selector for AC values
  5381. * (0x00000038)
  5382. *
  5383. *****************************************************************************/
  5384. /* Slice: ac_table_select_v:*/
  5385. /* "0" = ac table 0; component 2 (V)*/
  5386. /* "1" = ac table 1; component 2 (V)*/
  5387. #ifdef MRV_JPE_AC_TABLE_SELECT_V
  5388. #endif /* MRV_JPE_AC_TABLE_SELECT_V */
  5389. /* Slice: ac_table_select_u:*/
  5390. /* "0" = ac table 0; component 1 (U)*/
  5391. /* "1" = ac table 1; component 1 (U)*/
  5392. #ifdef MRV_JPE_AC_TABLE_SELECT_U
  5393. #endif /* MRV_JPE_AC_TABLE_SELECT_U */
  5394. /* Slice: ac_table_select_y:*/
  5395. /* "0" = ac table 0; component 0 (Y)*/
  5396. /* "1" = ac table 1; component 0 (Y)*/
  5397. #ifdef MRV_JPE_AC_TABLE_SELECT_Y
  5398. #endif /* MRV_JPE_AC_TABLE_SELECT_Y */
  5399. /*****************************************************************************/
  5400. /**
  5401. * register: jpe_table_data: table programming register (0x0000003c)
  5402. *
  5403. *****************************************************************************/
  5404. /* Slice: table_wdata_h:*/
  5405. /* Table data MSB */
  5406. #ifdef MRV_JPE_TABLE_WDATA_H
  5407. #endif /* MRV_JPE_TABLE_WDATA_H */
  5408. /* Slice: table_wdata_l:*/
  5409. /* Table data LSB */
  5410. #ifdef MRV_JPE_TABLE_WDATA_L
  5411. #endif /* MRV_JPE_TABLE_WDATA_L */
  5412. /*****************************************************************************/
  5413. /**
  5414. * register: jpe_table_id: table programming select register (0x00000040)
  5415. *
  5416. *****************************************************************************/
  5417. /* Slice: table_id:*/
  5418. /* select table */
  5419. /* "0000" : Q-table 0 */
  5420. /* "0001" : Q-table 1 */
  5421. /* "0010" : Q-table 2 */
  5422. /* "0011" : Q-table 3 */
  5423. /* "0100" : VLC DC-table 0 */
  5424. /* "0101" : VLC AC-table 0 */
  5425. /* "0110" : VLC DC-table 1 */
  5426. /* "0111" : VLC AC-table 1 */
  5427. /* "1xxx" : reserved for debug */
  5428. #ifdef MRV_JPE_TABLE_ID
  5429. #define MRV_JPE_TABLE_ID_QUANT0 0 /* "0000" : Q-table 0 */
  5430. #define MRV_JPE_TABLE_ID_QUANT1 1 /* "0001" : Q-table 1 */
  5431. #define MRV_JPE_TABLE_ID_QUANT2 2 /* "0010" : Q-table 2 */
  5432. #define MRV_JPE_TABLE_ID_QUANT3 3 /* "0011" : Q-table 3 */
  5433. #define MRV_JPE_TABLE_ID_VLC_DC0 4 /* "0100" : VLC DC-table 0 */
  5434. #define MRV_JPE_TABLE_ID_VLC_AC0 5 /* "0101" : VLC AC-table 0 */
  5435. #define MRV_JPE_TABLE_ID_VLC_DC1 6 /* "0110" : VLC DC-table 1 */
  5436. #define MRV_JPE_TABLE_ID_VLC_AC1 7 /* "0111" : VLC AC-table 1 */
  5437. #endif /* MRV_JPE_TABLE_ID */
  5438. /*****************************************************************************/
  5439. /**
  5440. * register: jpe_tac0_len: Huffman AC table 0 length (0x0044)
  5441. *
  5442. *****************************************************************************/
  5443. /* Slice: tac0_len:*/
  5444. /* Huffman table length for ac0 table */
  5445. #ifdef MRV_JPE_TAC0_LEN
  5446. #endif /* MRV_JPE_TAC0_LEN */
  5447. /*****************************************************************************/
  5448. /**
  5449. * register: jpe_tdc0_len: Huffman DC table 0 length (0x00000048)
  5450. *
  5451. *****************************************************************************/
  5452. /* Slice: tdc0_len:*/
  5453. /* Huffman table length for dc0 table */
  5454. #ifdef MRV_JPE_TDC0_LEN
  5455. #endif /* MRV_JPE_TDC0_LEN */
  5456. /*****************************************************************************/
  5457. /**
  5458. * register: jpe_tac1_len: Huffman AC table 1 length (0x0000004c)
  5459. *
  5460. *****************************************************************************/
  5461. /* Slice: tac1_len:*/
  5462. /* Huffman table length for ac1 table */
  5463. #ifdef MRV_JPE_TAC1_LEN
  5464. #endif /* MRV_JPE_TAC1_LEN */
  5465. /*****************************************************************************/
  5466. /**
  5467. * register: jpe_tdc1_len: Huffman DC table 1 length (0x00000050)
  5468. *
  5469. *****************************************************************************/
  5470. /* Slice: tdc1_len:*/
  5471. /* Huffman table length for dc1 table */
  5472. #ifdef MRV_JPE_TDC1_LEN
  5473. #endif /* MRV_JPE_TDC1_LEN */
  5474. /*****************************************************************************/
  5475. /**
  5476. * register: jpe_encoder_busy: encoder status flag (0x00000058)
  5477. *
  5478. *****************************************************************************/
  5479. /* Slice: codec_busy:*/
  5480. /* Bit 0 = "1" : JPEG codec in process */
  5481. #ifdef MRV_JPE_CODEC_BUSY
  5482. #endif /* MRV_JPE_CODEC_BUSY */
  5483. /*****************************************************************************/
  5484. /**
  5485. * register: jpe_header_mode: header mode definition (0x0000005c)
  5486. *
  5487. *****************************************************************************/
  5488. /* Slice: header_mode:*/
  5489. /* "00" = no header */
  5490. /* "01" = reserved */
  5491. /* "10" = JFIF 1.02 header */
  5492. /* "11" = reserved */
  5493. #ifdef MRV_JPE_HEADER_MODE
  5494. #define MRV_JPE_HEADER_MODE_NONE 0 /* "00" = no APPn header */
  5495. #define MRV_JPE_HEADER_MODE_JFIF 2 /* "10" = JFIF header */
  5496. #endif /* MRV_JPE_HEADER_MODE */
  5497. /*****************************************************************************/
  5498. /**
  5499. * register: jpe_encode_mode: encode mode (0x00000060)
  5500. *
  5501. *****************************************************************************/
  5502. /* Slice: encode_mode:*/
  5503. /* Always "1", because this is the encoder only edition */
  5504. #ifdef MRV_JPE_ENCODE_MODE
  5505. #endif /* MRV_JPE_ENCODE_MODE */
  5506. /*****************************************************************************/
  5507. /**
  5508. * register: jpe_debug: debug information register (0x00000064)
  5509. *
  5510. *****************************************************************************/
  5511. /* Slice: deb_bad_table_access:*/
  5512. /* Debug signal only (set if an access to the TABLE_DATA or to the TABLE_ID */
  5513. /* register is performed, when the JPEG_ENCODER is busy. In this case a default */
  5514. /* PVCI Acknowledge is generated. Thus the configuration bus is not blocked)*/
  5515. #ifdef MRV_JPE_DEB_BAD_TABLE_ACCESS
  5516. #endif /* MRV_JPE_DEB_BAD_TABLE_ACCESS */
  5517. /* Slice: deb_vlc_table_busy:*/
  5518. /* Debug signal only (vlc access to huff-tables)*/
  5519. #ifdef MRV_JPE_DEB_VLC_TABLE_BUSY
  5520. #endif /* MRV_JPE_DEB_VLC_TABLE_BUSY */
  5521. /* Slice: deb_r2b_memory_full:*/
  5522. /* Debug signal only (line memory status of r2b)*/
  5523. #ifdef MRV_JPE_DEB_R2B_MEMORY_FULL
  5524. #endif /* MRV_JPE_DEB_R2B_MEMORY_FULL */
  5525. /* Slice: deb_vlc_encode_busy:*/
  5526. /* Debug signal only (vlc encode processing active)*/
  5527. #ifdef MRV_JPE_DEB_VLC_ENCODE_BUSY
  5528. #endif /* MRV_JPE_DEB_VLC_ENCODE_BUSY */
  5529. /* Slice: deb_qiq_table_acc:*/
  5530. /* Debug signal only (QIQ table access)*/
  5531. #ifdef MRV_JPE_DEB_QIQ_TABLE_ACC
  5532. #endif /* MRV_JPE_DEB_QIQ_TABLE_ACC */
  5533. /*****************************************************************************/
  5534. /**
  5535. * register: jpe_error_imr: JPEG error interrupt mask register (0x00000068)
  5536. * jpe_error_ris: JPEG error raw interrupt status register (0x0000006c)
  5537. * jpe_error_mis: JPEG error masked interrupt status register (0x00000070)
  5538. * jpe_error_icr: JPEG error interrupt set register (0x00000074)
  5539. * jpe_error_isr: JPEG error interrupt clear register (0x00000078)
  5540. *
  5541. *****************************************************************************/
  5542. /* Slice: vlc_table_err:*/
  5543. /* "1" = interrupt is activated (masked in)*/
  5544. #ifdef MRV_JPE_VLC_TABLE_ERR
  5545. #endif /* MRV_JPE_VLC_TABLE_ERR */
  5546. /* Slice: r2b_IMG_size_err:*/
  5547. /* "1" = interrupt is activated (masked in)*/
  5548. #ifdef MRV_JPE_R2B_IMG_SIZE_ERR
  5549. #endif /* MRV_JPE_R2B_IMG_SIZE_ERR */
  5550. /* Slice: DCT_ERR:*/
  5551. /* "1" = interrupt is activated (masked in)*/
  5552. #ifdef MRV_JPE_DCT_ERR
  5553. #endif /* MRV_JPE_DCT_ERR */
  5554. /* Slice: vlc_symbol_err:*/
  5555. /* "1" = interrupt is activated (masked in)*/
  5556. #ifdef MRV_JPE_VLC_SYMBOL_ERR
  5557. #endif /* MRV_JPE_VLC_SYMBOL_ERR */
  5558. /*****************************************************************************/
  5559. /**
  5560. * register: jpe_status_imr: JPEG status interrupt mask register (0x0000007c)
  5561. * jpe_status_ris: JPEG status raw interrupt status register (0x00000080)
  5562. * jpe_status_mis: JPEG status masked interrupt status register (0x00000084)
  5563. * jpe_status_icr: JPEG status interrupt clear register (0x00000088)
  5564. * jpe_status_isr: JPEG status interrupt set register (0x0000008c)
  5565. *
  5566. *****************************************************************************/
  5567. /* Slice: gen_header_done:*/
  5568. /* "1" = interrupt is activated (masked in)*/
  5569. #ifdef MRV_JPE_GEN_HEADER_DONE
  5570. #endif /* MRV_JPE_GEN_HEADER_DONE */
  5571. /* Slice: encode_done:*/
  5572. /* "1" = interrupt is activated (masked in)*/
  5573. #ifdef MRV_JPE_ENCODE_DONE
  5574. #endif /* MRV_JPE_ENCODE_DONE */
  5575. /*****************************************************************************/
  5576. /**
  5577. * register: jpe_config: JPEG configuration register (0x00000090)
  5578. *
  5579. *****************************************************************************/
  5580. /* Slice: speedview_en:*/
  5581. /* 1: speed view enabled */
  5582. /* 0: speed view disabled */
  5583. #ifdef MRV_JPE_SPEEDVIEW_EN
  5584. #define MRV_JPE_SPEEDVIEW_EN_DISABLE 0 /* "0": JPEG Stream Encoding according to JPEG standard */
  5585. #define MRV_JPE_SPEEDVIEW_EN_ENABLE 1 /* "1": SpeedView JPEG Stream Encoding enabled */
  5586. #endif /* MRV_JPE_SPEEDVIEW_EN */
  5587. /* Slice: cont_mode:*/
  5588. /* Encoder continous mode */
  5589. /* "00": encoder stops at frame end (corresponds to former behavior)*/
  5590. /* "01": encoder starts automatically to encode the next frame */
  5591. /* "10": unused */
  5592. /* "11": encoder first generates next header and then encodes automatically the next frame */
  5593. /* These settings are checked after encoding one frame. They are not auto-reset by hardware.*/
  5594. #ifdef MRV_JPE_CONT_MODE
  5595. #define MRV_JPE_CONT_MODE_STOP 0 /* "00": encoder stops at frame end (corresponds to former behavior) */
  5596. #define MRV_JPE_CONT_MODE_NEXT 1 /* "01": encoder starts automatically to encode the next frame */
  5597. #define MRV_JPE_CONT_MODE_HEADER 3 /* "11": encoder first generates next header and then encodes automatically the next frame */
  5598. #endif /* MRV_JPE_CONT_MODE */
  5599. /*****************************************************************************/
  5600. /* MIPI Registers */
  5601. /*****************************************************************************/
  5602. /*****************************************************************************/
  5603. /**
  5604. * register: mipi_ctrl: global control register (0x0000)
  5605. *
  5606. *****************************************************************************/
  5607. /* Slice: S_ENABLE_CLK */
  5608. /* 1: enable sensor clock lane (DEFAULT)*/
  5609. /* 0: disable sensor clock lane */
  5610. #ifdef MRV_MIPI_S_ENABLE_CLK
  5611. #endif /* MRV_MIPI_S_ENABLE_CLK */
  5612. /* Slice: ERR_SOT_SYNC_HS_SKIP:*/
  5613. /* 1: data within the current transmission is skipped if ErrSotSyncHS is detected (default)*/
  5614. /* 0: ErrSotSyncHS does not affect transmission */
  5615. #ifdef MRV_MIPI_ERR_SOT_SYNC_HS_SKIP
  5616. #endif /* MRV_MIPI_ERR_SOT_SYNC_HS_SKIP */
  5617. /* Slice: ERR_SOT_HS_SKIP:*/
  5618. /* 1: data within the current transmission is skipped if ErrSotHS is detected */
  5619. /* 0: ErrSotHS does not affect transmission (default)*/
  5620. #ifdef MRV_MIPI_ERR_SOT_HS_SKIP
  5621. #endif /* MRV_MIPI_ERR_SOT_HS_SKIP */
  5622. /* Slice: NUM_LANES:*/
  5623. /* 00: Lane 1 is used;*/
  5624. /* 01: Lanes 1 and 2 are used;*/
  5625. /* 10: Lanes 1...3 are used;*/
  5626. /* 11: Lanes 1...4 are used */
  5627. #ifdef MRV_MIPI_NUM_LANES
  5628. #define MRV_MIPI_NUM_LANES_1 0 /* 00: Lane 1 is used */
  5629. #define MRV_MIPI_NUM_LANES_2 1 /* 01: Lanes 1 and 2 are used */
  5630. #define MRV_MIPI_NUM_LANES_3 2 /* 10: Lanes 1...3 are used */
  5631. #define MRV_MIPI_NUM_LANES_4 3 /* 11: Lanes 1...4 are used */
  5632. #endif /* MRV_MIPI_NUM_LANES */
  5633. /* Slice: SHUTDOWN_LANE:*/
  5634. /* Shutdown Lane Module. Content of this register is directly connected to the output signal shutdown[n-1:0]*/
  5635. #ifdef MRV_MIPI_SHUTDOWN_LANE
  5636. #define MRV_MIPI_SHUTDOWN_LANE_1 1 /* 0001: shutdown lane 1 */
  5637. #define MRV_MIPI_SHUTDOWN_LANE_2 2 /* 0010: shutdown lane 1 */
  5638. #define MRV_MIPI_SHUTDOWN_LANE_3 4 /* 0100: shutdown lane 1 */
  5639. #define MRV_MIPI_SHUTDOWN_LANE_4 8 /* 1000: shutdown lane 1 */
  5640. #endif /* MRV_MIPI_SHUTDOWN_LANE */
  5641. /* Slice: FLUSH_FIFO:*/
  5642. /* writing '1' resets the write- and read pointers of the additional data fifo.*/
  5643. #ifdef MRV_MIPI_FLUSH_FIFO
  5644. #endif /* MRV_MIPI_FLUSH_FIFO */
  5645. /* Slice: OUTPUT_ENA:*/
  5646. /* 1: output to add data fifo and to output interface is enabled */
  5647. #ifdef MRV_MIPI_OUTPUT_ENA
  5648. #endif /* MRV_MIPI_OUTPUT_ENA */
  5649. /*****************************************************************************/
  5650. /**
  5651. * register: mipi_status: global status register (0x0004)
  5652. *
  5653. *****************************************************************************/
  5654. /* Slice: S_ULP_ACTIVE_NOT_CLK:*/
  5655. /* sensor clock lane is in ULP state. This register is directly connected to the synchronized input signal "s_ulpsactivenotclk"*/
  5656. #ifdef MRV_MIPI_S_ULP_ACTIVE_NOT_CLK
  5657. #endif /* MRV_MIPI_S_ULP_ACTIVE_NOT_CLK */
  5658. /* Slice: S_STOPSTATE_CLK:*/
  5659. /* sensor clock lane is in stopstate. This register is directly connected to the synchronized input signal "s_stopstateclk"*/
  5660. #ifdef MRV_MIPI_S_STOPSTATE_CLK
  5661. #endif /* MRV_MIPI_S_STOPSTATE_CLK */
  5662. /* Slice: STOPSTATE:*/
  5663. /* Lane is in stopstate. This register is directly connected to the synchronized input signal stopstate[n-1:0]*/
  5664. #ifdef MRV_MIPI_STOPSTATE
  5665. #endif /* MRV_MIPI_STOPSTATE */
  5666. /* Slice: ADD_DATA_AVAIL:*/
  5667. /* 1: additional data fifo contains data */
  5668. /* 0: additional data fifo is empty */
  5669. #ifdef MRV_MIPI_ADD_DATA_AVAIL
  5670. #endif /* MRV_MIPI_ADD_DATA_AVAIL */
  5671. /*****************************************************************************/
  5672. /**
  5673. * register: mipi_imsc: Interrupt mask (0x00000008)
  5674. *
  5675. *****************************************************************************/
  5676. /* Slice: IMSC_GEN_SHORT_PACK:*/
  5677. /* enable interrupt (1) or mask out (0)*/
  5678. #ifndef MRV_MIPI_IMSC_GEN_SHORT_PACK
  5679. #define MRV_MIPI_IMSC_GEN_SHORT_PACK_MASK 0
  5680. #endif /* MRV_MIPI_IMSC_GEN_SHORT_PACK */
  5681. /* Slice: IMSC_ADD_DATA_FILL_LEVEL:*/
  5682. /* enable interrupt (1) or mask out (0)*/
  5683. #ifndef MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL
  5684. #define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_MASK 0
  5685. #endif /* MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL */
  5686. /* Slice: IMSC_ADD_DATA_OVFLW:*/
  5687. /* enable interrupt (1) or mask out (0)*/
  5688. #ifndef MRV_MIPI_IMSC_ADD_DATA_OVFLW
  5689. #endif /* MRV_MIPI_IMSC_ADD_DATA_OVFLW */
  5690. /* Slice: IMSC_FRAME_END:*/
  5691. /* enable interrupt (1) or mask out (0)*/
  5692. #ifndef MRV_MIPI_IMSC_FRAME_END
  5693. #define MRV_MIPI_IMSC_FRAME_END_MASK 0
  5694. #endif /* MRV_MIPI_IMSC_ADD_DATA_OVFLW */
  5695. /* Slice: IMSC_ERR_CS:*/
  5696. /* enable interrupt (1) or mask out (0)*/
  5697. #ifndef MRV_MIPI_IMSC_ERR_CS
  5698. #define MRV_MIPI_IMSC_ERR_CS_MASK 0
  5699. #endif /* MRV_MIPI_IMSC_ERR_CS */
  5700. /* Slice: IMSC_ERR_ECC1:*/
  5701. /* enable interrupt (1) or mask out (0)*/
  5702. #ifndef MRV_MIPI_IMSC_ERR_ECC1
  5703. #define MRV_MIPI_IMSC_ERR_ECC1_MASK 0
  5704. #endif /* MRV_MIPI_IMSC_ERR_ECC1 */
  5705. /* Slice: IMSC_ERR_ECC2:*/
  5706. /* enable interrupt (1) or mask out (0)*/
  5707. #ifndef MRV_MIPI_IMSC_ERR_ECC2
  5708. #define MRV_MIPI_IMSC_ERR_ECC2_MASK 0
  5709. #endif /* MRV_MIPI_IMSC_ERR_ECC2 */
  5710. /* Slice: IMSC_ERR_PROTOCOL:*/
  5711. /* enable interrupt (1) or mask out (0)*/
  5712. #ifndef MRV_MIPI_IMSC_ERR_PROTOCOL
  5713. #define MRV_MIPI_IMSC_ERR_PROTOCOL_MASK 0
  5714. #endif /* MRV_MIPI_IMSC_ERR_PROTOCOL */
  5715. /* Slice: IMSC_ERR_CONTROL:*/
  5716. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5717. #ifndef MRV_MIPI_IMSC_ERR_CONTROL
  5718. #define MRV_MIPI_IMSC_ERR_CONTROL_MASK 0
  5719. #endif /* MRV_MIPI_IMSC_ERR_CONTROL */
  5720. /* Slice: IMSC_ERR_EOT_SYNC:*/
  5721. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5722. #ifndef MRV_MIPI_IMSC_ERR_EOT_SYNC
  5723. #define MRV_MIPI_IMSC_ERR_EOT_SYNC_MASK 0
  5724. #endif /* MRV_MIPI_IMSC_ERR_EOT_SYNC */
  5725. /* Slice: IMSC_ERR_SOT_SYNC:*/
  5726. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5727. #ifndef MRV_MIPI_IMSC_ERR_SOT_SYNC
  5728. #define MRV_MIPI_IMSC_ERR_SOT_SYNC_MASK 0
  5729. #endif /* MRV_MIPI_IMSC_ERR_SOT_SYNC */
  5730. /* Slice: IMSC_ERR_SOT:*/
  5731. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5732. #ifndef MRV_MIPI_IMSC_ERR_SOT
  5733. #define MRV_MIPI_IMSC_ERR_SOT_MASK 0
  5734. #endif /* MRV_MIPI_IMSC_ERR_SOT */
  5735. /* Slice: IMSC_SYNC_FIFO_OVFLW:*/
  5736. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5737. #ifndef MRV_MIPI_IMSC_SYNC_FIFO_OVFLW
  5738. #define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_MASK 0
  5739. #endif /* MRV_MIPI_IMSC_SYNC_FIFO_OVFLW */
  5740. /* combination of all interrupt lines */
  5741. #define MRV_MIPI_IMSC_ALL_IRQS
  5742. #define MRV_MIPI_IMSC_ALL_IRQS_MASK \
  5743. (MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_MASK \
  5744. | MRV_MIPI_IMSC_ADD_DATA_OVFLW_MASK \
  5745. | MRV_MIPI_IMSC_FRAME_END_MASK \
  5746. | MRV_MIPI_IMSC_ERR_CS_MASK \
  5747. | MRV_MIPI_IMSC_ERR_ECC1_MASK \
  5748. | MRV_MIPI_IMSC_ERR_ECC2_MASK \
  5749. | MRV_MIPI_IMSC_ERR_PROTOCOL_MASK \
  5750. | MRV_MIPI_IMSC_ERR_CONTROL_MASK \
  5751. | MRV_MIPI_IMSC_ERR_EOT_SYNC_MASK \
  5752. | MRV_MIPI_IMSC_ERR_SOT_SYNC_MASK \
  5753. | MRV_MIPI_IMSC_ERR_SOT_MASK \
  5754. | MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_MASK \
  5755. )
  5756. #define MRV_MIPI_IMSC_ALL_IRQS_SHIFT 0
  5757. /*****************************************************************************/
  5758. /**
  5759. * register: mipi_ris: Raw interrupt status (0x0000000c)
  5760. *
  5761. *****************************************************************************/
  5762. /* Slice: RIS_GEN_SHORT_PACK:*/
  5763. /* enable interrupt (1) or mask out (0)*/
  5764. #ifndef MRV_MIPI_RIS_GEN_SHORT_PACK
  5765. #define MRV_MIPI_RIS_GEN_SHORT_PACK_MASK 0
  5766. #endif /* MRV_MIPI_RIS_GEN_SHORT_PACK */
  5767. /* Slice: RIS_ADD_DATA_FILL_LEVEL:*/
  5768. /* enable interrupt (1) or mask out (0)*/
  5769. #ifndef MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL
  5770. #define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_MASK 0
  5771. #endif /* MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL */
  5772. /* Slice: RIS_ADD_DATA_OVFLW:*/
  5773. /* enable interrupt (1) or mask out (0)*/
  5774. #ifndef MRV_MIPI_RIS_ADD_DATA_OVFLW
  5775. #endif /* MRV_MIPI_RIS_ADD_DATA_OVFLW */
  5776. /* Slice: RIS_FRAME_END:*/
  5777. /* enable interrupt (1) or mask out (0)*/
  5778. #ifndef MRV_MIPI_RIS_FRAME_END
  5779. #define MRV_MIPI_RIS_FRAME_END_MASK 0
  5780. #endif /* MRV_MIPI_RIS_ADD_DATA_OVFLW */
  5781. /* Slice: RIS_ERR_CS:*/
  5782. /* enable interrupt (1) or mask out (0)*/
  5783. #ifndef MRV_MIPI_RIS_ERR_CS
  5784. #define MRV_MIPI_RIS_ERR_CS_MASK 0
  5785. #endif /* MRV_MIPI_RIS_ERR_CS */
  5786. /* Slice: RIS_ERR_ECC1:*/
  5787. /* enable interrupt (1) or mask out (0)*/
  5788. #ifndef MRV_MIPI_RIS_ERR_ECC1
  5789. #define MRV_MIPI_RIS_ERR_ECC1_MASK 0
  5790. #endif /* MRV_MIPI_RIS_ERR_ECC1 */
  5791. /* Slice: RIS_ERR_ECC2:*/
  5792. /* enable interrupt (1) or mask out (0)*/
  5793. #ifndef MRV_MIPI_RIS_ERR_ECC2
  5794. #define MRV_MIPI_RIS_ERR_ECC2_MASK 0
  5795. #endif /* MRV_MIPI_RIS_ERR_ECC2 */
  5796. /* Slice: RIS_ERR_PROTOCOL:*/
  5797. /* enable interrupt (1) or mask out (0)*/
  5798. #ifndef MRV_MIPI_RIS_ERR_PROTOCOL
  5799. #define MRV_MIPI_RIS_ERR_PROTOCOL_MASK 0
  5800. #endif /* MRV_MIPI_RIS_ERR_PROTOCOL */
  5801. /* Slice: RIS_ERR_CONTROL:*/
  5802. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5803. #ifndef MRV_MIPI_RIS_ERR_CONTROL
  5804. #define MRV_MIPI_RIS_ERR_CONTROL_MASK 0
  5805. #endif /* MRV_MIPI_RIS_ERR_CONTROL */
  5806. /* Slice: RIS_ERR_EOT_SYNC:*/
  5807. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5808. #ifndef MRV_MIPI_RIS_ERR_EOT_SYNC
  5809. #define MRV_MIPI_RIS_ERR_EOT_SYNC_MASK 0
  5810. #endif /* MRV_MIPI_RIS_ERR_EOT_SYNC */
  5811. /* Slice: RIS_ERR_SOT_SYNC:*/
  5812. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5813. #ifndef MRV_MIPI_RIS_ERR_SOT_SYNC
  5814. #define MRV_MIPI_RIS_ERR_SOT_SYNC_MASK 0
  5815. #endif /* MRV_MIPI_RIS_ERR_SOT_SYNC */
  5816. /* Slice: RIS_ERR_SOT:*/
  5817. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5818. #ifndef MRV_MIPI_RIS_ERR_SOT
  5819. #define MRV_MIPI_RIS_ERR_SOT_MASK 0
  5820. #endif /* MRV_MIPI_RIS_ERR_SOT */
  5821. /* Slice: RIS_SYNC_FIFO_OVFLW:*/
  5822. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5823. #ifndef MRV_MIPI_RIS_SYNC_FIFO_OVFLW
  5824. #define MRV_MIPI_RIS_SYNC_FIFO_OVFLW_MASK 0
  5825. #endif /* MRV_MIPI_RIS_SYNC_FIFO_OVFLW */
  5826. /* combination of all interrupt lines */
  5827. #define MRV_MIPI_RIS_ALL_IRQS
  5828. #define MRV_MIPI_RIS_ALL_IRQS_MASK \
  5829. (MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_MASK \
  5830. | MRV_MIPI_RIS_ADD_DATA_OVFLW_MASK \
  5831. | MRV_MIPI_RIS_FRAME_END_MASK \
  5832. | MRV_MIPI_RIS_ERR_CS_MASK \
  5833. | MRV_MIPI_RIS_ERR_ECC1_MASK \
  5834. | MRV_MIPI_RIS_ERR_ECC2_MASK \
  5835. | MRV_MIPI_RIS_ERR_PROTOCOL_MASK \
  5836. | MRV_MIPI_RIS_ERR_CONTROL_MASK \
  5837. | MRV_MIPI_RIS_ERR_EOT_SYNC_MASK \
  5838. | MRV_MIPI_RIS_ERR_SOT_SYNC_MASK \
  5839. | MRV_MIPI_RIS_ERR_SOT_MASK \
  5840. | MRV_MIPI_RIS_SYNC_FIFO_OVFLW_MASK \
  5841. )
  5842. #define MRV_MIPI_RIS_ALL_IRQS_SHIFT 0
  5843. /*****************************************************************************/
  5844. /**
  5845. * register: mipi_mis: Masked interrupt status (0x00000010)
  5846. *
  5847. *****************************************************************************/
  5848. /* Slice: MIS_GEN_SHORT_PACK:*/
  5849. /* enable interrupt (1) or mask out (0)*/
  5850. #ifndef MRV_MIPI_MIS_GEN_SHORT_PACK
  5851. #define MRV_MIPI_MIS_GEN_SHORT_PACK_MASK 0
  5852. #endif /* MRV_MIPI_MIS_GEN_SHORT_PACK */
  5853. /* Slice: MIS_ADD_DATA_FILL_LEVEL:*/
  5854. /* enable interrupt (1) or mask out (0)*/
  5855. #ifndef MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL
  5856. #define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_MASK 0
  5857. #endif /* MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL */
  5858. /* Slice: MIS_ADD_DATA_OVFLW:*/
  5859. /* enable interrupt (1) or mask out (0)*/
  5860. #ifndef MRV_MIPI_MIS_ADD_DATA_OVFLW
  5861. #endif /* MRV_MIPI_MIS_ADD_DATA_OVFLW */
  5862. /* Slice: MIS_FRAME_END:*/
  5863. /* enable interrupt (1) or mask out (0)*/
  5864. #ifndef MRV_MIPI_MIS_FRAME_END
  5865. #define MRV_MIPI_MIS_FRAME_END_MASK 0
  5866. #endif /* MRV_MIPI_MIS_ADD_DATA_OVFLW */
  5867. /* Slice: MIS_ERR_CS:*/
  5868. /* enable interrupt (1) or mask out (0)*/
  5869. #ifndef MRV_MIPI_MIS_ERR_CS
  5870. #define MRV_MIPI_MIS_ERR_CS_MASK 0
  5871. #endif /* MRV_MIPI_MIS_ERR_CS */
  5872. /* Slice: MIS_ERR_ECC1:*/
  5873. /* enable interrupt (1) or mask out (0)*/
  5874. #ifndef MRV_MIPI_MIS_ERR_ECC1
  5875. #define MRV_MIPI_MIS_ERR_ECC1_MASK 0
  5876. #endif /* MRV_MIPI_MIS_ERR_ECC1 */
  5877. /* Slice: MIS_ERR_ECC2:*/
  5878. /* enable interrupt (1) or mask out (0)*/
  5879. #ifndef MRV_MIPI_MIS_ERR_ECC2
  5880. #define MRV_MIPI_MIS_ERR_ECC2_MASK 0
  5881. #endif /* MRV_MIPI_MIS_ERR_ECC2 */
  5882. /* Slice: MIS_ERR_PROTOCOL:*/
  5883. /* enable interrupt (1) or mask out (0)*/
  5884. #ifndef MRV_MIPI_MIS_ERR_PROTOCOL
  5885. #define MRV_MIPI_MIS_ERR_PROTOCOL_MASK 0
  5886. #endif /* MRV_MIPI_MIS_ERR_PROTOCOL */
  5887. /* Slice: MIS_ERR_CONTROL:*/
  5888. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5889. #ifndef MRV_MIPI_MIS_ERR_CONTROL
  5890. #define MRV_MIPI_MIS_ERR_CONTROL_MASK 0
  5891. #endif /* MRV_MIPI_MIS_ERR_CONTROL */
  5892. /* Slice: MIS_ERR_EOT_SYNC:*/
  5893. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5894. #ifndef MRV_MIPI_MIS_ERR_EOT_SYNC
  5895. #define MRV_MIPI_MIS_ERR_EOT_SYNC_MASK 0
  5896. #endif /* MRV_MIPI_MIS_ERR_EOT_SYNC */
  5897. /* Slice: MIS_ERR_SOT_SYNC:*/
  5898. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5899. #ifndef MRV_MIPI_MIS_ERR_SOT_SYNC
  5900. #define MRV_MIPI_MIS_ERR_SOT_SYNC_MASK 0
  5901. #endif /* MRV_MIPI_MIS_ERR_SOT_SYNC */
  5902. /* Slice: MIS_ERR_SOT:*/
  5903. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5904. #ifndef MRV_MIPI_MIS_ERR_SOT
  5905. #define MRV_MIPI_MIS_ERR_SOT_MASK 0
  5906. #endif /* MRV_MIPI_MIS_ERR_SOT */
  5907. /* Slice: MIS_SYNC_FIFO_OVFLW:*/
  5908. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5909. #ifndef MRV_MIPI_MIS_SYNC_FIFO_OVFLW
  5910. #define MRV_MIPI_MIS_SYNC_FIFO_OVFLW_MASK 0
  5911. #endif /* MRV_MIPI_MIS_SYNC_FIFO_OVFLW */
  5912. /* combination of all interrupt lines */
  5913. #define MRV_MIPI_MIS_ALL_IRQS
  5914. #define MRV_MIPI_MIS_ALL_IRQS_MASK \
  5915. (MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_MASK \
  5916. | MRV_MIPI_MIS_ADD_DATA_OVFLW_MASK \
  5917. | MRV_MIPI_MIS_FRAME_END_MASK \
  5918. | MRV_MIPI_MIS_ERR_CS_MASK \
  5919. | MRV_MIPI_MIS_ERR_ECC1_MASK \
  5920. | MRV_MIPI_MIS_ERR_ECC2_MASK \
  5921. | MRV_MIPI_MIS_ERR_PROTOCOL_MASK \
  5922. | MRV_MIPI_MIS_ERR_CONTROL_MASK \
  5923. | MRV_MIPI_MIS_ERR_EOT_SYNC_MASK \
  5924. | MRV_MIPI_MIS_ERR_SOT_SYNC_MASK \
  5925. | MRV_MIPI_MIS_ERR_SOT_MASK \
  5926. | MRV_MIPI_MIS_SYNC_FIFO_OVFLW_MASK \
  5927. )
  5928. #define MRV_MIPI_MIS_ALL_IRQS_SHIFT 0
  5929. /*****************************************************************************/
  5930. /**
  5931. * register: mipi_icr: Interrupt clear register (0x00000014)
  5932. *
  5933. *****************************************************************************/
  5934. /* Slice: ICR_GEN_SHORT_PACK:*/
  5935. /* enable interrupt (1) or mask out (0)*/
  5936. #ifndef MRV_MIPI_ICR_GEN_SHORT_PACK
  5937. #define MRV_MIPI_ICR_GEN_SHORT_PACK_MASK 0
  5938. #endif /* MRV_MIPI_ICR_GEN_SHORT_PACK */
  5939. /* Slice: ICR_ADD_DATA_FILL_LEVEL:*/
  5940. /* enable interrupt (1) or mask out (0)*/
  5941. #ifndef MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL
  5942. #define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_MASK 0
  5943. #endif /* MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL */
  5944. /* Slice: ICR_ADD_DATA_OVFLW:*/
  5945. /* enable interrupt (1) or mask out (0)*/
  5946. #ifndef MRV_MIPI_ICR_ADD_DATA_OVFLW
  5947. #endif /* MRV_MIPI_ICR_ADD_DATA_OVFLW */
  5948. /* Slice: ICR_FRAME_END:*/
  5949. /* enable interrupt (1) or mask out (0)*/
  5950. #ifndef MRV_MIPI_ICR_FRAME_END
  5951. #define MRV_MIPI_ICR_FRAME_END_MASK 0
  5952. #endif /* MRV_MIPI_ICR_ADD_DATA_OVFLW */
  5953. /* Slice: ICR_ERR_CS:*/
  5954. /* enable interrupt (1) or mask out (0)*/
  5955. #ifndef MRV_MIPI_ICR_ERR_CS
  5956. #define MRV_MIPI_ICR_ERR_CS_MASK 0
  5957. #endif /* MRV_MIPI_ICR_ERR_CS */
  5958. /* Slice: ICR_ERR_ECC1:*/
  5959. /* enable interrupt (1) or mask out (0)*/
  5960. #ifndef MRV_MIPI_ICR_ERR_ECC1
  5961. #define MRV_MIPI_ICR_ERR_ECC1_MASK 0
  5962. #endif /* MRV_MIPI_ICR_ERR_ECC1 */
  5963. /* Slice: ICR_ERR_ECC2:*/
  5964. /* enable interrupt (1) or mask out (0)*/
  5965. #ifndef MRV_MIPI_ICR_ERR_ECC2
  5966. #define MRV_MIPI_ICR_ERR_ECC2_MASK 0
  5967. #endif /* MRV_MIPI_ICR_ERR_ECC2 */
  5968. /* Slice: ICR_ERR_PROTOCOL:*/
  5969. /* enable interrupt (1) or mask out (0)*/
  5970. #ifndef MRV_MIPI_ICR_ERR_PROTOCOL
  5971. #define MRV_MIPI_ICR_ERR_PROTOCOL_MASK 0
  5972. #endif /* MRV_MIPI_ICR_ERR_PROTOCOL */
  5973. /* Slice: ICR_ERR_CONTROL:*/
  5974. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5975. #ifndef MRV_MIPI_ICR_ERR_CONTROL
  5976. #define MRV_MIPI_ICR_ERR_CONTROL_MASK 0
  5977. #endif /* MRV_MIPI_ICR_ERR_CONTROL */
  5978. /* Slice: ICR_ERR_EOT_SYNC:*/
  5979. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5980. #ifndef MRV_MIPI_ICR_ERR_EOT_SYNC
  5981. #define MRV_MIPI_ICR_ERR_EOT_SYNC_MASK 0
  5982. #endif /* MRV_MIPI_ICR_ERR_EOT_SYNC */
  5983. /* Slice: ICR_ERR_SOT_SYNC:*/
  5984. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5985. #ifndef MRV_MIPI_ICR_ERR_SOT_SYNC
  5986. #define MRV_MIPI_ICR_ERR_SOT_SYNC_MASK 0
  5987. #endif /* MRV_MIPI_ICR_ERR_SOT_SYNC */
  5988. /* Slice: ICR_ERR_SOT:*/
  5989. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5990. #ifndef MRV_MIPI_ICR_ERR_SOT
  5991. #define MRV_MIPI_ICR_ERR_SOT_MASK 0
  5992. #endif /* MRV_MIPI_ICR_ERR_SOT */
  5993. /* Slice: ICR_SYNC_FIFO_OVFLW:*/
  5994. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5995. #ifndef MRV_MIPI_ICR_SYNC_FIFO_OVFLW
  5996. #define MRV_MIPI_ICR_SYNC_FIFO_OVFLW_MASK 0
  5997. #endif /* MRV_MIPI_ICR_SYNC_FIFO_OVFLW */
  5998. /* combination of all interrupt lines */
  5999. #define MRV_MIPI_ICR_ALL_IRQS
  6000. #define MRV_MIPI_ICR_ALL_IRQS_MASK \
  6001. (MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_MASK \
  6002. | MRV_MIPI_ICR_ADD_DATA_OVFLW_MASK \
  6003. | MRV_MIPI_ICR_FRAME_END_MASK \
  6004. | MRV_MIPI_ICR_ERR_CS_MASK \
  6005. | MRV_MIPI_ICR_ERR_ECC1_MASK \
  6006. | MRV_MIPI_ICR_ERR_ECC2_MASK \
  6007. | MRV_MIPI_ICR_ERR_PROTOCOL_MASK \
  6008. | MRV_MIPI_ICR_ERR_CONTROL_MASK \
  6009. | MRV_MIPI_ICR_ERR_EOT_SYNC_MASK \
  6010. | MRV_MIPI_ICR_ERR_SOT_SYNC_MASK \
  6011. | MRV_MIPI_ICR_ERR_SOT_MASK \
  6012. | MRV_MIPI_ICR_SYNC_FIFO_OVFLW_MASK \
  6013. )
  6014. #define MRV_MIPI_ICR_ALL_IRQS_SHIFT 0
  6015. /*****************************************************************************/
  6016. /**
  6017. * register: mipi_isr: Interrupt set register (0x00000018)
  6018. *
  6019. *****************************************************************************/
  6020. /* Slice: ISR_GEN_SHORT_PACK:*/
  6021. /* enable interrupt (1) or mask out (0)*/
  6022. #ifndef MRV_MIPI_ISR_GEN_SHORT_PACK
  6023. #define MRV_MIPI_ISR_GEN_SHORT_PACK_MASK 0
  6024. #endif /* MRV_MIPI_ISR_GEN_SHORT_PACK */
  6025. /* Slice: ISR_ADD_DATA_FILL_LEVEL:*/
  6026. /* enable interrupt (1) or mask out (0)*/
  6027. #ifndef MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL
  6028. #define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_MASK 0
  6029. #endif /* MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL */
  6030. /* Slice: ISR_ADD_DATA_OVFLW:*/
  6031. /* enable interrupt (1) or mask out (0)*/
  6032. #ifndef MRV_MIPI_ISR_ADD_DATA_OVFLW
  6033. #endif /* MRV_MIPI_ISR_ADD_DATA_OVFLW */
  6034. /* Slice: ISR_FRAME_END:*/
  6035. /* enable interrupt (1) or mask out (0)*/
  6036. #ifndef MRV_MIPI_ISR_FRAME_END
  6037. #define MRV_MIPI_ISR_FRAME_END_MASK 0
  6038. #endif /* MRV_MIPI_ISR_ADD_DATA_OVFLW */
  6039. /* Slice: ISR_ERR_CS:*/
  6040. /* enable interrupt (1) or mask out (0)*/
  6041. #ifndef MRV_MIPI_ISR_ERR_CS
  6042. #define MRV_MIPI_ISR_ERR_CS_MASK 0
  6043. #endif /* MRV_MIPI_ISR_ERR_CS */
  6044. /* Slice: ISR_ERR_ECC1:*/
  6045. /* enable interrupt (1) or mask out (0)*/
  6046. #ifndef MRV_MIPI_ISR_ERR_ECC1
  6047. #define MRV_MIPI_ISR_ERR_ECC1_MASK 0
  6048. #endif /* MRV_MIPI_ISR_ERR_ECC1 */
  6049. /* Slice: ISR_ERR_ECC2:*/
  6050. /* enable interrupt (1) or mask out (0)*/
  6051. #ifndef MRV_MIPI_ISR_ERR_ECC2
  6052. #define MRV_MIPI_ISR_ERR_ECC2_MASK 0
  6053. #endif /* MRV_MIPI_ISR_ERR_ECC2 */
  6054. /* Slice: ISR_ERR_PROTOCOL:*/
  6055. /* enable interrupt (1) or mask out (0)*/
  6056. #ifndef MRV_MIPI_ISR_ERR_PROTOCOL
  6057. #define MRV_MIPI_ISR_ERR_PROTOCOL_MASK 0
  6058. #endif /* MRV_MIPI_ISR_ERR_PROTOCOL */
  6059. /* Slice: ISR_ERR_CONTROL:*/
  6060. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  6061. #ifndef MRV_MIPI_ISR_ERR_CONTROL
  6062. #define MRV_MIPI_ISR_ERR_CONTROL_MASK 0
  6063. #endif /* MRV_MIPI_ISR_ERR_CONTROL */
  6064. /* Slice: ISR_ERR_EOT_SYNC:*/
  6065. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  6066. #ifndef MRV_MIPI_ISR_ERR_EOT_SYNC
  6067. #define MRV_MIPI_ISR_ERR_EOT_SYNC_MASK 0
  6068. #endif /* MRV_MIPI_ISR_ERR_EOT_SYNC */
  6069. /* Slice: ISR_ERR_SOT_SYNC:*/
  6070. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  6071. #ifndef MRV_MIPI_ISR_ERR_SOT_SYNC
  6072. #define MRV_MIPI_ISR_ERR_SOT_SYNC_MASK 0
  6073. #endif /* MRV_MIPI_ISR_ERR_SOT_SYNC */
  6074. /* Slice: ISR_ERR_SOT:*/
  6075. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  6076. #ifndef MRV_MIPI_ISR_ERR_SOT
  6077. #define MRV_MIPI_ISR_ERR_SOT_MASK 0
  6078. #endif /* MRV_MIPI_ISR_ERR_SOT */
  6079. /* Slice: ISR_SYNC_FIFO_OVFLW:*/
  6080. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  6081. #ifndef MRV_MIPI_ISR_SYNC_FIFO_OVFLW
  6082. #define MRV_MIPI_ISR_SYNC_FIFO_OVFLW_MASK 0
  6083. #endif /* MRV_MIPI_ISR_SYNC_FIFO_OVFLW */
  6084. /* combination of all interrupt lines */
  6085. #define MRV_MIPI_ISR_ALL_IRQS
  6086. #define MRV_MIPI_ISR_ALL_IRQS_MASK \
  6087. (MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_MASK \
  6088. | MRV_MIPI_ISR_ADD_DATA_OVFLW_MASK \
  6089. | MRV_MIPI_ISR_FRAME_END_MASK \
  6090. | MRV_MIPI_ISR_ERR_CS_MASK \
  6091. | MRV_MIPI_ISR_ERR_ECC1_MASK \
  6092. | MRV_MIPI_ISR_ERR_ECC2_MASK \
  6093. | MRV_MIPI_ISR_ERR_PROTOCOL_MASK \
  6094. | MRV_MIPI_ISR_ERR_CONTROL_MASK \
  6095. | MRV_MIPI_ISR_ERR_EOT_SYNC_MASK \
  6096. | MRV_MIPI_ISR_ERR_SOT_SYNC_MASK \
  6097. | MRV_MIPI_ISR_ERR_SOT_MASK \
  6098. | MRV_MIPI_ISR_SYNC_FIFO_OVFLW_MASK \
  6099. )
  6100. #define MRV_MIPI_ISR_ALL_IRQS_SHIFT 0
  6101. /*****************************************************************************/
  6102. /**
  6103. * register: mipi_cur_data_id: Current Data Identifier (0x0000001c)
  6104. *
  6105. *****************************************************************************/
  6106. /* Slice: VIRTUAL_CHANNEL:*/
  6107. /* virtual channel of currently received packet */
  6108. #ifdef MRV_MIPI_VIRTUAL_CHANNEL
  6109. #endif /* MRV_MIPI_VIRTUAL_CHANNEL */
  6110. /* Slice: DATA_TYPE:*/
  6111. /* data type of currently received packet */
  6112. #ifdef MRV_MIPI_DATA_TYPE
  6113. #endif /* MRV_MIPI_DATA_TYPE */
  6114. /*****************************************************************************/
  6115. /**
  6116. * register: mipi_img_data_sel: Image Data Selector (0x00000020)
  6117. *
  6118. *****************************************************************************/
  6119. /* Slice: VIRTUAL_CHANNEL_SEL:*/
  6120. /* virtual channel selector for image data output */
  6121. #ifdef MRV_MIPI_VIRTUAL_CHANNEL_SEL
  6122. #endif /* MRV_MIPI_VIRTUAL_CHANNEL_SEL */
  6123. /* Slice: DATA_TYPE_SEL:*/
  6124. /* data type selector for image data output:*/
  6125. /* 0x08...0x0F: generic short packets */
  6126. /* 0x12: embedded 8-bit data */
  6127. /* 0x18: YUV 420 8-bit */
  6128. /* 0x19: YUV 420 10-bit */
  6129. /* 0x1A: Legacy YUV 420 8-bit */
  6130. /* 0x1C: YUV 420 8-bit (CSPS)*/
  6131. /* 0x1D: YUV 420 10-bit (CSPS)*/
  6132. /* 0x1E: YUV 422 8-bit */
  6133. /* 0x1F: YUV 422 10-bit */
  6134. /* 0x20: RGB 444 */
  6135. /* 0x21: RGB 555 */
  6136. /* 0x22: RGB 565 */
  6137. /* 0x23: RGB 666 */
  6138. /* 0x24: RGB 888 */
  6139. /* 0x28: RAW 6 */
  6140. /* 0x29: RAW 7 */
  6141. /* 0x2A: RAW 8 */
  6142. /* 0x2B: RAW 10 */
  6143. /* 0x2C: RAW 12 */
  6144. /* 0x30...0x37: User Defined Byte-based data */
  6145. #ifdef MRV_MIPI_DATA_TYPE_SEL
  6146. #define MRV_MIPI_DATA_TYPE_SEL_YUV420_8BIT 24 /* 0x18 YUV 420 8-bit */
  6147. #define MRV_MIPI_DATA_TYPE_SEL_YUV420_10BIT 25 /* 0x19 YUV 420 10-bit */
  6148. #define MRV_MIPI_DATA_TYPE_SEL_YUV420_8BIT_LEGACY 26 /* 0x1A Legacy YUV 420 8-bit */
  6149. #define MRV_MIPI_DATA_TYPE_SEL_YUV420_8BIT_CSPS 28 /* 0x1C YUV 420 8-bit (CSPS) */
  6150. #define MRV_MIPI_DATA_TYPE_SEL_YUV420_10BIT_CSPS 29 /* 0x1D YUV 420 10-bit (CSPS) */
  6151. #define MRV_MIPI_DATA_TYPE_SEL_YUV422_8BIT 30 /* 0x1E YUV 422 8-bit */
  6152. #define MRV_MIPI_DATA_TYPE_SEL_YUV422_10BIT 31 /* 0x1F YUV 422 10-bit */
  6153. #define MRV_MIPI_DATA_TYPE_SEL_RGB444 32 /* 0x20 RGB 444 */
  6154. #define MRV_MIPI_DATA_TYPE_SEL_RGB555 33 /* 0x21 RGB 555 */
  6155. #define MRV_MIPI_DATA_TYPE_SEL_RGB565 34 /* 0x22 RGB 565 */
  6156. #define MRV_MIPI_DATA_TYPE_SEL_RGB666 35 /* 0x23 RGB 666 */
  6157. #define MRV_MIPI_DATA_TYPE_SEL_RGB888 36 /* 0x24 RGB 888 */
  6158. #define MRV_MIPI_DATA_TYPE_SEL_RAW6 40 /* 0x28 RAW 6 */
  6159. #define MRV_MIPI_DATA_TYPE_SEL_RAW7 41 /* 0x29 RAW 7 */
  6160. #define MRV_MIPI_DATA_TYPE_SEL_RAW8 42 /* 0x2A RAW 8 */
  6161. #define MRV_MIPI_DATA_TYPE_SEL_RAW10 43 /* 0x2B RAW 10 */
  6162. #define MRV_MIPI_DATA_TYPE_SEL_RAW12 44 /* 0x2C RAW 12 */
  6163. #define MRV_MIPI_DATA_TYPE_SEL_USER1 48 /* 0x30...0x37 User Defined Byte-based data */
  6164. #define MRV_MIPI_DATA_TYPE_SEL_USER2 49 /* 0x30...0x37 User Defined Byte-based data */
  6165. #define MRV_MIPI_DATA_TYPE_SEL_USER3 50 /* 0x30...0x37 User Defined Byte-based data */
  6166. #define MRV_MIPI_DATA_TYPE_SEL_USER4 51 /* 0x30...0x37 User Defined Byte-based data */
  6167. #define MRV_MIPI_DATA_TYPE_SEL_USER5 52 /* 0x30...0x37 User Defined Byte-based data */
  6168. #define MRV_MIPI_DATA_TYPE_SEL_USER6 53 /* 0x30...0x37 User Defined Byte-based data */
  6169. #define MRV_MIPI_DATA_TYPE_SEL_USER7 54 /* 0x30...0x37 User Defined Byte-based data */
  6170. #define MRV_MIPI_DATA_TYPE_SEL_USER8 55 /* 0x30...0x37 User Defined Byte-based data */
  6171. #endif /* MRV_MIPI_DATA_TYPE_SEL */
  6172. /*****************************************************************************/
  6173. /**
  6174. * register: mipi_add_data_sel_1: Additional Data Selector 1 (0x00000024)
  6175. *
  6176. *****************************************************************************/
  6177. /* Slice: ADD_DATA_VC_1:*/
  6178. /* virtual channel selector for additional data output */
  6179. #ifdef MRV_MIPI_ADD_DATA_VC_1
  6180. #endif /* MRV_MIPI_ADD_DATA_VC_1 */
  6181. /* Slice: ADD_DATA_TYPE_1:*/
  6182. /* data type selector for additional data output */
  6183. #ifdef MRV_MIPI_ADD_DATA_TYPE_1
  6184. #endif /* MRV_MIPI_ADD_DATA_TYPE_1 */
  6185. /*****************************************************************************/
  6186. /**
  6187. * register: mipi_add_data_sel_2: Additional Data Selector 2 (0x00000028)
  6188. *
  6189. *****************************************************************************/
  6190. /* Slice: ADD_DATA_VC_2:*/
  6191. /* virtual channel selector for additional data output */
  6192. #ifdef MRV_MIPI_ADD_DATA_VC_2
  6193. #endif /* MRV_MIPI_ADD_DATA_VC_2 */
  6194. /* Slice: ADD_DATA_TYPE_2:*/
  6195. /* data type selector for additional data output */
  6196. #ifdef MRV_MIPI_ADD_DATA_TYPE_2
  6197. #endif /* MRV_MIPI_ADD_DATA_TYPE_2 */
  6198. /*****************************************************************************/
  6199. /**
  6200. * register: mipi_add_data_sel_3: Additional Data Selector 3 (0x0000002c)
  6201. *
  6202. *****************************************************************************/
  6203. /* Slice: ADD_DATA_VC_3:*/
  6204. /* virtual channel selector for additional data output */
  6205. #ifdef MRV_MIPI_ADD_DATA_VC_3
  6206. #endif /* MRV_MIPI_ADD_DATA_VC_3 */
  6207. /* Slice: ADD_DATA_TYPE_3:*/
  6208. /* data type selector for additional data output */
  6209. #ifdef MRV_MIPI_ADD_DATA_TYPE_3
  6210. #endif /* MRV_MIPI_ADD_DATA_TYPE_3 */
  6211. /*****************************************************************************/
  6212. /**
  6213. * register: mipi_add_data_sel_4: Additional Data Selector 4 (0x00000030)
  6214. *
  6215. *****************************************************************************/
  6216. /* Slice: ADD_DATA_VC_4:*/
  6217. /* virtual channel selector for additional data output */
  6218. #ifdef MRV_MIPI_ADD_DATA_VC_4
  6219. #endif /* MRV_MIPI_ADD_DATA_VC_4 */
  6220. /* Slice: ADD_DATA_TYPE_4:*/
  6221. /* data type selector for additional data output */
  6222. #ifdef MRV_MIPI_ADD_DATA_TYPE_4
  6223. #endif /* MRV_MIPI_ADD_DATA_TYPE_4 */
  6224. /*****************************************************************************/
  6225. /**
  6226. * register: mipi_add_data_fifo: Additional Data Fifo (0x00000034)
  6227. *
  6228. *****************************************************************************/
  6229. /* Slice: ADD_DATA_FIFO:*/
  6230. /* lowest 4 bytes in additional data fifo;*/
  6231. /* reading increments fifo read pointer.*/
  6232. /* First embedded data byte will be written to bits 7:0 of 32-bit data word, second data byte written to 15:8 etc.*/
  6233. #ifdef MRV_MIPI_ADD_DATA_FIFO
  6234. #endif /* MRV_MIPI_ADD_DATA_FIFO */
  6235. /*****************************************************************************/
  6236. /**
  6237. * register: mipi_add_data_fill_level: additional data fifo fill level
  6238. * (0x00000038)
  6239. *
  6240. *****************************************************************************/
  6241. /* Slice: ADD_DATA_FILL_LEVEL:*/
  6242. /* FIFO level in dwords for triggering the FILL_LEVEL interrupt,*/
  6243. /* must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/
  6244. #ifdef MRV_MIPI_ADD_DATA_FILL_LEVEL
  6245. #endif /* MRV_MIPI_ADD_DATA_FILL_LEVEL */
  6246. /*****************************************************************************/
  6247. /**
  6248. * register: mipi_compressed_mode: controls processing of compressed raw data
  6249. * types (0x0000003c)
  6250. *
  6251. *****************************************************************************/
  6252. /* Slice: predictor_sel:*/
  6253. /* predictor to be used:*/
  6254. /* 0: predictor 1 */
  6255. /* 1: predictor 2 */
  6256. #ifdef MRV_MIPI_PREDICTOR_SEL
  6257. #define MRV_MIPI_PREDICTOR_SEL_1 0 /* 0: predictor 1 */
  6258. #define MRV_MIPI_PREDICTOR_SEL_2 1 /* 1: predictor 2 */
  6259. #endif /* MRV_MIPI_PREDICTOR_SEL */
  6260. /* Slice: MRV_MIPI_COMP_SCHEME:*/
  6261. /* Compressed raw data types */
  6262. /* 000: 12-8-12 */
  6263. /* 001: 12-8-12 */
  6264. /* 010: 12-8-12 */
  6265. /* 011: 10-8-10 */
  6266. /* 100: 10-7-10 */
  6267. /* 101: 10-6-10 */
  6268. #ifdef MRV_MIPI_COMP_SCHEME
  6269. #define MRV_MIPI_COMP_SCHEME_12_8_12 0 /* 000: 12-8-12 */
  6270. #define MRV_MIPI_COMP_SCHEME_12_7_12 1 /* 001: 12-8-12 */
  6271. #define MRV_MIPI_COMP_SCHEME_12_6_12 2 /* 010: 12-8-12 */
  6272. #define MRV_MIPI_COMP_SCHEME_10_8_10 3 /* 011: 10-8-10 */
  6273. #define MRV_MIPI_COMP_SCHEME_10_7_10 4 /* 100: 10-7-10 */
  6274. #define MRV_MIPI_COMP_SCHEME_10_6_10 5 /* 101: 10-6-10 */
  6275. #endif /* MRV_MIPI_COMP_SCHEME */
  6276. /* Slice: compress_en:*/
  6277. /* 1: enable compressed mode processing */
  6278. /* 0: disable compressed mode */
  6279. #ifdef MRV_MIPI_COMPRESS_EN
  6280. #endif /* MRV_MIPI_COMPRESS_EN */
  6281. /*****************************************************************************/
  6282. /* ISP Image Stabilization Registers */
  6283. /*****************************************************************************/
  6284. /*****************************************************************************/
  6285. /**
  6286. * register: isp_is_ctrl: Image Stabilization Control Register (0x00000000)
  6287. *
  6288. *****************************************************************************/
  6289. /* Slice: is_en:*/
  6290. /* 1: image stabilization switched on */
  6291. /* 0: image stabilization switched off */
  6292. #ifdef MRV_IS_IS_EN
  6293. #define MRV_IS_IS_EN_PROCESS 1
  6294. #define MRV_IS_IS_EN_BYPASS 0
  6295. #endif /* MRV_IS_IS_EN */
  6296. /*****************************************************************************/
  6297. /**
  6298. * register: isp_is_recenter: Recenter register (0x00000004)
  6299. *
  6300. *****************************************************************************/
  6301. /* Slice: is_recenter:*/
  6302. /* 000: recenter feature switched off */
  6303. /* 1..7: recentering by (cur_h/v_offs-H/V_OFFS)/2^RECENTER */
  6304. #ifdef MRV_IS_IS_RECENTER
  6305. #define MRV_IS_IS_RECENTER_MAX (MRV_IS_IS_RECENTER_MASK >> MRV_IS_IS_RECENTER_SHIFT)
  6306. #endif /* MRV_IS_IS_RECENTER */
  6307. /*****************************************************************************/
  6308. /**
  6309. * register: isp_is_h_offs: Horizontal offset of output window (0x00000008)
  6310. *
  6311. *****************************************************************************/
  6312. /* Slice: is_h_offs:*/
  6313. /* horizontal picture offset in pixel */
  6314. #ifdef MRV_IS_IS_H_OFFS
  6315. #define MRV_IS_IS_H_OFFS_MAX (MRV_IS_IS_H_OFFS_MASK >> MRV_IS_IS_H_OFFS_SHIFT)
  6316. #endif /* MRV_IS_IS_H_OFFS */
  6317. /*****************************************************************************/
  6318. /**
  6319. * register: isp_is_v_offs: Vertical offset of output window (0x0000000c)
  6320. *
  6321. *****************************************************************************/
  6322. /* Slice: is_v_offs:*/
  6323. /* vertical picture offset in lines */
  6324. #ifdef MRV_IS_IS_V_OFFS
  6325. #define MRV_IS_IS_V_OFFS_MAX (MRV_IS_IS_V_OFFS_MASK >> MRV_IS_IS_V_OFFS_SHIFT)
  6326. #endif /* MRV_IS_IS_V_OFFS */
  6327. /*****************************************************************************/
  6328. /**
  6329. * register: isp_is_h_size: Output horizontal picture size (0x00000010)
  6330. *
  6331. *****************************************************************************/
  6332. /* Slice: is_h_size:*/
  6333. /* horizontal picture size in pixel */
  6334. /* if ISP_MODE is set to */
  6335. /* 001-(ITU-R BT.656 YUV),*/
  6336. /* 010-(ITU-R BT.601 YUV),*/
  6337. /* 011-(ITU-R BT.601 Bayer RGB),*/
  6338. /* 101-(ITU-R BT.656 Bayer RGB)*/
  6339. /* only even numbers are accepted, because complete quadruples of YUYV(YCbYCr)*/
  6340. /* are needed for the following modules. If an odd size is programmed the value */
  6341. /* will be truncated to even size.*/
  6342. #ifdef MRV_IS_IS_H_SIZE
  6343. #define MRV_IS_IS_H_SIZE_MAX (MRV_IS_IS_H_SIZE_MASK >> MRV_IS_IS_H_SIZE_SHIFT)
  6344. #endif /* MRV_IS_IS_H_SIZE */
  6345. /*****************************************************************************/
  6346. /**
  6347. * register: isp_is_v_size: Output vertical picture size (0x00000014)
  6348. *
  6349. *****************************************************************************/
  6350. /* Slice: is_v_size:*/
  6351. /* vertical picture size in lines */
  6352. #ifdef MRV_IS_IS_V_SIZE
  6353. #define MRV_IS_IS_V_SIZE_MAX (MRV_IS_IS_V_SIZE_MASK >> MRV_IS_IS_V_SIZE_SHIFT)
  6354. #endif /* MRV_IS_IS_V_SIZE */
  6355. /*****************************************************************************/
  6356. /**
  6357. * register: isp_is_max_dx: Maximum Horizontal Displacement (0x00000018)
  6358. *
  6359. *****************************************************************************/
  6360. /* Slice: is_max_dx:*/
  6361. /* maximum allowed accumulated horizontal displacement in pixels */
  6362. #ifdef MRV_IS_IS_MAX_DX
  6363. #define MRV_IS_IS_MAX_DX_MAX (MRV_IS_IS_MAX_DX_MASK >> MRV_IS_IS_MAX_DX_SHIFT)
  6364. #endif /* MRV_IS_IS_MAX_DX */
  6365. /*****************************************************************************/
  6366. /**
  6367. * register: isp_is_max_dy: Maximum Vertical Displacement (0x0000001c)
  6368. *
  6369. *****************************************************************************/
  6370. /* Slice: is_max_dy:*/
  6371. /* maximum allowed accumulated vertical displacement in lines */
  6372. #ifdef MRV_IS_IS_MAX_DY
  6373. #define MRV_IS_IS_MAX_DY_MAX (MRV_IS_IS_MAX_DY_MASK >> MRV_IS_IS_MAX_DY_SHIFT)
  6374. #endif /* MRV_IS_IS_MAX_DY */
  6375. /*****************************************************************************/
  6376. /**
  6377. * register: isp_is_displace: Camera displacement (0x00000020)
  6378. *
  6379. *****************************************************************************/
  6380. /* Slice: dy:*/
  6381. /* ISP_IS will compensate for vertical camera displacement of DY lines in the next frame */
  6382. #ifdef MRV_IS_DY
  6383. #define MRV_IS_DY_MAX 0x000007FF
  6384. #define MRV_IS_DY_MIN (~MRV_IS_DY_MAX)
  6385. #endif /* MRV_IS_DY */
  6386. /* Slice: dx:*/
  6387. /* ISP_IS will compensate for horizontal camera displacement of DX pixels in the next frame */
  6388. #ifdef MRV_IS_DX
  6389. #define MRV_IS_DX_MAX 0x000007FF
  6390. #define MRV_IS_DX_MIN (~MRV_IS_DX_MAX)
  6391. #endif /* MRV_IS_DX */
  6392. /*****************************************************************************/
  6393. /**
  6394. * register: isp_is_h_offs_shd: current horizontal offset of output window
  6395. * (shadow register) (0x00000024)
  6396. *
  6397. *****************************************************************************/
  6398. /* Slice: is_h_offs_shd:*/
  6399. /* current horizonatl picture offset in lines */
  6400. #ifdef MRV_IS_IS_H_OFFS_SHD
  6401. #endif /* MRV_IS_IS_H_OFFS_SHD */
  6402. /*****************************************************************************/
  6403. /**
  6404. * register: isp_is_v_offs_shd: current vertical offset of output window
  6405. * (shadow register) (0x00000028)
  6406. *
  6407. *****************************************************************************/
  6408. /* Slice: is_v_offs_shd:*/
  6409. /* current vertical picture offset in lines */
  6410. #ifdef MRV_IS_IS_V_OFFS_SHD
  6411. #endif /* MRV_IS_IS_V_OFFS_SHD */
  6412. /*****************************************************************************/
  6413. /**
  6414. * register: isp_is_h_size_shd: current output horizontal picture size
  6415. * (shadow register) (0x0000002c)
  6416. *
  6417. *****************************************************************************/
  6418. /* Slice: isp_h_size_shd:*/
  6419. /* current horizontal picture size in pixel */
  6420. #ifdef MRV_IS_ISP_H_SIZE_SHD
  6421. #endif /* MRV_IS_ISP_H_SIZE_SHD */
  6422. /*****************************************************************************/
  6423. /**
  6424. * register: isp_is_v_size_shd: current output vertical picture size
  6425. * (shadow register) (0x00000030)
  6426. *
  6427. *****************************************************************************/
  6428. /* Slice: isp_v_size_shd:*/
  6429. /* vertical picture size in lines */
  6430. #ifdef MRV_IS_ISP_V_SIZE_SHD
  6431. #endif /* MRV_IS_ISP_V_SIZE_SHD */
  6432. /*****************************************************************************/
  6433. /* ISP Histogram Module Registers */
  6434. /*****************************************************************************/
  6435. /*****************************************************************************/
  6436. /**
  6437. * register: isp_hist_prop: Histogram properties (0x00000000)
  6438. *
  6439. *****************************************************************************/
  6440. /* Slice: stepsize:*/
  6441. /* histogram predivider, process every (stepsize)th pixel, all other pixels are skipped */
  6442. /* 0,1,2: not allowed */
  6443. /* 3: process every third input pixel */
  6444. /* 4: process every fourth input pixel */
  6445. /* ...*/
  6446. /* 7FH: process every 127th pixel */
  6447. #ifdef MRV_HIST_STEPSIZE
  6448. #define MRV_HIST_STEPSIZE_MIN 0x00000003
  6449. #define MRV_HIST_STEPSIZE_MAX 0x0000007F
  6450. #endif /* MRV_HIST_STEPSIZE */
  6451. /* Slice: hist_mode:*/
  6452. /* histogram mode, luminance is taken at ISP output before output formatter,*/
  6453. /* RGB is taken at xtalk output */
  6454. /**/
  6455. /* 7, 6: must not be used */
  6456. /* 5: Y (luminance) histogram */
  6457. /* 4: B histogram */
  6458. /* 3: G histogram */
  6459. /* 2: R histogram */
  6460. /* 1: RGB combined histogram */
  6461. /* 0: disable, no measurements */
  6462. #ifdef MRV_HIST_MODE
  6463. #define MRV_HIST_MODE_MAX 5 /* because 6 and 7 are reserved */
  6464. #define MRV_HIST_MODE_LUM 5 /* 5: Y (luminance) histogram */
  6465. #define MRV_HIST_MODE_B 4 /* 4: B histogram */
  6466. #define MRV_HIST_MODE_G 3 /* 3: G histogram */
  6467. #define MRV_HIST_MODE_R 2 /* 2: R histogram */
  6468. #define MRV_HIST_MODE_RGB 1 /* 1: RGB combined histogram */
  6469. #define MRV_HIST_MODE_NONE 0 /* 0: disable, no measurements */
  6470. #endif /* MRV_HIST_MODE */
  6471. /*****************************************************************************/
  6472. /**
  6473. * register: isp_hist_h_offs: Histogram window horizontal offset for first
  6474. * window of 25 sub-windows (0x00000004)
  6475. *
  6476. *****************************************************************************/
  6477. /* Slice: hist_h_offset:*/
  6478. /* Horizontal offset of first window in pixels.*/
  6479. #ifdef MRV_HIST_H_OFFSET
  6480. #endif /* MRV_HIST_H_OFFSET */
  6481. /*****************************************************************************/
  6482. /**
  6483. * register: isp_hist_v_offs: Histogram window vertical offset for first
  6484. * window of 25 sub-windows (0x00000008)
  6485. *
  6486. *****************************************************************************/
  6487. /* Slice: hist_v_offset:*/
  6488. /* Vertical offset of first window in pixels.*/
  6489. #ifdef MRV_HIST_V_OFFSET
  6490. #endif /* MRV_HIST_V_OFFSET */
  6491. /*****************************************************************************/
  6492. /**
  6493. * register: isp_hist_h_size: Horizontal (sub-)window size (0x0000000c)
  6494. *
  6495. *****************************************************************************/
  6496. /* Slice: hist_h_size:*/
  6497. /* Horizontal size in pixels of one sub-window, if histogram version 3 is implemented.*/
  6498. #ifdef MRV_HIST_H_SIZE
  6499. #endif /* MRV_HIST_H_SIZE */
  6500. /*****************************************************************************/
  6501. /**
  6502. * register: isp_hist_v_size: Vertical (sub-)window size (0x00000010)
  6503. *
  6504. *****************************************************************************/
  6505. /* Slice: hist_v_size:*/
  6506. /* Vertical size in lines of one sub-window, if histogram version 3 is implemented.*/
  6507. #ifdef MRV_HIST_V_SIZE
  6508. #endif /* MRV_HIST_V_SIZE */
  6509. /*****************************************************************************/
  6510. /**
  6511. * register array: isp_hist_bin: histogram measurement result bin
  6512. * (0x028 + n*0x4 (n=0..15))
  6513. *
  6514. *****************************************************************************/
  6515. /* Slice: hist_bin_n:*/
  6516. /* measured bin count as 16-bit unsigned integer value plus 4 bit fractional part */
  6517. #ifdef MRV_HIST_BIN_N
  6518. #define MRV_HIST_BIN_N_MAX (MRV_HIST_BIN_N_MASK >> MRV_HIST_BIN_N_SHIFT)
  6519. #endif /* MRV_HIST_BIN_N */
  6520. /*****************************************************************************/
  6521. /**
  6522. * register: isp_hist_weight_00to30: Weighting factor for sub-windows
  6523. * (0x00000054)
  6524. *
  6525. *****************************************************************************/
  6526. /* Slice: hist_weight_30:*/
  6527. /* weighting factor for sub-window 30 */
  6528. #ifdef MRV_HIST_WEIGHT_30
  6529. #endif /* MRV_HIST_WEIGHT_30 */
  6530. /* Slice: hist_weight_20:*/
  6531. /* weighting factor for sub-window 20 */
  6532. #ifdef MRV_HIST_WEIGHT_20
  6533. #endif /* MRV_HIST_WEIGHT_20 */
  6534. /* Slice: hist_weight_10:*/
  6535. /* weighting factor for sub-window 10 */
  6536. #ifdef MRV_HIST_WEIGHT_10
  6537. #endif /* MRV_HIST_WEIGHT_10 */
  6538. /* Slice: hist_weight_00:*/
  6539. /* weighting factor for sub-window 00 */
  6540. #ifdef MRV_HIST_WEIGHT_00
  6541. #endif /* MRV_HIST_WEIGHT_00 */
  6542. /*****************************************************************************/
  6543. /**
  6544. * register: isp_hist_weight_40to21: Weighting factor for sub-windows
  6545. * (0x00000058)
  6546. *
  6547. *****************************************************************************/
  6548. /* Slice: hist_weight_21:*/
  6549. /* weighting factor for sub-window 21 */
  6550. #ifdef MRV_HIST_WEIGHT_21
  6551. #endif /* MRV_HIST_WEIGHT_21 */
  6552. /* Slice: hist_weight_11:*/
  6553. /* weighting factor for sub-window 11 */
  6554. #ifdef MRV_HIST_WEIGHT_11
  6555. #endif /* MRV_HIST_WEIGHT_11 */
  6556. /* Slice: hist_weight_01:*/
  6557. /* weighting factor for sub-window 01 */
  6558. #ifdef MRV_HIST_WEIGHT_01
  6559. #endif /* MRV_HIST_WEIGHT_01 */
  6560. /* Slice: hist_weight_40:*/
  6561. /* weighting factor for sub-window 40 */
  6562. #ifdef MRV_HIST_WEIGHT_40
  6563. #endif /* MRV_HIST_WEIGHT_40 */
  6564. /*****************************************************************************/
  6565. /**
  6566. * register: isp_hist_weight_31to12: Weighting factor for sub-windows
  6567. * (0x0000005c)
  6568. *
  6569. *****************************************************************************/
  6570. /* Slice: hist_weight_12:*/
  6571. /* weighting factor for sub-window 12 */
  6572. #ifdef MRV_HIST_WEIGHT_12
  6573. #endif /* MRV_HIST_WEIGHT_12 */
  6574. /* Slice: hist_weight_02:*/
  6575. /* weighting factor for sub-window 02 */
  6576. #ifdef MRV_HIST_WEIGHT_02
  6577. #endif /* MRV_HIST_WEIGHT_02 */
  6578. /* Slice: hist_weight_41:*/
  6579. /* weighting factor for sub-window 41 */
  6580. #ifdef MRV_HIST_WEIGHT_41
  6581. #endif /* MRV_HIST_WEIGHT_41 */
  6582. /* Slice: hist_weight_31:*/
  6583. /* weighting factor for sub-window 31 */
  6584. #ifdef MRV_HIST_WEIGHT_31
  6585. #endif /* MRV_HIST_WEIGHT_31 */
  6586. /*****************************************************************************/
  6587. /**
  6588. * register: isp_hist_weight_22to03: Weighting factor for sub-windows
  6589. * (0x00000060)
  6590. *
  6591. *****************************************************************************/
  6592. /* Slice: hist_weight_03:*/
  6593. /* weighting factor for sub-window 03 */
  6594. #ifdef MRV_HIST_WEIGHT_03
  6595. #endif /* MRV_HIST_WEIGHT_03 */
  6596. /* Slice: hist_weight_42:*/
  6597. /* weighting factor for sub-window 42 */
  6598. #ifdef MRV_HIST_WEIGHT_42
  6599. #endif /* MRV_HIST_WEIGHT_42 */
  6600. /* Slice: hist_weight_32:*/
  6601. /* weighting factor for sub-window 32 */
  6602. #ifdef MRV_HIST_WEIGHT_32
  6603. #endif /* MRV_HIST_WEIGHT_32 */
  6604. /* Slice: hist_weight_22:*/
  6605. /* weighting factor for sub-window 22 */
  6606. #ifdef MRV_HIST_WEIGHT_22
  6607. #endif /* MRV_HIST_WEIGHT_22 */
  6608. /*****************************************************************************/
  6609. /**
  6610. * register: isp_hist_weight_13to43: Weighting factor for sub-windows
  6611. * (0x00000064)
  6612. *
  6613. *****************************************************************************/
  6614. /* Slice: hist_weight_43:*/
  6615. /* weighting factor for sub-window 43 */
  6616. #ifdef MRV_HIST_WEIGHT_43
  6617. #endif /* MRV_HIST_WEIGHT_43 */
  6618. /* Slice: hist_weight_33:*/
  6619. /* weighting factor for sub-window 33 */
  6620. #ifdef MRV_HIST_WEIGHT_33
  6621. #endif /* MRV_HIST_WEIGHT_33 */
  6622. /* Slice: hist_weight_23:*/
  6623. /* weighting factor for sub-window 23 */
  6624. #ifdef MRV_HIST_WEIGHT_23
  6625. #endif /* MRV_HIST_WEIGHT_23 */
  6626. /* Slice: hist_weight_13:*/
  6627. /* weighting factor for sub-window 13 */
  6628. #ifdef MRV_HIST_WEIGHT_13
  6629. #endif /* MRV_HIST_WEIGHT_13 */
  6630. /*****************************************************************************/
  6631. /**
  6632. * register: isp_hist_weight_04to34: Weighting factor for sub-windows
  6633. * (0x00000068)
  6634. *
  6635. *****************************************************************************/
  6636. /* Slice: hist_weight_34:*/
  6637. /* weighting factor for sub-window 34 */
  6638. #ifdef MRV_HIST_WEIGHT_34
  6639. #endif /* MRV_HIST_WEIGHT_34 */
  6640. /* Slice: hist_weight_24:*/
  6641. /* weighting factor for sub-window 24 */
  6642. #ifdef MRV_HIST_WEIGHT_24
  6643. #endif /* MRV_HIST_WEIGHT_24 */
  6644. /* Slice: hist_weight_14:*/
  6645. /* weighting factor for sub-window 14 */
  6646. #ifdef MRV_HIST_WEIGHT_14
  6647. #endif /* MRV_HIST_WEIGHT_14 */
  6648. /* Slice: hist_weight_04:*/
  6649. /* weighting factor for sub-window 04 */
  6650. #ifdef MRV_HIST_WEIGHT_04
  6651. #endif /* MRV_HIST_WEIGHT_04 */
  6652. /*****************************************************************************/
  6653. /**
  6654. * register: isp_hist_weight_44: Weighting factor for sub-windows (0x0000006c)
  6655. *
  6656. *****************************************************************************/
  6657. /* Slice: hist_weight_44:*/
  6658. /* weighting factor for sub-window 44 */
  6659. #ifdef MRV_HIST_WEIGHT_44
  6660. #endif /* MRV_HIST_WEIGHT_44 */
  6661. #define MRV_HIST_WEIGHT_MAX 0x10
  6662. /*****************************************************************************/
  6663. /* ISP Filter Module Registers */
  6664. /*****************************************************************************/
  6665. /*****************************************************************************/
  6666. /**
  6667. * register: isp_filt_mode: mode control register for the filter block
  6668. * (0x00000000)
  6669. *
  6670. *****************************************************************************/
  6671. /* Slice: stage1_select:*/
  6672. /* Green filter stage 1 select (range 0x0...0x8)*/
  6673. /* 0x0 maximum blurring */
  6674. /* 0x4 Default */
  6675. /* 0x7 minimum blurring */
  6676. /* 0x8 filter stage1 bypass */
  6677. /* For a detailed description refer to chapter "ISP Filter Programming" of user manual */
  6678. #ifdef MRV_FILT_STAGE1_SELECT
  6679. #define MRV_FILT_STAGE1_SELECT_MAX_BLUR 0U /* 0x0 maximum blurring */
  6680. #define MRV_FILT_STAGE1_SELECT_DEFAULT 4U /* 0x4 Default */
  6681. #define MRV_FILT_STAGE1_SELECT_MIN_BLUR 7U /* 0x7 minimum blurring */
  6682. #define MRV_FILT_STAGE1_SELECT_BYPASS 8U /* 0x8 filter stage1 bypass */
  6683. #endif /* MRV_FILT_STAGE1_SELECT */
  6684. /* Slice: filt_chr_h_mode:*/
  6685. /* Chroma filter horizontal mode */
  6686. /* 00 horizontal chroma filter bypass */
  6687. /* 01 horizontal chroma filter 1 static mask = [10 12 10]*/
  6688. /* 10 horizontal chroma filter 2 (dynamic blur1)*/
  6689. /* 11 horizontal chroma filter 3 (dynamic blur2) Default */
  6690. #ifdef MRV_FILT_FILT_CHR_H_MODE
  6691. #define MRV_FILT_FILT_CHR_H_MODE_BYPASS 0U /* 00 horizontal chroma filter bypass */
  6692. #define MRV_FILT_FILT_CHR_H_MODE_STATIC 1U /* 01 horizontal chroma filter 1 static mask = [10 12 10] */
  6693. #define MRV_FILT_FILT_CHR_H_MODE_DYN_1 2U /* 10 horizontal chroma filter 2 (dynamic blur1) */
  6694. #define MRV_FILT_FILT_CHR_H_MODE_DYN_2 3U /* 11 horizontal chroma filter 3 (dynamic blur2) Default */
  6695. #endif /* MRV_FILT_FILT_CHR_H_MODE */
  6696. /* Slice: filt_chr_v_mode:*/
  6697. /* Chroma filter vertical mode */
  6698. /* 00 vertical chroma filter bypass */
  6699. /* 01 vertical chroma filter 1 static [8 16 8]*/
  6700. /* 10 vertical chroma filter 2 static [10 12 10]*/
  6701. /* 11 vertical chroma filter 3 static [12 8 12] Default */
  6702. #ifdef MRV_FILT_FILT_CHR_V_MODE
  6703. #define MRV_FILT_FILT_CHR_V_MODE_BYPASS 0U /* 00 vertical chroma filter bypass */
  6704. #define MRV_FILT_FILT_CHR_V_MODE_STATIC8 1U /* 01 vertical chroma filter 1 static [8 16 8] */
  6705. #define MRV_FILT_FILT_CHR_V_MODE_STATIC10 2U /* 10 vertical chroma filter 2 static [10 12 10] */
  6706. #define MRV_FILT_FILT_CHR_V_MODE_STATIC12 3U /* 11 vertical chroma filter 3 static [12 8 12] Default */
  6707. #endif /* MRV_FILT_FILT_CHR_V_MODE */
  6708. /* Slice: filt_mode:*/
  6709. /* 0 green filter static mode (active filter factor = FILT_FAC_MID)*/
  6710. /* 1 dynamic noise reduction/sharpen Default */
  6711. #ifdef MRV_FILT_FILT_MODE
  6712. #define MRV_FILT_FILT_MODE_STATIC 0U /* 0 green filter static mode (active filter factor = FILT_FAC_MID) */
  6713. #define MRV_FILT_FILT_MODE_DYNAMIC 1U /* 1 dynamic noise reduction/sharpen Default */
  6714. #endif /* MRV_FILT_FILT_MODE */
  6715. /* Slice: filt_enable:*/
  6716. /* 1 enable filter */
  6717. /* 0 bypass filter Default */
  6718. #ifdef MRV_FILT_FILT_ENABLE
  6719. #define MRV_FILT_FILT_ENABLE_PROCESS 1U
  6720. #define MRV_FILT_FILT_ENABLE_BYPASS 0U
  6721. #endif /* MRV_FILT_FILT_ENABLE */
  6722. /*****************************************************************************/
  6723. /**
  6724. * register: isp_filt_thresh_bl0: Blurring threshold 0 (0x00000028)
  6725. *
  6726. *****************************************************************************/
  6727. /* Slice: filt_thresh_bl0:*/
  6728. /* If filt_thresh_bl1 < sum_grad < filt_thresh_bl0 then filt_fac_bl0 is selected */
  6729. #ifdef MRV_FILT_FILT_THRESH_BL0
  6730. #endif /* MRV_FILT_FILT_THRESH_BL0 */
  6731. /*****************************************************************************/
  6732. /**
  6733. * register: isp_filt_thresh_bl1: Blurring threshold 1 (0x0000002c)
  6734. *
  6735. *****************************************************************************/
  6736. /* Slice: filt_thresh_bl1:*/
  6737. /* If sum_grad < filt_thresh_bl1 then filt_fac_bl1 is selected */
  6738. #ifdef MRV_FILT_FILT_THRESH_BL1
  6739. #endif /* MRV_FILT_FILT_THRESH_BL1 */
  6740. /*****************************************************************************/
  6741. /**
  6742. * register: isp_filt_thresh_sh0: Sharpening threshold 0 (0x00000030)
  6743. *
  6744. *****************************************************************************/
  6745. /* Slice: filt_thresh_sh0:*/
  6746. /* If filt_thresh_sh0 < sum_grad < filt_thresh_sh1 then filt_thresh_sh0 is selected */
  6747. #ifdef MRV_FILT_FILT_THRESH_SH0
  6748. #endif /* MRV_FILT_FILT_THRESH_SH0 */
  6749. /*****************************************************************************/
  6750. /**
  6751. * register: isp_filt_thresh_sh1: Sharpening threshold 1 (0x00000034)
  6752. *
  6753. *****************************************************************************/
  6754. /* Slice: filt_thresh_sh1:*/
  6755. /* If filt_thresh_sh1 < sum_grad then filt_thresh_sh1 is selected */
  6756. #ifdef MRV_FILT_FILT_THRESH_SH1
  6757. #endif /* MRV_FILT_FILT_THRESH_SH1 */
  6758. /*****************************************************************************/
  6759. /**
  6760. * register: isp_filt_lum_weight: Parameters for luminance weight function
  6761. * (0x00000038)
  6762. *
  6763. *****************************************************************************/
  6764. /* Slice: lum_weight_gain:*/
  6765. /* Gain select of luminance weight function */
  6766. #ifdef MRV_FILT_LUM_WEIGHT_GAIN
  6767. #endif /* MRV_FILT_LUM_WEIGHT_GAIN */
  6768. /* Slice: lum_weight_kink:*/
  6769. /* Kink position of luminance weight function */
  6770. #ifdef MRV_FILT_LUM_WEIGHT_KINK
  6771. #endif /* MRV_FILT_LUM_WEIGHT_KINK */
  6772. /* Slice: lum_weight_min:*/
  6773. /* Minimum value of luminance weight function */
  6774. #ifdef MRV_FILT_LUM_WEIGHT_MIN
  6775. #endif /* MRV_FILT_LUM_WEIGHT_MIN */
  6776. /*****************************************************************************/
  6777. /**
  6778. * register: isp_filt_fac_sh1: filter factor sharp1 (0x0000003c)
  6779. *
  6780. *****************************************************************************/
  6781. /* Slice: filt_fac_sh1:*/
  6782. /* Filter factor for sharp1 level */
  6783. #ifdef MRV_FILT_FILT_FAC_SH1
  6784. #endif /* MRV_FILT_FILT_FAC_SH1 */
  6785. /*****************************************************************************/
  6786. /**
  6787. * register: isp_filt_fac_sh0: filter factor sharp0 (0x00000040)
  6788. *
  6789. *****************************************************************************/
  6790. /* Slice: filt_fac_sh0:*/
  6791. /* Filter factor for sharp0 level */
  6792. #ifdef MRV_FILT_FILT_FAC_SH0
  6793. #endif /* MRV_FILT_FILT_FAC_SH0 */
  6794. /*****************************************************************************/
  6795. /**
  6796. * register: isp_filt_fac_mid: filter factor middle (0x00000044)
  6797. *
  6798. *****************************************************************************/
  6799. /* Slice: filt_fac_mid:*/
  6800. /* Filter factor for mid level and for static filter mode */
  6801. #ifdef MRV_FILT_FILT_FAC_MID
  6802. #endif /* MRV_FILT_FILT_FAC_MID */
  6803. /*****************************************************************************/
  6804. /**
  6805. * register: isp_filt_fac_bl0: Parameter for blur 0 filter (0x00000048)
  6806. *
  6807. *****************************************************************************/
  6808. /* Slice: filt_fac_bl0:*/
  6809. /* Filter factor for blur 0 level */
  6810. #ifdef MRV_FILT_FILT_FAC_BL0
  6811. #endif /* MRV_FILT_FILT_FAC_BL0 */
  6812. /*****************************************************************************/
  6813. /**
  6814. * register: isp_filt_fac_bl1: Parameter for blur 1 filter (0x0000004c)
  6815. *
  6816. *****************************************************************************/
  6817. /* Slice: filt_fac_bl1:*/
  6818. /* Filter factor for blur 1 level (max blur)*/
  6819. #ifdef MRV_FILT_FILT_FAC_BL1
  6820. #endif /* MRV_FILT_FILT_FAC_BL1 */
  6821. /*****************************************************************************/
  6822. /* ISP Auto Focus Measurement Registers */
  6823. /*****************************************************************************/
  6824. /*****************************************************************************/
  6825. /**
  6826. * register: isp_afm_ctrl: This is the control register for AF measurement
  6827. * unit (0x00000000)
  6828. *
  6829. *****************************************************************************/
  6830. /* Slice: afm_en:*/
  6831. /* AF measurement enable */
  6832. /* 0: AF measurement is disabled */
  6833. /* 1: AF measurement is enabled */
  6834. /* Writing a 1 to this register starts a new measurement and resets the afm_fin (measurement finished) interrupt to 0.*/
  6835. /* As long as the afm_en is 1, the AFM unit calculates new sharpness values for each frame.*/
  6836. #ifdef MRV_AFM_AFM_EN
  6837. #define MRV_AFM_AFM_EN_ENABLE 1 /* 1: enable AF measurment */
  6838. #define MRV_AFM_AFM_EN_DISABLE 0 /* 0: processing is deactivated, bypass mode is selected */
  6839. #endif /* MRV_AFM_AFM_EN */
  6840. /*****************************************************************************/
  6841. /**
  6842. * register: isp_afm_lt_a: Top Left corner of measure window A (0x00000004)
  6843. *
  6844. *****************************************************************************/
  6845. /* Slice: a_h_l:*/
  6846. /* first pixel of window A (horizontal left row), value must be greater or equal 5 */
  6847. #ifdef MRV_AFM_A_H_L
  6848. #define MRV_AFM_A_H_L_MIN (5U)
  6849. #define MRV_AFM_A_H_L_MAX (MRV_AFM_A_H_L_MASK >> MRV_AFM_A_H_L_SHIFT)
  6850. #endif /* MRV_AFM_A_H_L */
  6851. /* Slice: a_v_t:*/
  6852. /* first line of window A (vertical top line), value must be greater or equal 2 */
  6853. #ifdef MRV_AFM_A_V_T
  6854. #define MRV_AFM_A_V_T_MIN (2U)
  6855. #define MRV_AFM_A_V_T_MAX (MRV_AFM_A_V_T_MASK >> MRV_AFM_A_V_T_SHIFT)
  6856. #endif /* MRV_AFM_A_V_T */
  6857. /*****************************************************************************/
  6858. /**
  6859. * register: isp_afm_rb_a: Bottom right corner of measure window A (0x00000008)
  6860. *
  6861. *****************************************************************************/
  6862. /* Slice: a_h_r:*/
  6863. /* last pixel of window A (horizontal right row)*/
  6864. #ifdef MRV_AFM_A_H_R
  6865. #define MRV_AFM_A_H_R_MIN (5U)
  6866. #define MRV_AFM_A_H_R_MAX (MRV_AFM_A_H_R_MASK >> MRV_AFM_A_H_R_SHIFT)
  6867. #endif /* MRV_AFM_A_H_R */
  6868. /* Slice: a_v_b:*/
  6869. /* last line of window A (vertical bottom line), value must be lower than */
  6870. /* (number of lines -2)*/
  6871. #ifdef MRV_AFM_A_V_B
  6872. #define MRV_AFM_A_V_B_MIN (2U)
  6873. #define MRV_AFM_A_V_B_MAX (MRV_AFM_A_V_B_MASK >> MRV_AFM_A_V_B_SHIFT)
  6874. #endif /* MRV_AFM_A_V_B */
  6875. /*****************************************************************************/
  6876. /**
  6877. * register: isp_afm_lt_b: Top left corner of measure window B (0x0000000c)
  6878. *
  6879. *****************************************************************************/
  6880. /* Slice: b_h_l:*/
  6881. /* first pixel of window B (horizontal left row), value must be greater or equal 5 */
  6882. #ifdef MRV_AFM_B_H_L
  6883. #define MRV_AFM_B_H_L_MIN (5U)
  6884. #define MRV_AFM_B_H_L_MAX (MRV_AFM_B_H_L_MASK >> MRV_AFM_B_H_L_SHIFT)
  6885. #endif /* MRV_AFM_B_H_L */
  6886. /* Slice: b_v_t:*/
  6887. /* first line of window B (vertical top line), value must be greater or equal 2 */
  6888. #ifdef MRV_AFM_B_V_T
  6889. #define MRV_AFM_B_V_T_MIN (2U)
  6890. #define MRV_AFM_B_V_T_MAX (MRV_AFM_B_V_T_MASK >> MRV_AFM_B_V_T_SHIFT)
  6891. #endif /* MRV_AFM_B_V_T */
  6892. /*****************************************************************************/
  6893. /**
  6894. * register: isp_afm_rb_b: Bottom right corner of measure window B (0x00000010)
  6895. *
  6896. *****************************************************************************/
  6897. /* Slice: b_h_r:*/
  6898. /* last pixel of window B (horizontal right row)*/
  6899. #ifdef MRV_AFM_B_H_R
  6900. #define MRV_AFM_B_H_R_MIN (5U)
  6901. #define MRV_AFM_B_H_R_MAX (MRV_AFM_B_H_R_MASK >> MRV_AFM_B_H_R_SHIFT)
  6902. #endif /* MRV_AFM_B_H_R */
  6903. /* Slice: b_v_b:*/
  6904. /* last line of window B (vertical bottom line), value must be lower than */
  6905. /* (number of lines -2)*/
  6906. #ifdef MRV_AFM_B_V_B
  6907. #define MRV_AFM_B_V_B_MIN (2U)
  6908. #define MRV_AFM_B_V_B_MAX (MRV_AFM_B_V_B_MASK >> MRV_AFM_B_V_B_SHIFT)
  6909. #endif /* MRV_AFM_B_V_B */
  6910. /*****************************************************************************/
  6911. /**
  6912. * register: isp_afm_lt_c: Top left corner of measure window C (0x00000014)
  6913. *
  6914. *****************************************************************************/
  6915. /* Slice: c_h_l:*/
  6916. /* first pixel of window C (horizontal left row), value must be greater or equal 5 */
  6917. #ifdef MRV_AFM_C_H_L
  6918. #define MRV_AFM_C_H_L_MIN (5U)
  6919. #define MRV_AFM_C_H_L_MAX (MRV_AFM_C_H_L_MASK >> MRV_AFM_C_H_L_SHIFT)
  6920. #endif /* MRV_AFM_C_H_L */
  6921. /* Slice: c_v_t:*/
  6922. /* first line of window C (vertical top line), value must be greater or equal 2 */
  6923. #ifdef MRV_AFM_C_V_T
  6924. #define MRV_AFM_C_V_T_MIN (2U)
  6925. #define MRV_AFM_C_V_T_MAX (MRV_AFM_C_V_T_MASK >> MRV_AFM_C_V_T_SHIFT)
  6926. #endif /* MRV_AFM_C_V_T */
  6927. /*****************************************************************************/
  6928. /**
  6929. * register: isp_afm_rb_c: Bottom right corner of measure window C (0x00000018)
  6930. *
  6931. *****************************************************************************/
  6932. /* Slice: c_h_r:*/
  6933. /* last pixel of window C (horizontal right row)*/
  6934. #ifdef MRV_AFM_C_H_R
  6935. #define MRV_AFM_C_H_R_MIN (5U)
  6936. #define MRV_AFM_C_H_R_MAX (MRV_AFM_C_H_R_MASK >> MRV_AFM_C_H_R_SHIFT)
  6937. #endif /* MRV_AFM_C_H_R */
  6938. /* Slice: c_v_b:*/
  6939. /* last line of window C (vertical bottom line), value must be lower than */
  6940. /* (number of lines -2)*/
  6941. #ifdef MRV_AFM_C_V_B
  6942. #define MRV_AFM_C_V_B_MIN (2U)
  6943. #define MRV_AFM_C_V_B_MAX (MRV_AFM_C_V_B_MASK >> MRV_AFM_C_V_B_SHIFT)
  6944. #endif /* MRV_AFM_C_V_B */
  6945. /*****************************************************************************/
  6946. /**
  6947. * register: isp_afm_thres: Threshold register (0x0000001c)
  6948. *
  6949. *****************************************************************************/
  6950. /* Slice: afm_thres:*/
  6951. /* AF measurement threshold */
  6952. /* This register defines a threshold which can be used for minimizing the */
  6953. /* influence of noise in the measurement result.*/
  6954. #ifdef MRV_AFM_AFM_THRES
  6955. #endif /* MRV_AFM_AFM_THRES */
  6956. /*****************************************************************************/
  6957. /**
  6958. * register: isp_afm_var_shift: Variable shift register (0x00000020)
  6959. *
  6960. *****************************************************************************/
  6961. /* Slice: lum_var_shift:*/
  6962. /* variable shift for luminance summation */
  6963. /* The lum_var_shift defines the number of bits for the shift operation of the */
  6964. /* value of the current pixel before summation. The shift operation is used to */
  6965. /* avoid a luminance sum overflow.*/
  6966. #ifdef MRV_AFM_LUM_VAR_SHIFT
  6967. #endif /* MRV_AFM_LUM_VAR_SHIFT */
  6968. /* Slice: afm_var_shift:*/
  6969. /* variable shift for AF measurement */
  6970. /* The afm_var_shift defines the number of bits for the shift operation at the */
  6971. /* end of the calculation chain. The shift operation is used to avoid an AF */
  6972. /* measurement sum overflow.*/
  6973. #ifdef MRV_AFM_AFM_VAR_SHIFT
  6974. #endif /* MRV_AFM_AFM_VAR_SHIFT */
  6975. /*****************************************************************************/
  6976. /**
  6977. * register: isp_afm_sum_a: Sharpness Value Status Register of Window A (0x0024)
  6978. *
  6979. *****************************************************************************/
  6980. /* Slice: afm_sum_a:*/
  6981. /* sharpness value of window A */
  6982. #ifdef MRV_AFM_AFM_SUM_A
  6983. #endif /* MRV_AFM_AFM_SUM_A */
  6984. /*****************************************************************************/
  6985. /**
  6986. * register: isp_afm_sum_b: Sharpness Value Status Register of Window B (0x0028)
  6987. *
  6988. *****************************************************************************/
  6989. /* Slice: afm_sum_b:*/
  6990. /* sharpness value of window B */
  6991. #ifdef MRV_AFM_AFM_SUM_B
  6992. #endif /* MRV_AFM_AFM_SUM_B */
  6993. /*****************************************************************************/
  6994. /**
  6995. * register: isp_afm_sum_c: Sharpness Value Status Register of Window C (0x002c)
  6996. *
  6997. *****************************************************************************/
  6998. /* Slice: afm_sum_c:*/
  6999. /* sharpness value of window C */
  7000. #ifdef MRV_AFM_AFM_SUM_C
  7001. #endif /* MRV_AFM_AFM_SUM_C */
  7002. /*****************************************************************************/
  7003. /**
  7004. * register: isp_afm_lum_a: Luminance Value Status Register of Window A (0x0030)
  7005. *
  7006. *****************************************************************************/
  7007. /* Slice: afm_lum_a:*/
  7008. /* luminance value of window A */
  7009. #ifdef MRV_AFM_AFM_LUM_A
  7010. #endif /* MRV_AFM_AFM_LUM_A */
  7011. /*****************************************************************************/
  7012. /**
  7013. * register: isp_afm_lum_b: Luminance Value Status Register of Window B (0x0034)
  7014. *
  7015. *****************************************************************************/
  7016. /* Slice: afm_lum_b:*/
  7017. /* luminance value of window B */
  7018. #ifdef MRV_AFM_AFM_LUM_B
  7019. #endif /* MRV_AFM_AFM_LUM_B */
  7020. /*****************************************************************************/
  7021. /**
  7022. * register: isp_afm_lum_c: Luminance Value Status Register of Window C (0x0038)
  7023. *
  7024. *****************************************************************************/
  7025. /* Slice: afm_lum_c:*/
  7026. /* luminance value of window C */
  7027. #ifdef MRV_AFM_AFM_LUM_C
  7028. #endif /* MRV_AFM_AFM_LUM_C */
  7029. /*****************************************************************************/
  7030. /* ISP Lens Shade Correction Registers */
  7031. /*****************************************************************************/
  7032. /*****************************************************************************/
  7033. /**
  7034. * register: isp_lsc_ctrl: Lens shade control (0x00000000)
  7035. *
  7036. *****************************************************************************/
  7037. /* Slice: lsc_en:*/
  7038. /* 0: activation request for lens shading correction */
  7039. /* 1: deactivation reqeust for lens shading correction */
  7040. /* Activation/Deactivation is object of a shadowing mechnism. The current */
  7041. /* status is visible at ISP_LSC_STATUS::lsc_enable_status */
  7042. #ifdef MRV_LSC_LSC_EN
  7043. #define MRV_LSC_LSC_EN_ENABLE 1U
  7044. #define MRV_LSC_LSC_EN_DISABLE 0U
  7045. #endif /* MRV_LSC_LSC_EN */
  7046. /*****************************************************************************/
  7047. /**
  7048. * register: isp_lsc_r_table_addr: Table RAM Address for red component (0x00000004)
  7049. *
  7050. *****************************************************************************/
  7051. /* Slice: r_ram_addr:*/
  7052. /* table address in RAM for samples of the R color component.*/
  7053. /* Will be automatically incremented by each read or write access to the table.*/
  7054. /* Valid addresses are in the range 0 to 152 for Bank0 and 153 to 305 for Bank1 */
  7055. /* (if available).*/
  7056. #ifdef MRV_LSC_R_RAM_ADDR
  7057. #define MRV_LSC_R_RAM_ADDR_MIN_BANK0 (0x00000000U)
  7058. #define MRV_LSC_R_RAM_ADDR_MAX_BANK0 (0x00000098U)
  7059. #define MRV_LSC_R_RAM_ADDR_MIN_BANK1 (0x00000099U)
  7060. #define MRV_LSC_R_RAM_ADDR_MAX_BANK1 (0x00000132U)
  7061. #endif /* MRV_LSC_R_RAM_ADDR */
  7062. /*****************************************************************************/
  7063. /**
  7064. * register: isp_lsc_gr_table_addr: Table RAM Address for green (red) component
  7065. * (0x00000008)
  7066. *
  7067. *****************************************************************************/
  7068. /* Slice: gr_ram_addr:*/
  7069. /* table address in RAM for samples of the G_R color component.*/
  7070. /* Will be automatically incremented by each read or write access to the table.*/
  7071. /* Valid addresses are in the range 0 to 152 for Bank0 and 153 to 305 for Bank1 */
  7072. /* (if available).*/
  7073. #ifdef MRV_LSC_GR_RAM_ADDR
  7074. #define MRV_LSC_GR_RAM_ADDR_MIN_BANK0 (0x00000000U)
  7075. #define MRV_LSC_GR_RAM_ADDR_MAX_BANK0 (0x00000098U)
  7076. #define MRV_LSC_GR_RAM_ADDR_MIN_BANK1 (0x00000099U)
  7077. #define MRV_LSC_GR_RAM_ADDR_MAX_BANK1 (0x00000131U)
  7078. #endif /* MRV_LSC_GR_RAM_ADDR */
  7079. /*****************************************************************************/
  7080. /**
  7081. * register: isp_lsc_b_table_addr: Table RAM Address for blue component
  7082. * (0x0000000c)
  7083. *
  7084. *****************************************************************************/
  7085. /* Slice: b_ram_addr:*/
  7086. /* table address in RAM for samples of the B color component.*/
  7087. /* Will be automatically incremented by each read or write access to the table.*/
  7088. /* Valid addresses are in the range 0 to 152 for Bank0 and 153 to 305 for Bank1 */
  7089. /* (if available).*/
  7090. #ifdef MRV_LSC_B_RAM_ADDR
  7091. #define MRV_LSC_B_RAM_ADDR_MIN_BANK0 (0x00000000U)
  7092. #define MRV_LSC_B_RAM_ADDR_MAX_BANK0 (0x00000098U)
  7093. #define MRV_LSC_B_RAM_ADDR_MIN_BANK1 (0x00000099U)
  7094. #define MRV_LSC_B_RAM_ADDR_MAX_BANK1 (0x00000132U)
  7095. #endif /* MRV_LSC_B_RAM_ADDR */
  7096. /*****************************************************************************/
  7097. /**
  7098. * register: isp_lsc_gb_table_addr: Table RAM Address for green (blue) component
  7099. * (0x00000010)
  7100. *
  7101. *****************************************************************************/
  7102. /* Slice: gb_ram_addr:*/
  7103. /* table address in RAM for samples of the G_B color component.*/
  7104. /* Will be automatically incremented by each read or write access to the table.*/
  7105. /* Valid addresses are in the range 0 to 152 for Bank0 and 153 to 305 for Bank1 */
  7106. /* (if available).*/
  7107. #ifdef MRV_LSC_GB_RAM_ADDR
  7108. #define MRV_LSC_GB_RAM_ADDR_MIN_BANK0 (0x00000000U)
  7109. #define MRV_LSC_GB_RAM_ADDR_MAX_BANK0 (0x00000098U)
  7110. #define MRV_LSC_GB_RAM_ADDR_MIN_BANK1 (0x00000099U)
  7111. #define MRV_LSC_GB_RAM_ADDR_MAX_BANK1 (0x00000132U)
  7112. #endif /* MRV_LSC_GB_RAM_ADDR */
  7113. /*****************************************************************************/
  7114. /**
  7115. * register: isp_lsc_r_table_data: Sample table red (0x00000014)
  7116. *
  7117. *****************************************************************************/
  7118. /* Slice: r_sample_1:*/
  7119. /* correction factor at sample point (fixed point number: 2 bits integer with */
  7120. /* 10-bit fractional part, range 1..3.999)*/
  7121. #ifdef MRV_LSC_R_SAMPLE_1
  7122. #endif /* MRV_LSC_R_SAMPLE_1 */
  7123. /* Slice: r_sample_0:*/
  7124. /* correction factor at sample point (fixed point number: 2 bits integer with */
  7125. /* 10-bit fractional part, range 1..3.999)*/
  7126. #ifdef MRV_LSC_R_SAMPLE_0
  7127. #endif /* MRV_LSC_R_SAMPLE_0 */
  7128. /*****************************************************************************/
  7129. /**
  7130. * register: isp_lsc_gr_table_data: Sample table green (red) (0x00000018)
  7131. *
  7132. *****************************************************************************/
  7133. /* Slice: gr_sample_1:*/
  7134. /* correction factor at sample point (fixed point number: 2 bits integer with */
  7135. /* 10-bit fractional part, range 1..3.999)*/
  7136. #ifdef MRV_LSC_GR_SAMPLE_1
  7137. #endif /* MRV_LSC_GR_SAMPLE_1 */
  7138. /* Slice: gr_sample_0:*/
  7139. /* correction factor at sample point (fixed point number: 2 bits integer with */
  7140. /* 10-bit fractional part, range 1..3.999)*/
  7141. #ifdef MRV_LSC_GR_SAMPLE_0
  7142. #endif /* MRV_LSC_GR_SAMPLE_0 */
  7143. /*****************************************************************************/
  7144. /**
  7145. * register: Register: isp_lsc_b_table_data: Sample table blue (0x0000001c)
  7146. *
  7147. *****************************************************************************/
  7148. /* Slice: b_sample_1:*/
  7149. /* correction factor at sample point (fixed point number: 2 bits integer with */
  7150. /* 10-bit fractional part, range 1..3.999)*/
  7151. #ifdef MRV_LSC_B_SAMPLE_1
  7152. #endif /* MRV_LSC_B_SAMPLE_1 */
  7153. /* Slice: b_sample_0:*/
  7154. /* correction factor at sample point (fixed point number: 2 bits integer with */
  7155. /* 10-bit fractional part, range 1..3.999)*/
  7156. #ifdef MRV_LSC_B_SAMPLE_0
  7157. #endif /* MRV_LSC_B_SAMPLE_0 */
  7158. /*****************************************************************************/
  7159. /**
  7160. * register: isp_lsc_gb_table_data: Sample table green (blue) (0x00000020)
  7161. *
  7162. *****************************************************************************/
  7163. /* Slice: gb_sample_1:*/
  7164. /* correction factor at sample point (fixed point number: 2 bits integer with */
  7165. /* 10-bit fractional part, range 1..3.999)*/
  7166. #ifdef MRV_LSC_GB_SAMPLE_1
  7167. #endif /* MRV_LSC_GB_SAMPLE_1 */
  7168. /* Slice: gb_sample_0:*/
  7169. /* correction factor at sample point (fixed point number: 2 bits integer with */
  7170. /* 10-bit fractional part, range 1..3.999)*/
  7171. #ifdef MRV_LSC_GB_SAMPLE_0
  7172. #endif /* MRV_LSC_GB_SAMPLE_0 */
  7173. /*****************************************************************************/
  7174. /**
  7175. * register: isp_lsc_xgrad_01: Gradient table x (0x00000024)
  7176. *
  7177. *****************************************************************************/
  7178. /* Slice: xgrad_1:*/
  7179. /* factor for x-gradient calculation of sector 1 */
  7180. #ifdef MRV_LSC_XGRAD_1
  7181. #endif /* MRV_LSC_XGRAD_1 */
  7182. /* Slice: xgrad_0:*/
  7183. /* factor for x-gradient calculation of sector 0 */
  7184. #ifdef MRV_LSC_XGRAD_0
  7185. #endif /* MRV_LSC_XGRAD_0 */
  7186. /*****************************************************************************/
  7187. /**
  7188. * register: isp_lsc_xgrad_23: Gradient table x (0x00000028)
  7189. *
  7190. *****************************************************************************/
  7191. /* Slice: xgrad_3:*/
  7192. /* factor for x-gradient calculation of sector 3 */
  7193. #ifdef MRV_LSC_XGRAD_3
  7194. #endif /* MRV_LSC_XGRAD_3 */
  7195. /* Slice: xgrad_2:*/
  7196. /* factor for x-gradient calculation of sector 2 */
  7197. #ifdef MRV_LSC_XGRAD_2
  7198. #endif /* MRV_LSC_XGRAD_2 */
  7199. /*****************************************************************************/
  7200. /**
  7201. * register: isp_lsc_xgrad_45: Gradient table x (0x0000002c)
  7202. *
  7203. *****************************************************************************/
  7204. /* Slice: xgrad_5:*/
  7205. /* factor for x-gradient calculation of sector 5 */
  7206. #ifdef MRV_LSC_XGRAD_5
  7207. #endif /* MRV_LSC_XGRAD_5 */
  7208. /* Slice: xgrad_4:*/
  7209. /* factor for x-gradient calculation of sector 4 */
  7210. #ifdef MRV_LSC_XGRAD_4
  7211. #endif /* MRV_LSC_XGRAD_4 */
  7212. /*****************************************************************************/
  7213. /**
  7214. * register: isp_lsc_xgrad_67: Gradient table x (0x00000030)
  7215. *
  7216. *****************************************************************************/
  7217. /* Slice: xgrad_7:*/
  7218. /* factor for x-gradient calculation of sector 7 */
  7219. #ifdef MRV_LSC_XGRAD_7
  7220. #endif /* MRV_LSC_XGRAD_7 */
  7221. /* Slice: xgrad_6:*/
  7222. /* factor for x-gradient calculation of sector 6 */
  7223. #ifdef MRV_LSC_XGRAD_6
  7224. #endif /* MRV_LSC_XGRAD_6 */
  7225. /*****************************************************************************/
  7226. /**
  7227. * register: isp_lsc_ygrad_01: Gradient table y (0x00000034)
  7228. *
  7229. *****************************************************************************/
  7230. /* Slice: ygrad_1:*/
  7231. /* factor for y-gradient calculation of sector 1 */
  7232. #ifdef MRV_LSC_YGRAD_1
  7233. #endif /* MRV_LSC_YGRAD_1 */
  7234. /* Slice: ygrad_0:*/
  7235. /* factor for y-gradient calculation of sector 0 */
  7236. #ifdef MRV_LSC_YGRAD_0
  7237. #endif /* MRV_LSC_YGRAD_0 */
  7238. /*****************************************************************************/
  7239. /**
  7240. * register: isp_lsc_ygrad_23: Gradient table y (0x00000038)
  7241. *
  7242. *****************************************************************************/
  7243. /* Slice: ygrad_3:*/
  7244. /* factor for y-gradient calculation of sector 3 */
  7245. #ifdef MRV_LSC_YGRAD_3
  7246. #endif /* MRV_LSC_YGRAD_3 */
  7247. /* Slice: ygrad_2:*/
  7248. /* factor for y-gradient calculation of sector 2 */
  7249. #ifdef MRV_LSC_YGRAD_2
  7250. #endif /* MRV_LSC_YGRAD_2 */
  7251. /*****************************************************************************/
  7252. /**
  7253. * register: isp_lsc_ygrad_45: Gradient table y (0x0000003c)
  7254. *
  7255. *****************************************************************************/
  7256. /* Slice: ygrad_5:*/
  7257. /* factor for y-gradient calculation of sector 5 */
  7258. #ifdef MRV_LSC_YGRAD_5
  7259. #endif /* MRV_LSC_YGRAD_5 */
  7260. /* Slice: ygrad_4:*/
  7261. /* factor for y-gradient calculation of sector 4 */
  7262. #ifdef MRV_LSC_YGRAD_4
  7263. #endif /* MRV_LSC_YGRAD_4 */
  7264. /*****************************************************************************/
  7265. /**
  7266. * register: isp_lsc_ygrad_67: Gradient table y (0x00000040)
  7267. *
  7268. *****************************************************************************/
  7269. /* Slice: ygrad_7:*/
  7270. /* factor for y-gradient calculation of sector 7 */
  7271. #ifdef MRV_LSC_YGRAD_7
  7272. #endif /* MRV_LSC_YGRAD_7 */
  7273. /* Slice: ygrad_6:*/
  7274. /* factor for y-gradient calculation of sector 6 */
  7275. #ifdef MRV_LSC_YGRAD_6
  7276. #endif /* MRV_LSC_YGRAD_6 */
  7277. /*****************************************************************************/
  7278. /**
  7279. * register: isp_lsc_xsize_01: Size table (0x00000044)
  7280. *
  7281. *****************************************************************************/
  7282. /* Slice: x_sect_size_1:*/
  7283. /* sector size 1 in x-direction */
  7284. #ifdef MRV_LSC_X_SECT_SIZE_1
  7285. #endif /* MRV_LSC_X_SECT_SIZE_1 */
  7286. /* Slice: x_sect_size_0:*/
  7287. /* sector size 0 in x-direction */
  7288. #ifdef MRV_LSC_X_SECT_SIZE_0
  7289. #endif /* MRV_LSC_X_SECT_SIZE_0 */
  7290. /*****************************************************************************/
  7291. /**
  7292. * register: isp_lsc_xsize_23: Size table (0x00000048)
  7293. *
  7294. *****************************************************************************/
  7295. /* Slice: x_sect_size_3:*/
  7296. /* sector size 3 in x-direction */
  7297. #ifdef MRV_LSC_X_SECT_SIZE_3
  7298. #endif /* MRV_LSC_X_SECT_SIZE_3 */
  7299. /* Slice: x_sect_size_2:*/
  7300. /* sector size 2 in x-direction */
  7301. #ifdef MRV_LSC_X_SECT_SIZE_2
  7302. #endif /* MRV_LSC_X_SECT_SIZE_2 */
  7303. /*****************************************************************************/
  7304. /**
  7305. * register: isp_lsc_xsize_45: Size table (0x0000004c)
  7306. *
  7307. *****************************************************************************/
  7308. /* Slice: x_sect_size_5:*/
  7309. /* sector size 5 in x-direction */
  7310. #ifdef MRV_LSC_X_SECT_SIZE_5
  7311. #endif /* MRV_LSC_X_SECT_SIZE_5 */
  7312. /* Slice: x_sect_size_4:*/
  7313. /* sector size 4in x-direction */
  7314. #ifdef MRV_LSC_X_SECT_SIZE_4
  7315. #endif /* MRV_LSC_X_SECT_SIZE_4 */
  7316. /*****************************************************************************/
  7317. /**
  7318. * register: isp_lsc_xsize_67: Size table (0x00000050)
  7319. *
  7320. *****************************************************************************/
  7321. /* Slice: x_sect_size_7:*/
  7322. /* sector size 7 in x-direction */
  7323. #ifdef MRV_LSC_X_SECT_SIZE_7
  7324. #endif /* MRV_LSC_X_SECT_SIZE_7 */
  7325. /* Slice: x_sect_size_6:*/
  7326. /* sector size 6 in x-direction */
  7327. #ifdef MRV_LSC_X_SECT_SIZE_6
  7328. #endif /* MRV_LSC_X_SECT_SIZE_6 */
  7329. /*****************************************************************************/
  7330. /**
  7331. * register: isp_lsc_ysize_01: Size table (0x00000054)
  7332. *
  7333. *****************************************************************************/
  7334. /* Slice: y_sect_size_1:*/
  7335. /* sector size 1 in y-direction */
  7336. #ifdef MRV_LSC_Y_SECT_SIZE_1
  7337. #endif /* MRV_LSC_Y_SECT_SIZE_1 */
  7338. /* Slice: y_sect_size_0:*/
  7339. /* sector size 0 in y-direction */
  7340. #ifdef MRV_LSC_Y_SECT_SIZE_0
  7341. #endif /* MRV_LSC_Y_SECT_SIZE_0 */
  7342. /*****************************************************************************/
  7343. /**
  7344. * register: isp_lsc_ysize_23: Size table (0x00000058)
  7345. *
  7346. *****************************************************************************/
  7347. /* Slice: y_sect_size_3:*/
  7348. /* sector size 3 in y-direction */
  7349. #ifdef MRV_LSC_Y_SECT_SIZE_3
  7350. #endif /* MRV_LSC_Y_SECT_SIZE_3 */
  7351. /* Slice: y_sect_size_2:*/
  7352. /* sector size 2 in y-direction */
  7353. #ifdef MRV_LSC_Y_SECT_SIZE_2
  7354. #endif /* MRV_LSC_Y_SECT_SIZE_2 */
  7355. /*****************************************************************************/
  7356. /**
  7357. * register: isp_lsc_ysize_45: Size table (0x0000005c)
  7358. *
  7359. *****************************************************************************/
  7360. /* Slice: y_sect_size_5:*/
  7361. /* sector size 5 in y-direction */
  7362. #ifdef MRV_LSC_Y_SECT_SIZE_5
  7363. #endif /* MRV_LSC_Y_SECT_SIZE_5 */
  7364. /* Slice: y_sect_size_4:*/
  7365. /* sector size 4 in y-direction */
  7366. #ifdef MRV_LSC_Y_SECT_SIZE_4
  7367. #endif /* MRV_LSC_Y_SECT_SIZE_4 */
  7368. /*****************************************************************************/
  7369. /**
  7370. * register: isp_lsc_ysize_67: Size table (0x00000060)
  7371. *
  7372. *****************************************************************************/
  7373. /* Slice: y_sect_size_7:*/
  7374. /* sector size 7 in y-direction */
  7375. #ifdef MRV_LSC_Y_SECT_SIZE_7
  7376. #endif /* MRV_LSC_Y_SECT_SIZE_7 */
  7377. /* Slice: y_sect_size_6:*/
  7378. /* sector size 6 in y-direction */
  7379. #ifdef MRV_LSC_Y_SECT_SIZE_6
  7380. #endif /* MRV_LSC_Y_SECT_SIZE_6 */
  7381. /*****************************************************************************/
  7382. /**
  7383. * register: isp_lsc_table_sel: Lens shade table set selection (0x00000064)
  7384. *
  7385. *****************************************************************************/
  7386. /* Slice: table_sel:*/
  7387. /* 0: next active tables set is table set 0.*/
  7388. /* 1: next active tables set is table set 1.*/
  7389. /* Table selection is object of a shadowing mechnism. The current status is */
  7390. /* visible at ISP_LSC_STATUS::active_table.*/
  7391. #ifdef MRV_LSC_TABLE_SEL
  7392. #define MRV_LSC_TABLE_SEL_BANK0 (0U)
  7393. #define MRV_LSC_TABLE_SEL_BANK1 (1U)
  7394. #endif /* MRV_LSC_TABLE_SEL */
  7395. /*****************************************************************************/
  7396. /**
  7397. * register: isp_lsc_status: Lens shade status (0x00000068)
  7398. *
  7399. *****************************************************************************/
  7400. /* Slice: active_table:*/
  7401. /* 0: currently active tables set is table set 0 */
  7402. /* 1: currently active tables set is table set 1 */
  7403. #ifdef MRV_LSC_ACTIVE_TABLE
  7404. #define MRV_LSC_ACTIVE_TABLE_BANK0 (0U)
  7405. #define MRV_LSC_ACTIVE_TABLE_BANK1 (1U)
  7406. #endif /* MRV_LSC_ACTIVE_TABLE */
  7407. /* Slice: lsc_en_status:*/
  7408. /* 0: lens shading correction is currently off */
  7409. /* 1: lens shading correction is currently on */
  7410. #ifdef MRV_LSC_LSC_EN_STATUS
  7411. #endif /* MRV_LSC_LSC_EN_STATUS */
  7412. /*****************************************************************************/
  7413. /* ISP Chromatic Aberration Correction Registers */
  7414. /*****************************************************************************/
  7415. /*****************************************************************************/
  7416. /**
  7417. * register: isp_cac_ctrl: Control register for chromatic aberration
  7418. * correction (0x00000000)
  7419. *
  7420. *****************************************************************************/
  7421. /* Slice: h_clip_mode:*/
  7422. /* Defines the maximum red/blue pixel shift in horizontal direction at pixel */
  7423. /* positions, that require a larger displacement, the maximum shift value is */
  7424. /* used instead (vector clipping)*/
  7425. /**/
  7426. /* 0: Set horizontal vector clipping to +/-4 pixel displacement (Default)*/
  7427. /* 1: Set horizontal vector clipping to +/-4 or +/-5 pixel displacement */
  7428. /* depending on pixel position inside the Bayer raster (dynamic switching */
  7429. /* between +/-4 and +/-5)*/
  7430. #ifdef MRV_CAC_H_CLIP_MODE
  7431. #define MRV_CAC_H_CLIP_MODE_FIX4 0 /* 0: Set horizontal vector clipping */
  7432. /* to +/-4 pixel displacement (Default) */
  7433. #define MRV_CAC_H_CLIP_MODE_DYN5 1 /* 1: Set horizontal vector clipping */
  7434. /* to +/-4 or +/-5 pixel displacement depending on */
  7435. /* pixel position inside the Bayer raster */
  7436. /* (dynamic switching between +/-4 and +/-5) */
  7437. #endif /* MRV_CAC_H_CLIP_MODE */
  7438. /* Slice: v_clip_mode:*/
  7439. /* Defines the maximum red/blue pixel shift in vertical direction */
  7440. /* 00: Set vertical vector clipping to +/-2 pixel ; fix filter_enable (Default)*/
  7441. /* 01: Set vertical vector clipping to +/-3 pixel; dynamic filter_enable for */
  7442. /* chroma low pass filter */
  7443. /* 10: Set vertical vector clipping +/-3 or +/-4 pixel displacement depending */
  7444. /* on pixel position inside the Bayer raster (dynamic switching between +/-3 and +/-4)*/
  7445. /* 11: reserved */
  7446. #ifdef MRV_CAC_V_CLIP_MODE
  7447. #define MRV_CAC_V_CLIP_MODE_FIX2 0 /* 00: Set vertical vector clipping to +/-2 pixel; */
  7448. /* fix filter_enable (Default) */
  7449. #define MRV_CAC_V_CLIP_MODE_FIX3 1 /* 01: Set vertical vector clipping to +/-3 pixel; */
  7450. /* dynamic filter_enable for chroma low pass filter */
  7451. #define MRV_CAC_V_CLIP_MODE_DYN4 2 /* 10: Set vertical vector clipping +/-3 or +/-4 pixel */
  7452. /* displacement depending on pixel position inside */
  7453. /* the Bayer raster (dynamic switching between +/-3 and +/-4) */
  7454. #endif /* MRV_CAC_V_CLIP_MODE */
  7455. /* Slice: cac_en:*/
  7456. /* 0: chromatic aberration correction off */
  7457. /* 1: chromatic aberration correction on */
  7458. #ifdef MRV_CAC_CAC_EN
  7459. #define MRV_CAC_CAC_EN_PROCESS 1
  7460. #define MRV_CAC_CAC_EN_BYPASS 0
  7461. #endif /* MRV_CAC_CAC_EN */
  7462. /*****************************************************************************/
  7463. /**
  7464. * register: isp_cac_count_start: Preload values for CAC pixel and line
  7465. * counter (0x00000004)
  7466. *
  7467. *****************************************************************************/
  7468. /* Slice: v_count_start:*/
  7469. /* 12 bit v_count preload value (range 4095 ... 1) of the vertical CAC line */
  7470. /* counter. Before frame start v_count has to be preloaded with */
  7471. /* (v_size/2 + v_center_offset), with v_size the image height and v_center_offset */
  7472. /* the vertical distance between image center and optical center.*/
  7473. /**/
  7474. /* After frame start the v_count decrements with every line until a value of zero */
  7475. /* is reached for the line in the optical center. Than the v_sign bit toggles and */
  7476. /* the v_counter decrements with every line until end of frame.*/
  7477. #ifdef MRV_CAC_V_COUNT_START
  7478. #define MRV_CAC_V_COUNT_START_MIN 1
  7479. #define MRV_CAC_V_COUNT_START_MAX (MRV_CAC_V_COUNT_START_MASK >> MRV_CAC_V_COUNT_START_SHIFT)
  7480. #endif /* MRV_CAC_V_COUNT_START */
  7481. /* Slice: h_count_start:*/
  7482. /* 12 bit h_count preload value (range 4095 .. 1) of the horizontal CAC pixel */
  7483. /* counter. Before line start h_count has to be preloaded with (h_size/2 + h_center_offset),*/
  7484. /* with h_size the image width and h_center_offset the horizontal distance between image */
  7485. /* center and optical center.*/
  7486. /**/
  7487. /* After line start the h_count decrements with every pixel until a value of zero is */
  7488. /* reached for the column in the optical center. Than the h_sign bit toggles and the */
  7489. /* h_counter increments with every pixel until end of line.*/
  7490. #ifdef MRV_CAC_H_COUNT_START
  7491. #define MRV_CAC_H_COUNT_START_MIN 1
  7492. #define MRV_CAC_H_COUNT_START_MAX (MRV_CAC_H_COUNT_START_MASK >> MRV_CAC_H_COUNT_START_SHIFT)
  7493. #endif /* MRV_CAC_H_COUNT_START */
  7494. /*****************************************************************************/
  7495. /**
  7496. * register: isp_cac_a: Linear Parameters for radial shift calculation (0x00000008)
  7497. *
  7498. *****************************************************************************/
  7499. /* Slice: A_Blue:*/
  7500. /* Parameter A_Blue for radial blue shift calculation, according to */
  7501. /* (A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/
  7502. /* It is a 9 bit twos complement integer with 4 fractional digits value and */
  7503. /* value range from -16 up to 15.9375.*/
  7504. #ifdef MRV_CAC_A_BLUE
  7505. #define MRV_CAC_A_BLUE_MAX (MRV_CAC_A_BLUE_MASK >> (MRV_CAC_A_BLUE_SHIFT))
  7506. #define MRV_CAC_A_BLUE_MIN 0
  7507. #endif /* MRV_CAC_A_BLUE */
  7508. /* Slice: A_Red:*/
  7509. /* Parameter A_Red for radial red shift calculation, according to */
  7510. /* (A_Red * r + B_Red * r^2 + C_Red * r^3).*/
  7511. /* It is a 9 bit twos complement integer with 4 fractional digits value and */
  7512. /* value range from -16 up to 15.9375.*/
  7513. #ifdef MRV_CAC_A_RED
  7514. #define MRV_CAC_A_RED_MAX (MRV_CAC_A_RED_MASK >> (MRV_CAC_A_RED_SHIFT))
  7515. #define MRV_CAC_A_RED_MIN 0
  7516. #endif /* MRV_CAC_A_RED */
  7517. /*****************************************************************************/
  7518. /**
  7519. * register: isp_cac_b: Square Parameters for radial shift calculation (0x0000000c)
  7520. *
  7521. *****************************************************************************/
  7522. /* Slice: B_Blue:*/
  7523. /* Parameter B_Blue for radial blue shift calculation, according to */
  7524. /* (A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/
  7525. /* It is a 9 bit twos complement integer with 4 fractional digits value and */
  7526. /* value range from -16 up to 15.9375.*/
  7527. #ifdef MRV_CAC_B_BLUE
  7528. #define MRV_CAC_B_BLUE_MAX (MRV_CAC_B_BLUE_MASK >> (MRV_CAC_B_BLUE_SHIFT))
  7529. #define MRV_CAC_B_BLUE_MIN 0
  7530. #endif /* MRV_CAC_B_BLUE */
  7531. /* Slice: B_Red:*/
  7532. /* Parameter B_Red for radial red shift calculation, according to */
  7533. /* (A_Red * r + B_Red * r^2 + C_Red * r^3).*/
  7534. /* It is a 9 bit twos complement integer with 4 fractional digits value and */
  7535. /* value range from -16 up to 15.9375.*/
  7536. #ifdef MRV_CAC_B_RED
  7537. #define MRV_CAC_B_RED_MAX (MRV_CAC_B_RED_MASK >> (MRV_CAC_B_RED_SHIFT))
  7538. #define MRV_CAC_B_RED_MIN 0
  7539. #endif /* MRV_CAC_B_RED */
  7540. /*****************************************************************************/
  7541. /**
  7542. * register: isp_cac_c: Cubical Parameters for radial shift calculation (0x00000010)
  7543. *
  7544. *****************************************************************************/
  7545. /* Slice: C_Blue:*/
  7546. /* Parameter C_Blue for radial blue shift calculation, according to */
  7547. /* (A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/
  7548. /* It is a 9 bit twos complement integer with 4 fractional digits value and */
  7549. /* value range from -16 up to 15.9375.*/
  7550. #ifdef MRV_CAC_C_BLUE
  7551. #define MRV_CAC_C_BLUE_MAX (MRV_CAC_C_BLUE_MASK >> (MRV_CAC_C_BLUE_SHIFT))
  7552. #define MRV_CAC_C_BLUE_MIN 0
  7553. #endif /* MRV_CAC_C_BLUE */
  7554. /* Slice: C_Red:*/
  7555. /* Parameter C_Red for radial red shift calculation, according to */
  7556. /* (A_Red * r + B_Red * r^2 + C_Red * r^3).*/
  7557. /* It is a 9 bit twos complement integer with 4 fractional digits value and */
  7558. /* value range from -16 up to 15.9375.*/
  7559. #ifdef MRV_CAC_C_RED
  7560. #define MRV_CAC_C_RED_MAX (MRV_CAC_C_RED_MASK >> (MRV_CAC_C_RED_SHIFT))
  7561. #define MRV_CAC_C_RED_MIN 0
  7562. #endif /* MRV_CAC_C_RED */
  7563. /*****************************************************************************/
  7564. /**
  7565. * register: isp_cac_x_norm: Normalization parameters for calculation of image
  7566. * coordinate x_d relative to optical center (0x00000014)
  7567. *
  7568. *****************************************************************************/
  7569. /* Slice: x_ns:*/
  7570. /* Horizontal normalization shift parameter x_ns (4 bit unsigned integer)*/
  7571. /* in equation x_d[7:0] = (((h_count <% 4) %> x_ns) * x_nf) >> 5 */
  7572. #ifdef MRV_CAC_X_NS
  7573. #define MRV_CAC_X_NS_MIN 0
  7574. #define MRV_CAC_X_NS_MAX (MRV_CAC_X_NS_MASK >> MRV_CAC_X_NS_SHIFT)
  7575. #endif /* MRV_CAC_X_NS */
  7576. /* Slice: x_nf:*/
  7577. /* Horizontal scaling or normalization factor x_nf (5 bit unsigned integer)*/
  7578. /* range 0 .. 31 in equation x_d[7:0] = (((h_count <% 4) %> x_ns) * x_nf) >> 5 */
  7579. #ifdef MRV_CAC_X_NF
  7580. #define MRV_CAC_X_NF_MIN 0
  7581. #define MRV_CAC_X_NF_MAX 31
  7582. #endif /* MRV_CAC_X_NF */
  7583. /*****************************************************************************/
  7584. /**
  7585. * register: isp_cac_y_norm: Normalization parameters for calculation of image
  7586. * coordinate y_d relative to optical center (0x00000018)
  7587. *
  7588. *****************************************************************************/
  7589. /* Slice: y_ns:*/
  7590. /* Vertical normalization shift parameter y_ns (4 bit unsigned integer)*/
  7591. /* in equation y_d[7:0] = (((v_count <% 4) %> y_ns) * y_nf) >> 5 */
  7592. #ifdef MRV_CAC_Y_NS
  7593. #define MRV_CAC_Y_NS_MIN 0
  7594. #define MRV_CAC_Y_NS_MAX (MRV_CAC_Y_NS_MASK >> MRV_CAC_Y_NS_SHIFT)
  7595. #endif /* MRV_CAC_Y_NS */
  7596. /* Slice: y_nf:*/
  7597. /* Vertical scaling or normalization factor y_nf (5 bit unsigned integer)*/
  7598. /* range 0 .. 31 in equation y_d[7:0] = (((v_count <% 4) %> y_ns) * y_nf) >> 5 */
  7599. #ifdef MRV_CAC_Y_NF
  7600. #define MRV_CAC_Y_NF_MIN 0
  7601. #define MRV_CAC_Y_NF_MAX 31
  7602. #endif /* MRV_CAC_Y_NF */
  7603. /*****************************************************************************/
  7604. /* ISP Exposure Measurement Registers */
  7605. /*****************************************************************************/
  7606. /*****************************************************************************/
  7607. /**
  7608. * register: isp_exp_ctrl: Exposure control (0x00000000)
  7609. *
  7610. *****************************************************************************/
  7611. /* Slice: exp_meas_mode:*/
  7612. /* '1' luminance calculation according to Y=(R+G+B) x 0.332 (85/256)*/
  7613. /* '0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B */
  7614. #ifdef MRV_AE_EXP_MEAS_MODE
  7615. #define MRV_AE_EXP_MEAS_MODE_1 1 /* '1' luminance calculation according to Y=(R+G+B) x 0.332 (85/256) */
  7616. #define MRV_AE_EXP_MEAS_MODE_0 0 /* '0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B */
  7617. #endif /* MRV_AE_EXP_MEAS_MODE */
  7618. /* Slice: autostop:*/
  7619. /* '1' stop measuring after a complete frame */
  7620. /* '0' continous measurement */
  7621. #ifdef MRV_AE_AUTOSTOP
  7622. #define MRV_AE_AUTOSTOP_STOP_MEASURING 1 /* stop measuring after a complete frame */
  7623. #define MRV_AE_AUTOSTOP_CONTINOUS_MEASURING 0 /* don't stop measurement, continoue with next frame */
  7624. #endif /* MRV_AE_AUTOSTOP */
  7625. /* Slice: exp_start:*/
  7626. /* '1' start measuring a frame. The exp block will reset this bit and halt */
  7627. /* after completing one frame, if bit "autostop" is set to '1'.*/
  7628. #ifdef MRV_AE_EXP_START
  7629. #define MRV_AE_EXP_START_PROCESS 1 /* 1: processing is activated */
  7630. #define MRV_AE_EXP_START_BYPASS 0 /* 0: processing is deactivated, bypass mode is selected */
  7631. #endif /* MRV_AE_EXP_START */
  7632. /*****************************************************************************/
  7633. /**
  7634. * register: isp_exp_h_offset: Horizontal offset for first block (0x00000004)
  7635. *
  7636. *****************************************************************************/
  7637. /* Slice: isp_exp_h_offset:*/
  7638. /* Horizontal offset of first block in pixels.*/
  7639. /* 0 <= value <= 3920 */
  7640. #ifdef MRV_AE_ISP_EXP_H_OFFSET
  7641. #define MRV_AE_ISP_EXP_H_OFFSET_MIN 0x00000000
  7642. #define MRV_AE_ISP_EXP_H_OFFSET_MAX 0x00000F50 /* 4096-176 */
  7643. #endif /* MRV_AE_ISP_EXP_H_OFFSET */
  7644. /*****************************************************************************/
  7645. /**
  7646. * register: isp_exp_v_offset: Vertical offset for first block (0x00000008)
  7647. *
  7648. *****************************************************************************/
  7649. /* Slice: isp_exp_v_offset:*/
  7650. /* Vertical offset of first block in pixels.*/
  7651. /* 0 <= value <= 1806 */
  7652. #ifdef MRV_AE_ISP_EXP_V_OFFSET
  7653. #define MRV_AE_ISP_EXP_V_OFFSET_MIN 0x00000000
  7654. #define MRV_AE_ISP_EXP_V_OFFSET_MAX 0x00000B74 /* 3072-140 */
  7655. #endif /* MRV_AE_ISP_EXP_V_OFFSET */
  7656. /*****************************************************************************/
  7657. /**
  7658. * register: isp_exp_h_size: Horizontal size of one block (0x0000000c)
  7659. *
  7660. *****************************************************************************/
  7661. /* Slice: isp_exp_h_size:*/
  7662. /* Horizontal size in pixels of one block.*/
  7663. /* 35 <= value <= 516 */
  7664. #ifdef MRV_AE_ISP_EXP_H_SIZE
  7665. #define MRV_AE_ISP_EXP_H_SIZE_MIN 0x00000023
  7666. #define MRV_AE_ISP_EXP_H_SIZE_MAX 0x00000333
  7667. #endif /* MRV_AE_ISP_EXP_H_SIZE */
  7668. /*****************************************************************************/
  7669. /**
  7670. * register: isp_exp_v_size: Vertical size of one block (0x00000010)
  7671. *
  7672. *****************************************************************************/
  7673. /* Slice: isp_exp_v_size:*/
  7674. /* Vertical size in pixels of one block.*/
  7675. /* 28 <= value <= 390 */
  7676. #ifdef MRV_AE_ISP_EXP_V_SIZE
  7677. #define MRV_AE_ISP_EXP_V_SIZE_VALID_MASK (MRV_AE_ISP_EXP_V_SIZE_MASK & ~0x00000001)
  7678. #define MRV_AE_ISP_EXP_V_SIZE_MIN 0x0000001C
  7679. #define MRV_AE_ISP_EXP_V_SIZE_MAX 0x00000266
  7680. #endif /* MRV_AE_ISP_EXP_V_SIZE */
  7681. /*****************************************************************************/
  7682. /**
  7683. * register: isp_exp_mean_00: Mean luminance value of block 00 (0x00000014)
  7684. *
  7685. *****************************************************************************/
  7686. /* Slice: isp_exp_mean_00:*/
  7687. /* Mean luminance value of block 00 (x,y)*/
  7688. #ifdef MRV_AE_ISP_EXP_MEAN_00
  7689. #endif /* MRV_AE_ISP_EXP_MEAN_00 */
  7690. /*****************************************************************************/
  7691. /**
  7692. * register: isp_exp_mean_10: Mean luminance value of block 10 (0x00000018)
  7693. *
  7694. *****************************************************************************/
  7695. /* Slice: isp_exp_mean_10:*/
  7696. /* Mean luminance value of block 10 (x,y)*/
  7697. #ifdef MRV_AE_ISP_EXP_MEAN_10
  7698. #endif /* MRV_AE_ISP_EXP_MEAN_10 */
  7699. /*****************************************************************************/
  7700. /**
  7701. * register: isp_exp_mean_20: Mean luminance value of block 20 (0x0000001c)
  7702. *
  7703. *****************************************************************************/
  7704. /* Slice: isp_exp_mean_20:*/
  7705. /* Mean luminance value of block 20 (x,y)*/
  7706. #ifdef MRV_AE_ISP_EXP_MEAN_20
  7707. #endif /* MRV_AE_ISP_EXP_MEAN_20 */
  7708. /*****************************************************************************/
  7709. /**
  7710. * register: isp_exp_mean_30: Mean luminance value of block 30 (0x00000020)
  7711. *
  7712. *****************************************************************************/
  7713. /* Slice: isp_exp_mean_30:*/
  7714. /* Mean luminance value of block 30 (x,y)*/
  7715. #ifdef MRV_AE_ISP_EXP_MEAN_30
  7716. #endif /* MRV_AE_ISP_EXP_MEAN_30 */
  7717. /*****************************************************************************/
  7718. /**
  7719. * register: isp_exp_mean_40: Mean luminance value of block 40 (0x00000024)
  7720. *
  7721. *****************************************************************************/
  7722. /* Slice: isp_exp_mean_40:*/
  7723. /* Mean luminance value of block 40 (x,y)*/
  7724. #ifdef MRV_AE_ISP_EXP_MEAN_40
  7725. #endif /* MRV_AE_ISP_EXP_MEAN_40 */
  7726. /*****************************************************************************/
  7727. /**
  7728. * register: isp_exp_mean_01: Mean luminance value of block 01 (0x00000028)
  7729. *
  7730. *****************************************************************************/
  7731. /* Slice: isp_exp_mean_01:*/
  7732. /* Mean luminance value of block 01 (x,y)*/
  7733. #ifdef MRV_AE_ISP_EXP_MEAN_01
  7734. #endif /* MRV_AE_ISP_EXP_MEAN_01 */
  7735. /*****************************************************************************/
  7736. /**
  7737. * register: isp_exp_mean_11: Mean luminance value of block 11 (0x0000002c)
  7738. *
  7739. *****************************************************************************/
  7740. /* Register: isp_exp_mean_11: Mean luminance value of block 11 (0x0000002c)*/
  7741. /* Slice: isp_exp_mean_11:*/
  7742. /* Mean luminance value of block 11 (x,y)*/
  7743. #ifdef MRV_AE_ISP_EXP_MEAN_11
  7744. #endif /* MRV_AE_ISP_EXP_MEAN_11 */
  7745. /*****************************************************************************/
  7746. /**
  7747. * register: isp_exp_mean_21: Mean luminance value of block 21 (0x00000030)
  7748. *
  7749. *****************************************************************************/
  7750. /* Slice: isp_exp_mean_21:*/
  7751. /* Mean luminance value of block 21 (x,y)*/
  7752. #ifdef MRV_AE_ISP_EXP_MEAN_21
  7753. #endif /* MRV_AE_ISP_EXP_MEAN_21 */
  7754. /*****************************************************************************/
  7755. /**
  7756. * register: isp_exp_mean_31: Mean luminance value of block 31 (0x00000034)
  7757. *
  7758. *****************************************************************************/
  7759. /* Slice: isp_exp_mean_31:*/
  7760. /* Mean luminance value of block 31 (x,y)*/
  7761. #ifdef MRV_AE_ISP_EXP_MEAN_31
  7762. #endif /* MRV_AE_ISP_EXP_MEAN_31 */
  7763. /*****************************************************************************/
  7764. /**
  7765. * register: isp_exp_mean_41: Mean luminance value of block 41 (0x00000038)
  7766. *
  7767. *****************************************************************************/
  7768. /* Slice: isp_exp_mean_41:*/
  7769. /* Mean luminance value of block 41 (x,y)*/
  7770. #ifdef MRV_AE_ISP_EXP_MEAN_41
  7771. #endif /* MRV_AE_ISP_EXP_MEAN_41 */
  7772. /*****************************************************************************/
  7773. /**
  7774. * register: isp_exp_mean_02: Mean luminance value of block 02 (0x0000003c)
  7775. *
  7776. *****************************************************************************/
  7777. /* Slice: isp_exp_mean_02:*/
  7778. /* Mean luminance value of block 02 (x,y)*/
  7779. #ifdef MRV_AE_ISP_EXP_MEAN_02
  7780. #endif /* MRV_AE_ISP_EXP_MEAN_02 */
  7781. /*****************************************************************************/
  7782. /**
  7783. * register: isp_exp_mean_12: Mean luminance value of block 12 (0x00000040)
  7784. *
  7785. *****************************************************************************/
  7786. /* Slice: isp_exp_mean_12:*/
  7787. /* Mean luminance value of block 12 (x,y)*/
  7788. #ifdef MRV_AE_ISP_EXP_MEAN_12
  7789. #endif /* MRV_AE_ISP_EXP_MEAN_12 */
  7790. /*****************************************************************************/
  7791. /**
  7792. * register: isp_exp_mean_22: Mean luminance value of block 22 (0x00000044)
  7793. *
  7794. *****************************************************************************/
  7795. /* Slice: isp_exp_mean_22:*/
  7796. /* Mean luminance value of block 22 (x,y)*/
  7797. #ifdef MRV_AE_ISP_EXP_MEAN_22
  7798. #endif /* MRV_AE_ISP_EXP_MEAN_22 */
  7799. /*****************************************************************************/
  7800. /**
  7801. * register: isp_exp_mean_32: Mean luminance value of block 32 (0x00000048)
  7802. *
  7803. *****************************************************************************/
  7804. /* Slice: isp_exp_mean_32:*/
  7805. /* Mean luminance value of block 32 (x,y)*/
  7806. #ifdef MRV_AE_ISP_EXP_MEAN_32
  7807. #endif /* MRV_AE_ISP_EXP_MEAN_32 */
  7808. /*****************************************************************************/
  7809. /**
  7810. * register: isp_exp_mean_42: Mean luminance value of block 42 (0x0000004c)
  7811. *
  7812. *****************************************************************************/
  7813. /* Slice: isp_exp_mean_42:*/
  7814. /* Mean luminance value of block 42 (x,y)*/
  7815. #ifdef MRV_AE_ISP_EXP_MEAN_42
  7816. #endif /* MRV_AE_ISP_EXP_MEAN_42 */
  7817. /*****************************************************************************/
  7818. /**
  7819. * register: isp_exp_mean_03: Mean luminance value of block 03 (0x00000050)
  7820. *
  7821. *****************************************************************************/
  7822. /* Slice: isp_exp_mean_03:*/
  7823. /* Mean luminance value of block 03 (x,y)*/
  7824. #ifdef MRV_AE_ISP_EXP_MEAN_03
  7825. #endif /* MRV_AE_ISP_EXP_MEAN_03 */
  7826. /*****************************************************************************/
  7827. /**
  7828. * register: isp_exp_mean_13: Mean luminance value of block 13 (0x00000054)
  7829. *
  7830. *****************************************************************************/
  7831. /* Slice: isp_exp_mean_13:*/
  7832. /* Mean luminance value of block 13 (x,y)*/
  7833. #ifdef MRV_AE_ISP_EXP_MEAN_13
  7834. #endif /* MRV_AE_ISP_EXP_MEAN_13 */
  7835. /*****************************************************************************/
  7836. /**
  7837. * register: isp_exp_mean_23: Mean luminance value of block 23 (0x00000058)
  7838. *
  7839. *****************************************************************************/
  7840. /* Slice: isp_exp_mean_23:*/
  7841. /* Mean luminance value of block 23 (x,y)*/
  7842. #ifdef MRV_AE_ISP_EXP_MEAN_23
  7843. #endif /* MRV_AE_ISP_EXP_MEAN_23 */
  7844. /*****************************************************************************/
  7845. /**
  7846. * register: isp_exp_mean_33: Mean luminance value of block 33 (0x0000005c)
  7847. *
  7848. *****************************************************************************/
  7849. /* Slice: isp_exp_mean_33:*/
  7850. /* Mean luminance value of block 33 (x,y)*/
  7851. #ifdef MRV_AE_ISP_EXP_MEAN_33
  7852. #endif /* MRV_AE_ISP_EXP_MEAN_33 */
  7853. /*****************************************************************************/
  7854. /**
  7855. * register: isp_exp_mean_43: Mean luminance value of block 43 (0x00000060)
  7856. *
  7857. *****************************************************************************/
  7858. /* Slice: isp_exp_mean_43:*/
  7859. /* Mean luminance value of block 43 (x,y)*/
  7860. #ifdef MRV_AE_ISP_EXP_MEAN_43
  7861. #endif /* MRV_AE_ISP_EXP_MEAN_43 */
  7862. /*****************************************************************************/
  7863. /**
  7864. * register: isp_exp_mean_04: Mean luminance value of block 04 (0x00000064)
  7865. *
  7866. *****************************************************************************/
  7867. /* Slice: isp_exp_mean_04:*/
  7868. /* Mean luminance value of block 04 (x,y)*/
  7869. #ifdef MRV_AE_ISP_EXP_MEAN_04
  7870. #endif /* MRV_AE_ISP_EXP_MEAN_04 */
  7871. /*****************************************************************************/
  7872. /**
  7873. * register: isp_exp_mean_14: Mean luminance value of block 14 (0x00000068)
  7874. *
  7875. *****************************************************************************/
  7876. /* Slice: isp_exp_mean_14:*/
  7877. /* Mean luminance value of block 14 (x,y)*/
  7878. #ifdef MRV_AE_ISP_EXP_MEAN_14
  7879. #endif /* MRV_AE_ISP_EXP_MEAN_14 */
  7880. /*****************************************************************************/
  7881. /**
  7882. * register: isp_exp_mean_24: Mean luminance value of block 24 (0x0000006c)
  7883. *
  7884. *****************************************************************************/
  7885. /* Slice: isp_exp_mean_24:*/
  7886. /* Mean luminance value of block 24 (x,y)*/
  7887. #ifdef MRV_AE_ISP_EXP_MEAN_24
  7888. #endif /* MRV_AE_ISP_EXP_MEAN_24 */
  7889. /*****************************************************************************/
  7890. /**
  7891. * register: isp_exp_mean_34: Mean luminance value of block 34 (0x00000070)
  7892. *
  7893. *****************************************************************************/
  7894. /* Slice: isp_exp_mean_34:*/
  7895. /* Mean luminance value of block 34 (x,y)*/
  7896. #ifdef MRV_AE_ISP_EXP_MEAN_34
  7897. #endif /* MRV_AE_ISP_EXP_MEAN_34 */
  7898. /*****************************************************************************/
  7899. /**
  7900. * register: isp_exp_mean_44: Mean luminance value of block 44 (0x00000074)
  7901. *
  7902. *****************************************************************************/
  7903. /* Slice: isp_exp_mean_44:*/
  7904. /* Mean luminance value of block 44 (x,y)*/
  7905. #ifdef MRV_AE_ISP_EXP_MEAN_44
  7906. #endif /* MRV_AE_ISP_EXP_MEAN_44 */
  7907. /*****************************************************************************/
  7908. /* ISP Black Level Subtraction Registers */
  7909. /*****************************************************************************/
  7910. /*****************************************************************************/
  7911. /**
  7912. * register: isp_bls_ctrl: global control register (0x00000000)
  7913. *
  7914. *****************************************************************************/
  7915. /* Slice: WINDOW_ENABLE:*/
  7916. /* 0: no measuring is performed */
  7917. /* 1: only window 1 is measured */
  7918. /* 2: only window 2 is measured */
  7919. /* 3: both windows are measured */
  7920. #ifdef MRV_BLS_WINDOW_ENABLE
  7921. #define MRV_BLS_WINDOW_ENABLE_NONE 0U /* 0: no measuring is performed */
  7922. #define MRV_BLS_WINDOW_ENABLE_WND1 1U /* 1: only window 1 is measured */
  7923. #define MRV_BLS_WINDOW_ENABLE_WND2 2U /* 2: only window 2 is measured */
  7924. #define MRV_BLS_WINDOW_ENABLE_BOTH 3U /* 3: both windows are measured */
  7925. #define MRV_BLS_WINDOW_ENABLE_WND1_MASK 0x00000004U
  7926. #define MRV_BLS_WINDOW_ENABLE_WND1_SHIFT 2U
  7927. #define MRV_BLS_WINDOW_ENABLE_WND2_MASK 0x00000008U
  7928. #define MRV_BLS_WINDOW_ENABLE_WND2_SHIFT 3U
  7929. #endif /* MRV_BLS_WINDOW_ENABLE */
  7930. /* Slice: BLS_MODE:*/
  7931. /* 1: subtract measured values */
  7932. /* 0: subtract fixed values */
  7933. #ifdef MRV_BLS_BLS_MODE
  7934. #define MRV_BLS_BLS_MODE_MEAS 1U /* 1: subtract measured values */
  7935. #define MRV_BLS_BLS_MODE_FIX 0U /* 0: subtract fixed values */
  7936. #endif /* MRV_BLS_BLS_MODE */
  7937. /* Slice: BLS_ENABLE:*/
  7938. /* 1: black level subtraction is enabled */
  7939. /* 0: bypass the black level processing */
  7940. #ifdef MRV_BLS_BLS_ENABLE
  7941. #define MRV_BLS_BLS_ENABLE_PROCESS 1U /* 1: black level subtraction is enabled */
  7942. #define MRV_BLS_BLS_ENABLE_BYPASS 0U /* 0: bypass the black level processing */
  7943. #endif /* MRV_BLS_BLS_ENABLE */
  7944. /*****************************************************************************/
  7945. /**
  7946. * register: isp_bls_samples: samples register (0x00000004)
  7947. *
  7948. *****************************************************************************/
  7949. /* Slice: BLS_SAMPLES:*/
  7950. /* This number to the power of two gives the number of measure samples for */
  7951. /* each Bayer position. Range 0x00: 2^0=1 to 0x12: 2^18=262144. This number */
  7952. /* is also the divider for the accumulator for each Bayer position.*/
  7953. /**/
  7954. /* The accumulation will be stopped, if the number of measured pixels for the */
  7955. /* current Bayer position is equal to the number of samples.*/
  7956. /**/
  7957. /* The measure windows must be positioned that way that the number of included */
  7958. /* pixels of each Bayer position included by both windows is equal or greater */
  7959. /* than the number of measure samples calculated by 2^BLS_SAMPLES !*/
  7960. /**/
  7961. /* NOTE:*/
  7962. /* - The number of pixels of one Bayer position is 1/4 of the number of all */
  7963. /* Pixels included by the measure windows.*/
  7964. #ifdef MRV_BLS_BLS_SAMPLES
  7965. #define MRV_BLS_BLS_SAMPLES_MAX (0x00000014U) /* maximum is 2^20 = 1048576 */
  7966. #endif /* MRV_BLS_BLS_SAMPLES */
  7967. /*****************************************************************************/
  7968. /**
  7969. * register: isp_bls_h1_start: window 1 horizontal start (0x00000008)
  7970. *
  7971. *****************************************************************************/
  7972. /* Slice: BLS_H1_START:*/
  7973. /* Black pixel window 1 horizontal start position */
  7974. #ifdef MRV_BLS_BLS_H1_START
  7975. #define MRV_BLS_BLS_H1_START_MAX (MRV_BLS_BLS_H1_START_MASK >> MRV_BLS_BLS_H1_START_SHIFT)
  7976. #endif /* MRV_BLS_BLS_H1_START */
  7977. /*****************************************************************************/
  7978. /**
  7979. * register: isp_bls_h1_stop: window 1 horizontal stop (0x0000000c)
  7980. *
  7981. *****************************************************************************/
  7982. /* Slice: BLS_H1_STOP:*/
  7983. /* Black pixel window 1 horizontal stop position */
  7984. #ifdef MRV_BLS_BLS_H1_STOP
  7985. #define MRV_BLS_BLS_H1_STOP_MAX (MRV_BLS_BLS_H1_STOP_MASK >> MRV_BLS_BLS_H1_STOP_SHIFT)
  7986. #endif /* MRV_BLS_BLS_H1_STOP */
  7987. /*****************************************************************************/
  7988. /**
  7989. * register: isp_bls_v1_start: window 1 vertical start (0x00000010)
  7990. *
  7991. *****************************************************************************/
  7992. /* Slice: BLS_V1_START:*/
  7993. /* Black pixel window 1 vertical start position */
  7994. #ifdef MRV_BLS_BLS_V1_START
  7995. #define MRV_BLS_BLS_V1_START_MAX (MRV_BLS_BLS_V1_START_MASK >> MRV_BLS_BLS_V1_START_SHIFT)
  7996. #endif /* MRV_BLS_BLS_V1_START */
  7997. /*****************************************************************************/
  7998. /**
  7999. * register: isp_bls_v1_stop: window 1 vertical stop (0x00000014)
  8000. *
  8001. *****************************************************************************/
  8002. /* Slice: BLS_V1_STOP:*/
  8003. /* Black pixel window 1 vertical stop position */
  8004. #ifdef MRV_BLS_BLS_V1_STOP
  8005. #define MRV_BLS_BLS_V1_STOP_MAX (MRV_BLS_BLS_V1_STOP_MASK >> MRV_BLS_BLS_V1_STOP_SHIFT)
  8006. #endif /* MRV_BLS_BLS_V1_STOP */
  8007. /*****************************************************************************/
  8008. /**
  8009. * register: isp_bls_h2_start: window 2 horizontal start (0x00000018)
  8010. *
  8011. *****************************************************************************/
  8012. /* Slice: BLS_H2_START:*/
  8013. /* Black pixel window 2 horizontal start position */
  8014. #ifdef MRV_BLS_BLS_H2_START
  8015. #define MRV_BLS_BLS_H2_START_MAX (MRV_BLS_BLS_H2_START_MASK >> MRV_BLS_BLS_H2_START_SHIFT)
  8016. #endif /* MRV_BLS_BLS_H2_START */
  8017. /*****************************************************************************/
  8018. /**
  8019. * register: isp_bls_h2_stop: window 2 horizontal stop (0x0000001c)
  8020. *
  8021. *****************************************************************************/
  8022. /* Slice: BLS_H2_STOP:*/
  8023. /* Black pixel window 2 horizontal stop position */
  8024. #ifdef MRV_BLS_BLS_H2_STOP
  8025. #define MRV_BLS_BLS_H2_STOP_MAX (MRV_BLS_BLS_H2_STOP_MASK >> MRV_BLS_BLS_H2_STOP_SHIFT)
  8026. #endif /* MRV_BLS_BLS_H2_STOP */
  8027. /*****************************************************************************/
  8028. /**
  8029. * register: isp_bls_v2_start: window 2 vertical start (0x00000020)
  8030. *
  8031. *****************************************************************************/
  8032. /* Slice: BLS_V2_START:*/
  8033. /* Black pixel window 2 vertical start position */
  8034. #ifdef MRV_BLS_BLS_V2_START
  8035. #define MRV_BLS_BLS_V2_START_MAX (MRV_BLS_BLS_V2_START_MASK >> MRV_BLS_BLS_V2_START_SHIFT)
  8036. #endif /* MRV_BLS_BLS_V2_START */
  8037. /*****************************************************************************/
  8038. /**
  8039. * register: isp_bls_v2_stop: window 2 vertical stop (0x00000024)
  8040. *
  8041. *****************************************************************************/
  8042. /* Slice: BLS_V2_STOP:*/
  8043. /* Black pixel window 2 vertical stop position */
  8044. #ifdef MRV_BLS_BLS_V2_STOP
  8045. #define MRV_BLS_BLS_V2_STOP_MAX (MRV_BLS_BLS_V2_STOP_MASK >> MRV_BLS_BLS_V2_STOP_SHIFT)
  8046. #endif /* MRV_BLS_BLS_V2_STOP */
  8047. /*****************************************************************************/
  8048. /**
  8049. * register: isp_bls_a_fixed: fixed black level A (0x00000028)
  8050. *
  8051. *****************************************************************************/
  8052. /* Slice: BLS_A_FIXED:*/
  8053. /* Fixed black level for A pixels – signed */
  8054. /* two's complement, value range from -4096 to +4095,*/
  8055. /* a positive value will be subtracted from the pixel values */
  8056. #ifdef MRV_BLS_BLS_A_FIXED
  8057. #endif /* MRV_BLS_BLS_A_FIXED */
  8058. /*****************************************************************************/
  8059. /**
  8060. * register: isp_bls_b_fixed: fixed black level B (0x0000002c)
  8061. *
  8062. *****************************************************************************/
  8063. /* Slice: BLS_B_FIXED:*/
  8064. /* Fixed black level for B pixels – signed */
  8065. /* two's complement, value range from -4096 to +4095 */
  8066. #ifdef MRV_BLS_BLS_B_FIXED
  8067. #endif /* MRV_BLS_BLS_B_FIXED */
  8068. /*****************************************************************************/
  8069. /**
  8070. * register: isp_bls_c_fixed: fixed black level C (0x00000030)
  8071. *
  8072. *****************************************************************************/
  8073. /* Slice: BLS_C_FIXED:*/
  8074. /* Fixed black level for C pixels – signed */
  8075. /* two's complement, value range from -4096 to +4095 */
  8076. #ifdef MRV_BLS_BLS_C_FIXED
  8077. #endif /* MRV_BLS_BLS_C_FIXED */
  8078. /*****************************************************************************/
  8079. /**
  8080. * register: isp_bls_d_fixed: fixed black level D (0x00000034)
  8081. *
  8082. *****************************************************************************/
  8083. /* Slice: BLS_D_FIXED:*/
  8084. /* Fixed black level for D pixels - signed */
  8085. /* two's complement, value range from -4096 to +4095 */
  8086. #ifdef MRV_BLS_BLS_D_FIXED
  8087. #endif /* MRV_BLS_BLS_D_FIXED */
  8088. /*****************************************************************************/
  8089. /**
  8090. * register: isp_bls_a_measured: measured black level A (0x00000038)
  8091. *
  8092. *****************************************************************************/
  8093. /* Slice: BLS_A_MEASURED:*/
  8094. /* Measured black level for A pixels */
  8095. #ifdef MRV_BLS_BLS_A_MEASURED
  8096. #endif /* MRV_BLS_BLS_A_MEASURED */
  8097. /*****************************************************************************/
  8098. /**
  8099. * register: isp_bls_b_measured: measured black level B (0x0000003c)
  8100. *
  8101. *****************************************************************************/
  8102. /* Slice: BLS_B_MEASURED:*/
  8103. /* Measured black level for B pixels */
  8104. #ifdef MRV_BLS_BLS_B_MEASURED
  8105. #endif /* MRV_BLS_BLS_B_MEASURED */
  8106. /*****************************************************************************/
  8107. /**
  8108. * register: isp_bls_c_measured: measured black level C (0x00000040)
  8109. *
  8110. *****************************************************************************/
  8111. /* Slice: BLS_C_MEASURED:*/
  8112. /* Measured black level for C pixels */
  8113. #ifdef MRV_BLS_BLS_C_MEASURED
  8114. #endif /* MRV_BLS_BLS_C_MEASURED */
  8115. /*****************************************************************************/
  8116. /**
  8117. * register: isp_bls_d_measured: measured black level D (0x00000044)
  8118. *
  8119. *****************************************************************************/
  8120. /* Slice: BLS_D_MEASURED:*/
  8121. /* Measured black level for D pixels */
  8122. #ifdef MRV_BLS_BLS_D_MEASURED
  8123. #endif /* MRV_BLS_BLS_D_MEASURED */
  8124. /*****************************************************************************/
  8125. /* ISP Denoising Pre-Filter Registers */
  8126. /*****************************************************************************/
  8127. /*****************************************************************************/
  8128. /**
  8129. * register: isp_dpf_mode: Mode control for Denoising Pre-Filter block
  8130. * (0x00000000)
  8131. *
  8132. *****************************************************************************/
  8133. /* Slice: USE_NF_GAIN:*/
  8134. /* 1: dpf_nf_gain's will be used */
  8135. /* 0: external AWB gains will be used *Default**/
  8136. #ifdef MRV_DPF_USE_NF_GAIN
  8137. #endif /* MRV_DPF_USE_NF_GAIN */
  8138. /* Slice: LSC_GAIN_COMP:*/
  8139. /* 1: LSC gain will be processed */
  8140. /* 0: LSC gain will not be processed *Default**/
  8141. #ifdef MRV_DPF_LSC_GAIN_COMP
  8142. #endif /* MRV_DPF_LSC_GAIN_COMP */
  8143. /* Slice: AWB_GAIN_COMP:*/
  8144. /* 1: AWB gain or internal dpf_nf_gain will be processed */
  8145. /* 0: AWB gain or internal dpf_nf_gain will not be processed *Default**/
  8146. #ifdef MRV_DPF_AWB_GAIN_COMP
  8147. #endif /* MRV_DPF_AWB_GAIN_COMP */
  8148. /* Slice: NLL_SEGMENTATION:*/
  8149. /* 1: optimized logarithmic like segmentation for Noise Level Lookup (NLL)*/
  8150. /* 0: equidistant segmentation for NLL *Default**/
  8151. #ifdef MRV_DPF_NLL_SEGMENTATION
  8152. #endif /* MRV_DPF_NLL_SEGMENTATION */
  8153. /* Slice: RB_FILTER_SIZE:*/
  8154. /* 1: Red and Blue filter kernel size of 9x9 (5x5 active) pixels */
  8155. /* 0: Wide Red and Blue filter kernel size of 13x9 (7x5 active) pixels *Default**/
  8156. #ifdef MRV_DPF_RB_FILTER_SIZE
  8157. #endif /* MRV_DPF_RB_FILTER_SIZE */
  8158. /* Slice: R_FILTER_OFF:*/
  8159. /* 1: disable filter processing for red pixels (R)*/
  8160. /* 0: filter R pixels *Default**/
  8161. #ifdef MRV_DPF_R_FILTER_OFF
  8162. #endif /* MRV_DPF_R_FILTER_OFF */
  8163. /* Slice: GR_FILTER_OFF:*/
  8164. /* 1: disable filter processing for green pixels in green/red lines (GR)*/
  8165. /* 0: filter GR pixels *Default**/
  8166. #ifdef MRV_DPF_GR_FILTER_OFF
  8167. #endif /* MRV_DPF_GR_FILTER_OFF */
  8168. /* Slice: GB_FILTER_OFF:*/
  8169. /* 1: disable filter processing for green pixels in green/blue lines (GB)*/
  8170. /* 0: filter GB pixels *Default**/
  8171. #ifdef MRV_DPF_GB_FILTER_OFF
  8172. #endif /* MRV_DPF_GB_FILTER_OFF */
  8173. /* Slice: B_FILTER_OFF:*/
  8174. /* 1: disable filter processing for blue pixels (B)*/
  8175. /* 0: filter B pixels *Default**/
  8176. #ifdef MRV_DPF_B_FILTER_OFF
  8177. #endif /* MRV_DPF_B_FILTER_OFF */
  8178. /* Slice: DPF_ENABLE:*/
  8179. /* 1: enable dpf */
  8180. /* 0: bypass dpf *Default**/
  8181. #ifdef MRV_DPF_DPF_ENABLE
  8182. #endif /* MRV_DPF_DPF_ENABLE */
  8183. /*****************************************************************************/
  8184. /**
  8185. * register: isp_dpf_strength_r: filter strength of the RED filter (0x00000004)
  8186. *
  8187. *****************************************************************************/
  8188. /* Slice: INV_WEIGHT_R:*/
  8189. /* Filter strength of the filter is determined by weight. Default is a */
  8190. /* weight of 1. A higher weight increases the filter strength. In this */
  8191. /* register the unsigned 8 bit value 64/weight is stored.*/
  8192. /**/
  8193. /* The following values show examples:*/
  8194. /* weight=0.251 -> 255, weight=0.5 -> 128,*/
  8195. /* weight=1 -> 64 *default**/
  8196. /* weight=1.25 -> 51, weight=1.5 -> 42,*/
  8197. /* weight=1.75 -> 37, weight=2 -> 32 */
  8198. #ifdef MRV_DPF_INV_WEIGHT_R
  8199. #endif /* MRV_DPF_INV_WEIGHT_R */
  8200. /*****************************************************************************/
  8201. /**
  8202. * register: isp_dpf_strength_g: filter strength of the GREEN filter (0x00000008)
  8203. *
  8204. *****************************************************************************/
  8205. /* Slice: INV_WEIGHT_G:*/
  8206. /* Filter strength of the filter is determined by weight. Default is a */
  8207. /* weight of 1. A higher weight increases the filter strength. In this */
  8208. /* register the unsigned 8 bit value 64/weight is stored.*/
  8209. /**/
  8210. /* The following values show examples:*/
  8211. /* weight=0.251 -> 255, weight=0.5 -> 128,*/
  8212. /* weight=1 -> 64 *default**/
  8213. /* weight=1.25 -> 51, weight=1.5 -> 42,*/
  8214. /* weight=1.75 -> 37, weight=2 -> 32 */
  8215. #ifdef MRV_DPF_INV_WEIGHT_G
  8216. #endif /* MRV_DPF_INV_WEIGHT_G */
  8217. /*****************************************************************************/
  8218. /**
  8219. * register: isp_dpf_strength_b: filter strength of the BLUE filter (0x0000000c)
  8220. *
  8221. *****************************************************************************/
  8222. /* Slice: INV_WEIGHT_B:*/
  8223. /* Filter strength of the filter is determined by weight. Default is a */
  8224. /* weight of 1. A higher weight increases the filter strength. In this */
  8225. /* register the unsigned 8 bit value 64/weight is stored.*/
  8226. /**/
  8227. /* The following values show examples:*/
  8228. /* weight=0.251 -> 255, weight=0.5 -> 128,*/
  8229. /* weight=1 -> 64 *default**/
  8230. /* weight=1.25 -> 51, weight=1.5 -> 42,*/
  8231. /* weight=1.75 -> 37, weight=2 -> 32 */
  8232. #ifdef MRV_DPF_INV_WEIGHT_B
  8233. #endif /* MRV_DPF_INV_WEIGHT_B */
  8234. /*****************************************************************************/
  8235. /**
  8236. * register: isp_dpf_s_weight_g_1_4: Spatial Weights green channel 1 2 3 4
  8237. * (0x00000010)
  8238. *
  8239. *****************************************************************************/
  8240. /* Slice: S_WEIGHT_G4:*/
  8241. /* Filter Coefficient green channel S_WEIGHT_G4 */
  8242. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8243. /* Default value is 16/16 (*Default*)*/
  8244. #ifdef MRV_DPF_S_WEIGHT_G4
  8245. #endif /* MRV_DPF_S_WEIGHT_G4 */
  8246. /* Slice: S_WEIGHT_G3:*/
  8247. /* Filter Coefficient green channel S_WEIGHT_G3 */
  8248. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8249. /* Default value is 16/16 (*Default*)*/
  8250. #ifdef MRV_DPF_S_WEIGHT_G3
  8251. #endif /* MRV_DPF_S_WEIGHT_G3 */
  8252. /* Slice: S_WEIGHT_G2:*/
  8253. /* Filter Coefficient green channel S_WEIGHT_G2 */
  8254. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8255. /* Default value is 16/16 (*Default*)*/
  8256. #ifdef MRV_DPF_S_WEIGHT_G2
  8257. #endif /* MRV_DPF_S_WEIGHT_G2 */
  8258. /* Slice: S_WEIGHT_G1:*/
  8259. /* Filter Coefficient green channel S_WEIGHT_G1 */
  8260. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8261. /* Default value is 16/16 (*Default*)*/
  8262. #ifdef MRV_DPF_S_WEIGHT_G1
  8263. #endif /* MRV_DPF_S_WEIGHT_G1 */
  8264. /*****************************************************************************/
  8265. /**
  8266. * register: isp_dpf_s_weight_g_5_6: Spatial Weights green channel 5 6
  8267. * (0x00000014)
  8268. *
  8269. *****************************************************************************/
  8270. /* Slice: S_WEIGHT_G6:*/
  8271. /* Filter Coefficient green channel S_WEIGHT_G6 */
  8272. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8273. /* Default value is 16/16 (*Default*)*/
  8274. #ifdef MRV_DPF_S_WEIGHT_G6
  8275. #endif /* MRV_DPF_S_WEIGHT_G6 */
  8276. /* Slice: S_WEIGHT_G5:*/
  8277. /* Filter Coefficient green channel S_WEIGHT_G5 */
  8278. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8279. /* Default value is 16/16 (*Default*)*/
  8280. #ifdef MRV_DPF_S_WEIGHT_G5
  8281. #endif /* MRV_DPF_S_WEIGHT_G5 */
  8282. /*****************************************************************************/
  8283. /**
  8284. * register: isp_dpf_s_weight_rb_1_4: Spatial Weights red/blue channels 1 2 3 4
  8285. * (0x00000018)
  8286. *
  8287. *****************************************************************************/
  8288. /* Slice: S_WEIGHT_RB4:*/
  8289. /* Filter Coefficient red/blue channels S_WEIGHT_RB4 */
  8290. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8291. /* Default value is 16/16 (*Default*)*/
  8292. #ifdef MRV_DPF_S_WEIGHT_RB4
  8293. #endif /* MRV_DPF_S_WEIGHT_RB4 */
  8294. /* Slice: S_WEIGHT_RB3:*/
  8295. /* Filter Coefficient red/blue channels S_WEIGHT_RB3 */
  8296. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8297. /* Default value is 16/16 (*Default*)*/
  8298. #ifdef MRV_DPF_S_WEIGHT_RB3
  8299. #endif /* MRV_DPF_S_WEIGHT_RB3 */
  8300. /* Slice: S_WEIGHT_RB2:*/
  8301. /* Filter Coefficient red/blue channels S_WEIGHT_RB2 */
  8302. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8303. /* Default value is 16/16 (*Default*)*/
  8304. #ifdef MRV_DPF_S_WEIGHT_RB2
  8305. #endif /* MRV_DPF_S_WEIGHT_RB2 */
  8306. /* Slice: S_WEIGHT_RB1:*/
  8307. /* Filter Coefficient red/blue channels S_WEIGHT_RB1 */
  8308. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8309. /* Default value is 16/16 (*Default*)*/
  8310. #ifdef MRV_DPF_S_WEIGHT_RB1
  8311. #endif /* MRV_DPF_S_WEIGHT_RB1 */
  8312. /*****************************************************************************/
  8313. /**
  8314. * register: isp_dpf_s_weight_rb_5_6: Spatial Weights red/blue channels 5 6
  8315. * (0x0000001c)
  8316. *
  8317. *****************************************************************************/
  8318. /* Slice: S_WEIGHT_RB6:*/
  8319. /* Filter Coefficient red/blue channels S_WEIGHT_RB6 */
  8320. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8321. /* Default value is 16/16 (*Default*)*/
  8322. #ifdef MRV_DPF_S_WEIGHT_RB6
  8323. #endif /* MRV_DPF_S_WEIGHT_RB6 */
  8324. /* Slice: S_WEIGHT_RB5:*/
  8325. /* Filter Coefficient red/blue channels S_WEIGHT_RB5 */
  8326. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8327. /* Default value is 16/16 (*Default*)*/
  8328. #ifdef MRV_DPF_S_WEIGHT_RB5
  8329. #endif /* MRV_DPF_S_WEIGHT_RB5 */
  8330. /*****************************************************************************/
  8331. /**
  8332. * register array: isp_dpf_nll_coeff: Noise Level Lookup Coefficient
  8333. * (0x0040 + n*0x4 (n=0..16))
  8334. *
  8335. *****************************************************************************/
  8336. /* Slice: nll_coeff_n:*/
  8337. /* Noise Level Lookup Table Coefficient nll_coeff_n */
  8338. /* 10 bit unsigned, value range 1/1024 to 1023/1024 (*Default*)*/
  8339. #ifdef MRV_DPF_NLL_COEFF_N
  8340. #endif /* MRV_DPF_NLL_COEFF_N */
  8341. /*****************************************************************************/
  8342. /**
  8343. * register: isp_dpf_nf_gain_r: noise function gain for red pixels (0x00000064)
  8344. *
  8345. *****************************************************************************/
  8346. /* Slice: DPF_NF_GAIN_R:*/
  8347. /* Noise Function (NF) Gain that replaces the AWB gain for red pixels.*/
  8348. /* 12 bit unsigned integer format: gain=1 -> 0x100 */
  8349. #ifdef MRV_DPF_DPF_NF_GAIN_R
  8350. #endif /* MRV_DPF_DPF_NF_GAIN_R */
  8351. /*****************************************************************************/
  8352. /**
  8353. * register: isp_dpf_nf_gain_gr: noise function gain for green in red pixels
  8354. * (0x00000068)
  8355. *
  8356. *****************************************************************************/
  8357. /* Slice: DPF_NF_GAIN_GR:*/
  8358. /* Noise Function (NF) Gain that replaces the AWB gain for green pixels in a */
  8359. /* red line.*/
  8360. /* 12 bit unsigned integer format: gain=1 -> 0x100 */
  8361. #ifdef MRV_DPF_DPF_NF_GAIN_GR
  8362. #endif /* MRV_DPF_DPF_NF_GAIN_GR */
  8363. /*****************************************************************************/
  8364. /**
  8365. * register: isp_dpf_nf_gain_gb: noise function gain for green in blue pixels
  8366. * (0x0000006c)
  8367. *
  8368. *****************************************************************************/
  8369. /* Slice: DPF_NF_GAIN_GB:*/
  8370. /* Noise Function (NF) Gain that replaces the AWB gain for green pixels in a */
  8371. /* blue line.*/
  8372. /* 12 bit unsigned integer format: gain=1 -> 0x100 */
  8373. #ifdef MRV_DPF_DPF_NF_GAIN_GB
  8374. #endif /* MRV_DPF_DPF_NF_GAIN_GB */
  8375. /*****************************************************************************/
  8376. /**
  8377. * register: isp_dpf_nf_gain_b: noise function gain for blue pixels (0x00000070)
  8378. *
  8379. *****************************************************************************/
  8380. /* Slice: DPF_NF_GAIN_B:*/
  8381. /* Noise Function (NF) Gain that replaces the AWB gain for blue pixels.*/
  8382. /* 12 bit unsigned integer format: gain=1 -> 0x100 */
  8383. #ifdef MRV_DPF_DPF_NF_GAIN_B
  8384. #endif /* MRV_DPF_DPF_NF_GAIN_B */
  8385. /*****************************************************************************/
  8386. /* ISP Defect Pixel Cluster Correction Registers */
  8387. /*****************************************************************************/
  8388. /*****************************************************************************/
  8389. /**
  8390. * register: isp_dpcc_mode: mode control for DPCC block (0x0000)
  8391. *
  8392. *****************************************************************************/
  8393. /* Slice: STAGE1_ENABLE:*/
  8394. /* 1: enable stage1 *Default**/
  8395. /* 0: bypass stage1 */
  8396. #ifdef MRV_DPCC_STAGE1_ENABLE
  8397. #endif /* MRV_DPCC_STAGE1_ENABLE */
  8398. /* Slice: GRAYSCALE_MODE:*/
  8399. /* 1: enable gray scale data input from black and white sensors (without color filter array)*/
  8400. /* 0: BAYER DATA INPUT *Default**/
  8401. #ifdef MRV_DPCC_GRAYSCALE_MODE
  8402. #endif /* MRV_DPCC_GRAYSCALE_MODE */
  8403. /* Slice: ISP_DPCC_enable:*/
  8404. /* 1: enable DPCC */
  8405. /* 0: bypass DPCC *Default**/
  8406. #ifdef MRV_DPCC_ISP_DPCC_ENABLE
  8407. #endif /* MRV_DPCC_ISP_DPCC_ENABLE */
  8408. /*****************************************************************************/
  8409. /**
  8410. * register: isp_dpcc_output_mode: interpolation mode for correction unit
  8411. * (0x00000004)
  8412. *
  8413. *****************************************************************************/
  8414. /* Slice: STAGE1_RB_3x3:*/
  8415. /* 1: stage1 red/blue 9 pixel (3x3) output median */
  8416. /* 0: stage1 red/blue 4 or 5 pixel output median *Default**/
  8417. #ifdef MRV_DPCC_STAGE1_RB_3X3
  8418. #endif /* MRV_DPCC_STAGE1_RB_3X3 */
  8419. /* Slice: STAGE1_G_3x3:*/
  8420. /* 1: stage1 green 9 pixel (3x3) output median */
  8421. /* 0: stage1 green 4 or 5 pixel output median *Default**/
  8422. #ifdef MRV_DPCC_STAGE1_G_3X3
  8423. #endif /* MRV_DPCC_STAGE1_G_3X3 */
  8424. /* Slice: STAGE1_INCL_RB_CENTER:*/
  8425. /* 1: stage1 include center pixel for red/blue output median 2x2+1 */
  8426. /* *Default* 0: stage1 do not include center pixel for red/blue output median 2x2 */
  8427. #ifdef MRV_DPCC_STAGE1_INCL_RB_CENTER
  8428. #endif /* MRV_DPCC_STAGE1_INCL_RB_CENTER */
  8429. /* Slice: STAGE1_INCL_GREEN_CENTER:*/
  8430. /* 1: stage1 include center pixel for green output median 2x2+1 *Default**/
  8431. /* 0: stage1 do not include center pixel for green output median 2x2 */
  8432. #ifdef MRV_DPCC_STAGE1_INCL_GREEN_CENTER
  8433. #endif /* MRV_DPCC_STAGE1_INCL_GREEN_CENTER */
  8434. /*****************************************************************************/
  8435. /**
  8436. * register: isp_dpcc_set_use: DPCC methods set usage for detection
  8437. * (0x00000008)
  8438. *
  8439. *****************************************************************************/
  8440. /* Slice: STAGE1_USE_FIX_SET:*/
  8441. /* 1: stage1 use hard coded methods set *Default**/
  8442. /* 0: stage1 do not use hard coded methods set */
  8443. #ifdef MRV_DPCC_STAGE1_USE_FIX_SET
  8444. #endif /* MRV_DPCC_STAGE1_USE_FIX_SET */
  8445. /* Slice: STAGE1_USE_SET_3:*/
  8446. /* 1: stage1 use methods set 3 */
  8447. /* 0: stage1 do not use methods set 3 *Default**/
  8448. #ifdef MRV_DPCC_STAGE1_USE_SET_3
  8449. #endif /* MRV_DPCC_STAGE1_USE_SET_3 */
  8450. /* Slice: STAGE1_USE_SET_2:*/
  8451. /* 1: stage1 use methods set 2 */
  8452. /* 0: stage1 do not use methods set 2 *Default**/
  8453. #ifdef MRV_DPCC_STAGE1_USE_SET_2
  8454. #endif /* MRV_DPCC_STAGE1_USE_SET_2 */
  8455. /* Slice: STAGE1_USE_SET_1:*/
  8456. /* 1: stage1 use methods set 1 *Default**/
  8457. /* 0: stage1 do not use methods set 1 */
  8458. #ifdef MRV_DPCC_STAGE1_USE_SET_1
  8459. #endif /* MRV_DPCC_STAGE1_USE_SET_1 */
  8460. /*****************************************************************************/
  8461. /**
  8462. * register: isp_dpcc_methods_set_1: Methods enable bits for SET_1
  8463. * (0x0000000c)
  8464. *
  8465. *****************************************************************************/
  8466. /* Slice: RG_RED_BLUE1_ENABLE:*/
  8467. /* 1: enable Rank Gradient check for red_blue *Default**/
  8468. /* 0: bypass Rank Gradient check for red_blue */
  8469. #ifdef MRV_DPCC_RG_RED_BLUE1_ENABLE
  8470. #endif /* MRV_DPCC_RG_RED_BLUE1_ENABLE */
  8471. /* Slice: RND_RED_BLUE1_ENABLE:*/
  8472. /* 1: enable Rank Neighbor Difference check for red_blue *Default**/
  8473. /* 0: bypass Rank Neighbor Difference check for red_blue */
  8474. #ifdef MRV_DPCC_RND_RED_BLUE1_ENABLE
  8475. #endif /* MRV_DPCC_RND_RED_BLUE1_ENABLE */
  8476. /* Slice: RO_RED_BLUE1_ENABLE:*/
  8477. /* 1: enable Rank Order check for red_blue *Default**/
  8478. /* 0: bypass Rank Order check for red_blue */
  8479. #ifdef MRV_DPCC_RO_RED_BLUE1_ENABLE
  8480. #endif /* MRV_DPCC_RO_RED_BLUE1_ENABLE */
  8481. /* Slice: LC_RED_BLUE1_ENABLE:*/
  8482. /* 1: enable Line check for red_blue *Default**/
  8483. /* 0: bypass Line check for red_blue */
  8484. #ifdef MRV_DPCC_LC_RED_BLUE1_ENABLE
  8485. #endif /* MRV_DPCC_LC_RED_BLUE1_ENABLE */
  8486. /* Slice: PG_RED_BLUE1_ENABLE:*/
  8487. /* 1: enable Peak Gradient check for red_blue *Default**/
  8488. /* 0: bypass Peak Gradient check for red_blue */
  8489. #ifdef MRV_DPCC_PG_RED_BLUE1_ENABLE
  8490. #endif /* MRV_DPCC_PG_RED_BLUE1_ENABLE */
  8491. /* Slice: RG_GREEN1_ENABLE:*/
  8492. /* 1: enable Rank Gradient check for green *Default**/
  8493. /* 0: bypass Rank Gradient check for green */
  8494. #ifdef MRV_DPCC_RG_GREEN1_ENABLE
  8495. #endif /* MRV_DPCC_RG_GREEN1_ENABLE */
  8496. /* Slice: RND_GREEN1_ENABLE:*/
  8497. /* 1: enable Rank Neighbor Difference check for green *Default**/
  8498. /* 0: bypass Rank Neighbor Difference check for green */
  8499. #ifdef MRV_DPCC_RND_GREEN1_ENABLE
  8500. #endif /* MRV_DPCC_RND_GREEN1_ENABLE */
  8501. /* Slice: RO_GREEN1_ENABLE:*/
  8502. /* 1: enable Rank Order check for green *Default**/
  8503. /* 0: bypass Rank Order check for green */
  8504. #ifdef MRV_DPCC_RO_GREEN1_ENABLE
  8505. #endif /* MRV_DPCC_RO_GREEN1_ENABLE */
  8506. /* Slice: LC_GREEN1_ENABLE:*/
  8507. /* 1: enable Line check for green *Default**/
  8508. /* 0: bypass Line check for green */
  8509. #ifdef MRV_DPCC_LC_GREEN1_ENABLE
  8510. #endif /* MRV_DPCC_LC_GREEN1_ENABLE */
  8511. /* Slice: PG_GREEN1_ENABLE:*/
  8512. /* 1: enable Peak Gradient check for green *Default**/
  8513. /* 0: bypass Peak Gradient check for green */
  8514. #ifdef MRV_DPCC_PG_GREEN1_ENABLE
  8515. #endif /* MRV_DPCC_PG_GREEN1_ENABLE */
  8516. /*****************************************************************************/
  8517. /**
  8518. * register: isp_dpcc_methods_set_2: Methods enable bits for SET_2
  8519. * (0x00000010)
  8520. *
  8521. *****************************************************************************/
  8522. /* Slice: RG_RED_BLUE2_ENABLE:*/
  8523. /* 1: enable Rank Gradient check for red_blue *Default**/
  8524. /* 0: bypass Rank Gradient check for red_blue */
  8525. #ifdef MRV_DPCC_RG_RED_BLUE2_ENABLE
  8526. #endif /* MRV_DPCC_RG_RED_BLUE2_ENABLE */
  8527. /* Slice: RND_RED_BLUE2_ENABLE:*/
  8528. /* 1: enable Rank Neighbor Difference check for red_blue *Default**/
  8529. /* 0: bypass Rank Neighbor Difference check for red_blue */
  8530. #ifdef MRV_DPCC_RND_RED_BLUE2_ENABLE
  8531. #endif /* MRV_DPCC_RND_RED_BLUE2_ENABLE */
  8532. /* Slice: RO_RED_BLUE2_ENABLE:*/
  8533. /* 1: enable Rank Order check for red_blue *Default**/
  8534. /* 0: bypass Rank Order check for red_blue */
  8535. #ifdef MRV_DPCC_RO_RED_BLUE2_ENABLE
  8536. #endif /* MRV_DPCC_RO_RED_BLUE2_ENABLE */
  8537. /* Slice: LC_RED_BLUE2_ENABLE:*/
  8538. /* 1: enable Line check for red_blue *Default**/
  8539. /* 0: bypass Line check for red_blue */
  8540. #ifdef MRV_DPCC_LC_RED_BLUE2_ENABLE
  8541. #endif /* MRV_DPCC_LC_RED_BLUE2_ENABLE */
  8542. /* Slice: PG_RED_BLUE2_ENABLE:*/
  8543. /* 1: enable Peak Gradient check for red_blue *Default**/
  8544. /* 0: bypass Peak Gradient check for red_blue */
  8545. #ifdef MRV_DPCC_PG_RED_BLUE2_ENABLE
  8546. #endif /* MRV_DPCC_PG_RED_BLUE2_ENABLE */
  8547. /* Slice: RG_GREEN2_ENABLE:*/
  8548. /* 1: enable Rank Gradient check for green *Default**/
  8549. /* 0: bypass Rank Gradient check for green */
  8550. #ifdef MRV_DPCC_RG_GREEN2_ENABLE
  8551. #endif /* MRV_DPCC_RG_GREEN2_ENABLE */
  8552. /* Slice: RND_GREEN2_ENABLE:*/
  8553. /* 1: enable Rank Neighbor Difference check for green *Default**/
  8554. /* 0: bypass Rank Neighbor Difference check for green */
  8555. #ifdef MRV_DPCC_RND_GREEN2_ENABLE
  8556. #endif /* MRV_DPCC_RND_GREEN2_ENABLE */
  8557. /* Slice: RO_GREEN2_ENABLE:*/
  8558. /* 1: enable Rank Order check for green *Default**/
  8559. /* 0: bypass Rank Order check for green */
  8560. #ifdef MRV_DPCC_RO_GREEN2_ENABLE
  8561. #endif /* MRV_DPCC_RO_GREEN2_ENABLE */
  8562. /* Slice: LC_GREEN2_ENABLE:*/
  8563. /* 1: enable Line check for green *Default**/
  8564. /* 0: bypass Line check for green */
  8565. #ifdef MRV_DPCC_LC_GREEN2_ENABLE
  8566. #endif /* MRV_DPCC_LC_GREEN2_ENABLE */
  8567. /* Slice: PG_GREEN2_ENABLE:*/
  8568. /* 1: enable Peak Gradient check for green *Default**/
  8569. /* 0: bypass Peak Gradient check for green */
  8570. #ifdef MRV_DPCC_PG_GREEN2_ENABLE
  8571. #endif /* MRV_DPCC_PG_GREEN2_ENABLE */
  8572. /*****************************************************************************/
  8573. /**
  8574. * register: isp_dpcc_methods_set_3: Methods enable bits for SET_3
  8575. * (0x00000014)
  8576. *
  8577. *****************************************************************************/
  8578. /* Slice: RG_RED_BLUE3_ENABLE:*/
  8579. /* 1: enable Rank Gradient check for red_blue *Default**/
  8580. /* 0: bypass Rank Gradient check for red_blue */
  8581. #ifdef MRV_DPCC_RG_RED_BLUE3_ENABLE
  8582. #endif /* MRV_DPCC_RG_RED_BLUE3_ENABLE */
  8583. /* Slice: RND_RED_BLUE3_ENABLE:*/
  8584. /* 1: enable Rank Neighbor Difference check for red_blue *Default**/
  8585. /* 0: bypass Rank Neighbor Difference check for red_blue */
  8586. #ifdef MRV_DPCC_RND_RED_BLUE3_ENABLE
  8587. #endif /* MRV_DPCC_RND_RED_BLUE3_ENABLE */
  8588. /* Slice: RO_RED_BLUE3_ENABLE:*/
  8589. /* 1: enable Rank Order check for red_blue *Default**/
  8590. /* 0: bypass Rank Order check for red_blue */
  8591. #ifdef MRV_DPCC_RO_RED_BLUE3_ENABLE
  8592. #endif /* MRV_DPCC_RO_RED_BLUE3_ENABLE */
  8593. /* Slice: LC_RED_BLUE3_ENABLE:*/
  8594. /* 1: enable Line check for red_blue *Default**/
  8595. /* 0: bypass Line check for red_blue */
  8596. #ifdef MRV_DPCC_LC_RED_BLUE3_ENABLE
  8597. #endif /* MRV_DPCC_LC_RED_BLUE3_ENABLE */
  8598. /* Slice: PG_RED_BLUE3_ENABLE:*/
  8599. /* 1: enable Peak Gradient check for red_blue *Default**/
  8600. /* 0: bypass Peak Gradient check for red_blue */
  8601. #ifdef MRV_DPCC_PG_RED_BLUE3_ENABLE
  8602. #endif /* MRV_DPCC_PG_RED_BLUE3_ENABLE */
  8603. /* Slice: RG_GREEN3_ENABLE:*/
  8604. /* 1: enable Rank Gradient check for green *Default**/
  8605. /* 0: bypass Rank Gradient check for green */
  8606. #ifdef MRV_DPCC_RG_GREEN3_ENABLE
  8607. #endif /* MRV_DPCC_RG_GREEN3_ENABLE */
  8608. /* Slice: RND_GREEN3_ENABLE:*/
  8609. /* 1: enable Rank Neighbor Difference check for green *Default**/
  8610. /* 0: bypass Rank Neighbor Difference check for green */
  8611. #ifdef MRV_DPCC_RND_GREEN3_ENABLE
  8612. #endif /* MRV_DPCC_RND_GREEN3_ENABLE */
  8613. /* Slice: RO_GREEN3_ENABLE:*/
  8614. /* 1: enable Rank Order check for green *Default**/
  8615. /* 0: bypass Rank Order check for green */
  8616. #ifdef MRV_DPCC_RO_GREEN3_ENABLE
  8617. #endif /* MRV_DPCC_RO_GREEN3_ENABLE */
  8618. /* Slice: LC_GREEN3_ENABLE:*/
  8619. /* 1: enable Line check for green *Default**/
  8620. /* 0: bypass Line check for green */
  8621. #ifdef MRV_DPCC_LC_GREEN3_ENABLE
  8622. #endif /* MRV_DPCC_LC_GREEN3_ENABLE */
  8623. /* Slice: PG_GREEN3_ENABLE:*/
  8624. /* 1: enable Peak Gradient check for green *Default**/
  8625. /* 0: bypass Peak Gradient check for green */
  8626. #ifdef MRV_DPCC_PG_GREEN3_ENABLE
  8627. #endif /* MRV_DPCC_PG_GREEN3_ENABLE */
  8628. /*****************************************************************************/
  8629. /**
  8630. * register: isp_dpcc_line_thresh_1: Line threshold SET_1 (0x00000018)
  8631. *
  8632. *****************************************************************************/
  8633. /* Slice: LINE_THR_1_RB:*/
  8634. /* line threshold for set 1 red/blue */
  8635. #ifdef MRV_DPCC_LINE_THR_1_RB
  8636. #endif /* MRV_DPCC_LINE_THR_1_RB */
  8637. /* Slice: LINE_THR_1_G:*/
  8638. /* line threshold for set 1 green */
  8639. #ifdef MRV_DPCC_LINE_THR_1_G
  8640. #endif /* MRV_DPCC_LINE_THR_1_G */
  8641. /*****************************************************************************/
  8642. /**
  8643. * register: isp_dpcc_line_mad_fac_1: Mean Absolute Difference (MAD) factor
  8644. * for Line check set 1 (0x0000001c)
  8645. *
  8646. *****************************************************************************/
  8647. /* Slice: LINE_MAD_FAC_1_RB:*/
  8648. /* line MAD factor for set 1 red/blue */
  8649. #ifdef MRV_DPCC_LINE_MAD_FAC_1_RB
  8650. #endif /* MRV_DPCC_LINE_MAD_FAC_1_RB */
  8651. /* Slice: LINE_MAD_FAC_1_G:*/
  8652. /* line MAD factor for set 1 green */
  8653. #ifdef MRV_DPCC_LINE_MAD_FAC_1_G
  8654. #endif /* MRV_DPCC_LINE_MAD_FAC_1_G */
  8655. /*****************************************************************************/
  8656. /**
  8657. * register: isp_dpcc_pg_fac_1: Peak gradient factor for set 1 (0x00000020)
  8658. *
  8659. *****************************************************************************/
  8660. /* Slice: PG_FAC_1_RB:*/
  8661. /* Peak gradient factor for set 1 red/blue */
  8662. #ifdef MRV_DPCC_PG_FAC_1_RB
  8663. #endif /* MRV_DPCC_PG_FAC_1_RB */
  8664. /* Slice: PG_FAC_1_G:*/
  8665. /* Peak gradient factor for set 1 green */
  8666. #ifdef MRV_DPCC_PG_FAC_1_G
  8667. #endif /* MRV_DPCC_PG_FAC_1_G */
  8668. /*****************************************************************************/
  8669. /**
  8670. * register: isp_dpcc_rnd_thresh_1: Rank Neighbor Difference threshold for
  8671. * set 1 (0x00000024)
  8672. *
  8673. *****************************************************************************/
  8674. /* Slice: RND_THR_1_RB:*/
  8675. /* Rank Neighbor Difference threshold for set 1 red/blue */
  8676. #ifdef MRV_DPCC_RND_THR_1_RB
  8677. #endif /* MRV_DPCC_RND_THR_1_RB */
  8678. /* Slice: RND_THR_1_G:*/
  8679. /* Rank Neighbor Difference threshold for set 1 green */
  8680. #ifdef MRV_DPCC_RND_THR_1_G
  8681. #endif /* MRV_DPCC_RND_THR_1_G */
  8682. /*****************************************************************************/
  8683. /**
  8684. * register: isp_dpcc_rg_fac_1: Rank gradient factor for set 1 (0x00000028)
  8685. *
  8686. *****************************************************************************/
  8687. /* Slice: RG_FAC_1_RB:*/
  8688. /* Rank gradient factor for set 1 red/blue */
  8689. #ifdef MRV_DPCC_RG_FAC_1_RB
  8690. #endif /* MRV_DPCC_RG_FAC_1_RB */
  8691. /* Slice: RG_FAC_1_G:*/
  8692. /* Rank gradient factor for set 1 green */
  8693. #ifdef MRV_DPCC_RG_FAC_1_G
  8694. #endif /* MRV_DPCC_RG_FAC_1_G */
  8695. /*****************************************************************************/
  8696. /**
  8697. * register: isp_dpcc_line_thresh_2: Line threshold SET_2 (0x0000002C)
  8698. *
  8699. *****************************************************************************/
  8700. /* Slice: LINE_THR_2_RB:*/
  8701. /* line threshold for set 1 red/blue */
  8702. #ifdef MRV_DPCC_LINE_THR_2_RB
  8703. #endif /* MRV_DPCC_LINE_THR_2_RB */
  8704. /* Slice: LINE_THR_2_G:*/
  8705. /* line threshold for set 1 green */
  8706. #ifdef MRV_DPCC_LINE_THR_2_G
  8707. #endif /* MRV_DPCC_LINE_THR_2_G */
  8708. /*****************************************************************************/
  8709. /**
  8710. * register: isp_dpcc_line_mad_fac_2: Mean Absolute Difference (MAD) factor
  8711. * for Line check set 1 (0x00000030)
  8712. *
  8713. *****************************************************************************/
  8714. /* Slice: LINE_MAD_FAC_2_RB:*/
  8715. /* line MAD factor for set 1 red/blue */
  8716. #ifdef MRV_DPCC_LINE_MAD_FAC_2_RB
  8717. #endif /* MRV_DPCC_LINE_MAD_FAC_2_RB */
  8718. /* Slice: LINE_MAD_FAC_2_G:*/
  8719. /* line MAD factor for set 1 green */
  8720. #ifdef MRV_DPCC_LINE_MAD_FAC_2_G
  8721. #endif /* MRV_DPCC_LINE_MAD_FAC_2_G */
  8722. /*****************************************************************************/
  8723. /**
  8724. * register: isp_dpcc_pg_fac_2: Peak gradient factor for set 1 (0x00000034)
  8725. *
  8726. *****************************************************************************/
  8727. /* Slice: PG_FAC_2_RB:*/
  8728. /* Peak gradient factor for set 1 red/blue */
  8729. #ifdef MRV_DPCC_PG_FAC_2_RB
  8730. #endif /* MRV_DPCC_PG_FAC_2_RB */
  8731. /* Slice: PG_FAC_2_G:*/
  8732. /* Peak gradient factor for set 1 green */
  8733. #ifdef MRV_DPCC_PG_FAC_2_G
  8734. #endif /* MRV_DPCC_PG_FAC_2_G */
  8735. /*****************************************************************************/
  8736. /**
  8737. * register: isp_dpcc_rnd_thresh_2: Rank Neighbor Difference threshold for
  8738. * set 1 (0x00000038)
  8739. *
  8740. *****************************************************************************/
  8741. /* Slice: RND_THR_2_RB:*/
  8742. /* Rank Neighbor Difference threshold for set 1 red/blue */
  8743. #ifdef MRV_DPCC_RND_THR_2_RB
  8744. #endif /* MRV_DPCC_RND_THR_2_RB */
  8745. /* Slice: RND_THR_2_G:*/
  8746. /* Rank Neighbor Difference threshold for set 1 green */
  8747. #ifdef MRV_DPCC_RND_THR_2_G
  8748. #endif /* MRV_DPCC_RND_THR_2_G */
  8749. /*****************************************************************************/
  8750. /**
  8751. * register: isp_dpcc_rg_fac_2: Rank gradient factor for set 1 (0x0000003C)
  8752. *
  8753. *****************************************************************************/
  8754. /* Slice: RG_FAC_2_RB:*/
  8755. /* Rank gradient factor for set 1 red/blue */
  8756. #ifdef MRV_DPCC_RG_FAC_2_RB
  8757. #endif /* MRV_DPCC_RG_FAC_2_RB */
  8758. /* Slice: RG_FAC_2_G:*/
  8759. /* Rank gradient factor for set 1 green */
  8760. #ifdef MRV_DPCC_RG_FAC_2_G
  8761. #endif /* MRV_DPCC_RG_FAC_2_G */
  8762. /*****************************************************************************/
  8763. /**
  8764. * register: isp_dpcc_line_thresh_3: Line threshold SET_3 (0x00000040)
  8765. *
  8766. *****************************************************************************/
  8767. /* Slice: LINE_THR_3_RB:*/
  8768. /* line threshold for set 1 red/blue */
  8769. #ifdef MRV_DPCC_LINE_THR_3_RB
  8770. #endif /* MRV_DPCC_LINE_THR_3_RB */
  8771. /* Slice: LINE_THR_3_G:*/
  8772. /* line threshold for set 1 green */
  8773. #ifdef MRV_DPCC_LINE_THR_3_G
  8774. #endif /* MRV_DPCC_LINE_THR_3_G */
  8775. /*****************************************************************************/
  8776. /**
  8777. * register: isp_dpcc_line_mad_fac_3: Mean Absolute Difference (MAD) factor
  8778. * for Line check set 1 (0x00000044)
  8779. *
  8780. *****************************************************************************/
  8781. /* Slice: LINE_MAD_FAC_3_RB:*/
  8782. /* line MAD factor for set 1 red/blue */
  8783. #ifdef MRV_DPCC_LINE_MAD_FAC_3_RB
  8784. #endif /* MRV_DPCC_LINE_MAD_FAC_3_RB */
  8785. /* Slice: LINE_MAD_FAC_3_G:*/
  8786. /* line MAD factor for set 1 green */
  8787. #ifdef MRV_DPCC_LINE_MAD_FAC_3_G
  8788. #endif /* MRV_DPCC_LINE_MAD_FAC_3_G */
  8789. /*****************************************************************************/
  8790. /**
  8791. * register: isp_dpcc_pg_fac_3: Peak gradient factor for set 1 (0x00000048)
  8792. *
  8793. *****************************************************************************/
  8794. /* Slice: PG_FAC_3_RB:*/
  8795. /* Peak gradient factor for set 1 red/blue */
  8796. #ifdef MRV_DPCC_PG_FAC_3_RB
  8797. #endif /* MRV_DPCC_PG_FAC_3_RB */
  8798. /* Slice: PG_FAC_3_G:*/
  8799. /* Peak gradient factor for set 1 green */
  8800. #ifdef MRV_DPCC_PG_FAC_3_G
  8801. #endif /* MRV_DPCC_PG_FAC_3_G */
  8802. /*****************************************************************************/
  8803. /**
  8804. * register: isp_dpcc_rnd_thresh_3: Rank Neighbor Difference threshold for
  8805. * set 1 (0x0000004C)
  8806. *
  8807. *****************************************************************************/
  8808. /* Slice: RND_THR_3_RB:*/
  8809. /* Rank Neighbor Difference threshold for set 1 red/blue */
  8810. #ifdef MRV_DPCC_RND_THR_3_RB
  8811. #endif /* MRV_DPCC_RND_THR_3_RB */
  8812. /* Slice: RND_THR_3_G:*/
  8813. /* Rank Neighbor Difference threshold for set 1 green */
  8814. #ifdef MRV_DPCC_RND_THR_3_G
  8815. #endif /* MRV_DPCC_RND_THR_3_G */
  8816. /*****************************************************************************/
  8817. /**
  8818. * register: isp_dpcc_rg_fac_3: Rank gradient factor for set 1 (0x00000050)
  8819. *
  8820. *****************************************************************************/
  8821. /* Slice: RG_FAC_3_RB:*/
  8822. /* Rank gradient factor for set 1 red/blue */
  8823. #ifdef MRV_DPCC_RG_FAC_3_RB
  8824. #endif /* MRV_DPCC_RG_FAC_3_RB */
  8825. /* Slice: RG_FAC_3_G:*/
  8826. /* Rank gradient factor for set 1 green */
  8827. #ifdef MRV_DPCC_RG_FAC_3_G
  8828. #endif /* MRV_DPCC_RG_FAC_3_G */
  8829. /*****************************************************************************/
  8830. /**
  8831. * register: isp_dpcc_ro_limits: Rank Order Limits (0x00000054)
  8832. *
  8833. *****************************************************************************/
  8834. /* Slice: RO_LIM_3_RB:*/
  8835. /* Rank order limit for set 3 red/blue */
  8836. #ifdef MRV_DPCC_RO_LIM_3_RB
  8837. #endif /* MRV_DPCC_RO_LIM_3_RB */
  8838. /* Slice: RO_LIM_3_G:*/
  8839. /* Rank order limit for set 3 green */
  8840. #ifdef MRV_DPCC_RO_LIM_3_G
  8841. #endif /* MRV_DPCC_RO_LIM_3_G */
  8842. /* Slice: RO_LIM_2_RB:*/
  8843. /* Rank order limit for set 2 red/blue */
  8844. #ifdef MRV_DPCC_RO_LIM_2_RB
  8845. #endif /* MRV_DPCC_RO_LIM_2_RB */
  8846. /* Slice: RO_LIM_2_G:*/
  8847. /* Rank order limit for set 2 green */
  8848. #ifdef MRV_DPCC_RO_LIM_2_G
  8849. #endif /* MRV_DPCC_RO_LIM_2_G */
  8850. /* Slice: RO_LIM_1_RB:*/
  8851. /* Rank order limit for set 1 red/blue */
  8852. #ifdef MRV_DPCC_RO_LIM_1_RB
  8853. #endif /* MRV_DPCC_RO_LIM_1_RB */
  8854. /* Slice: RO_LIM_1_G:*/
  8855. /* Rank order limit for set 1 green */
  8856. #ifdef MRV_DPCC_RO_LIM_1_G
  8857. #endif /* MRV_DPCC_RO_LIM_1_G */
  8858. /*****************************************************************************/
  8859. /**
  8860. * register: isp_dpcc_rnd_offs: Differential Rank Offsets for Rank Neighbor
  8861. * Difference (0x00000058)
  8862. *
  8863. *****************************************************************************/
  8864. /* Slice: RND_OFFS_3_RB:*/
  8865. /* Rank Offset to Neighbor for set 3 red/blue */
  8866. #ifdef MRV_DPCC_RND_OFFS_3_RB
  8867. #endif /* MRV_DPCC_RND_OFFS_3_RB */
  8868. /* Slice: RND_OFFS_3_G:*/
  8869. /* Rank Offset to Neighbor for set 3 green */
  8870. #ifdef MRV_DPCC_RND_OFFS_3_G
  8871. #endif /* MRV_DPCC_RND_OFFS_3_G */
  8872. /* Slice: RND_OFFS_2_RB:*/
  8873. /* Rank Offset to Neighbor for set 2 red/blue */
  8874. #ifdef MRV_DPCC_RND_OFFS_2_RB
  8875. #endif /* MRV_DPCC_RND_OFFS_2_RB */
  8876. /* Slice: RND_OFFS_2_G:*/
  8877. /* Rank Offset to Neighbor for set 2 green */
  8878. #ifdef MRV_DPCC_RND_OFFS_2_G
  8879. #endif /* MRV_DPCC_RND_OFFS_2_G */
  8880. /* Slice: RND_OFFS_1_RB:*/
  8881. /* Rank Offset to Neighbor for set 1 red/blue */
  8882. #ifdef MRV_DPCC_RND_OFFS_1_RB
  8883. #endif /* MRV_DPCC_RND_OFFS_1_RB */
  8884. /* Slice: RND_OFFS_1_G:*/
  8885. /* Rank Offset to Neighbor for set 1 green */
  8886. #ifdef MRV_DPCC_RND_OFFS_1_G
  8887. #endif /* MRV_DPCC_RND_OFFS_1_G */
  8888. /*****************************************************************************/
  8889. /**
  8890. * register: isp_dpcc_bpt_ctrl: bad pixel table settings (0x0000005c)
  8891. *
  8892. *****************************************************************************/
  8893. /* Slice: BPT_RB_3x3:*/
  8894. /* 1: if BPT active red/blue 9 pixel (3x3) output median */
  8895. /* 0: if BPT active red/blue 4 or 5 pixel output median *Default**/
  8896. #ifdef MRV_DPCC_BPT_RB_3X3
  8897. #endif /* MRV_DPCC_BPT_RB_3X3 */
  8898. /* Slice: BPT_G_3x3:*/
  8899. /* 1: if BPT active green 9 pixel (3x3) output median */
  8900. /* 0: if BPT active green 4 or 5 pixel output median *Default**/
  8901. #ifdef MRV_DPCC_BPT_G_3X3
  8902. #endif /* MRV_DPCC_BPT_G_3X3 */
  8903. /* Slice: BPT_INCL_RB_CENTER:*/
  8904. /* 1: if BPT active include center pixel for red/blue output median 2x2+1 */
  8905. /* 0: if BPT active do not include center pixel for red/blue output median 2x2 *Default**/
  8906. #ifdef MRV_DPCC_BPT_INCL_RB_CENTER
  8907. #endif /* MRV_DPCC_BPT_INCL_RB_CENTER */
  8908. /* Slice: BPT_INCL_GREEN_CENTER:*/
  8909. /* 1: if BPT active include center pixel for green output median 2x2+1 */
  8910. /* 0: if BPT active do not include center pixel for green output median 2x2 *Default**/
  8911. #ifdef MRV_DPCC_BPT_INCL_GREEN_CENTER
  8912. #endif /* MRV_DPCC_BPT_INCL_GREEN_CENTER */
  8913. /* Slice: BPT_USE_FIX_SET:*/
  8914. /* 1: for BPT write use hard coded methods set */
  8915. /* 0: for BPT write do not use hard coded methods set *Default**/
  8916. #ifdef MRV_DPCC_BPT_USE_FIX_SET
  8917. #endif /* MRV_DPCC_BPT_USE_FIX_SET */
  8918. /* Slice: BPT_USE_SET_3:*/
  8919. /* 1: for BPT write use methods set 3 */
  8920. /* 0: for BPT write do not use methods set 3 *Default**/
  8921. #ifdef MRV_DPCC_BPT_USE_SET_3
  8922. #endif /* MRV_DPCC_BPT_USE_SET_3 */
  8923. /* Slice: BPT_USE_SET_2:*/
  8924. /* 1: for BPT write use methods set 2 */
  8925. /* 0: for BPT write do not use methods set 2 *Default**/
  8926. #ifdef MRV_DPCC_BPT_USE_SET_2
  8927. #endif /* MRV_DPCC_BPT_USE_SET_2 */
  8928. /* Slice: BPT_USE_SET_1:*/
  8929. /* 1: for BPT write use methods set 1 */
  8930. /* 0: for BPT write do not use methods set 1 *Default**/
  8931. #ifdef MRV_DPCC_BPT_USE_SET_1
  8932. #endif /* MRV_DPCC_BPT_USE_SET_1 */
  8933. /* Slice: bpt_cor_en:*/
  8934. /* table based correction enable */
  8935. /* 1: table based correction is enabled */
  8936. /* 0: table based correction is disabled */
  8937. #ifdef MRV_DPCC_BPT_COR_EN
  8938. #endif /* MRV_DPCC_BPT_COR_EN */
  8939. /* Slice: bpt_det_en:*/
  8940. /* Bad pixel detection write enable */
  8941. /* 1: bad pixel detection write to memory is enabled */
  8942. /* 0: bad pixel detection write to memory is disabled */
  8943. #ifdef MRV_DPCC_BPT_DET_EN
  8944. #endif /* MRV_DPCC_BPT_DET_EN */
  8945. /*****************************************************************************/
  8946. /**
  8947. * register: isp_dpcc_bpt_addr: TABLE Start Address for table-based correction
  8948. * algorithm (0x00000064)
  8949. *
  8950. *****************************************************************************/
  8951. /* Slice: bp_table_addr:*/
  8952. /* Table RAM start address for read or write operations. The address counter */
  8953. /* is incremented at each read or write access to the data register (auto-*/
  8954. /* increment mechanism).*/
  8955. #ifdef MRV_DPCC_BP_TABLE_ADDR
  8956. #endif /* MRV_DPCC_BP_TABLE_ADDR */
  8957. /*****************************************************************************/
  8958. /**
  8959. * register: isp_dpcc_bpt_data: TABLE DATA register for read and write access
  8960. * of table RAM (0x00000068)
  8961. *
  8962. *****************************************************************************/
  8963. /* Slice: bpt_v_addr:*/
  8964. /* Bad Pixel vertical address (pixel position)*/
  8965. #ifdef MRV_DPCC_BPT_V_ADDR
  8966. #endif /* MRV_DPCC_BPT_V_ADDR */
  8967. /* Slice: bpt_h_addr:*/
  8968. /* Bad Pixel horizontal address (pixel position)*/
  8969. #ifdef MRV_DPCC_BPT_H_ADDR
  8970. #endif /* MRV_DPCC_BPT_H_ADDR */
  8971. /*****************************************************************************/
  8972. /* ISP Wide Dynamic Range */
  8973. /*****************************************************************************/
  8974. /*****************************************************************************/
  8975. /**
  8976. * register: isp_wdr_ctrl: Control Bits for Wide Dynamic Range Unit (0x00000000)
  8977. *
  8978. *****************************************************************************/
  8979. /* Slice: WDR_RGB_FACTOR:*/
  8980. /* rgb_factor defines how much influence the RGBmax approach has in comparison */
  8981. /* to Y. The illumination reference Iref is calculated according to the following */
  8982. /* formula:*/
  8983. /**/
  8984. /* Iref = (WDR_RGB_FACTOR * RGBYmax_tr + (8 - WDR_RGB_FACTOR) * Y) / 8 */
  8985. /**/
  8986. /* So, rgb_factor = 0 means that the standard approach is used. Use of this */
  8987. /* factor requires that Iref has been selected, see WDR_USE_IREF.*/
  8988. /**/
  8989. /* Value range of rgb_factor: 0...8 */
  8990. #ifdef MRV_WDR_RGB_FACTOR
  8991. #endif /* MRV_WDR_RGB_FACTOR */
  8992. /* Slice: WDR_DISABLE_TRANSIENT:*/
  8993. /* 1: disable transient between Y and RGBY_max */
  8994. /* 0: calculate transient between Y and RGBY_max (for noise reduction) *Default**/
  8995. /* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/
  8996. #ifdef MRV_WDR_DISABLE_TRANSIENT
  8997. #endif /* MRV_WDR_DISABLE_TRANSIENT */
  8998. /* Slice: WDR_USE_RGB7_8:*/
  8999. /* 1: decrease RGBmax by 7/8 (for noise reduction)*/
  9000. /* 0: do not modify RGBmax *Default**/
  9001. /* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/
  9002. #ifdef MRV_WDR_USE_RGB7_8
  9003. #endif /* MRV_WDR_USE_RGB7_8 */
  9004. /* Slice: WDR_USE_Y9_8:*/
  9005. /* 1: use R G B and Y*9/8 for maximum value calculation (for noise reduction)*/
  9006. /* 0: only use R G B for maximum value calculation (RGBYmax approach) *Default**/
  9007. /* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/
  9008. #ifdef MRV_WDR_USE_Y9_8
  9009. #endif /* MRV_WDR_USE_Y9_8 */
  9010. /* Slice: WDR_USE_IREF:*/
  9011. /* 1: use Iref (Illumination reference) instead of Y for ToneMapping and Gain calculation */
  9012. /* 0: use Y for ToneMapping and Gain calculation *Default**/
  9013. /* Iref is calculated according to the following formula:*/
  9014. /* Iref = (WDR_RGB_FACTOR * RGBmax_tr + (8 - WDR_RGB_FACTOR) * Y) / 8 */
  9015. #ifdef MRV_WDR_USE_IREF
  9016. #endif /* MRV_WDR_USE_IREF */
  9017. /* Slice: WDR_CR_MAPPING_DISABLE:*/
  9018. /* 1: disable (bypass) Chrominance Mapping */
  9019. /* 0: enable Chrominance Mapping *Default**/
  9020. /* requires that Luminance/chrominance color space has been selected */
  9021. #ifdef MRV_WDR_CR_MAPPING_DISABLE
  9022. #endif /* MRV_WDR_CR_MAPPING_DISABLE */
  9023. /* Slice: WDR_COLOR_SPACE_SELECT:*/
  9024. /* 1: R, G, B color space */
  9025. /* 0: Luminance/Chrominance color space *Default**/
  9026. #ifdef MRV_WDR_COLOR_SPACE_SELECT
  9027. #endif /* MRV_WDR_COLOR_SPACE_SELECT */
  9028. /* Slice: WDR_ENABLE:*/
  9029. /* 1: enable WDR */
  9030. /* 0: bypass WDR *Default**/
  9031. #ifdef MRV_WDR_ENABLE
  9032. #endif /* MRV_WDR_ENABLE */
  9033. /*****************************************************************************/
  9034. /**
  9035. * register: isp_wdr_tonecurve_1: Tone Curve sample points dYn definition
  9036. * (part 1) (0x00000004)
  9037. *
  9038. * isp_wdr_tonecurve_1_shd: Tone Curve sample points dYn definition
  9039. * shadow register (part 1) (0x000000a0)
  9040. *
  9041. *****************************************************************************/
  9042. /* Slice: WDR_dY8:*/
  9043. /* Tone curve sample point definition dY8 on the horizontal axis (input)*/
  9044. #ifdef MRV_WDR_DY8
  9045. #endif /* MRV_WDR_DY8 */
  9046. /* Slice: WDR_dY7:*/
  9047. /* Tone curve sample point definition dY7 on the horizontal axis (input)*/
  9048. #ifdef MRV_WDR_DY7
  9049. #endif /* MRV_WDR_DY7 */
  9050. /* Slice: WDR_dY6:*/
  9051. /* Tone curve sample point definition dY6 on the horizontal axis (input)*/
  9052. #ifdef MRV_WDR_DY6
  9053. #endif /* MRV_WDR_DY6 */
  9054. /* Slice: WDR_dY5:*/
  9055. /* Tone curve sample point definition dY5 on the horizontal axis (input)*/
  9056. #ifdef MRV_WDR_DY5
  9057. #endif /* MRV_WDR_DY5 */
  9058. /* Slice: WDR_dY4:*/
  9059. /* Tone curve sample point definition dY4 on the horizontal axis (input)*/
  9060. #ifdef MRV_WDR_DY4
  9061. #endif /* MRV_WDR_DY4 */
  9062. /* Slice: WDR_dY3:*/
  9063. /* Tone curve sample point definition dY3 on the horizontal axis (input)*/
  9064. #ifdef MRV_WDR_DY3
  9065. #endif /* MRV_WDR_DY3 */
  9066. /* Slice: WDR_dY2:*/
  9067. /* Tone curve sample point definition dY2 on the horizontal axis (input)*/
  9068. #ifdef MRV_WDR_DY2
  9069. #endif /* MRV_WDR_DY2 */
  9070. /* Slice: WDR_dY1:*/
  9071. /* Tone curve sample point definition dY1 on the horizontal axis (input)*/
  9072. #ifdef MRV_WDR_DY1
  9073. #endif /* MRV_WDR_DY1 */
  9074. /*****************************************************************************/
  9075. /**
  9076. * register: isp_wdr_tonecurve_2: Tone Curve sample points dYn definition
  9077. * (part 2) (0x00000008)
  9078. *
  9079. * isp_wdr_tonecurve_2_shd: Tone Curve sample points dYn definition
  9080. * shadow register (part 2) (0x000000a4)
  9081. *
  9082. *****************************************************************************/
  9083. /* Slice: WDR_dY16:*/
  9084. /* Tone curve sample point definition dY16 on the horizontal axis (input)*/
  9085. #ifdef MRV_WDR_DY16
  9086. #endif /* MRV_WDR_DY16 */
  9087. /* Slice: WDR_dY15:*/
  9088. /* Tone curve sample point definition dY15 on the horizontal axis (input)*/
  9089. #ifdef MRV_WDR_DY15
  9090. #endif /* MRV_WDR_DY15 */
  9091. /* Slice: WDR_dY14:*/
  9092. /* Tone curve sample point definition dY14 on the horizontal axis (input)*/
  9093. #ifdef MRV_WDR_DY14
  9094. #endif /* MRV_WDR_DY14 */
  9095. /* Slice: WDR_dY13:*/
  9096. /* Tone curve sample point definition dY13 on the horizontal axis (input)*/
  9097. #ifdef MRV_WDR_DY13
  9098. #endif /* MRV_WDR_DY13 */
  9099. /* Slice: WDR_dY12:*/
  9100. /* Tone curve sample point definition dY12 on the horizontal axis (input)*/
  9101. #ifdef MRV_WDR_DY12
  9102. #endif /* MRV_WDR_DY12 */
  9103. /* Slice: WDR_dY11:*/
  9104. /* Tone curve sample point definition dY11 on the horizontal axis (input)*/
  9105. #ifdef MRV_WDR_DY11
  9106. #endif /* MRV_WDR_DY11 */
  9107. /* Slice: WDR_dY10:*/
  9108. /* Tone curve sample point definition dY10 on the horizontal axis (input)*/
  9109. #ifdef MRV_WDR_DY10
  9110. #endif /* MRV_WDR_DY10 */
  9111. /* Slice: WDR_dY9:*/
  9112. /* Tone curve sample point definition dY9 on the horizontal axis (input)*/
  9113. #ifdef MRV_WDR_DY9
  9114. #endif /* MRV_WDR_DY9 */
  9115. /*****************************************************************************/
  9116. /**
  9117. * register: isp_wdr_tonecurve_3: Tone Curve sample points dYn definition
  9118. * (part 3) (0x0000000c)
  9119. *
  9120. * isp_wdr_tonecurve_3_shd: Tone Curve sample points dYn definition
  9121. * shadow register (part 3) (0x000000a8)
  9122. *
  9123. *****************************************************************************/
  9124. /* Slice: WDR_dY24:*/
  9125. /* Tone curve sample point definition dY24 on the horizontal axis (input)*/
  9126. #ifdef MRV_WDR_DY24
  9127. #endif /* MRV_WDR_DY24 */
  9128. /* Slice: WDR_dY23:*/
  9129. /* Tone curve sample point definition dY23 on the horizontal axis (input)*/
  9130. #ifdef MRV_WDR_DY23
  9131. #endif /* MRV_WDR_DY23 */
  9132. /* Slice: WDR_dY22:*/
  9133. /* Tone curve sample point definition dY22 on the horizontal axis (input)*/
  9134. #ifdef MRV_WDR_DY22
  9135. #endif /* MRV_WDR_DY22 */
  9136. /* Slice: WDR_dY21:*/
  9137. /* Tone curve sample point definition dY21 on the horizontal axis (input)*/
  9138. #ifdef MRV_WDR_DY21
  9139. #endif /* MRV_WDR_DY21 */
  9140. /* Slice: WDR_dY20:*/
  9141. /* Tone curve sample point definition dY20 on the horizontal axis (input)*/
  9142. #ifdef MRV_WDR_DY20
  9143. #endif /* MRV_WDR_DY20 */
  9144. /* Slice: WDR_dY19:*/
  9145. /* Tone curve sample point definition dY19 on the horizontal axis (input)*/
  9146. #ifdef MRV_WDR_DY19
  9147. #endif /* MRV_WDR_DY19 */
  9148. /* Slice: WDR_dY18:*/
  9149. /* Tone curve sample point definition dY18 on the horizontal axis (input)*/
  9150. #ifdef MRV_WDR_DY18
  9151. #endif /* MRV_WDR_DY18 */
  9152. /* Slice: WDR_dY17:*/
  9153. /* Tone curve sample point definition dY17 on the horizontal axis (input)*/
  9154. #ifdef MRV_WDR_DY17
  9155. #endif /* MRV_WDR_DY17 */
  9156. /*****************************************************************************/
  9157. /**
  9158. * register: isp_wdr_tonecurve_4: Tone Curve sample points dYn definition
  9159. * (part 4) (0x00000010)
  9160. *
  9161. * isp_wdr_tonecurve_4_shd: Tone Curve sample points dYn definition
  9162. * shadow register(part 4) (0x000000ac)
  9163. *
  9164. *****************************************************************************/
  9165. /* Slice: WDR_dY32:*/
  9166. /* Tone curve sample point definition dY32 on the horizontal axis (input)*/
  9167. #ifdef MRV_WDR_DY32
  9168. #endif /* MRV_WDR_DY32 */
  9169. /* Slice: WDR_dY31:*/
  9170. /* Tone curve sample point definition dY31 on the horizontal axis (input)*/
  9171. #ifdef MRV_WDR_DY31
  9172. #endif /* MRV_WDR_DY31 */
  9173. /* Slice: WDR_dY30:*/
  9174. /* Tone curve sample point definition dY30 on the horizontal axis (input)*/
  9175. #ifdef MRV_WDR_DY30
  9176. #endif /* MRV_WDR_DY30 */
  9177. /* Slice: WDR_dY29:*/
  9178. /* Tone curve sample point definition dY29 on the horizontal axis (input)*/
  9179. #ifdef MRV_WDR_DY29
  9180. #endif /* MRV_WDR_DY29 */
  9181. /* Slice: WDR_dY28:*/
  9182. /* Tone curve sample point definition dY28 on the horizontal axis (input)*/
  9183. #ifdef MRV_WDR_DY28
  9184. #endif /* MRV_WDR_DY28 */
  9185. /* Slice: WDR_dY27:*/
  9186. /* Tone curve sample point definition dY27 on the horizontal axis (input)*/
  9187. #ifdef MRV_WDR_DY27
  9188. #endif /* MRV_WDR_DY27 */
  9189. /* Slice: WDR_dY26:*/
  9190. /* Tone curve sample point definition dY26 on the horizontal axis (input)*/
  9191. #ifdef MRV_WDR_DY26
  9192. #endif /* MRV_WDR_DY26 */
  9193. /* Slice: WDR_dY25:*/
  9194. /* Tone curve sample point definition dY25 on the horizontal axis (input)*/
  9195. #ifdef MRV_WDR_DY25
  9196. #endif /* MRV_WDR_DY25 */
  9197. /*****************************************************************************/
  9198. /**
  9199. * register array: isp_wdr_tonecurve_ym: Tonemapping curve coefficient Ym_
  9200. * (0x0028 + n*0x4 (n=0..32))
  9201. *
  9202. *****************************************************************************/
  9203. /* Slice: tonecurve_ym_n:*/
  9204. /* Tone curve value definition y-axis (output) of WDR unit */
  9205. #ifdef MRV_WDR_TONECURVE_YM_N
  9206. #endif /* MRV_WDR_TONECURVE_YM_N */
  9207. /*****************************************************************************/
  9208. /**
  9209. * register: isp_wdr_offset: Offset values for RGB path (0x00000098)
  9210. *
  9211. *****************************************************************************/
  9212. /* Slice: LUM_OFFSET:*/
  9213. /* Luminance Offset value (a) for RGB operation mode */
  9214. /* unsigned 12 bit value */
  9215. #ifdef MRV_WDR_LUM_OFFSET
  9216. #endif /* MRV_WDR_LUM_OFFSET */
  9217. /* Slice: RGB_OFFSET:*/
  9218. /* RGB Offset value (b) for RGB operation mode */
  9219. /* unsigned 12 bit value */
  9220. #ifdef MRV_WDR_RGB_OFFSET
  9221. #endif /* MRV_WDR_RGB_OFFSET */
  9222. /*****************************************************************************/
  9223. /**
  9224. * register: isp_wdr_deltamin: DeltaMin Threshold and Strength factor (0x0000009c)
  9225. *
  9226. *****************************************************************************/
  9227. /* Slice: DMIN_STRENGTH:*/
  9228. /* strength factor for DMIN */
  9229. /* unsigned 5 bit value, range 0x00...0x10 */
  9230. #ifdef MRV_WDR_DMIN_STRENGTH
  9231. #endif /* MRV_WDR_DMIN_STRENGTH */
  9232. /* Slice: DMIN_THRESH:*/
  9233. /* Lower threshold for deltaMin value */
  9234. /* unsigned 12 bit value */
  9235. #ifdef MRV_WDR_DMIN_THRESH
  9236. #endif /* MRV_WDR_DMIN_THRESH */
  9237. /*****************************************************************************/
  9238. /**
  9239. * register array: isp_wdr_tonecurve_ym_shd: Tonemapping curve coefficient
  9240. * shadow register (0x0160 + n*0x4 (n=0..32))
  9241. *
  9242. *****************************************************************************/
  9243. /* Slice: tonecurve_ym_n_shd:*/
  9244. /* Tone curve value definition y-axis (output) of WDR unit */
  9245. /* shadow register.*/
  9246. #ifdef MRV_WDR_TONECURVE_YM_N_SHD
  9247. #endif /* MRV_WDR_TONECURVE_YM_N_SHD */
  9248. /*****************************************************************************/
  9249. /* ISP Elliptic Auto White Balance Registers */
  9250. /*****************************************************************************/
  9251. /*****************************************************************************/
  9252. /**
  9253. * register: awb_meas_mode: AWB Measure Mode (0x00000000)
  9254. *
  9255. *****************************************************************************/
  9256. /*! Register: awb_meas_mode: AWB Measure Mode (0x00000000)*/
  9257. /*! Slice: AWB_union_e5_and_e8:*/
  9258. /*! unite ellipse 5 with ellipse 8. Accu and count for ellipse 8.*/
  9259. #ifdef ISP_AWB_UNION_E5_AND_E8
  9260. #define ISP_AWB_UNION_E5_AND_E8_ON 1 /* 1: enable unite ellipse 5 with ellipse 8 */
  9261. #define ISP_AWB_UNION_E5_AND_E8_OFF 0 /* 0: disable unite ellipse 5 with ellipse 8 */
  9262. #endif /* ISP_AWB_UNION_E5_AND_E8 */
  9263. /*! Slice: AWB_union_e5_and_e7:*/
  9264. /*! unite ellipse 5 with ellipse 7. Accu and count for ellipse 7.*/
  9265. #ifdef ISP_AWB_UNION_E5_AND_E7
  9266. #define ISP_AWB_UNION_E5_AND_E7_ON 1 /* 1: enable unite ellipse 5 with ellipse 7 */
  9267. #define ISP_AWB_UNION_E5_AND_E7_OFF 0 /* 0: disable unite ellipse 5 with ellipse 7 */
  9268. #endif /* ISP_AWB_UNION_E5_AND_E7 */
  9269. /*! Slice: AWB_union_e5_and_e6:*/
  9270. /*! unite ellipse 5 with ellipse 6. Accu and count for ellipse 6.*/
  9271. #ifdef ISP_AWB_UNION_E5_AND_E6
  9272. #define ISP_AWB_UNION_E5_AND_E6_ON 1 /* 1: enable unite ellipse 5 with ellipse 6 */
  9273. #define ISP_AWB_UNION_E5_AND_E6_OFF 0 /* 0: disable unite ellipse 5 with ellipse 6 */
  9274. #endif /* ISP_AWB_UNION_E5_AND_E6 */
  9275. /*! Slice: AWB_union_e1_and_e4:*/
  9276. /*! unite ellipse 1 with ellipse 4. Accu and count for ellipse 4.*/
  9277. #ifdef ISP_AWB_UNION_E1_AND_E4
  9278. #define ISP_AWB_UNION_E1_AND_E4_ON 1 /* 1: enable unite ellipse 1 with ellipse 4 */
  9279. #define ISP_AWB_UNION_E1_AND_E4_OFF 0 /* 0: disable unite ellipse 1 with ellipse 4 */
  9280. #endif /* ISP_AWB_UNION_E1_AND_E4 */
  9281. /*! Slice: AWB_union_e1_and_e3:*/
  9282. /*! unite ellipse 1 with ellipse 3. Accu and count for ellipse 3.*/
  9283. #ifdef ISP_AWB_UNION_E1_AND_E3
  9284. #define ISP_AWB_UNION_E1_AND_E3_ON 1 /* 1: enable unite ellipse 1 with ellipse 3 */
  9285. #define ISP_AWB_UNION_E1_AND_E3_OFF 0 /* 0: disable unite ellipse 1 with ellipse 3 */
  9286. #endif /* ISP_AWB_UNION_E1_AND_E3 */
  9287. /*! Slice: AWB_union_e1_and_e2:*/
  9288. /*! unite ellipse 1 with ellipse 2. Accu and count for ellipse 2.*/
  9289. #ifdef ISP_AWB_UNION_E1_AND_E2
  9290. #define ISP_AWB_UNION_E1_AND_E2_ON 1 /* 1: enable unite ellipse 1 with ellipse 2 */
  9291. #define ISP_AWB_UNION_E1_AND_E2_OFF 0 /* 0: disable unite ellipse 1 with ellipse 2 */
  9292. #endif /* ISP_AWB_UNION_E1_AND_E2 */
  9293. /*! Slice: AWB_meas_chrom_switch:*/
  9294. /*! Accumulates Q1 and Q2 chromaticies instead of R, G, B color signals. Results are written on AWB_ACCU registers as well.*/
  9295. #ifdef ISP_AWB_MEAS_CHROM_SWITCH
  9296. #define ISP_AWB_MEAS_CHROM_SWITCH_ON 1 /* 1: accumulates Q1 and Q2 chromaticies */
  9297. #define ISP_AWB_MEAS_CHROM_SWITCH_OFF 0 /* 0: accumulates R, G, B color signals */
  9298. #endif /* ISP_AWB_MEAS_CHROM_SWITCH */
  9299. /* Slice: AWB_meas_irq_enable:*/
  9300. /* AWB measure done IRQ enable.*/
  9301. #ifdef ISP_AWB_MEAS_IRQ_ENABLE
  9302. #define ISP_AWB_MEAS_IRQ_ENABLE_ON 1 /* 1: enable measuring done irq */
  9303. #define ISP_AWB_MEAS_IRQ_ENABLE_OFF 0 /* 0: enable measuring done irq */
  9304. #endif /* ISP_AWB_MEAS_IRQ_ENABLE */
  9305. /* Slice: AWB_pre_filt_en:*/
  9306. /* median pre filter enable.*/
  9307. #ifdef ISP_AWB_PRE_FILT_EN
  9308. #define ISP_AWB_PRE_FILT_EN_ON 1 /* 1: enable median pre filter */
  9309. #define ISP_AWB_PRE_FILT_EN_OFF 0 /* 0: disable median pre filter */
  9310. #endif /* ISP_AWB_PRE_FILT_EN */
  9311. /* Slice: AWB_meas_en:*/
  9312. /* enable measure.*/
  9313. #ifdef ISP_AWB_MEAS_EN
  9314. #define ISP_AWB_MEAS_EN_ON 1 /* 1: enable measuring */
  9315. #define ISP_AWB_MEAS_EN_OFF 0 /* 0: disable measuring */
  9316. #endif /* ISP_AWB_MEAS_EN */
  9317. /*****************************************************************************/
  9318. /**
  9319. * register: awb_meas_h_offs: AWB window horizontal offset (0x00000004)
  9320. *
  9321. *****************************************************************************/
  9322. /* Slice: AWB_h_offset:*/
  9323. /* Horizontal offset in pixels.*/
  9324. #ifdef ISP_AWB_H_OFFSET
  9325. #define ISP_AWB_H_OFFSET_MIN 0U
  9326. #define ISP_AWB_H_OFFSET_MAX (ISP_AWB_H_OFFSET_MASK >> ISP_AWB_H_OFFSET_SHIFT)
  9327. #endif /* ISP_AWB_H_OFFSET */
  9328. /*****************************************************************************/
  9329. /**
  9330. * register: awb_meas_v_offs: AWB window vertical offset (0x00000008)
  9331. *
  9332. *****************************************************************************/
  9333. /* Slice: AWB_v_offset:*/
  9334. /* Vertical offset in pixels.*/
  9335. #ifdef ISP_AWB_V_OFFSET
  9336. #define ISP_AWB_V_OFFSET_MIN 0U
  9337. #define ISP_AWB_V_OFFSET_MAX (ISP_AWB_V_OFFSET_MASK >> ISP_AWB_V_OFFSET_SHIFT)
  9338. #endif /* ISP_AWB_V_OFFSET */
  9339. /*****************************************************************************/
  9340. /**
  9341. * register: awb_meas_h_size: Horizontal window size (0x0000000c)
  9342. *
  9343. *****************************************************************************/
  9344. /* Slice: AWB_h_size:*/
  9345. /* Horizontal size in pixels.*/
  9346. #ifdef ISP_AWB_H_SIZE
  9347. #define ISP_AWB_H_SIZE_MIN 0U
  9348. #define ISP_AWB_H_SIZE_MAX (ISP_AWB_H_SIZE_MASK >> ISP_AWB_H_SIZE_SHIFT)
  9349. #endif /* ISP_AWB_H_SIZE */
  9350. /*****************************************************************************/
  9351. /**
  9352. * register: awb_meas_v_size: Vertical window size (0x00000010)
  9353. *
  9354. *****************************************************************************/
  9355. /* Slice: AWB_v_size:*/
  9356. /* Vertical size.*/
  9357. #ifdef ISP_AWB_V_SIZE
  9358. #define ISP_AWB_V_SIZE_MIN 0U
  9359. #define ISP_AWB_V_SIZE_MAX (ISP_AWB_V_SIZE_MASK >> ISP_AWB_V_SIZE_SHIFT)
  9360. #endif /* ISP_AWB_V_SIZE */
  9361. /*****************************************************************************/
  9362. /**
  9363. * register: awb_meas_r_min_max: Min Max Compare Red (0x00000014)
  9364. *
  9365. *****************************************************************************/
  9366. /* Slice: r_max:*/
  9367. /* max red value */
  9368. #ifdef ISP_AWB_R_MAX
  9369. #endif /* ISP_AWB_R_MAX */
  9370. /* Slice: r_min:*/
  9371. /* min red value */
  9372. #ifdef ISP_AWB_R_MIN
  9373. #endif /* ISP_AWB_R_MIN */
  9374. /*****************************************************************************/
  9375. /**
  9376. * register: awb_meas_g_min_max: Min Max Compare Green (0x00000018)
  9377. *
  9378. *****************************************************************************/
  9379. /* Slice: g_max:*/
  9380. /* max green value */
  9381. #ifdef ISP_AWB_G_MAX
  9382. #endif /* ISP_AWB_G_MAX */
  9383. /* Slice: g_min:*/
  9384. /* min green value */
  9385. #ifdef ISP_AWB_G_MIN
  9386. #endif /* ISP_AWB_G_MIN */
  9387. /*****************************************************************************/
  9388. /**
  9389. * register: awb_meas_b_min_max: Min Max Compare Blue (0x0000001c)
  9390. *
  9391. *****************************************************************************/
  9392. /* Slice: b_max:*/
  9393. /* max blue value */
  9394. #ifdef ISP_AWB_B_MAX
  9395. #endif /* ISP_AWB_B_MAX */
  9396. /*! Slice: b_min:*/
  9397. /*! min blue value */
  9398. #ifdef ISP_AWB_B_MIN
  9399. #endif /* ISP_AWB_B_MIN */
  9400. /*****************************************************************************/
  9401. /**
  9402. * register: awb_meas_divider_min: Min Compare Divider (0x00000020)
  9403. *
  9404. *****************************************************************************/
  9405. /* Slice: div_min:*/
  9406. /* min divider value unsigned integer with 10 fractional Bits range 0 to 0.999 */
  9407. #ifdef ISP_AWB_DIV_MIN
  9408. #endif /* ISP_AWB_DIV_MIN */
  9409. /*****************************************************************************/
  9410. /**
  9411. * register: awb_meas_csc_coeff_0: Color conversion coefficient 0 (0x00000024)
  9412. *
  9413. *****************************************************************************/
  9414. /* Slice: cc_coeff_0:*/
  9415. /* coefficient 0 for color space conversion */
  9416. #ifdef ISP_AWB_CC_COEFF_0
  9417. #endif /* ISP_AWB_CC_COEFF_0 */
  9418. /*****************************************************************************/
  9419. /**
  9420. * register: awb_meas_csc_coeff_1: Color conversion coefficient 1 (0x00000028)
  9421. *
  9422. *****************************************************************************/
  9423. /* Slice: cc_coeff_1:*/
  9424. /* coefficient 1 for color space conversion */
  9425. #ifdef ISP_AWB_CC_COEFF_1
  9426. #endif /* ISP_AWB_CC_COEFF_1 */
  9427. /*****************************************************************************/
  9428. /**
  9429. * register: awb_meas_csc_coeff_2: Color conversion coefficient 2 (0x0000002c)
  9430. *
  9431. *****************************************************************************/
  9432. /* Slice: cc_coeff_2:*/
  9433. /* coefficient 2 for color space conversion */
  9434. #ifdef ISP_AWB_CC_COEFF_2
  9435. #endif /* ISP_AWB_CC_COEFF_2 */
  9436. /*****************************************************************************/
  9437. /**
  9438. * register: awb_meas_csc_coeff_3: Color conversion coefficient 3 (0x00000030)
  9439. *
  9440. *****************************************************************************/
  9441. /* Slice: cc_coeff_3:*/
  9442. /* coefficient 3 for color space conversion */
  9443. #ifdef ISP_AWB_CC_COEFF_3
  9444. #endif /* ISP_AWB_CC_COEFF_3 */
  9445. /*****************************************************************************/
  9446. /**
  9447. * register: awb_meas_csc_coeff_4: Color conversion coefficient 4 (0x00000034)
  9448. *
  9449. *****************************************************************************/
  9450. /* Slice: cc_coeff_4:*/
  9451. /* coefficient 4 for color space conversion */
  9452. #ifdef ISP_AWB_CC_COEFF_4
  9453. #endif /* ISP_AWB_CC_COEFF_4 */
  9454. /*****************************************************************************/
  9455. /**
  9456. * register: awb_meas_csc_coeff_5: Color conversion coefficient 5 (0x00000038)
  9457. *
  9458. *****************************************************************************/
  9459. /* Slice: cc_coeff_5:*/
  9460. /* coefficient 5 for color space conversion */
  9461. #ifdef ISP_AWB_CC_COEFF_5
  9462. #endif /* ISP_AWB_CC_COEFF_5 */
  9463. /*****************************************************************************/
  9464. /**
  9465. * register: awb_meas_csc_coeff_6: Color conversion coefficient 6 (0x0000003c)
  9466. *
  9467. *****************************************************************************/
  9468. /* Slice: cc_coeff_6:*/
  9469. /* coefficient 6 for color space conversion */
  9470. #ifdef ISP_AWB_CC_COEFF_6
  9471. #endif /* ISP_AWB_CC_COEFF_6 */
  9472. /*****************************************************************************/
  9473. /**
  9474. * register: awb_meas_csc_coeff_7: Color conversion coefficient 7 (0x00000040)
  9475. *
  9476. *****************************************************************************/
  9477. /* Slice: cc_coeff_7:*/
  9478. /* coefficient 7 for color space conversion */
  9479. #ifdef ISP_AWB_CC_COEFF_7
  9480. #endif /* ISP_AWB_CC_COEFF_7 */
  9481. /*****************************************************************************/
  9482. /**
  9483. * register: awb_meas_csc_coeff_8: Color conversion coefficient 8 (0x00000044)
  9484. *
  9485. *****************************************************************************/
  9486. /* Slice: cc_coeff_8:*/
  9487. /* coefficient 8 for color space conversion */
  9488. #ifdef ISP_AWB_CC_COEFF_8
  9489. #endif /* ISP_AWB_CC_COEFF_8 */
  9490. /*****************************************************************************/
  9491. /**
  9492. * register: awb_meas_ellip1_cen_x: Ellipse 1 Center X (0x00000048)
  9493. *
  9494. *****************************************************************************/
  9495. /* Slice: ellip1_cen_x:*/
  9496. /* Ellipse 1 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9497. #ifdef ISP_AWB_ELLIP1_CEN_X
  9498. #endif /* ISP_AWB_ELLIP1_CEN_X */
  9499. /*****************************************************************************/
  9500. /**
  9501. * register: awb_meas_ellip1_cen_y: Ellipse 1 Center Y (0x0000004c)
  9502. *
  9503. *****************************************************************************/
  9504. /* Slice: ellip1_cen_y:*/
  9505. /* Ellipse 1 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9506. #ifdef ISP_AWB_ELLIP1_CEN_Y
  9507. #endif /* ISP_AWB_ELLIP1_CEN_Y */
  9508. /*****************************************************************************/
  9509. /**
  9510. * register: awb_meas_ellip2_cen_x: Ellipse 2 Center X (0x00000050)
  9511. *
  9512. *****************************************************************************/
  9513. /* Slice: ellip2_cen_x:*/
  9514. /* Ellipse 2 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9515. #ifdef ISP_AWB_ELLIP2_CEN_X
  9516. #endif /* ISP_AWB_ELLIP2_CEN_X */
  9517. /*****************************************************************************/
  9518. /**
  9519. * register: awb_meas_ellip2_cen_y: Ellipse 2 Center Y (0x00000054)
  9520. *
  9521. *****************************************************************************/
  9522. /* Slice: ellip2_cen_y:*/
  9523. /* Ellipse 2 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9524. #ifdef ISP_AWB_ELLIP2_CEN_Y
  9525. #endif /* ISP_AWB_ELLIP2_CEN_Y */
  9526. /*****************************************************************************/
  9527. /**
  9528. * register: awb_meas_ellip3_cen_x: Ellipse 3 Center X (0x00000058)
  9529. *
  9530. *****************************************************************************/
  9531. /* Slice: ellip3_cen_x:*/
  9532. /* Ellipse 3 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9533. #ifdef ISP_AWB_ELLIP3_CEN_X
  9534. #endif /* ISP_AWB_ELLIP3_CEN_X */
  9535. /*****************************************************************************/
  9536. /**
  9537. * register: awb_meas_ellip3_cen_y: Ellipse 3 Center Y (0x0000005c)
  9538. *
  9539. *****************************************************************************/
  9540. /* Slice: ellip3_cen_y:*/
  9541. /* Ellipse 3 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9542. #ifdef ISP_AWB_ELLIP3_CEN_Y
  9543. #endif /* ISP_AWB_ELLIP3_CEN_Y */
  9544. /*****************************************************************************/
  9545. /**
  9546. * register: awb_meas_ellip4_cen_x: Ellipse 4 Center X (0x00000060)
  9547. *
  9548. *****************************************************************************/
  9549. /* Slice: ellip4_cen_x:*/
  9550. /* Ellipse 4 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9551. #ifdef ISP_AWB_ELLIP4_CEN_X
  9552. #endif /* ISP_AWB_ELLIP4_CEN_X */
  9553. /*****************************************************************************/
  9554. /**
  9555. * register: awb_meas_ellip4_cen_y: Ellipse 4 Center Y (0x00000064)
  9556. *
  9557. *****************************************************************************/
  9558. /* Register: awb_meas_ellip4_cen_y: Ellipse 4 Center Y (0x00000064)*/
  9559. /* Slice: ellip4_cen_y:*/
  9560. /* Ellipse 4 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9561. #ifdef ISP_AWB_ELLIP4_CEN_Y
  9562. #endif /* ISP_AWB_ELLIP4_CEN_Y */
  9563. /*****************************************************************************/
  9564. /**
  9565. * register: awb_meas_ellip5_cen_x: Ellipse 5 Center X (0x00000068)
  9566. *
  9567. *****************************************************************************/
  9568. /* Slice: ellip5_cen_x:*/
  9569. /* Ellipse 5 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9570. #ifdef ISP_AWB_ELLIP5_CEN_X
  9571. #endif /* ISP_AWB_ELLIP5_CEN_X */
  9572. /*****************************************************************************/
  9573. /**
  9574. * register: awb_meas_ellip5_cen_y: Ellipse 5 Center Y (0x0000006c)
  9575. *
  9576. *****************************************************************************/
  9577. /* Slice: ellip5_cen_y:*/
  9578. /* Ellipse 5 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9579. #ifdef ISP_AWB_ELLIP5_CEN_Y
  9580. #endif /* ISP_AWB_ELLIP5_CEN_Y */
  9581. /*****************************************************************************/
  9582. /**
  9583. * register: awb_meas_ellip6_cen_x: Ellipse 6 Center X (0x00000070)
  9584. *
  9585. *****************************************************************************/
  9586. /* Slice: ellip6_cen_x:*/
  9587. /* Ellipse 6 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9588. #ifdef ISP_AWB_ELLIP6_CEN_X
  9589. #endif /* ISP_AWB_ELLIP6_CEN_X */
  9590. /*****************************************************************************/
  9591. /**
  9592. * register: awb_meas_ellip6_cen_y: Ellipse 6 Center Y (0x00000074)
  9593. *
  9594. *****************************************************************************/
  9595. /* Slice: ellip6_cen_y:*/
  9596. /* Ellipse 6 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9597. #ifdef ISP_AWB_ELLIP6_CEN_Y
  9598. #endif /* ISP_AWB_ELLIP6_CEN_Y */
  9599. /*****************************************************************************/
  9600. /**
  9601. * register: awb_meas_ellip7_cen_x: Ellipse 7 Center X (0x00000078)
  9602. *
  9603. *****************************************************************************/
  9604. /* Slice: ellip7_cen_x:*/
  9605. /* Ellipse 7 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9606. #ifdef ISP_AWB_ELLIP7_CEN_X
  9607. #endif /* ISP_AWB_ELLIP7_CEN_X */
  9608. /*****************************************************************************/
  9609. /**
  9610. * register: awb_meas_ellip7_cen_y: Ellipse 7 Center Y (0x0000007c)
  9611. *
  9612. *****************************************************************************/
  9613. /* Slice: ellip7_cen_y:*/
  9614. /* Ellipse 7 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9615. #ifdef ISP_AWB_ELLIP7_CEN_Y
  9616. #endif /* ISP_AWB_ELLIP7_CEN_Y */
  9617. /*****************************************************************************/
  9618. /**
  9619. * register: awb_meas_ellip8_cen_x: Ellipse 8 Center X (0x00000080)
  9620. *
  9621. *****************************************************************************/
  9622. /* Slice: ellip8_cen_x:*/
  9623. /* Ellipse 8 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9624. #ifdef ISP_AWB_ELLIP8_CEN_X
  9625. #endif /* ISP_AWB_ELLIP8_CEN_X */
  9626. /*****************************************************************************/
  9627. /**
  9628. * register: awb_meas_ellip8_cen_y: Ellipse 8 Center Y (0x00000084)
  9629. *
  9630. *****************************************************************************/
  9631. /* Slice: ellip8_cen_y:*/
  9632. /* Ellipse 8 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9633. #ifdef ISP_AWB_ELLIP8_CEN_Y
  9634. #endif /* ISP_AWB_ELLIP8_CEN_Y */
  9635. /*****************************************************************************/
  9636. /**
  9637. * register: awb_meas_ellip1_a1: Ellipse 1 coefficient a1 (0x00000088)
  9638. *
  9639. *****************************************************************************/
  9640. /* Slice: ellip1_a1:*/
  9641. /* Ellipse 1 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9642. #ifdef ISP_AWB_ELLIP1_A1
  9643. #endif /* ISP_AWB_ELLIP1_A1 */
  9644. /*****************************************************************************/
  9645. /**
  9646. * register: awb_meas_ellip1_a2: Ellipse 1 coefficient a2 (0x0000008c)
  9647. *
  9648. *****************************************************************************/
  9649. /* Slice: ellip1_a2:*/
  9650. /* Ellipse 1 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9651. #ifdef ISP_AWB_ELLIP1_A2
  9652. #endif /* ISP_AWB_ELLIP1_A2 */
  9653. /*****************************************************************************/
  9654. /**
  9655. * register: awb_meas_ellip1_a3: Ellipse 1 coefficient a3 (0x00000090)
  9656. *
  9657. *****************************************************************************/
  9658. /* Slice: ellip1_a3:*/
  9659. /* Ellipse 1 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9660. #ifdef ISP_AWB_ELLIP1_A3
  9661. #endif /* ISP_AWB_ELLIP1_A3 */
  9662. /*****************************************************************************/
  9663. /**
  9664. * register: awb_meas_ellip1_a4: Ellipse 1 coefficient a4 (0x00000094)
  9665. *
  9666. *****************************************************************************/
  9667. /* Slice: ellip1_a4:*/
  9668. /* Ellipse 1 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9669. #ifdef ISP_AWB_ELLIP1_A4
  9670. #endif /* ISP_AWB_ELLIP1_A4 */
  9671. /*****************************************************************************/
  9672. /**
  9673. * register: awb_meas_ellip2_a1: Ellipse 2 coefficient a1 (0x00000098)
  9674. *
  9675. *****************************************************************************/
  9676. /* Slice: ellip2_a1:*/
  9677. /* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9678. #ifdef ISP_AWB_ELLIP2_A1
  9679. #endif /* ISP_AWB_ELLIP2_A1 */
  9680. /*****************************************************************************/
  9681. /**
  9682. * register: awb_meas_ellip2_a2: Ellipse 2 coefficient a2 (0x0000009c)
  9683. *
  9684. *****************************************************************************/
  9685. /* Slice: ellip2_a2:*/
  9686. /* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9687. #ifdef ISP_AWB_ELLIP2_A2
  9688. #endif /* ISP_AWB_ELLIP2_A2 */
  9689. /*****************************************************************************/
  9690. /**
  9691. * register: awb_meas_ellip2_a3: Ellipse 2 coefficient a3 (0x000000a0)
  9692. *
  9693. *****************************************************************************/
  9694. /* Slice: ellip2_a3:*/
  9695. /* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9696. #ifdef ISP_AWB_ELLIP2_A3
  9697. #endif /* ISP_AWB_ELLIP2_A3 */
  9698. /*****************************************************************************/
  9699. /**
  9700. * register: awb_meas_ellip2_a4: Ellipse 2 coefficient a4 (0x000000a4)
  9701. *
  9702. *****************************************************************************/
  9703. /* Slice: ellip2_a4:*/
  9704. /* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9705. #ifdef ISP_AWB_ELLIP2_A4
  9706. #endif /* ISP_AWB_ELLIP2_A4 */
  9707. /*****************************************************************************/
  9708. /**
  9709. * register: awb_meas_ellip3_a1: Ellipse 3 coefficient a1 (0x000000a8)
  9710. *
  9711. *****************************************************************************/
  9712. /* Slice: ellip3_a1:*/
  9713. /* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9714. #ifdef ISP_AWB_ELLIP3_A1
  9715. #endif /* ISP_AWB_ELLIP3_A1 */
  9716. /*****************************************************************************/
  9717. /**
  9718. * register: awb_meas_ellip3_a2: Ellipse 3 coefficient a2 (0x000000ac)
  9719. *
  9720. *****************************************************************************/
  9721. /* Slice: ellip3_a2:*/
  9722. /* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9723. #ifdef ISP_AWB_ELLIP3_A2
  9724. #endif /* ISP_AWB_ELLIP3_A2 */
  9725. /*****************************************************************************/
  9726. /**
  9727. * register: awb_meas_ellip3_a3: Ellipse 3 coefficient a3 (0x000000b0)
  9728. *
  9729. *****************************************************************************/
  9730. /* Slice: ellip3_a3:*/
  9731. /* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9732. #ifdef ISP_AWB_ELLIP3_A3
  9733. #endif /* ISP_AWB_ELLIP3_A3 */
  9734. /*****************************************************************************/
  9735. /**
  9736. * register: awb_meas_ellip3_a4: Ellipse 3 coefficient a4 (0x000000b4)
  9737. *
  9738. *****************************************************************************/
  9739. /* Slice: ellip3_a4:*/
  9740. /* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9741. #ifdef ISP_AWB_ELLIP3_A4
  9742. #endif /* ISP_AWB_ELLIP3_A4 */
  9743. /*****************************************************************************/
  9744. /**
  9745. * register: awb_meas_ellip4_a1: Ellipse 4 coefficient a1 (0x000000b8)
  9746. *
  9747. *****************************************************************************/
  9748. /* Slice: ellip4_a1:*/
  9749. /* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9750. #ifdef ISP_AWB_ELLIP4_A1
  9751. #endif /* ISP_AWB_ELLIP4_A1 */
  9752. /*****************************************************************************/
  9753. /**
  9754. * register: awb_meas_ellip4_a2: Ellipse 4 coefficient a2 (0x000000bc)
  9755. *
  9756. *****************************************************************************/
  9757. /* Slice: ellip4_a2:*/
  9758. /* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9759. #ifdef ISP_AWB_ELLIP4_A2
  9760. #endif /* ISP_AWB_ELLIP4_A2 */
  9761. /*****************************************************************************/
  9762. /**
  9763. * register: awb_meas_ellip4_a3: Ellipse 4 coefficient a3 (0x000000c0)
  9764. *
  9765. *****************************************************************************/
  9766. /* Slice: ellip4_a3:*/
  9767. /* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9768. #ifdef ISP_AWB_ELLIP4_A3
  9769. #endif /* ISP_AWB_ELLIP4_A3 */
  9770. /*****************************************************************************/
  9771. /**
  9772. * register: awb_meas_ellip4_a4: Ellipse 4 coefficient a4 (0x000000c4)
  9773. *
  9774. *****************************************************************************/
  9775. /* Slice: ellip4_a4:*/
  9776. /* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9777. #ifdef ISP_AWB_ELLIP4_A4
  9778. #endif /* ISP_AWB_ELLIP4_A4 */
  9779. /*****************************************************************************/
  9780. /**
  9781. * register: awb_meas_ellip5_a1: Ellipse 5 coefficient a1 (0x000000c8)
  9782. *
  9783. *****************************************************************************/
  9784. /* Slice: ellip5_a1:*/
  9785. /* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9786. #ifdef ISP_AWB_ELLIP5_A1
  9787. #endif /* ISP_AWB_ELLIP5_A1 */
  9788. /*****************************************************************************/
  9789. /**
  9790. * register: awb_meas_ellip5_a2: Ellipse 5 coefficient a2 (0x000000cc)
  9791. *
  9792. *****************************************************************************/
  9793. /* Slice: ellip5_a2:*/
  9794. /* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9795. #ifdef ISP_AWB_ELLIP5_A2
  9796. #endif /* ISP_AWB_ELLIP5_A2 */
  9797. /*****************************************************************************/
  9798. /**
  9799. * register: awb_meas_ellip5_a3: Ellipse 5 coefficient a3 (0x000000d0)
  9800. *
  9801. *****************************************************************************/
  9802. /* Slice: ellip5_a3:*/
  9803. /* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9804. #ifdef ISP_AWB_ELLIP5_A3
  9805. #endif /* ISP_AWB_ELLIP5_A3 */
  9806. /*****************************************************************************/
  9807. /**
  9808. * register: awb_meas_ellip5_a4: Ellipse 5 coefficient a4 (0x000000d4)
  9809. *
  9810. *****************************************************************************/
  9811. /* Slice: ellip5_a4:*/
  9812. /* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9813. #ifdef ISP_AWB_ELLIP5_A4
  9814. #endif /* ISP_AWB_ELLIP5_A4 */
  9815. /*****************************************************************************/
  9816. /**
  9817. * register: awb_meas_ellip6_a1: Ellipse 6 coefficient a1 (0x000000d8)
  9818. *
  9819. *****************************************************************************/
  9820. /* Slice: ellip6_a1:*/
  9821. /* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9822. #ifdef ISP_AWB_ELLIP6_A1
  9823. #endif /* ISP_AWB_ELLIP6_A1 */
  9824. /*****************************************************************************/
  9825. /**
  9826. * register: awb_meas_ellip6_a2: Ellipse 6 coefficient a2 (0x000000dc)
  9827. *
  9828. *****************************************************************************/
  9829. /* Slice: ellip6_a2:*/
  9830. /* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9831. #ifdef ISP_AWB_ELLIP6_A2
  9832. #endif /* ISP_AWB_ELLIP6_A2 */
  9833. /*****************************************************************************/
  9834. /**
  9835. * register: awb_meas_ellip6_a3: Ellipse 6 coefficient a3 (0x000000e0)
  9836. *
  9837. *****************************************************************************/
  9838. /* Slice: ellip6_a3:*/
  9839. /* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9840. #ifdef ISP_AWB_ELLIP6_A3
  9841. #endif /* ISP_AWB_ELLIP6_A3 */
  9842. /*****************************************************************************/
  9843. /**
  9844. * register: awb_meas_ellip6_a4: Ellipse 6 coefficient a4 (0x000000e4)
  9845. *
  9846. *****************************************************************************/
  9847. /* Slice: ellip6_a4:*/
  9848. /* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9849. #ifdef ISP_AWB_ELLIP6_A4
  9850. #endif /* ISP_AWB_ELLIP6_A4 */
  9851. /*****************************************************************************/
  9852. /**
  9853. * register: awb_meas_ellip7_a1: Ellipse 7 coefficient a1 (0x000000e8)
  9854. *
  9855. *****************************************************************************/
  9856. /* Slice: ellip7_a1:*/
  9857. /* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9858. #ifdef ISP_AWB_ELLIP7_A1
  9859. #endif /* ISP_AWB_ELLIP7_A1 */
  9860. /*****************************************************************************/
  9861. /**
  9862. * register: awb_meas_ellip7_a2: Ellipse 7 coefficient a2 (0x000000ec)
  9863. *
  9864. *****************************************************************************/
  9865. /* Slice: ellip7_a2:*/
  9866. /* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9867. #ifdef ISP_AWB_ELLIP7_A2
  9868. #endif /* ISP_AWB_ELLIP7_A2 */
  9869. /*****************************************************************************/
  9870. /**
  9871. * register: awb_meas_ellip7_a3: Ellipse 7 coefficient a3 (0x000000f0)
  9872. *
  9873. *****************************************************************************/
  9874. /* Slice: ellip7_a3:*/
  9875. /* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9876. #ifdef ISP_AWB_ELLIP7_A3
  9877. #endif /* ISP_AWB_ELLIP7_A3 */
  9878. /*****************************************************************************/
  9879. /**
  9880. * register: awb_meas_ellip7_a4: Ellipse 7 coefficient a4 (0x000000f4)
  9881. *
  9882. *****************************************************************************/
  9883. /* Slice: ellip7_a4:*/
  9884. /* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9885. #ifdef ISP_AWB_ELLIP7_A4
  9886. #endif /* ISP_AWB_ELLIP7_A4 */
  9887. /*****************************************************************************/
  9888. /**
  9889. * register: awb_meas_ellip8_a1: Ellipse 8 coefficient a1 (0x000000f8)
  9890. *
  9891. *****************************************************************************/
  9892. /* Slice: ellip8_a1:*/
  9893. /* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9894. #ifdef ISP_AWB_ELLIP8_A1
  9895. #endif /* ISP_AWB_ELLIP8_A1 */
  9896. /*****************************************************************************/
  9897. /**
  9898. * register: awb_meas_ellip8_a2: Ellipse 8 coefficient a2 (0x000000fc)
  9899. *
  9900. *****************************************************************************/
  9901. /* Slice: ellip8_a2:*/
  9902. /* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9903. #ifdef ISP_AWB_ELLIP8_A2
  9904. #endif /* ISP_AWB_ELLIP8_A2 */
  9905. /*****************************************************************************/
  9906. /**
  9907. * register: awb_meas_ellip8_a3: Ellipse 8 coefficient a3 (0x00000100)
  9908. *
  9909. *****************************************************************************/
  9910. /* Slice: ellip8_a3:*/
  9911. /* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9912. #ifdef ISP_AWB_ELLIP8_A3
  9913. #endif /* ISP_AWB_ELLIP8_A3 */
  9914. /*****************************************************************************/
  9915. /**
  9916. * register: awb_meas_ellip8_a4: Ellipse 8 coefficient a4 (0x00000104)
  9917. *
  9918. *****************************************************************************/
  9919. /* Slice: ellip8_a4:*/
  9920. /* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9921. #ifdef ISP_AWB_ELLIP8_A4
  9922. #endif /* ISP_AWB_ELLIP8_A4 */
  9923. /*****************************************************************************/
  9924. /**
  9925. * register: awb_meas_ellip1_rmax: Ellipse 1 r_max (0x00000108)
  9926. *
  9927. *****************************************************************************/
  9928. /* Slice: ellip1_rmax:*/
  9929. /* Ellipse 1 max radius square compare value */
  9930. #ifdef ISP_AWB_ELLIP1_RMAX
  9931. #endif /* ISP_AWB_ELLIP1_RMAX */
  9932. /*****************************************************************************/
  9933. /**
  9934. * register: awb_meas_ellip2_rmax: Ellipse 2 r_max (0x0000010c)
  9935. *
  9936. *****************************************************************************/
  9937. /* Slice: ellip2_rmax:*/
  9938. /* Ellipse 2 max radius square compare value */
  9939. #ifdef ISP_AWB_ELLIP2_RMAX
  9940. #endif /* ISP_AWB_ELLIP2_RMAX */
  9941. /*****************************************************************************/
  9942. /**
  9943. * register: awb_meas_ellip3_rmax: Ellipse 3 r_max (0x00000110)
  9944. *
  9945. *****************************************************************************/
  9946. /* Slice: ellip3_rmax:*/
  9947. /* Ellipse 3 max radius square compare value */
  9948. #ifdef ISP_AWB_ELLIP3_RMAX
  9949. #endif /* ISP_AWB_ELLIP3_RMAX */
  9950. /*****************************************************************************/
  9951. /**
  9952. * register: awb_meas_ellip4_rmax: Ellipse 4 r_max (0x00000114)
  9953. *
  9954. *****************************************************************************/
  9955. /* Slice: ellip4_rmax:*/
  9956. /* Ellipse 4 max radius square compare value */
  9957. #ifdef ISP_AWB_ELLIP4_RMAX
  9958. #endif /* ISP_AWB_ELLIP4_RMAX */
  9959. /*****************************************************************************/
  9960. /**
  9961. * register: awb_meas_ellip5_rmax: Ellipse 5 r_max (0x00000118)
  9962. *
  9963. *****************************************************************************/
  9964. /* Slice: ellip5_rmax:*/
  9965. /* Ellipse 5 max radius square compare value */
  9966. #ifdef ISP_AWB_ELLIP5_RMAX
  9967. #endif /* ISP_AWB_ELLIP5_RMAX */
  9968. /*****************************************************************************/
  9969. /**
  9970. * register: awb_meas_ellip6_rmax: Ellipse 6 r_max (0x0000011c)
  9971. *
  9972. *****************************************************************************/
  9973. /* Slice: ellip6_rmax:*/
  9974. /* Ellipse 6 max radius square compare value */
  9975. #ifdef ISP_AWB_ELLIP6_RMAX
  9976. #endif /* ISP_AWB_ELLIP6_RMAX */
  9977. /*****************************************************************************/
  9978. /**
  9979. * register: awb_meas_ellip7_rmax: Ellipse 7 r_max (0x00000120)
  9980. *
  9981. *****************************************************************************/
  9982. /* Slice: ellip7_rmax:*/
  9983. /* Ellipse 7 max radius square compare value */
  9984. #ifdef ISP_AWB_ELLIP7_RMAX
  9985. #endif /* ISP_AWB_ELLIP7_RMAX */
  9986. /*****************************************************************************/
  9987. /**
  9988. * register: awb_meas_ellip8_rmax: Ellipse 8 r_max (0x00000124)
  9989. *
  9990. *****************************************************************************/
  9991. /* Slice: ellip8_rmax:*/
  9992. /* Ellipse 8 max radius square compare value */
  9993. #ifdef ISP_AWB_ELLIP8_RMAX
  9994. #endif /* ISP_AWB_ELLIP8_RMAX */
  9995. /*****************************************************************************/
  9996. /**
  9997. * register: awb_meas_counter_1: AWB Counter 1 (0x00000128)
  9998. *
  9999. *****************************************************************************/
  10000. /* Slice: count_1:*/
  10001. /* counted Pixels of Ellipse 1 */
  10002. #ifdef ISP_AWB_COUNT_1
  10003. #endif /* ISP_AWB_COUNT_1 */
  10004. /*****************************************************************************/
  10005. /**
  10006. * register: awb_meas_counter_2: AWB Counter 2 (0x0000012c)
  10007. *
  10008. *****************************************************************************/
  10009. /* Slice: count_2:*/
  10010. /* counted Pixels of Ellipse 2 */
  10011. #ifdef ISP_AWB_COUNT_2
  10012. #endif /* ISP_AWB_COUNT_2 */
  10013. /*****************************************************************************/
  10014. /**
  10015. * register: awb_meas_counter_3: AWB Counter 3 (0x00000130)
  10016. *
  10017. *****************************************************************************/
  10018. /* Slice: count_3:*/
  10019. /* counted Pixels of Ellipse 3 */
  10020. #ifdef ISP_AWB_COUNT_3
  10021. #endif /* ISP_AWB_COUNT_3 */
  10022. /*****************************************************************************/
  10023. /**
  10024. * register: awb_meas_counter_4: AWB Counter 4 (0x00000134)
  10025. *
  10026. *****************************************************************************/
  10027. /* Slice: count_4:*/
  10028. /* counted Pixels of Ellipse 4 */
  10029. #ifdef ISP_AWB_COUNT_4
  10030. #endif /* ISP_AWB_COUNT_4 */
  10031. /*****************************************************************************/
  10032. /**
  10033. * register: awb_meas_counter_5: AWB Counter 5 (0x00000138)
  10034. *
  10035. *****************************************************************************/
  10036. /* Slice: count_5:*/
  10037. /* counted Pixels of Ellipse 5 */
  10038. #ifdef ISP_AWB_COUNT_5
  10039. #endif /* ISP_AWB_COUNT_5 */
  10040. /*****************************************************************************/
  10041. /**
  10042. * register: awb_meas_counter_6: AWB Counter 6 (0x0000013c)
  10043. *
  10044. *****************************************************************************/
  10045. /* Slice: count_6:*/
  10046. /* counted Pixels of Ellipse 6 */
  10047. #ifdef ISP_AWB_COUNT_6
  10048. #endif /* ISP_AWB_COUNT_6 */
  10049. /*****************************************************************************/
  10050. /**
  10051. * register: awb_meas_counter_7: AWB Counter 7 (0x00000140)
  10052. *
  10053. *****************************************************************************/
  10054. /* Slice: count_7:*/
  10055. /* counted Pixels of Ellipse 7 */
  10056. #ifdef ISP_AWB_COUNT_7
  10057. #endif /* ISP_AWB_COUNT_7 */
  10058. /*****************************************************************************/
  10059. /**
  10060. * register: awb_meas_counter_8: AWB Counter 8 (0x00000144)
  10061. *
  10062. *****************************************************************************/
  10063. /* Slice: count_8:*/
  10064. /* counted Pixels of Ellipse 8 */
  10065. #ifdef ISP_AWB_COUNT_8
  10066. #endif /* ISP_AWB_COUNT_8 */
  10067. /*****************************************************************************/
  10068. /**
  10069. * register array: awb_meas_accu: AWB Accu Read (0x298 + n*0x4 (n=0..23))
  10070. *
  10071. *****************************************************************************/
  10072. /* Slice: read_accu:*/
  10073. /* measured sum[34:3] of RGB values.*/
  10074. #ifdef ISP_AWB_READ_ACCU
  10075. #endif /* ISP_AWB_READ_ACCU */
  10076. #ifdef EE_CTRL_ENABLE
  10077. #define EE_CTRL_ENABLE_SET 1
  10078. #define EE_CTRL_ENABLE_CLEAR 0
  10079. #endif
  10080. /*****************************************************************************/
  10081. /**
  10082. * register array: awb_meas_accu: AWB Accu Read (0x298 + n*0x4 (n=0..23))
  10083. *
  10084. *****************************************************************************/
  10085. /* Slice: read_accu:*/
  10086. /* measured sum[34:3] of RGB values.*/
  10087. #ifdef ISP_VSM_DELTA_H
  10088. #endif /* ISP_AWB_READ_ACCU */
  10089. /*****************************************************************************/
  10090. /**
  10091. * register: isp_vsm_h_offs: VSM window horizontal offset
  10092. *
  10093. *****************************************************************************/
  10094. /* Slice: vsm_h_offset:*/
  10095. /* Horizontal offset in pixels.*/
  10096. #ifdef ISP_VSM_H_OFFSET
  10097. #define ISP_VSM_H_OFFSET_MAX (ISP_VSM_H_OFFSET_MASK >> ISP_VSM_H_OFFSET_SHIFT)
  10098. #endif /* ISP_VSM_H_OFFSET */
  10099. /*****************************************************************************/
  10100. /**
  10101. * register: isp_vsm_v_offs: VSM window vertical offset
  10102. *
  10103. *****************************************************************************/
  10104. /* Slice: vsm_v_offset:*/
  10105. /* Vertical offset in pixels.*/
  10106. #ifdef ISP_VSM_V_OFFSET
  10107. #define ISP_VSM_V_OFFSET_MAX (ISP_VSM_V_OFFSET_MASK >> ISP_VSM_V_OFFSET_SHIFT)
  10108. #endif /* ISP_VSM_V_OFFSET */
  10109. /*****************************************************************************/
  10110. /**
  10111. * register: isp_vsm_h_size: Horizontal measure window size
  10112. *
  10113. *****************************************************************************/
  10114. /* Slice: vsm_h_size:*/
  10115. /* Horizontal size in pixels..*/
  10116. #ifdef ISP_VSM_H_SIZE
  10117. /* note: do not apply shift, since bit 0 is only excluded to get even values */
  10118. #define ISP_VSM_H_SIZE_MAX ISP_VSM_H_SIZE_MASK
  10119. #endif /* ISP_VSM_H_SIZE */
  10120. /*****************************************************************************/
  10121. /**
  10122. * register: isp_vsm_v_size: Vertical measure window size
  10123. *
  10124. *****************************************************************************/
  10125. /* Slice: vsm_v_size:*/
  10126. /* Vertical size in pixels.*/
  10127. #ifdef ISP_VSM_V_SIZE
  10128. /* note: do not apply shift, since bit 0 is only excluded to get even values */
  10129. #define ISP_VSM_V_SIZE_MAX ISP_VSM_V_SIZE_MASK
  10130. #endif /* ISP_VSM_V_SIZE */
  10131. /*****************************************************************************/
  10132. /**
  10133. * register: isp_vsm_h_segments: Iteration 1 horizontal segments
  10134. *
  10135. *****************************************************************************/
  10136. /* Slice: vsm_h_segments:*/
  10137. /* number of 16 point wide segments enclosed by the first iteration sample */
  10138. /* points in horizontal direction. Range: 1 ... 128 */
  10139. #ifdef ISP_VSM_H_SEGMENTS
  10140. #define ISP_VSM_H_SEGMENTS_MIN 1
  10141. #define ISP_VSM_H_SEGMENTS_MAX 128
  10142. #endif /* ISP_VSM_H_SEGMENTS */
  10143. /*****************************************************************************/
  10144. /**
  10145. * register: isp_vsm_v_segments: Iteration 1 vertical segments
  10146. *
  10147. *****************************************************************************/
  10148. /* Slice: vsm_v_segments:*/
  10149. /* number of 16 point wide segments enclosed by the first iteration sample */
  10150. /* points in vertical direction. Range: 1 ... 128 */
  10151. /* Note: number of 1st iteration sample points = vsm_v_segments + 1.*/
  10152. /* vsm_v_segments must be equal or smaller than vsm_h_segments.*/
  10153. #ifdef ISP_VSM_V_SEGMENTS
  10154. #define ISP_VSM_V_SEGMENTS_MIN 1
  10155. #define ISP_VSM_V_SEGMENTS_MAX 128
  10156. #endif /* ISP_VSM_V_SEGMENTS */
  10157. #ifdef ISP_GCMONO
  10158. /*****************************************************************************/
  10159. /**
  10160. * register: isp_gcmono_ctrl: gcmono enable and lut table cfg
  10161. *
  10162. *****************************************************************************/
  10163. /*! Slice: mono_gc_enable */
  10164. /*! Control of gamma correction for mono sensor RAW data */
  10165. /*! 1'b0: disable GC and enter bypass mode */
  10166. /*! 1'b1: enable GC mode */
  10167. #ifdef ISP_GCMONO_SWITCH
  10168. #define ISP_GCMONO_SWITCH_DISABLE 0 /* 0: disable GC */
  10169. #define ISP_GCMONO_SWITCH_ENABLE 1 /* 1: enable GC */
  10170. #endif
  10171. /*! Slice: mono_gc_cfg_done */
  10172. /*! To notify the ISP HW the LUT configuration is done, ready to use, active high.*/
  10173. /*! Writing ZERO reset teh internal read/write pointer and also indicates that the LUT can be configured or read from CPU.*/
  10174. #ifdef ISP_GCMONO_CFG_DONE
  10175. #define ISP_GCMONO_CFG_DONE_CURVE_READY 1 /* 1: notify ISP HW LUT configuration is done */
  10176. #define ISP_GCMONO_CFG_DONE_SET_CURVE 0 /* 0: Write ZERO reset the internal pointer and can cfg LUT. */
  10177. #endif
  10178. #ifdef ISP_GCMONO_PARA_BASE
  10179. #endif
  10180. #endif
  10181. /*****************************************************************************/
  10182. /* MIV2 Registers */
  10183. /*****************************************************************************/
  10184. /*****************************************************************************/
  10185. /**
  10186. * register: miv2_mp_fmt: main path pixel format control register (0x1314)
  10187. *
  10188. *****************************************************************************/
  10189. // Slice: MP_WR_JDP_FMT
  10190. // 1: JPEG
  10191. // 0: DPCC
  10192. #ifdef MP_WR_JDP_FMT
  10193. #define MIV2_MP_WRITE_FORMAT_DPCC 0 //DPCC
  10194. #define MIV2_MP_WRITE_FORMAT_JPEG 1 //JPEG
  10195. #endif /* MP_WR_JDP_FMT */
  10196. // Slice: MP_WR_YUV_BIT:
  10197. // 1: 10bit YUV/RGB
  10198. // 0: 8bit YUV/RGB
  10199. #ifdef MP_WR_YUV_BIT
  10200. #define MIV2_MP_WRITE_FORMAT_8BIT 0 //8bit YUV/RGB
  10201. #define MIV2_MP_WRITE_FORMAT_10BIT 1 //10bit YUV/RGB
  10202. #endif /* MP_WR_YUV_BIT */
  10203. // Slice: MP_WR_YUV_FMT:
  10204. #ifdef MP_WR_YUV_FMT
  10205. #define MIV2_MP_WRITE_FORMAT_YUV420 0 // 00: YUV420
  10206. #define MIV2_MP_WRITE_FORMAT_YUV422 1 // 01: YUV422
  10207. #define MIV2_MP_WRITE_FORMAT_YUV444 2 // 10: YUV444
  10208. #endif /* MP_WR_YUV_FMT */
  10209. // Slice: MP_WR_YUV_STR:
  10210. #ifdef MP_WR_YUV_STR
  10211. #define MIV2_MP_WRITE_STRIDE_SEMIPLANAR 0 // 00: YUV/RGB SemiPlanar
  10212. #define MIV2_MP_WRITE_STRIDE_INTERLEAVE 1 // 01: YUV Interleave, RGB Raster
  10213. #define MIV2_MP_WRITE_STRIDE_PLANAR 2 // 10: YUV/RGB Planar
  10214. #endif /* MP_WR_YUV_STR */
  10215. // Slice: MP_WR_RAW_BIT:
  10216. #ifdef MP_WR_RAW_BIT
  10217. #define MIV2_MP_WRITE_FORMAT_RAW8 0 // 000: RAW8
  10218. #define MIV2_MP_WRITE_FORMAT_RAW10 1 // 001: RAW10
  10219. #define MIV2_MP_WRITE_FORMAT_RAW12 2 // 010: RAW12
  10220. #define MIV2_MP_WRITE_FORMAT_RAW14 3 // 011: RAW14
  10221. #define MIV2_MP_WRITE_FORMAT_RAW16 4 // 100: RAW16
  10222. #define MIV2_MP_WRITE_FORMAT_RAW20 5 // 101: RAW20
  10223. #endif /* MP_WR_RAW_BIT */
  10224. // Slice: MP_WR_YUV_ALIGNED
  10225. // 1: aligned
  10226. // 0: unaligned
  10227. #ifdef MP_WR_YUV_ALIGNED
  10228. #define MIV2_MP_WRITE_YUV_UNALIGNED 0 //unaligned
  10229. #define MIV2_MP_WRITE_YUV_ALIGNED 1 //aligned
  10230. #endif /* MP_WR_YUV_ALIGNED */
  10231. // Slice: MP_WR_RAW_ALIGNED:
  10232. #ifdef MP_WR_RAW_ALIGNED
  10233. #define MIV2_MP_WRITE_RAW_UNALIGNED 0 // 00: unaligned
  10234. #define MIV2_MP_WRITE_RAW_ALIGNED_MODE1 1 // 01: aligned mode1
  10235. #define MIV2_MP_WRITE_RAW_ALIGNED_MODE2 2 // 10: aligned mode2
  10236. #endif /* MP_WR_RAW_ALIGNED */
  10237. // Slice: MP_WR_YUV_NV21
  10238. // 1: Put U before V
  10239. // 0: Put V before U
  10240. #ifdef MP_WR_YUV_NV21
  10241. #define MIV2_MP_WRITE_YUV_NV21_UV 0 //Put U before V
  10242. #define MIV2_MP_WRITE_YUV_NV21_VU 1 //Put V before U
  10243. #endif /* MP_WR_YUV_NV21 */
  10244. // Slice: MP_WR_YUV_NVY:
  10245. #ifdef MP_WR_YUV_NVY
  10246. #define MIV2_MP_WRITE_YUV_NVY_YC1C2 0 // 00: Put Y first => YC1C2
  10247. #define MIV2_MP_WRITE_YUV_NVY_C1YC2 1 // 01: Put Y second => C1YC2
  10248. #define MIV2_MP_WRITE_YUV_NVY_C1C2Y 2 // 10: Put Y Third => C1C2Y
  10249. #endif /* MP_WR_YUV_NVY */
  10250. // =========================================================================================
  10251. #ifdef ISP_DEMOSAIC_DENOISE_STRENGTH
  10252. #define ISP_DEMOSAIC_DENOISE_STRENGTH_MIN 0
  10253. #define ISP_DEMOSAIC_DENOISE_STRENGTH_MAX 32
  10254. #endif
  10255. #ifdef ISP_DEMOSAIC_SHARPEN_SIZE
  10256. #define ISP_DEMOSAIC_SHARPEN_SIZE_MIN 0
  10257. #define ISP_DEMOSAIC_SHARPEN_SIZE_MAX 16
  10258. #endif
  10259. #ifdef ISP_DMSC_DEMOIRE_AREA_THR
  10260. #define ISP_DMSC_DEMOIRE_AREA_THR_MIN 0
  10261. #define ISP_DMSC_DEMOIRE_AREA_THR_MAX 32
  10262. #endif
  10263. #ifdef ISP_DMSC_DEMOIRE_SAT_SHRINK
  10264. #define ISP_DMSC_DEMOIRE_SAT_SHRINK_MIN 0
  10265. #define ISP_DMSC_DEMOIRE_SAT_SHRINK_MAX 32
  10266. #endif
  10267. #ifdef ISP_DMSC_SHARPEN_T4_SHIFT
  10268. #define ISP_DMSC_SHARPEN_SHIFT_MIN 0
  10269. #define ISP_DMSC_SHARPEN_SHIFT_MAX 11
  10270. #endif
  10271. #ifdef ISP_DMSC_SHARPEN_LINE_SHIFT1
  10272. #define ISP_DMSC_SHARPEN_LINE_SHIFT1_MIN 0
  10273. #define ISP_DMSC_SHARPEN_LINE_SHIFT1_MAX 10
  10274. #endif
  10275. #ifdef ISP_DMSC_HF_FILT_00
  10276. #define ISP_DMSC_HF_FILT_MIN 0
  10277. #define ISP_DMSC_HF_FILT_MAX 34
  10278. #endif
  10279. #ifdef ISP_DMSC_CBCR_MODE
  10280. #define ISP_DMSC_CBCR_MODE_MIN 0
  10281. #define ISP_DMSC_CBCR_MODE_MAX 3
  10282. #endif
  10283. #ifdef ISP_DMSC_DEPURPLE_SAT_SHRINK
  10284. #define ISP_DMSC_DEPURPLE_SAT_SHRINK_MIN 0
  10285. #define ISP_DMSC_DEPURPLE_SAT_SHRINK_MAX 8
  10286. #endif
  10287. #ifdef ISP_DMSC_X_NF
  10288. #define ISP_DMSC_X_NF_MIN 0
  10289. #define ISP_DMSC_X_NF_MAX 31
  10290. #endif
  10291. #ifdef ISP_DMSC_X_NS
  10292. #define ISP_DMSC_X_NS_MIN 0
  10293. #define ISP_DMSC_X_NS_MAX 15
  10294. #endif
  10295. #ifdef ISP_DMSC_Y_NF
  10296. #define ISP_DMSC_Y_NF_MIN 0
  10297. #define ISP_DMSC_Y_NF_MAX 31
  10298. #endif
  10299. #ifdef ISP_DMSC_Y_NS
  10300. #define ISP_DMSC_Y_NS_MIN 0
  10301. #define ISP_DMSC_Y_NS_MAX 15
  10302. #endif
  10303. /* =========================================================================================*/
  10304. /*! returns the value of slice \a name from register or variable \a reg
  10305. * \note "parameter" \a reg could be a hardware register or a (32bit) variable, but not a pointer! \n
  10306. * each slice (specified as "parameter" \a name) requires two \#defines: \n
  10307. * - <tt>\<name\>_MASK </tt>: defines the mask to use on register side
  10308. * - <tt>\<name\>_SHIFT </tt>: defines the shift value to use (left on write, right on read)
  10309. */
  10310. #define REG_GET_SLICE(reg, name) \
  10311. (((reg) & (name##_MASK)) >> (name##_SHIFT))
  10312. /* =========================================================================================*/
  10313. /*! writes the value \a value into slice \a name of register or variable \a reg
  10314. * \note "parameter" \a reg could be a hardware register or a (32bit) variable, but not a pointer! \n
  10315. * each slice (specified as "parameter" \a name) requires two \#defines: \n
  10316. * - <tt>\<name\>_MASK </tt>: defines the mask to use on register side
  10317. * - <tt>\<name\>_SHIFT </tt>: defines the shift value to use (left on write, right on read)
  10318. */
  10319. #define REG_SET_SLICE(reg, name, value) \
  10320. { \
  10321. ((reg) = (((reg) & ~(name##_MASK)) | (((value) << (name##_SHIFT)) & (name##_MASK))));\
  10322. }
  10323. #endif /* __MRV_ALL_BITS_H__ */