isp_ioctl.c 115 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. /* process public and sample isp command. for complex modules, need new files.*/
  54. #include "mrv_all_bits.h"
  55. #include "isp_ioctl.h"
  56. #include "isp_types.h"
  57. #include "isp_wdr.h"
  58. #include <linux/dma-mapping.h>
  59. #include <linux/dma-buf.h>
  60. #ifdef __KERNEL__
  61. #include <linux/regmap.h>
  62. #include <linux/of_reserved_mem.h>
  63. #endif
  64. #include "isp_ioctl.h"
  65. volatile MrvAllRegister_t *all_regs = NULL;
  66. #ifndef __KERNEL__
  67. #define ISP_REG_SIZE 0x10000
  68. static HalHandle_t hal_handle;
  69. void isp_ic_set_hal(HalHandle_t hal)
  70. {
  71. hal_handle = hal;
  72. }
  73. void isp_write_reg(struct isp_ic_dev *dev, u32 offset, u32 val)
  74. {
  75. //isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);
  76. if (offset >= ISP_REG_SIZE)
  77. return;
  78. HalWriteReg(hal_handle, offset, val);
  79. }
  80. u32 isp_read_reg(struct isp_ic_dev *dev, u32 offset)
  81. {
  82. if (offset >= ISP_REG_SIZE)
  83. return 0;
  84. return HalReadReg(hal_handle, offset);
  85. }
  86. long isp_copy_data(void *dst, void *src, int size)
  87. {
  88. if (dst != src)
  89. memcpy(dst, src, size);
  90. return 0;
  91. }
  92. #else
  93. void isp_write_reg(struct isp_ic_dev *dev, u32 offset, u32 val)
  94. {
  95. // isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);
  96. if (offset >= ISP_REG_SIZE)
  97. return;
  98. __raw_writel(val, dev->base + offset);
  99. /*isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);*/
  100. }
  101. u32 isp_read_reg(struct isp_ic_dev *dev, u32 offset)
  102. {
  103. u32 val = 0;
  104. if (offset >= ISP_REG_SIZE)
  105. return 0;
  106. val = __raw_readl(dev->base + offset);
  107. /*isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);*/
  108. return val;
  109. }
  110. #endif
  111. int isp_reset(struct isp_ic_dev *dev)
  112. {
  113. isp_info("enter %s\n", __func__);
  114. isp_write_reg(dev, REG_ADDR(vi_ircl), 0xFFFFFFBF);
  115. #ifdef __KERNEL__
  116. mdelay(2);
  117. #endif
  118. isp_write_reg(dev, REG_ADDR(vi_ircl), 0x0);
  119. /*clear mis array*/
  120. isp_write_reg(dev, REG_ADDR(isp_ctrl), 0x0); //clear isp_ctrl disable_isp_clk
  121. isp_info("exit %s\n", __func__);
  122. return 0;
  123. }
  124. int isp_enable_tpg(struct isp_ic_dev *dev)
  125. {
  126. u32 addr, isp_tpg_ctrl;
  127. isp_info("enter %s\n", __func__);
  128. addr = REG_ADDR(isp_tpg_ctrl);
  129. isp_tpg_ctrl = isp_read_reg(dev, addr);
  130. //REG_SET_SLICE(isp_tpg_ctrl, TPG_FRAME_NUM, 1);//set tpg frame num
  131. REG_SET_SLICE(isp_tpg_ctrl, TPG_ENABLE, 1);
  132. isp_write_reg(dev, addr, isp_tpg_ctrl);
  133. isp_info("exit %s\n", __func__);
  134. return 0;
  135. }
  136. int isp_disable_tpg(struct isp_ic_dev *dev)
  137. {
  138. u32 addr, isp_tpg_ctrl;
  139. isp_info("enter %s\n", __func__);
  140. addr = REG_ADDR(isp_tpg_ctrl);
  141. isp_tpg_ctrl = isp_read_reg(dev, addr);
  142. REG_SET_SLICE(isp_tpg_ctrl, TPG_ENABLE, 0);
  143. isp_write_reg(dev, addr, isp_tpg_ctrl);
  144. isp_info("exit %s\n", __func__);
  145. return 0;
  146. }
  147. int isp_enable_bls(struct isp_ic_dev *dev)
  148. {
  149. #ifndef ISP_BLS
  150. //isp_err("unsupported function %s", __func__);
  151. return -1;
  152. #else
  153. u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl));
  154. isp_info("enter %s\n", __func__);
  155. REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_ENABLE,
  156. MRV_BLS_BLS_ENABLE_PROCESS);
  157. isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl);
  158. isp_info("exit %s\n", __func__);
  159. return 0;
  160. #endif
  161. }
  162. int isp_disable_bls(struct isp_ic_dev *dev)
  163. {
  164. #ifndef ISP_BLS
  165. //isp_err("unsupported function %s", __func__);
  166. return -1;
  167. #else
  168. u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl));
  169. isp_info("enter %s\n", __func__);
  170. REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_ENABLE,
  171. MRV_BLS_BLS_ENABLE_BYPASS);
  172. isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl);
  173. isp_info("exit %s\n", __func__);
  174. return 0;
  175. #endif
  176. }
  177. int isp_enable(struct isp_ic_dev *dev)
  178. {
  179. u32 isp_ctrl, isp_imsc;
  180. isp_info("enter %s\n", __func__);
  181. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  182. isp_imsc |= (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK);
  183. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  184. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  185. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 1);
  186. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  187. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 1);
  188. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  189. /*Set lsc tbl after isp enable*/
  190. if (dev->update_lsc_tbl) {
  191. isp_s_lsc_tbl(dev);
  192. dev->update_lsc_tbl = false;
  193. }
  194. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1);
  195. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  196. isp_info("exit %s\n", __func__);
  197. return 0;
  198. }
  199. int isp_disable(struct isp_ic_dev *dev)
  200. {
  201. u32 isp_ctrl;
  202. /* #ifndef ENABLE_IRQ
  203. u32 isp_imsc;
  204. #endif*/
  205. isp_info("enter %s\n", __func__);
  206. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  207. /* #ifndef ENABLE_IRQ
  208. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  209. isp_imsc |= (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK);
  210. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  211. #endif*/
  212. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 0);
  213. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  214. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 0);
  215. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  216. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  217. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  218. isp_write_reg(dev, REG_ADDR(isp_isr), MRV_ISP_ISR_ISP_OFF_MASK);
  219. isp_info("exit %s\n", __func__);
  220. return 0;
  221. }
  222. bool is_isp_enable(struct isp_ic_dev *dev)
  223. {
  224. // isp_info("enter %s\n", __func__);
  225. return isp_read_reg(dev, REG_ADDR(isp_ctrl)) & 0x01;
  226. }
  227. int isp_enable_lsc(struct isp_ic_dev *dev)
  228. {
  229. u32 isp_lsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_lsc_ctrl));
  230. isp_info("enter %s\n", __func__);
  231. REG_SET_SLICE(isp_lsc_ctrl, MRV_LSC_LSC_EN, 1U);
  232. isp_write_reg(dev, REG_ADDR(isp_lsc_ctrl), isp_lsc_ctrl);
  233. {
  234. uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  235. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  236. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  237. }
  238. isp_info("exit %s\n", __func__);
  239. return 0;
  240. }
  241. int isp_disable_lsc(struct isp_ic_dev *dev)
  242. {
  243. u32 isp_lsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_lsc_ctrl));
  244. isp_info("enter %s\n", __func__);
  245. REG_SET_SLICE(isp_lsc_ctrl, MRV_LSC_LSC_EN, 0U);
  246. isp_write_reg(dev, REG_ADDR(isp_lsc_ctrl), isp_lsc_ctrl);
  247. {
  248. uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  249. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  250. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  251. }
  252. isp_info("exit %s\n", __func__);
  253. return 0;
  254. }
  255. #if defined(__KERNEL__) && defined(ISP8000NANO_V1802)
  256. static int isp_gpr_input_control(struct isp_ic_dev *dev)
  257. {
  258. struct isp_context isp_ctx = *(&dev->ctx);
  259. unsigned int fmt_offset = 3;
  260. unsigned int isp_dewarp_control_val;
  261. if (dev->mix_gpr == NULL)
  262. return -ENOMEM;
  263. if (dev->id == 0)
  264. fmt_offset = 3;
  265. else
  266. fmt_offset = 13;
  267. regmap_read(dev->mix_gpr, 0x138, &isp_dewarp_control_val);
  268. if (isp_dewarp_control_val == 0)
  269. isp_dewarp_control_val = 0x8d8360;
  270. switch (isp_ctx.input_selection) {
  271. case MRV_ISP_INPUT_SELECTION_12EXT:
  272. isp_dewarp_control_val &= ~(0x3f << fmt_offset);
  273. isp_dewarp_control_val |= (0x2c << fmt_offset);
  274. break;
  275. case MRV_ISP_INPUT_SELECTION_10ZERO:
  276. case MRV_ISP_INPUT_SELECTION_10MSB:
  277. isp_dewarp_control_val &= ~(0x3f << fmt_offset);
  278. isp_dewarp_control_val |= (0x2b << fmt_offset);
  279. break;
  280. case MRV_ISP_INPUT_SELECTION_8ZERO:
  281. case MRV_ISP_INPUT_SELECTION_8MSB:
  282. isp_dewarp_control_val &= ~(0x3f << fmt_offset);
  283. isp_dewarp_control_val |= (0x2a << fmt_offset);
  284. break;
  285. default:
  286. return 0;
  287. }
  288. regmap_write(dev->mix_gpr, 0x138, isp_dewarp_control_val);
  289. return 0;
  290. }
  291. #endif
  292. int isp_s_input(struct isp_ic_dev *dev)
  293. {
  294. struct isp_context isp_ctx = *(&dev->ctx);
  295. u32 isp_ctrl, isp_acq_prop, isp_demosaic;
  296. #ifdef ISP_HDR_STITCH_RY
  297. u32 isp_stitching_ctrl;
  298. #endif //ISP_HDR_STITCH_RY
  299. isp_info("enter %s\n", __func__);
  300. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  301. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_MODE, isp_ctx.mode);
  302. isp_acq_prop = isp_read_reg(dev, REG_ADDR(isp_acq_prop));
  303. REG_SET_SLICE(isp_acq_prop, MRV_ISP_SAMPLE_EDGE, isp_ctx.sample_edge);
  304. REG_SET_SLICE(isp_acq_prop, MRV_ISP_HSYNC_POL,
  305. isp_ctx.hSyncLowPolarity);
  306. REG_SET_SLICE(isp_acq_prop, MRV_ISP_VSYNC_POL,
  307. isp_ctx.vSyncLowPolarity);
  308. REG_SET_SLICE(isp_acq_prop, MRV_ISP_BAYER_PAT, isp_ctx.bayer_pattern);
  309. REG_SET_SLICE(isp_acq_prop, MRV_ISP_CONV_422, isp_ctx.sub_sampling);
  310. REG_SET_SLICE(isp_acq_prop, MRV_ISP_CCIR_SEQ, isp_ctx.seq_ccir);
  311. REG_SET_SLICE(isp_acq_prop, MRV_ISP_FIELD_SELECTION,
  312. isp_ctx.field_selection);
  313. REG_SET_SLICE(isp_acq_prop, MRV_ISP_INPUT_SELECTION,
  314. isp_ctx.input_selection);
  315. REG_SET_SLICE(isp_acq_prop, MRV_ISP_LATENCY_FIFO_SELECTION,
  316. isp_ctx.latency_fifo);
  317. isp_write_reg(dev, REG_ADDR(isp_acq_prop), isp_acq_prop);
  318. isp_write_reg(dev, REG_ADDR(isp_acq_h_offs), isp_ctx.acqWindow.x);
  319. isp_write_reg(dev, REG_ADDR(isp_acq_v_offs), isp_ctx.acqWindow.y);
  320. isp_write_reg(dev, REG_ADDR(isp_acq_h_size), isp_ctx.acqWindow.width);
  321. isp_write_reg(dev, REG_ADDR(isp_acq_v_size), isp_ctx.acqWindow.height);
  322. #ifdef ISP_MI_HDR_RY
  323. isp_write_reg(dev, REG_ADDR(isp_hdr_interval), 0x113);
  324. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_h_blank), 0x30);
  325. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_v_blank), 0x30);
  326. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_h_size), isp_ctx.acqWindow.width);
  327. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_v_size), isp_ctx.acqWindow.height);
  328. #endif
  329. isp_write_reg(dev, REG_ADDR(isp_out_h_offs),
  330. (isp_ctx.ofWindow.x & MRV_ISP_ISP_OUT_H_OFFS_MASK));
  331. isp_write_reg(dev, REG_ADDR(isp_out_v_offs),
  332. (isp_ctx.ofWindow.y & MRV_ISP_ISP_OUT_V_OFFS_MASK));
  333. isp_write_reg(dev, REG_ADDR(isp_out_h_size),
  334. (isp_ctx.ofWindow.width & MRV_ISP_ISP_OUT_H_SIZE_MASK));
  335. isp_write_reg(dev, REG_ADDR(isp_out_v_size),
  336. (isp_ctx.ofWindow.height & MRV_ISP_ISP_OUT_V_SIZE_MASK));
  337. isp_write_reg(dev, REG_ADDR(isp_is_h_offs),
  338. (isp_ctx.isWindow.x & MRV_IS_IS_H_OFFS_MASK));
  339. isp_write_reg(dev, REG_ADDR(isp_is_v_offs),
  340. (isp_ctx.isWindow.y & MRV_IS_IS_V_OFFS_MASK));
  341. isp_write_reg(dev, REG_ADDR(isp_is_h_size),
  342. (isp_ctx.isWindow.width & MRV_IS_IS_H_SIZE_MASK));
  343. isp_write_reg(dev, REG_ADDR(isp_is_v_size),
  344. (isp_ctx.isWindow.height & MRV_IS_IS_V_SIZE_MASK));
  345. isp_demosaic = isp_read_reg(dev, REG_ADDR(isp_demosaic));
  346. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_BYPASS,
  347. isp_ctx.bypass_mode);
  348. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_TH,
  349. isp_ctx.demosaic_threshold);
  350. isp_write_reg(dev, REG_ADDR(isp_demosaic), isp_demosaic);
  351. #ifdef ISP_HDR_STITCH
  352. isp_write_reg(dev, REG_ADDR(isp_stitching_frame_width), isp_ctx.acqWindow.width);
  353. isp_write_reg(dev, REG_ADDR(isp_stitching_frame_height), isp_ctx.acqWindow.height);
  354. isp_write_reg(dev, REG_ADDR(isp_stitching_hdr_mode), isp_ctx.stitching_mode);
  355. isp_stitching_ctrl = isp_read_reg(dev, REG_ADDR(isp_stitching_ctrl));
  356. REG_SET_SLICE(isp_stitching_ctrl, STITCHING_BAYER_PATTERN, isp_ctx.bayer_pattern);
  357. isp_write_reg(dev, REG_ADDR(isp_stitching_ctrl), isp_stitching_ctrl);
  358. #endif
  359. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  360. #if defined(__KERNEL__) && defined(ISP8000NANO_V1802)
  361. isp_gpr_input_control(dev);
  362. #endif
  363. return 0;
  364. }
  365. int isp_s_digital_gain(struct isp_ic_dev *dev)
  366. {
  367. struct isp_digital_gain_cxt dgain = *(&dev->dgain);
  368. u32 isp_dgain_rb = isp_read_reg(dev, REG_ADDR(isp_dgain_rb));
  369. u32 isp_dgain_g = isp_read_reg(dev, REG_ADDR(isp_dgain_g));
  370. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  371. if (!dgain.enable) {
  372. isp_err("%s, Disable isp digital gain", __func__);
  373. REG_SET_SLICE(isp_ctrl, MRV_ISP_DIGITAL_GAIN_EN, 0U);
  374. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  375. return 0;
  376. }
  377. isp_info("enter %s\n", __func__);
  378. REG_SET_SLICE(isp_dgain_rb, ISP_DIGITAL_GAIN_R, dgain.gain_r);
  379. REG_SET_SLICE(isp_dgain_rb, ISP_DIGITAL_GAIN_B, dgain.gain_b);
  380. REG_SET_SLICE(isp_dgain_g, ISP_DIGITAL_GAIN_GR, dgain.gain_gr);
  381. REG_SET_SLICE(isp_dgain_g, ISP_DIGITAL_GAIN_GB, dgain.gain_gb);
  382. REG_SET_SLICE(isp_ctrl, MRV_ISP_DIGITAL_GAIN_EN, 1U);
  383. isp_write_reg(dev, REG_ADDR(isp_dgain_rb), isp_dgain_rb);
  384. isp_write_reg(dev, REG_ADDR(isp_dgain_g), isp_dgain_g);
  385. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  386. isp_info("exit %s\n", __func__);
  387. return 0;
  388. }
  389. int isp_s_demosaic(struct isp_ic_dev *dev)
  390. {
  391. struct isp_context isp_ctx = *(&dev->ctx);
  392. u32 isp_demosaic;
  393. isp_info("enter %s\n", __func__);
  394. isp_demosaic = isp_read_reg(dev, REG_ADDR(isp_demosaic));
  395. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_BYPASS,
  396. isp_ctx.bypass_mode);
  397. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_TH,
  398. isp_ctx.demosaic_threshold);
  399. isp_write_reg(dev, REG_ADDR(isp_demosaic), isp_demosaic);
  400. isp_info("exit %s\n", __func__);
  401. return 0;;
  402. }
  403. int isp_s_tpg(struct isp_ic_dev *dev)
  404. {
  405. struct isp_tpg_context tpg = *(&dev->tpg);
  406. u32 addr, regVal;
  407. isp_info("enter %s\n", __func__);
  408. addr = REG_ADDR(isp_tpg_ctrl);
  409. regVal = isp_read_reg(dev, addr);
  410. REG_SET_SLICE(regVal, TPG_IMG_NUM, tpg.image_type);
  411. REG_SET_SLICE(regVal, TPG_CFA_PAT, tpg.bayer_pattern);
  412. REG_SET_SLICE(regVal, TPG_COLOR_DEPTH, tpg.color_depth);
  413. REG_SET_SLICE(regVal, TPG_RESOLUTION, tpg.resolution);
  414. REG_SET_SLICE(regVal, TPG_FRAME_NUM, tpg.frame_num);
  415. isp_write_reg(dev, addr, regVal);
  416. regVal = 0;
  417. REG_SET_SLICE(regVal, TPG_PIX_GAP_IN, tpg.pixleGap);
  418. REG_SET_SLICE(regVal, TPG_LINE_GAP_IN, tpg.lineGap);
  419. isp_write_reg(dev, REG_ADDR(isp_tpg_gap_in), regVal);
  420. regVal = 0;
  421. REG_SET_SLICE(regVal, TPG_PIX_GAP_STD_IN, tpg.gapStandard);
  422. isp_write_reg(dev, REG_ADDR(isp_tpg_gap_std_in), regVal);
  423. regVal = 0;
  424. REG_SET_SLICE(regVal, TPG_RANDOM_SEED, tpg.randomSeed);
  425. isp_write_reg(dev, REG_ADDR(isp_tpg_random_seed), regVal);
  426. REG_SET_SLICE(regVal, TPG_HTOTAL_IN, tpg.user_mode_h.total);
  427. REG_SET_SLICE(regVal, TPG_VTOTAL_IN, tpg.user_mode_v.total);
  428. isp_write_reg(dev, REG_ADDR(isp_tpg_total_in), regVal);
  429. regVal = 0;
  430. REG_SET_SLICE(regVal, TPG_HACT_IN, tpg.user_mode_h.act);
  431. REG_SET_SLICE(regVal, TPG_VACT_IN, tpg.user_mode_v.act);
  432. isp_write_reg(dev, REG_ADDR(isp_tpg_act_in), regVal);
  433. regVal = 0;
  434. REG_SET_SLICE(regVal, TPG_FP_H_IN, tpg.user_mode_h.fp);
  435. REG_SET_SLICE(regVal, TPG_FP_V_IN, tpg.user_mode_v.fp);
  436. isp_write_reg(dev, REG_ADDR(isp_tpg_fp_in), regVal);
  437. regVal = 0;
  438. REG_SET_SLICE(regVal, TPG_BP_H_IN, tpg.user_mode_h.bp);
  439. REG_SET_SLICE(regVal, TPG_BP_V_IN, tpg.user_mode_v.bp);
  440. isp_write_reg(dev, REG_ADDR(isp_tpg_bp_in), regVal);
  441. regVal = 0;
  442. REG_SET_SLICE(regVal, TPG_HS_W_IN, tpg.user_mode_h.sync);
  443. REG_SET_SLICE(regVal, TPG_VS_W_IN, tpg.user_mode_v.sync);
  444. isp_write_reg(dev, REG_ADDR(isp_tpg_w_in), regVal);
  445. isp_info("exit %s\n", __func__);
  446. return 0;
  447. }
  448. int isp_s_mcm_wr(struct isp_ic_dev *dev)
  449. {
  450. struct isp_mcm_context *mcm = &dev->mcm;
  451. u32 mcm_ctrl;
  452. u32 mcm_hsync_preample_ext;
  453. u32 mcm_size, mcm_rd_fmt;
  454. int i;
  455. isp_info("enter %s\n", __func__);
  456. mcm_ctrl = isp_read_reg(dev, REG_ADDR(mcm_ctrl));
  457. mcm_rd_fmt = isp_read_reg(dev, REG_ADDR(mcm_rd_cfg));
  458. mcm_hsync_preample_ext = isp_read_reg(dev, REG_ADDR(mcm_hsync_preample_ext));
  459. REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_SWITCH, mcm->bypass_switch);
  460. REG_SET_SLICE(mcm_ctrl, MCM_WR0_FMT, mcm->wr_fmt[MCM_INDEX_WR0]);
  461. REG_SET_SLICE(mcm_ctrl, MCM_WR1_FMT, mcm->wr_fmt[MCM_INDEX_WR1]);
  462. REG_SET_SLICE(mcm_ctrl, MCM_G2_WR0_FMT, mcm->wr_fmt[MCM_INDEX_G2_WR0]);
  463. REG_SET_SLICE(mcm_ctrl, MCM_G2_WR1_FMT, mcm->wr_fmt[MCM_INDEX_G2_WR1]);
  464. REG_SET_SLICE(mcm_ctrl, MCM_SENSOR_MEM_BYPASS, mcm->sensor_mem_bypass);
  465. REG_SET_SLICE(mcm_rd_fmt, MCM_RD_FMT, mcm->rd_fmt);
  466. REG_SET_SLICE(mcm_hsync_preample_ext, MCM_HSYNC_PREAMPLE_EXT, mcm->hsync_rpeample_ext);
  467. for (i = MCM_INDEX_WR0 ; i < MCM_INDEX_WR_MAX; i++){
  468. REG_SET_SLICE(mcm_size, MCM_HEIGHT0, mcm->height[i]);
  469. REG_SET_SLICE(mcm_size, MCM_WIDTH0, mcm->width[i]);
  470. isp_write_reg(dev, REG_ADDR(mcm_size0) + i *4, mcm_size);
  471. }
  472. isp_write_reg(dev, REG_ADDR(mcm_hsync_preample_ext), mcm_hsync_preample_ext);
  473. isp_write_reg(dev, REG_ADDR(mcm_rd_cfg), mcm_rd_fmt);
  474. isp_write_reg(dev, REG_ADDR(mcm_ctrl), mcm_ctrl);
  475. isp_info("exit %s\n", __func__);
  476. return 0;
  477. }
  478. int isp_bypass_mcm(struct isp_ic_dev *dev)
  479. {
  480. struct isp_mcm_context *mcm = &dev->mcm;
  481. u32 mcm_ctrl;
  482. u32 mcm_retiming0;
  483. u32 mcm_retiming1;
  484. u32 mcm_wr_retiming0;
  485. u32 mcm_wr_retiming1;
  486. isp_info("enter %s\n", __func__);
  487. mcm_ctrl = isp_read_reg(dev, REG_ADDR(mcm_ctrl));
  488. mcm_retiming0 = isp_read_reg(dev, REG_ADDR(mcm_retiming0));
  489. mcm_retiming1 = isp_read_reg(dev, REG_ADDR(mcm_retiming1));
  490. mcm_wr_retiming0 = isp_read_reg(dev, REG_ADDR(mcm_wr_retiming0));
  491. mcm_wr_retiming1 = isp_read_reg(dev, REG_ADDR(mcm_wr_retiming1));
  492. if (mcm->bypass_enable) {
  493. REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_EN, 1);
  494. } else {
  495. REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_EN, 0);
  496. }
  497. REG_SET_SLICE(mcm_retiming0, MCM_VSYNC_DURATION, mcm->vsync_duration);
  498. REG_SET_SLICE(mcm_retiming0, MCM_VSYNC_BLANK, mcm->vsync_blank);
  499. REG_SET_SLICE(mcm_retiming1, MCM_HSYNC_PREAMPLE, mcm->hsync_preample);
  500. REG_SET_SLICE(mcm_retiming1, MCM_HSYNC_BLANK, mcm->hsync_blank);
  501. REG_SET_SLICE(mcm_wr_retiming0, MCM_VSYNC_DURATION, mcm->vsync_duration);
  502. REG_SET_SLICE(mcm_wr_retiming0, MCM_VSYNC_BLANK, mcm->vsync_blank);
  503. REG_SET_SLICE(mcm_wr_retiming1, MCM_HSYNC_PREAMPLE, mcm->hsync_preample);
  504. REG_SET_SLICE(mcm_wr_retiming1, MCM_HSYNC_BLANK, mcm->hsync_blank);
  505. isp_write_reg(dev, REG_ADDR(mcm_ctrl), mcm_ctrl);
  506. isp_write_reg(dev, REG_ADDR(mcm_retiming0), mcm_retiming0); // 0x01042801);//
  507. isp_write_reg(dev, REG_ADDR(mcm_retiming1), mcm_retiming1); //0x00008478); //
  508. isp_write_reg(dev, REG_ADDR(mcm_wr_retiming0), mcm_wr_retiming0); //0x01042801); //
  509. isp_write_reg(dev, REG_ADDR(mcm_wr_retiming1), mcm_wr_retiming1); //0x000084ec);//
  510. isp_info("exit %s\n", __func__);
  511. return 0;
  512. }
  513. int isp_s_mux(struct isp_ic_dev *dev)
  514. {
  515. struct isp_mux_context mux = *(&dev->mux);
  516. u32 vi_dpcl;
  517. isp_info("enter %s\n", __func__);
  518. vi_dpcl = isp_read_reg(dev, REG_ADDR(vi_dpcl));
  519. REG_SET_SLICE(vi_dpcl, MRV_VI_MP_MUX, mux.mp_mux);
  520. REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_SPMUX, mux.sp_mux);
  521. REG_SET_SLICE(vi_dpcl, MRV_VI_CHAN_MODE, mux.chan_mode);
  522. REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_IEMUX, mux.ie_mux);
  523. REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_SWITCH, mux.dma_read_switch);
  524. REG_SET_SLICE(vi_dpcl, MRV_IF_SELECT, mux.if_select);
  525. isp_write_reg(dev, REG_ADDR(vi_dpcl), vi_dpcl);
  526. isp_info("exit %s\n", __func__);
  527. return 0;
  528. }
  529. int isp_s_bls(struct isp_ic_dev *dev)
  530. {
  531. #ifndef ISP_BLS
  532. //isp_err("unsupported function %s", __func__);
  533. return -1;
  534. #else
  535. struct isp_bls_context bls = *(&dev->bls);
  536. u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl));
  537. isp_info("enter %s\n", __func__);
  538. REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_MODE, bls.mode);
  539. isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl);
  540. isp_write_reg(dev, REG_ADDR(isp_bls_a_fixed), bls.a);
  541. isp_write_reg(dev, REG_ADDR(isp_bls_b_fixed), bls.b);
  542. isp_write_reg(dev, REG_ADDR(isp_bls_c_fixed), bls.c);
  543. isp_write_reg(dev, REG_ADDR(isp_bls_d_fixed), bls.d);
  544. return 0;
  545. #endif
  546. }
  547. int isp_enable_awb(struct isp_ic_dev *dev)
  548. {
  549. u32 isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop));
  550. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  551. isp_info("enter %s\n", __func__);
  552. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MODE, MRV_ISP_AWB_MODE_MEAS);
  553. isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop);
  554. isp_write_reg(dev, REG_ADDR(isp_imsc),
  555. isp_imsc | MRV_ISP_IMSC_AWB_DONE_MASK);
  556. isp_info("exit %s\n", __func__);
  557. return 0;
  558. }
  559. int isp_disable_awb(struct isp_ic_dev *dev)
  560. {
  561. u32 isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop));
  562. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  563. isp_info("enter %s\n", __func__);
  564. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MODE, MRV_ISP_AWB_MODE_NOMEAS);
  565. isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop);
  566. isp_write_reg(dev, REG_ADDR(isp_imsc),
  567. isp_imsc & ~MRV_ISP_IMSC_AWB_DONE_MASK);
  568. isp_info("exit %s\n", __func__);
  569. return 0;
  570. }
  571. int isp_s_awb(struct isp_ic_dev *dev)
  572. {
  573. struct isp_awb_context awb = *(&dev->awb);
  574. u32 gain_data = 0;
  575. u32 isp_awb_thresh = 0;
  576. u32 isp_awb_ref = 0;
  577. u32 isp_awb_prop = 0;
  578. /* isp_info("enter %s\n", __func__); */
  579. isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop));
  580. if (awb.mode == MRV_ISP_AWB_MEAS_MODE_YCBCR) {
  581. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MEAS_MODE,
  582. MRV_ISP_AWB_MEAS_MODE_YCBCR);
  583. if (awb.max_y == 0) {
  584. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN,
  585. MRV_ISP_AWB_MAX_EN_DISABLE);
  586. } else {
  587. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN,
  588. MRV_ISP_AWB_MAX_EN_ENABLE);
  589. }
  590. } else if (awb.mode == MRV_ISP_AWB_MEAS_MODE_RGB) {
  591. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN,
  592. MRV_ISP_AWB_MAX_EN_DISABLE);
  593. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MEAS_MODE,
  594. MRV_ISP_AWB_MEAS_MODE_RGB);
  595. }
  596. isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop);
  597. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MAX_Y, awb.max_y);
  598. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MIN_Y__MAX_G,
  599. awb.min_y_max_g);
  600. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MAX_CSUM, awb.max_c_sum);
  601. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MIN_C, awb.min_c);
  602. isp_write_reg(dev, REG_ADDR(isp_awb_thresh), isp_awb_thresh);
  603. REG_SET_SLICE(isp_awb_ref, MRV_ISP_AWB_REF_CR__MAX_R, awb.refcr_max_r);
  604. REG_SET_SLICE(isp_awb_ref, MRV_ISP_AWB_REF_CB__MAX_B, awb.refcb_max_b);
  605. isp_write_reg(dev, REG_ADDR(isp_awb_ref), isp_awb_ref);
  606. isp_write_reg(dev, REG_ADDR(isp_awb_frames), 0);
  607. isp_write_reg(dev, REG_ADDR(isp_awb_h_offs),
  608. (MRV_ISP_AWB_H_OFFS_MASK & awb.window.x));
  609. isp_write_reg(dev, REG_ADDR(isp_awb_v_offs),
  610. (MRV_ISP_AWB_V_OFFS_MASK & awb.window.y));
  611. isp_write_reg(dev, REG_ADDR(isp_awb_h_size),
  612. (MRV_ISP_AWB_H_SIZE_MASK & awb.window.width));
  613. isp_write_reg(dev, REG_ADDR(isp_awb_v_size),
  614. (MRV_ISP_AWB_V_SIZE_MASK & awb.window.height));
  615. gain_data = 0UL;
  616. #ifdef ISP_AWB_0410 //This is Gain value component 4 bit int part and 10 bit fractional part
  617. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_R, awb.gain_r << 2);
  618. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_B, awb.gain_b << 2) ;
  619. #else //This is Gain value component 2 bit int part and 8 bit fractional part
  620. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_R, awb.gain_r);
  621. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_B, awb.gain_b);
  622. #endif
  623. isp_write_reg(dev, REG_ADDR(isp_awb_gain_rb), gain_data);
  624. gain_data = 0UL;
  625. #ifdef ISP_AWB_0410 //This is Gain value component 4 bit int part and 10 bit fractional part
  626. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GR, awb.gain_gr << 2);
  627. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GB, awb.gain_gb << 2);
  628. #else //This is Gain value component 2 bit int part and 8 bit fractional part
  629. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GR, awb.gain_gr);
  630. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GB, awb.gain_gb);
  631. #endif
  632. isp_write_reg(dev, REG_ADDR(isp_awb_gain_g), gain_data);
  633. return 0;
  634. }
  635. int isp_s_is(struct isp_ic_dev *dev)
  636. {
  637. struct isp_is_context is = *(&dev->is);
  638. u32 isp_is_ctrl;
  639. u32 isp_is_displace;
  640. u32 isp_ctrl;
  641. isp_info("enter %s\n", __func__);
  642. isp_is_ctrl = isp_read_reg(dev, REG_ADDR(isp_is_ctrl));
  643. if (!is.enable) {
  644. REG_SET_SLICE(isp_is_ctrl, MRV_IS_IS_EN, 0);
  645. isp_write_reg(dev, REG_ADDR(isp_is_ctrl), isp_is_ctrl);
  646. return 0;
  647. }
  648. REG_SET_SLICE(isp_is_ctrl, MRV_IS_IS_EN, 1);
  649. isp_write_reg(dev, REG_ADDR(isp_is_h_offs), is.window.x);
  650. isp_write_reg(dev, REG_ADDR(isp_is_v_offs), is.window.y);
  651. isp_write_reg(dev, REG_ADDR(isp_is_h_size), is.window.width);
  652. isp_write_reg(dev, REG_ADDR(isp_is_v_size), is.window.height);
  653. isp_write_reg(dev, REG_ADDR(isp_is_recenter),
  654. is.recenter & MRV_IS_IS_RECENTER_MASK);
  655. isp_write_reg(dev, REG_ADDR(isp_is_max_dx), is.max_dx);
  656. isp_write_reg(dev, REG_ADDR(isp_is_max_dy), is.max_dy);
  657. isp_is_displace = isp_read_reg(dev, REG_ADDR(isp_is_displace));
  658. REG_SET_SLICE(isp_is_displace, MRV_IS_DX, is.displace_x);
  659. REG_SET_SLICE(isp_is_displace, MRV_IS_DY, is.displace_y);
  660. isp_write_reg(dev, REG_ADDR(isp_is_displace), isp_is_displace);
  661. isp_write_reg(dev, REG_ADDR(isp_is_ctrl), isp_is_ctrl);
  662. if (is.update) {
  663. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  664. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  665. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  666. is.update = false;
  667. }
  668. isp_info("exit %s\n", __func__);
  669. return 0;
  670. }
  671. int isp_s_raw_is(struct isp_ic_dev *dev)
  672. {
  673. #ifndef ISP_RAWIS
  674. //isp_err("unsupported funciton: %s\n", __func__);
  675. return -EINVAL;
  676. #else
  677. struct isp_is_context rawis = *(&dev->rawis);
  678. u32 isp_raw_is_ctrl;
  679. u32 isp_raw_is_displace;
  680. // u32 isp_ctrl;
  681. isp_info("enter %s\n", __func__);
  682. isp_raw_is_ctrl = isp_read_reg(dev, REG_ADDR(isp_raw_is_ctrl));
  683. if (!rawis.enable) {
  684. isp_write_reg(dev, REG_ADDR(isp_raw_is_h_size),
  685. rawis.window.width);
  686. isp_write_reg(dev, REG_ADDR(isp_raw_is_v_size),
  687. rawis.window.height);
  688. REG_SET_SLICE(isp_raw_is_ctrl, MRV_ISP_RAW_IS_EN, 0);
  689. isp_write_reg(dev, REG_ADDR(isp_raw_is_ctrl), isp_raw_is_ctrl);
  690. return 0;
  691. }
  692. REG_SET_SLICE(isp_raw_is_ctrl, MRV_ISP_RAW_IS_EN, 1);
  693. isp_write_reg(dev, REG_ADDR(isp_raw_is_h_offs), rawis.window.x);
  694. isp_write_reg(dev, REG_ADDR(isp_raw_is_v_offs), rawis.window.y);
  695. isp_write_reg(dev, REG_ADDR(isp_raw_is_h_size), rawis.window.width);
  696. isp_write_reg(dev, REG_ADDR(isp_raw_is_v_size), rawis.window.height);
  697. isp_write_reg(dev, REG_ADDR(isp_raw_is_recenter),
  698. rawis.recenter & MRV_IS_IS_RECENTER_MASK);
  699. isp_write_reg(dev, REG_ADDR(isp_raw_is_max_dx), rawis.max_dx);
  700. isp_write_reg(dev, REG_ADDR(isp_raw_is_max_dy), rawis.max_dy);
  701. isp_raw_is_displace = isp_read_reg(dev, REG_ADDR(isp_raw_is_displace));
  702. REG_SET_SLICE(isp_raw_is_displace, MRV_ISP_RAW_IS_DX, rawis.displace_x);
  703. REG_SET_SLICE(isp_raw_is_displace, MRV_ISP_RAW_IS_DY, rawis.displace_y);
  704. isp_write_reg(dev, REG_ADDR(isp_raw_is_displace), isp_raw_is_displace);
  705. isp_write_reg(dev, REG_ADDR(isp_raw_is_ctrl), isp_raw_is_ctrl);
  706. /*dont update the configuration at the sub module function*/
  707. #if 0
  708. if (rawis.update) {
  709. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  710. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1);
  711. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  712. rawis.update = false;
  713. }
  714. #endif
  715. return 0;
  716. #endif
  717. }
  718. int isp_s_cnr(struct isp_ic_dev *dev)
  719. {
  720. struct isp_cnr_context *cnr = &dev->cnr;
  721. u32 isp_ctrl;
  722. isp_info("enter %s\n", __func__);
  723. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  724. if (!cnr->enable) {
  725. REG_SET_SLICE(isp_ctrl, MRV_ISP_CNR_EN, 0);
  726. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  727. return 0;
  728. }
  729. REG_SET_SLICE(isp_ctrl, MRV_ISP_CNR_EN, 1);
  730. isp_write_reg(dev, REG_ADDR(isp_cnr_linesize), cnr->line_width);
  731. isp_write_reg(dev, REG_ADDR(isp_cnr_threshold_c1), cnr->threshold_1);
  732. isp_write_reg(dev, REG_ADDR(isp_cnr_threshold_c2), cnr->threshold_2);
  733. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  734. isp_info("exit %s\n", __func__);
  735. return 0;
  736. }
  737. static void isp_test_bt(struct isp_ic_dev *dev)
  738. {
  739. isp_write_reg(dev, 0x00000010, 0x00019f7b);
  740. isp_write_reg(dev, 0x00000014, 0x00020000);
  741. isp_write_reg(dev, 0x00001200, 0x00000000);
  742. isp_write_reg(dev, 0x00001204, 0x01e00280);
  743. isp_write_reg(dev, 0x00001208, 0x01e00280);
  744. isp_write_reg(dev, 0x00001308, 0x6ce60608);
  745. isp_write_reg(dev, 0x00001314, 0x000008c4);
  746. isp_write_reg(dev, 0x00001318, 0x00000001);
  747. isp_write_reg(dev, 0x0000131c, 0x03a2013b);
  748. isp_write_reg(dev, 0x00001320, 0x00000000);
  749. isp_write_reg(dev, 0x00001324, 0xc0000000);
  750. isp_write_reg(dev, 0x00001328, 0x0004B000);
  751. isp_write_reg(dev, 0x0000132c, 0x00000000);
  752. isp_write_reg(dev, 0x00001330, 0x00000280);
  753. isp_write_reg(dev, 0x00001334, 0x00000280);
  754. isp_write_reg(dev, 0x00001338, 0x000001e0);
  755. isp_write_reg(dev, 0x0000133c, 0x0004B000);
  756. isp_write_reg(dev, 0x00001340, 0xc0040000);
  757. isp_write_reg(dev, 0x00001344, 0x0004B000);
  758. isp_write_reg(dev, 0x000016c0, 0x07ffffff);
  759. isp_write_reg(dev, 0x000005bc, 0x00000003);
  760. isp_write_reg(dev, 0x000016c4, 0x052c4e39);
  761. isp_write_reg(dev, 0x00000404, 0x00d00018);
  762. isp_write_reg(dev, 0x00000410, 0x00000280);
  763. isp_write_reg(dev, 0x00000414, 0x000001e0);
  764. isp_write_reg(dev, 0x00000538, 0x01000100);
  765. isp_write_reg(dev, 0x0000053c, 0x02270220);
  766. isp_write_reg(dev, 0x0000059c, 0x00000280);
  767. isp_write_reg(dev, 0x000005a0, 0x000001e0);
  768. isp_write_reg(dev, 0x00002310, 0x00000280);
  769. isp_write_reg(dev, 0x00002314, 0x000001e0);
  770. isp_write_reg(dev, 0x0000295c, 0x00000070);
  771. isp_write_reg(dev, 0x00003e00, 0x040128be);
  772. isp_write_reg(dev, 0x00003e04, 0x00000000);
  773. isp_write_reg(dev, 0x00003e08, 0x00001f08);
  774. isp_write_reg(dev, 0x00003e0c, 0x200003ff);
  775. isp_write_reg(dev, 0x00003e10, 0x0c968628);
  776. isp_write_reg(dev, 0x00003e14, 0x00008008);
  777. isp_write_reg(dev, 0x00003e18, 0x007d07d0);
  778. isp_write_reg(dev, 0x00003e1c, 0x301a3012);
  779. isp_write_reg(dev, 0x00003e20, 0x04010000);
  780. isp_write_reg(dev, 0x00003e24, 0x22018000);
  781. isp_write_reg(dev, 0x00003e28, 0x00020000);
  782. isp_write_reg(dev, 0x00003e2c, 0x0210210a);
  783. isp_write_reg(dev, 0x00003e30, 0x00102102);
  784. isp_write_reg(dev, 0x00003e34, 0x0000388c);
  785. isp_write_reg(dev, 0x00003e38, 0x00000000);
  786. isp_write_reg(dev, 0x00003e3c, 0x00000000);
  787. isp_write_reg(dev, 0x00003e40, 0x00000000);
  788. isp_write_reg(dev, 0x00003e44, 0x00000001);
  789. isp_write_reg(dev, 0x00003e48, 0x10001000);
  790. isp_write_reg(dev, 0x00003e4c, 0x00000000);
  791. isp_write_reg(dev, 0x00003e50, 0x00000000);
  792. isp_write_reg(dev, 0x00003e54, 0x00000000);
  793. isp_write_reg(dev, 0x00003e58, 0x00080010);
  794. isp_write_reg(dev, 0x00003e5c, 0x00080010);
  795. isp_write_reg(dev, 0x00003e60, 0x01300280);
  796. isp_write_reg(dev, 0x00000018, 0x00001000);
  797. isp_write_reg(dev, 0x00001200, 0x00000001); //why
  798. isp_write_reg(dev, 0x00000418, 0x00000001);
  799. isp_write_reg(dev, 0x00000400, 0x80100686);
  800. isp_write_reg(dev, 0x00000400, 0x80100097);
  801. isp_write_reg(dev, 0x00001300, 0x00000001);
  802. isp_write_reg(dev, 0x00001310, 0x00000038);
  803. isp_write_reg(dev, 0x000014e4, 0x00000238);
  804. isp_write_reg(dev, 0x00001600, 0x0000005c);
  805. isp_write_reg(dev, 0x00000704, 0x00c00222);
  806. isp_write_reg(dev, 0x00000708, 0x00a001e0);
  807. isp_write_reg(dev, 0x0000070c, 0x000a4023);
  808. isp_write_reg(dev, 0x00000710, 0x000a401e);
  809. isp_write_reg(dev, 0x00000714, 0x000b8001);
  810. isp_write_reg(dev, 0x00000718, 0x003540a0);
  811. isp_write_reg(dev, 0x0000071c, 0x00000050);
  812. isp_write_reg(dev, 0x00000720, 0x3aca095b);
  813. isp_write_reg(dev, 0x00000700, 0x00000c42);
  814. isp_info("end %s\n", __func__);
  815. }
  816. int isp_start_stream(struct isp_ic_dev *dev, u32 numFrames)
  817. {
  818. u32 isp_imsc, isp_ctrl;
  819. isp_info("enter %s\n", __func__);
  820. #ifdef ISP_PDAF
  821. isp_write_reg(dev, 0x5d00, 0x1);
  822. #endif
  823. isp_write_reg(dev, REG_ADDR(isp_sh_ctrl), 0x10);
  824. isp_write_reg(dev, REG_ADDR(isp_acq_nr_frames),
  825. (MRV_ISP_ACQ_NR_FRAMES_MASK & numFrames));
  826. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  827. isp_imsc |=
  828. (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK |
  829. MRV_ISP_IMSC_FRAME_IN_MASK | MRV_ISP_IMSC_PIC_SIZE_ERR_MASK | MRV_ISP_IMSC_FLASH_ON_MASK | MRV_ISP_IMSC_FLASH_OFF_MASK |
  830. MRV_ISP_IMSC_DATA_LOSS_MASK | MRV_ISP_IMSC_SHUTTER_OFF_MASK | MRV_ISP_MIS_VSM_END_MASK);
  831. /* isp_imsc |= (MRV_ISP_IMSC_FRAME_MASK | MRV_ISP_IMSC_DATA_LOSS_MASK | MRV_ISP_IMSC_FRAME_IN_MASK); */
  832. isp_write_reg(dev, REG_ADDR(isp_icr), 0xFFFFFFFF);
  833. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  834. isp_write_reg(dev, 0x00001320, 1);
  835. isp_write_reg(dev, 0x00001610, 1);
  836. #if 0/*add by shenwuyi for live sensor*/
  837. isp_write_reg(dev, 0x00002200, 0x00000000); //disable lsc
  838. isp_write_reg(dev, 0x000005bc, 0x00000001); //irq_enable
  839. isp_write_reg(dev, 0x00000538, 0x01000100); //awb_gain_gr
  840. isp_write_reg(dev, 0x0000053c, 0x02270220); //awb_gain_gc
  841. #endif
  842. /*isp_test_bt(dev);*/
  843. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  844. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 1);
  845. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 1);
  846. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  847. /*Set lsc tbl after isp enable*/
  848. if (dev->update_lsc_tbl) {
  849. isp_s_lsc_tbl(dev);
  850. dev->update_lsc_tbl = false;
  851. }
  852. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  853. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1);
  854. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  855. isp_info("exit %s\n", __func__);
  856. return 0;
  857. }
  858. int isp_stop_stream(struct isp_ic_dev *dev)
  859. {
  860. isp_info("enter %s\n", __func__);
  861. isp_write_reg(dev, REG_ADDR(isp_imsc), 0);
  862. isp_disable(dev);
  863. isp_info("exit %s\n", __func__);
  864. return 0;
  865. }
  866. int isp_s_cc(struct isp_ic_dev *dev)
  867. {
  868. struct isp_cc_context *cc = &dev->cc;
  869. u32 isp_ctrl, addr;
  870. int i;
  871. isp_info("enter %s\n", __func__);
  872. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  873. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CSM_Y_RANGE, cc->conv_range_y_full);
  874. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CSM_C_RANGE, cc->conv_range_c_full);
  875. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  876. if (cc->update_curve) {
  877. addr = REG_ADDR(isp_cc_coeff_0);
  878. for (i = 0; i < 9; i++) {
  879. isp_write_reg(dev, addr + i * 4,
  880. MRV_ISP_CC_COEFF_0_MASK & cc->lCoeff[i]);
  881. }
  882. }
  883. isp_info("exit %s\n", __func__);
  884. return 0;
  885. }
  886. int isp_s_xtalk(struct isp_ic_dev *dev)
  887. {
  888. struct isp_xtalk_context xtalk = *(&dev->xtalk);
  889. int i;
  890. /* isp_info("enter %s\n", __func__); */
  891. for (i = 0; i < 9; i++) {
  892. #ifdef ISP_CTM_0507 // Coefficient for cross talk matrix.Use bit 11,Values are 12-bit signed fixed-point numbers with 5 bit integer and 7 bit fractional part, ranging from -16 (0x800) to +15.992 (0x7FF).
  893. isp_write_reg(dev, REG_ADDR(cross_talk_coef_block_arr[i]),
  894. MRV_ISP_CT_COEFF_MASK & (xtalk.lCoeff[i] << 1));
  895. #else // Coefficient for cross talk matrix.Values are 11-bit signed fixed-point numbers with 4 bit integer and 7 bit fractional part, ranging from -8 (0x400) to +7.992 (0x3FF).
  896. isp_write_reg(dev, REG_ADDR(cross_talk_coef_block_arr[i]),
  897. MRV_ISP_CT_COEFF_MASK & xtalk.lCoeff[i]);
  898. #endif
  899. }
  900. isp_write_reg(dev, REG_ADDR(isp_ct_offset_r),
  901. (MRV_ISP_CT_OFFSET_R_MASK & xtalk.r));
  902. isp_write_reg(dev, REG_ADDR(isp_ct_offset_g),
  903. (MRV_ISP_CT_OFFSET_G_MASK & xtalk.g));
  904. isp_write_reg(dev, REG_ADDR(isp_ct_offset_b),
  905. (MRV_ISP_CT_OFFSET_B_MASK & xtalk.b));
  906. return 0;
  907. }
  908. int isp_enable_wb(struct isp_ic_dev *dev, bool bEnable)
  909. {
  910. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  911. isp_info("enter %s\n", __func__);
  912. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_AWB_ENABLE, bEnable);
  913. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  914. isp_info("exit %s\n", __func__);
  915. return 0;
  916. }
  917. int isp_enable_gamma_out(struct isp_ic_dev *dev, bool bEnable)
  918. {
  919. u32 isp_ctrl;
  920. struct isp_gamma_out_context *gamma = &dev->gamma_out;
  921. isp_info("enter %s\n", __func__);
  922. gamma->enableGamma = bEnable;
  923. if(gamma->changed || !is_isp_enable(dev))
  924. {
  925. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  926. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_OUT_ENABLE, bEnable);
  927. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  928. gamma->changed = false;
  929. } else {
  930. gamma->changed = true;
  931. }
  932. isp_info("exit %s\n", __func__);
  933. return 0;
  934. }
  935. int isp_s_gamma_out(struct isp_ic_dev *dev)
  936. {
  937. u32 isp_gamma_out_mode;
  938. int i;
  939. u32 isp_ctrl;
  940. struct isp_gamma_out_context *gamma = &dev->gamma_out;
  941. if(gamma->changed || !is_isp_enable(dev)) {
  942. isp_gamma_out_mode = isp_read_reg(dev, REG_ADDR(isp_gamma_out_mode));
  943. REG_SET_SLICE(isp_gamma_out_mode, MRV_ISP_EQU_SEGM, gamma->mode);
  944. isp_write_reg(dev, REG_ADDR(isp_gamma_out_mode), isp_gamma_out_mode);
  945. for (i = 0; i < 17; i++) {
  946. isp_write_reg(dev, REG_ADDR(gamma_out_y_block_arr[i]),
  947. MRV_ISP_ISP_GAMMA_OUT_Y_MASK & gamma->curve[i]);
  948. }
  949. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  950. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_OUT_ENABLE, gamma->enableGamma);
  951. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  952. gamma->changed = false;
  953. } else {
  954. gamma->changed = true;
  955. }
  956. return 0;
  957. }
  958. int isp_s_lsc_tbl(struct isp_ic_dev *dev)
  959. {
  960. int i, n;
  961. u32 isp_ctrl;
  962. u32 sram_addr;
  963. u32 isp_lsc_status;
  964. struct isp_lsc_context *lsc = (&dev->lsc);
  965. isp_debug("enter %s\n", __func__);
  966. /*need to set tbl after isp_ctrl enable In ISP8000NANO_V1802*/
  967. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  968. /* Enable isp to enable ram clock for write correct table to ram. */
  969. if (!(isp_ctrl & 0x01)) {
  970. dev->update_lsc_tbl = true;
  971. return 0;
  972. }
  973. isp_lsc_status = isp_read_reg(dev, REG_ADDR(isp_lsc_status));
  974. sram_addr = (isp_lsc_status & 0x2U) ? 0U : 153U;
  975. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_addr), sram_addr);
  976. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_addr), sram_addr);
  977. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_addr), sram_addr);
  978. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_addr), sram_addr);
  979. #ifdef ISP_LSC_V2
  980. for (n = 0; n < ((CAMERIC_MAX_LSC_SECTORS + 1) * (CAMERIC_MAX_LSC_SECTORS + 1)); n += CAMERIC_MAX_LSC_SECTORS + 1) {
  981. for (i = 0; i < (CAMERIC_MAX_LSC_SECTORS); i += 2) {
  982. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), (lsc->r[n + i] & 0xFFF) | ((lsc->r[n + i + 1] & 0xFFF) << 12) | ((lsc->r[n + i] >> 12) << 24) | ((lsc->r[n + i + 1] >> 12) << 28));
  983. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), (lsc->gr[n + i] & 0xFFF) | ((lsc->gr[n + i + 1] & 0xFFF) << 12) | ((lsc->gr[n + i] >> 12) << 24) | ((lsc->gr[n + i + 1] >> 12) << 28));
  984. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), (lsc->gb[n + i] & 0xFFF) | ((lsc->gb[n + i + 1] & 0xFFF) << 12) | ((lsc->gb[n + i] >> 12) << 24) | ((lsc->gb[n + i + 1] >> 12) << 28));
  985. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), (lsc->b[n + i] & 0xFFF) | ((lsc->b[n + i + 1] & 0xFFF) << 12) | ((lsc->b[n + i] >> 12) << 24) | ((lsc->b[n + i + 1] >> 12) << 28));
  986. }
  987. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), (lsc->r[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->r[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  988. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), (lsc->gr[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->gr[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  989. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), (lsc->gb[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->gb[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  990. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), (lsc->b[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->b[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  991. }
  992. #else
  993. for (n = 0;
  994. n <
  995. ((CAMERIC_MAX_LSC_SECTORS + 1) * (CAMERIC_MAX_LSC_SECTORS + 1));
  996. n += CAMERIC_MAX_LSC_SECTORS + 1) {
  997. /* 17 sectors with 2 values in one DWORD = 9 DWORDs (8 steps + 1 outside loop) */
  998. for (i = 0; i < (CAMERIC_MAX_LSC_SECTORS); i += 2) {
  999. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data),
  1000. lsc->r[n +
  1001. i] | (lsc->r[n + i + 1] << 12));
  1002. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data),
  1003. lsc->gr[n +
  1004. i] | (lsc->gr[n + i + 1] << 12));
  1005. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data),
  1006. lsc->gb[n +
  1007. i] | (lsc->gb[n + i + 1] << 12));
  1008. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data),
  1009. lsc->b[n +
  1010. i] | (lsc->b[n + i + 1] << 12));
  1011. }
  1012. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data),
  1013. lsc->r[n + CAMERIC_MAX_LSC_SECTORS]);
  1014. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data),
  1015. lsc->gr[n + CAMERIC_MAX_LSC_SECTORS]);
  1016. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data),
  1017. lsc->gb[n + CAMERIC_MAX_LSC_SECTORS]);
  1018. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data),
  1019. lsc->b[n + CAMERIC_MAX_LSC_SECTORS]);
  1020. }
  1021. #endif
  1022. isp_write_reg(dev, REG_ADDR(isp_lsc_table_sel),
  1023. (isp_lsc_status & 0x2U) ? 0U : 1U);
  1024. isp_info("exit %s\n", __func__);
  1025. return 0;
  1026. }
  1027. int isp_s_lsc_sec(struct isp_ic_dev *dev)
  1028. {
  1029. int i;
  1030. struct isp_lsc_context *lsc = (&dev->lsc);
  1031. /* isp_info("enter %s\n", __func__); */
  1032. for (i = 0; i < CAEMRIC_GRAD_TBL_SIZE; i += 2) {
  1033. isp_write_reg(dev, REG_ADDR(isp_lsc_xsize_01) + i * 2,
  1034. (lsc->x_size[i] & MRV_LSC_Y_SECT_SIZE_0_MASK) |
  1035. ((lsc->x_size[i + 1]
  1036. << MRV_LSC_X_SECT_SIZE_1_SHIFT)
  1037. & MRV_LSC_X_SECT_SIZE_1_MASK));
  1038. isp_write_reg(dev, REG_ADDR(isp_lsc_ysize_01) + i * 2,
  1039. (lsc->y_size[i] & MRV_LSC_Y_SECT_SIZE_0_MASK) |
  1040. ((lsc->y_size[i + 1]
  1041. << MRV_LSC_Y_SECT_SIZE_1_SHIFT)
  1042. & MRV_LSC_Y_SECT_SIZE_1_MASK));
  1043. isp_write_reg(dev, REG_ADDR(isp_lsc_xgrad_01) + i * 2,
  1044. (lsc->x_grad[i] & MRV_LSC_XGRAD_0_MASK) |
  1045. ((lsc->x_grad[i + 1]
  1046. << MRV_LSC_XGRAD_1_SHIFT)
  1047. & MRV_LSC_XGRAD_1_MASK));
  1048. isp_write_reg(dev, REG_ADDR(isp_lsc_ygrad_01) + i * 2,
  1049. (lsc->y_grad[i] & MRV_LSC_YGRAD_0_MASK) |
  1050. ((lsc->y_grad[i + 1]
  1051. << MRV_LSC_YGRAD_1_SHIFT)
  1052. & MRV_LSC_YGRAD_1_MASK));
  1053. }
  1054. return 0;
  1055. }
  1056. int isp_ioc_read_mis(struct isp_ic_dev *dev, void __user *args)
  1057. {
  1058. isp_mis_list_t* pCList = &dev->circle_list;
  1059. isp_mis_t mis_data;
  1060. u64 ary[2];
  1061. int ret = -1;
  1062. ret = isp_irq_read_circle_queue(&mis_data, pCList);
  1063. if (ret < 0) {
  1064. /*isp_info("%s can not dequeue mis data\n", __func__);*/
  1065. return ret;
  1066. }
  1067. /*isp_info("%s irq src %d val 0x%lx\n", __func__, mis_data.irq_src, mis_data.val);*/
  1068. ary[0] = mis_data.irq_src;
  1069. ary[1] = mis_data.val;
  1070. viv_check_retval(copy_to_user(args, ary, sizeof( ary)));
  1071. return 0;
  1072. }
  1073. static int isp_ioc_read_reg(struct isp_ic_dev *dev, void __user * args)
  1074. {
  1075. struct isp_reg_t reg;
  1076. viv_check_retval(copy_from_user(&reg, args, sizeof(reg)));
  1077. reg.val = isp_read_reg(dev, reg.offset);
  1078. viv_check_retval(copy_to_user(args, &reg, sizeof(reg)));
  1079. return 0;
  1080. }
  1081. static int isp_ioc_write_reg(struct isp_ic_dev *dev, void __user *args)
  1082. {
  1083. struct isp_reg_t reg;
  1084. viv_check_retval((copy_from_user(&reg, args, sizeof(reg))));
  1085. isp_write_reg(dev, reg.offset, reg.val);
  1086. return 0;
  1087. }
  1088. int isp_ioc_disable_isp_off(struct isp_ic_dev *dev, void __user *args)
  1089. {
  1090. u32 isp_imsc;
  1091. isp_info("enter %s\n", __func__);
  1092. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1093. isp_imsc &= ~MRV_ISP_IMSC_ISP_OFF_MASK;
  1094. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  1095. isp_info("exit %s\n", __func__);
  1096. return 0;
  1097. }
  1098. int isp_g_awbmean(struct isp_ic_dev *dev, struct isp_awb_mean *mean)
  1099. {
  1100. u32 reg = isp_read_reg(dev, REG_ADDR(isp_awb_mean));
  1101. /* isp_info("enter %s\n", __func__); */
  1102. mean->g = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_Y__G);
  1103. mean->b = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_CB__B);
  1104. mean->r = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_CR__R);
  1105. mean->no_white_count = isp_read_reg(dev, REG_ADDR(isp_awb_white_cnt));
  1106. return 0;
  1107. }
  1108. int isp_s_ee(struct isp_ic_dev *dev)
  1109. {
  1110. #ifndef ISP_EE_RY
  1111. //isp_err("unsupported function: %s\n", __func__);
  1112. return -EINVAL;
  1113. #else
  1114. struct isp_ee_context *ee = &dev->ee;
  1115. u32 isp_ee_ctrl = isp_read_reg(dev, REG_ADDR(isp_ee_ctrl));
  1116. u32 gain = 0;
  1117. isp_info("enter %s\n", __func__);
  1118. if (!ee->enable) {
  1119. isp_write_reg(dev, REG_ADDR(isp_ee_ctrl),
  1120. isp_ee_ctrl & ~EE_CTRL_ENABLE_MASK);
  1121. return 0;
  1122. }
  1123. REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_INPUT_SEL, ee->input_sel);
  1124. REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_SOURCE_STRENGTH, ee->src_strength);
  1125. REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_STRENGTH, ee->strength);
  1126. REG_SET_SLICE(gain, EE_UV_GAIN, ee->uv_gain);
  1127. REG_SET_SLICE(gain, EE_EDGE_GAIN, ee->edge_gain);
  1128. isp_write_reg(dev, REG_ADDR(isp_ee_y_gain), ee->y_gain);
  1129. isp_write_reg(dev, REG_ADDR(isp_ee_uv_gain), gain);
  1130. isp_write_reg(dev, REG_ADDR(isp_ee_ctrl),
  1131. isp_ee_ctrl | EE_CTRL_ENABLE_MASK);
  1132. isp_info("exit %s\n", __func__);
  1133. return 0;
  1134. #endif
  1135. }
  1136. int isp_s_exp(struct isp_ic_dev *dev)
  1137. {
  1138. struct isp_exp_context *exp = &dev->exp;
  1139. u32 isp_exp_ctrl = isp_read_reg(dev, REG_ADDR(isp_exp_ctrl));
  1140. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1141. isp_info("enter %s\n", __func__);
  1142. if (!exp->enable) {
  1143. REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_START, 0);
  1144. isp_write_reg(dev, REG_ADDR(isp_exp_ctrl), isp_exp_ctrl);
  1145. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1146. isp_imsc & ~MRV_ISP_IMSC_EXP_END_MASK);
  1147. return 0;
  1148. }
  1149. isp_write_reg(dev, REG_ADDR(isp_exp_h_offset),
  1150. (MRV_AE_ISP_EXP_H_OFFSET_MASK & exp->window.x));
  1151. isp_write_reg(dev, REG_ADDR(isp_exp_v_offset),
  1152. (MRV_AE_ISP_EXP_V_OFFSET_MASK & exp->window.y));
  1153. isp_write_reg(dev, REG_ADDR(isp_exp_h_size),
  1154. (MRV_AE_ISP_EXP_H_SIZE_MASK & exp->window.width));
  1155. isp_write_reg(dev, REG_ADDR(isp_exp_v_size),
  1156. (MRV_AE_ISP_EXP_V_SIZE_MASK & exp->window.height));
  1157. #ifdef ISP_AE_SHADOW_RY
  1158. isp_write_reg(dev, REG_ADDR(isp_exp_h_offset_shd),
  1159. (MRV_AE_ISP_EXP_H_OFFSET_MASK & exp->window.x));
  1160. isp_write_reg(dev, REG_ADDR(isp_exp_v_offset_shd),
  1161. (MRV_AE_ISP_EXP_V_OFFSET_MASK & exp->window.y));
  1162. isp_write_reg(dev, REG_ADDR(isp_exp_h_size_shd),
  1163. (MRV_AE_ISP_EXP_H_SIZE_MASK & exp->window.width));
  1164. isp_write_reg(dev, REG_ADDR(isp_exp_v_size_shd),
  1165. (MRV_AE_ISP_EXP_V_SIZE_MASK & exp->window.height));
  1166. #endif
  1167. REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_MEAS_MODE, exp->mode);
  1168. REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_START, 1);
  1169. isp_write_reg(dev, REG_ADDR(isp_exp_ctrl), isp_exp_ctrl);
  1170. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1171. isp_imsc | MRV_ISP_IMSC_EXP_END_MASK);
  1172. isp_info("exit %s\n", __func__);
  1173. return 0;
  1174. }
  1175. int isp_s_hdrexp(struct isp_ic_dev *dev)
  1176. {
  1177. struct isp_exp_context *hdrexp = &dev->hdrexp;
  1178. u32 isp_hdr_exp_conf = isp_read_reg(dev, REG_ADDR(isp_hdr_exp_conf));
  1179. u32 isp_stitching_imsc = isp_read_reg(dev, REG_ADDR(isp_stitching_imsc));
  1180. isp_info("enter %s\n", __func__);
  1181. if (!dev->hdrexp.enable) {
  1182. isp_info("%s, hdr disabled\n",__func__);
  1183. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_START, 0);
  1184. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_conf), isp_hdr_exp_conf);
  1185. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc & ~0x38);
  1186. return 0;
  1187. }
  1188. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_h_offset),
  1189. (MRV_ISP_HDR_EXP_H_OFFSET_MASK & hdrexp->window.x));
  1190. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_v_offset),
  1191. (MRV_ISP_HDR_EXP_V_OFFSET_MASK & hdrexp->window.y));
  1192. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_h_size),
  1193. (MRV_ISP_HDR_EXP_H_SIZE_MASK & hdrexp->window.width));
  1194. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_v_size),
  1195. (MRV_ISP_HDR_EXP_V_SIZE_MASK & hdrexp->window.height));
  1196. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_MEAS_MODE, hdrexp->mode);
  1197. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_SRC_SEL, 1); //hardware only support 1
  1198. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_START, 1);
  1199. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_conf), isp_hdr_exp_conf);
  1200. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc | 0x38);
  1201. return 0;
  1202. }
  1203. int isp_g_expmean(struct isp_ic_dev *dev, u8 *mean)
  1204. {
  1205. int i = 0;
  1206. /* isp_info("enter %s\n", __func__); */
  1207. if (!dev || !mean)
  1208. return -EINVAL;
  1209. for (; i < 25; i++) {
  1210. mean[i] = isp_read_reg(dev, REG_ADDR(isp_exp_mean_00) + i * 4);
  1211. }
  1212. return 0;
  1213. }
  1214. int isp_g_hdrexpmean(struct isp_ic_dev *dev, u8 * mean)
  1215. {
  1216. int i = 0;
  1217. isp_info("enter %s\n", __func__);
  1218. if (!dev || !mean)
  1219. return -EINVAL;
  1220. for (; i < 75; i++) {
  1221. mean[i] = isp_read_reg(dev, REG_ADDR(isp_hdr_exp_statistics[i]));
  1222. }
  1223. return 0;
  1224. }
  1225. #ifdef ISP_HIST256
  1226. #define HIST_BIN_TOTAL 256
  1227. #else
  1228. #define HIST_BIN_TOTAL 16
  1229. #endif
  1230. int isp_s_hist(struct isp_ic_dev *dev)
  1231. {
  1232. struct isp_hist_context *hist = &dev->hist;
  1233. #ifdef ISP_HIST256_RY
  1234. u32 isp_hist256_prop = isp_read_reg(dev, REG_ADDR(isp_hist256_prop));
  1235. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1236. int i;
  1237. if (!hist->enable) {
  1238. REG_SET_SLICE(isp_hist256_prop, MRV_HIST_MODE,
  1239. MRV_HIST_MODE_NONE);
  1240. isp_write_reg(dev, REG_ADDR(isp_hist256_prop),
  1241. isp_hist256_prop);
  1242. //isp_write_reg(dev, REG_ADDR(isp_imsc),
  1243. // isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1244. return 0;
  1245. }
  1246. isp_write_reg(dev, REG_ADDR(isp_hist256_h_offs),
  1247. (MRV_HIST_H_OFFSET_MASK & hist->window.x));
  1248. isp_write_reg(dev, REG_ADDR(isp_hist256_v_offs),
  1249. (MRV_HIST_V_OFFSET_MASK & hist->window.y));
  1250. isp_write_reg(dev, REG_ADDR(isp_hist256_h_size),
  1251. (MRV_HIST_H_SIZE_MASK & hist->window.width));
  1252. isp_write_reg(dev, REG_ADDR(isp_hist256_v_size),
  1253. (MRV_HIST_V_SIZE_MASK & hist->window.height));
  1254. for (i = 0; i < 24; i += 4) {
  1255. isp_write_reg(dev, REG_ADDR(isp_hist256_weight_00to30) + i,
  1256. hist->weight[i +
  1257. 0] | (hist->weight[i +
  1258. 1] << 8) |
  1259. (hist->weight[i + 2] << 16) | (hist->weight[i +
  1260. 3] <<
  1261. 24));
  1262. }
  1263. isp_write_reg(dev, REG_ADDR(isp_hist256_weight_44), hist->weight[24]);
  1264. REG_SET_SLICE(isp_hist256_prop, MRV_HIST_STEPSIZE, hist->step_size);
  1265. REG_SET_SLICE(isp_hist256_prop, MRV_HIST_MODE, hist->mode);
  1266. isp_write_reg(dev, REG_ADDR(isp_hist256_prop), isp_hist256_prop);
  1267. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1268. isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1269. #else
  1270. u32 isp_hist_prop = isp_read_reg(dev, REG_ADDR(isp_hist_prop));
  1271. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1272. int i;
  1273. isp_info("enter %s\n", __func__);
  1274. if (!hist->enable) {
  1275. REG_SET_SLICE(isp_hist_prop, MRV_HIST_MODE, MRV_HIST_MODE_NONE);
  1276. isp_write_reg(dev, REG_ADDR(isp_hist_prop), isp_hist_prop);
  1277. //isp_write_reg(dev, REG_ADDR(isp_imsc),
  1278. // isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1279. return 0;
  1280. }
  1281. isp_write_reg(dev, REG_ADDR(isp_hist_h_offs),
  1282. (MRV_HIST_H_OFFSET_MASK & hist->window.x));
  1283. isp_write_reg(dev, REG_ADDR(isp_hist_v_offs),
  1284. (MRV_HIST_V_OFFSET_MASK & hist->window.y));
  1285. isp_write_reg(dev, REG_ADDR(isp_hist_h_size),
  1286. (MRV_HIST_H_SIZE_MASK & hist->window.width));
  1287. isp_write_reg(dev, REG_ADDR(isp_hist_v_size),
  1288. (MRV_HIST_V_SIZE_MASK & hist->window.height));
  1289. for (i = 0; i < 24; i += 4) {
  1290. isp_write_reg(dev, REG_ADDR(isp_hist_weight_00to30) + i,
  1291. hist->weight[i + 0] |
  1292. (hist->weight[i + 1] << 8) |
  1293. (hist->weight[i + 2] << 16) |
  1294. (hist->weight[i + 3] << 24));
  1295. }
  1296. isp_write_reg(dev, REG_ADDR(isp_hist_weight_44), hist->weight[24]);
  1297. REG_SET_SLICE(isp_hist_prop, MRV_HIST_STEPSIZE, hist->step_size);
  1298. REG_SET_SLICE(isp_hist_prop, MRV_HIST_MODE, hist->mode);
  1299. isp_write_reg(dev, REG_ADDR(isp_hist_prop), isp_hist_prop);
  1300. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1301. isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1302. isp_info("exit %s\n", __func__);
  1303. #endif
  1304. return 0;
  1305. }
  1306. int isp_s_hdrhist(struct isp_ic_dev *dev)
  1307. {
  1308. struct isp_hist_context *hdrhist = &dev->hdrhist;
  1309. u32 isp_hdr_hist_prop = isp_read_reg(dev, REG_ADDR(isp_hdr_hist_prop));
  1310. u32 isp_stitching_imsc = isp_read_reg(dev, REG_ADDR(isp_stitching_imsc));
  1311. isp_info("enter %s\n", __func__);
  1312. if (!dev->hdrhist.enable) {
  1313. isp_info("%s, hdr disable\n", __func__);
  1314. REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_MODE, MRV_HIST_MODE_NONE);
  1315. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_prop), isp_hdr_hist_prop);
  1316. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc),
  1317. isp_stitching_imsc & ~0x1c0);
  1318. return 0;
  1319. }
  1320. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_h_offs),
  1321. (MRV_HIST_H_OFFSET_MASK & hdrhist->window.x));
  1322. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_v_offs),
  1323. (MRV_HIST_V_OFFSET_MASK & hdrhist->window.y));
  1324. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_h_size),
  1325. (MRV_HIST_H_SIZE_MASK & hdrhist->window.width));
  1326. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_v_size),
  1327. (MRV_HIST_V_SIZE_MASK & hdrhist->window.height));
  1328. REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_STEPSIZE, hdrhist->step_size);
  1329. REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_MODE, hdrhist->mode);
  1330. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_prop), isp_hdr_hist_prop);
  1331. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc | 0x1c0);
  1332. return 0;
  1333. }
  1334. int isp_g_histmean(struct isp_ic_dev *dev, u32 *mean)
  1335. {
  1336. int i = 0;
  1337. /* isp_info("enter %s\n", __func__); */
  1338. if (!dev || !mean)
  1339. return -EINVAL;
  1340. #ifdef ISP_HIST256_RY
  1341. for (; i < HIST_BIN_TOTAL; i++) {
  1342. mean[i] = isp_read_reg(dev, REG_ADDR(isp_hist256_bin_n));
  1343. }
  1344. #else
  1345. for (; i < HIST_BIN_TOTAL; i++) {
  1346. mean[i] = isp_read_reg(dev,
  1347. REG_ADDR(histogram_measurement_result_arr[i]));
  1348. }
  1349. #endif
  1350. return 0;
  1351. }
  1352. int isp_g_hdrhistmean(struct isp_ic_dev *dev, u32 * mean)
  1353. {
  1354. int i = 0;
  1355. isp_info("enter %s\n", __func__);
  1356. if (!dev || !mean)
  1357. return -EINVAL;
  1358. // size is fixed 48 now, contain 3 channels
  1359. for (; i < 48; i++) {
  1360. mean[i] = isp_read_reg(dev, REG_ADDR(isp_hdr_hist_statistics[i]));
  1361. }
  1362. return 0;
  1363. }
  1364. int isp_s_hist64(struct isp_ic_dev *dev)
  1365. {
  1366. #ifndef ISP_HIST64_RY
  1367. //pr_err("Not supported hist64 module\n");
  1368. return -1;
  1369. #else
  1370. struct isp_hist64_context *hist64 = &dev->hist64;
  1371. u32 isp64_hist_prop = isp_read_reg(dev, REG_ADDR(isp64_hist_prop));
  1372. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1373. u32 isp64_hist_subsampling = isp_read_reg(dev, REG_ADDR(isp64_hist_subsampling));
  1374. u32 isp64_hist_sample_range = isp_read_reg(dev, REG_ADDR(isp64_hist_sample_range));
  1375. u32 isp64_hist_coeff_r = 0, isp64_hist_coeff_g = 0, isp64_hist_coeff_b = 0;
  1376. int i;
  1377. if (!hist64->enable) {
  1378. REG_SET_SLICE(isp64_hist_prop, MRV_HIST_MODE,
  1379. MRV_HIST_MODE_NONE);
  1380. isp_write_reg(dev, REG_ADDR(isp64_hist_prop),
  1381. isp64_hist_prop);
  1382. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1383. isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1384. //isp_write_reg(dev, REG_ADDR(isp64_hist_ctrl),
  1385. /// hist64->enable & ~MRV_HIST_UPDATE_ENABLE_MASK);
  1386. return 0;
  1387. }
  1388. isp_write_reg(dev, REG_ADDR(isp64_hist_h_offs),
  1389. (MRV_HIST_H_OFFSET_MASK & hist64->window.x));
  1390. isp_write_reg(dev, REG_ADDR(isp64_hist_v_offs),
  1391. (MRV_HIST_V_OFFSET_MASK & hist64->window.y));
  1392. isp_write_reg(dev, REG_ADDR(isp64_hist_h_size),
  1393. (MRV_HIST_H_SIZE_MASK & hist64->window.width));
  1394. isp_write_reg(dev, REG_ADDR(isp64_hist_v_size),
  1395. (MRV_HIST_V_SIZE_MASK & hist64->window.height));
  1396. for (i = 0; i < 24; i += 4) {
  1397. isp_write_reg(dev, REG_ADDR(isp64_hist_weight_00to30) + i,
  1398. hist64->weight[i +
  1399. 0] | (hist64->weight[i +
  1400. 1] << 8) |
  1401. (hist64->weight[i + 2] << 16) | (hist64->weight[i +
  1402. 3] <<
  1403. 24));
  1404. }
  1405. isp_write_reg(dev, REG_ADDR(isp64_hist_weight_44), hist64->weight[24]);
  1406. REG_SET_SLICE(isp64_hist_prop, MRV_HIST_CHANNEL_SELECT, hist64->channel);
  1407. REG_SET_SLICE(isp64_hist_prop, MRV_HIST_MODE, hist64->mode);
  1408. REG_SET_SLICE(isp64_hist_subsampling, MRV_HIST_V_STEPSIZE, hist64->vStepSize);
  1409. REG_SET_SLICE(isp64_hist_subsampling, MRV_HIST_H_STEP_INC, hist64->hStepInc);
  1410. REG_SET_SLICE(isp64_hist_sample_range, MRV_HIST_SAMPLE_OFFSET, hist64->sample_offset);
  1411. REG_SET_SLICE(isp64_hist_sample_range, MRV_HIST_SAMPLE_SHIFT, hist64->sample_shift);
  1412. REG_SET_SLICE(isp64_hist_coeff_r, MRV_HIST_COEFF_R, hist64->r_coeff);
  1413. REG_SET_SLICE(isp64_hist_coeff_g, MRV_HIST_COEFF_G, hist64->g_coeff);
  1414. REG_SET_SLICE(isp64_hist_coeff_b, MRV_HIST_COEFF_B, hist64->b_coeff);
  1415. isp_write_reg(dev, REG_ADDR(isp64_hist_subsampling), isp64_hist_subsampling);
  1416. isp_write_reg(dev, REG_ADDR(isp64_hist_sample_range), isp64_hist_sample_range);
  1417. isp_write_reg(dev, REG_ADDR(isp64_hist_prop), isp64_hist_prop);
  1418. isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_r), isp64_hist_coeff_r);
  1419. isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_g), isp64_hist_coeff_g);
  1420. isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_b), isp64_hist_coeff_b);
  1421. isp_write_reg(dev, REG_ADDR(isp64_hist_ctrl),
  1422. hist64->enable);
  1423. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1424. isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1425. return 0;
  1426. #endif
  1427. }
  1428. #define HIST64_BIN_TOTAL 32
  1429. int isp_g_hist64mean(struct isp_ic_dev *dev, u32 *mean)
  1430. {
  1431. #ifndef ISP_HIST64_RY
  1432. //pr_err("Not supported hist64 module\n");
  1433. return -1;
  1434. #else
  1435. int i = 0;
  1436. isp_info("enter %s\n", __func__);
  1437. if (!dev || !mean)
  1438. return -EINVAL;
  1439. for (; i < HIST64_BIN_TOTAL; i++) {
  1440. mean[i] = isp_read_reg(dev,
  1441. REG_ADDR(isp64_histogram_measurement_result_arr[i]));
  1442. }
  1443. isp_info("exit %s\n", __func__);
  1444. return 0;
  1445. #endif
  1446. }
  1447. int isp_g_hist64_vstart_status(struct isp_ic_dev *dev, u32 *status)
  1448. {
  1449. #ifndef ISP_HIST64_RY
  1450. //pr_err("Not supported hist64 module\n");
  1451. return -1;
  1452. #else
  1453. /* isp_info("enter %s\n", __func__); */
  1454. if (!dev || !status)
  1455. return -EINVAL;
  1456. *status = isp_read_reg(dev, REG_ADDR(isp64_hist_vstart_status));
  1457. return 0;
  1458. #endif
  1459. }
  1460. int isp_update_hist64(struct isp_ic_dev *dev)
  1461. {
  1462. #ifndef ISP_HIST64_RY
  1463. //pr_err("Not supported hist64\n");
  1464. return -1;
  1465. #else
  1466. struct isp_hist64_context* hist64 =&dev->hist64;
  1467. isp_write_reg(dev, REG_ADDR(isp64_hist_forced_upd_start_line),hist64->forced_upd_start_line);
  1468. isp_write_reg(dev, REG_ADDR(isp64_hist_forced_update), hist64->forced_upd);
  1469. return 0;
  1470. #endif
  1471. }
  1472. int isp_s_ge(struct isp_ic_dev *dev)
  1473. {
  1474. #ifndef ISP_GREENEQUILIBRATE
  1475. //isp_err("unsupported function %s\n", __func__);
  1476. return -1;
  1477. #else
  1478. struct isp_ge_context *ge = &dev->ge;
  1479. u32 green_equilibrate_ctrl =
  1480. isp_read_reg(dev, REG_ADDR(green_equilibrate_ctrl));
  1481. u32 green_equilibrate_hcnt_dummy = 0;
  1482. isp_info("enter %s\n", __func__);
  1483. if (!ge->enable) {
  1484. REG_SET_SLICE(green_equilibrate_ctrl,
  1485. ISP_GREEN_EQUILIBTATE_ENABLE, 0);
  1486. isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl),
  1487. green_equilibrate_ctrl);
  1488. return 0;
  1489. }
  1490. REG_SET_SLICE(green_equilibrate_ctrl, ISP_GREEN_EQUILIBTATE_TH,
  1491. ge->threshold);
  1492. REG_SET_SLICE(green_equilibrate_ctrl, ISP_GREEN_EQUILIBTATE_ENABLE, 1);
  1493. REG_SET_SLICE(green_equilibrate_hcnt_dummy,
  1494. ISP_GREEN_EQUILIBTATE_HCNT_DUMMY, ge->h_dummy);
  1495. isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl),
  1496. green_equilibrate_ctrl);
  1497. isp_write_reg(dev, REG_ADDR(green_equilibrate_hcnt_dummy),
  1498. green_equilibrate_hcnt_dummy);
  1499. isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl_shd),
  1500. green_equilibrate_ctrl);
  1501. isp_info("exit %s\n", __func__);
  1502. return 0;
  1503. #endif
  1504. }
  1505. int isp_s_ca(struct isp_ic_dev *dev)
  1506. {
  1507. #ifndef ISP_CA_RY
  1508. //isp_err("unsupported function %s\n", __func__);
  1509. return -1;
  1510. #else
  1511. struct isp_ca_context *ca = &dev->ca;
  1512. u32 isp_curve_ctrl = isp_read_reg(dev, REG_ADDR(isp_curve_ctrl));
  1513. // u32 isp_curve_lut_x_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_x_addr));
  1514. // u32 isp_curve_lut_luma_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_luma_addr));
  1515. // u32 isp_curve_lut_chroma_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_chroma_addr));
  1516. // u32 isp_curve_lut_shift_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_shift_addr));
  1517. int i = 0;
  1518. isp_info("enter %s\n", __func__);
  1519. if (!ca->enable) {
  1520. REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_ENABLE, 0);
  1521. isp_write_reg(dev, REG_ADDR(isp_curve_ctrl), isp_curve_ctrl);
  1522. return 0;
  1523. }
  1524. isp_write_reg(dev, REG_ADDR(isp_curve_lut_x_addr), 0);
  1525. isp_write_reg(dev, REG_ADDR(isp_curve_lut_luma_addr), 0);
  1526. isp_write_reg(dev, REG_ADDR(isp_curve_lut_chroma_addr), 0);
  1527. isp_write_reg(dev, REG_ADDR(isp_curve_lut_shift_addr), 0);
  1528. for (i = 0; i < CA_CURVE_DATA_TABLE_LEN; i++) {
  1529. isp_write_reg(dev, REG_ADDR(isp_curve_lut_x_write_data),
  1530. dev->ca.lut_x[i]);
  1531. isp_write_reg(dev, REG_ADDR(isp_curve_lut_luma_write_data),
  1532. dev->ca.lut_luma[i]);
  1533. isp_write_reg(dev, REG_ADDR(isp_curve_lut_chroma_write_data),
  1534. dev->ca.lut_chroma[i]);
  1535. isp_write_reg(dev, REG_ADDR(isp_curve_lut_shift_write_data),
  1536. dev->ca.lut_shift[i]);
  1537. }
  1538. REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_MODE, dev->ca.mode);
  1539. REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_ENABLE, 1);
  1540. isp_write_reg(dev, REG_ADDR(isp_curve_ctrl), isp_curve_ctrl);
  1541. isp_info("exit %s\n", __func__);
  1542. return 0;
  1543. #endif
  1544. }
  1545. int isp_s_dpcc(struct isp_ic_dev *dev)
  1546. {
  1547. struct isp_dpcc_context *dpcc = &dev->dpcc;
  1548. const u32 reg_gap = 20;
  1549. int i;
  1550. u32 isp_dpcc_mode = isp_read_reg(dev, REG_ADDR(isp_dpcc_mode));
  1551. isp_info("enter %s\n", __func__);
  1552. if (!dpcc->enable) {
  1553. REG_SET_SLICE(isp_dpcc_mode, MRV_DPCC_ISP_DPCC_ENABLE, 0);
  1554. } else {
  1555. REG_SET_SLICE(isp_dpcc_mode, MRV_DPCC_ISP_DPCC_ENABLE, 1);
  1556. }
  1557. isp_write_reg(dev, REG_ADDR(isp_dpcc_mode), dpcc->mode);
  1558. isp_write_reg(dev, REG_ADDR(isp_dpcc_output_mode), dpcc->outmode);
  1559. isp_write_reg(dev, REG_ADDR(isp_dpcc_set_use), dpcc->set_use);
  1560. for (i = 0; i < 3; i++) {
  1561. isp_write_reg(dev, REG_ADDR(isp_dpcc_methods_set_1) + i * 4,
  1562. 0x1FFF & dpcc->methods_set[i]);
  1563. isp_write_reg(dev,
  1564. REG_ADDR(isp_dpcc_line_thresh_1) + i * reg_gap,
  1565. 0xFFFF & dpcc->params[i].line_thresh);
  1566. isp_write_reg(dev,
  1567. REG_ADDR(isp_dpcc_line_mad_fac_1) + i * reg_gap,
  1568. 0x3F3F & dpcc->params[i].line_mad_fac);
  1569. isp_write_reg(dev, REG_ADDR(isp_dpcc_pg_fac_1) + i * reg_gap,
  1570. 0x3F3F & dpcc->params[i].pg_fac);
  1571. isp_write_reg(dev,
  1572. REG_ADDR(isp_dpcc_rnd_thresh_1) + i * reg_gap,
  1573. 0xFFFF & dpcc->params[i].rnd_thresh);
  1574. isp_write_reg(dev, REG_ADDR(isp_dpcc_rg_fac_1) + i * reg_gap,
  1575. 0x3F3F & dpcc->params[i].rg_fac);
  1576. }
  1577. isp_write_reg(dev, REG_ADDR(isp_dpcc_ro_limits), dpcc->ro_limits);
  1578. isp_write_reg(dev, REG_ADDR(isp_dpcc_rnd_offs), dpcc->rnd_offs);
  1579. isp_write_reg(dev, REG_ADDR(isp_dpcc_mode), isp_dpcc_mode);
  1580. isp_info("exit %s\n", __func__);
  1581. return 0;
  1582. }
  1583. int isp_s_flt(struct isp_ic_dev *dev)
  1584. {
  1585. struct flt_denoise_type {
  1586. u32 thresh_sh0;
  1587. u32 thresh_sh1;
  1588. u32 thresh_bl0;
  1589. u32 thresh_bl1;
  1590. u32 stage_select;
  1591. u32 vmode;
  1592. u32 hmode;
  1593. };
  1594. struct flt_sharpen_type {
  1595. u32 fac_sh0;
  1596. u32 fac_sh1;
  1597. u32 fac_mid;
  1598. u32 fac_bl0;
  1599. u32 fac_bl1;
  1600. };
  1601. static struct flt_denoise_type denoise_tbl[] = {
  1602. {0, 0, 0, 0, 6, MRV_FILT_FILT_CHR_V_MODE_STATIC8,
  1603. MRV_FILT_FILT_CHR_H_MODE_BYPASS},
  1604. {18, 33, 8, 2, 6, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1605. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1606. {26, 44, 13, 5, 4, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1607. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1608. {36, 51, 23, 10, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1609. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1610. {41, 67, 26, 15, 3, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1611. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1612. {75, 10, 50, 20, 3, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1613. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1614. {90, 120, 60, 26, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1615. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1616. {120, 150, 80, 51, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1617. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1618. {170, 200, 140, 100, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1619. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1620. {250, 300, 180, 150, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1621. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1622. {1023, 1023, 1023, 1023, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1623. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1624. {1023, 1023, 1023, 1023, 0, MRV_FILT_FILT_CHR_V_MODE_BYPASS,
  1625. MRV_FILT_FILT_CHR_H_MODE_BYPASS},
  1626. };
  1627. static struct flt_sharpen_type sharpen_tbl[] = {
  1628. {0x4, 0x4, 0x4, 0x2, 0x0},
  1629. {0x7, 0x8, 0x6, 0x2, 0x0},
  1630. {0xA, 0xC, 0x8, 0x4, 0x0},
  1631. {0xC, 0x10, 0xA, 0x6, 0x2},
  1632. {0x16, 0x16, 0xC, 0x8, 0x4},
  1633. {0x14, 0x1B, 0x10, 0xA, 0x4},
  1634. {0x1A, 0x20, 0x13, 0xC, 0x6},
  1635. {0x1E, 0x26, 0x17, 0x10, 0x8},
  1636. {0x24, 0x2C, 0x1D, 0x15, 0x0D},
  1637. {0x2A, 0x30, 0x22, 0x1A, 0x14},
  1638. {0x30, 0x3F, 0x28, 0x24, 0x20},
  1639. };
  1640. // isp_info("enter %s\n", __func__);
  1641. if(dev->flt.changed || !is_isp_enable(dev))
  1642. {
  1643. struct isp_flt_context *flt = &dev->flt;
  1644. u32 isp_flt_mode = isp_read_reg(dev, REG_ADDR(isp_filt_mode));
  1645. if (!flt->enable) {
  1646. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_ENABLE, 0);
  1647. isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode);
  1648. return 0;
  1649. }
  1650. if (flt->denoise >= 0) {
  1651. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_sh0),
  1652. denoise_tbl[flt->denoise].thresh_sh0);
  1653. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_sh1),
  1654. denoise_tbl[flt->denoise].thresh_sh1);
  1655. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_bl0),
  1656. denoise_tbl[flt->denoise].thresh_bl0);
  1657. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_bl1),
  1658. denoise_tbl[flt->denoise].thresh_bl1);
  1659. REG_SET_SLICE(isp_flt_mode, MRV_FILT_STAGE1_SELECT,
  1660. denoise_tbl[flt->denoise].stage_select);
  1661. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_CHR_V_MODE,
  1662. denoise_tbl[flt->denoise].vmode);
  1663. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_CHR_H_MODE,
  1664. denoise_tbl[flt->denoise].hmode);
  1665. }
  1666. if (flt->sharpen >= 0) {
  1667. isp_write_reg(dev, REG_ADDR(isp_filt_fac_sh0),
  1668. sharpen_tbl[flt->sharpen].fac_sh0);
  1669. isp_write_reg(dev, REG_ADDR(isp_filt_fac_sh1),
  1670. sharpen_tbl[flt->sharpen].fac_sh1);
  1671. isp_write_reg(dev, REG_ADDR(isp_filt_fac_mid),
  1672. sharpen_tbl[flt->sharpen].fac_mid);
  1673. isp_write_reg(dev, REG_ADDR(isp_filt_fac_bl0),
  1674. sharpen_tbl[flt->sharpen].fac_bl0);
  1675. isp_write_reg(dev, REG_ADDR(isp_filt_fac_bl1),
  1676. sharpen_tbl[flt->sharpen].fac_bl1);
  1677. }
  1678. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_MODE,
  1679. MRV_FILT_FILT_MODE_DYNAMIC);
  1680. isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode);
  1681. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_ENABLE, 1);
  1682. isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode);
  1683. isp_write_reg(dev, REG_ADDR(isp_filt_lum_weight), 0x00032040);
  1684. dev->flt.changed = false;
  1685. } else {
  1686. dev->flt.changed = true;
  1687. }
  1688. isp_info("exit %s\n", __func__);
  1689. return 0;
  1690. }
  1691. int isp_s_cac(struct isp_ic_dev *dev)
  1692. {
  1693. struct isp_cac_context *cac = &dev->cac;
  1694. u32 val = 0;
  1695. u32 isp_cac_ctrl = isp_read_reg(dev, REG_ADDR(isp_cac_ctrl));
  1696. isp_info("enter %s\n", __func__);
  1697. if (!cac->enable) {
  1698. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_CAC_EN, 0);
  1699. isp_write_reg(dev, REG_ADDR(isp_cac_ctrl), isp_cac_ctrl);
  1700. return 0;
  1701. }
  1702. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_H_CLIP_MODE, cac->hmode);
  1703. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_V_CLIP_MODE, cac->vmode);
  1704. isp_write_reg(dev, REG_ADDR(isp_cac_count_start),
  1705. cac->hstart | (cac->vstart << 16));
  1706. isp_write_reg(dev, REG_ADDR(isp_cac_a), cac->ar | (cac->ab << 16));
  1707. isp_write_reg(dev, REG_ADDR(isp_cac_b), cac->br | (cac->bb << 16));
  1708. isp_write_reg(dev, REG_ADDR(isp_cac_c), cac->cr | (cac->cb << 16));
  1709. REG_SET_SLICE(val, MRV_CAC_X_NS, cac->xns);
  1710. REG_SET_SLICE(val, MRV_CAC_X_NF, cac->xnf);
  1711. isp_write_reg(dev, REG_ADDR(isp_cac_x_norm), val);
  1712. val = 0;
  1713. REG_SET_SLICE(val, MRV_CAC_Y_NS, cac->yns);
  1714. REG_SET_SLICE(val, MRV_CAC_Y_NF, cac->ynf);
  1715. isp_write_reg(dev, REG_ADDR(isp_cac_y_norm), val);
  1716. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_CAC_EN, 1);
  1717. isp_write_reg(dev, REG_ADDR(isp_cac_ctrl), isp_cac_ctrl);
  1718. isp_info("exit %s\n", __func__);
  1719. return 0;
  1720. }
  1721. int isp_s_deg(struct isp_ic_dev *dev)
  1722. {
  1723. struct isp_deg_context *deg = &dev->deg;
  1724. int i;
  1725. u32 isp_gamma_dx_lo = 0;
  1726. u32 isp_gamma_dx_hi = 0;
  1727. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  1728. isp_info("enter %s\n", __func__);
  1729. if (!deg->enable) {
  1730. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_IN_ENABLE, 0);
  1731. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  1732. return 0;
  1733. }
  1734. for (i = 0; i < 8; i++) {
  1735. isp_gamma_dx_lo |= deg->segment[i] << (i * 4);
  1736. isp_gamma_dx_hi |= deg->segment[i + 8] << (i * 4);
  1737. }
  1738. isp_write_reg(dev, REG_ADDR(isp_gamma_dx_lo), isp_gamma_dx_lo);
  1739. isp_write_reg(dev, REG_ADDR(isp_gamma_dx_hi), isp_gamma_dx_hi);
  1740. for (i = 0; i < 17; i++) {
  1741. isp_write_reg(dev, REG_ADDR(degamma_r_y_block_arr[i]),
  1742. deg->r[i]);
  1743. isp_write_reg(dev, REG_ADDR(degamma_g_y_block_arr[i]),
  1744. deg->g[i]);
  1745. isp_write_reg(dev, REG_ADDR(degamma_b_y_block_arr[i]),
  1746. deg->b[i]);
  1747. }
  1748. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_IN_ENABLE, 1);
  1749. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  1750. isp_info("exit %s\n", __func__);
  1751. return 0;
  1752. }
  1753. static u32 get_eff_coeff(int decimal)
  1754. {
  1755. u32 value = 0;
  1756. if (decimal <= -6)
  1757. value = 15;
  1758. else if (decimal <= -3)
  1759. value = 14;
  1760. else if (decimal == -2)
  1761. value = 13;
  1762. else if (decimal == -1)
  1763. value = 12;
  1764. else if (decimal == 0)
  1765. value = 0;
  1766. else if (decimal == 1)
  1767. value = 8;
  1768. else if (decimal == 2)
  1769. value = 9;
  1770. else if (decimal < 6)
  1771. value = 10;
  1772. else
  1773. value = 11;
  1774. return value;
  1775. }
  1776. int isp_s_ie(struct isp_ic_dev *dev)
  1777. {
  1778. struct isp_ie_context *ie = &dev->ie;
  1779. u32 img_eff_ctrl = isp_read_reg(dev, REG_ADDR(img_eff_ctrl));
  1780. u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl));
  1781. u32 vi_ircl = isp_read_reg(dev, REG_ADDR(vi_ircl));
  1782. u32 img_eff_tint = isp_read_reg(dev, REG_ADDR(img_eff_tint));
  1783. u32 img_eff_color_sel = isp_read_reg(dev, REG_ADDR(img_eff_color_sel));
  1784. u32 mat[9];
  1785. u32 sharpen = 0;
  1786. int i;
  1787. isp_info("enter %s\n", __func__);
  1788. REG_SET_SLICE(vi_ircl, MRV_VI_IE_SOFT_RST, 1);
  1789. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  1790. if (!ie->enable) {
  1791. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_CFG_UPD,
  1792. MRV_IMGEFF_CFG_UPD_UPDATE);
  1793. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_BYPASS_MODE,
  1794. MRV_IMGEFF_BYPASS_MODE_BYPASS);
  1795. REG_SET_SLICE(vi_iccl, MRV_VI_IE_CLK_ENABLE, 0);
  1796. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  1797. isp_write_reg(dev, REG_ADDR(img_eff_ctrl), img_eff_ctrl);
  1798. return 0;
  1799. }
  1800. REG_SET_SLICE(vi_ircl, MRV_VI_IE_SOFT_RST, 0);
  1801. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  1802. REG_SET_SLICE(vi_iccl, MRV_VI_IE_CLK_ENABLE, 1);
  1803. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  1804. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_EFFECT_MODE, ie->mode);
  1805. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_FULL_RANGE, ie->full_range);
  1806. for (i = 0; i < 9; i++)
  1807. mat[i] = get_eff_coeff(ie->m[i]);
  1808. if (ie->mode == MRV_IMGEFF_EFFECT_MODE_SEPIA) {
  1809. img_eff_tint = isp_read_reg(dev, REG_ADDR(img_eff_tint));
  1810. REG_SET_SLICE(img_eff_tint, MRV_IMGEFF_INCR_CR, ie->tint_cr);
  1811. REG_SET_SLICE(img_eff_tint, MRV_IMGEFF_INCR_CB, ie->tint_cb);
  1812. isp_write_reg(dev, REG_ADDR(img_eff_tint), img_eff_tint);
  1813. } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_COLOR_SEL) {
  1814. REG_SET_SLICE(img_eff_color_sel, MRV_IMGEFF_COLOR_SELECTION,
  1815. ie->color_sel);
  1816. REG_SET_SLICE(img_eff_color_sel, MRV_IMGEFF_COLOR_THRESHOLD,
  1817. ie->color_thresh);
  1818. isp_write_reg(dev, REG_ADDR(img_eff_color_sel),
  1819. img_eff_color_sel);
  1820. } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_EMBOSS) {
  1821. isp_write_reg(dev, REG_ADDR(img_eff_mat_1),
  1822. mat[0] | (mat[1] << 4) | (mat[2] << 8) | (mat[3]
  1823. << 12));
  1824. isp_write_reg(dev, REG_ADDR(img_eff_mat_2),
  1825. mat[4] | (mat[5] << 4) | (mat[6] << 8) | (mat[7]
  1826. << 12));
  1827. isp_write_reg(dev, REG_ADDR(img_eff_mat_3), mat[8]);
  1828. } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_SKETCH ||
  1829. ie->mode == MRV_IMGEFF_EFFECT_MODE_SHARPEN) {
  1830. isp_write_reg(dev, REG_ADDR(img_eff_mat_3),
  1831. (mat[0] << 4) | (mat[1] << 8) | (mat[2] << 12));
  1832. isp_write_reg(dev, REG_ADDR(img_eff_mat_4),
  1833. mat[3] | (mat[4] << 4) | (mat[5] << 8) | (mat[6]
  1834. << 12));
  1835. isp_write_reg(dev, REG_ADDR(img_eff_mat_5),
  1836. mat[7] | (mat[8] << 4));
  1837. REG_SET_SLICE(sharpen, MRV_IMGEFF_SHARP_FACTOR,
  1838. ie->sharpen_factor);
  1839. REG_SET_SLICE(sharpen, MRV_IMGEFF_CORING_THR,
  1840. ie->sharpen_thresh);
  1841. isp_write_reg(dev, REG_ADDR(img_eff_sharpen), sharpen);
  1842. }
  1843. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_CFG_UPD,
  1844. MRV_IMGEFF_CFG_UPD_UPDATE);
  1845. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_BYPASS_MODE,
  1846. MRV_IMGEFF_BYPASS_MODE_PROCESS);
  1847. isp_write_reg(dev, REG_ADDR(img_eff_ctrl), img_eff_ctrl);
  1848. isp_info("exit %s\n", __func__);
  1849. return 0;
  1850. }
  1851. int isp_s_vsm(struct isp_ic_dev *dev)
  1852. {
  1853. struct isp_vsm_context *vsm = &dev->vsm;
  1854. u32 isp_vsm_mode = isp_read_reg(dev, REG_ADDR(isp_vsm_mode));
  1855. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1856. isp_info("enter %s\n", __func__);
  1857. if (!vsm->enable) {
  1858. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_EN, 0);
  1859. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_IRQ_ENABLE, 0);
  1860. isp_write_reg(dev, REG_ADDR(isp_vsm_mode), isp_vsm_mode);
  1861. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1862. isp_imsc & ~MRV_ISP_IMSC_VSM_END_MASK);
  1863. return 0;
  1864. }
  1865. isp_write_reg(dev, REG_ADDR(isp_vsm_h_offs), vsm->window.x);
  1866. isp_write_reg(dev, REG_ADDR(isp_vsm_v_offs), vsm->window.y);
  1867. isp_write_reg(dev, REG_ADDR(isp_vsm_h_size),
  1868. vsm->window.width & 0xFFFFE);
  1869. isp_write_reg(dev, REG_ADDR(isp_vsm_v_size),
  1870. vsm->window.height & 0xFFFFE);
  1871. isp_write_reg(dev, REG_ADDR(isp_vsm_h_segments), vsm->h_seg);
  1872. isp_write_reg(dev, REG_ADDR(isp_vsm_v_segments), vsm->v_seg);
  1873. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_EN, 1);
  1874. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_IRQ_ENABLE, 1);
  1875. isp_write_reg(dev, REG_ADDR(isp_vsm_mode), isp_vsm_mode);
  1876. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1877. isp_imsc | MRV_ISP_IMSC_VSM_END_MASK);
  1878. isp_info("exit %s\n", __func__);
  1879. return 0;
  1880. }
  1881. int isp_g_vsm(struct isp_ic_dev *dev, struct isp_vsm_result *vsm)
  1882. {
  1883. isp_info("enter %s\n", __func__);
  1884. vsm->x = isp_read_reg(dev, REG_ADDR(isp_vsm_delta_h));
  1885. vsm->y = isp_read_reg(dev, REG_ADDR(isp_vsm_delta_v));
  1886. isp_info("exit %s\n", __func__);
  1887. return 0;
  1888. }
  1889. #if 0
  1890. u32 get_afm_shift(u32 count, u32 thresh)
  1891. {
  1892. u32 grad = count;
  1893. u32 shift = 0;
  1894. while (grad > (thresh)) {
  1895. ++shift;
  1896. grad >>= 1;
  1897. }
  1898. return shift;
  1899. }
  1900. #endif
  1901. int isp_s_afm(struct isp_ic_dev *dev)
  1902. {
  1903. struct isp_afm_context *afm = &dev->afm;
  1904. u32 mask =
  1905. (MRV_ISP_IMSC_AFM_FIN_MASK | MRV_ISP_IMSC_AFM_LUM_OF_MASK |
  1906. MRV_ISP_IMSC_AFM_SUM_OF_MASK);
  1907. u32 shift = 0;
  1908. int i;
  1909. u32 isp_afm_ctrl = isp_read_reg(dev, REG_ADDR(isp_afm_ctrl));
  1910. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1911. isp_info("enter %s\n", __func__);
  1912. if (!afm->enable) {
  1913. REG_SET_SLICE(isp_afm_ctrl, MRV_AFM_AFM_EN, 0);
  1914. isp_imsc &= ~mask;
  1915. isp_write_reg(dev, REG_ADDR(isp_afm_ctrl), isp_afm_ctrl);
  1916. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  1917. return 0;
  1918. }
  1919. for (i = 0; i < 3; i++) {
  1920. isp_write_reg(dev, REG_ADDR(isp_afm_lt_a) + i * 8,
  1921. (afm->window[i].x << 16) | afm->window[i].y);
  1922. isp_write_reg(dev, REG_ADDR(isp_afm_rb_a) + i * 8,
  1923. ((afm->window[i].x + afm->window[i].width -
  1924. 1) << 16) | ((afm->window[i].y +
  1925. afm->window[i].height - 1)));
  1926. }
  1927. REG_SET_SLICE(shift, MRV_AFM_LUM_VAR_SHIFT, afm->lum_shift);
  1928. REG_SET_SLICE(shift, MRV_AFM_AFM_VAR_SHIFT, afm->afm_shift);
  1929. isp_write_reg(dev, REG_ADDR(isp_afm_var_shift), shift);
  1930. isp_write_reg(dev, REG_ADDR(isp_afm_thres), afm->thresh);
  1931. REG_SET_SLICE(isp_afm_ctrl, MRV_AFM_AFM_EN, 1);
  1932. isp_imsc |= mask;
  1933. isp_write_reg(dev, REG_ADDR(isp_afm_ctrl), isp_afm_ctrl);
  1934. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  1935. isp_info("exit %s\n", __func__);
  1936. return 0;
  1937. }
  1938. int isp_g_afm(struct isp_ic_dev *dev, struct isp_afm_result *afm)
  1939. {
  1940. isp_info("enter %s\n", __func__);
  1941. afm->sum_a = isp_read_reg(dev, REG_ADDR(isp_afm_sum_a));
  1942. afm->sum_b = isp_read_reg(dev, REG_ADDR(isp_afm_sum_b));
  1943. afm->sum_c = isp_read_reg(dev, REG_ADDR(isp_afm_sum_c));
  1944. afm->lum_a = isp_read_reg(dev, REG_ADDR(isp_afm_lum_a));
  1945. afm->lum_b = isp_read_reg(dev, REG_ADDR(isp_afm_lum_b));
  1946. afm->lum_c = isp_read_reg(dev, REG_ADDR(isp_afm_lum_c));
  1947. isp_info("exit %s\n", __func__);
  1948. return 0;
  1949. }
  1950. int isp_s_exp2_inputsel(struct isp_ic_dev *dev)
  1951. {
  1952. #ifndef ISP_AEV2_RY
  1953. pr_err("unsupported function: %s\n", __func__);
  1954. return -EINVAL;
  1955. #else
  1956. struct isp_exp2_context *exp2 = &dev->exp2;
  1957. u32 isp_expv2_ctrl = isp_read_reg(dev, REG_ADDR(isp_expv2_ctrl));
  1958. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_INPUT_SELECT, exp2->input_select);
  1959. isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl);
  1960. return 0;
  1961. #endif
  1962. }
  1963. int isp_s_exp2_sizeratio(struct isp_ic_dev *dev, u32 h_size)
  1964. {
  1965. #ifndef ISP_AEV2_RY
  1966. pr_err("unsupported function: %s\n", __func__);
  1967. return -EINVAL;
  1968. #else
  1969. u32 size_inv;
  1970. size_inv = isp_read_reg(dev, REG_ADDR(isp_expv2_size_invert));
  1971. REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_H, h_size);
  1972. isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert), size_inv);
  1973. return 0;
  1974. #endif
  1975. }
  1976. int isp_s_exp2(struct isp_ic_dev *dev)
  1977. {
  1978. #ifndef ISP_AEV2_RY
  1979. //isp_err("unsupported function: %s\n", __func__);
  1980. return -EINVAL;
  1981. #else
  1982. u32 miv2_ctrl;
  1983. struct isp_exp2_context *exp2 = &dev->exp2;
  1984. u32 isp_expv2_ctrl = isp_read_reg(dev, REG_ADDR(isp_expv2_ctrl));
  1985. u32 grid_w, grid_h;
  1986. u32 size, offset, size_inv, weight;
  1987. isp_info("enter %s\n", __func__);
  1988. grid_w = ((exp2->window.width - 1) >> 6) << 1;
  1989. grid_h = ((exp2->window.height - 1) >> 6) << 1;
  1990. if (!exp2->enable) {
  1991. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_ENABLE, 0);
  1992. isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl);
  1993. return 0;
  1994. }
  1995. size = 0;
  1996. REG_SET_SLICE(size, MRV_AE_ISP_EXPV2_SIZE_H, grid_w);
  1997. REG_SET_SLICE(size, MRV_AE_ISP_EXPV2_SIZE_V, grid_h);
  1998. offset = 0;
  1999. REG_SET_SLICE(offset, MRV_AE_ISP_EXPV2_OFFSET_H, exp2->window.x);
  2000. REG_SET_SLICE(offset, MRV_AE_ISP_EXPV2_OFFSET_V, exp2->window.y);
  2001. size_inv = 0;
  2002. REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_H, (65536 + grid_w/2) / grid_w);
  2003. REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_V, (65536 + grid_h/2) / grid_h);
  2004. weight = 0;
  2005. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_R, exp2->r)
  2006. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR, exp2->gr)
  2007. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB, exp2->gb)
  2008. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_B, exp2->b)
  2009. isp_write_reg(dev, REG_ADDR(isp_expv2_offset), offset);
  2010. isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert), size_inv);
  2011. isp_write_reg(dev, REG_ADDR(isp_expv2_size), size);
  2012. #ifdef ISP_AE_SHADOW_RY
  2013. isp_write_reg(dev, REG_ADDR(isp_expv2_offset_shd), offset);
  2014. isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert_shd), size_inv);
  2015. isp_write_reg(dev, REG_ADDR(isp_expv2_size_shd), size);
  2016. #endif
  2017. isp_write_reg(dev, REG_ADDR(isp_expv2_pixel_weight), weight);
  2018. miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl));
  2019. REG_SET_SLICE(miv2_ctrl, MP_JDP_PATH_ENABLE, 1);
  2020. isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl);
  2021. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_base_ad_init), dev->exp2.pa);
  2022. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_size_init), AEV2_DMA_SIZE);
  2023. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_offs_cnt_init), 0);
  2024. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_llength), AEV2_DMA_SIZE);
  2025. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_width), 1024);
  2026. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_height), 1);
  2027. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_size), AEV2_DMA_SIZE);
  2028. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_ENABLE, 1);
  2029. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_INPUT_SELECT, exp2->input_select);
  2030. isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl);
  2031. return 0;
  2032. #endif
  2033. }
  2034. int isp_s_2dnr(struct isp_ic_dev *dev)
  2035. {
  2036. #ifndef ISP_2DNR
  2037. //isp_err("unsupported function: %s\n", __func__);
  2038. return -EINVAL;
  2039. #else
  2040. struct isp_2dnr_context *dnr2 = &dev->dnr2;
  2041. u32 isp_denoise2d_control =
  2042. isp_read_reg(dev, REG_ADDR(isp_denoise2d_control));
  2043. u32 value, addr, strength;
  2044. u32 isp_ctrl;
  2045. int i;
  2046. isp_info("enter %s\n", __func__);
  2047. if (!dnr2->enable) {
  2048. #ifndef ISP_2DNR_V4
  2049. REG_SET_SLICE(isp_denoise2d_control, ISP_2DNR_ENABLE, 0);
  2050. isp_write_reg(dev, REG_ADDR(isp_denoise2d_control),
  2051. isp_denoise2d_control);
  2052. #else
  2053. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  2054. REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 0);
  2055. if((value & DENOISE3D_V20_TNR_ENABLE_MASK) == 0)
  2056. REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 0);
  2057. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl),
  2058. value);
  2059. #endif
  2060. return 0;
  2061. }
  2062. strength = isp_read_reg(dev, REG_ADDR(isp_denoise2d_strength));
  2063. REG_SET_SLICE(strength, ISP_2DNR_PRGAMMA_STRENGTH, dnr2->pre_gamma);
  2064. REG_SET_SLICE(strength, ISP_2DNR_STRENGTH, dnr2->strength);
  2065. isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength), strength);
  2066. addr = REG_ADDR(isp_denoise2d_sigma_y[0]);
  2067. for (i = 0; i < 60; i += 5) {
  2068. value = 0;
  2069. REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i]);
  2070. REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 1]);
  2071. REG_SET_SLICE(value, ISP_2DNR_SIGMAY2A,
  2072. dnr2->sigma[i + 2] >> 6);
  2073. isp_write_reg(dev, addr, value);
  2074. value = 0;
  2075. addr += 4;
  2076. REG_SET_SLICE(value, ISP_2DNR_SIGMAY2B,
  2077. dnr2->sigma[i + 2] & 0x3f);
  2078. REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i + 3]);
  2079. REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 4]);
  2080. isp_write_reg(dev, addr, value);
  2081. addr += 4;
  2082. }
  2083. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  2084. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  2085. REG_SET_SLICE(isp_denoise2d_control, ISP_2DNR_ENABLE, 1);
  2086. #if defined(ISP_2DNR_V2) || defined(ISP_2DNR_V4)
  2087. isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr), dnr2->sigma_sqr);
  2088. isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr_shd),
  2089. dnr2->sigma_sqr);
  2090. isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor),
  2091. dnr2->weight);
  2092. isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor_shd),
  2093. dnr2->weight);
  2094. /* refer to HW spec for HBLANK */
  2095. //isp_write_reg(dev, REG_ADDR(isp_denoise2d_dummy_hblank), 0);
  2096. isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength_shd), strength);
  2097. isp_write_reg(dev, REG_ADDR(isp_denoise2d_control_shd),
  2098. isp_denoise2d_control);
  2099. #endif
  2100. #ifndef ISP_2DNR_V4
  2101. isp_write_reg(dev, REG_ADDR(isp_denoise2d_control),
  2102. isp_denoise2d_control);
  2103. #else
  2104. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_blending));
  2105. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_OFFSET, dnr2->str_off);
  2106. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_MAX, dnr2->str_max);
  2107. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_SLOPE, dnr2->str_slope);
  2108. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_blending), value);
  2109. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  2110. REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 1);
  2111. REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 1);
  2112. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl),
  2113. value);
  2114. #endif
  2115. isp_info("exit %s\n", __func__);
  2116. return 0;
  2117. #endif
  2118. }
  2119. int isp_s_simp(struct isp_ic_dev *dev)
  2120. {
  2121. struct isp_simp_context *simp = &dev->simp;
  2122. u32 vi_ircl = isp_read_reg(dev, REG_ADDR(vi_ircl));
  2123. u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl));
  2124. u32 super_imp_ctrl = isp_read_reg(dev, REG_ADDR(super_imp_ctrl));
  2125. isp_info("enter %s\n", __func__);
  2126. REG_SET_SLICE(vi_ircl, MRV_VI_SIMP_SOFT_RST, 1);
  2127. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2128. if (!simp->enable) {
  2129. REG_SET_SLICE(vi_iccl, MRV_VI_SIMP_CLK_ENABLE, 0);
  2130. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  2131. return 0;
  2132. }
  2133. REG_SET_SLICE(vi_ircl, MRV_VI_SIMP_SOFT_RST, 0);
  2134. isp_write_reg(dev, REG_ADDR(super_imp_offset_x), simp->x);
  2135. isp_write_reg(dev, REG_ADDR(super_imp_offset_y), simp->y);
  2136. isp_write_reg(dev, REG_ADDR(super_imp_color_y), simp->r);
  2137. isp_write_reg(dev, REG_ADDR(super_imp_color_cb), simp->g);
  2138. isp_write_reg(dev, REG_ADDR(super_imp_color_cr), simp->b);
  2139. REG_SET_SLICE(super_imp_ctrl, MRV_SI_TRANSPARENCY_MODE,
  2140. simp->transparency_mode);
  2141. REG_SET_SLICE(super_imp_ctrl, MRV_SI_REF_IMAGE, simp->ref_image);
  2142. isp_write_reg(dev, REG_ADDR(super_imp_ctrl), super_imp_ctrl);
  2143. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2144. REG_SET_SLICE(vi_iccl, MRV_VI_SIMP_CLK_ENABLE, 1);
  2145. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  2146. isp_info("exit %s\n", __func__);
  2147. return 0;
  2148. }
  2149. int isp_s_cproc(struct isp_ic_dev *dev)
  2150. {
  2151. struct isp_cproc_context *cproc = &dev->cproc;
  2152. u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl));
  2153. u32 cproc_ctrl = isp_read_reg(dev, REG_ADDR(cproc_ctrl));
  2154. //REG_SET_SLICE(vi_ircl, MRV_VI_CP_SOFT_RST, 1);
  2155. //isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2156. //if there is no shd register. should update cporc register in isp frame end irq.
  2157. #ifndef ISP_CPROC_SHD_RY
  2158. if(dev->cproc.changed || !is_isp_enable(dev))
  2159. {
  2160. #endif
  2161. isp_info("enter %s %d\n", __func__, cproc->enable);
  2162. if (!cproc->enable) {
  2163. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_ENABLE, 0);
  2164. /* REG_SET_SLICE(vi_iccl, MRV_VI_CP_CLK_ENABLE, 0); */
  2165. /* isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl); */
  2166. isp_write_reg(dev, REG_ADDR(cproc_ctrl), cproc_ctrl);
  2167. return 0;
  2168. }
  2169. //REG_SET_SLICE(vi_ircl, MRV_VI_CP_SOFT_RST, 0);
  2170. //isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2171. isp_write_reg(dev, REG_ADDR(cproc_contrast), cproc->contrast);
  2172. isp_write_reg(dev, REG_ADDR(cproc_brightness), cproc->brightness);
  2173. isp_write_reg(dev, REG_ADDR(cproc_saturation), cproc->saturation);
  2174. isp_write_reg(dev, REG_ADDR(cproc_hue), cproc->hue);
  2175. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_ENABLE, 1);
  2176. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_C_OUT_RANGE,
  2177. cproc->c_out_full);
  2178. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_Y_OUT_RANGE,
  2179. cproc->y_out_full);
  2180. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_Y_IN_RANGE, cproc->y_in_full);
  2181. REG_SET_SLICE(vi_iccl, MRV_VI_CP_CLK_ENABLE, 1);
  2182. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  2183. isp_write_reg(dev, REG_ADDR(cproc_ctrl), cproc_ctrl);
  2184. #ifndef ISP_CPROC_SHD_RY
  2185. dev->cproc.changed = false;
  2186. } else {
  2187. dev->cproc.changed = true;
  2188. }
  2189. #endif
  2190. isp_info("exit %s\n", __func__);
  2191. return 0;
  2192. }
  2193. int isp_s_elawb(struct isp_ic_dev *dev)
  2194. {
  2195. struct isp_elawb_context *elawb = &dev->elawb;
  2196. u32 awb_meas_mode = isp_read_reg(dev, REG_ADDR(awb_meas_mode));
  2197. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  2198. u32 id = elawb->id;
  2199. u32 data;
  2200. if (!elawb->enable) {
  2201. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_IRQ_ENABLE, 0);
  2202. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_EN, 0);
  2203. isp_write_reg(dev, REG_ADDR(awb_meas_mode), awb_meas_mode);
  2204. isp_write_reg(dev, REG_ADDR(isp_imsc),
  2205. isp_imsc & ~MRV_ISP_IMSC_AWB_DONE_MASK);
  2206. return 0;
  2207. }
  2208. isp_write_reg(dev, REG_ADDR(awb_meas_h_offs), elawb->window.x);
  2209. isp_write_reg(dev, REG_ADDR(awb_meas_v_offs), elawb->window.y);
  2210. isp_write_reg(dev, REG_ADDR(awb_meas_h_size), elawb->window.width);
  2211. isp_write_reg(dev, REG_ADDR(awb_meas_v_size), elawb->window.height);
  2212. if (id > 0 && id < 9) {
  2213. isp_write_reg(dev, REG_ADDR(awb_meas_center[id - 1].x),
  2214. elawb->info[id - 1].x);
  2215. isp_write_reg(dev, REG_ADDR(awb_meas_center[id - 1].y),
  2216. elawb->info[id - 1].y);
  2217. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a1),
  2218. elawb->info[id - 1].a1);
  2219. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a2),
  2220. elawb->info[id - 1].a2);
  2221. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a3),
  2222. elawb->info[id - 1].a3);
  2223. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a4),
  2224. elawb->info[id - 1].a4);
  2225. isp_write_reg(dev, REG_ADDR(awb_meas_rmax[id - 1]),
  2226. elawb->info[id - 1].r_max_sqr);
  2227. }
  2228. data = 0;
  2229. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_R, elawb->r);
  2230. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_B, elawb->b);
  2231. isp_write_reg(dev, REG_ADDR(isp_awb_gain_rb), data);
  2232. data = 0;
  2233. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_GR, elawb->gr);
  2234. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_GB, elawb->gb);
  2235. isp_write_reg(dev, REG_ADDR(isp_awb_gain_g), data);
  2236. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_IRQ_ENABLE, 1);
  2237. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_EN, 1);
  2238. isp_write_reg(dev, REG_ADDR(awb_meas_mode), awb_meas_mode);
  2239. isp_write_reg(dev, REG_ADDR(isp_imsc),
  2240. isp_imsc | MRV_ISP_IMSC_AWB_DONE_MASK);
  2241. return 0;
  2242. }
  2243. int isp_ioc_qcap(struct isp_ic_dev *dev, void __user *args)
  2244. {
  2245. /* use public VIDIOC_QUERYCAP to query the type of v4l-subdevs. */
  2246. #ifdef __KERNEL__
  2247. #ifndef USE_FPGA
  2248. struct v4l2_capability *cap = (struct v4l2_capability *)args;
  2249. strcpy((char *)cap->driver, "viv_isp_subdev");
  2250. cap->bus_info[0] = (__u8)dev->id;//isp channel id
  2251. #else
  2252. struct v4l2_capability cap;
  2253. strcpy((char *)cap.driver, "viv_isp_subdev");
  2254. cap.bus_info[0] = (__u8)dev->id;//isp channel id
  2255. isp_info("enter %s viv_isp_subdev\n", __func__);
  2256. viv_check_retval(copy_to_user
  2257. ((struct v4l2_capability *)args, &cap, sizeof(cap)));
  2258. #endif
  2259. #endif
  2260. return 0;
  2261. }
  2262. int isp_ioc_g_status(struct isp_ic_dev *dev, void __user *args)
  2263. {
  2264. u32 val = 0;
  2265. /* val = isp_read_reg(REG_ADDR(isp_feature_version)); */
  2266. viv_check_retval(copy_to_user(args, &val, sizeof(val)));
  2267. return 0;
  2268. }
  2269. static u32 getScaleFactor(u32 src, u32 dst)
  2270. {
  2271. if (dst > src) {
  2272. return ((65536 * (src - 1)) / (dst - 1));
  2273. } else if (dst < src) {
  2274. return ((65536 * (dst - 1)) / (src - 1)) + 1;
  2275. }
  2276. return 65536;
  2277. }
  2278. int isp_set_scaling(int id, struct isp_ic_dev *dev, bool stabilization, bool crop)
  2279. {
  2280. u32 addr, ctrl;
  2281. u32 iw, ih, ow, oh;
  2282. u32 inputWidth, inputHeight, outputWidth, outputHeight;
  2283. u32 scale_hy, scale_hcb, scale_hcr, scale_vy, scale_vc;
  2284. struct isp_mi_data_path_context *path = &dev->mi.path[id];
  2285. if (crop) { //enabled crop.Do not need to scaler.
  2286. isp_info("%s:The crop enabled ,So does not need to do scaler.\n", __func__);
  2287. return 0;
  2288. }
  2289. if (id == IC_MI_PATH_MAIN) { /* mp */
  2290. addr = REG_ADDR(mrsz_ctrl);
  2291. } else if (id == IC_MI_PATH_SELF) { /* sp */
  2292. addr = REG_ADDR(srsz_ctrl);
  2293. } else if (id == IC_MI_PATH_SELF2) { /* sp2 */
  2294. addr = REG_ADDR(srsz2_ctrl);
  2295. } else {
  2296. return -EFAULT;
  2297. }
  2298. inputWidth = path->in_width;
  2299. inputHeight = path->in_height;
  2300. outputWidth = path->out_width;
  2301. outputHeight = path->out_height;
  2302. if (stabilization) { /* enabled image stabilization. */
  2303. inputWidth = isp_read_reg(dev, REG_ADDR(isp_is_h_size));
  2304. inputHeight = isp_read_reg(dev, REG_ADDR(isp_is_v_size));
  2305. }
  2306. ctrl = isp_read_reg(dev, addr);
  2307. iw = inputWidth / 2;
  2308. ih = inputHeight;
  2309. ow = outputWidth / 2;
  2310. oh = outputHeight;
  2311. switch (path->in_mode) {
  2312. case IC_MI_DATAMODE_YUV422:
  2313. oh = outputHeight;
  2314. break;
  2315. case IC_MI_DATAMODE_YUV420:
  2316. oh = outputHeight / 2; /* scale cbcr */
  2317. break;
  2318. case IC_MI_DATAMODE_YUV444:
  2319. oh = outputHeight;
  2320. break;
  2321. case IC_MI_DATAMODE_RGB888:
  2322. oh = outputHeight;
  2323. break;
  2324. default:
  2325. return -EFAULT;
  2326. }
  2327. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_ENABLE,
  2328. inputWidth != outputWidth);
  2329. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_ENABLE,
  2330. inputHeight != outputHeight);
  2331. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_UP, inputWidth < outputWidth);
  2332. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_UP, inputHeight < outputHeight);
  2333. scale_hy = getScaleFactor(inputWidth, outputWidth);
  2334. scale_vy = getScaleFactor(inputHeight, outputHeight);
  2335. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_ENABLE, iw != ow);
  2336. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_ENABLE, ih != oh);
  2337. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_UP, iw < ow);
  2338. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_UP, ih < oh);
  2339. scale_hcr = getScaleFactor(iw, ow);
  2340. scale_hcb = getScaleFactor(iw, ow);
  2341. scale_vc = getScaleFactor(ih, oh);
  2342. /*Need to update immediately*/
  2343. REG_SET_SLICE(ctrl, MRV_MRSZ_CFG_UPD, 1);
  2344. if (id == IC_MI_PATH_MAIN) {
  2345. isp_write_reg(dev, REG_ADDR(mrsz_scale_vc), scale_vc);
  2346. isp_write_reg(dev, REG_ADDR(mrsz_scale_vy), scale_vy);
  2347. isp_write_reg(dev, REG_ADDR(mrsz_scale_hcr), scale_hcr);
  2348. isp_write_reg(dev, REG_ADDR(mrsz_scale_hcb), scale_hcb);
  2349. isp_write_reg(dev, REG_ADDR(mrsz_scale_hy), scale_hy);
  2350. isp_write_reg(dev, REG_ADDR(mrsz_ctrl), ctrl);
  2351. } else if (id == IC_MI_PATH_SELF) {
  2352. isp_write_reg(dev, REG_ADDR(srsz_scale_vc), scale_vc);
  2353. isp_write_reg(dev, REG_ADDR(srsz_scale_vy), scale_vy);
  2354. isp_write_reg(dev, REG_ADDR(srsz_scale_hcr), scale_hcr);
  2355. isp_write_reg(dev, REG_ADDR(srsz_scale_hcb), scale_hcb);
  2356. isp_write_reg(dev, REG_ADDR(srsz_scale_hy), scale_hy);
  2357. isp_write_reg(dev, REG_ADDR(srsz_ctrl), ctrl);
  2358. } else if (id == IC_MI_PATH_SELF2) {
  2359. isp_write_reg(dev, REG_ADDR(srsz2_scale_vc), scale_vc);
  2360. isp_write_reg(dev, REG_ADDR(srsz2_scale_vy), scale_vy);
  2361. isp_write_reg(dev, REG_ADDR(srsz2_scale_hcr), scale_hcr);
  2362. isp_write_reg(dev, REG_ADDR(srsz2_scale_hcb), scale_hcb);
  2363. isp_write_reg(dev, REG_ADDR(srsz2_scale_hy), scale_hy);
  2364. isp_write_reg(dev, REG_ADDR(srsz2_ctrl), ctrl);
  2365. }
  2366. return 0;
  2367. }
  2368. typedef struct isp_crop_reg_s {
  2369. u32 crop_ctrl_addr;
  2370. u32 crop_x_dir_addr;
  2371. u32 crop_y_dir_addr;
  2372. } isp_crop_reg_t;
  2373. int isp_set_crop(struct isp_ic_dev *dev)
  2374. {
  2375. long ret = 0;
  2376. u32 crop_ctrl, crop_x_dir, crop_y_dir;
  2377. u8 i;
  2378. isp_crop_reg_t crop_reg[ISP_MI_PATH_SP2_BP + 1] = {
  2379. {
  2380. REG_ADDR(mrsz_ctrl),
  2381. REG_ADDR(mrsz_phase_crop_x),
  2382. REG_ADDR(mrsz_phase_crop_y)
  2383. },
  2384. {
  2385. REG_ADDR(srsz_ctrl),
  2386. REG_ADDR(srsz_phase_crop_x),
  2387. REG_ADDR(srsz_phase_crop_y)
  2388. },
  2389. {
  2390. REG_ADDR(srsz2_ctrl),
  2391. REG_ADDR(srsz2_phase_crop_x),
  2392. REG_ADDR(srsz2_phase_crop_y)
  2393. }
  2394. };
  2395. struct isp_crop_context *crop = dev->crop;
  2396. for ( i = 0; i <= ISP_MI_PATH_SP2_BP; i++) {
  2397. crop_ctrl = isp_read_reg(dev, crop_reg[i].crop_ctrl_addr);
  2398. crop_x_dir = isp_read_reg(dev, crop_reg[i].crop_x_dir_addr);
  2399. crop_y_dir = isp_read_reg(dev, crop_reg[i].crop_y_dir_addr);
  2400. if (!crop[i].enabled) {
  2401. #ifndef ISP8000NANO_BASE
  2402. REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CROP_ENABLE, 0);
  2403. #endif
  2404. isp_write_reg(dev, crop_reg[i].crop_ctrl_addr, crop_ctrl);
  2405. continue;
  2406. }
  2407. REG_SET_SLICE(crop_x_dir, MRV_MRSZ_PHASE_H_START, crop[i].window.x);
  2408. REG_SET_SLICE(crop_y_dir, MRV_MRSZ_PHASE_V_START, crop[i].window.y);
  2409. REG_SET_SLICE(crop_x_dir, MRV_MRSZ_PHASE_H_END, crop[i].window.width + crop[i].window.x - 1); //x_end = x + width -1
  2410. REG_SET_SLICE(crop_y_dir, MRV_MRSZ_PHASE_V_END, crop[i].window.height + crop[i].window.y - 1); //y_end = y + height -1
  2411. #ifndef ISP8000NANO_BASE
  2412. REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CROP_ENABLE, 1);
  2413. /*Need to update immediately*/
  2414. REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CFG_UPD, 1);
  2415. #endif
  2416. isp_write_reg(dev, crop_reg[i].crop_x_dir_addr, crop_x_dir);
  2417. isp_write_reg(dev, crop_reg[i].crop_y_dir_addr, crop_y_dir);
  2418. isp_write_reg(dev, crop_reg[i].crop_ctrl_addr, crop_ctrl);
  2419. }
  2420. return ret;
  2421. }
  2422. int isp_ioc_g_feature(struct isp_ic_dev *dev, void __user *args)
  2423. {
  2424. u32 val = 0;
  2425. #ifdef ISP_EE_RY
  2426. val |= ISP_EE_SUPPORT;
  2427. #endif
  2428. #ifdef ISP_WDR3
  2429. val |= ISP_WDR3_SUPPORT;
  2430. #endif
  2431. #ifdef ISP_2DNR
  2432. val |= ISP_2DNR_SUPPORT;
  2433. #endif
  2434. #ifdef ISP_3DNR
  2435. val |= ISP_3DNR_SUPPORT;
  2436. #endif
  2437. #ifdef ISP_WDR_V3
  2438. val |= ISP_WDR3_SUPPORT;
  2439. #endif
  2440. #ifdef ISP_MIV2_RY
  2441. val |= ISP_MIV2_SUPPORT;
  2442. #endif
  2443. #ifdef ISP_AEV2_RY
  2444. val |= ISP_AEV2_SUPPORT;
  2445. #endif
  2446. #ifdef ISP_HDR_STITCH_RY
  2447. val |= ISP_HDR_STITCH_SUPPORT;
  2448. #endif
  2449. viv_check_retval(copy_to_user(args, &val, sizeof(val)));
  2450. return 0;
  2451. }
  2452. int isp_ioc_g_feature_veresion(struct isp_ic_dev *dev, void __user *args)
  2453. {
  2454. u32 val = 0;
  2455. /* val = isp_read_reg(REG_ADDR(isp_feature_version)); */
  2456. viv_check_retval(copy_to_user(args, &val, sizeof(val)));
  2457. return 0;
  2458. }
  2459. static long isp_get_extmem(struct isp_ic_dev *dev, void __user *args)
  2460. {
  2461. #define UT_USED_SIZE 0x01000000
  2462. long ret = 0;
  2463. struct isp_extmem_info ext_mem;
  2464. dev->ut_addr = dma_alloc_coherent(dev->device, UT_USED_SIZE, &dev->ut_phy_addr, GFP_KERNEL);
  2465. if (dev->ut_addr != NULL) {
  2466. ext_mem.addr = dev->ut_phy_addr;
  2467. ext_mem.size = UT_USED_SIZE;
  2468. } else {
  2469. return -1;
  2470. }
  2471. ret = copy_to_user(args, &ext_mem, sizeof(struct isp_extmem_info));
  2472. return ret;
  2473. }
  2474. long isp_priv_ioctl(struct isp_ic_dev *dev, unsigned int cmd, void __user *args)
  2475. {
  2476. int ret = -1;
  2477. if (!dev) {
  2478. return ret;
  2479. }
  2480. /*isp_info("ry [%s:%d]cmd 0x%08x\n", __func__, __LINE__, cmd);*/
  2481. switch (cmd) {
  2482. case ISPIOC_RESET:
  2483. if((ret = isp_mi_stop(dev)) != 0 )
  2484. {
  2485. pr_err("[%s:%d]stop mi error before resetting!\n", __func__, __LINE__);
  2486. break;
  2487. }
  2488. if((ret = isp_stop_stream(dev)) != 0)
  2489. {
  2490. pr_err("[%s:%d]stop isp stream before resetting!\n", __func__, __LINE__);
  2491. break;
  2492. }
  2493. ret = isp_reset(dev);
  2494. break;
  2495. case ISPIOC_WRITE_REG:
  2496. ret = isp_ioc_write_reg(dev, args);
  2497. break;
  2498. case ISPIOC_READ_REG:
  2499. ret = isp_ioc_read_reg(dev, args);
  2500. break;
  2501. case ISPIOC_GET_MIS:
  2502. ret = isp_ioc_read_mis(dev, args);
  2503. break;
  2504. case ISPIOC_ENABLE_TPG:
  2505. ret = isp_enable_tpg(dev);
  2506. break;
  2507. case ISPIOC_DISABLE_TPG:
  2508. ret = isp_disable_tpg(dev);
  2509. break;
  2510. case ISPIOC_ENABLE_BLS:
  2511. ret = isp_enable_bls(dev);
  2512. break;
  2513. case ISPIOC_DISABLE_BLS:
  2514. ret = isp_disable_bls(dev);
  2515. break;
  2516. case ISPIOC_START_DMA_READ:
  2517. ret = isp_ioc_start_dma_read(dev, args);
  2518. break;
  2519. case ISPIOC_CFG_DMA:
  2520. ret = isp_ioc_cfg_dma(dev, args);
  2521. break;
  2522. case ISPIOC_MI_STOP:
  2523. ret = isp_mi_stop(dev);
  2524. break;
  2525. case ISPIOC_DISABLE_ISP_OFF:
  2526. ret = isp_ioc_disable_isp_off(dev, args);
  2527. break;
  2528. case ISPIOC_ISP_STOP:
  2529. ret = isp_stop_stream(dev);
  2530. if(!ret) {
  2531. dev->streaming = false;
  2532. }
  2533. break;
  2534. case ISPIOC_ENABLE:
  2535. ret = isp_enable(dev);
  2536. break;
  2537. case ISPIOC_DISABLE:
  2538. ret = isp_disable(dev);
  2539. break;
  2540. case ISPIOC_ISP_STATUS:{
  2541. bool enable = is_isp_enable(dev);
  2542. viv_check_retval(copy_to_user
  2543. (args, &enable, sizeof(bool)));
  2544. ret = 0;
  2545. break;
  2546. }
  2547. case ISPIOC_ENABLE_LSC:
  2548. ret = isp_enable_lsc(dev);
  2549. break;
  2550. case ISPIOC_DISABLE_LSC:
  2551. ret = isp_disable_lsc(dev);
  2552. break;
  2553. case ISPIOC_S_DIGITAL_GAIN:
  2554. viv_check_retval(copy_from_user
  2555. (&dev->dgain, args, sizeof(dev->dgain)));
  2556. ret = isp_s_digital_gain(dev);
  2557. break;
  2558. #ifdef ISP_DEMOSAIC2_RY
  2559. case ISPIOC_S_DMSC_INTP:
  2560. viv_check_retval(copy_from_user
  2561. (&dev->demosaic.intp, args,
  2562. sizeof(dev->demosaic.intp)));
  2563. ret = isp_set_dmsc_intp(dev);
  2564. break;
  2565. case ISPIOC_S_DMSC_DMOI:
  2566. viv_check_retval(copy_from_user
  2567. (&dev->demosaic.demoire, args,
  2568. sizeof(dev->demosaic.demoire)));
  2569. ret = isp_set_dmsc_dmoi(dev);
  2570. break;
  2571. case ISPIOC_S_DMSC_SKIN:
  2572. viv_check_retval(copy_from_user
  2573. (&dev->demosaic.skin, args,
  2574. sizeof(dev->demosaic.skin)));
  2575. ret = isp_set_dmsc_skin(dev);
  2576. break;
  2577. case ISPIOC_S_DMSC_SHAP:
  2578. viv_check_retval(copy_from_user
  2579. (&dev->demosaic.sharpen, args,
  2580. sizeof(dev->demosaic.sharpen)));
  2581. ret = isp_set_dmsc_sharpen(dev);
  2582. break;
  2583. case ISPIOC_S_DMSC_SHAP_LINE:
  2584. viv_check_retval(copy_from_user
  2585. (&dev->demosaic.sharpenLine, args,
  2586. sizeof(dev->demosaic.sharpenLine)));
  2587. ret = isp_set_dmsc_sharpen_line(dev);
  2588. break;
  2589. case ISPIOC_S_DMSC_CAC:
  2590. viv_check_retval(copy_from_user
  2591. (&dev->cac, args, sizeof(dev->cac)));
  2592. ret = isp_set_dmsc_cac(dev);
  2593. break;
  2594. case ISPIOC_S_DMSC_DEPURPLE:
  2595. viv_check_retval(copy_from_user
  2596. (&dev->demosaic.depurple, args,
  2597. sizeof(dev->demosaic.depurple)));
  2598. ret = isp_set_dmsc_depurple(dev);
  2599. break;
  2600. case ISPIOC_S_DMSC_GFILTER:
  2601. viv_check_retval(copy_from_user
  2602. (&dev->demosaic.gFilter, args,
  2603. sizeof(dev->demosaic.gFilter)));
  2604. ret = isp_set_dmsc_gfilter(dev);
  2605. break;
  2606. case ISPIOC_S_DMSC:
  2607. viv_check_retval(copy_from_user
  2608. (&dev->demosaic, args, sizeof(dev->demosaic)));
  2609. ret = isp_s_dmsc(dev);
  2610. break;
  2611. #endif
  2612. case ISPIOC_ENABLE_AWB:
  2613. ret = isp_enable_awb(dev);
  2614. break;
  2615. case ISPIOC_DISABLE_AWB:
  2616. ret = isp_disable_awb(dev);
  2617. break;
  2618. case ISPIOC_ENABLE_WB:
  2619. ret = isp_enable_wb(dev, 1);
  2620. break;
  2621. case ISPIOC_DISABLE_WB:
  2622. ret = isp_enable_wb(dev, 0);
  2623. break;
  2624. case ISPIOC_ENABLE_GAMMA_OUT:
  2625. ret = isp_enable_gamma_out(dev, 1);
  2626. break;
  2627. case ISPIOC_DISABLE_GAMMA_OUT:
  2628. ret = isp_enable_gamma_out(dev, 0);
  2629. break;
  2630. #if defined(ISP_3DNR) || defined(ISP_3DNR_V2_V1)
  2631. case ISPIOC_R_3DNR:
  2632. viv_check_retval(copy_from_user
  2633. (&dev->dnr3, args, sizeof(dev->dnr3)));
  2634. ret = isp_r_3dnr(dev);
  2635. break;
  2636. #endif
  2637. case ISPIOC_S_IS:
  2638. viv_check_retval(copy_from_user
  2639. (&dev->is, args, sizeof(dev->is)));
  2640. ret = isp_s_is(dev);
  2641. break;
  2642. case ISPIOC_S_RAW_IS:
  2643. viv_check_retval(copy_from_user
  2644. (&dev->rawis, args, sizeof(dev->rawis)));
  2645. ret = isp_s_raw_is(dev);
  2646. break;
  2647. case ISPIOC_S_CC:
  2648. viv_check_retval(copy_from_user
  2649. (&dev->cc, args, sizeof(dev->cc)));
  2650. ret = isp_s_cc(dev);
  2651. break;
  2652. case ISPIOC_S_EE:
  2653. viv_check_retval(copy_from_user
  2654. (&dev->ee, args, sizeof(dev->ee)));
  2655. ret = isp_s_ee(dev);
  2656. break;
  2657. case ISPIOC_S_IE:
  2658. viv_check_retval(copy_from_user
  2659. (&dev->ie, args, sizeof(dev->ie)));
  2660. ret = isp_s_ie(dev);
  2661. break;
  2662. case ISPIOC_S_TPG:
  2663. viv_check_retval(copy_from_user
  2664. (&dev->tpg, args, sizeof(dev->tpg)));
  2665. ret = isp_s_tpg(dev);
  2666. break;
  2667. case ISPIOC_S_BLS:
  2668. viv_check_retval(copy_from_user
  2669. (&dev->bls, args, sizeof(dev->bls)));
  2670. ret = isp_s_bls(dev);
  2671. break;
  2672. case ISPIOC_BYPASS_MCM:
  2673. viv_check_retval(copy_from_user
  2674. (&dev->mcm, args, sizeof(dev->mcm)));
  2675. ret = isp_bypass_mcm(dev);
  2676. break;
  2677. case ISPIOC_S_MCM_WR:
  2678. viv_check_retval(copy_from_user
  2679. (&dev->mcm, args, sizeof(dev->mcm)));
  2680. ret = isp_s_mcm_wr(dev);
  2681. break;
  2682. case ISPIOC_S_MUX:
  2683. viv_check_retval(copy_from_user
  2684. (&dev->mux, args, sizeof(dev->mux)));
  2685. ret = isp_s_mux(dev);
  2686. break;
  2687. case ISPIOC_S_AWB:
  2688. viv_check_retval(copy_from_user
  2689. (&dev->awb, args, sizeof(dev->awb)));
  2690. ret = isp_s_awb(dev);
  2691. break;
  2692. case ISPIOC_S_LSC_TBL:
  2693. viv_check_retval(copy_from_user
  2694. (&dev->lsc, args, sizeof(dev->lsc)));
  2695. ret = isp_s_lsc_tbl(dev);
  2696. break;
  2697. case ISPIOC_S_LSC_SEC:
  2698. viv_check_retval(copy_from_user
  2699. (&dev->lsc, args, sizeof(dev->lsc)));
  2700. ret = isp_s_lsc_sec(dev);
  2701. break;
  2702. case ISPIOC_S_DPF:
  2703. viv_check_retval(copy_from_user
  2704. (&dev->dpf, args, sizeof(dev->dpf)));
  2705. ret = isp_s_dpf(dev);
  2706. break;
  2707. case ISPIOC_S_EXP:
  2708. viv_check_retval(copy_from_user
  2709. (&dev->exp, args, sizeof(dev->exp)));
  2710. ret = isp_s_exp(dev);
  2711. break;
  2712. case ISPIOC_S_HDREXP:
  2713. viv_check_retval(copy_from_user
  2714. (&dev->hdrexp, args, sizeof(dev->hdrexp)));
  2715. ret = isp_s_hdrexp(dev);
  2716. break;
  2717. case ISPIOC_S_CNR:
  2718. viv_check_retval(copy_from_user
  2719. (&dev->cnr, args, sizeof(dev->cnr)));
  2720. ret = isp_s_cnr(dev);
  2721. break;
  2722. case ISPIOC_S_FLT:
  2723. {
  2724. viv_check_retval(copy_from_user
  2725. (&dev->flt, args, sizeof(dev->flt)));
  2726. ret = isp_s_flt(dev);
  2727. break;
  2728. }
  2729. case ISPIOC_S_CAC:
  2730. viv_check_retval(copy_from_user
  2731. (&dev->cac, args, sizeof(dev->cac)));
  2732. ret = isp_s_cac(dev);
  2733. break;
  2734. case ISPIOC_S_DEG:
  2735. viv_check_retval(copy_from_user
  2736. (&dev->deg, args, sizeof(dev->deg)));
  2737. ret = isp_s_deg(dev);
  2738. break;
  2739. case ISPIOC_S_VSM:
  2740. viv_check_retval(copy_from_user
  2741. (&dev->vsm, args, sizeof(dev->vsm)));
  2742. ret = isp_s_vsm(dev);
  2743. break;
  2744. case ISPIOC_S_AFM:
  2745. viv_check_retval(copy_from_user
  2746. (&dev->afm, args, sizeof(dev->afm)));
  2747. ret = isp_s_afm(dev);
  2748. break;
  2749. case ISPIOC_S_HDR:
  2750. viv_check_retval(copy_from_user
  2751. (&dev->hdr, args, sizeof(dev->hdr)));
  2752. ret = isp_s_hdr(dev);
  2753. break;
  2754. case ISPIOC_ENABLE_HDR:
  2755. viv_check_retval(copy_from_user
  2756. (&dev->hdr, args, sizeof(dev->hdr)));
  2757. ret = isp_enable_hdr(dev);
  2758. break;
  2759. case ISPIOC_DISABLE_HDR:
  2760. viv_check_retval(copy_from_user
  2761. (&dev->hdr, args, sizeof(dev->hdr)));
  2762. ret = isp_disable_hdr(dev);
  2763. break;
  2764. case ISPIOC_S_HIST:
  2765. viv_check_retval(copy_from_user
  2766. (&dev->hist, args, sizeof(dev->hist)));
  2767. ret = isp_s_hist(dev);
  2768. break;
  2769. case ISPIOC_S_HDRHIST:
  2770. viv_check_retval(copy_from_user
  2771. (&dev->hdrhist, args, sizeof(dev->hdrhist)));
  2772. ret = isp_s_hdrhist(dev);
  2773. break;
  2774. #ifdef ISP_HIST64_RY
  2775. case ISPIOC_S_HIST64:
  2776. viv_check_retval(copy_from_user
  2777. (&dev->hist64, args, sizeof(dev->hist64)));
  2778. ret = isp_s_hist64(dev);
  2779. break;
  2780. case ISPIOC_U_HIST64:
  2781. viv_check_retval(copy_from_user
  2782. (&dev->hist64, args, sizeof(dev->hist64)));
  2783. ret = isp_update_hist64(dev);
  2784. break;
  2785. #endif
  2786. case ISPIOC_S_DPCC:
  2787. viv_check_retval(copy_from_user
  2788. (&dev->dpcc, args, sizeof(dev->dpcc)));
  2789. ret = isp_s_dpcc(dev);
  2790. break;
  2791. case ISPIOC_ENABLE_WDR3:
  2792. ret = isp_enable_wdr3(dev);
  2793. break;
  2794. case ISPIOC_DISABLE_WDR3:
  2795. ret = isp_disable_wdr3(dev);
  2796. break;
  2797. case ISPIOC_U_WDR3:
  2798. viv_check_retval(copy_from_user
  2799. (&dev->wdr3, args, sizeof(dev->wdr3)));
  2800. ret = isp_u_wdr3(dev);
  2801. break;
  2802. case ISPIOC_S_WDR3:
  2803. viv_check_retval(copy_from_user
  2804. (&dev->wdr3, args, sizeof(dev->wdr3)));
  2805. ret = isp_s_wdr3(dev);
  2806. break;
  2807. #ifdef ISP_WDR_V4
  2808. case ISPIOC_ENABLE_WDR4:
  2809. ret = isp_enable_wdr4(dev);
  2810. break;
  2811. case ISPIOC_DISABLE_WDR4:
  2812. ret = isp_disable_wdr4(dev);
  2813. break;
  2814. case ISPIOC_U_WDR4:
  2815. viv_check_retval(copy_from_user
  2816. (&dev->wdr4, args, sizeof(dev->wdr4)));
  2817. ret = isp_u_wdr4(dev);
  2818. break;
  2819. case ISPIOC_S_WDR4:
  2820. viv_check_retval(copy_from_user
  2821. (&dev->wdr4, args, sizeof(dev->wdr4)));
  2822. ret = isp_s_wdr4(dev);
  2823. break;
  2824. #endif
  2825. case ISPIOC_S_EXP2:
  2826. viv_check_retval(copy_from_user
  2827. (&dev->exp2, args, sizeof(dev->exp2)));
  2828. ret = isp_s_exp2(dev);
  2829. break;
  2830. case ISPIOC_S_EXP2_INPUTSEL:
  2831. viv_check_retval(copy_from_user
  2832. (&dev->exp2.input_select, args,
  2833. sizeof(dev->exp2.input_select)));
  2834. ret = isp_s_exp2_inputsel(dev);
  2835. break;
  2836. case ISPIOC_S_EXP2_SIZERATIO: {
  2837. u32 ratio;
  2838. viv_check_retval(copy_from_user(&ratio, args, sizeof(ratio)));
  2839. ret = isp_s_exp2_sizeratio(dev, ratio);
  2840. break;
  2841. }
  2842. case ISPIOC_S_2DNR:
  2843. viv_check_retval(copy_from_user
  2844. (&dev->dnr2, args, sizeof(dev->dnr2)));
  2845. ret = isp_s_2dnr(dev);
  2846. break;
  2847. case ISPIOC_S_SIMP:
  2848. viv_check_retval(copy_from_user
  2849. (&dev->simp, args, sizeof(dev->simp)));
  2850. ret = isp_s_simp(dev);
  2851. break;
  2852. case ISPIOC_S_COMP:
  2853. viv_check_retval(copy_from_user
  2854. (&dev->comp, args, sizeof(dev->comp)));
  2855. ret = isp_s_comp(dev);
  2856. break;
  2857. case ISPIOC_S_CPROC:
  2858. viv_check_retval(copy_from_user
  2859. (&dev->cproc, args, sizeof(dev->cproc)));
  2860. ret = isp_s_cproc(dev);
  2861. break;
  2862. case ISPIOC_S_XTALK:
  2863. viv_check_retval(copy_from_user
  2864. (&dev->xtalk, args, sizeof(dev->xtalk)));
  2865. ret = isp_s_xtalk(dev);
  2866. break;
  2867. case ISPIOC_S_ELAWB:
  2868. viv_check_retval(copy_from_user
  2869. (&dev->elawb, args, sizeof(dev->elawb)));
  2870. ret = isp_s_elawb(dev);
  2871. break;
  2872. case ISPIOC_S_INPUT:
  2873. viv_check_retval(copy_from_user
  2874. (&dev->ctx, args, sizeof(dev->ctx)));
  2875. ret = isp_s_input(dev);
  2876. break;
  2877. case ISPIOC_S_DEMOSAIC:
  2878. viv_check_retval(copy_from_user
  2879. (&dev->ctx, args, sizeof(dev->ctx)));
  2880. ret = isp_s_demosaic(dev);
  2881. break;
  2882. case ISPIOC_MI_START:
  2883. viv_check_retval(copy_from_user
  2884. (&dev->mi, args, sizeof(dev->mi)));
  2885. ret = isp_mi_start(dev);
  2886. break;
  2887. case ISPIOC_S_HDR_WB:
  2888. viv_check_retval(copy_from_user
  2889. (&dev->hdr, args, sizeof(dev->hdr)));
  2890. ret = isp_s_hdr_wb(dev);
  2891. break;
  2892. case ISPIOC_S_HDR_BLS:
  2893. viv_check_retval(copy_from_user
  2894. (&dev->hdr, args, sizeof(dev->hdr)));
  2895. ret = isp_s_hdr_bls(dev);
  2896. break;
  2897. case ISPIOC_S_HDR_DIGITAL_GAIN:
  2898. viv_check_retval(copy_from_user
  2899. (&dev->hdr, args, sizeof(dev->hdr)));
  2900. // ret = isp_s_hdr_digal_gain(dev);
  2901. break;
  2902. case ISPIOC_S_GAMMA_OUT:{
  2903. viv_check_retval(copy_from_user
  2904. (&dev->gamma_out, args,
  2905. sizeof(dev->gamma_out)));
  2906. ret = isp_s_gamma_out(dev);
  2907. break;
  2908. }
  2909. case ISPIOC_SET_BUFFER:{
  2910. struct isp_buffer_context buf;
  2911. viv_check_retval(copy_from_user
  2912. (&buf, args, sizeof(buf)));
  2913. #if defined(__KERNEL__) && defined(ENABLE_IRQ)
  2914. if (dev->alloc)
  2915. ret = dev->alloc(dev, &buf);
  2916. #else
  2917. ret = isp_set_buffer(dev, &buf);
  2918. #endif
  2919. break;
  2920. }
  2921. case ISPIOC_SET_BP_BUFFER:{
  2922. struct isp_bp_buffer_context buf;
  2923. viv_check_retval(copy_from_user
  2924. (&buf, args, sizeof(buf)));
  2925. ret = isp_set_bp_buffer(dev, &buf);
  2926. break;
  2927. }
  2928. case ISPIOC_START_CAPTURE:{
  2929. u32 num;
  2930. viv_check_retval(copy_from_user
  2931. (&num, args, sizeof(num)));
  2932. ret = isp_start_stream(dev, num);
  2933. if(!ret) {
  2934. dev->streaming = true;
  2935. }
  2936. break;
  2937. }
  2938. #if defined(ISP_3DNR_V2) || defined(ISP_3DNR_V2_V1)
  2939. case ISPIOC_S_3DNR_CMP: {
  2940. viv_check_retval(
  2941. copy_from_user(&dev->dnr3.compress, args, sizeof(dev->dnr3.compress)));
  2942. ret = isp_s_3dnr_cmp(dev);
  2943. break;
  2944. }
  2945. #endif
  2946. #if defined(ISP_3DNR) || defined(ISP_3DNR_V2)
  2947. case ISPIOC_U_3DNR:{
  2948. struct isp_3dnr_update param;
  2949. viv_check_retval(copy_from_user
  2950. (&param, args, sizeof(param)));
  2951. ret = isp_u_3dnr(dev, &param);
  2952. break;
  2953. }
  2954. case ISPIOC_S_3DNR:
  2955. viv_check_retval(copy_from_user
  2956. (&dev->dnr3, args, sizeof(dev->dnr3)));
  2957. ret = isp_s_3dnr(dev);
  2958. break;
  2959. case ISPIOC_U_3DNR_STRENGTH: {
  2960. viv_check_retval(
  2961. copy_from_user(&dev->dnr3, args, sizeof(dev->dnr3)));
  2962. ret = isp_u_3dnr_strength(dev);
  2963. break;
  2964. }
  2965. case ISPIOC_S_3DNR_MOT:{
  2966. viv_check_retval(copy_from_user
  2967. (&dev->dnr3, args, sizeof(dev->dnr3)));
  2968. ret = isp_s_3dnr_motion(dev);
  2969. break;
  2970. }
  2971. case ISPIOC_S_3DNR_DLT:{
  2972. viv_check_retval(copy_from_user
  2973. (&dev->dnr3, args, sizeof(dev->dnr3)));
  2974. ret = isp_s_3dnr_delta(dev);
  2975. break;
  2976. }
  2977. case ISPIOC_G_3DNR:{
  2978. u32 avg;
  2979. ret = isp_g_3dnr(dev, &avg);
  2980. viv_check_retval(copy_to_user(args, &avg, sizeof(avg)));
  2981. break;
  2982. }
  2983. #endif
  2984. case ISPIOC_G_AWBMEAN:{
  2985. struct isp_awb_mean mean;
  2986. ret = isp_g_awbmean(dev, &mean);
  2987. viv_check_retval(copy_to_user
  2988. (args, &mean, sizeof(mean)));
  2989. break;
  2990. }
  2991. case ISPIOC_G_EXPMEAN:{
  2992. u8 mean[25];
  2993. ret = isp_g_expmean(dev, mean);
  2994. viv_check_retval(copy_to_user
  2995. (args, mean, sizeof(mean)));
  2996. break;
  2997. }
  2998. case ISPIOC_G_HDREXPMEAN:{
  2999. u8 mean[75];
  3000. ret = isp_g_hdrexpmean(dev, mean);
  3001. viv_check_retval(copy_to_user
  3002. (args, mean, sizeof(mean)));
  3003. break;
  3004. }
  3005. case ISPIOC_G_HISTMEAN:{
  3006. u32 mean[HIST_BIN_TOTAL];
  3007. ret = isp_g_histmean(dev, mean);
  3008. viv_check_retval(copy_to_user
  3009. (args, mean, sizeof(mean)));
  3010. break;
  3011. }
  3012. case ISPIOC_G_HDRHISTMEAN:{
  3013. u32 mean[48];
  3014. ret = isp_g_hdrhistmean(dev, mean);
  3015. viv_check_retval(copy_to_user
  3016. (args, mean, sizeof(mean)));
  3017. break;
  3018. }
  3019. #ifdef ISP_HIST64_RY
  3020. case ISPIOC_G_HIST64MEAN:{
  3021. u32 mean[HIST64_BIN_TOTAL];
  3022. ret = isp_g_hist64mean(dev, mean);
  3023. viv_check_retval(copy_to_user
  3024. (args, mean, sizeof(mean)));
  3025. break;
  3026. }
  3027. case ISPIOC_G_HIST64VSTART_STATUS:{
  3028. u32 status = 0;
  3029. ret = isp_g_hist64_vstart_status(dev, &status);
  3030. viv_check_retval(copy_to_user
  3031. (args, &status, sizeof(status)));
  3032. break;
  3033. }
  3034. #endif
  3035. case ISPIOC_G_VSM:{
  3036. struct isp_vsm_result vsm;
  3037. ret = isp_g_vsm(dev, &vsm);
  3038. viv_check_retval(copy_to_user(args, &vsm, sizeof(vsm)));
  3039. break;
  3040. }
  3041. case ISPIOC_G_AFM:{
  3042. struct isp_afm_result afm;
  3043. ret = isp_g_afm(dev, &afm);
  3044. viv_check_retval(copy_to_user(args, &afm, sizeof(afm)));
  3045. break;
  3046. }
  3047. case ISPIOC_G_STATUS:
  3048. ret = isp_ioc_g_status(dev, args);
  3049. break;
  3050. case ISPIOC_G_FEATURE:
  3051. ret = isp_ioc_g_feature(dev, args);
  3052. break;
  3053. case ISPIOC_G_FEATURE_VERSION:
  3054. ret = isp_ioc_g_feature_veresion(dev, args);
  3055. break;
  3056. case ISPIOC_WDR_CONFIG:
  3057. viv_check_retval(copy_from_user
  3058. (&dev->wdr, args, sizeof(dev->wdr)));
  3059. ret = isp_s_wdr(dev);
  3060. break;
  3061. case ISPIOC_S_WDR_CURVE:
  3062. viv_check_retval(copy_from_user
  3063. (&dev->wdr, args, sizeof(dev->wdr)));
  3064. ret = isp_s_wdr_curve(dev);
  3065. break;
  3066. case ISPIOC_ENABLE_GCMONO:
  3067. viv_check_retval(copy_from_user
  3068. (&dev->gcmono.mode, args, sizeof(u32)));
  3069. ret = isp_enable_gcmono(dev);
  3070. break;
  3071. case ISPIOC_DISABLE_GCMONO:
  3072. ret = isp_disable_gcmono(dev);
  3073. break;
  3074. case ISPIOC_S_GCMONO:{
  3075. struct isp_gcmono_data *data;
  3076. #ifdef __KERNEL__
  3077. data = (struct isp_gcmono_data *)
  3078. kmalloc(sizeof(struct isp_gcmono_data), GFP_KERNEL);
  3079. #else
  3080. data = (struct isp_gcmono_data *)
  3081. malloc(sizeof(struct isp_gcmono_data));
  3082. #endif
  3083. if (data == NULL) {
  3084. isp_err("%s, malloc mem for rgb gamma failed.", __func__);
  3085. ret = -1;
  3086. } else {
  3087. viv_check_retval(copy_from_user
  3088. (data, args,
  3089. sizeof(struct
  3090. isp_gcmono_data)));
  3091. ret = isp_s_gcmono(dev, data);
  3092. #ifdef __KERNEL__
  3093. kfree(data);
  3094. #else
  3095. free(data);
  3096. #endif
  3097. }
  3098. break;
  3099. }
  3100. case ISPIOC_ENABLE_RGBGAMMA:
  3101. ret = isp_enable_rgbgamma(dev);
  3102. break;
  3103. case ISPIOC_DISABLE_RGBGAMMA:
  3104. ret = isp_disable_rgbgamma(dev);
  3105. break;
  3106. case ISPIOC_S_RGBGAMMA:{
  3107. struct isp_rgbgamma_data *data;
  3108. #ifdef __KERNEL__
  3109. data = (struct isp_rgbgamma_data *)
  3110. kmalloc(sizeof(struct isp_rgbgamma_data),
  3111. GFP_KERNEL);
  3112. #else
  3113. data = (struct isp_rgbgamma_data *)
  3114. malloc(sizeof(struct isp_rgbgamma_data));
  3115. #endif
  3116. if (data == NULL) {
  3117. isp_err("%s, malloc mem for rgb gamma failed.", __func__);
  3118. ret = -1;
  3119. } else {
  3120. viv_check_retval(copy_from_user
  3121. (data, args,
  3122. sizeof(struct
  3123. isp_rgbgamma_data)));
  3124. ret = isp_s_rgbgamma(dev, data);
  3125. #ifdef __KERNEL__
  3126. kfree(data);
  3127. #else
  3128. free(data);
  3129. #endif
  3130. }
  3131. break;
  3132. }
  3133. case ISPIOC_S_GREENEQUILIBRATE:
  3134. viv_check_retval(copy_from_user
  3135. (&dev->ge, args, sizeof(dev->ge)));
  3136. ret = isp_s_ge(dev);
  3137. break;
  3138. case ISPIOC_S_COLOR_ADJUST:
  3139. viv_check_retval(copy_from_user
  3140. (&dev->ca, args, sizeof(dev->ca)));
  3141. ret = isp_s_ca(dev);
  3142. break;
  3143. #ifdef __KERNEL__
  3144. case VIDIOC_QUERYCAP:
  3145. ret = isp_ioc_qcap(dev, args);
  3146. break;
  3147. #endif
  3148. case ISPIOC_G_QUERY_EXTMEM:
  3149. ret = isp_get_extmem(dev, args);
  3150. break;
  3151. case ISPIOC_ENABLE_RGBIR:
  3152. viv_check_retval(copy_from_user
  3153. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3154. ret = isp_enable_rgbir(dev);
  3155. break;
  3156. case ISPIOC_S_RGBIR:
  3157. viv_check_retval(copy_from_user
  3158. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3159. ret = isp_s_rgbir(dev);
  3160. break;
  3161. case ISPIOC_RGBIR_HW_INIT:
  3162. viv_check_retval(copy_from_user
  3163. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3164. ret = isp_rgbir_hw_init(dev);
  3165. break;
  3166. case ISPIOC_RGBIR_S_IR_DNR:
  3167. viv_check_retval(copy_from_user
  3168. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3169. ret = isp_rgbir_s_ir_dnr(dev);
  3170. break;
  3171. case ISPIOC_RGBIR_S_SHARPEN:
  3172. viv_check_retval(copy_from_user
  3173. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3174. ret = isp_rgbir_s_sharpen(dev);
  3175. break;
  3176. case ISPIOC_RGBIR_S_DES:
  3177. viv_check_retval(copy_from_user
  3178. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3179. ret = isp_rgbir_s_des(dev);
  3180. break;
  3181. case ISPIOC_RGBIR_S_CC_MATRIX:
  3182. viv_check_retval(copy_from_user
  3183. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3184. ret = isp_rgbir_s_cc_matrix(dev);
  3185. break;
  3186. case ISPIOC_RGBIR_S_DPCC:
  3187. viv_check_retval(copy_from_user
  3188. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3189. ret = isp_rgbir_s_dpcc(dev);
  3190. break;
  3191. case ISPIOC_RGBIR_S_GAIN:
  3192. viv_check_retval(copy_from_user
  3193. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3194. ret = isp_rgbir_s_gain(dev);
  3195. break;
  3196. case ISPIOC_RGBIR_S_BLS:
  3197. viv_check_retval(copy_from_user
  3198. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3199. ret = isp_rgbir_s_bls(dev);
  3200. break;
  3201. case ISPIOC_RGBIR_S_IR_RAW_OUT:
  3202. viv_check_retval(copy_from_user
  3203. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3204. ret = isp_rgbir_out_ir_raw(dev);
  3205. break;
  3206. case ISPIOC_S_CROP:
  3207. viv_check_retval(copy_from_user
  3208. (&dev->crop, args, sizeof(struct isp_crop_context) * 3));
  3209. ret = isp_set_crop(dev);
  3210. break;
  3211. #ifdef ISP_3DNR_V3
  3212. case ISPIOC_S_TDNR:
  3213. viv_check_retval(copy_from_user
  3214. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3215. ret = isp_s_tdnr(dev);
  3216. break;
  3217. case ISPIOC_TDNR_ENABLE:
  3218. ret = isp_tdnr_enable(dev);
  3219. break;
  3220. case ISPIOC_TDNR_DISABLE:
  3221. ret = isp_tdnr_disable(dev);
  3222. break;
  3223. case ISPIOC_TDNR_ENABLE_TDNR:
  3224. ret = isp_tdnr_enable_tdnr(dev);
  3225. break;
  3226. case ISPIOC_TDNR_DISABLE_TDNR:
  3227. ret = isp_tdnr_disable_tdnr(dev);
  3228. break;
  3229. case ISPIOC_TDNR_ENABLE_2DNR:
  3230. ret = isp_tdnr_enable_2dnr(dev);
  3231. break;
  3232. case ISPIOC_TDNR_DISABLE_2DNR:
  3233. ret = isp_tdnr_disable_2dnr(dev);
  3234. break;
  3235. case ISPIOC_S_TDNR_CURVE:
  3236. viv_check_retval(copy_from_user
  3237. (&dev->tdnr.curve, args, sizeof(dev->tdnr.curve)));
  3238. ret = isp_tdnr_cfg_gamma(dev);
  3239. break;
  3240. case ISPIOC_G_TDNR: {
  3241. struct isp_tdnr_stats stats;
  3242. ret = isp_tdnr_g_stats(dev, &stats);
  3243. viv_check_retval(copy_to_user(args, &stats, sizeof(stats)));
  3244. }
  3245. break;
  3246. case ISPIOC_S_TDNR_STRENGTH:
  3247. viv_check_retval(copy_from_user
  3248. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3249. ret = isp_tdnr_set_strength(dev);
  3250. break;
  3251. case ISPIOC_U_TDNR_NOISE:
  3252. viv_check_retval(copy_from_user
  3253. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3254. ret = isp_tdnr_u_noise(dev);
  3255. break;
  3256. case ISPIOC_U_TDNR_THR:
  3257. viv_check_retval(copy_from_user
  3258. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3259. ret = isp_tdnr_u_thr(dev);
  3260. break;
  3261. case ISPIOC_R_TDNR_REFER:
  3262. ret = isp_r_tdnr_refer(dev);
  3263. break;
  3264. case ISPIOC_R_TDNR_MOTION:
  3265. ret = isp_r_tdnr_motion(dev);
  3266. break;
  3267. case ISPIOC_S_TDNR_BUF:
  3268. viv_check_retval(copy_from_user
  3269. (&dev->tdnr.buf, args, sizeof(dev->tdnr.buf)));
  3270. ret = isp_tdnr_s_buf(dev);
  3271. break;
  3272. #endif
  3273. #ifdef ISP_MI_PP_WRITE_RY
  3274. case ISPIOC_GET_PPW_LINE_CNT:
  3275. {
  3276. u16 ppw_pic_cnt;
  3277. ret = isp_get_ppw_pic_cnt(dev, &ppw_pic_cnt);
  3278. viv_check_retval(copy_to_user
  3279. (args, &ppw_pic_cnt, sizeof(ppw_pic_cnt)));
  3280. break;
  3281. }
  3282. case ISPIOC_SET_PPW_LINE_NUM:
  3283. {
  3284. viv_check_retval(copy_from_user
  3285. (&dev->pp_write, args, sizeof(dev->pp_write)));
  3286. ret = isp_set_ppw_line_num(dev);
  3287. break;
  3288. }
  3289. #endif
  3290. #ifdef ISP_MI_PP_READ_RY
  3291. case ISPIOC_CFG_DMA_LINE_ENTRY:
  3292. viv_check_retval(copy_from_user
  3293. (&dev->pp_dma_line_entry, args, sizeof(dev->pp_dma_line_entry)));
  3294. ret = isp_cfg_pp_dma_line_entry(dev);
  3295. break;
  3296. #endif
  3297. default:
  3298. isp_err("unsupported command %d", cmd);
  3299. break;
  3300. }
  3301. if (cmd != ISPIOC_WRITE_REG) //frame end isp update shd registers.
  3302. ISP_GEN_CFG_UPDATE(dev);
  3303. return ret;
  3304. }