vi_pre_ioctl.c 30 KB

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  1. /*
  2. * Copyright (C) 2021 Alibaba Group Holding Limited
  3. * Author: Shenwuyi <shenwuyi.swy@alibaba-inc.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. */
  9. #include <linux/poll.h>
  10. #include <linux/regmap.h>
  11. #include <linux/of_reserved_mem.h>
  12. #include <linux/io.h>
  13. #include "vi_pre.h"
  14. #include "vi_pre_ioctl.h"
  15. #include "vi_pre_reg.h"
  16. #define check_retval(x)\
  17. do {\
  18. if ((x))\
  19. return -EIO;\
  20. } while (0)
  21. static void vi_pre_write(struct vi_pre_dev *dec, unsigned int addr, unsigned int val)
  22. {
  23. writel(val, dec->reg_base + addr);
  24. }
  25. static unsigned int vi_pre_read(struct vi_pre_dev *dev, unsigned int addr)
  26. {
  27. return readl(dev->reg_base + addr);
  28. }
  29. static int vi_pre_write_reg(struct vi_pre_dev *dev, void *__user args)
  30. {
  31. struct vi_pre_reg_t reg;
  32. unsigned int val;
  33. check_retval(copy_from_user(&reg, args, sizeof(reg)));
  34. vi_pre_write(dev, reg.offset, reg.value);
  35. pr_info("%s write addr 0x%08x val 0x%08x\n", __func__, reg.offset, reg.value);
  36. val = vi_pre_read(dev, reg.offset);
  37. pr_info("%s rad back addr 0x%08x val 0x%08x\n", __func__, reg.offset, val);
  38. return 0;
  39. }
  40. static int vi_pre_read_reg(struct vi_pre_dev *dev, void *__user args)
  41. {
  42. struct vi_pre_reg_t reg;
  43. check_retval(copy_from_user(&reg, args, sizeof(reg)));
  44. reg.value = vi_pre_read(dev, reg.offset);
  45. check_retval(copy_to_user(args, &reg, sizeof(reg)));
  46. //pr_info("%s addr 0x%08x val 0x%08x\n", __func__, reg.offset, reg.value);
  47. return 0;
  48. }
  49. static int vi_pre_set_hdrpro_merge_para(struct vi_pre_dev *dev, void *args)
  50. {
  51. int ret = 0;
  52. unsigned int i = 0, j = 0, val = 0;
  53. struct hdrpro_merge_para merge_para;
  54. struct hdrpro_para *w;
  55. struct hdrpro_para *b;
  56. struct hdrpro_para *a;
  57. check_retval(copy_from_user(&merge_para, args, sizeof(merge_para)));
  58. a = &merge_para.a;
  59. b = &merge_para.b;
  60. w = &merge_para.w;
  61. for (i = HDRPRO_LINW(1); i <= HDRPRO_LINW(8); i += 4) {
  62. val = 0;
  63. val |= (w->para[j] << 16);
  64. j++;
  65. val |= w->para[j];
  66. j++;
  67. vi_pre_write(dev, i, val);
  68. }
  69. j = 0;
  70. for (i = HDRPRO_LINA(1); i <= HDRPRO_LINA(16); i += 4) {
  71. val = 0;
  72. val |= a->para[j];
  73. vi_pre_write(dev, i, val);
  74. j++;
  75. }
  76. j = 0;
  77. for (i = HDRPRO_LINB(1); i <= HDRPRO_LINB(16); i += 4) {
  78. val = 0;
  79. val |= b->para[j];
  80. vi_pre_write(dev, i, val);
  81. j++;
  82. }
  83. return ret;
  84. }
  85. static int vi_pre_set_hdrpro_color_para(struct vi_pre_dev *dev, void *args)
  86. {
  87. int ret = 0;
  88. unsigned int val = 0;
  89. struct hdrpro_color_para color_para;
  90. check_retval(copy_from_user(&color_para, args, sizeof(color_para)));
  91. val = vi_pre_read(dev, HDRPRO_COE(1));
  92. val &= ~HDRPRO_COE1_BE_COLOR_WG0_00_MASK;
  93. val |= (color_para.wg0.pattern_00 << HDRPRO_COE1_BE_COLOR_WG0_00_SHIFT);
  94. val &= ~HDRPRO_COE1_BE_COLOR_WG0_01_MASK;
  95. val |= (color_para.wg0.pattern_01 << HDRPRO_COE1_BE_COLOR_WG0_01_SHIFT);
  96. val &= ~HDRPRO_COE1_BE_COLOR_WG0_02_MASK;
  97. val |= (color_para.wg0.pattern_02 << HDRPRO_COE1_BE_COLOR_WG0_02_SHIFT);
  98. val &= ~HDRPRO_COE1_BE_COLOR_WG0_10_MASK;
  99. val |= (color_para.wg0.pattern_10 << HDRPRO_COE1_BE_COLOR_WG0_10_SHIFT);
  100. vi_pre_write(dev, HDRPRO_COE(1), val);
  101. //val = vi_pre_read(dev, HDRPRO_COE(2));
  102. val = 0;
  103. val |= (color_para.wg0.pattern_11 << HDRPRO_COE2_BE_COLOR_WG0_11_SHIFT);
  104. val |= (color_para.wg0.pattern_12 << HDRPRO_COE2_BE_COLOR_WG0_12_SHIFT);
  105. val |= (color_para.wg0.pattern_20 << HDRPRO_COE2_BE_COLOR_WG0_20_SHIFT);
  106. val |= (color_para.wg0.pattern_21 << HDRPRO_COE2_BE_COLOR_WG0_21_SHIFT);
  107. val |= (color_para.wg0.pattern_22 << HDRPRO_COE2_BE_COLOR_WG0_22_SHIFT);
  108. val |= (color_para.wg1.pattern_00 << HDRPRO_COE2_BE_COLOR_WG1_00_SHIFT);
  109. val |= (color_para.wg1.pattern_01 << HDRPRO_COE2_BE_COLOR_WG1_01_SHIFT);
  110. val |= (color_para.wg1.pattern_02 << HDRPRO_COE2_BE_COLOR_WG1_02_SHIFT);
  111. vi_pre_write(dev, HDRPRO_COE(2), val);
  112. //val = vi_pre_read(dev, HDRPRO_COE(3));
  113. val = 0;
  114. val |= (color_para.wg1.pattern_10 << HDRPRO_COE3_BE_COLOR_WG1_10_SHIFT);
  115. val |= (color_para.wg1.pattern_11 << HDRPRO_COE3_BE_COLOR_WG1_11_SHIFT);
  116. val |= (color_para.wg1.pattern_12 << HDRPRO_COE3_BE_COLOR_WG1_12_SHIFT);
  117. val |= (color_para.wg1.pattern_20 << HDRPRO_COE3_BE_COLOR_WG1_20_SHIFT);
  118. val |= (color_para.wg1.pattern_21 << HDRPRO_COE3_BE_COLOR_WG1_21_SHIFT);
  119. val |= (color_para.wg1.pattern_22 << HDRPRO_COE3_BE_COLOR_WG1_22_SHIFT);
  120. val |= (color_para.wr.pattern_00 << HDRPRO_COE3_BE_COLOR_WR_00_SHIFT);
  121. val |= (color_para.wr.pattern_01 << HDRPRO_COE3_BE_COLOR_WR_01_SHIFT);
  122. vi_pre_write(dev, HDRPRO_COE(3), val);
  123. //val = vi_pre_read(dev, HDRPRO_COE(4));
  124. val = 0;
  125. val |= (color_para.wr.pattern_02 << HDRPRO_COE4_BE_COLOR_WR_02_SHIFT);
  126. val |= (color_para.wr.pattern_10 << HDRPRO_COE4_BE_COLOR_WR_10_SHIFT);
  127. val |= (color_para.wr.pattern_11 << HDRPRO_COE4_BE_COLOR_WR_11_SHIFT);
  128. val |= (color_para.wr.pattern_12 << HDRPRO_COE4_BE_COLOR_WR_12_SHIFT);
  129. val |= (color_para.wr.pattern_20 << HDRPRO_COE4_BE_COLOR_WR_20_SHIFT);
  130. val |= (color_para.wr.pattern_21 << HDRPRO_COE4_BE_COLOR_WR_21_SHIFT);
  131. val |= (color_para.wr.pattern_22 << HDRPRO_COE4_BE_COLOR_WR_22_SHIFT);
  132. val |= (color_para.wb.pattern_00 << HDRPRO_COE4_BE_COLOR_WB_00_SHIFT);
  133. vi_pre_write(dev, HDRPRO_COE(4), val);
  134. //val = vi_pre_read(dev, HDRPRO_COE(5));
  135. val = 0;
  136. val |= (color_para.wb.pattern_01 << HDRPRO_COE5_BE_COLOR_WB_01_SHIFT);
  137. val |= (color_para.wb.pattern_02 << HDRPRO_COE5_BE_COLOR_WB_02_SHIFT);
  138. val |= (color_para.wb.pattern_10 << HDRPRO_COE5_BE_COLOR_WB_10_SHIFT);
  139. val |= (color_para.wb.pattern_11 << HDRPRO_COE5_BE_COLOR_WB_11_SHIFT);
  140. val |= (color_para.wb.pattern_12 << HDRPRO_COE5_BE_COLOR_WB_12_SHIFT);
  141. val |= (color_para.wb.pattern_20 << HDRPRO_COE5_BE_COLOR_WB_20_SHIFT);
  142. val |= (color_para.wb.pattern_21 << HDRPRO_COE5_BE_COLOR_WB_21_SHIFT);
  143. val |= (color_para.wb.pattern_22 << HDRPRO_COE5_BE_COLOR_WB_22_SHIFT);
  144. vi_pre_write(dev, HDRPRO_COE(5), val);
  145. err:
  146. return ret;
  147. }
  148. static int vi_pre_set_hdrpro_black_para(struct vi_pre_dev *dev, void *args)
  149. {
  150. int ret = 0;
  151. unsigned int val = 0;
  152. struct hdrpro_black_para black_para;
  153. check_retval(copy_from_user(&black_para, args, sizeof(black_para)));
  154. val = vi_pre_read(dev, HDRPRO_COE(1));
  155. val &= ~HDRPRO_COE1_BE_BLACK_WR_MASK;
  156. val |= (black_para.weight_para.wr << HDRPRO_COE1_BE_BLACK_WR_SHIFT);
  157. val &= ~HDRPRO_COE1_BE_BLACK_WB_MASK;
  158. val |= (black_para.weight_para.wb << HDRPRO_COE1_BE_BLACK_WB_SHIFT);
  159. val &= ~HDRPRO_COE1_BE_BLACK_WG0_MASK;
  160. val |= (black_para.weight_para.wg0 << HDRPRO_COE1_BE_BLACK_WG0_SHIFT);
  161. val &= ~HDRPRO_COE1_BE_BLACK_WG1_MASK;
  162. val |= (black_para.weight_para.wg1 << HDRPRO_COE1_BE_BLACK_WG1_SHIFT);
  163. vi_pre_write(dev, HDRPRO_COE(1), val);
  164. err:
  165. return ret;
  166. }
  167. static int vi_pre_set_hdrpro_resolution(struct vi_pre_dev *dev, void *args)
  168. {
  169. int ret = 0;
  170. unsigned int val = 0;
  171. struct hdrpro_resolution resolution;
  172. check_retval(copy_from_user(&resolution, args, sizeof(resolution)));
  173. val = vi_pre_read(dev, HDRPRO_CTRL(2));
  174. val &= ~HDRPRO_CTRL2_VERTICAL_MASK;
  175. val |= (resolution.height << HDRPRO_CTRL2_VERTICAL_SHIFT);
  176. val &= ~HDRPRO_CTRL2_HORIZON_MASK;
  177. val |= (resolution.width << HDRPRO_CTRL2_HORIZON_SHIFT);
  178. vi_pre_write(dev, HDRPRO_CTRL(2), val);
  179. return ret;
  180. }
  181. static int vi_pre_set_hdrpro_mode(struct vi_pre_dev *dev, void *args)
  182. {
  183. int ret = 0;
  184. unsigned int val = 0;
  185. struct hdrpro_mode mode;
  186. check_retval(copy_from_user(&mode, args, sizeof(mode)));
  187. val = vi_pre_read(dev, HDRPRO_CTRL(1));
  188. val &= ~HDRPRO_CTRL1_BAYER_MODSEL_MASK;
  189. val |= mode.bayer_modesel;
  190. val &= ~HDRPRO_CTRL1_COLOR_MODSEL_MASK;
  191. val |= mode.color_modesel;
  192. val &= ~HDRPRO_CTRL1_HDRPRO_RAWMOD_MASK;
  193. val |= mode.raw_mode;
  194. vi_pre_write(dev, HDRPRO_CTRL(1), val);
  195. return ret;
  196. }
  197. static int vi_pre_hdrpro_en(struct vi_pre_dev *dev, int en)
  198. {
  199. int ret = 0;
  200. unsigned int val = 0;
  201. val = vi_pre_read(dev, HDRPRO_CTRL(1));
  202. val &= ~HDRPRO_CTRL1_HDRPRO_EN_MASK;
  203. val |= en;
  204. vi_pre_write(dev, HDRPRO_CTRL(1), val);
  205. return ret;
  206. }
  207. static int vi_pre_set_mipi2dma_n_line(struct vi_pre_dev *dev, void *args)
  208. {
  209. #define WIDTH 640
  210. #define HEIGHT 480
  211. #define RAW_SIZE 16 //RAW12
  212. #define BURST_LEN 16
  213. #define OUT_STANDING 1024
  214. //K > N, N>2
  215. #define K_LINE 32
  216. #define N_LINE 16
  217. int ret = 0;
  218. unsigned int val = 0;
  219. unsigned int stride = 0;
  220. unsigned int horizon_cnt128 = 0;
  221. unsigned int readnum = 0;
  222. stride = WIDTH * RAW_SIZE / 8;
  223. horizon_cnt128 = stride / 16;
  224. readnum = horizon_cnt128 / BURST_LEN;
  225. //base mode config
  226. //val = vi_pre_read(dev, MIPI2DMA_CTRL(0));
  227. val = 0;
  228. val |= MIPI2DMA_CTRL0_MODE_N_LINE;
  229. val |= MIPI2DMA_CTRL0_RAW10;
  230. val |= MIPI2DMA_CTRL0_HIGH_BIT_MODE;
  231. //val |= MIPI2DMA_CTRL0_4_FRAME;
  232. vi_pre_write(dev, MIPI2DMA_CTRL(0), val);
  233. //val = vi_pre_read(dev, MIPI2DMA_CTRL(1));
  234. val = 0;
  235. val |= MIPI2DMA_CTRL1_WBURSTLEN_16;
  236. val |= ((OUT_STANDING - 1) << MIPI2DMA_CTRL1_WOSNUM_SHIFT);
  237. vi_pre_write(dev, MIPI2DMA_CTRL(1), val);
  238. //val = vi_pre_read(dev, MIPI2DMA_CTRL(3));
  239. val = 0;
  240. val |= (WIDTH << MIPI2DMA_CTRL3_HORIZON_SHIFT);
  241. val |= (HEIGHT << MIPI2DMA_CTRL3_VERTICAL_SHIFT);
  242. vi_pre_write(dev, MIPI2DMA_CTRL(3), val);
  243. //val = vi_pre_read(dev, MIPI2DMA_CTRL(4));
  244. val = 0;
  245. //need calculate BURSTREM by unsing the function from vipre doc
  246. val |= (BURST_LEN << MIPI2DMA_CTRL4_BURSTREM_SHIFT);
  247. val |= (readnum << MIPI2DMA_CTRL4_READNUM_SHIFT);
  248. val |= (horizon_cnt128 << MIPI2DMA_CTRL4_HORIZON_CNT128_SHIFT);
  249. vi_pre_write(dev, MIPI2DMA_CTRL(4), val);
  250. //val = vi_pre_read(dev, MIPI2DMA_CTRL(5));
  251. val = 0;
  252. val |= (N_LINE << MIPI2DMA_CTRL5_N_NLINENUM_SHIFT);
  253. val |= (K_LINE << MIPI2DMA_CTRL5_N_LINENUM_SHIFT);
  254. vi_pre_write(dev, MIPI2DMA_CTRL(5), val);
  255. //val = vi_pre_read(dev, MIPI2DMA_CTRL(6));
  256. val = 0;
  257. val |= (stride << MIPI2DMA_CTRL6_N_STRIDE_SHIFT);
  258. vi_pre_write(dev, MIPI2DMA_CTRL(6), val);
  259. val = vi_pre_read(dev, MIPI2DMA_CTRL(51));
  260. val |= MIPI2DMA_CTRL51_CROSS_4K_EN;
  261. vi_pre_write(dev, MIPI2DMA_CTRL(51), val);
  262. //feedback config to default
  263. //clear INV_FLAG
  264. val = 0;
  265. vi_pre_write(dev, MIPI2DMA_CTRL(11), val);
  266. //clear N_LINENUM_NEW_ID0
  267. val = 0;
  268. vi_pre_write(dev, MIPI2DMA_CTRL(12), val);
  269. //clear N_LINENUM_NEW_ID1
  270. val = 0;
  271. vi_pre_write(dev, MIPI2DMA_CTRL(13), val);
  272. //clear N_LINENUM_NEW_ID2
  273. val = 0;
  274. vi_pre_write(dev, MIPI2DMA_CTRL(14), val);
  275. //clear N_num_done_idx
  276. val = 0;
  277. vi_pre_write(dev, MIPI2DMA_CTRL(21), val);
  278. val = 0;
  279. vi_pre_write(dev, MIPI2DMA_CTRL(22), val);
  280. //N ID0 address
  281. //val = vi_pre_read(dev, MIPI2DMA_CTRL(15));
  282. val = 0;
  283. val |= (0x0 << MIPI2DMA_CTRL15_N_SADDR_ID0_H_SHIFT);
  284. vi_pre_write(dev, MIPI2DMA_CTRL(15), val);
  285. //val = vi_pre_read(dev, MIPI2DMA_CTRL(16));
  286. val = 0;
  287. val |= (0xf0000000 << MIPI2DMA_CTRL16_N_SADDR_ID0_L_SHIFT);
  288. vi_pre_write(dev, MIPI2DMA_CTRL(16), val);
  289. //N ID1 address
  290. //val = vi_pre_read(dev, MIPI2DMA_CTRL(17));
  291. val = 0;
  292. val |= (0x0 << MIPI2DMA_CTRL17_N_SADDR_ID1_H_SHIFT);
  293. vi_pre_write(dev, MIPI2DMA_CTRL(17), val);
  294. //val = vi_pre_read(dev, MIPI2DMA_CTRL(18));
  295. val = 0;
  296. val |= (0xf1000000 << MIPI2DMA_CTRL18_N_SADDR_ID1_L_SHIFT);
  297. vi_pre_write(dev, MIPI2DMA_CTRL(18), val);
  298. //N ID2 address
  299. //val = vi_pre_read(dev, MIPI2DMA_CTRL(19));
  300. val = 0;
  301. val |= (0x0 << MIPI2DMA_CTRL19_N_SADDR_ID2_H_SHIFT);
  302. vi_pre_write(dev, MIPI2DMA_CTRL(19), val);
  303. //val = vi_pre_read(dev, MIPI2DMA_CTRL(20));
  304. val = 0;
  305. val |= (0xf2000000 << MIPI2DMA_CTRL20_N_SADDR_ID2_L_SHIFT);
  306. vi_pre_write(dev, MIPI2DMA_CTRL(20), val);
  307. // int status clean & mask
  308. //val = vi_pre_read(dev, MIPI2DMA_CTRL(44));
  309. //enable all interrupt
  310. val = 0;
  311. vi_pre_write(dev, MIPI2DMA_CTRL(44), val);
  312. val = vi_pre_read(dev, MIPI2DMA_CTRL(10));
  313. val |= MIPI2DMA_START;
  314. vi_pre_write(dev, MIPI2DMA_CTRL(10), val);
  315. return ret;
  316. }
  317. #if 0
  318. extern void test(struct vi_pre_dev *pdev);
  319. static int vi_pre_set_mipi2dma_m_frame(struct vi_pre_dev *dev, void *args)
  320. {
  321. int ret = 0;
  322. test(dev);
  323. #if 0
  324. #define WIDTH 640
  325. #define HEIGHT 480
  326. #define RAW_SIZE 16 //RAW12
  327. #define BURST_LEN 16
  328. #define OUT_STANDING 1024
  329. int ret = 0;
  330. unsigned int val = 0;
  331. unsigned int stride = 0;
  332. unsigned int horizon_cnt128 = 0;
  333. unsigned int readnum = 0;
  334. stride = WIDTH * RAW_SIZE / 8;
  335. horizon_cnt128 = stride / 16;
  336. readnum = horizon_cnt128 / BURST_LEN;
  337. //base mode config
  338. //val = vi_pre_read(dev, MIPI2DMA_CTRL(0));
  339. val = 0;
  340. val |= MIPI2DMA_CTRL0_MODE_M_FRAME;
  341. val |= MIPI2DMA_CTRL0_RAW10;
  342. val |= MIPI2DMA_CTRL0_HIGH_BIT_MODE;
  343. val |= MIPI2DMA_CTRL0_4_FRAME;
  344. vi_pre_write(dev, MIPI2DMA_CTRL(0), val);
  345. //val = vi_pre_read(dev, MIPI2DMA_CTRL(1));
  346. val = 0;
  347. val |= MIPI2DMA_CTRL1_WBURSTLEN_16;
  348. val |= ((OUT_STANDING - 1) << MIPI2DMA_CTRL1_WOSNUM_SHIFT);
  349. vi_pre_write(dev, MIPI2DMA_CTRL(1), val);
  350. //val = vi_pre_read(dev, MIPI2DMA_CTRL(3));
  351. val = 0;
  352. val |= (WIDTH << MIPI2DMA_CTRL3_HORIZON_SHIFT);
  353. val |= (HEIGHT << MIPI2DMA_CTRL3_VERTICAL_SHIFT);
  354. vi_pre_write(dev, MIPI2DMA_CTRL(3), val);
  355. //val = vi_pre_read(dev, MIPI2DMA_CTRL(4));
  356. val = 0;
  357. //need calculate BURSTREM by unsing the function from vipre doc
  358. val |= (BURST_LEN << MIPI2DMA_CTRL4_BURSTREM_SHIFT);
  359. val |= (readnum << MIPI2DMA_CTRL4_READNUM_SHIFT);
  360. val |= (horizon_cnt128 << MIPI2DMA_CTRL4_HORIZON_CNT128_SHIFT);
  361. vi_pre_write(dev, MIPI2DMA_CTRL(4), val);
  362. //val = vi_pre_read(dev, MIPI2DMA_CTRL(7));
  363. val = 0;
  364. val |= (stride << MIPI2DMA_CTRL7_M0_STRIDE_SHIFT);
  365. val |= (stride << MIPI2DMA_CTRL7_M1_STRIDE_SHIFT);
  366. vi_pre_write(dev, MIPI2DMA_CTRL(7), val);
  367. //val = vi_pre_read(dev, MIPI2DMA_CTRL(8));
  368. val = 0;
  369. val |= (stride << MIPI2DMA_CTRL8_M2_STRIDE_SHIFT);
  370. val |= (stride << MIPI2DMA_CTRL8_M3_STRIDE_SHIFT);
  371. vi_pre_write(dev, MIPI2DMA_CTRL(8), val);
  372. //M0 ADDR
  373. val = vi_pre_read(dev, MIPI2DMA_CTRL(25));
  374. val |= (0x1 << MIPI2DMA_CTRL25_M0_SADDR_ID0_H_SHIFT);
  375. vi_pre_write(dev, MIPI2DMA_CTRL(25), val);
  376. val = vi_pre_read(dev, MIPI2DMA_CTRL(26));
  377. val |= (0x00000000 << MIPI2DMA_CTRL26_M0_SADDR_ID0_L_SHIFT);
  378. vi_pre_write(dev, MIPI2DMA_CTRL(26), val);
  379. val = vi_pre_read(dev, MIPI2DMA_CTRL(27));
  380. val |= (0x1 << MIPI2DMA_CTRL27_M0_SADDR_ID1_H_SHIFT);
  381. vi_pre_write(dev, MIPI2DMA_CTRL(27), val);
  382. val = vi_pre_read(dev, MIPI2DMA_CTRL(28));
  383. val |= (0x04000000 << MIPI2DMA_CTRL28_M0_SADDR_ID1_L_SHIFT);
  384. vi_pre_write(dev, MIPI2DMA_CTRL(28), val);
  385. val = vi_pre_read(dev, MIPI2DMA_CTRL(29));
  386. val |= (0x1 << MIPI2DMA_CTRL29_M0_SADDR_ID2_H_SHIFT);
  387. vi_pre_write(dev, MIPI2DMA_CTRL(29), val);
  388. val = vi_pre_read(dev, MIPI2DMA_CTRL(30));
  389. val |= (0x08000000 << MIPI2DMA_CTRL30_M0_SADDR_ID2_L_SHIFT);
  390. vi_pre_write(dev, MIPI2DMA_CTRL(30), val);
  391. //M1 ADDR
  392. val = vi_pre_read(dev, MIPI2DMA_CTRL(31));
  393. val |= (0x0 << MIPI2DMA_CTRL31_M1_SADDR_ID0_H_SHIFT);
  394. vi_pre_write(dev, MIPI2DMA_CTRL(31), val);
  395. val = vi_pre_read(dev, MIPI2DMA_CTRL(32));
  396. val |= (0xF3000000 << MIPI2DMA_CTRL32_M1_SADDR_ID0_L_SHIFT);
  397. vi_pre_write(dev, MIPI2DMA_CTRL(32), val);
  398. val = vi_pre_read(dev, MIPI2DMA_CTRL(33));
  399. val |= (0x0 << MIPI2DMA_CTRL33_M1_SADDR_ID1_H_SHIFT);
  400. vi_pre_write(dev, MIPI2DMA_CTRL(33), val);
  401. val = vi_pre_read(dev, MIPI2DMA_CTRL(34));
  402. val |= (0xF4000000 << MIPI2DMA_CTRL34_M1_SADDR_ID1_L_SHIFT);
  403. vi_pre_write(dev, MIPI2DMA_CTRL(34), val);
  404. val = vi_pre_read(dev, MIPI2DMA_CTRL(35));
  405. val |= (0x0 << MIPI2DMA_CTRL35_M1_SADDR_ID2_H_SHIFT);
  406. vi_pre_write(dev, MIPI2DMA_CTRL(35), val);
  407. val = vi_pre_read(dev, MIPI2DMA_CTRL(36));
  408. val |= (0xF5000000 << MIPI2DMA_CTRL36_M1_SADDR_ID2_L_SHIFT);
  409. vi_pre_write(dev, MIPI2DMA_CTRL(36), val);
  410. //M2 ADDR
  411. val = vi_pre_read(dev, MIPI2DMA_CTRL(37));
  412. val |= (0x0 << MIPI2DMA_CTRL37_M2_SADDR_ID0_H_SHIFT);
  413. vi_pre_write(dev, MIPI2DMA_CTRL(37), val);
  414. val = vi_pre_read(dev, MIPI2DMA_CTRL(38));
  415. val |= (0xF6000000 << MIPI2DMA_CTRL38_M2_SADDR_ID0_L_SHIFT);
  416. vi_pre_write(dev, MIPI2DMA_CTRL(38), val);
  417. val = vi_pre_read(dev, MIPI2DMA_CTRL(39));
  418. val |= (0x0 << MIPI2DMA_CTRL39_M2_SADDR_ID1_H_SHIFT);
  419. vi_pre_write(dev, MIPI2DMA_CTRL(39), val);
  420. val = vi_pre_read(dev, MIPI2DMA_CTRL(40));
  421. val |= (0xF7000000 << MIPI2DMA_CTRL40_M2_SADDR_ID1_L_SHIFT);
  422. vi_pre_write(dev, MIPI2DMA_CTRL(40), val);
  423. val = vi_pre_read(dev, MIPI2DMA_CTRL(41));
  424. val |= (0x0 << MIPI2DMA_CTRL41_M2_SADDR_ID2_H_SHIFT);
  425. vi_pre_write(dev, MIPI2DMA_CTRL(41), val);
  426. val = vi_pre_read(dev, MIPI2DMA_CTRL(42));
  427. val |= (0xF8000000 << MIPI2DMA_CTRL42_M2_SADDR_ID2_L_SHIFT);
  428. vi_pre_write(dev, MIPI2DMA_CTRL(42), val);
  429. //M3 ADDR
  430. val = vi_pre_read(dev, MIPI2DMA_CTRL(45));
  431. val |= (0x0 << MIPI2DMA_CTRL45_M3_SADDR_ID0_H_SHIFT);
  432. vi_pre_write(dev, MIPI2DMA_CTRL(45), val);
  433. val = vi_pre_read(dev, MIPI2DMA_CTRL(46));
  434. val |= (0xF9000000 << MIPI2DMA_CTRL46_M3_SADDR_ID0_L_SHIFT);
  435. vi_pre_write(dev, MIPI2DMA_CTRL(46), val);
  436. val = vi_pre_read(dev, MIPI2DMA_CTRL(47));
  437. val |= (0x0 << MIPI2DMA_CTRL47_M3_SADDR_ID1_H_SHIFT);
  438. vi_pre_write(dev, MIPI2DMA_CTRL(47), val);
  439. val = vi_pre_read(dev, MIPI2DMA_CTRL(48));
  440. val |= (0xFa000000 << MIPI2DMA_CTRL48_M3_SADDR_ID1_L_SHIFT);
  441. vi_pre_write(dev, MIPI2DMA_CTRL(48), val);
  442. val = vi_pre_read(dev, MIPI2DMA_CTRL(49));
  443. val |= (0x0 << MIPI2DMA_CTRL49_M3_SADDR_ID2_H_SHIFT);
  444. vi_pre_write(dev, MIPI2DMA_CTRL(49), val);
  445. val = vi_pre_read(dev, MIPI2DMA_CTRL(50));
  446. val |= (0xFb000000 << MIPI2DMA_CTRL50_M3_SADDR_ID2_L_SHIFT);
  447. vi_pre_write(dev, MIPI2DMA_CTRL(50), val);
  448. val = vi_pre_read(dev, MIPI2DMA_CTRL(51));
  449. val |= MIPI2DMA_CTRL51_CROSS_4K_EN;
  450. vi_pre_write(dev, MIPI2DMA_CTRL(51), val);
  451. // feedback config to default
  452. val = 0;
  453. vi_pre_write(dev, MIPI2DMA_CTRL(11), val);
  454. val = 0;
  455. vi_pre_write(dev, MIPI2DMA_CTRL(23), val);
  456. val = 0;
  457. vi_pre_write(dev, MIPI2DMA_CTRL(24), val);
  458. // int status clean & mask
  459. //val = vi_pre_read(dev, MIPI2DMA_CTRL(44));
  460. //enable all interrupt
  461. val = 0; //open all interrupt
  462. vi_pre_write(dev, MIPI2DMA_CTRL(44), val);
  463. val = vi_pre_read(dev, MIPI2DMA_CTRL(10));
  464. val |= MIPI2DMA_START;
  465. vi_pre_write(dev, MIPI2DMA_CTRL(10), val);
  466. #endif
  467. return ret;
  468. }
  469. #endif
  470. static u16 read_interrupt_status(struct vi_pre_dev *dev)
  471. {
  472. return vi_pre_read(dev, MIPI2DMA_CTRL(44)) & 0x1ff;
  473. }
  474. static u32 mframe_frame_done_flag(struct vi_pre_dev *dev)
  475. {
  476. return vi_pre_read(dev, MIPI2DMA_CTRL(43)) & 0xfff;
  477. }
  478. static void mframe_frame_done_flag_clear(struct vi_pre_dev *dev, u32 mask)
  479. {
  480. u32 reg_val = vi_pre_read(dev, MIPI2DMA_CTRL(43));
  481. reg_val |= mask;
  482. vi_pre_write(dev, MIPI2DMA_CTRL(43), mask);
  483. }
  484. static int get_frame_num(struct vi_pre_dev *dev)
  485. {
  486. u32 reg_val = vi_pre_read(dev, MIPI2DMA_CTRL(0));
  487. reg_val &= (3 << 2);
  488. return (reg_val >> 2) + 1;
  489. }
  490. static void dma_period_clear(struct vi_pre_dev *dev, int ch)
  491. {
  492. u32 reg_val = vi_pre_read(dev, MIPI2DMA_CTRL(11));
  493. if (reg_val & (1 << ch)) {
  494. reg_val &= ~(1 << ch);
  495. } else {
  496. reg_val |= (1 << ch);
  497. }
  498. vi_pre_write(dev, MIPI2DMA_CTRL(11), reg_val);
  499. }
  500. #if 0
  501. void vi_pre_interrupt_handler(struct vi_pre_dev *dev)
  502. {
  503. u32 status = read_interrupt_status(dev);
  504. u32 f_done_sta = 0;
  505. int i = 0;
  506. if (status & VIPRE_FRAME_DONE) {
  507. f_done_sta = mframe_frame_done_flag(dev);
  508. for(i = 11; i >= 0; i--) {
  509. if (f_done_sta & (1 << i)) {
  510. if (i >= 8) {
  511. dev->cnt[0]++;
  512. } else if (i >= 4) {
  513. dev->cnt[1]++;
  514. } else {
  515. dev->cnt[2]++;
  516. }
  517. }
  518. }
  519. mframe_frame_done_flag_clear(dev, f_done_sta);
  520. /*TODO send event*/
  521. //printk("frame done %x\n", f_done_sta);
  522. } else if (status & VIPRE_LINE_DONE) {
  523. //u32 nline_done_sta =;
  524. //pdriver_dev->cnt++;
  525. //printk("line done %x\n", f_done_sta);
  526. }
  527. //u32 line_cnt = pdriver_dev->cnt * get_nline_int_period(pdriver_dev);
  528. if (dev->is_mframe_mode) {
  529. for(i = 0; i < 3; i++) {
  530. if(dev->cnt[i] < get_frame_num(dev)) {
  531. continue;
  532. }
  533. dev->cnt[i] = 0;
  534. dma_period_clear(dev, i);
  535. }
  536. }
  537. }
  538. #endif
  539. int vi_pre_set_resolution(struct vi_pre_dev *dev, void *arg)
  540. {
  541. u32 val = 0;
  542. vipre_resolution_cfg_t cfg;
  543. check_retval(copy_from_user(&cfg, arg, sizeof(cfg)));
  544. val = (cfg.h << 16) | cfg.v;
  545. if(cfg.glue_idx == 0) {
  546. vi_pre_write(dev, G0_RESCFG, val);
  547. vi_pre_write(dev, G0_RESCFG2, val);
  548. vi_pre_write(dev, G0_RESCFG3, val);
  549. } else if(cfg.glue_idx == 1) {
  550. vi_pre_write(dev, G1_RESCFG, val);
  551. vi_pre_write(dev, G1_RESCFG2, val);
  552. vi_pre_write(dev, G1_RESCFG3, val);
  553. } else if(cfg.glue_idx == 2) {
  554. vi_pre_write(dev, G2_RESCFG, val);
  555. vi_pre_write(dev, G2_RESCFG2, val);
  556. vi_pre_write(dev, G2_RESCFG3, val);
  557. } else {
  558. return -1;
  559. }
  560. return 0;
  561. }
  562. typedef enum {
  563. DDR,
  564. ISP1,
  565. ISP2,
  566. }img_processor_e;
  567. typedef struct {
  568. int csi_idx;
  569. int glue_idx;
  570. img_processor_e processor;
  571. } vipre_pipline_t;
  572. static void glue0_select_csi(struct vi_pre_dev *dev, int csi_idx)
  573. {
  574. unsigned int val = 0;
  575. val = vi_pre_read(dev, G1_MUX3_2);
  576. val &= ~(3 << 4);
  577. val |= (csi_idx << 4);
  578. vi_pre_write(dev, G1_MUX3_2, val);
  579. }
  580. static void glue1_select_csi(struct vi_pre_dev *dev, int csi_idx)
  581. {
  582. unsigned int val = 0;
  583. val = vi_pre_read(dev, G1_MUX3_2);
  584. val &= ~(3 << 2);
  585. val |= (csi_idx << 2);
  586. vi_pre_write(dev, G1_MUX3_2, val);
  587. }
  588. static void glue2_select_csi(struct vi_pre_dev *dev, int csi_idx)
  589. {
  590. unsigned int val = 0;
  591. val = vi_pre_read(dev, G1_MUX3_2);
  592. val &= ~3;
  593. val |= csi_idx;
  594. vi_pre_write(dev, G1_MUX3_2, val);
  595. }
  596. static void isp2_select_glue(struct vi_pre_dev *dev, int glue_idx)
  597. {
  598. unsigned int val = 0;
  599. val = vi_pre_read(dev, G1_MUX3_2);
  600. val &= ~(1 << 7);
  601. if (glue_idx == 1) {
  602. val |= (1 << 7);
  603. }
  604. vi_pre_write(dev, G1_MUX3_2, val);
  605. }
  606. static void isp1_select_glue(struct vi_pre_dev *dev, int glue_idx)
  607. {
  608. unsigned int val = 0;
  609. val = vi_pre_read(dev, G1_MUX3_2);
  610. val &= ~(1 << 6);
  611. if (glue_idx == 2) {
  612. val |= (1 << 6);
  613. }
  614. vi_pre_write(dev, G1_MUX3_2, val);
  615. }
  616. static void ipi_enable(struct vi_pre_dev *dev, int ipi_idx)
  617. {
  618. unsigned int val = 0;
  619. val = vi_pre_read(dev, G1_MUX3_2);
  620. val |= (1 << (10 - ipi_idx));
  621. vi_pre_write(dev, G1_MUX3_2, val);
  622. }
  623. static void ipi_disable(struct vi_pre_dev *dev, int ipi_idx)
  624. {
  625. unsigned int val = 0;
  626. val = vi_pre_read(dev, G1_MUX3_2);
  627. val &= ~(1 << (10 - ipi_idx));
  628. vi_pre_write(dev, G1_MUX3_2, val);
  629. }
  630. static int vi_pre_reset(struct vi_pre_dev *dev, void *args)
  631. {
  632. uint32_t ipi_idx = 0;
  633. unsigned int val = 0;
  634. check_retval(copy_from_user(&ipi_idx, args, sizeof(ipi_idx)));
  635. val = vi_pre_read(dev, MIPI2DMA_CTRL9);
  636. val |= 1 << ipi_idx;
  637. vi_pre_write(dev, MIPI2DMA_CTRL9, val);
  638. while(vi_pre_read(dev, MIPI2DMA_CTRL9)) {
  639. ;
  640. }
  641. val = (0x3f << 16);
  642. vi_pre_write(dev, MIPI2DMA_CTRL44, val);
  643. vi_pre_write(dev, MIPI2DMA_CTRL23, 0);
  644. vi_pre_write(dev, MIPI2DMA_CTRL24, 0);
  645. vi_pre_write(dev, MIPI2DMA_CTRL11, 0);
  646. vi_pre_write(dev, MIPI2DMA_CTRL12, 0);
  647. vi_pre_write(dev, MIPI2DMA_CTRL13, 0);
  648. vi_pre_write(dev, MIPI2DMA_CTRL14, 0);
  649. val = vi_pre_read(dev, MIPI2DMA_CTRL43);
  650. vi_pre_write(dev,MIPI2DMA_CTRL43,val);
  651. return 0;
  652. }
  653. static int vi_pre_press_interror(struct vi_pre_dev *dev, void *args)
  654. {
  655. uint32_t stat = (uint32_t)args;
  656. int err_flag = 0;
  657. if (stat & VIPRE_BUS_ERR) {
  658. pr_err("%s, %d, vipre bus error!\n", __func__, __LINE__);
  659. err_flag = 1;
  660. }
  661. if (stat & VIPRE_FIFO_OVER) {
  662. pr_err("%s, %d, vipre fifo overflow!\n", __func__, __LINE__);
  663. err_flag = 1;
  664. }
  665. if (stat & VIPRE_NMOVERFLOW) {
  666. pr_err("%s, %d, vipre nmoverflow!\n", __func__, __LINE__);
  667. err_flag = 1;
  668. }
  669. if(err_flag) {
  670. return vi_pre_reset(dev, NULL);
  671. }
  672. return 0;
  673. }
  674. int vi_pre_set_pipline(struct vi_pre_dev *dev, void *arg)
  675. {
  676. vipre_pipline_t cfg;
  677. check_retval(copy_from_user(&cfg, arg, sizeof(cfg)));
  678. if (cfg.glue_idx == 0) {
  679. glue0_select_csi(dev, cfg.csi_idx);
  680. } else if (cfg.glue_idx == 1) {
  681. glue1_select_csi(dev, cfg.csi_idx);
  682. if (cfg.processor == DDR) {
  683. return -1;
  684. }
  685. } else if (cfg.glue_idx == 2) {
  686. glue2_select_csi(dev, cfg.csi_idx);
  687. if (cfg.processor == DDR) {
  688. return -1;
  689. }
  690. }
  691. if (cfg.processor == ISP1) {
  692. isp1_select_glue(dev, cfg.glue_idx);
  693. } else if (cfg.processor == ISP2) {
  694. isp2_select_glue(dev, cfg.glue_idx);
  695. }
  696. return 0;
  697. }
  698. int vi_pre_set_ipi_mode(struct vi_pre_dev *dev, void *arg)
  699. {
  700. ipi_mode_cfg_t ipi_mode;
  701. check_retval(copy_from_user(&ipi_mode, arg, sizeof(ipi_mode)));
  702. switch(ipi_mode.glue_idx) {
  703. case 0:
  704. vi_pre_write(dev, G0_MODSEL, ipi_mode.mode);
  705. break;
  706. case 1:
  707. vi_pre_write(dev, G1_MODSEL, ipi_mode.mode);
  708. break;
  709. case 2:
  710. vi_pre_write(dev, G2_MODSEL, ipi_mode.mode);
  711. break;
  712. default:
  713. return -1;
  714. }
  715. return 0;
  716. }
  717. int vi_pre_set_ipi_idnum(struct vi_pre_dev *dev, void *arg)
  718. {
  719. ipi_idnum_cfg_t cfg;
  720. uint32_t val = 0;
  721. check_retval(copy_from_user(&cfg, arg, sizeof(cfg)));
  722. val = cfg.id_1 | (cfg.id_2 << 2) | (cfg.id_3 << 4)
  723. | (cfg.id_first_sync << 6) | (cfg.id_second_sync << 8) | (cfg.id_third_sync << 10);
  724. switch(cfg.glue_idx) {
  725. case 0:
  726. vi_pre_write(dev, G0_IDNUM, val);
  727. break;
  728. case 1:
  729. vi_pre_write(dev, G1_IDNUM, val);
  730. break;
  731. case 2:
  732. vi_pre_write(dev, G2_IDNUM, val);
  733. break;
  734. default:
  735. return -1;
  736. }
  737. return 0;
  738. }
  739. int vi_pre_enable_ipi(struct vi_pre_dev *dev, void *arg)
  740. {
  741. int ipi_idx;
  742. check_retval(copy_from_user(&ipi_idx, arg, sizeof(ipi_idx)));
  743. ipi_enable(dev, ipi_idx);
  744. return 0;
  745. }
  746. int vi_pre_disable_ipi(struct vi_pre_dev *dev, void *arg)
  747. {
  748. int ipi_idx;
  749. check_retval(copy_from_user(&ipi_idx, arg, sizeof(ipi_idx)));
  750. ipi_disable(dev, ipi_idx);
  751. return 0;
  752. }
  753. extern int vi_pre_dma_config(struct vi_pre_dev *pdriver_dev, void *arg);
  754. extern int vi_pre_dma_start(struct vi_pre_dev *pdriver_dev);
  755. extern int vi_pre_dma_stop(struct vi_pre_dev *pdriver_dev);
  756. extern int vi_pre_dma_mframe_set_buf(struct vi_pre_dev *pdriver_dev, void *arg);
  757. extern int vi_pre_dma_get_mframe_done_id(struct vi_pre_dev *pdriver_dev, void *arg);
  758. extern int vi_pre_dma_mframe_update_buf(struct vi_pre_dev *pdriver_dev, void *arg);
  759. static DECLARE_WAIT_QUEUE_HEAD(vipre_waitq);
  760. static irqreturn_t vi_pre_irq(int irq, void *dev_id)
  761. {
  762. extern void vi_pre_dma_interrupt_handler(struct vi_pre_dev *pdriver_dev);
  763. struct vi_pre_dev *pdriver_dev = dev_id;
  764. vi_pre_dma_interrupt_handler(pdriver_dev);
  765. wake_up_interruptible(&vipre_waitq);
  766. return IRQ_HANDLED;
  767. }
  768. unsigned vi_pre_poll(struct file *file, poll_table *wait)
  769. {
  770. extern int *vi_pre_event(void);
  771. int *event = 0;
  772. unsigned int mask = 0;
  773. event = vi_pre_event();
  774. poll_wait(file, &vipre_waitq, wait);
  775. if (*event) {
  776. mask |= POLLIN | POLLRDNORM;
  777. *event = 0;
  778. }
  779. return mask;
  780. }
  781. static int vi_pre_request_irq(struct vi_pre_dev *pdriver_dev, void *arg)
  782. {
  783. int ret = 0;
  784. struct device *dev = &pdriver_dev->pdev->dev;
  785. ret = devm_request_irq(dev, pdriver_dev->irq,
  786. vi_pre_irq, IRQF_SHARED,
  787. dev_name(dev), pdriver_dev);
  788. if (ret) {
  789. dev_err(dev, "irq vipre failed\n");
  790. }
  791. return ret;
  792. }
  793. static int vi_pre_free_irq(struct vi_pre_dev *pdriver_dev, void *arg)
  794. {
  795. int ret = free_irq(pdriver_dev->irq, pdriver_dev);
  796. return ret;
  797. }
  798. unsigned int vi_pre_priv_ioctl(struct vi_pre_dev *dev, unsigned int cmd, void *args)
  799. {
  800. int ret = -1;
  801. if (!dev) {
  802. pr_err("%s invalid para\n", __func__);
  803. return ret;
  804. }
  805. switch (cmd) {
  806. case VI_PRE_IOCTL_RESET:
  807. ret = vi_pre_reset(dev, (void *)args);
  808. break;
  809. case VI_PRE_IOCTL_WRITE_REG:
  810. ret = vi_pre_write_reg(dev, (void *)args);
  811. break;
  812. case VI_PRE_IOCTL_READ_REG:
  813. ret = vi_pre_read_reg(dev, (void *)args);
  814. break;
  815. case VI_PRE_IOCTL_SET_IPI_RESOLUTION:
  816. ret = vi_pre_set_resolution(dev, (void*)args);
  817. break;
  818. case VI_PRE_IOCTL_SET_PIPLINE:
  819. ret = vi_pre_set_pipline(dev, (void*)args);
  820. break;
  821. case VI_PRE_IOCTL_SET_IPI_MODE:
  822. ret = vi_pre_set_ipi_mode(dev, (void*)args);
  823. break;
  824. case VI_PRE_IOCTL_SET_IPI_IDNUM:
  825. ret = vi_pre_set_ipi_idnum(dev, (void*)args);
  826. break;
  827. case VI_PRE_IOCTL_ENABLE_IPI:
  828. ret = vi_pre_enable_ipi(dev, (void *)args);
  829. break;
  830. case VI_PRE_IOCTL_DISABLE_IPI:
  831. ret = vi_pre_disable_ipi(dev, (void *)args);
  832. break;
  833. case VI_PRE_IOCTL_SET_MIPI2DMA_M_FRMAE:
  834. ret = vi_pre_dma_config(dev, (void*)args);
  835. break;
  836. case VI_PRE_IOCTL_SET_MIPI2DMA_START:
  837. ret = vi_pre_dma_start(dev);
  838. break;
  839. case VI_PRE_IOCTL_SET_MIPI2DMA_STOP:
  840. ret = vi_pre_dma_stop(dev);
  841. break;
  842. case VI_PRE_IOCTL_SET_MIPI2DMA_N_LINE:
  843. //ret = vi_pre_set_mipi2dma_n_line(dev, args);
  844. ret = vi_pre_dma_config(dev, (void*)args);
  845. break;
  846. case VI_PRE_IOCTL_SET_HDRPRO_MODE:
  847. ret = vi_pre_set_hdrpro_mode(dev, args);
  848. break;
  849. case VI_PRE_IOCTL_HDRPRO_ENABLE:
  850. ret = vi_pre_hdrpro_en(dev, 1);
  851. break;
  852. case VI_PRE_IOCTL_HDRPRO_DISABLE:
  853. ret = vi_pre_hdrpro_en(dev, 0);
  854. break;
  855. case VI_PRE_IOCTL_SET_HDRPRO_RESOLUTION:
  856. ret = vi_pre_set_hdrpro_resolution(dev, args);
  857. break;
  858. case VI_PRE_IOCTL_SET_HDRPRO_BLACK_PARA:
  859. ret = vi_pre_set_hdrpro_black_para(dev, args);
  860. break;
  861. case VI_PRE_IOCTL_SET_HDRPRO_COLOR_PARA:
  862. ret = vi_pre_set_hdrpro_color_para(dev, args);
  863. break;
  864. case VI_PRE_IOCTL_SET_HDRPRO_MERGE_PARA:
  865. ret = vi_pre_set_hdrpro_merge_para(dev, args);
  866. break;
  867. case VI_PRE_IOCTL_PRESS_INTERROR:
  868. ret = vi_pre_press_interror(dev, args);
  869. break;
  870. case VI_PRE_IOCTL_SET_MFRAME_BUF:
  871. ret = vi_pre_dma_mframe_set_buf(dev, args);
  872. break;
  873. case VI_PRE_IOCTL_GET_MFRAME_DONE_ID:
  874. ret = vi_pre_dma_get_mframe_done_id(dev, args);
  875. break;
  876. case VI_PRE_IOCTL_MFRAME_UPDATE_BUF:
  877. ret = vi_pre_dma_mframe_update_buf(dev, args);
  878. break;
  879. case VI_PRE_IOCTL_REQUEST_IRQ:
  880. ret = vi_pre_request_irq(dev, args);
  881. break;
  882. case VI_PRE_IOCTL_FREE_IRQ:
  883. ret = vi_pre_free_irq(dev, args);
  884. break;
  885. default:
  886. pr_err("unsupported command %d\n", cmd);
  887. break;
  888. }
  889. return ret;
  890. }