vi_pre_dma.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781
  1. #include <linux/debugfs.h>
  2. #include <linux/delay.h>
  3. #include <linux/gpio.h>
  4. #include <linux/io.h>
  5. #include <linux/kernel.h>
  6. #include <linux/module.h>
  7. #include <linux/of.h>
  8. #include <linux/of_address.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/spinlock.h>
  11. //#include <sys/types.h>
  12. #include "vi_pre.h"
  13. #include "vi_pre_ioctl.h"
  14. #define check_retval(x)\
  15. do {\
  16. if ((x))\
  17. return -EIO;\
  18. } while (0)
  19. #define img_buf 0xf0000000
  20. typedef struct {
  21. u32 dma_ctl0;
  22. u32 dma_ctl1;
  23. u32 dma_ctl2;
  24. u32 dma_ctl3;
  25. u32 dma_ctl4;
  26. u32 dma_ctl5;
  27. u32 dma_ctl6;
  28. u32 dma_ctl7;
  29. u32 dma_ctl8;
  30. u32 dma_ctl9;
  31. u32 dma_ctl10;
  32. u32 dma_ctl11;
  33. u32 dma_ctl12;
  34. u32 dma_ctl13;
  35. u32 dma_ctl14;
  36. u32 dma_ctl15;
  37. u32 dma_ctl16;
  38. u32 dma_ctl17;
  39. u32 dma_ctl18;
  40. u32 dma_ctl19;
  41. u32 dma_ctl20;
  42. u32 dma_ctl21;
  43. u32 dma_ctl22;
  44. u32 dma_ctl23;
  45. u32 dma_ctl24;
  46. u32 dma_ctl25;
  47. u32 dma_ctl26;
  48. u32 dma_ctl27;
  49. u32 dma_ctl28;
  50. u32 dma_ctl29;
  51. u32 dma_ctl30;
  52. u32 dma_ctl31;
  53. u32 dma_ctl32;
  54. u32 dma_ctl33;
  55. u32 dma_ctl34;
  56. u32 dma_ctl35;
  57. u32 dma_ctl36;
  58. u32 dma_ctl37;
  59. u32 dma_ctl38;
  60. u32 dma_ctl39;
  61. u32 dma_ctl40;
  62. u32 dma_ctl41;
  63. u32 dma_ctl42;
  64. u32 dma_ctl43;
  65. u32 dma_ctl44;
  66. u32 dma_ctl45;
  67. u32 dma_ctl46;
  68. u32 dma_ctl47;
  69. u32 dma_ctl48;
  70. u32 dma_ctl49;
  71. u32 dma_ctl50;
  72. u32 dma_ctl51;
  73. } vi_dma_reg_t;
  74. static vi_dma_reg_t dma_reg = {
  75. .dma_ctl0 = 0x198,
  76. .dma_ctl1 = 0x19c,
  77. .dma_ctl2 = 0x1a0,
  78. .dma_ctl3 = 0x1a4,
  79. .dma_ctl4 = 0x1a8,
  80. .dma_ctl5 = 0x1ac,
  81. .dma_ctl6 = 0x1b0,
  82. .dma_ctl7 = 0x1b4,
  83. .dma_ctl8 = 0x1b8,
  84. .dma_ctl9 = 0x1bc,
  85. .dma_ctl10 = 0x1c0,
  86. .dma_ctl11 = 0x1c4,
  87. .dma_ctl12 = 0x1c8,
  88. .dma_ctl13 = 0x1cc,
  89. .dma_ctl14 = 0x1d0,
  90. .dma_ctl15 = 0x1d4,
  91. .dma_ctl16 = 0x1d8,
  92. .dma_ctl17 = 0x1dc,
  93. .dma_ctl18 = 0x1e0,
  94. .dma_ctl19 = 0x1e4,
  95. .dma_ctl20 = 0x1e8,
  96. .dma_ctl21 = 0x1ec,
  97. .dma_ctl22 = 0x1f0,
  98. .dma_ctl23 = 0x1f4,
  99. .dma_ctl24 = 0x1f8,
  100. .dma_ctl25 = 0x1fc,
  101. .dma_ctl26 = 0x200,
  102. .dma_ctl27 = 0x204,
  103. .dma_ctl28 = 0x208,
  104. .dma_ctl29 = 0x20c,
  105. .dma_ctl30 = 0x210,
  106. .dma_ctl31 = 0x214,
  107. .dma_ctl32 = 0x218,
  108. .dma_ctl33 = 0x21c,
  109. .dma_ctl34 = 0x220,
  110. .dma_ctl35 = 0x224,
  111. .dma_ctl36 = 0x228,
  112. .dma_ctl37 = 0x22c,
  113. .dma_ctl38 = 0x230,
  114. .dma_ctl39 = 0x234,
  115. .dma_ctl40 = 0x238,
  116. .dma_ctl41 = 0x23c,
  117. .dma_ctl42 = 0x240,
  118. .dma_ctl43 = 0x244,
  119. .dma_ctl44 = 0x248,
  120. .dma_ctl45 = 0x24c,
  121. .dma_ctl46 = 0x250,
  122. .dma_ctl47 = 0x254,
  123. .dma_ctl48 = 0x258,
  124. .dma_ctl49 = 0x25c,
  125. .dma_ctl50 = 0x260,
  126. .dma_ctl51 = 0x264,
  127. };
  128. static inline void vi_pre_dma_write(struct vi_pre_dev *dev,
  129. u32 address, u32 data)
  130. {
  131. writel(data, dev->reg_base + address);
  132. }
  133. static inline u32 vi_pre_dma_read(struct vi_pre_dev *dev,
  134. u32 address)
  135. {
  136. return readl(dev->reg_base + address);
  137. }
  138. static void set_dma_mode(struct vi_pre_dev *dev, vi_pre_dma_mode_t mode)
  139. {
  140. u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl0);
  141. if(mode == VI_PRE_M_FRAME) {
  142. reg_val &= ~1;
  143. } else {
  144. reg_val |= 1;
  145. }
  146. vi_pre_dma_write(dev, dma_reg.dma_ctl0, reg_val);
  147. }
  148. static void set_frame_num(struct vi_pre_dev *dev, u32 num)
  149. {
  150. u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl0);
  151. num -= 1;
  152. reg_val &= ~(3 << 1);
  153. reg_val |= (num << 1);
  154. vi_pre_dma_write(dev, dma_reg.dma_ctl0, reg_val);
  155. }
  156. static int get_frame_num(struct vi_pre_dev *dev)
  157. {
  158. u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl0);
  159. reg_val &= (3 << 2);
  160. return (reg_val >> 2) + 1;
  161. }
  162. /*big align ro little align*/
  163. static void set_bit_mode(struct vi_pre_dev *dev, bool is_big)
  164. {
  165. u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl0);
  166. if (is_big) {
  167. reg_val |= (1 << 3);
  168. } else {
  169. reg_val &= ~(1 << 3);
  170. }
  171. vi_pre_dma_write(dev, dma_reg.dma_ctl0, reg_val);
  172. }
  173. static void set_dma_data_width(struct vi_pre_dev *dev, vi_pre_data_width_t width)
  174. {
  175. u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl0);
  176. reg_val &= ~(0x7 <<4);
  177. reg_val |= (width << 4);
  178. vi_pre_dma_write(dev, dma_reg.dma_ctl0, reg_val);
  179. }
  180. /*length is 4, 8, 16*/
  181. static void set_dma_burst_length(struct vi_pre_dev *dev, u8 len)
  182. {
  183. u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl1);
  184. len -=1;
  185. reg_val &= ~(0xff << 16);
  186. reg_val |= (len << 16);
  187. reg_val |= 0x3ff;
  188. vi_pre_dma_write(dev, dma_reg.dma_ctl1, reg_val);
  189. }
  190. static u32 read_dma_burst_length(struct vi_pre_dev *dev)
  191. {
  192. u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl1);
  193. return ((reg_val >> 16) & 0xff) + 1;
  194. }
  195. static void set_dma_resolution(struct vi_pre_dev *dev, u16 h, u16 v)
  196. {
  197. u32 reg_val = 0;
  198. h &= 0x1fff;
  199. v &= 0x1fff;
  200. reg_val = h | (v << 16);
  201. vi_pre_dma_write(dev, dma_reg.dma_ctl3, reg_val);
  202. }
  203. static int set_nline_oneline_size(struct vi_pre_dev *dev, vi_pre_dma_cfg_t *cfg)
  204. {
  205. u32 reg_val = 0;
  206. u32 stream_min = 0;
  207. u32 cnt_128 = 0;
  208. u32 read_num = 0;
  209. u32 burstrem = 0;
  210. stream_min = cfg->resolution_h;
  211. if (cfg->width == VI_PRE_RAW_12BIT ||
  212. cfg->width == VI_PRE_RAW_10BIT_16ALIGN) {
  213. stream_min = cfg->resolution_h * 2;
  214. }
  215. if (stream_min > cfg->line_size) {
  216. return -1;
  217. }
  218. if (stream_min % 16) {
  219. stream_min += 16 - (stream_min % 16);
  220. }
  221. cnt_128 = stream_min / 16;
  222. read_num = cnt_128 / read_dma_burst_length(dev);
  223. burstrem = cnt_128 % read_dma_burst_length(dev);
  224. if (cnt_128 % read_dma_burst_length(dev)) {
  225. read_num +=1;
  226. }
  227. if (burstrem == 0) {
  228. burstrem = read_dma_burst_length(dev);
  229. }
  230. reg_val = cnt_128 | (read_num << 16) | (burstrem << 27);
  231. vi_pre_dma_write(dev, dma_reg.dma_ctl4, reg_val);
  232. vi_pre_dma_write(dev, dma_reg.dma_ctl6, cfg->line_size);
  233. return 0;
  234. }
  235. static void set_nline_period(struct vi_pre_dev *dev, u32 num)
  236. {
  237. u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl5);
  238. reg_val &= ~0xfff;
  239. reg_val |= num;
  240. printk("vipre nline period num %d, reg_val 0x%x\n", num, reg_val);
  241. vi_pre_dma_write(dev, dma_reg.dma_ctl5, reg_val);
  242. }
  243. static void set_nline_int_period(struct vi_pre_dev *dev, u32 num)
  244. {
  245. u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl5);
  246. reg_val &= ~(0x7ff << 16);
  247. reg_val |= (num << 16);
  248. printk("vipre nline int period num %d, reg_val 0x%x\n", num, reg_val);
  249. vi_pre_dma_write(dev, dma_reg.dma_ctl5, reg_val);
  250. }
  251. static u16 get_nline_period(struct vi_pre_dev *dev)
  252. {
  253. u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl5);
  254. return reg_val & 0xfff;
  255. }
  256. static u16 get_nline_int_period(struct vi_pre_dev *dev)
  257. {
  258. u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl5);
  259. return (reg_val >> 16) & 0xfff;
  260. }
  261. static int set_mfram_oneline_range(struct vi_pre_dev *dev, int frame_id, u32 size)
  262. {
  263. u32 aligned = 0;
  264. u32 reg_val = 0;
  265. u32 reg = 0;
  266. aligned = read_dma_burst_length(dev) * 16;
  267. /*set buf addr*/
  268. if(size % aligned) {
  269. printk("<0>""###########error !!!!!!!!! %s, %d\n", __func__, __LINE__);
  270. return -1;
  271. }
  272. reg = frame_id / 2 * 4 + dma_reg.dma_ctl7;
  273. reg_val = vi_pre_dma_read(dev, reg);
  274. if (frame_id % 2 == 0) {
  275. reg_val &= ~(0xffff << 16);
  276. reg_val |= (size << 16);
  277. } else {
  278. reg_val &= ~0xffff;
  279. reg_val |= size;
  280. }
  281. vi_pre_dma_write(dev, reg, reg_val);
  282. return 0;
  283. }
  284. static int set_mframe_oneline_group(struct vi_pre_dev *dev, vi_pre_dma_cfg_t *cfg)
  285. {
  286. u32 reg_val = 0;
  287. u32 stream_min = 0;
  288. u32 cnt_128 = 0;
  289. u32 read_num = 0;
  290. u32 burstrem = 0;
  291. stream_min = cfg->resolution_h;
  292. if (cfg->width == VI_PRE_RAW_12BIT ||
  293. cfg->width == VI_PRE_RAW_10BIT_16ALIGN) {
  294. stream_min = cfg->resolution_h * 2;
  295. }
  296. if (stream_min > cfg->line_size) {
  297. return -1;
  298. }
  299. if (stream_min % 16) {
  300. stream_min += 16 - (stream_min % 16);
  301. }
  302. cnt_128 = stream_min / 16;
  303. read_num = cnt_128 / read_dma_burst_length(dev);
  304. burstrem = cnt_128 % read_dma_burst_length(dev);
  305. if (cnt_128 % read_dma_burst_length(dev)) {
  306. read_num +=1;
  307. }
  308. if (burstrem == 0) {
  309. burstrem = read_dma_burst_length(dev);
  310. }
  311. reg_val = cnt_128 | (read_num << 16) | (burstrem << 27);
  312. vi_pre_dma_write(dev, dma_reg.dma_ctl4, reg_val);
  313. return 0;
  314. }
  315. static void dma_reset(struct vi_pre_dev *dev)
  316. {
  317. vi_pre_dma_write(dev, dma_reg.dma_ctl9, 1);
  318. while(vi_pre_dma_read(dev, dma_reg.dma_ctl9) == 1);
  319. }
  320. static void dma_enable(struct vi_pre_dev *dev, int en)
  321. {
  322. if(en) {
  323. vi_pre_dma_write(dev, dma_reg.dma_ctl10, 1);
  324. pr_info("%s, %d, dma start\n", __func__, __LINE__);
  325. } else {
  326. vi_pre_dma_write(dev, dma_reg.dma_ctl10, 0);
  327. pr_info("%s, %d, dma stop\n", __func__, __LINE__);
  328. }
  329. }
  330. static void dma_period_clear(struct vi_pre_dev *dev, int ch)
  331. {
  332. u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl11);
  333. if (reg_val & (1 << ch)) {
  334. reg_val &= ~(1 << ch);
  335. } else {
  336. reg_val |= (1 << ch);
  337. }
  338. vi_pre_dma_write(dev, dma_reg.dma_ctl11, reg_val);
  339. }
  340. static void nline_mode_set_line_position(struct vi_pre_dev *dev, int ch, int p)
  341. {
  342. u32 reg = dma_reg.dma_ctl12 + ch * 4;
  343. vi_pre_dma_write(dev, reg, p);
  344. }
  345. static void nline_mode_set_start_addr(struct vi_pre_dev *dev, int ch, unsigned long addr)
  346. {
  347. u32 reg = dma_reg.dma_ctl15 + ch * 8;
  348. u8 h = addr >> 32;
  349. u32 l = addr & 0xffffffff;
  350. vi_pre_dma_write(dev, reg, h);
  351. vi_pre_dma_write(dev, reg + 4, l);
  352. }
  353. static u16 nline_mode_period_cnt(struct vi_pre_dev *dev, int ch)
  354. {
  355. u32 reg = dma_reg.dma_ctl21 + ch / 2 * 4;
  356. if(ch % 2) {
  357. return (vi_pre_dma_read(dev, reg) >> 16) & 0xfff;
  358. } else {
  359. return vi_pre_dma_read(dev, reg) & 0xfff;
  360. }
  361. }
  362. static void mframe_mode_set_position(struct vi_pre_dev *dev, int vc_ch, int f, int l)
  363. {
  364. u32 reg = dma_reg.dma_ctl23 + vc_ch / 2 * 4;
  365. u32 reg_val = vi_pre_dma_read(dev, reg);
  366. f &= 3;
  367. l &= 0xfff;
  368. if (vc_ch % 2) {
  369. reg_val &=~(0xffff << 16);
  370. reg_val |= (l << 16) | (f << 29);
  371. } else {
  372. reg_val &=~0xffff;
  373. reg_val |= l | (f << 13);
  374. }
  375. vi_pre_dma_write(dev, reg, reg_val);
  376. }
  377. static void mframe_set_start_addr(struct vi_pre_dev *dev, int frame_id, int vc_ch, unsigned long addr)
  378. {
  379. u32 reg = 0;
  380. u8 h = addr >> 32;
  381. u32 l = addr & 0xffffffff;
  382. if (frame_id <= 2) {
  383. reg = dma_reg.dma_ctl25 + frame_id * 24 + vc_ch * 8;
  384. } else {
  385. reg = dma_reg.dma_ctl45 + vc_ch * 8;
  386. }
  387. vi_pre_dma_write(dev, reg, h);
  388. vi_pre_dma_write(dev, reg + 4, l);
  389. }
  390. static u32 mframe_frame_done_flag(struct vi_pre_dev *dev)
  391. {
  392. return vi_pre_dma_read(dev, dma_reg.dma_ctl43);
  393. }
  394. static void mframe_frame_done_flag_clear(struct vi_pre_dev *dev, u32 mask)
  395. {
  396. vi_pre_dma_write(dev, dma_reg.dma_ctl43, mask);
  397. }
  398. static void dma_interrupt_set(struct vi_pre_dev *dev, u32 mask, int en)
  399. {
  400. u32 reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl44);
  401. if (en) {
  402. reg_val &= ~(mask << 16);
  403. } else {
  404. reg_val |= (mask << 16);
  405. }
  406. vi_pre_dma_write(dev, dma_reg.dma_ctl44, reg_val);
  407. reg_val = vi_pre_dma_read(dev, dma_reg.dma_ctl44);
  408. }
  409. static u16 dma_interrupt_status(struct vi_pre_dev *dev)
  410. {
  411. return vi_pre_dma_read(dev, dma_reg.dma_ctl44) & 0xffff;
  412. }
  413. static void dma_clear_interrupt_status(struct vi_pre_dev *dev, u32 sta)
  414. {
  415. u32 reg = vi_pre_dma_read(dev, dma_reg.dma_ctl44);
  416. reg |= sta;
  417. return vi_pre_dma_write(dev, dma_reg.dma_ctl44, reg);
  418. }
  419. static int vi_pre_mframe_config(struct vi_pre_dev *dev, vi_pre_dma_cfg_t *cfg)
  420. {
  421. unsigned long buf_base = (unsigned long)cfg->buf;
  422. int ret = 0;
  423. int i = 0;
  424. int j = 0;
  425. if (cfg->num > 4) {
  426. printk("%s, %d, cfg frame num error!!!\n", __func__, __LINE__);
  427. return -1;
  428. }
  429. if (cfg->buf_size < cfg->line_size * cfg->resolution_v * cfg->num) {
  430. printk("%s, %d, vipre buf size error!!!\n", __func__, __LINE__);
  431. return -1;
  432. }
  433. set_frame_num(dev, cfg->num);
  434. ret = set_mframe_oneline_group(dev, cfg);
  435. if (ret != 0) {
  436. printk("<0>""!!!!!!!set mframe oneline size error!!!!!!!!!!!!!!!!\n");
  437. return -1;
  438. }
  439. for(i = 0; i < cfg->num; i++) {
  440. ret = set_mfram_oneline_range(dev, i, cfg->line_size);
  441. if (ret != 0) {
  442. printk("<0>""!!!!!!!set mframe oneline range error!!!!!!!!!!!!!!!!\n");
  443. return -1;
  444. }
  445. for (j = 0; j < cfg->vc_num; j++) {
  446. mframe_set_start_addr(dev, i, j, buf_base);
  447. buf_base += cfg->line_size * cfg->resolution_v;
  448. }
  449. }
  450. return 0;
  451. }
  452. static int vi_pre_nline_config(struct vi_pre_dev *dev, vi_pre_dma_cfg_t *cfg)
  453. {
  454. unsigned long buf_base = (unsigned long)cfg->buf;
  455. int i = 0;
  456. if (cfg->line_size % 256) {
  457. return -1;
  458. }
  459. if (cfg->buf_size < cfg->line_size * cfg->num) {
  460. return -1;
  461. }
  462. if (set_nline_oneline_size(dev, cfg) != 0) {
  463. return -1;
  464. }
  465. set_nline_period(dev, cfg->num);
  466. set_nline_int_period(dev, cfg->n_line_int);
  467. for(i = 0; i < cfg->vc_num; i++) {
  468. nline_mode_set_start_addr(dev, i, buf_base);
  469. buf_base += cfg->line_size * cfg->resolution_v;
  470. }
  471. return 0;
  472. }
  473. int vi_pre_dma_init(struct vi_pre_dev *pdriver_dev)
  474. {
  475. return 0;
  476. }
  477. int vi_pre_dma_uninit(struct platform_device *pdev)
  478. {
  479. struct vi_pre_dev *pdriver_dev;
  480. pdriver_dev = platform_get_drvdata(pdev);
  481. memset(pdriver_dev->cnt, 0, sizeof(pdriver_dev->cnt));
  482. return 0;
  483. }
  484. static int dma_config(struct vi_pre_dev *pdriver_dev, vi_pre_dma_cfg_t *cfg)
  485. {
  486. int ret = 0;
  487. set_dma_burst_length(pdriver_dev, 16);
  488. set_dma_data_width(pdriver_dev, cfg->width);
  489. set_bit_mode(pdriver_dev, 0);
  490. set_dma_mode(pdriver_dev, cfg->mode);
  491. set_dma_resolution(pdriver_dev, cfg->resolution_h, cfg->resolution_v);
  492. if (cfg->mode == VI_PRE_M_FRAME) {
  493. ret = vi_pre_mframe_config(pdriver_dev, cfg);
  494. pdriver_dev->is_mframe_mode = true;
  495. } else if (cfg->mode == VI_PRE_N_LANE) {
  496. ret = vi_pre_nline_config(pdriver_dev, cfg);
  497. pdriver_dev->is_mframe_mode = false;
  498. }
  499. return ret;
  500. }
  501. int vi_pre_dma_config(struct vi_pre_dev *pdriver_dev, void *arg)
  502. {
  503. vi_pre_dma_cfg_t cfg;
  504. check_retval(copy_from_user(&cfg, arg, sizeof(cfg)));
  505. //cfg.buf_size = cfg.num * cfg.vc_num * cfg.line_size * cfg.resolution_v;
  506. //cfg.buf = (u8 *)img_buf;
  507. return dma_config(pdriver_dev, &cfg);
  508. }
  509. int vi_pre_dma_mframe_set_buf(struct vi_pre_dev *pdriver_dev, void *arg)
  510. {
  511. int j = 0;
  512. vi_pre_mframe_cfg_t mframe_cfg;
  513. check_retval(copy_from_user(&mframe_cfg, arg, sizeof(mframe_cfg)));
  514. unsigned long buf_base = (unsigned long)mframe_cfg.buf_addr;
  515. for (j = 0; j < mframe_cfg.vc_num; j++) {
  516. mframe_set_start_addr(pdriver_dev, mframe_cfg.frame_id, j, buf_base);
  517. buf_base += mframe_cfg.frame_size;
  518. }
  519. return 0;
  520. }
  521. int vi_pre_dma_get_mframe_done_id(struct vi_pre_dev *pdriver_dev, void *arg)
  522. {
  523. vi_pre_update_frame_info_t info;
  524. info.update_frame_id = pdriver_dev->update_frame_id;
  525. info.update_vc_id = pdriver_dev->update_vc_id;
  526. check_retval(copy_to_user(arg, &info,sizeof(info)));
  527. return 0;
  528. }
  529. int vi_pre_dma_mframe_update_buf(struct vi_pre_dev *pdriver_dev, void *arg)
  530. {
  531. vi_pre_mframe_update_t mframe;
  532. check_retval(copy_from_user(&mframe, arg, sizeof(mframe)));
  533. unsigned long buf_base = (unsigned long)mframe.buf_addr;
  534. mframe_set_start_addr(pdriver_dev, mframe.frame_id, mframe.vc_id, buf_base);
  535. return 0;
  536. }
  537. int vi_pre_dma_start(struct vi_pre_dev *pdriver_dev)
  538. {
  539. u32 mask = VIPRE_BUS_ERR | VIPRE_FIFO_OVER | VIPRE_NMOVERFLOW;
  540. if (pdriver_dev->is_mframe_mode) {
  541. mask |= VIPRE_FRAME_DONE;
  542. } else {
  543. mask |= VIPRE_LINE_DONE;
  544. }
  545. dma_interrupt_set(pdriver_dev, mask, 1);
  546. dma_enable(pdriver_dev, 1);
  547. return 0;
  548. }
  549. int vi_pre_dma_stop(struct vi_pre_dev *pdriver_dev)
  550. {
  551. u32 mask = VIPRE_BUS_ERR | VIPRE_FIFO_OVER | VIPRE_NMOVERFLOW;
  552. dma_interrupt_set(pdriver_dev, mask, 0);
  553. dma_enable(pdriver_dev, 0);
  554. udelay(1000);
  555. return 0;
  556. }
  557. static int vipre_event = 0;
  558. int *vi_pre_event(void)
  559. {
  560. return &vipre_event;
  561. }
  562. static int f_done_sta_to_frame_id(u32 sta)
  563. {
  564. #define FRAME_0_DONE (1 << 11)
  565. #define FRAME_1_DONE (1 << 10)
  566. #define FRAME_2_DONE (1 << 9)
  567. #define FRAME_3_DONE (1 << 8)
  568. int f_id = 0;
  569. if (sta & FRAME_0_DONE) {
  570. f_id = 3;
  571. } else if (sta & FRAME_1_DONE) {
  572. f_id = 0;
  573. } else if (sta & FRAME_2_DONE) {
  574. f_id = 1;
  575. } else if (sta & FRAME_3_DONE) {
  576. f_id = 2;
  577. }
  578. return f_id;
  579. }
  580. void vi_pre_dma_interrupt_handler(struct vi_pre_dev *pdriver_dev)
  581. {
  582. u32 status = 0;
  583. u32 f_done_sta = 0;
  584. unsigned long flags = 0;
  585. //int i = 0;
  586. spin_lock_irqsave(&pdriver_dev->slock, flags);
  587. status = dma_interrupt_status(pdriver_dev);
  588. if (status & (1 << 4)) {
  589. printk("<0>""vipre err int sta 0x%x\n", status);
  590. }
  591. dma_clear_interrupt_status(pdriver_dev, status);
  592. if (status & VIPRE_FRAME_DONE) {
  593. pdriver_dev->cnt++;
  594. if (pdriver_dev->cnt >= 4) {
  595. pdriver_dev->cnt = 0;
  596. }
  597. vipre_event = 1;
  598. f_done_sta = mframe_frame_done_flag(pdriver_dev);
  599. mframe_frame_done_flag_clear(pdriver_dev, f_done_sta);
  600. pdriver_dev->update_frame_id = f_done_sta_to_frame_id(f_done_sta);
  601. mframe_mode_set_position(pdriver_dev, 0, pdriver_dev->update_frame_id, 0);
  602. pdriver_dev->update_vc_id = 0;
  603. } else if (status & VIPRE_LINE_DONE) {
  604. //u32 nline_done_sta =;
  605. //pdriver_dev->cnt++;
  606. //printk("line done %x\n", f_done_sta);
  607. //vipre_event = 1;
  608. }
  609. #if 0
  610. //u32 line_cnt = pdriver_dev->cnt * get_nline_int_period(pdriver_dev);
  611. if (pdriver_dev->is_mframe_mode) {
  612. for(i = 0; i < 3; i++) {
  613. if(pdriver_dev->cnt[i] < get_frame_num(pdriver_dev)) {
  614. continue;
  615. }
  616. pdriver_dev->cnt[i] = 0;
  617. dma_period_clear(pdriver_dev, i);
  618. }
  619. }
  620. else (pdriver_dev->is_mframe_mode == 0 && line_cnt >= get_nline_period(pdriver_dev)){
  621. dma_period_clear(struct vi_pre_dev *dev, int ch)
  622. }
  623. #endif
  624. spin_unlock_irqrestore(&pdriver_dev->slock, flags);
  625. }
  626. int vi_pore_vc_bind(struct platform_device *pdev, u8 buf_id, u8 vc_id)
  627. {
  628. return 0;
  629. }
  630. int vi_pore_attach_callback(struct platform_device *pdev)
  631. {
  632. return 0;
  633. }
  634. int vi_pore_deattach_callback(struct platform_device *pdev)
  635. {
  636. return 0;
  637. }
  638. /////////////////demo///////////////////////
  639. void test(struct vi_pre_dev *pdev)
  640. {
  641. vi_pre_dma_cfg_t cfg;
  642. cfg.vc_num = 1;
  643. cfg.width = VI_PRE_RAW_12BIT;
  644. cfg.mode = VI_PRE_M_FRAME;
  645. cfg.resolution_h = 1944; //1920;//3840;
  646. cfg.resolution_v = 1100; //1080;//2160;
  647. cfg.line_size = 2048 * 2; //必须256byte对齐
  648. cfg.num = 4; //n line num, or m frame num(m frme max is 4)
  649. cfg.buf_size = 2048 * 1100 * 2 * 10;
  650. cfg.buf = (u8 *)img_buf;
  651. dma_config(pdev, &cfg);
  652. vi_pre_dma_start(pdev);
  653. }