vi_pre.h 11 KB

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  1. /*
  2. * Copyright (C) 2021 Alibaba Group Holding Limited
  3. * Author: Shenwuyi <shenwuyi.swy@alibaba-inc.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. */
  9. #ifndef __VI_PRE_H__
  10. #define __VI_PRE_H__
  11. #include <linux/io.h>
  12. #include <linux/of.h>
  13. #include <linux/err.h>
  14. #include <linux/clk.h>
  15. #include <linux/slab.h>
  16. #include <linux/delay.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/of_dma.h>
  21. #include <linux/device.h>
  22. #include <linux/videodev2.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/cdev.h>
  27. #define VI_PRE_DEV_NAME "vi_pre"
  28. #define VI_PRE_NAME "vipre"
  29. #define VI_PRE_MAXCNT 1
  30. #define HDRPRO_CTRL(n) (0x0094 + (n-1) * 4)
  31. #define HDRPRO_COE(n) (0x009c + (n-1) * 4)
  32. #define HDRPRO_LINW(n) (0x00b0 + (n-1) * 4)
  33. #define HDRPRO_LINA(n) (0x00d0 + (n-1) * 4)
  34. #define HDRPRO_LINB(n) (0x0110 + (n-1) * 4)
  35. #define MIPI2DMA_CTRL(n) (0x0198 + (n) * 4)
  36. #define VIPRE_BUS_ERR (1 << 5)
  37. #define VIPRE_FIFO_OVER (1 << 4)
  38. #define VIPRE_IDLE_DONE (1 << 3)
  39. #define VIPRE_NMOVERFLOW (1 << 2)
  40. #define VIPRE_LINE_DONE (1 << 1)
  41. #define VIPRE_FRAME_DONE (1 << 0)
  42. /* mipi2dma ctrl0 */
  43. enum mipi2dma_ctrl0_regval {
  44. //RAWMOD
  45. MIPI2DMA_CTRL0_RAW6 = 0 << 4,
  46. MIPI2DMA_CTRL0_RAW7 = 1 << 4,
  47. MIPI2DMA_CTRL0_RAW8 = 2 << 4,
  48. MIPI2DMA_CTRL0_RAW10 = 3 << 4,
  49. MIPI2DMA_CTRL0_RAW12 = 4 << 4,
  50. //RAWPOS
  51. MIPI2DMA_CTRL0_LOW_BIT_MODE = 0 << 3,
  52. MIPI2DMA_CTRL0_HIGH_BIT_MODE = 1 << 3,
  53. //mnum
  54. MIPI2DMA_CTRL0_1_FRAME = 0 << 1,
  55. MIPI2DMA_CTRL0_2_FRAME = 1 << 1,
  56. MIPI2DMA_CTRL0_3_FRAME = 2 << 1,
  57. MIPI2DMA_CTRL0_4_FRAME = 3 << 1,
  58. //mnmod
  59. MIPI2DMA_CTRL0_MODE_M_FRAME = 0 << 0,
  60. MIPI2DMA_CTRL0_MODE_N_LINE = 1 << 0,
  61. };
  62. /* mipi2dma ctrl1 */
  63. enum mipi2dma_ctrl1_regval {
  64. //MIPI2DMA_WBURSTLEN
  65. MIPI2DMA_CTRL1_WBURSTLEN_4 = 3 << 16,
  66. MIPI2DMA_CTRL1_WBURSTLEN_8 = 7 << 16,
  67. MIPI2DMA_CTRL1_WBURSTLEN_16 = 15 << 16,
  68. };
  69. /* mipi2dma ctrl10 */
  70. enum mipi2dma_ctrl10_regval {
  71. MIPI2DMA_START = 1 << 0,
  72. MIPI2DMA_STOP = 0 << 0,
  73. };
  74. /* mipi2dma ctrl51 */
  75. enum mipi2dma_ctrl51_regval {
  76. MIPI2DMA_CTRL51_CROSS_4K_EN = 1 << 0,
  77. MIPI2DMA_CTRL51_CROSS_4K_DIS = 0 << 0,
  78. };
  79. //MIPI2DMA
  80. #define MIPI2DMA_CTRL1_WOSNUM_SHIFT 0
  81. #define MIPI2DMA_CTRL3_VERTICAL_SHIFT 16
  82. #define MIPI2DMA_CTRL3_HORIZON_SHIFT 0
  83. #define MIPI2DMA_CTRL4_BURSTREM_SHIFT 27
  84. #define MIPI2DMA_CTRL4_READNUM_SHIFT 16
  85. #define MIPI2DMA_CTRL4_HORIZON_CNT128_SHIFT 0
  86. #define MIPI2DMA_CTRL5_N_NLINENUM_SHIFT 16
  87. #define MIPI2DMA_CTRL5_N_LINENUM_SHIFT 0
  88. #define MIPI2DMA_CTRL6_N_STRIDE_SHIFT 0
  89. #define MIPI2DMA_CTRL7_M0_STRIDE_SHIFT 16
  90. #define MIPI2DMA_CTRL7_M1_STRIDE_SHIFT 0
  91. #define MIPI2DMA_CTRL8_M2_STRIDE_SHIFT 16
  92. #define MIPI2DMA_CTRL8_M3_STRIDE_SHIFT 0
  93. #define MIPI2DMA_CTRL15_N_SADDR_ID0_H_SHIFT 0
  94. #define MIPI2DMA_CTRL16_N_SADDR_ID0_L_SHIFT 0
  95. #define MIPI2DMA_CTRL17_N_SADDR_ID1_H_SHIFT 0
  96. #define MIPI2DMA_CTRL18_N_SADDR_ID1_L_SHIFT 0
  97. #define MIPI2DMA_CTRL19_N_SADDR_ID2_H_SHIFT 0
  98. #define MIPI2DMA_CTRL20_N_SADDR_ID2_L_SHIFT 0
  99. #define MIPI2DMA_CTRL25_M0_SADDR_ID0_H_SHIFT 0
  100. #define MIPI2DMA_CTRL26_M0_SADDR_ID0_L_SHIFT 0
  101. #define MIPI2DMA_CTRL27_M0_SADDR_ID1_H_SHIFT 0
  102. #define MIPI2DMA_CTRL28_M0_SADDR_ID1_L_SHIFT 0
  103. #define MIPI2DMA_CTRL29_M0_SADDR_ID2_H_SHIFT 0
  104. #define MIPI2DMA_CTRL30_M0_SADDR_ID2_L_SHIFT 0
  105. #define MIPI2DMA_CTRL31_M1_SADDR_ID0_H_SHIFT 0
  106. #define MIPI2DMA_CTRL32_M1_SADDR_ID0_L_SHIFT 0
  107. #define MIPI2DMA_CTRL33_M1_SADDR_ID1_H_SHIFT 0
  108. #define MIPI2DMA_CTRL34_M1_SADDR_ID1_L_SHIFT 0
  109. #define MIPI2DMA_CTRL35_M1_SADDR_ID2_H_SHIFT 0
  110. #define MIPI2DMA_CTRL36_M1_SADDR_ID2_L_SHIFT 0
  111. #define MIPI2DMA_CTRL37_M2_SADDR_ID0_H_SHIFT 0
  112. #define MIPI2DMA_CTRL38_M2_SADDR_ID0_L_SHIFT 0
  113. #define MIPI2DMA_CTRL39_M2_SADDR_ID1_H_SHIFT 0
  114. #define MIPI2DMA_CTRL40_M2_SADDR_ID1_L_SHIFT 0
  115. #define MIPI2DMA_CTRL41_M2_SADDR_ID2_H_SHIFT 0
  116. #define MIPI2DMA_CTRL42_M2_SADDR_ID2_L_SHIFT 0
  117. #define MIPI2DMA_CTRL44_BUSERR_MASK_SHIFT 21
  118. #define MIPI2DMA_CTRL44_FIFO_OVERERR_MASK_SHIFT 20
  119. #define MIPI2DMA_CTRL44_IDLE_DONE_MASK_SHIFT 19
  120. #define MIPI2DMA_CTRL44_MN_OVERERR_MASK_SHIFT 18
  121. #define MIPI2DMA_CTRL44_NLINE_DONE_MASK_SHIFT 17
  122. #define MIPI2DMA_CTRL44_MFRAME_DONE_MASK_SHIFT 16
  123. #define MIPI2DMA_CTRL45_M3_SADDR_ID0_H_SHIFT 0
  124. #define MIPI2DMA_CTRL46_M3_SADDR_ID0_L_SHIFT 0
  125. #define MIPI2DMA_CTRL47_M3_SADDR_ID1_H_SHIFT 0
  126. #define MIPI2DMA_CTRL48_M3_SADDR_ID1_L_SHIFT 0
  127. #define MIPI2DMA_CTRL49_M3_SADDR_ID2_H_SHIFT 0
  128. #define MIPI2DMA_CTRL50_M3_SADDR_ID2_L_SHIFT 0
  129. //HDRPRO
  130. #define HDRPRO_CTRL1_HDRPRO_RAWMOD_MASK 0x00e00000
  131. #define HDRPRO_CTRL1_BAYER_MODSEL_MASK 0x00180000
  132. #define HDRPRO_CTRL1_COLOR_MODSEL_MASK 0x00070000
  133. #define HDRPRO_CTRL1_LAST_DELAY_MASK 0x0000fff8
  134. #define HDRPRO_CTRL1_HDRPRO_ID_MASK 0x00000006
  135. #define HDRPRO_CTRL1_HDRPRO_EN_MASK 0x00000001
  136. #define HDRPRO_CTRL1_HDRPRO_ID_SHIFT 1
  137. #define HDRPRO_CTRL2_VERTICAL_MASK 0x1fff0000
  138. #define HDRPRO_CTRL2_HORIZON_MASK 0x00001fff
  139. #define HDRPRO_CTRL2_VERTICAL_SHIFT 16
  140. #define HDRPRO_CTRL2_HORIZON_SHIFT 0
  141. #define HDRPRO_COE1_BE_BLACK_WR_MASK 0xf0000000
  142. #define HDRPRO_COE1_BE_BLACK_WB_MASK 0x0f000000
  143. #define HDRPRO_COE1_BE_BLACK_WG0_MASK 0x00f00000
  144. #define HDRPRO_COE1_BE_BLACK_WG1_MASK 0x000f0000
  145. #define HDRPRO_COE1_BE_COLOR_WG0_00_MASK 0x0000f000
  146. #define HDRPRO_COE1_BE_COLOR_WG0_01_MASK 0x00000f00
  147. #define HDRPRO_COE1_BE_COLOR_WG0_02_MASK 0x000000f0
  148. #define HDRPRO_COE1_BE_COLOR_WG0_10_MASK 0x0000000f
  149. #define HDRPRO_COE1_BE_BLACK_WR_SHIFT 28
  150. #define HDRPRO_COE1_BE_BLACK_WB_SHIFT 24
  151. #define HDRPRO_COE1_BE_BLACK_WG0_SHIFT 20
  152. #define HDRPRO_COE1_BE_BLACK_WG1_SHIFT 16
  153. #define HDRPRO_COE1_BE_COLOR_WG0_00_SHIFT 12
  154. #define HDRPRO_COE1_BE_COLOR_WG0_01_SHIFT 8
  155. #define HDRPRO_COE1_BE_COLOR_WG0_02_SHIFT 4
  156. #define HDRPRO_COE1_BE_COLOR_WG0_10_SHIFT 0
  157. #define HDRPRO_COE2_BE_COLOR_WG0_11_SHIFT 28
  158. #define HDRPRO_COE2_BE_COLOR_WG0_12_SHIFT 24
  159. #define HDRPRO_COE2_BE_COLOR_WG0_20_SHIFT 20
  160. #define HDRPRO_COE2_BE_COLOR_WG0_21_SHIFT 16
  161. #define HDRPRO_COE2_BE_COLOR_WG0_22_SHIFT 12
  162. #define HDRPRO_COE2_BE_COLOR_WG1_00_SHIFT 8
  163. #define HDRPRO_COE2_BE_COLOR_WG1_01_SHIFT 4
  164. #define HDRPRO_COE2_BE_COLOR_WG1_02_SHIFT 0
  165. #define HDRPRO_COE3_BE_COLOR_WG1_10_SHIFT 28
  166. #define HDRPRO_COE3_BE_COLOR_WG1_11_SHIFT 24
  167. #define HDRPRO_COE3_BE_COLOR_WG1_12_SHIFT 20
  168. #define HDRPRO_COE3_BE_COLOR_WG1_20_SHIFT 16
  169. #define HDRPRO_COE3_BE_COLOR_WG1_21_SHIFT 12
  170. #define HDRPRO_COE3_BE_COLOR_WG1_22_SHIFT 8
  171. #define HDRPRO_COE3_BE_COLOR_WR_00_SHIFT 4
  172. #define HDRPRO_COE3_BE_COLOR_WR_01_SHIFT 0
  173. #define HDRPRO_COE4_BE_COLOR_WR_02_SHIFT 28
  174. #define HDRPRO_COE4_BE_COLOR_WR_10_SHIFT 24
  175. #define HDRPRO_COE4_BE_COLOR_WR_11_SHIFT 20
  176. #define HDRPRO_COE4_BE_COLOR_WR_12_SHIFT 16
  177. #define HDRPRO_COE4_BE_COLOR_WR_20_SHIFT 12
  178. #define HDRPRO_COE4_BE_COLOR_WR_21_SHIFT 8
  179. #define HDRPRO_COE4_BE_COLOR_WR_22_SHIFT 4
  180. #define HDRPRO_COE4_BE_COLOR_WB_00_SHIFT 0
  181. #define HDRPRO_COE5_BE_COLOR_WB_01_SHIFT 28
  182. #define HDRPRO_COE5_BE_COLOR_WB_02_SHIFT 24
  183. #define HDRPRO_COE5_BE_COLOR_WB_10_SHIFT 20
  184. #define HDRPRO_COE5_BE_COLOR_WB_11_SHIFT 16
  185. #define HDRPRO_COE5_BE_COLOR_WB_12_SHIFT 12
  186. #define HDRPRO_COE5_BE_COLOR_WB_20_SHIFT 8
  187. #define HDRPRO_COE5_BE_COLOR_WB_21_SHIFT 4
  188. #define HDRPRO_COE5_BE_COLOR_WB_22_SHIFT 0
  189. #define HDRPRO_LINW1_W1_MASK 0x0fff0000
  190. #define HDRPRO_LINW1_W2_MASK 0x00000fff
  191. #define HDRPRO_LINW2_W3_MASK 0x0fff0000
  192. #define HDRPRO_LINW2_W4_MASK 0x00000fff
  193. #define HDRPRO_LINW3_W5_MASK 0x0fff0000
  194. #define HDRPRO_LINW3_W6_MASK 0x00000fff
  195. #define HDRPRO_LINW4_W7_MASK 0x0fff0000
  196. #define HDRPRO_LINW4_W8_MASK 0x00000fff
  197. #define HDRPRO_LINW5_W9_MASK 0x0fff0000
  198. #define HDRPRO_LINW5_W10_MASK 0x00000fff
  199. #define HDRPRO_LINW6_W11_MASK 0x0fff0000
  200. #define HDRPRO_LINW6_W12_MASK 0x00000fff
  201. #define HDRPRO_LINW7_W13_MASK 0x0fff0000
  202. #define HDRPRO_LINW7_W14_MASK 0x00000fff
  203. #define HDRPRO_LINW8_W15_MASK 0x0fff0000
  204. #define HDRPRO_LINW8_W16_MASK 0x00000fff
  205. #define HDRPRO_LINW1_W1_SHIFT 16
  206. #define HDRPRO_LINW1_W2_SHIFT 0
  207. #define HDRPRO_LINW2_W3_SHIFT 16
  208. #define HDRPRO_LINW2_W4_SHIFT 0
  209. #define HDRPRO_LINW3_W5_SHIFT 16
  210. #define HDRPRO_LINW3_W6_SHIFT 0
  211. #define HDRPRO_LINW4_W7_SHIFT 16
  212. #define HDRPRO_LINW4_W8_SHIFT 0
  213. #define HDRPRO_LINW5_W9_SHIFT 16
  214. #define HDRPRO_LINW5_W10_SHIFT 0
  215. #define HDRPRO_LINW6_W11_SHIFT 16
  216. #define HDRPRO_LINW6_W12_SHIFT 0
  217. #define HDRPRO_LINW7_W13_SHIFT 16
  218. #define HDRPRO_LINW7_W14_SHIFT 0
  219. #define HDRPRO_LINW8_W15_SHIFT 16
  220. #define HDRPRO_LINW8_W16_SHIFT 0
  221. #define HDRPRO_LINA1_A1_MASK 0x000fffff
  222. #define HDRPRO_LINA2_A2_MASK 0x000fffff
  223. #define HDRPRO_LINA3_A3_MASK 0x000fffff
  224. #define HDRPRO_LINA4_A4_MASK 0x000fffff
  225. #define HDRPRO_LINA5_A5_MASK 0x000fffff
  226. #define HDRPRO_LINA6_A6_MASK 0x000fffff
  227. #define HDRPRO_LINA7_A7_MASK 0x000fffff
  228. #define HDRPRO_LINA8_A8_MASK 0x000fffff
  229. #define HDRPRO_LINA9_A9_MASK 0x000fffff
  230. #define HDRPRO_LINA10_A10_MASK 0x000fffff
  231. #define HDRPRO_LINA11_A11_MASK 0x000fffff
  232. #define HDRPRO_LINA12_A12_MASK 0x000fffff
  233. #define HDRPRO_LINA13_A13_MASK 0x000fffff
  234. #define HDRPRO_LINA14_A14_MASK 0x000fffff
  235. #define HDRPRO_LINA15_A15_MASK 0x000fffff
  236. #define HDRPRO_LINA16_A16_MASK 0x000fffff
  237. #define HDRPRO_LINA1_A1_SHIFT 0
  238. #define HDRPRO_LINA2_A2_SHIFT 0
  239. #define HDRPRO_LINA3_A3_SHIFT 0
  240. #define HDRPRO_LINA4_A4_SHIFT 0
  241. #define HDRPRO_LINA5_A5_SHIFT 0
  242. #define HDRPRO_LINA6_A6_SHIFT 0
  243. #define HDRPRO_LINA7_A7_SHIFT 0
  244. #define HDRPRO_LINA8_A8_SHIFT 0
  245. #define HDRPRO_LINA9_A9_SHIFT 0
  246. #define HDRPRO_LINA10_A10_SHIFT 0
  247. #define HDRPRO_LINA11_A11_SHIFT 0
  248. #define HDRPRO_LINA12_A12_SHIFT 0
  249. #define HDRPRO_LINA13_A13_SHIFT 0
  250. #define HDRPRO_LINA14_A14_SHIFT 0
  251. #define HDRPRO_LINA15_A15_SHIFT 0
  252. #define HDRPRO_LINA16_A16_SHIFT 0
  253. #define HDRPRO_LINB1_B1_MASK 0x0000ffff
  254. #define HDRPRO_LINB2_B2_MASK 0x0000ffff
  255. #define HDRPRO_LINB3_B3_MASK 0x0000ffff
  256. #define HDRPRO_LINB4_B4_MASK 0x0000ffff
  257. #define HDRPRO_LINB5_B5_MASK 0x0000ffff
  258. #define HDRPRO_LINB6_B6_MASK 0x0000ffff
  259. #define HDRPRO_LINB7_B7_MASK 0x0000ffff
  260. #define HDRPRO_LINB8_B8_MASK 0x0000ffff
  261. #define HDRPRO_LINB9_B9_MASK 0x0000ffff
  262. #define HDRPRO_LINB10_B10_MASK 0x0000ffff
  263. #define HDRPRO_LINB11_B11_MASK 0x0000ffff
  264. #define HDRPRO_LINB12_B12_MASK 0x0000ffff
  265. #define HDRPRO_LINB13_B13_MASK 0x0000ffff
  266. #define HDRPRO_LINB14_B14_MASK 0x0000ffff
  267. #define HDRPRO_LINB15_B15_MASK 0x0000ffff
  268. #define HDRPRO_LINB16_B16_MASK 0x0000ffff
  269. #define HDRPRO_LINB1_B1_SHIFT 0
  270. #define HDRPRO_LINB2_B2_SHIFT 0
  271. #define HDRPRO_LINB3_B3_SHIFT 0
  272. #define HDRPRO_LINB4_B4_SHIFT 0
  273. #define HDRPRO_LINB5_B5_SHIFT 0
  274. #define HDRPRO_LINB6_B6_SHIFT 0
  275. #define HDRPRO_LINB7_B7_SHIFT 0
  276. #define HDRPRO_LINB8_B8_SHIFT 0
  277. #define HDRPRO_LINB9_B9_SHIFT 0
  278. #define HDRPRO_LINB10_B10_SHIFT 0
  279. #define HDRPRO_LINB11_B11_SHIFT 0
  280. #define HDRPRO_LINB12_B12_SHIFT 0
  281. #define HDRPRO_LINB13_B13_SHIFT 0
  282. #define HDRPRO_LINB14_B14_SHIFT 0
  283. #define HDRPRO_LINB15_B15_SHIFT 0
  284. #define HDRPRO_LINB16_B16_SHIFT 0
  285. struct vi_pre_dev {
  286. int id;
  287. int irq;
  288. dev_t devt;
  289. struct class *class;
  290. struct cdev cdev;
  291. spinlock_t slock; /* interrupt handling lock */
  292. struct mutex mutex;
  293. void __iomem *reg_base;
  294. unsigned long cnt; //used to cnt frame num or line num;
  295. int update_frame_id;
  296. int update_vc_id;
  297. bool is_mframe_mode;
  298. struct clk *aclk;
  299. struct clk *pclk;
  300. struct clk *pixclk;
  301. struct platform_device *pdev;
  302. };
  303. #endif/*__VI_PRE_H__*/