isp_miv2.c 42 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. #ifdef __KERNEL__
  54. #include <linux/io.h>
  55. #include <linux/module.h>
  56. #endif
  57. #include "mrv_all_bits.h"
  58. #include "isp_ioctl.h"
  59. #include "isp_types.h"
  60. #ifdef ISP_MIV2
  61. static void mi_set_slice(u32* val, u32 mask, u32 slice);
  62. extern MrvAllRegister_t *all_regs;
  63. static int getRawBit(u32 type, u32 *bit, u32 *len)
  64. {
  65. *len = 16;
  66. switch (type) {
  67. case ISP_PICBUF_TYPE_RAW8:
  68. *bit = 0;
  69. *len = 8;
  70. break;
  71. #if 0 /* normal process, need pass type from engine. */
  72. case ISP_PICBUF_TYPE_RAW10:
  73. *bit = 1;
  74. break;
  75. case ISP_PICBUF_TYPE_RAW12:
  76. *bit = 2;
  77. break;
  78. case ISP_PICBUF_TYPE_RAW14:
  79. *bit = 3;
  80. break;
  81. case ISP_PICBUF_TYPE_RAW16:
  82. *bit = 4;
  83. break;
  84. #else /* WA */
  85. case ISP_PICBUF_TYPE_RAW10:
  86. case ISP_PICBUF_TYPE_RAW12:
  87. case ISP_PICBUF_TYPE_RAW14:
  88. case ISP_PICBUF_TYPE_RAW16:
  89. *bit = 4;
  90. break;
  91. #endif
  92. default:
  93. isp_err("unsupport raw formt: %d\n", type);
  94. return -1;
  95. }
  96. return 0;
  97. }
  98. static bool isYuv(int type)
  99. {
  100. return (type == ISP_PICBUF_TYPE_YCbCr444) ||
  101. (type == ISP_PICBUF_TYPE_YCbCr422) ||
  102. (type == ISP_PICBUF_TYPE_YCbCr420) ||
  103. (type == ISP_PICBUF_TYPE_YCbCr400);
  104. }
  105. static bool isRaw(u32 type)
  106. {
  107. return (type == ISP_PICBUF_TYPE_RAW8) ||
  108. (type == ISP_PICBUF_TYPE_RAW10) ||
  109. (type == ISP_PICBUF_TYPE_RAW12) ||
  110. (type == ISP_PICBUF_TYPE_RAW14) || (type == ISP_PICBUF_TYPE_RAW16);
  111. }
  112. static void set_rgb_buffer(struct isp_ic_dev *dev, struct isp_buffer_context *buf)
  113. {
  114. u32 addr = buf->path == 0 ? REG_ADDR(miv2_mp_y_base_ad_init) :
  115. (buf->path ==
  116. 1) ? REG_ADDR(miv2_sp1_y_base_ad_init) :
  117. REG_ADDR(miv2_sp2_y_base_ad_init);
  118. if (buf->type == ISP_PICBUF_TYPE_RGB888) {
  119. isp_write_reg(dev, addr, (buf->addr_y & MP_Y_BASE_AD_MASK));
  120. isp_write_reg(dev, addr + 1 * 4,
  121. (buf->size_y & MP_Y_SIZE_MASK));
  122. isp_write_reg(dev, addr + 2 * 4, 0);
  123. isp_write_reg(dev, addr + 7 * 4,
  124. (buf->addr_cb & MP_CB_BASE_AD_MASK));
  125. isp_write_reg(dev, addr + 8 * 4,
  126. (buf->size_cb & MP_CB_SIZE_MASK));
  127. isp_write_reg(dev, addr + 9 * 4, 0);
  128. isp_write_reg(dev, addr + 10 * 4,
  129. (buf->addr_cr & MP_CR_BASE_AD_MASK));
  130. isp_write_reg(dev, addr + 11 * 4,
  131. (buf->size_cr & MP_CR_SIZE_MASK));
  132. isp_write_reg(dev, addr + 12 * 4, 0);
  133. }
  134. }
  135. /*#define PP_LINE_ENTRY*/
  136. #define PP_LINE_NUM 80*2
  137. static void set_yuv_buffer(struct isp_ic_dev *dev, struct isp_buffer_context *buf)
  138. {
  139. u32 addr = buf->path == 0 ? REG_ADDR(miv2_mp_y_base_ad_init) :
  140. (buf->path == 1) ? REG_ADDR(miv2_sp1_y_base_ad_init) :
  141. (buf->path == 2) ? REG_ADDR(miv2_sp2_y_base_ad_init) :
  142. REG_ADDR(isp_mi_pp_y_base_ad_init);
  143. if (isYuv(buf->type)) {
  144. isp_write_reg(dev, addr, (buf->addr_y & MP_Y_BASE_AD_MASK));
  145. isp_write_reg(dev, addr + 1 * 4,
  146. (buf->size_y & MP_Y_SIZE_MASK));
  147. isp_write_reg(dev, addr + 2 * 4, 0);
  148. isp_write_reg(dev, addr + 7 * 4,
  149. (buf->addr_cb & MP_CB_BASE_AD_MASK));
  150. isp_write_reg(dev, addr + 8 * 4,
  151. (buf->size_cb & MP_CB_SIZE_MASK));
  152. isp_write_reg(dev, addr + 9 * 4, 0);
  153. isp_write_reg(dev, addr + 10 * 4,
  154. (buf->addr_cr & MP_CR_BASE_AD_MASK));
  155. isp_write_reg(dev, addr + 11 * 4,
  156. (buf->size_cr & MP_CR_SIZE_MASK));
  157. isp_write_reg(dev, addr + 12 * 4, 0);
  158. }
  159. }
  160. static void set_raw_buffer(struct isp_ic_dev *dev, struct isp_buffer_context *buf)
  161. {
  162. u32 addr = buf->path == ISP_MI_PATH_MP ? REG_ADDR(miv2_mp_raw_base_ad_init) :
  163. (buf->path == ISP_MI_PATH_SP2_BP) ? REG_ADDR(miv2_sp2_raw_base_ad_init) :
  164. (buf->path == ISP_MI_PATH_PP) ?REG_ADDR(isp_mi_pp_y_base_ad_init):
  165. #ifdef ISP_MI_MCM_WR
  166. (buf->path == ISP_MI_MCM_WR0) ?REG_ADDR(miv2_mcm_raw0_base_ad_init):
  167. (buf->path == ISP_MI_MCM_WR1) ?REG_ADDR(miv2_mcm_raw1_base_ad_init):
  168. #endif
  169. #ifdef ISP_MI_HDR
  170. (buf->path == ISP_MI_HDR_L) ?REG_ADDR(isp_mi_hdr_l_base_ad_init):
  171. (buf->path == ISP_MI_HDR_S) ?REG_ADDR(isp_mi_hdr_s_base_ad_init):
  172. (buf->path == ISP_MI_HDR_VS) ?REG_ADDR(isp_mi_hdr_vs_base_ad_init):
  173. #endif
  174. 0;
  175. uint32_t line_num = isp_read_reg(dev, REG_ADDR(mi_sp1_ppw_ycbcr_entry_line_num));
  176. if ((buf->path == ISP_MI_PATH_PP) && (line_num != 0)) {
  177. buf->addr_y = dev->pp_write.buf_addr;
  178. buf->size_y = dev->pp_write.buf_size;
  179. }
  180. /*isp_info("%s path %d type %d addr %08x line_num = %d buf_addr = 0x%x, buf_size = %d\n",
  181. __func__, buf->path, buf->type, addr, line_num, buf->addr_y, buf->size_y);*/
  182. if (isRaw(buf->type)) {
  183. if (addr != 0) {
  184. isp_write_reg(dev, addr,
  185. (buf->addr_y & MP_RAW_BASE_AD_MASK));
  186. isp_write_reg(dev, addr + 4,
  187. (buf->size_y & MP_RAW_SIZE_MASK));
  188. isp_write_reg(dev, addr + 2 * 4, 0);
  189. }
  190. }
  191. }
  192. int isp_set_buffer(struct isp_ic_dev *dev, struct isp_buffer_context *buf)
  193. {
  194. if (!dev || !buf) {
  195. isp_err("NULL pointer %s\n", __func__);
  196. return -1;
  197. }
  198. set_yuv_buffer(dev, buf);
  199. set_raw_buffer(dev, buf);
  200. set_rgb_buffer(dev, buf);
  201. return 0;
  202. }
  203. static int calc_raw_lval(int width, int out_mode, int align_mode)
  204. {
  205. u32 lval = 0;
  206. if (align_mode == ISP_MI_DATA_ALIGN_16BIT_MODE) {
  207. if ((out_mode == IC_MI_DATAMODE_RAW10) ||
  208. (out_mode == IC_MI_DATAMODE_RAW12) ||
  209. (out_mode == IC_MI_DATAMODE_RAW14)) {
  210. lval = (width + 7) / 8;
  211. }
  212. } else if (align_mode == ISP_MI_DATA_ALIGN_128BIT_MODE) {
  213. if (out_mode == IC_MI_DATAMODE_RAW10){
  214. lval = (width + 12 - 1)/12;
  215. }else if(out_mode == IC_MI_DATAMODE_RAW12){
  216. lval = (width + 10 - 1)/10;
  217. }else if(out_mode == IC_MI_DATAMODE_RAW14){
  218. lval = (width + 9 - 1)/9;
  219. }else{
  220. lval = (width + 128 - 1)/128;
  221. }
  222. } else {
  223. if (out_mode == IC_MI_DATAMODE_RAW10) {
  224. lval = (width * 10 + 127) / 128;
  225. } else if (out_mode == IC_MI_DATAMODE_RAW12) {
  226. lval = (width * 12 + 127) / 128;
  227. } else if (out_mode == IC_MI_DATAMODE_RAW14) {
  228. lval = (width * 14 + 127) / 128;
  229. } else if (out_mode == IC_MI_DATAMODE_RAW16) {
  230. lval = (width * 16 + 127) / 128;
  231. } else {
  232. lval = (width * 8 + 127) / 128;
  233. }
  234. }
  235. return lval;
  236. }
  237. struct isp_dma_path_context{
  238. u32 ctrl_addr;
  239. u32 fmt_addr;
  240. u32 bus_cfg_addr;
  241. u32 bus_id_addr;
  242. u32 mi_imsc_addr;
  243. u32 rd_fmt_align;
  244. u32 rd_raw_bit;
  245. u32 rd_cfg_upd;
  246. u32 rd_auto_upd;
  247. u32 pic_start_addr;
  248. u32 pic_width;
  249. u32 pic_height;
  250. u32 pic_llength;
  251. u32 pic_size;
  252. u32 pic_lval;
  253. u32 path_enable_mask;
  254. u32 path_dma_start_mask;
  255. };
  256. int isp_ioc_cfg_dma(struct isp_ic_dev *dev, void __user *args)
  257. {
  258. u32 llength, miv2_imsc, miv2_ctrl,path_ctrl,path_fmt;
  259. struct isp_dma_context dma;
  260. //u32 path_bus_cfg;
  261. u32 bus_id;
  262. u32 path_rd_fmt_bit = 0;
  263. u8 id;
  264. struct isp_dma_path_context dma_path_ctx[] =
  265. #ifndef ISP_MI_PP_READ
  266. {{REG_ADDR(miv2_mcm_ctrl), REG_ADDR(miv2_mcm_fmt), REG_ADDR(miv2_mcm_bus_cfg), REG_ADDR(miv2_mcm_bus_id),
  267. REG_ADDR(miv2_imsc), MCM_RD_FMT_ALIGNED_MASK, MCM_RD_RAW_BIT_MASK, MCM_RD_CFG_UPD_MASK, MCM_RD_AUTO_UPDATE_MASK, \
  268. REG_ADDR(miv2_mcm_dma_raw_pic_start_ad), REG_ADDR(miv2_mcm_dma_raw_pic_width), 0, \
  269. REG_ADDR(miv2_mcm_dma_raw_pic_llength), REG_ADDR(miv2_mcm_dma_raw_pic_size), \
  270. REG_ADDR(miv2_mcm_dma_raw_pic_lval), MCM_RAW_RDMA_PATH_ENABLE_MASK, MCM_RAW_RDMA_START_MASK},
  271. #ifdef ISP_MI_HDR
  272. {REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(miv2_imsc2), \
  273. HDR_RD_RAW_ALIGNED_MASK, HDR_RD_L_BIT_MASK, HDR_RD_RAW_CFG_UPDATE_MASK,HDR_RD_RAW_CFG_UPDATE_MASK, \
  274. REG_ADDR(isp_mi_hdr_dma_l_base_ad_init), REG_ADDR(isp_mi_hdr_dma_pic_width), REG_ADDR(isp_mi_hdr_dma_pic_height), \
  275. REG_ADDR(isp_mi_hdr_dma_l_llength), REG_ADDR(isp_mi_hdr_dma_l_size_init), \
  276. REG_ADDR(isp_mi_hdr_dma_l_lval), 0, HDR_DMA_START_MASK},
  277. {REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(miv2_imsc2), \
  278. HDR_RD_RAW_ALIGNED_MASK, HDR_RD_S_BIT_MASK, HDR_RD_RAW_CFG_UPDATE_MASK,HDR_RD_RAW_CFG_UPDATE_MASK, \
  279. REG_ADDR(isp_mi_hdr_dma_s_base_ad_init), REG_ADDR(isp_mi_hdr_dma_pic_width), REG_ADDR(isp_mi_hdr_dma_pic_height), \
  280. REG_ADDR(isp_mi_hdr_dma_s_llength), REG_ADDR(isp_mi_hdr_dma_s_size_init), \
  281. REG_ADDR(isp_mi_hdr_dma_s_lval), 0, HDR_DMA_START_MASK},
  282. {REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(miv2_imsc2), \
  283. HDR_RD_RAW_ALIGNED_MASK, HDR_RD_VS_BIT_MASK, HDR_RD_RAW_CFG_UPDATE_MASK,HDR_RD_RAW_CFG_UPDATE_MASK, \
  284. REG_ADDR(isp_mi_hdr_dma_vs_base_ad_init), REG_ADDR(isp_mi_hdr_pic_width), REG_ADDR(isp_mi_hdr_dma_pic_height), \
  285. REG_ADDR(isp_mi_hdr_dma_vs_llength), REG_ADDR(isp_mi_hdr_dma_vs_size_init), \
  286. REG_ADDR(isp_mi_hdr_dma_vs_lval), 0, HDR_DMA_START_MASK}
  287. #endif
  288. };
  289. #else
  290. {{REG_ADDR(isp_mi_pp_ctrl), REG_ADDR(isp_mi_pp_fmt), 0, 0, REG_ADDR(miv2_imsc2), \
  291. PP_RD_RAW_ALIGNED_MASK, PP_RD_RAW_BIT_MASK, PP_MI_CFG_UPD_MASK, PP_RD_YUV_CFG_UPDATE_MASK, \
  292. REG_ADDR(isp_mi_pp_dma_y_pic_start_ad), REG_ADDR(isp_mi_pp_dma_y_pic_width), 0, \
  293. REG_ADDR(isp_mi_pp_dma_y_pic_llength), REG_ADDR(isp_mi_pp_dma_y_pic_size), \
  294. REG_ADDR(isp_mi_pp_dma_y_pic_lval), 0, PP_DMA_START_MASK}};
  295. #endif
  296. if (dev == NULL || args == NULL) {
  297. isp_info("input wrong parameter %s\n", __func__);
  298. return -1;
  299. }
  300. isp_info("enter %s\n", __func__);
  301. viv_check_retval(copy_from_user(&dma, args, sizeof(dma)));
  302. id = dma.id;
  303. if ( id > ISP_MI_DMA_ID_MAX){
  304. isp_info("id config wrong %s\n", __func__);
  305. return -1;
  306. }
  307. path_fmt = isp_read_reg(dev, dma_path_ctx[id].fmt_addr);
  308. #ifdef ISP_MI_PP_READ
  309. path_fmt |= 0x80000000;
  310. #endif
  311. miv2_imsc = isp_read_reg(dev, dma_path_ctx[id].mi_imsc_addr);
  312. miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl));
  313. path_ctrl = isp_read_reg(dev, dma_path_ctx[id].ctrl_addr);
  314. //if ( dma_path_ctx[id].bus_cfg_addr != 0) {
  315. // path_bus_cfg = isp_read_reg(dev, dma_path_ctx[id].bus_cfg_addr);
  316. //}
  317. if ( dma_path_ctx[id].bus_id_addr != 0) {
  318. bus_id = isp_read_reg(dev, dma_path_ctx[id].bus_id_addr);
  319. }
  320. if ( dma.align == ISP_MI_DATA_UNALIGN_MODE ) {
  321. switch(dma.type){
  322. case ISP_PICBUF_TYPE_RAW10:
  323. llength = calc_raw_lval(dma.width,IC_MI_DATAMODE_RAW10, ISP_MI_DATA_UNALIGN_MODE);
  324. mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 1);
  325. break;
  326. case ISP_PICBUF_TYPE_RAW12:
  327. llength = calc_raw_lval(dma.width,IC_MI_DATAMODE_RAW12,ISP_MI_DATA_UNALIGN_MODE);
  328. if (id >= ISP_MI_DMA_ID_HDR_L && id <= ISP_MI_DMA_ID_HDR_VS) {
  329. mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 0); //mi dma hdr stitch raw only support raw12 and raw16
  330. } else {
  331. mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 2);
  332. }
  333. break;
  334. case ISP_PICBUF_TYPE_RAW14:
  335. llength = calc_raw_lval(dma.width,IC_MI_DATAMODE_RAW14, ISP_MI_DATA_UNALIGN_MODE);
  336. mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 3);
  337. break;
  338. case ISP_PICBUF_TYPE_RAW16:
  339. llength = calc_raw_lval(dma.width,IC_MI_DATAMODE_RAW16, ISP_MI_DATA_UNALIGN_MODE);
  340. if (id >= ISP_MI_DMA_ID_HDR_L && id <= ISP_MI_DMA_ID_HDR_VS) {
  341. mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 1); //mi dma hdr stitch raw only support raw12 and raw16
  342. } else {
  343. mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, 4);
  344. }
  345. break;
  346. default:
  347. return -EFAULT;
  348. }
  349. llength <<= 4;
  350. mi_set_slice(&path_fmt, dma_path_ctx[id].rd_fmt_align, dma.align);
  351. } else {
  352. getRawBit(dma.type, &path_rd_fmt_bit, &llength); //The old version load all kinds of raw format with raw16 format except raw8
  353. llength = dma.width * llength / 8;
  354. if (id >= ISP_MI_DMA_ID_HDR_L && id <= ISP_MI_DMA_ID_HDR_VS) {
  355. path_rd_fmt_bit = 1;
  356. }
  357. mi_set_slice(&path_fmt, dma_path_ctx[id].rd_raw_bit, path_rd_fmt_bit);
  358. }
  359. /* if (llength != 8)
  360. REG_SET_SLICE(mcm_bus_cfg, MCM_RD_SWAP_RAW, 1);*/
  361. //path_ctrl |= PP_RD_YUV_CFG_UPDATE_MASK; //PP_INIT_OFFSET_EN_MASK | PP_INIT_BASE_EN_MASK |
  362. isp_write_reg(dev, dma_path_ctx[id].pic_start_addr, (MCM_DMA_RAW_PIC_START_AD_MASK & dma.base));
  363. isp_write_reg(dev,dma_path_ctx[id].pic_width, (MCM_DMA_RAW_PIC_WIDTH_MASK & dma.width));
  364. if (dma_path_ctx[id].pic_height) {
  365. isp_write_reg(dev,dma_path_ctx[id].pic_height, dma.height);
  366. }
  367. isp_write_reg(dev, dma_path_ctx[id].pic_llength, (MCM_DMA_RAW_PIC_LLENGTH_MASK & llength));
  368. isp_write_reg(dev,dma_path_ctx[id].pic_size, (MCM_DMA_RAW_PIC_SIZE_MASK & (llength * dma.height)));
  369. isp_write_reg(dev, dma_path_ctx[id].pic_lval, (MCM_DMA_RAW_PIC_WIDTH_MASK & llength));
  370. isp_write_reg(dev, dma_path_ctx[id].fmt_addr, path_fmt);
  371. //isp_write_reg(dev, REG_ADDR(miv2_mcm_bus_cfg), path_bus_cfg);
  372. #ifdef ISP_MI_PP_READ
  373. isp_write_reg(dev, REG_ADDR(mi_pp_dma_y_pic_height), dma.height);
  374. isp_write_reg(dev, REG_ADDR(mi_pp_y_lval_bytes), llength);
  375. // isp_write_reg(dev, 0x55c0, dma.height);
  376. // isp_write_reg(dev, 0x55c4, dma.height);
  377. // isp_write_reg(dev, 0x55c8, dma.height);
  378. // isp_write_reg(dev, 0x55cc, llength);
  379. isp_write_reg(dev, dma_path_ctx[id].mi_imsc_addr, miv2_imsc | PPR_DMA_READY_MASK); /* enabled pp dma */
  380. #else
  381. isp_write_reg(dev, dma_path_ctx[id].mi_imsc_addr, miv2_imsc | 0x01800025); /* enabled jdp, sp2_raw, mp_raw, mcm */
  382. #endif
  383. if(id == ISP_MI_DMA_ID_MCM_PP) {
  384. miv2_ctrl |= (dma_path_ctx[id].path_enable_mask );//| dma_path_ctx[id].path_dma_start_mask);
  385. //path_ctrl |= 0xfa;
  386. mi_set_slice(&path_ctrl, dma_path_ctx[id].rd_cfg_upd, 1);
  387. mi_set_slice(&path_ctrl, dma_path_ctx[id].rd_auto_upd, 1);
  388. REG_SET_SLICE(bus_id, MCM_BUS_SW_EN, 1);
  389. REG_SET_SLICE(bus_id, MCM_RD_ID_EN, 1);
  390. if (dma_path_ctx[id].bus_id_addr) {
  391. isp_write_reg(dev, dma_path_ctx[id].bus_id_addr, bus_id);
  392. }
  393. isp_write_reg(dev,dma_path_ctx[id].ctrl_addr, path_ctrl);
  394. isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl);
  395. #ifdef ISP_MI_HDR
  396. } else {
  397. REG_SET_SLICE(path_fmt, HDR_RD_STR, dma.rd_wr_str);
  398. //config wr str, l,s,vs bit and wr raw aligned same with rd str,l,s,vs bit and wr raw aligned
  399. path_fmt |= ((path_fmt >> HDR_RD_STR_SHIFT) &0x3ff) ;
  400. isp_write_reg(dev, dma_path_ctx[id].fmt_addr, path_fmt);
  401. /*hdr mi dma path enable in mi hdr ctrl register*/
  402. path_ctrl |= (dma_path_ctx[id].path_enable_mask) ; //| dma_path_ctx[id].path_dma_start_mask);
  403. REG_SET_SLICE(path_ctrl, HDR_INIT_OFFSET_EN, 1);
  404. REG_SET_SLICE(path_ctrl, HDR_INIT_BASE_EN, 1);
  405. REG_SET_SLICE(bus_id, HDR_BUS_SW_EN, 1);
  406. REG_SET_SLICE(bus_id, HDR_RD_ID_EN, 1);
  407. if (dma_path_ctx[id].bus_id_addr) {
  408. isp_write_reg(dev, dma_path_ctx[id].bus_id_addr, bus_id);
  409. }
  410. isp_write_reg(dev,dma_path_ctx[id].ctrl_addr, path_ctrl);
  411. #endif
  412. }
  413. return 0;
  414. }
  415. /* only support read raw */
  416. int isp_ioc_start_dma_read(struct isp_ic_dev *dev, void __user *args)
  417. {
  418. start_dma_path_t dma_path;
  419. u32 mi_hdr_fmt;
  420. u32 mi_path_ctrl;
  421. u32 mi_hdr_ret_ctrl;
  422. u32 rd_wr_str;
  423. if (dev == NULL || args == NULL) {
  424. isp_info("input wrong parameter %s\n", __func__);
  425. return -1;
  426. }
  427. isp_info("enter %s\n", __func__);
  428. viv_check_retval(copy_from_user(&dma_path, args, sizeof(dma_path)));
  429. if (dma_path == ISP_MI_DMA_PATH_MCM_PP) {
  430. #ifndef ISP_MI_PP_READ
  431. mi_path_ctrl = isp_read_reg(dev,REG_ADDR(miv2_ctrl));
  432. REG_SET_SLICE(mi_path_ctrl, MCM_RAW_RDMA_START, 1);
  433. isp_write_reg(dev,REG_ADDR(miv2_ctrl), mi_path_ctrl);
  434. #else
  435. mi_path_ctrl = isp_read_reg(dev,REG_ADDR(miv2_ctrl));
  436. REG_SET_SLICE(mi_path_ctrl, PP_DMA_START, 1);
  437. isp_write_reg(dev,REG_ADDR(miv2_ctrl), mi_path_ctrl);
  438. #endif
  439. } else if (dma_path == ISP_MI_DMA_PATH_HDR) {
  440. isp_write_reg(dev, REG_ADDR(isp_mi_hdr_ret_bus_timeo), 0x00000001); //disable bus time out interrupt
  441. mi_hdr_ret_ctrl = isp_read_reg(dev,REG_ADDR(isp_hdr_ret_ctrl));
  442. REG_SET_SLICE(mi_hdr_ret_ctrl, HDR_RT_VSYNC_POL, 1);
  443. REG_SET_SLICE(mi_hdr_ret_ctrl, HDR_RETIMING_ENABLE, 1);
  444. REG_SET_SLICE(mi_hdr_ret_ctrl, DUMP_MODE_EN, 1);
  445. mi_hdr_fmt = isp_read_reg(dev,REG_ADDR(isp_mi_hdr_fmt));
  446. rd_wr_str = (mi_hdr_fmt & HDR_RD_STR_MASK)>>HDR_RD_STR_SHIFT;
  447. if (rd_wr_str == 0) {
  448. REG_SET_SLICE(mi_hdr_ret_ctrl, EXPOSURE_COUNT, 1);
  449. } else if (rd_wr_str == 1|| rd_wr_str == 3) {
  450. REG_SET_SLICE(mi_hdr_ret_ctrl, EXPOSURE_COUNT, 2);
  451. if (rd_wr_str == 3) {
  452. REG_SET_SLICE(mi_hdr_ret_ctrl, L_VS_COMBINING_ENABLE, 1);
  453. }
  454. } else if (rd_wr_str == 2) {
  455. REG_SET_SLICE(mi_hdr_ret_ctrl, EXPOSURE_COUNT, 0);
  456. }
  457. isp_write_reg(dev, REG_ADDR(isp_mi_hdr_dma_start_by_lines), 0x360);//0x10); //the written lines count of the last appearing frame after which start dma read
  458. isp_write_reg(dev,REG_ADDR(isp_hdr_ret_ctrl), mi_hdr_ret_ctrl);
  459. mi_path_ctrl = isp_read_reg(dev,REG_ADDR(isp_mi_hdr_ctrl));
  460. REG_SET_SLICE(mi_path_ctrl, HDR_RD_RAW_CFG_UPDATE, 1);
  461. REG_SET_SLICE(mi_path_ctrl, HDR_RD_RAW_AUTO_UPDATE, 1);
  462. REG_SET_SLICE(mi_path_ctrl, HDR_DMA_START, 1);
  463. isp_write_reg(dev,REG_ADDR(isp_mi_hdr_ctrl), mi_path_ctrl);
  464. }
  465. return 0;
  466. }
  467. #define PATHNUM ISP_MI_PATH_ID_MAX// hw related
  468. // only config write bits, SP2 read bit at 3dnr.c
  469. // read defined is same as write
  470. struct miv2_format_bit {
  471. u32 nyv, nv12;
  472. u32 raw_aligned, yuv_aligned;
  473. u32 raw_bit, yuv_str;
  474. u32 yuv_fmt, yuv_bit, jdp_fmt;
  475. };
  476. static struct miv2_format_bit fmt_bit[PATHNUM] = {
  477. {
  478. .nyv = 3 << 13, .nv12 = 1 << 12,
  479. .raw_aligned = 3 << 10,
  480. .yuv_aligned = 1 << 9,
  481. .raw_bit = 7 << 6,
  482. .yuv_str = 3 << 4,
  483. .yuv_fmt = 3 << 2,
  484. .yuv_bit = 1 << 1,
  485. .jdp_fmt = 1,
  486. },
  487. {
  488. .nyv = 3 << 7,
  489. .nv12 = 1 << 6,
  490. .yuv_aligned = 1 << 5,
  491. .yuv_str = 3 << 3,
  492. .yuv_fmt = 3 << 1,
  493. .yuv_bit = 1,
  494. },
  495. {
  496. .nyv = 3 << 12,
  497. .nv12 = 1 << 11,
  498. .raw_aligned = 3 << 9,
  499. .yuv_aligned = 1 << 8,
  500. .raw_bit = 7 << 5,
  501. .yuv_str = 3 << 3,
  502. .yuv_fmt = 3 << 1,
  503. .yuv_bit = 1,
  504. },
  505. #ifdef ISP_MI_MCM_WR
  506. {
  507. .nyv = 0,
  508. .nv12 = 0,
  509. .raw_aligned = 3 << 14,
  510. .raw_bit = 3 << 4,
  511. .yuv_aligned = 0,
  512. .yuv_str = 0,
  513. .yuv_fmt = 0,
  514. .yuv_bit = 0,
  515. },
  516. {
  517. .nyv = 0,
  518. .nv12 = 0,
  519. .raw_aligned = 3 << 16,
  520. .raw_bit = 3 << 8,
  521. .yuv_aligned = 0,
  522. .yuv_str = 0,
  523. .yuv_fmt = 0,
  524. .yuv_bit = 0,
  525. },
  526. #endif
  527. #ifdef ISP_MI_PP_WRITE
  528. {
  529. .nyv = 3 << 7,
  530. .nv12 = 1 << 6,
  531. .raw_aligned = 3 << 14,
  532. .raw_bit = 7 << 11,
  533. .yuv_aligned = 1 << 5,
  534. .yuv_str = 3 << 3,
  535. .yuv_fmt = 3 << 1,
  536. .yuv_bit = 1,
  537. },
  538. #endif
  539. #ifdef ISP_MI_HDR
  540. {
  541. .nyv = 0,
  542. .nv12 = 0,
  543. .raw_aligned = 3 << 8,
  544. .raw_bit = 3 << 2,
  545. .yuv_aligned = 0,
  546. .yuv_str = 0,
  547. .yuv_fmt = 0,
  548. .yuv_bit = 0,
  549. },
  550. {
  551. .nyv = 0,
  552. .nv12 = 0,
  553. .raw_aligned = 3 << 8,
  554. .raw_bit = 3 << 4,
  555. .yuv_aligned = 0,
  556. .yuv_str = 0,
  557. .yuv_fmt = 0,
  558. .yuv_bit = 0,
  559. },
  560. {
  561. .nyv = 0,
  562. .nv12 = 0,
  563. .raw_aligned = 3 << 8,
  564. .raw_bit = 3 << 6,
  565. .yuv_aligned = 0,
  566. .yuv_str = 0,
  567. .yuv_fmt = 0,
  568. .yuv_bit = 0,
  569. },
  570. #endif
  571. };
  572. static u32 bit_shift(u32 i) {
  573. u32 shift = 0;
  574. while(!(i&1)) {
  575. shift++;
  576. i >>= 1;
  577. }
  578. return shift;
  579. }
  580. void mi_set_slice(u32* val, u32 mask, u32 slice)
  581. {
  582. // mp, sp1, sp2 mcm postpath have different masks.
  583. if (mask) {
  584. *val &= ~mask;
  585. *val |= (slice << bit_shift(mask));
  586. }
  587. }
  588. struct miv2_path_address {
  589. u32 bus_cfg_addr;
  590. u32 bus_id_addr;
  591. u32 bus_timeo_addr; //axi bus time out waiting ctrl register
  592. u32 path_ctrl_addr;
  593. u32 format_addr;
  594. u32 y_length_addr;
  595. u32 raw_llength_addr;
  596. u32 raw_pic_width_addr;
  597. u32 raw_pic_height_addr;
  598. u32 raw_pic_size_addr;
  599. u32 ycbcr_enable_bit;
  600. u32 raw_enable_bit;
  601. u32 format_conv_ctrl;
  602. u32 wr_raw_swap_bit;
  603. };
  604. static void disable_bus_timeo_intr(struct isp_ic_dev *dev, u32 bus_addr)
  605. {
  606. u32 val;
  607. isp_info("%s bus timeo interrupt register addr 0x%08x\n", __func__, bus_addr);
  608. val = isp_read_reg(dev, bus_addr);
  609. REG_SET_SLICE(val, MP_BUS_TIMEO_INTERRUPT_DISABLE, 1);
  610. isp_write_reg(dev, bus_addr, val);
  611. }
  612. static void set_qos(struct isp_ic_dev *dev)
  613. {
  614. isp_info("isp %s enter\n", __func__);
  615. isp_write_reg(dev, 0x1308, MI_QOS);
  616. isp_write_reg(dev, 0x130C, MI_QOS2);
  617. isp_info("isp %s exit\n", __func__);
  618. }
  619. static void set_data_path(int id, struct isp_mi_data_path_context *path,
  620. struct isp_ic_dev *dev)
  621. {
  622. u32 bus_cfg, bus_id;
  623. u32 format;
  624. u32 miv2_ctrl;
  625. u32 path_ctrl;
  626. u32 lval;
  627. u32 acq_proc;
  628. u32 mcm_bus_cfg = isp_read_reg(dev, REG_ADDR(miv2_mcm_bus_cfg));
  629. u32 conv_format_ctrl = 0;
  630. u32 y_length_addr;
  631. u32 y_llength = 0;
  632. #ifdef ISP_MI_PP_WRITE
  633. u32 isp_ctrl;
  634. #endif
  635. // please take care the register order
  636. #if 0
  637. struct miv2_path_address path_list[PATHNUM] = {
  638. { 0x1318, 0x131c, 0x1310, 0x1314, 0x1330, 0x13a0, 0x13a4, 0x13a8, 0x13ac, 1, 0x0c6c },
  639. { 0x1434, 0x1438, 0x142c, 0x1430, 0x144c, 0, 0, 0, 8, 0x106c },
  640. { 0x14ec, 0x14f0, 0x14e4, 0x14e8, 0x1504, 0x1574, 0x1578, 0x157c, 0x1580, 0x10, 0x116c },
  641. };
  642. #else
  643. //id 0 is mp path;id 1 is sp path;id 2 is sp2 path;
  644. //id 3 is post process path write;
  645. struct miv2_path_address path_list[PATHNUM] = {
  646. {
  647. REG_ADDR(miv2_mp_bus_cfg), REG_ADDR(miv2_mp_bus_id), REG_ADDR(miv2_mp_bus_timeo), REG_ADDR(miv2_mp_ctrl),
  648. REG_ADDR(miv2_mp_fmt), REG_ADDR(miv2_mp_y_llength), REG_ADDR(miv2_mp_raw_llength),
  649. REG_ADDR(miv2_mp_raw_pic_width), REG_ADDR(miv2_mp_raw_pic_height), REG_ADDR(miv2_mp_raw_pic_size),
  650. MP_YCBCR_PATH_ENABLE_MASK, MP_RAW_PATH_ENABLE_MASK, REG_ADDR(mrsz_format_conv_ctrl), MP_WR_SWAP_RAW_MASK
  651. },
  652. {
  653. REG_ADDR(miv2_sp1_bus_cfg), REG_ADDR(miv2_sp1_bus_id), REG_ADDR(miv2_sp1_bus_timeo), REG_ADDR(miv2_sp1_ctrl),
  654. REG_ADDR(miv2_sp1_fmt), REG_ADDR(miv2_sp1_y_llength), 0,
  655. 0, 0, 0,
  656. SP1_YCBCR_PATH_ENABLE_MASK, 0, REG_ADDR(srsz_phase_format_conv_ctr), 0,
  657. },
  658. {
  659. REG_ADDR(miv2_sp2_bus_cfg), REG_ADDR(miv2_sp2_bus_id), REG_ADDR(miv2_sp2_bus_timeo), REG_ADDR(miv2_sp2_ctrl),
  660. REG_ADDR(miv2_sp2_fmt), REG_ADDR(miv2_sp2_y_llength), REG_ADDR(miv2_sp2_raw_llength),
  661. REG_ADDR(miv2_sp2_raw_pic_width), REG_ADDR(miv2_sp2_raw_pic_height), REG_ADDR(miv2_sp2_raw_pic_size),
  662. SP2_YCBCR_PATH_ENABLE_MASK, SP2_RAW_PATH_ENABLE_MASK, REG_ADDR(srsz2_phase_format_conv_ctr),
  663. SP2_WR_SWAP_RAW_MASK
  664. },
  665. #ifdef ISP_MI_MCM_WR
  666. {
  667. REG_ADDR(miv2_mcm_bus_cfg), REG_ADDR(miv2_mcm_bus_id), REG_ADDR(miv2_mcm_bus_timeo), REG_ADDR(miv2_mcm_ctrl),
  668. REG_ADDR(miv2_mcm_fmt), 0, REG_ADDR(miv2_mcm_raw0_llength),
  669. REG_ADDR(miv2_mcm_raw0_pic_width), REG_ADDR(miv2_mcm_raw0_pic_height), REG_ADDR(miv2_mcm_raw0_pic_size),
  670. 0, MCM_RAW0_PATH_ENABLE_MASK, 0, MCM_WR0_SWAP_RAW_MASK
  671. },
  672. {
  673. REG_ADDR(miv2_mcm_bus_cfg), REG_ADDR(miv2_mcm_bus_id), REG_ADDR(miv2_mcm_bus_timeo), REG_ADDR(miv2_mcm_ctrl),
  674. REG_ADDR(miv2_mcm_fmt), 0, REG_ADDR(miv2_mcm_raw1_llength),
  675. REG_ADDR(miv2_mcm_raw1_pic_width), REG_ADDR(miv2_mcm_raw1_pic_height), REG_ADDR(miv2_mcm_raw1_pic_size),
  676. 0, MCM_RAW1_PATH_ENABLE_MASK, 0, MCM_WR1_SWAP_RAW_MASK
  677. },
  678. #endif
  679. {
  680. REG_ADDR(isp_mi_pp_data_swap), REG_ADDR(miv2_sp1_bus_id), REG_ADDR(miv2_sp1_bus_timeo), REG_ADDR(isp_mi_pp_ctrl),
  681. REG_ADDR(isp_mi_pp_fmt), REG_ADDR(isp_mi_pp_y_llength), REG_ADDR(mi_pp_y_lval_bytes),
  682. REG_ADDR(isp_mi_pp_y_pic_width), REG_ADDR(isp_mi_pp_y_pic_height), REG_ADDR(isp_mi_pp_y_pic_size),
  683. PP_WRITE_PATH_ENABLE_MASK, PP_WRITE_PATH_ENABLE_MASK, 0,PP_WR_SWAP_Y_MASK
  684. },
  685. #ifdef ISP_MI_HDR
  686. {
  687. REG_ADDR(isp_mi_hdr_ret_bus_cfg), REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(isp_mi_hdr_ret_bus_timeo),
  688. REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_l_llength),
  689. REG_ADDR(isp_mi_hdr_pic_width), REG_ADDR(isp_mi_hdr_pic_height), REG_ADDR(isp_mi_hdr_l_size_init),
  690. 0, HDR_WR_ENABLE_MASK, 0, HDR_WR_SWAP_RAW_MASK
  691. },
  692. {
  693. REG_ADDR(isp_mi_hdr_ret_bus_cfg), REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(isp_mi_hdr_ret_bus_timeo),
  694. REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_s_llength),
  695. REG_ADDR(isp_mi_hdr_pic_width), REG_ADDR(isp_mi_hdr_pic_height), REG_ADDR(isp_mi_hdr_s_size_init),
  696. 0, HDR_WR_ENABLE_MASK, 0, HDR_WR_SWAP_RAW_MASK
  697. },
  698. {
  699. REG_ADDR(isp_mi_hdr_ret_bus_cfg), REG_ADDR(isp_mi_hdr_ret_bus_id), REG_ADDR(isp_mi_hdr_ret_bus_timeo),
  700. REG_ADDR(isp_mi_hdr_ctrl), REG_ADDR(isp_mi_hdr_fmt), 0, REG_ADDR(isp_mi_hdr_vs_llength),
  701. REG_ADDR(isp_mi_hdr_pic_width), REG_ADDR(isp_mi_hdr_pic_height), REG_ADDR(isp_mi_hdr_vs_size_init),
  702. 0, HDR_WR_ENABLE_MASK, 0, HDR_WR_SWAP_RAW_MASK
  703. },
  704. #endif
  705. };
  706. #endif
  707. if (!path->enable) {
  708. disable_bus_timeo_intr(dev, path_list[id].bus_timeo_addr);
  709. return;
  710. }
  711. if (path->hscale || path->vscale || dev->is.enable) {
  712. if (id <= ISP_MI_PATH_SP2_BP)
  713. isp_set_scaling(id, dev, dev->is.enable, dev->crop[id].enabled);
  714. else
  715. isp_set_scaling(id, dev, dev->is.enable, 0);
  716. }
  717. miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl));
  718. if(path_list[id].bus_cfg_addr)
  719. bus_cfg = isp_read_reg(dev, path_list[id].bus_cfg_addr);
  720. format = isp_read_reg(dev, path_list[id].format_addr);
  721. if (path_list[id].format_conv_ctrl) {
  722. conv_format_ctrl = isp_read_reg(dev, path_list[id].format_conv_ctrl);
  723. }
  724. isp_info("mi %s id %d fmt_bit[id].raw_bit 0x%08x miv2_ctrl 0x%08x ", __func__, id, path_list[id].raw_enable_bit, miv2_ctrl);
  725. path_ctrl = isp_read_reg(dev, path_list[id].path_ctrl_addr);
  726. switch (path->out_mode) {
  727. case IC_MI_DATAMODE_YUV444:
  728. mi_set_slice(&format, fmt_bit[id].yuv_fmt, 2);
  729. miv2_ctrl |= path_list[id].ycbcr_enable_bit;
  730. REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_OUTPUT, 3);
  731. REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_INPUT, 2);
  732. break;
  733. case IC_MI_DATAMODE_YUV422:
  734. mi_set_slice(&format, fmt_bit[id].yuv_fmt, 1);
  735. miv2_ctrl |= path_list[id].ycbcr_enable_bit;
  736. break;
  737. case IC_MI_DATAMODE_YUV420:
  738. mi_set_slice(&format, fmt_bit[id].yuv_fmt, 0);
  739. miv2_ctrl |= path_list[id].ycbcr_enable_bit;
  740. break;
  741. case IC_MI_DATAMODE_YUV400:
  742. case IC_MI_DATAMODE_JPEG:
  743. mi_set_slice(&format, fmt_bit[id].jdp_fmt, 1);
  744. REG_SET_SLICE(miv2_ctrl, MP_JDP_PATH_ENABLE, 1);
  745. break;
  746. case IC_MI_DATAMODE_RAW8:
  747. mi_set_slice(&format, fmt_bit[id].raw_bit, 0);
  748. miv2_ctrl |= path_list[id].raw_enable_bit;
  749. break;
  750. case IC_MI_DATAMODE_RAW10:
  751. mi_set_slice(&format, fmt_bit[id].raw_bit, 1);
  752. miv2_ctrl |= path_list[id].raw_enable_bit;
  753. mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, path->raw_is_big_endian);
  754. //if (id == ISP_MI_PATH_PP) {
  755. // mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, 0); // RY PP READ didn't cfg raw_swap_bit(pp_rd_swap_y) = 0(default)
  756. //} else {
  757. // mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, 1); // MP SP1 SP2 swap words
  758. //}
  759. break;
  760. case IC_MI_DATAMODE_RAW12:
  761. #ifdef ISP_MI_HDR
  762. if (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS) {
  763. mi_set_slice(&format, fmt_bit[id].raw_bit, 0);
  764. path_ctrl |= path_list[id].raw_enable_bit;
  765. //mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, 0);
  766. }
  767. #endif
  768. mi_set_slice(&format, fmt_bit[id].raw_bit, 2);
  769. miv2_ctrl |= path_list[id].raw_enable_bit;
  770. mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, path->raw_is_big_endian);
  771. //if (id == ISP_MI_PATH_PP) {
  772. // mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, 0); // RY PP READ didn't cfg raw_swap_bit(pp_rd_swap_y) = 0(default)
  773. //} else {
  774. // mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, 1); // MP SP1 SP2 swap words
  775. //}
  776. break;
  777. case IC_MI_DATAMODE_RAW14:
  778. mi_set_slice(&format, fmt_bit[id].raw_bit, 3);
  779. miv2_ctrl |= path_list[id].raw_enable_bit;
  780. mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, path->raw_is_big_endian);
  781. break;
  782. case IC_MI_DATAMODE_RAW16:
  783. #ifdef ISP_MI_HDR
  784. if (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS) {
  785. mi_set_slice(&format, fmt_bit[id].raw_bit, 1);
  786. path_ctrl |= path_list[id].raw_enable_bit;
  787. //mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, path->raw_is_big_endian);
  788. }
  789. #endif
  790. if (id <= ISP_MI_PATH_PP) {
  791. mi_set_slice(&format, fmt_bit[id].raw_bit, 4);
  792. miv2_ctrl |= path_list[id].raw_enable_bit;
  793. mi_set_slice(&bus_cfg, path_list[id].wr_raw_swap_bit, path->raw_is_big_endian);
  794. }
  795. break;
  796. case IC_MI_DATAMODE_RGB888:
  797. mi_set_slice(&format, fmt_bit[id].yuv_fmt, 2);
  798. REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_OUTPUT, 6);
  799. REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_INPUT, 2);
  800. miv2_ctrl |= path_list[id].ycbcr_enable_bit;
  801. break;
  802. default:
  803. isp_err("mi %s unsupport format: %d", __func__, path->out_mode);
  804. return;
  805. }
  806. switch (path->data_layout) {
  807. case IC_MI_DATASTORAGE_PLANAR:
  808. mi_set_slice(&format, fmt_bit[id].yuv_str, 2);
  809. break;
  810. case IC_MI_DATASTORAGE_SEMIPLANAR:
  811. mi_set_slice(&format, fmt_bit[id].yuv_str, 0);
  812. break;
  813. case IC_MI_DATASTORAGE_INTERLEAVED:
  814. mi_set_slice(&format, fmt_bit[id].yuv_str, 1);
  815. break;
  816. default:
  817. break;
  818. }
  819. mi_set_slice(&format, fmt_bit[id].yuv_bit, path->yuv_bit);
  820. if(path->yuv_bit){
  821. if(path->data_alignMode){
  822. mi_set_slice(&format, fmt_bit[id].yuv_aligned, 1);
  823. }else{
  824. mi_set_slice(&format, fmt_bit[id].yuv_aligned, 0);
  825. }
  826. REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_10_ENABLE, 1);
  827. REG_SET_SLICE(conv_format_ctrl, MRV_MRSZ_COVERT_10_METHOD, 0);
  828. }
  829. mi_set_slice(&format, fmt_bit[id].raw_aligned, path->data_alignMode);
  830. if (id == ISP_MI_PATH_MP) {
  831. REG_SET_SLICE(bus_cfg, MP_WR_BURST_LEN, dev->mi.burst_len);
  832. } else if (id == ISP_MI_PATH_SP) {
  833. REG_SET_SLICE(bus_cfg, SP1_WR_BURST_LEN, dev->mi.burst_len);
  834. } else if (id == ISP_MI_PATH_SP2_BP) {
  835. REG_SET_SLICE(bus_cfg, SP2_WR_BURST_LEN, dev->mi.burst_len);
  836. }
  837. REG_SET_SLICE(mcm_bus_cfg, MCM_WR_BURST_LEN, dev->mi.burst_len);
  838. if(path->yuv_bit){//
  839. if(path->data_alignMode){//aligned mode
  840. lval = (path->out_width + 12 - 1)/12;
  841. //printf("zw debug lval = 0x%x\n",lval);
  842. }else{ //unaligned mode
  843. lval = (path->out_width * 10 + 127)/128;
  844. }
  845. y_llength =lval<<4;
  846. //printf("zw debug y_llength = 0x%x\n",y_llength);
  847. }else{ //8bit output
  848. y_llength = ALIGN_16BYTE(path->out_width);
  849. }
  850. y_length_addr = path_list[id].y_length_addr;
  851. if (y_length_addr) {
  852. isp_write_reg(dev, y_length_addr, y_llength);
  853. isp_write_reg(dev, y_length_addr + 4, path->out_width);
  854. isp_write_reg(dev, y_length_addr + 8, path->out_height);
  855. isp_write_reg(dev, y_length_addr + 12,
  856. y_llength * path->out_height);
  857. }
  858. // aev2, 3dnr
  859. if (id == ISP_MI_PATH_MP) {
  860. if (dev->exp2.enable) {
  861. REG_SET_SLICE(miv2_ctrl, MP_JDP_PATH_ENABLE, 1);
  862. #ifdef ISP_AEV2_V2
  863. REG_SET_SLICE(format, MP_WR_JDP_DP_BIT, 1);
  864. #endif
  865. } else {
  866. REG_SET_SLICE(miv2_ctrl, MP_JDP_PATH_ENABLE, 0);
  867. }
  868. }
  869. if ((id == ISP_MI_PATH_MP && (miv2_ctrl & MP_RAW_PATH_ENABLE_MASK)) ||
  870. (id == ISP_MI_PATH_SP2_BP && (miv2_ctrl & SP2_RAW_PATH_ENABLE_MASK))
  871. #ifdef ISP_MI_MCM_WR
  872. || (id == ISP_MI_MCM_WR0 && (miv2_ctrl & MCM_RAW0_PATH_ENABLE_MASK)) ||
  873. (id == ISP_MI_MCM_WR1 && (miv2_ctrl & MCM_RAW1_PATH_ENABLE_MASK))
  874. #endif
  875. #ifdef ISP_MI_PP_WRITE
  876. || (id == ISP_MI_PATH_PP && ((path->out_mode == IC_MI_DATAMODE_RAW8) ||
  877. (path->out_mode == IC_MI_DATAMODE_RAW10) || (path->out_mode == IC_MI_DATAMODE_RAW12) ||
  878. (path->out_mode == IC_MI_DATAMODE_RAW14) || (path->out_mode == IC_MI_DATAMODE_RAW16)))
  879. #endif
  880. #ifdef ISP_MI_HDR
  881. || (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS)
  882. #endif
  883. ) {
  884. lval =
  885. calc_raw_lval(path->out_width, path->out_mode,
  886. path->data_alignMode);
  887. y_llength = lval <<4;
  888. isp_write_reg(dev, path_list[id].raw_llength_addr, y_llength);
  889. isp_write_reg(dev, path_list[id].raw_pic_width_addr, path->out_width);
  890. isp_write_reg(dev, path_list[id].raw_pic_height_addr, path->out_height);
  891. isp_write_reg(dev, path_list[id].raw_pic_size_addr, path->out_height * y_llength );
  892. #ifdef ISP_MI_MCM_WR
  893. if (id == ISP_MI_MCM_WR0 || id == ISP_MI_MCM_WR1) {
  894. isp_write_reg(dev, REG_ADDR(miv2_mcm_raw0_lval_bytes), y_llength);
  895. }
  896. #endif
  897. #ifdef ISP_MI_PP_WRITE
  898. //ppw line entry mode, llength need to align with 256.
  899. //llength is line length, lval is line availble data.
  900. #if 1/*should check by VV, if align with 256 is needed*/
  901. uint32_t line_num = isp_read_reg(dev, REG_ADDR(mi_sp1_ppw_ycbcr_entry_line_num));
  902. /*TODO shenweiyi to enable */
  903. // if (line_num != 0) {
  904. // y_llength = y_llength & 0xff ? (y_llength & 0xffffff00 + 0x100):y_llength;
  905. // }
  906. isp_info("%s:line_num = %d y_llength = 0x%x\n", __func__, line_num, y_llength);
  907. isp_write_reg(dev, REG_ADDR(isp_mi_pp_y_llength), y_llength);
  908. isp_write_reg(dev, path_list[id].raw_pic_size_addr, path->out_height * y_llength );
  909. #else
  910. if (id == ISP_MI_PATH_PP) {
  911. uint32_t line_num = isp_read_reg(dev, REG_ADDR(mi_sp1_ppw_ycbcr_entry_line_num));
  912. if (line_num != 0) {
  913. y_llength = (y_llength & 0xff) ? ((y_llength + 0xff) &(~0xff)):y_llength;
  914. }
  915. isp_write_reg(dev, REG_ADDR(isp_mi_pp_y_llength), y_llength);
  916. isp_write_reg(dev, path_list[id].raw_pic_size_addr, path->out_height * y_llength );
  917. }
  918. #endif
  919. #endif
  920. #if defined(ISP_MI_HDR)
  921. if (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS)
  922. isp_write_reg(dev, path_list[id].raw_llength_addr+4, y_llength);
  923. #endif
  924. }
  925. #ifdef ISP_MI_HDR
  926. if (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS) {
  927. REG_SET_SLICE(path_ctrl, HDR_MI_CFG_UPD, 1);
  928. REG_SET_SLICE(path_ctrl, HDR_AUTO_UPDATE, 1);
  929. path_ctrl |= (HDR_INIT_OFFSET_EN_MASK | HDR_INIT_BASE_EN_MASK);
  930. }
  931. #endif
  932. if (id <= ISP_MI_PATH_PP) {
  933. REG_SET_SLICE(path_ctrl, MP_MI_CFG_UPD, 1);
  934. REG_SET_SLICE(path_ctrl, MP_AUTO_UPDATE, 1);
  935. //path_ctrl |= 0x05;
  936. path_ctrl |= (MP_INIT_BASE_EN_MASK | MP_INIT_OFFSET_EN_MASK);
  937. }
  938. #ifdef ISP_MI_MCM_WR
  939. if (id <= ISP_MI_MCM_WR1 && id >= ISP_MI_MCM_WR0) {
  940. REG_SET_SLICE(path_ctrl, MCM_WR_CFG_UPD, 1);
  941. REG_SET_SLICE(path_ctrl, MCM_WR_AUTO_UPDATE, 1);
  942. //path_ctrl |= 0x05;
  943. path_ctrl |= (MCM_INIT_BASE_EN_MASK | MCM_INIT_OFFSET_EN_MASK);
  944. }
  945. #endif
  946. isp_info("%s:path_ctrl 0x%08x\n", __func__, path_ctrl);
  947. acq_proc = isp_read_reg(dev, REG_ADDR(isp_acq_prop));
  948. isp_write_reg(dev, REG_ADDR(isp_acq_prop),
  949. acq_proc & ~MRV_ISP_LATENCY_FIFO_SELECTION_MASK);
  950. bus_id = isp_read_reg(dev, path_list[id].bus_id_addr);
  951. if (id == ISP_MI_PATH_SP) {
  952. bus_id <<= 4;
  953. }
  954. bus_id |= MP_WR_ID_EN_MASK;
  955. if (id == ISP_MI_PATH_SP2_BP) {
  956. bus_id |= SP2_BUS_SW_EN_MASK;
  957. // REG_SET_SLICE(bus_cfg, SP2_WR_SWAP_Y, 1);
  958. #ifdef ISP_MI_HDR
  959. } else if (id >= ISP_MI_HDR_L && id <= ISP_MI_HDR_VS ) {
  960. bus_id |= HDR_BUS_SW_EN_MASK;
  961. #endif
  962. } else {
  963. bus_id |= MP_BUS_SW_EN_MASK;
  964. }
  965. if (path_list[id].bus_id_addr)
  966. isp_write_reg(dev, path_list[id].bus_id_addr, bus_id);
  967. if (path_list[id].bus_cfg_addr)
  968. isp_write_reg(dev, path_list[id].bus_cfg_addr, bus_cfg);
  969. isp_write_reg(dev, REG_ADDR(miv2_mcm_bus_cfg), mcm_bus_cfg);
  970. #ifdef ISP_MI_PP_WRITE
  971. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  972. if (id == ISP_MI_PATH_PP && ((path->out_mode == IC_MI_DATAMODE_RAW8) ||
  973. (path->out_mode == IC_MI_DATAMODE_RAW10) || (path->out_mode == IC_MI_DATAMODE_RAW12) ||
  974. (path->out_mode == IC_MI_DATAMODE_RAW14) || (path->out_mode == IC_MI_DATAMODE_RAW16))) { //pp path output raw
  975. format |= PP_WR_RAW_SEL_MASK;
  976. REG_SET_SLICE(format, PP_WR_RAW_SEL, 1);
  977. REG_SET_SLICE(isp_ctrl, PP_WRITE_SEL, 0);
  978. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  979. } else {
  980. REG_SET_SLICE(format, PP_WR_RAW_SEL, 0);
  981. REG_SET_SLICE(isp_ctrl, PP_WRITE_SEL, 1);
  982. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  983. }
  984. #endif
  985. isp_write_reg(dev, path_list[id].format_addr, format);
  986. isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl);
  987. isp_write_reg(dev, path_list[id].path_ctrl_addr, path_ctrl);
  988. /*config qos for isp*/
  989. set_qos(dev);
  990. if (path_list[id].format_conv_ctrl)
  991. isp_write_reg(dev, path_list[id].format_conv_ctrl, conv_format_ctrl);
  992. }
  993. int isp_mi_start(struct isp_ic_dev *dev)
  994. {
  995. int i;
  996. struct isp_mi_context mi = *(&dev->mi);
  997. u32 imsc, miv2_mcm_bus_id;
  998. isp_info("enter %s\n", __func__);
  999. miv2_mcm_bus_id = isp_read_reg(dev, REG_ADDR(miv2_mcm_bus_id));
  1000. miv2_mcm_bus_id |= MCM_BUS_SW_EN_MASK;
  1001. isp_write_reg(dev, REG_ADDR(miv2_mcm_bus_id), miv2_mcm_bus_id);
  1002. for (i = 0; i < ISP_MI_PATH_ID_MAX; i++) {
  1003. set_data_path(i, &mi.path[i], dev);
  1004. }
  1005. uint32_t line_num = isp_read_reg(dev, REG_ADDR(mi_sp1_ppw_ycbcr_entry_line_num));
  1006. imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc));
  1007. if (line_num == 0) {
  1008. isp_write_reg(dev, REG_ADDR(miv2_imsc),
  1009. imsc | (MP_YCBCR_FRAME_END_MASK | MP_RAW_FRAME_END_MASK |
  1010. WRAP_MP_Y_MASK | WRAP_MP_CB_MASK | WRAP_MP_CR_MASK |
  1011. WRAP_MP_RAW_MASK | WRAP_MP_JDP_MASK | MCM_RAW0_FRAME_END_MASK |
  1012. SP1_YCBCR_FRAME_END_MASK | WRAP_SP1_Y_MASK |MCM_RAW1_FRAME_END_MASK|
  1013. WRAP_SP1_CB_MASK | WRAP_SP1_CR_MASK |
  1014. SP2_YCBCR_FRAME_END_MASK | WRAP_SP2_Y_MASK |
  1015. WRAP_SP2_CB_MASK | WRAP_SP2_CR_MASK |
  1016. SP2_RAW_FRAME_END_MASK | MP_JDP_FRAME_END_MASK));
  1017. } else {
  1018. isp_write_reg(dev, REG_ADDR(miv2_imsc),
  1019. imsc | (MP_YCBCR_FRAME_END_MASK | MP_RAW_FRAME_END_MASK |
  1020. WRAP_MP_Y_MASK | WRAP_MP_CB_MASK | WRAP_MP_CR_MASK |
  1021. WRAP_MP_RAW_MASK | WRAP_MP_JDP_MASK | MCM_RAW0_FRAME_END_MASK |
  1022. MCM_RAW1_FRAME_END_MASK|
  1023. SP2_YCBCR_FRAME_END_MASK | WRAP_SP2_Y_MASK |
  1024. WRAP_SP2_CB_MASK | WRAP_SP2_CR_MASK |
  1025. SP2_RAW_FRAME_END_MASK | MP_JDP_FRAME_END_MASK));
  1026. }
  1027. //isp_write_reg(dev, REG_ADDR(miv2_imsc1), 0x7ffffff);
  1028. isp_write_reg(dev, REG_ADDR(miv2_imsc1), (MI_MP_BUS_TIMEO_MASK | MI_SP1_BUS_TIMEO_MASK | MI_SP2_BUS_TIMEO_MASK |
  1029. MI_MP_BUS_BUSERR_MASK | MI_SP1_BUS_BUSERR_MASK | MI_SP2_BUS_BUSERR_MASK));
  1030. #ifdef ISP_MI_PP_WRITE
  1031. imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc2));
  1032. if (line_num == 0) {
  1033. isp_write_reg(dev, REG_ADDR(miv2_imsc2),
  1034. imsc | ( PPW_U_BUF_FULL_MASK | PPW_Y_BUF_FULL_MASK |
  1035. PPW_V_BUF_FULL_MASK | PPR_Y_BUF_FULL_MASK | SP2_RAW2_W_BUF_FULL_MASK |
  1036. SP2_RAW2_R_BUF_FULL_MASK | HDR_W_BUF_FULL_MASK | HDR_R_BUF_FULL_MASK |
  1037. WRAP_SP2_RAW_MASK | WRAP_PPW_CR_MASK | WRAP_PPW_CB_MASK | //WRAP_PPW_Y_MASK |
  1038. SP2_RAW2_FRAME_END_MASK | PPW_FRAME_END_MASK | HDR_VS_DMA_READY_MASK |
  1039. HDR_S_DMA_READY_MASK | HDR_L_DMA_READY_MASK | HDR_L_DMA_READY_MASK |
  1040. WRAP_HDR_VS_MASK | WRAP_HDR_S_MASK | WRAP_HDR_L_MASK | HDR_VS_FRAME_END_MASK |
  1041. HDR_S_FRAME_END_MASK | HDR_L_FRAME_END_MASK | MI_RT_BUS_BUSERR_MASK |
  1042. MI_RT_BUS_TIMEO_MASK));
  1043. } else {
  1044. isp_write_reg(dev, REG_ADDR(miv2_imsc2),
  1045. imsc | (SP2_RAW2_W_BUF_FULL_MASK |
  1046. SP2_RAW2_R_BUF_FULL_MASK | HDR_W_BUF_FULL_MASK | HDR_R_BUF_FULL_MASK |
  1047. WRAP_SP2_RAW_MASK |PPW_FRAME_END_MASK|
  1048. SP2_RAW2_FRAME_END_MASK | HDR_VS_DMA_READY_MASK |
  1049. HDR_S_DMA_READY_MASK | HDR_L_DMA_READY_MASK | HDR_L_DMA_READY_MASK |
  1050. WRAP_HDR_VS_MASK | WRAP_HDR_S_MASK | WRAP_HDR_L_MASK | HDR_VS_FRAME_END_MASK |
  1051. HDR_S_FRAME_END_MASK | HDR_L_FRAME_END_MASK | MI_RT_BUS_BUSERR_MASK |
  1052. MI_RT_BUS_TIMEO_MASK));
  1053. }
  1054. #endif
  1055. isp_write_reg(dev, REG_ADDR(miv2_imsc3), 0x3f);
  1056. return 0;
  1057. }
  1058. int isp_mi_stop(struct isp_ic_dev *dev)
  1059. {
  1060. isp_info("enter %s\n", __func__);
  1061. #ifdef ISP_MI_PP_WRITE
  1062. isp_write_reg(dev, REG_ADDR(miv2_imsc2), 0);
  1063. #endif
  1064. isp_write_reg(dev, REG_ADDR(miv2_imsc3), 0);
  1065. isp_write_reg(dev, REG_ADDR(miv2_imsc), 0);
  1066. isp_write_reg(dev, REG_ADDR(miv2_imsc1), 0);
  1067. isp_write_reg(dev, REG_ADDR(miv2_ctrl), 0UL);
  1068. return 0;
  1069. }
  1070. u32 isp_read_mi_irq(struct isp_ic_dev *dev)
  1071. {
  1072. return isp_read_reg(dev, REG_ADDR(miv2_mis));
  1073. }
  1074. void isp_reset_mi_irq(struct isp_ic_dev *dev, u32 icr)
  1075. {
  1076. isp_write_reg(dev, REG_ADDR(miv2_icr), icr);
  1077. }
  1078. int isp_set_bp_buffer(struct isp_ic_dev *dev, struct isp_bp_buffer_context *buf)
  1079. {
  1080. return 0;
  1081. }
  1082. #ifdef ISP_MI_PP_WRITE
  1083. int isp_set_ppw_line_num(struct isp_ic_dev *dev)
  1084. {
  1085. if (dev == NULL) {
  1086. isp_err("Wrong input %s\n", __func__);
  1087. return -1;
  1088. }
  1089. isp_info("enter %s\n", __func__);
  1090. isp_write_reg(dev, REG_ADDR(mi_sp1_ppw_ycbcr_entry_line_num), dev->pp_write.entry_line_num);
  1091. isp_info("exit %s\n", __func__);
  1092. return 0;
  1093. }
  1094. int isp_get_ppw_pic_cnt(struct isp_ic_dev *dev, u16* pic_cnt)
  1095. {
  1096. if (dev == NULL) {
  1097. isp_err("Wrong input %s\n", __func__);
  1098. return -1;
  1099. }
  1100. isp_info("enter %s\n", __func__);
  1101. *pic_cnt = isp_read_reg(dev, REG_ADDR(mi_sp1_ppw_ycbcr_entry_pic_cnt));
  1102. isp_info("exit %s\n", __func__);
  1103. return 0;
  1104. }
  1105. #endif
  1106. #ifdef ISP_MI_PP_READ
  1107. int isp_cfg_pp_dma_line_entry(struct isp_ic_dev *dev)
  1108. {
  1109. pp_dma_line_entry_t* pp_dam_line_entry = &dev->pp_dma_line_entry;
  1110. if (dev == NULL) {
  1111. isp_err("Wrong input %s\n", __func__);
  1112. return -1;
  1113. }
  1114. isp_info("enter %s\n", __func__);
  1115. isp_write_reg(dev, REG_ADDR(mi_pp_dma_y_entry_line_num), pp_dam_line_entry->entry_line_num);
  1116. isp_write_reg(dev, REG_ADDR(mi_pp_dma_y_buf_line_num), pp_dam_line_entry->buf_line_num);
  1117. isp_info("exit %s\n", __func__);
  1118. return 0;
  1119. }
  1120. #endif
  1121. #endif