isp_ioctl.c 116 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. /* process public and sample isp command. for complex modules, need new files.*/
  54. #include "mrv_all_bits.h"
  55. #include "isp_ioctl.h"
  56. #include "isp_types.h"
  57. #include "isp_wdr.h"
  58. #include <linux/dma-mapping.h>
  59. #include <linux/dma-buf.h>
  60. #ifdef __KERNEL__
  61. #include <linux/regmap.h>
  62. #include <linux/of_reserved_mem.h>
  63. #endif
  64. #include "isp_ioctl.h"
  65. volatile MrvAllRegister_t *all_regs = NULL;
  66. #ifndef __KERNEL__
  67. #define ISP_REG_SIZE 0x10000
  68. static HalHandle_t hal_handle;
  69. void isp_ic_set_hal(HalHandle_t hal)
  70. {
  71. hal_handle = hal;
  72. }
  73. void isp_write_reg(struct isp_ic_dev *dev, u32 offset, u32 val)
  74. {
  75. //isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);
  76. if (offset >= ISP_REG_SIZE)
  77. return;
  78. HalWriteReg(hal_handle, offset, val);
  79. }
  80. u32 isp_read_reg(struct isp_ic_dev *dev, u32 offset)
  81. {
  82. if (offset >= ISP_REG_SIZE)
  83. return 0;
  84. return HalReadReg(hal_handle, offset);
  85. }
  86. long isp_copy_data(void *dst, void *src, int size)
  87. {
  88. if (dst != src)
  89. memcpy(dst, src, size);
  90. return 0;
  91. }
  92. #else
  93. void isp_write_reg(struct isp_ic_dev *dev, u32 offset, u32 val)
  94. {
  95. // isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);
  96. if (offset >= ISP_REG_SIZE)
  97. return;
  98. __raw_writel(val, dev->base + offset);
  99. /*isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);*/
  100. }
  101. u32 isp_read_reg(struct isp_ic_dev *dev, u32 offset)
  102. {
  103. u32 val = 0;
  104. if (offset >= ISP_REG_SIZE)
  105. return 0;
  106. val = __raw_readl(dev->base + offset);
  107. /*isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);*/
  108. return val;
  109. }
  110. #endif
  111. int isp_reset(struct isp_ic_dev *dev)
  112. {
  113. isp_info("enter %s\n", __func__);
  114. isp_write_reg(dev, REG_ADDR(vi_ircl), 0xFFFFFFBF);
  115. #ifdef __KERNEL__
  116. mdelay(2);
  117. #endif
  118. isp_write_reg(dev, REG_ADDR(vi_ircl), 0x0);
  119. /*clear mis array*/
  120. isp_write_reg(dev, REG_ADDR(isp_ctrl), 0x0); //clear isp_ctrl disable_isp_clk
  121. isp_info("exit %s\n", __func__);
  122. return 0;
  123. }
  124. int isp_enable_tpg(struct isp_ic_dev *dev)
  125. {
  126. u32 addr, isp_tpg_ctrl;
  127. isp_info("enter %s\n", __func__);
  128. addr = REG_ADDR(isp_tpg_ctrl);
  129. isp_tpg_ctrl = isp_read_reg(dev, addr);
  130. //REG_SET_SLICE(isp_tpg_ctrl, TPG_FRAME_NUM, 1);//set tpg frame num
  131. REG_SET_SLICE(isp_tpg_ctrl, TPG_ENABLE, 1);
  132. isp_write_reg(dev, addr, isp_tpg_ctrl);
  133. isp_info("exit %s\n", __func__);
  134. return 0;
  135. }
  136. int isp_disable_tpg(struct isp_ic_dev *dev)
  137. {
  138. u32 addr, isp_tpg_ctrl;
  139. isp_info("enter %s\n", __func__);
  140. addr = REG_ADDR(isp_tpg_ctrl);
  141. isp_tpg_ctrl = isp_read_reg(dev, addr);
  142. REG_SET_SLICE(isp_tpg_ctrl, TPG_ENABLE, 0);
  143. isp_write_reg(dev, addr, isp_tpg_ctrl);
  144. isp_info("exit %s\n", __func__);
  145. return 0;
  146. }
  147. int isp_enable_bls(struct isp_ic_dev *dev)
  148. {
  149. #ifndef ISP_BLS
  150. //isp_err("unsupported function %s", __func__);
  151. return -1;
  152. #else
  153. u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl));
  154. isp_info("enter %s\n", __func__);
  155. REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_ENABLE,
  156. MRV_BLS_BLS_ENABLE_PROCESS);
  157. isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl);
  158. isp_info("exit %s\n", __func__);
  159. return 0;
  160. #endif
  161. }
  162. int isp_disable_bls(struct isp_ic_dev *dev)
  163. {
  164. #ifndef ISP_BLS
  165. //isp_err("unsupported function %s", __func__);
  166. return -1;
  167. #else
  168. u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl));
  169. isp_info("enter %s\n", __func__);
  170. REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_ENABLE,
  171. MRV_BLS_BLS_ENABLE_BYPASS);
  172. isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl);
  173. isp_info("exit %s\n", __func__);
  174. return 0;
  175. #endif
  176. }
  177. int isp_enable(struct isp_ic_dev *dev)
  178. {
  179. u32 isp_ctrl, isp_imsc;
  180. isp_info("enter %s\n", __func__);
  181. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  182. isp_imsc |= (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK);
  183. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  184. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  185. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 1);
  186. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  187. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 1);
  188. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  189. /*Set lsc tbl after isp enable*/
  190. if (dev->update_lsc_tbl) {
  191. isp_s_lsc_tbl(dev);
  192. dev->update_lsc_tbl = false;
  193. }
  194. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1);
  195. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  196. isp_info("exit %s\n", __func__);
  197. return 0;
  198. }
  199. int isp_disable(struct isp_ic_dev *dev)
  200. {
  201. u32 isp_ctrl;
  202. /* #ifndef ENABLE_IRQ
  203. u32 isp_imsc;
  204. #endif*/
  205. isp_info("enter %s\n", __func__);
  206. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  207. /* #ifndef ENABLE_IRQ
  208. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  209. isp_imsc |= (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK);
  210. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  211. #endif*/
  212. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 0);
  213. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  214. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 0);
  215. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  216. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  217. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  218. isp_write_reg(dev, REG_ADDR(isp_isr), MRV_ISP_ISR_ISP_OFF_MASK);
  219. isp_info("exit %s\n", __func__);
  220. return 0;
  221. }
  222. bool is_isp_enable(struct isp_ic_dev *dev)
  223. {
  224. // isp_info("enter %s\n", __func__);
  225. return isp_read_reg(dev, REG_ADDR(isp_ctrl)) & 0x01;
  226. }
  227. int isp_enable_lsc(struct isp_ic_dev *dev)
  228. {
  229. u32 isp_lsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_lsc_ctrl));
  230. isp_info("enter %s\n", __func__);
  231. REG_SET_SLICE(isp_lsc_ctrl, MRV_LSC_LSC_EN, 1U);
  232. isp_write_reg(dev, REG_ADDR(isp_lsc_ctrl), isp_lsc_ctrl);
  233. {
  234. uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  235. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  236. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  237. }
  238. isp_info("exit %s\n", __func__);
  239. return 0;
  240. }
  241. int isp_disable_lsc(struct isp_ic_dev *dev)
  242. {
  243. u32 isp_lsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_lsc_ctrl));
  244. isp_info("enter %s\n", __func__);
  245. REG_SET_SLICE(isp_lsc_ctrl, MRV_LSC_LSC_EN, 0U);
  246. isp_write_reg(dev, REG_ADDR(isp_lsc_ctrl), isp_lsc_ctrl);
  247. {
  248. uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  249. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  250. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  251. }
  252. isp_info("exit %s\n", __func__);
  253. return 0;
  254. }
  255. #if defined(__KERNEL__) && defined(ISP8000NANO_V1802)
  256. static int isp_gpr_input_control(struct isp_ic_dev *dev)
  257. {
  258. struct isp_context isp_ctx = *(&dev->ctx);
  259. unsigned int fmt_offset = 3;
  260. unsigned int isp_dewarp_control_val;
  261. if (dev->mix_gpr == NULL)
  262. return -ENOMEM;
  263. if (dev->id == 0)
  264. fmt_offset = 3;
  265. else
  266. fmt_offset = 13;
  267. regmap_read(dev->mix_gpr, 0x138, &isp_dewarp_control_val);
  268. if (isp_dewarp_control_val == 0)
  269. isp_dewarp_control_val = 0x8d8360;
  270. switch (isp_ctx.input_selection) {
  271. case MRV_ISP_INPUT_SELECTION_12EXT:
  272. isp_dewarp_control_val &= ~(0x3f << fmt_offset);
  273. isp_dewarp_control_val |= (0x2c << fmt_offset);
  274. break;
  275. case MRV_ISP_INPUT_SELECTION_10ZERO:
  276. case MRV_ISP_INPUT_SELECTION_10MSB:
  277. isp_dewarp_control_val &= ~(0x3f << fmt_offset);
  278. isp_dewarp_control_val |= (0x2b << fmt_offset);
  279. break;
  280. case MRV_ISP_INPUT_SELECTION_8ZERO:
  281. case MRV_ISP_INPUT_SELECTION_8MSB:
  282. isp_dewarp_control_val &= ~(0x3f << fmt_offset);
  283. isp_dewarp_control_val |= (0x2a << fmt_offset);
  284. break;
  285. default:
  286. return 0;
  287. }
  288. regmap_write(dev->mix_gpr, 0x138, isp_dewarp_control_val);
  289. return 0;
  290. }
  291. #endif
  292. int isp_s_input(struct isp_ic_dev *dev)
  293. {
  294. struct isp_context isp_ctx = *(&dev->ctx);
  295. u32 isp_ctrl, isp_acq_prop, isp_demosaic;
  296. #ifdef ISP_HDR_STITCH
  297. u32 isp_stitching_ctrl;
  298. #endif //ISP_HDR_STITCH
  299. isp_info("enter %s\n", __func__);
  300. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  301. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_MODE, isp_ctx.mode);
  302. isp_acq_prop = isp_read_reg(dev, REG_ADDR(isp_acq_prop));
  303. REG_SET_SLICE(isp_acq_prop, MRV_ISP_SAMPLE_EDGE, isp_ctx.sample_edge);
  304. REG_SET_SLICE(isp_acq_prop, MRV_ISP_HSYNC_POL,
  305. isp_ctx.hSyncLowPolarity);
  306. REG_SET_SLICE(isp_acq_prop, MRV_ISP_VSYNC_POL,
  307. isp_ctx.vSyncLowPolarity);
  308. REG_SET_SLICE(isp_acq_prop, MRV_ISP_BAYER_PAT, isp_ctx.bayer_pattern);
  309. REG_SET_SLICE(isp_acq_prop, MRV_ISP_CONV_422, isp_ctx.sub_sampling);
  310. REG_SET_SLICE(isp_acq_prop, MRV_ISP_CCIR_SEQ, isp_ctx.seq_ccir);
  311. REG_SET_SLICE(isp_acq_prop, MRV_ISP_FIELD_SELECTION,
  312. isp_ctx.field_selection);
  313. REG_SET_SLICE(isp_acq_prop, MRV_ISP_INPUT_SELECTION,
  314. isp_ctx.input_selection);
  315. REG_SET_SLICE(isp_acq_prop, MRV_ISP_LATENCY_FIFO_SELECTION,
  316. isp_ctx.latency_fifo);
  317. isp_write_reg(dev, REG_ADDR(isp_acq_prop), isp_acq_prop);
  318. isp_write_reg(dev, REG_ADDR(isp_acq_h_offs), isp_ctx.acqWindow.x);
  319. isp_write_reg(dev, REG_ADDR(isp_acq_v_offs), isp_ctx.acqWindow.y);
  320. isp_write_reg(dev, REG_ADDR(isp_acq_h_size), isp_ctx.acqWindow.width);
  321. isp_write_reg(dev, REG_ADDR(isp_acq_v_size), isp_ctx.acqWindow.height);
  322. #ifdef ISP_MI_HDR
  323. isp_write_reg(dev, REG_ADDR(isp_hdr_interval), 0x113);
  324. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_h_blank), 0x200);
  325. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_v_blank), 0x30);
  326. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_h_size), isp_ctx.acqWindow.width);
  327. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_v_size), isp_ctx.acqWindow.height);
  328. #endif
  329. isp_write_reg(dev, REG_ADDR(isp_out_h_offs),
  330. (isp_ctx.ofWindow.x & MRV_ISP_ISP_OUT_H_OFFS_MASK));
  331. isp_write_reg(dev, REG_ADDR(isp_out_v_offs),
  332. (isp_ctx.ofWindow.y & MRV_ISP_ISP_OUT_V_OFFS_MASK));
  333. isp_write_reg(dev, REG_ADDR(isp_out_h_size),
  334. (isp_ctx.ofWindow.width & MRV_ISP_ISP_OUT_H_SIZE_MASK));
  335. isp_write_reg(dev, REG_ADDR(isp_out_v_size),
  336. (isp_ctx.ofWindow.height & MRV_ISP_ISP_OUT_V_SIZE_MASK));
  337. isp_write_reg(dev, REG_ADDR(isp_is_h_offs),
  338. (isp_ctx.isWindow.x & MRV_IS_IS_H_OFFS_MASK));
  339. isp_write_reg(dev, REG_ADDR(isp_is_v_offs),
  340. (isp_ctx.isWindow.y & MRV_IS_IS_V_OFFS_MASK));
  341. isp_write_reg(dev, REG_ADDR(isp_is_h_size),
  342. (isp_ctx.isWindow.width & MRV_IS_IS_H_SIZE_MASK));
  343. isp_write_reg(dev, REG_ADDR(isp_is_v_size),
  344. (isp_ctx.isWindow.height & MRV_IS_IS_V_SIZE_MASK));
  345. isp_demosaic = isp_read_reg(dev, REG_ADDR(isp_demosaic));
  346. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_BYPASS,
  347. isp_ctx.bypass_mode);
  348. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_TH,
  349. isp_ctx.demosaic_threshold);
  350. isp_write_reg(dev, REG_ADDR(isp_demosaic), isp_demosaic);
  351. #ifdef ISP_HDR_STITCH
  352. isp_write_reg(dev, REG_ADDR(isp_stitching_frame_width), isp_ctx.acqWindow.width);
  353. isp_write_reg(dev, REG_ADDR(isp_stitching_frame_height), isp_ctx.acqWindow.height);
  354. isp_write_reg(dev, REG_ADDR(isp_stitching_hdr_mode), isp_ctx.stitching_mode);
  355. isp_stitching_ctrl = isp_read_reg(dev, REG_ADDR(isp_stitching_ctrl));
  356. REG_SET_SLICE(isp_stitching_ctrl, STITCHING_BAYER_PATTERN, isp_ctx.bayer_pattern);
  357. isp_write_reg(dev, REG_ADDR(isp_stitching_ctrl), isp_stitching_ctrl);
  358. #endif
  359. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  360. #if defined(__KERNEL__) && defined(ISP8000NANO_V1802)
  361. isp_gpr_input_control(dev);
  362. #endif
  363. return 0;
  364. }
  365. int isp_s_digital_gain(struct isp_ic_dev *dev)
  366. {
  367. if (dev->dgain.changed) {
  368. u32 isp_dgain_rb = isp_read_reg(dev, REG_ADDR(isp_dgain_rb));
  369. u32 isp_dgain_g = isp_read_reg(dev, REG_ADDR(isp_dgain_g));
  370. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  371. if (!dev->dgain.enable) {
  372. isp_err("%s, Disable isp digital gain", __func__);
  373. REG_SET_SLICE(isp_ctrl, MRV_ISP_DIGITAL_GAIN_EN, 0U);
  374. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  375. return 0;
  376. }
  377. //isp_info("enter %s\n", __func__);
  378. REG_SET_SLICE(isp_dgain_rb, ISP_DIGITAL_GAIN_R, dev->dgain.gain_r);
  379. REG_SET_SLICE(isp_dgain_rb, ISP_DIGITAL_GAIN_B, dev->dgain.gain_b);
  380. REG_SET_SLICE(isp_dgain_g, ISP_DIGITAL_GAIN_GR, dev->dgain.gain_gr);
  381. REG_SET_SLICE(isp_dgain_g, ISP_DIGITAL_GAIN_GB, dev->dgain.gain_gb);
  382. REG_SET_SLICE(isp_ctrl, MRV_ISP_DIGITAL_GAIN_EN, 1U);
  383. isp_write_reg(dev, REG_ADDR(isp_dgain_rb), isp_dgain_rb);
  384. isp_write_reg(dev, REG_ADDR(isp_dgain_g), isp_dgain_g);
  385. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  386. //isp_info("exit %s\n", __func__);
  387. dev->dgain.changed = false;
  388. } else {
  389. dev->dgain.changed = true;
  390. }
  391. return 0;
  392. }
  393. int isp_s_demosaic(struct isp_ic_dev *dev)
  394. {
  395. struct isp_context isp_ctx = *(&dev->ctx);
  396. u32 isp_demosaic;
  397. isp_info("enter %s\n", __func__);
  398. isp_demosaic = isp_read_reg(dev, REG_ADDR(isp_demosaic));
  399. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_BYPASS,
  400. isp_ctx.bypass_mode);
  401. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_TH,
  402. isp_ctx.demosaic_threshold);
  403. isp_write_reg(dev, REG_ADDR(isp_demosaic), isp_demosaic);
  404. isp_info("exit %s\n", __func__);
  405. return 0;;
  406. }
  407. int isp_s_tpg(struct isp_ic_dev *dev)
  408. {
  409. struct isp_tpg_context tpg = *(&dev->tpg);
  410. u32 addr, regVal;
  411. isp_info("enter %s\n", __func__);
  412. addr = REG_ADDR(isp_tpg_ctrl);
  413. regVal = isp_read_reg(dev, addr);
  414. REG_SET_SLICE(regVal, TPG_IMG_NUM, tpg.image_type);
  415. REG_SET_SLICE(regVal, TPG_CFA_PAT, tpg.bayer_pattern);
  416. REG_SET_SLICE(regVal, TPG_COLOR_DEPTH, tpg.color_depth);
  417. REG_SET_SLICE(regVal, TPG_RESOLUTION, tpg.resolution);
  418. REG_SET_SLICE(regVal, TPG_FRAME_NUM, tpg.frame_num);
  419. isp_write_reg(dev, addr, regVal);
  420. regVal = 0;
  421. REG_SET_SLICE(regVal, TPG_PIX_GAP_IN, tpg.pixleGap);
  422. REG_SET_SLICE(regVal, TPG_LINE_GAP_IN, tpg.lineGap);
  423. isp_write_reg(dev, REG_ADDR(isp_tpg_gap_in), regVal);
  424. regVal = 0;
  425. REG_SET_SLICE(regVal, TPG_PIX_GAP_STD_IN, tpg.gapStandard);
  426. isp_write_reg(dev, REG_ADDR(isp_tpg_gap_std_in), regVal);
  427. regVal = 0;
  428. REG_SET_SLICE(regVal, TPG_RANDOM_SEED, tpg.randomSeed);
  429. isp_write_reg(dev, REG_ADDR(isp_tpg_random_seed), regVal);
  430. REG_SET_SLICE(regVal, TPG_HTOTAL_IN, tpg.user_mode_h.total);
  431. REG_SET_SLICE(regVal, TPG_VTOTAL_IN, tpg.user_mode_v.total);
  432. isp_write_reg(dev, REG_ADDR(isp_tpg_total_in), regVal);
  433. regVal = 0;
  434. REG_SET_SLICE(regVal, TPG_HACT_IN, tpg.user_mode_h.act);
  435. REG_SET_SLICE(regVal, TPG_VACT_IN, tpg.user_mode_v.act);
  436. isp_write_reg(dev, REG_ADDR(isp_tpg_act_in), regVal);
  437. regVal = 0;
  438. REG_SET_SLICE(regVal, TPG_FP_H_IN, tpg.user_mode_h.fp);
  439. REG_SET_SLICE(regVal, TPG_FP_V_IN, tpg.user_mode_v.fp);
  440. isp_write_reg(dev, REG_ADDR(isp_tpg_fp_in), regVal);
  441. regVal = 0;
  442. REG_SET_SLICE(regVal, TPG_BP_H_IN, tpg.user_mode_h.bp);
  443. REG_SET_SLICE(regVal, TPG_BP_V_IN, tpg.user_mode_v.bp);
  444. isp_write_reg(dev, REG_ADDR(isp_tpg_bp_in), regVal);
  445. regVal = 0;
  446. REG_SET_SLICE(regVal, TPG_HS_W_IN, tpg.user_mode_h.sync);
  447. REG_SET_SLICE(regVal, TPG_VS_W_IN, tpg.user_mode_v.sync);
  448. isp_write_reg(dev, REG_ADDR(isp_tpg_w_in), regVal);
  449. isp_info("exit %s\n", __func__);
  450. return 0;
  451. }
  452. int isp_s_mcm_wr(struct isp_ic_dev *dev)
  453. {
  454. struct isp_mcm_context *mcm = &dev->mcm;
  455. u32 mcm_ctrl;
  456. u32 mcm_hsync_preample_ext;
  457. u32 mcm_size, mcm_rd_fmt;
  458. int i;
  459. isp_info("enter %s\n", __func__);
  460. mcm_ctrl = isp_read_reg(dev, REG_ADDR(mcm_ctrl));
  461. mcm_rd_fmt = isp_read_reg(dev, REG_ADDR(mcm_rd_cfg));
  462. mcm_hsync_preample_ext = isp_read_reg(dev, REG_ADDR(mcm_hsync_preample_ext));
  463. REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_SWITCH, mcm->bypass_switch);
  464. REG_SET_SLICE(mcm_ctrl, MCM_WR0_FMT, mcm->wr_fmt[MCM_INDEX_WR0]);
  465. REG_SET_SLICE(mcm_ctrl, MCM_WR1_FMT, mcm->wr_fmt[MCM_INDEX_WR1]);
  466. REG_SET_SLICE(mcm_ctrl, MCM_G2_WR0_FMT, mcm->wr_fmt[MCM_INDEX_G2_WR0]);
  467. REG_SET_SLICE(mcm_ctrl, MCM_G2_WR1_FMT, mcm->wr_fmt[MCM_INDEX_G2_WR1]);
  468. REG_SET_SLICE(mcm_ctrl, MCM_SENSOR_MEM_BYPASS, mcm->sensor_mem_bypass);
  469. REG_SET_SLICE(mcm_rd_fmt, MCM_RD_FMT, mcm->rd_fmt);
  470. REG_SET_SLICE(mcm_hsync_preample_ext, MCM_HSYNC_PREAMPLE_EXT, mcm->hsync_rpeample_ext);
  471. for (i = MCM_INDEX_WR0 ; i < MCM_INDEX_WR_MAX; i++){
  472. REG_SET_SLICE(mcm_size, MCM_HEIGHT0, mcm->height[i]);
  473. REG_SET_SLICE(mcm_size, MCM_WIDTH0, mcm->width[i]);
  474. isp_write_reg(dev, REG_ADDR(mcm_size0) + i *4, mcm_size);
  475. }
  476. isp_write_reg(dev, REG_ADDR(mcm_hsync_preample_ext), mcm_hsync_preample_ext);
  477. isp_write_reg(dev, REG_ADDR(mcm_rd_cfg), mcm_rd_fmt);
  478. isp_write_reg(dev, REG_ADDR(mcm_ctrl), mcm_ctrl);
  479. isp_info("exit %s\n", __func__);
  480. return 0;
  481. }
  482. int isp_bypass_mcm(struct isp_ic_dev *dev)
  483. {
  484. struct isp_mcm_context *mcm = &dev->mcm;
  485. u32 mcm_ctrl;
  486. u32 mcm_retiming0;
  487. u32 mcm_retiming1;
  488. u32 mcm_wr_retiming0;
  489. u32 mcm_wr_retiming1;
  490. isp_info("enter %s\n", __func__);
  491. mcm_ctrl = isp_read_reg(dev, REG_ADDR(mcm_ctrl));
  492. mcm_retiming0 = isp_read_reg(dev, REG_ADDR(mcm_retiming0));
  493. mcm_retiming1 = isp_read_reg(dev, REG_ADDR(mcm_retiming1));
  494. mcm_wr_retiming0 = isp_read_reg(dev, REG_ADDR(mcm_wr_retiming0));
  495. mcm_wr_retiming1 = isp_read_reg(dev, REG_ADDR(mcm_wr_retiming1));
  496. if (mcm->bypass_enable) {
  497. REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_EN, 1);
  498. } else {
  499. REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_EN, 0);
  500. }
  501. REG_SET_SLICE(mcm_retiming0, MCM_VSYNC_DURATION, mcm->vsync_duration);
  502. REG_SET_SLICE(mcm_retiming0, MCM_VSYNC_BLANK, mcm->vsync_blank);
  503. REG_SET_SLICE(mcm_retiming1, MCM_HSYNC_PREAMPLE, mcm->hsync_preample);
  504. REG_SET_SLICE(mcm_retiming1, MCM_HSYNC_BLANK, mcm->hsync_blank);
  505. REG_SET_SLICE(mcm_wr_retiming0, MCM_VSYNC_DURATION, mcm->vsync_duration);
  506. REG_SET_SLICE(mcm_wr_retiming0, MCM_VSYNC_BLANK, mcm->vsync_blank);
  507. REG_SET_SLICE(mcm_wr_retiming1, MCM_HSYNC_PREAMPLE, mcm->hsync_preample);
  508. REG_SET_SLICE(mcm_wr_retiming1, MCM_HSYNC_BLANK, mcm->hsync_blank);
  509. isp_write_reg(dev, REG_ADDR(mcm_ctrl), mcm_ctrl);
  510. isp_write_reg(dev, REG_ADDR(mcm_retiming0), mcm_retiming0); // 0x01042801);//
  511. isp_write_reg(dev, REG_ADDR(mcm_retiming1), mcm_retiming1); //0x00008478); //
  512. isp_write_reg(dev, REG_ADDR(mcm_wr_retiming0), mcm_wr_retiming0); //0x01042801); //
  513. isp_write_reg(dev, REG_ADDR(mcm_wr_retiming1), mcm_wr_retiming1); //0x000084ec);//
  514. isp_info("exit %s\n", __func__);
  515. return 0;
  516. }
  517. int isp_s_mux(struct isp_ic_dev *dev)
  518. {
  519. struct isp_mux_context mux = *(&dev->mux);
  520. u32 vi_dpcl;
  521. isp_info("enter %s\n", __func__);
  522. vi_dpcl = isp_read_reg(dev, REG_ADDR(vi_dpcl));
  523. REG_SET_SLICE(vi_dpcl, MRV_VI_MP_MUX, mux.mp_mux);
  524. REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_SPMUX, mux.sp_mux);
  525. REG_SET_SLICE(vi_dpcl, MRV_VI_CHAN_MODE, mux.chan_mode);
  526. REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_IEMUX, mux.ie_mux);
  527. REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_SWITCH, mux.dma_read_switch);
  528. REG_SET_SLICE(vi_dpcl, MRV_IF_SELECT, mux.if_select);
  529. isp_write_reg(dev, REG_ADDR(vi_dpcl), vi_dpcl);
  530. isp_info("exit %s\n", __func__);
  531. return 0;
  532. }
  533. int isp_s_bls(struct isp_ic_dev *dev)
  534. {
  535. #ifndef ISP_BLS
  536. //isp_err("unsupported function %s", __func__);
  537. return -1;
  538. #else
  539. struct isp_bls_context bls = *(&dev->bls);
  540. u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl));
  541. isp_info("enter %s\n", __func__);
  542. REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_MODE, bls.mode);
  543. isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl);
  544. isp_write_reg(dev, REG_ADDR(isp_bls_a_fixed), bls.a);
  545. isp_write_reg(dev, REG_ADDR(isp_bls_b_fixed), bls.b);
  546. isp_write_reg(dev, REG_ADDR(isp_bls_c_fixed), bls.c);
  547. isp_write_reg(dev, REG_ADDR(isp_bls_d_fixed), bls.d);
  548. return 0;
  549. #endif
  550. }
  551. int isp_enable_awb(struct isp_ic_dev *dev)
  552. {
  553. u32 isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop));
  554. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  555. isp_info("enter %s\n", __func__);
  556. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MODE, MRV_ISP_AWB_MODE_MEAS);
  557. isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop);
  558. isp_write_reg(dev, REG_ADDR(isp_imsc),
  559. isp_imsc | MRV_ISP_IMSC_AWB_DONE_MASK);
  560. isp_info("exit %s\n", __func__);
  561. return 0;
  562. }
  563. int isp_disable_awb(struct isp_ic_dev *dev)
  564. {
  565. u32 isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop));
  566. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  567. isp_info("enter %s\n", __func__);
  568. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MODE, MRV_ISP_AWB_MODE_NOMEAS);
  569. isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop);
  570. isp_write_reg(dev, REG_ADDR(isp_imsc),
  571. isp_imsc & ~MRV_ISP_IMSC_AWB_DONE_MASK);
  572. isp_info("exit %s\n", __func__);
  573. return 0;
  574. }
  575. int isp_s_awb(struct isp_ic_dev *dev)
  576. {
  577. struct isp_awb_context awb = *(&dev->awb);
  578. u32 gain_data = 0;
  579. u32 isp_awb_thresh = 0;
  580. u32 isp_awb_ref = 0;
  581. u32 isp_awb_prop = 0;
  582. /* isp_info("enter %s\n", __func__); */
  583. isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop));
  584. if (awb.mode == MRV_ISP_AWB_MEAS_MODE_YCBCR) {
  585. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MEAS_MODE,
  586. MRV_ISP_AWB_MEAS_MODE_YCBCR);
  587. if (awb.max_y == 0) {
  588. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN,
  589. MRV_ISP_AWB_MAX_EN_DISABLE);
  590. } else {
  591. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN,
  592. MRV_ISP_AWB_MAX_EN_ENABLE);
  593. }
  594. } else if (awb.mode == MRV_ISP_AWB_MEAS_MODE_RGB) {
  595. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN,
  596. MRV_ISP_AWB_MAX_EN_DISABLE);
  597. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MEAS_MODE,
  598. MRV_ISP_AWB_MEAS_MODE_RGB);
  599. }
  600. isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop);
  601. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MAX_Y, awb.max_y);
  602. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MIN_Y__MAX_G,
  603. awb.min_y_max_g);
  604. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MAX_CSUM, awb.max_c_sum);
  605. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MIN_C, awb.min_c);
  606. isp_write_reg(dev, REG_ADDR(isp_awb_thresh), isp_awb_thresh);
  607. REG_SET_SLICE(isp_awb_ref, MRV_ISP_AWB_REF_CR__MAX_R, awb.refcr_max_r);
  608. REG_SET_SLICE(isp_awb_ref, MRV_ISP_AWB_REF_CB__MAX_B, awb.refcb_max_b);
  609. isp_write_reg(dev, REG_ADDR(isp_awb_ref), isp_awb_ref);
  610. isp_write_reg(dev, REG_ADDR(isp_awb_frames), 0);
  611. isp_write_reg(dev, REG_ADDR(isp_awb_h_offs),
  612. (MRV_ISP_AWB_H_OFFS_MASK & awb.window.x));
  613. isp_write_reg(dev, REG_ADDR(isp_awb_v_offs),
  614. (MRV_ISP_AWB_V_OFFS_MASK & awb.window.y));
  615. isp_write_reg(dev, REG_ADDR(isp_awb_h_size),
  616. (MRV_ISP_AWB_H_SIZE_MASK & awb.window.width));
  617. isp_write_reg(dev, REG_ADDR(isp_awb_v_size),
  618. (MRV_ISP_AWB_V_SIZE_MASK & awb.window.height));
  619. gain_data = 0UL;
  620. #ifdef ISP_AWB_0410 //This is Gain value component 4 bit int part and 10 bit fractional part
  621. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_R, awb.gain_r << 2);
  622. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_B, awb.gain_b << 2) ;
  623. #else //This is Gain value component 2 bit int part and 8 bit fractional part
  624. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_R, awb.gain_r);
  625. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_B, awb.gain_b);
  626. #endif
  627. isp_write_reg(dev, REG_ADDR(isp_awb_gain_rb), gain_data);
  628. gain_data = 0UL;
  629. #ifdef ISP_AWB_0410 //This is Gain value component 4 bit int part and 10 bit fractional part
  630. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GR, awb.gain_gr << 2);
  631. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GB, awb.gain_gb << 2);
  632. #else //This is Gain value component 2 bit int part and 8 bit fractional part
  633. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GR, awb.gain_gr);
  634. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GB, awb.gain_gb);
  635. #endif
  636. isp_write_reg(dev, REG_ADDR(isp_awb_gain_g), gain_data);
  637. return 0;
  638. }
  639. int isp_s_is(struct isp_ic_dev *dev)
  640. {
  641. struct isp_is_context is = *(&dev->is);
  642. u32 isp_is_ctrl;
  643. u32 isp_is_displace;
  644. u32 isp_ctrl;
  645. isp_info("enter %s\n", __func__);
  646. isp_is_ctrl = isp_read_reg(dev, REG_ADDR(isp_is_ctrl));
  647. if (!is.enable) {
  648. REG_SET_SLICE(isp_is_ctrl, MRV_IS_IS_EN, 0);
  649. isp_write_reg(dev, REG_ADDR(isp_is_ctrl), isp_is_ctrl);
  650. return 0;
  651. }
  652. REG_SET_SLICE(isp_is_ctrl, MRV_IS_IS_EN, 1);
  653. isp_write_reg(dev, REG_ADDR(isp_is_h_offs), is.window.x);
  654. isp_write_reg(dev, REG_ADDR(isp_is_v_offs), is.window.y);
  655. isp_write_reg(dev, REG_ADDR(isp_is_h_size), is.window.width);
  656. isp_write_reg(dev, REG_ADDR(isp_is_v_size), is.window.height);
  657. isp_write_reg(dev, REG_ADDR(isp_is_recenter),
  658. is.recenter & MRV_IS_IS_RECENTER_MASK);
  659. isp_write_reg(dev, REG_ADDR(isp_is_max_dx), is.max_dx);
  660. isp_write_reg(dev, REG_ADDR(isp_is_max_dy), is.max_dy);
  661. isp_is_displace = isp_read_reg(dev, REG_ADDR(isp_is_displace));
  662. REG_SET_SLICE(isp_is_displace, MRV_IS_DX, is.displace_x);
  663. REG_SET_SLICE(isp_is_displace, MRV_IS_DY, is.displace_y);
  664. isp_write_reg(dev, REG_ADDR(isp_is_displace), isp_is_displace);
  665. isp_write_reg(dev, REG_ADDR(isp_is_ctrl), isp_is_ctrl);
  666. if (is.update) {
  667. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  668. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  669. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  670. is.update = false;
  671. }
  672. isp_info("exit %s\n", __func__);
  673. return 0;
  674. }
  675. int isp_s_raw_is(struct isp_ic_dev *dev)
  676. {
  677. #ifndef ISP_RAWIS
  678. //isp_err("unsupported funciton: %s\n", __func__);
  679. return -EINVAL;
  680. #else
  681. struct isp_is_context rawis = *(&dev->rawis);
  682. u32 isp_raw_is_ctrl;
  683. u32 isp_raw_is_displace;
  684. // u32 isp_ctrl;
  685. isp_info("enter %s\n", __func__);
  686. isp_raw_is_ctrl = isp_read_reg(dev, REG_ADDR(isp_raw_is_ctrl));
  687. if (!rawis.enable) {
  688. isp_write_reg(dev, REG_ADDR(isp_raw_is_h_size),
  689. rawis.window.width);
  690. isp_write_reg(dev, REG_ADDR(isp_raw_is_v_size),
  691. rawis.window.height);
  692. REG_SET_SLICE(isp_raw_is_ctrl, MRV_ISP_RAW_IS_EN, 0);
  693. isp_write_reg(dev, REG_ADDR(isp_raw_is_ctrl), isp_raw_is_ctrl);
  694. return 0;
  695. }
  696. REG_SET_SLICE(isp_raw_is_ctrl, MRV_ISP_RAW_IS_EN, 1);
  697. isp_write_reg(dev, REG_ADDR(isp_raw_is_h_offs), rawis.window.x);
  698. isp_write_reg(dev, REG_ADDR(isp_raw_is_v_offs), rawis.window.y);
  699. isp_write_reg(dev, REG_ADDR(isp_raw_is_h_size), rawis.window.width);
  700. isp_write_reg(dev, REG_ADDR(isp_raw_is_v_size), rawis.window.height);
  701. isp_write_reg(dev, REG_ADDR(isp_raw_is_recenter),
  702. rawis.recenter & MRV_IS_IS_RECENTER_MASK);
  703. isp_write_reg(dev, REG_ADDR(isp_raw_is_max_dx), rawis.max_dx);
  704. isp_write_reg(dev, REG_ADDR(isp_raw_is_max_dy), rawis.max_dy);
  705. isp_raw_is_displace = isp_read_reg(dev, REG_ADDR(isp_raw_is_displace));
  706. REG_SET_SLICE(isp_raw_is_displace, MRV_ISP_RAW_IS_DX, rawis.displace_x);
  707. REG_SET_SLICE(isp_raw_is_displace, MRV_ISP_RAW_IS_DY, rawis.displace_y);
  708. isp_write_reg(dev, REG_ADDR(isp_raw_is_displace), isp_raw_is_displace);
  709. isp_write_reg(dev, REG_ADDR(isp_raw_is_ctrl), isp_raw_is_ctrl);
  710. /*dont update the configuration at the sub module function*/
  711. #if 0
  712. if (rawis.update) {
  713. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  714. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1);
  715. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  716. rawis.update = false;
  717. }
  718. #endif
  719. return 0;
  720. #endif
  721. }
  722. int isp_s_cnr(struct isp_ic_dev *dev)
  723. {
  724. struct isp_cnr_context *cnr = &dev->cnr;
  725. u32 isp_ctrl;
  726. isp_info("enter %s\n", __func__);
  727. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  728. if (!cnr->enable) {
  729. REG_SET_SLICE(isp_ctrl, MRV_ISP_CNR_EN, 0);
  730. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  731. return 0;
  732. }
  733. REG_SET_SLICE(isp_ctrl, MRV_ISP_CNR_EN, 1);
  734. isp_write_reg(dev, REG_ADDR(isp_cnr_linesize), cnr->line_width);
  735. isp_write_reg(dev, REG_ADDR(isp_cnr_threshold_c1), cnr->threshold_1);
  736. isp_write_reg(dev, REG_ADDR(isp_cnr_threshold_c2), cnr->threshold_2);
  737. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  738. isp_info("exit %s\n", __func__);
  739. return 0;
  740. }
  741. void isp_test_bt(struct isp_ic_dev *dev)
  742. {
  743. isp_write_reg(dev, 0x00000010, 0x00019f7b);
  744. isp_write_reg(dev, 0x00000014, 0x00020000);
  745. isp_write_reg(dev, 0x00001200, 0x00000000);
  746. isp_write_reg(dev, 0x00001204, 0x01e00280);
  747. isp_write_reg(dev, 0x00001208, 0x01e00280);
  748. isp_write_reg(dev, 0x00001308, 0x6ce60608);
  749. isp_write_reg(dev, 0x00001314, 0x000008c4);
  750. isp_write_reg(dev, 0x00001318, 0x00000001);
  751. isp_write_reg(dev, 0x0000131c, 0x03a2013b);
  752. isp_write_reg(dev, 0x00001320, 0x00000000);
  753. isp_write_reg(dev, 0x00001324, 0xc0000000);
  754. isp_write_reg(dev, 0x00001328, 0x0004B000);
  755. isp_write_reg(dev, 0x0000132c, 0x00000000);
  756. isp_write_reg(dev, 0x00001330, 0x00000280);
  757. isp_write_reg(dev, 0x00001334, 0x00000280);
  758. isp_write_reg(dev, 0x00001338, 0x000001e0);
  759. isp_write_reg(dev, 0x0000133c, 0x0004B000);
  760. isp_write_reg(dev, 0x00001340, 0xc0040000);
  761. isp_write_reg(dev, 0x00001344, 0x0004B000);
  762. isp_write_reg(dev, 0x000016c0, 0x07ffffff);
  763. isp_write_reg(dev, 0x000005bc, 0x00000003);
  764. isp_write_reg(dev, 0x000016c4, 0x052c4e39);
  765. isp_write_reg(dev, 0x00000404, 0x00d00018);
  766. isp_write_reg(dev, 0x00000410, 0x00000280);
  767. isp_write_reg(dev, 0x00000414, 0x000001e0);
  768. isp_write_reg(dev, 0x00000538, 0x01000100);
  769. isp_write_reg(dev, 0x0000053c, 0x02270220);
  770. isp_write_reg(dev, 0x0000059c, 0x00000280);
  771. isp_write_reg(dev, 0x000005a0, 0x000001e0);
  772. isp_write_reg(dev, 0x00002310, 0x00000280);
  773. isp_write_reg(dev, 0x00002314, 0x000001e0);
  774. isp_write_reg(dev, 0x0000295c, 0x00000070);
  775. isp_write_reg(dev, 0x00003e00, 0x040128be);
  776. isp_write_reg(dev, 0x00003e04, 0x00000000);
  777. isp_write_reg(dev, 0x00003e08, 0x00001f08);
  778. isp_write_reg(dev, 0x00003e0c, 0x200003ff);
  779. isp_write_reg(dev, 0x00003e10, 0x0c968628);
  780. isp_write_reg(dev, 0x00003e14, 0x00008008);
  781. isp_write_reg(dev, 0x00003e18, 0x007d07d0);
  782. isp_write_reg(dev, 0x00003e1c, 0x301a3012);
  783. isp_write_reg(dev, 0x00003e20, 0x04010000);
  784. isp_write_reg(dev, 0x00003e24, 0x22018000);
  785. isp_write_reg(dev, 0x00003e28, 0x00020000);
  786. isp_write_reg(dev, 0x00003e2c, 0x0210210a);
  787. isp_write_reg(dev, 0x00003e30, 0x00102102);
  788. isp_write_reg(dev, 0x00003e34, 0x0000388c);
  789. isp_write_reg(dev, 0x00003e38, 0x00000000);
  790. isp_write_reg(dev, 0x00003e3c, 0x00000000);
  791. isp_write_reg(dev, 0x00003e40, 0x00000000);
  792. isp_write_reg(dev, 0x00003e44, 0x00000001);
  793. isp_write_reg(dev, 0x00003e48, 0x10001000);
  794. isp_write_reg(dev, 0x00003e4c, 0x00000000);
  795. isp_write_reg(dev, 0x00003e50, 0x00000000);
  796. isp_write_reg(dev, 0x00003e54, 0x00000000);
  797. isp_write_reg(dev, 0x00003e58, 0x00080010);
  798. isp_write_reg(dev, 0x00003e5c, 0x00080010);
  799. isp_write_reg(dev, 0x00003e60, 0x01300280);
  800. isp_write_reg(dev, 0x00000018, 0x00001000);
  801. isp_write_reg(dev, 0x00001200, 0x00000001); //why
  802. isp_write_reg(dev, 0x00000418, 0x00000001);
  803. isp_write_reg(dev, 0x00000400, 0x80100686);
  804. isp_write_reg(dev, 0x00000400, 0x80100097);
  805. isp_write_reg(dev, 0x00001300, 0x00000001);
  806. isp_write_reg(dev, 0x00001310, 0x00000038);
  807. isp_write_reg(dev, 0x000014e4, 0x00000238);
  808. isp_write_reg(dev, 0x00001600, 0x0000005c);
  809. isp_write_reg(dev, 0x00000704, 0x00c00222);
  810. isp_write_reg(dev, 0x00000708, 0x00a001e0);
  811. isp_write_reg(dev, 0x0000070c, 0x000a4023);
  812. isp_write_reg(dev, 0x00000710, 0x000a401e);
  813. isp_write_reg(dev, 0x00000714, 0x000b8001);
  814. isp_write_reg(dev, 0x00000718, 0x003540a0);
  815. isp_write_reg(dev, 0x0000071c, 0x00000050);
  816. isp_write_reg(dev, 0x00000720, 0x3aca095b);
  817. isp_write_reg(dev, 0x00000700, 0x00000c42);
  818. isp_info("end %s\n", __func__);
  819. }
  820. int isp_start_stream(struct isp_ic_dev *dev, u32 numFrames)
  821. {
  822. u32 isp_imsc, isp_ctrl;
  823. isp_info("enter %s\n", __func__);
  824. #ifdef ISP_PDAF
  825. isp_write_reg(dev, 0x5d00, 0x1);
  826. #endif
  827. isp_write_reg(dev, REG_ADDR(isp_sh_ctrl), 0x10);
  828. isp_write_reg(dev, REG_ADDR(isp_acq_nr_frames),
  829. (MRV_ISP_ACQ_NR_FRAMES_MASK & numFrames));
  830. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  831. isp_imsc |=
  832. (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK |
  833. MRV_ISP_IMSC_FRAME_IN_MASK | MRV_ISP_IMSC_PIC_SIZE_ERR_MASK | MRV_ISP_IMSC_FLASH_ON_MASK |
  834. MRV_ISP_IMSC_DATA_LOSS_MASK);
  835. /* isp_imsc |= (MRV_ISP_IMSC_FRAME_MASK | MRV_ISP_IMSC_DATA_LOSS_MASK | MRV_ISP_IMSC_FRAME_IN_MASK); */
  836. isp_write_reg(dev, REG_ADDR(isp_icr), 0xFFFFFFFF);
  837. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  838. isp_write_reg(dev, 0x00001320, 1);
  839. isp_write_reg(dev, 0x00001610, 1);
  840. #if 0/*add by shenwuyi for live sensor*/
  841. isp_write_reg(dev, 0x00000c68, 10);/*fream_rete_ctrl*/
  842. isp_write_reg(dev, 0x00002200, 0x00000000); //disable lsc
  843. isp_write_reg(dev, 0x000005bc, 0x00000001); //irq_enable
  844. isp_write_reg(dev, 0x00000538, 0x01000100); //awb_gain_gr
  845. isp_write_reg(dev, 0x0000053c, 0x02270220); //awb_gain_gc
  846. #endif
  847. /*isp_test_bt(dev);*/
  848. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  849. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 1);
  850. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 1);
  851. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  852. /*Set lsc tbl after isp enable*/
  853. if (dev->update_lsc_tbl) {
  854. isp_s_lsc_tbl(dev);
  855. dev->update_lsc_tbl = false;
  856. }
  857. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  858. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1);
  859. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  860. isp_info("exit %s\n", __func__);
  861. return 0;
  862. }
  863. int isp_stop_stream(struct isp_ic_dev *dev)
  864. {
  865. isp_info("enter %s\n", __func__);
  866. isp_write_reg(dev, REG_ADDR(isp_imsc), 0);
  867. isp_disable(dev);
  868. isp_info("exit %s\n", __func__);
  869. return 0;
  870. }
  871. int isp_s_cc(struct isp_ic_dev *dev)
  872. {
  873. struct isp_cc_context *cc = &dev->cc;
  874. u32 isp_ctrl, addr;
  875. int i;
  876. isp_info("enter %s\n", __func__);
  877. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  878. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CSM_Y_RANGE, cc->conv_range_y_full);
  879. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CSM_C_RANGE, cc->conv_range_c_full);
  880. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  881. if (cc->update_curve) {
  882. addr = REG_ADDR(isp_cc_coeff_0);
  883. for (i = 0; i < 9; i++) {
  884. isp_write_reg(dev, addr + i * 4,
  885. MRV_ISP_CC_COEFF_0_MASK & cc->lCoeff[i]);
  886. }
  887. }
  888. isp_info("exit %s\n", __func__);
  889. return 0;
  890. }
  891. int isp_s_xtalk(struct isp_ic_dev *dev)
  892. {
  893. struct isp_xtalk_context xtalk = *(&dev->xtalk);
  894. int i;
  895. /* isp_info("enter %s\n", __func__); */
  896. for (i = 0; i < 9; i++) {
  897. #ifdef ISP_CTM_0507 // Coefficient for cross talk matrix.Use bit 11,Values are 12-bit signed fixed-point numbers with 5 bit integer and 7 bit fractional part, ranging from -16 (0x800) to +15.992 (0x7FF).
  898. isp_write_reg(dev, REG_ADDR(cross_talk_coef_block_arr[i]),
  899. MRV_ISP_CT_COEFF_MASK & (xtalk.lCoeff[i] << 1));
  900. #else // Coefficient for cross talk matrix.Values are 11-bit signed fixed-point numbers with 4 bit integer and 7 bit fractional part, ranging from -8 (0x400) to +7.992 (0x3FF).
  901. isp_write_reg(dev, REG_ADDR(cross_talk_coef_block_arr[i]),
  902. MRV_ISP_CT_COEFF_MASK & xtalk.lCoeff[i]);
  903. #endif
  904. }
  905. isp_write_reg(dev, REG_ADDR(isp_ct_offset_r),
  906. (MRV_ISP_CT_OFFSET_R_MASK & xtalk.r));
  907. isp_write_reg(dev, REG_ADDR(isp_ct_offset_g),
  908. (MRV_ISP_CT_OFFSET_G_MASK & xtalk.g));
  909. isp_write_reg(dev, REG_ADDR(isp_ct_offset_b),
  910. (MRV_ISP_CT_OFFSET_B_MASK & xtalk.b));
  911. return 0;
  912. }
  913. int isp_enable_wb(struct isp_ic_dev *dev, bool bEnable)
  914. {
  915. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  916. isp_info("enter %s\n", __func__);
  917. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_AWB_ENABLE, bEnable);
  918. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  919. isp_info("exit %s\n", __func__);
  920. return 0;
  921. }
  922. int isp_enable_gamma_out(struct isp_ic_dev *dev, bool bEnable)
  923. {
  924. u32 isp_ctrl;
  925. struct isp_gamma_out_context *gamma = &dev->gamma_out;
  926. isp_info("enter %s\n", __func__);
  927. gamma->enableGamma = bEnable;
  928. if(gamma->changed || !is_isp_enable(dev))
  929. {
  930. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  931. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_OUT_ENABLE, bEnable);
  932. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  933. gamma->changed = false;
  934. } else {
  935. gamma->changed = true;
  936. }
  937. isp_info("exit %s\n", __func__);
  938. return 0;
  939. }
  940. int isp_s_gamma_out(struct isp_ic_dev *dev)
  941. {
  942. u32 isp_gamma_out_mode;
  943. int i;
  944. u32 isp_ctrl;
  945. struct isp_gamma_out_context *gamma = &dev->gamma_out;
  946. if(gamma->changed || !is_isp_enable(dev)) {
  947. isp_gamma_out_mode = isp_read_reg(dev, REG_ADDR(isp_gamma_out_mode));
  948. REG_SET_SLICE(isp_gamma_out_mode, MRV_ISP_EQU_SEGM, gamma->mode);
  949. isp_write_reg(dev, REG_ADDR(isp_gamma_out_mode), isp_gamma_out_mode);
  950. for (i = 0; i < 17; i++) {
  951. isp_write_reg(dev, REG_ADDR(gamma_out_y_block_arr[i]),
  952. MRV_ISP_ISP_GAMMA_OUT_Y_MASK & gamma->curve[i]);
  953. }
  954. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  955. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_OUT_ENABLE, gamma->enableGamma);
  956. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  957. gamma->changed = false;
  958. } else {
  959. gamma->changed = true;
  960. }
  961. return 0;
  962. }
  963. int isp_s_lsc_tbl(struct isp_ic_dev *dev)
  964. {
  965. int i, n;
  966. u32 isp_ctrl;
  967. u32 sram_addr;
  968. u32 isp_lsc_status;
  969. struct isp_lsc_context *lsc = (&dev->lsc);
  970. //isp_debug("enter %s\n", __func__);
  971. /*need to set tbl after isp_ctrl enable In ISP8000NANO_V1802*/
  972. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  973. /* Enable isp to enable ram clock for write correct table to ram. */
  974. if (!(isp_ctrl & 0x01)) {
  975. dev->update_lsc_tbl = true;
  976. return 0;
  977. }
  978. isp_lsc_status = isp_read_reg(dev, REG_ADDR(isp_lsc_status));
  979. sram_addr = (isp_lsc_status & 0x2U) ? 0U : 153U;
  980. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_addr), sram_addr);
  981. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_addr), sram_addr);
  982. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_addr), sram_addr);
  983. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_addr), sram_addr);
  984. #ifdef ISP_LSC_V2
  985. for (n = 0; n < ((CAMERIC_MAX_LSC_SECTORS + 1) * (CAMERIC_MAX_LSC_SECTORS + 1)); n += CAMERIC_MAX_LSC_SECTORS + 1) {
  986. for (i = 0; i < (CAMERIC_MAX_LSC_SECTORS); i += 2) {
  987. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), (lsc->r[n + i] & 0xFFF) | ((lsc->r[n + i + 1] & 0xFFF) << 12) | ((lsc->r[n + i] >> 12) << 24) | ((lsc->r[n + i + 1] >> 12) << 28));
  988. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), (lsc->gr[n + i] & 0xFFF) | ((lsc->gr[n + i + 1] & 0xFFF) << 12) | ((lsc->gr[n + i] >> 12) << 24) | ((lsc->gr[n + i + 1] >> 12) << 28));
  989. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), (lsc->gb[n + i] & 0xFFF) | ((lsc->gb[n + i + 1] & 0xFFF) << 12) | ((lsc->gb[n + i] >> 12) << 24) | ((lsc->gb[n + i + 1] >> 12) << 28));
  990. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), (lsc->b[n + i] & 0xFFF) | ((lsc->b[n + i + 1] & 0xFFF) << 12) | ((lsc->b[n + i] >> 12) << 24) | ((lsc->b[n + i + 1] >> 12) << 28));
  991. }
  992. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), (lsc->r[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->r[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  993. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), (lsc->gr[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->gr[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  994. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), (lsc->gb[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->gb[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  995. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), (lsc->b[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->b[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  996. }
  997. #else
  998. for (n = 0;
  999. n <
  1000. ((CAMERIC_MAX_LSC_SECTORS + 1) * (CAMERIC_MAX_LSC_SECTORS + 1));
  1001. n += CAMERIC_MAX_LSC_SECTORS + 1) {
  1002. /* 17 sectors with 2 values in one DWORD = 9 DWORDs (8 steps + 1 outside loop) */
  1003. for (i = 0; i < (CAMERIC_MAX_LSC_SECTORS); i += 2) {
  1004. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data),
  1005. lsc->r[n +
  1006. i] | (lsc->r[n + i + 1] << 12));
  1007. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data),
  1008. lsc->gr[n +
  1009. i] | (lsc->gr[n + i + 1] << 12));
  1010. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data),
  1011. lsc->gb[n +
  1012. i] | (lsc->gb[n + i + 1] << 12));
  1013. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data),
  1014. lsc->b[n +
  1015. i] | (lsc->b[n + i + 1] << 12));
  1016. }
  1017. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data),
  1018. lsc->r[n + CAMERIC_MAX_LSC_SECTORS]);
  1019. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data),
  1020. lsc->gr[n + CAMERIC_MAX_LSC_SECTORS]);
  1021. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data),
  1022. lsc->gb[n + CAMERIC_MAX_LSC_SECTORS]);
  1023. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data),
  1024. lsc->b[n + CAMERIC_MAX_LSC_SECTORS]);
  1025. }
  1026. #endif
  1027. isp_write_reg(dev, REG_ADDR(isp_lsc_table_sel),
  1028. (isp_lsc_status & 0x2U) ? 0U : 1U);
  1029. //isp_info("exit %s\n", __func__);
  1030. return 0;
  1031. }
  1032. int isp_s_lsc_sec(struct isp_ic_dev *dev)
  1033. {
  1034. int i;
  1035. struct isp_lsc_context *lsc = (&dev->lsc);
  1036. /* isp_info("enter %s\n", __func__); */
  1037. for (i = 0; i < CAEMRIC_GRAD_TBL_SIZE; i += 2) {
  1038. isp_write_reg(dev, REG_ADDR(isp_lsc_xsize_01) + i * 2,
  1039. (lsc->x_size[i] & MRV_LSC_Y_SECT_SIZE_0_MASK) |
  1040. ((lsc->x_size[i + 1]
  1041. << MRV_LSC_X_SECT_SIZE_1_SHIFT)
  1042. & MRV_LSC_X_SECT_SIZE_1_MASK));
  1043. isp_write_reg(dev, REG_ADDR(isp_lsc_ysize_01) + i * 2,
  1044. (lsc->y_size[i] & MRV_LSC_Y_SECT_SIZE_0_MASK) |
  1045. ((lsc->y_size[i + 1]
  1046. << MRV_LSC_Y_SECT_SIZE_1_SHIFT)
  1047. & MRV_LSC_Y_SECT_SIZE_1_MASK));
  1048. isp_write_reg(dev, REG_ADDR(isp_lsc_xgrad_01) + i * 2,
  1049. (lsc->x_grad[i] & MRV_LSC_XGRAD_0_MASK) |
  1050. ((lsc->x_grad[i + 1]
  1051. << MRV_LSC_XGRAD_1_SHIFT)
  1052. & MRV_LSC_XGRAD_1_MASK));
  1053. isp_write_reg(dev, REG_ADDR(isp_lsc_ygrad_01) + i * 2,
  1054. (lsc->y_grad[i] & MRV_LSC_YGRAD_0_MASK) |
  1055. ((lsc->y_grad[i + 1]
  1056. << MRV_LSC_YGRAD_1_SHIFT)
  1057. & MRV_LSC_YGRAD_1_MASK));
  1058. }
  1059. return 0;
  1060. }
  1061. int isp_ioc_read_mis(struct isp_ic_dev *dev, void __user *args)
  1062. {
  1063. isp_mis_list_t* pCList = &dev->circle_list;
  1064. isp_mis_t mis_data;
  1065. u64 ary[2];
  1066. int ret = -1;
  1067. ret = isp_irq_read_circle_queue(&mis_data, pCList);
  1068. if (ret < 0) {
  1069. /*isp_info("%s can not dequeue mis data\n", __func__);*/
  1070. return ret;
  1071. }
  1072. /*isp_info("%s irq src %d val 0x%08x\n", __func__, mis_data.irq_src, mis_data.val);*/
  1073. ary[0] = mis_data.irq_src;
  1074. ary[1] = mis_data.val;
  1075. viv_check_retval(copy_to_user(args, ary, sizeof( ary)));
  1076. return 0;
  1077. }
  1078. static int isp_ioc_read_reg(struct isp_ic_dev *dev, void __user * args)
  1079. {
  1080. struct isp_reg_t reg;
  1081. viv_check_retval(copy_from_user(&reg, args, sizeof(reg)));
  1082. reg.val = isp_read_reg(dev, reg.offset);
  1083. viv_check_retval(copy_to_user(args, &reg, sizeof(reg)));
  1084. return 0;
  1085. }
  1086. static int isp_ioc_write_reg(struct isp_ic_dev *dev, void __user *args)
  1087. {
  1088. struct isp_reg_t reg;
  1089. viv_check_retval((copy_from_user(&reg, args, sizeof(reg))));
  1090. isp_write_reg(dev, reg.offset, reg.val);
  1091. return 0;
  1092. }
  1093. int isp_ioc_disable_isp_off(struct isp_ic_dev *dev, void __user *args)
  1094. {
  1095. u32 isp_imsc;
  1096. isp_info("enter %s\n", __func__);
  1097. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1098. isp_imsc &= ~MRV_ISP_IMSC_ISP_OFF_MASK;
  1099. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  1100. isp_info("exit %s\n", __func__);
  1101. return 0;
  1102. }
  1103. int isp_g_awbmean(struct isp_ic_dev *dev, struct isp_awb_mean *mean)
  1104. {
  1105. u32 reg = isp_read_reg(dev, REG_ADDR(isp_awb_mean));
  1106. /* isp_info("enter %s\n", __func__); */
  1107. mean->g = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_Y__G);
  1108. mean->b = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_CB__B);
  1109. mean->r = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_CR__R);
  1110. mean->no_white_count = isp_read_reg(dev, REG_ADDR(isp_awb_white_cnt));
  1111. return 0;
  1112. }
  1113. int isp_s_ee(struct isp_ic_dev *dev)
  1114. {
  1115. #ifndef ISP_EE
  1116. //isp_err("unsupported function: %s\n", __func__);
  1117. return -EINVAL;
  1118. #else
  1119. struct isp_ee_context *ee = &dev->ee;
  1120. u32 isp_ee_ctrl = isp_read_reg(dev, REG_ADDR(isp_ee_ctrl));
  1121. u32 gain = 0;
  1122. //isp_info("enter %s\n", __func__);
  1123. if (!ee->enable) {
  1124. isp_write_reg(dev, REG_ADDR(isp_ee_ctrl),
  1125. isp_ee_ctrl & ~EE_CTRL_ENABLE_MASK);
  1126. return 0;
  1127. }
  1128. REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_INPUT_SEL, ee->input_sel);
  1129. REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_SOURCE_STRENGTH, ee->src_strength);
  1130. REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_STRENGTH, ee->strength);
  1131. REG_SET_SLICE(gain, EE_UV_GAIN, ee->uv_gain);
  1132. REG_SET_SLICE(gain, EE_EDGE_GAIN, ee->edge_gain);
  1133. isp_write_reg(dev, REG_ADDR(isp_ee_y_gain), ee->y_gain);
  1134. isp_write_reg(dev, REG_ADDR(isp_ee_uv_gain), gain);
  1135. isp_write_reg(dev, REG_ADDR(isp_ee_ctrl),
  1136. isp_ee_ctrl | EE_CTRL_ENABLE_MASK);
  1137. //isp_info("exit %s\n", __func__);
  1138. return 0;
  1139. #endif
  1140. }
  1141. int isp_s_exp(struct isp_ic_dev *dev)
  1142. {
  1143. struct isp_exp_context *exp = &dev->exp;
  1144. u32 isp_exp_ctrl = isp_read_reg(dev, REG_ADDR(isp_exp_ctrl));
  1145. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1146. isp_info("enter %s\n", __func__);
  1147. if (!exp->enable) {
  1148. REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_START, 0);
  1149. isp_write_reg(dev, REG_ADDR(isp_exp_ctrl), isp_exp_ctrl);
  1150. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1151. isp_imsc & ~MRV_ISP_IMSC_EXP_END_MASK);
  1152. return 0;
  1153. }
  1154. isp_write_reg(dev, REG_ADDR(isp_exp_h_offset),
  1155. (MRV_AE_ISP_EXP_H_OFFSET_MASK & exp->window.x));
  1156. isp_write_reg(dev, REG_ADDR(isp_exp_v_offset),
  1157. (MRV_AE_ISP_EXP_V_OFFSET_MASK & exp->window.y));
  1158. isp_write_reg(dev, REG_ADDR(isp_exp_h_size),
  1159. (MRV_AE_ISP_EXP_H_SIZE_MASK & exp->window.width));
  1160. isp_write_reg(dev, REG_ADDR(isp_exp_v_size),
  1161. (MRV_AE_ISP_EXP_V_SIZE_MASK & exp->window.height));
  1162. #ifdef ISP_AE_SHADOW
  1163. isp_write_reg(dev, REG_ADDR(isp_exp_h_offset_shd),
  1164. (MRV_AE_ISP_EXP_H_OFFSET_MASK & exp->window.x));
  1165. isp_write_reg(dev, REG_ADDR(isp_exp_v_offset_shd),
  1166. (MRV_AE_ISP_EXP_V_OFFSET_MASK & exp->window.y));
  1167. isp_write_reg(dev, REG_ADDR(isp_exp_h_size_shd),
  1168. (MRV_AE_ISP_EXP_H_SIZE_MASK & exp->window.width));
  1169. isp_write_reg(dev, REG_ADDR(isp_exp_v_size_shd),
  1170. (MRV_AE_ISP_EXP_V_SIZE_MASK & exp->window.height));
  1171. #endif
  1172. REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_MEAS_MODE, exp->mode);
  1173. REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_START, 1);
  1174. isp_write_reg(dev, REG_ADDR(isp_exp_ctrl), isp_exp_ctrl);
  1175. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1176. isp_imsc | MRV_ISP_IMSC_EXP_END_MASK);
  1177. isp_info("exit %s\n", __func__);
  1178. return 0;
  1179. }
  1180. int isp_s_hdrexp(struct isp_ic_dev *dev)
  1181. {
  1182. struct isp_exp_context *hdrexp = &dev->hdrexp;
  1183. u32 isp_hdr_exp_conf = isp_read_reg(dev, REG_ADDR(isp_hdr_exp_conf));
  1184. u32 isp_stitching_imsc = isp_read_reg(dev, REG_ADDR(isp_stitching_imsc));
  1185. isp_info("enter %s\n", __func__);
  1186. if (!dev->hdrexp.enable) {
  1187. isp_info("%s, hdr disabled\n",__func__);
  1188. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_START, 0);
  1189. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_conf), isp_hdr_exp_conf);
  1190. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc & ~0x38);
  1191. return 0;
  1192. }
  1193. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_h_offset),
  1194. (MRV_ISP_HDR_EXP_H_OFFSET_MASK & hdrexp->window.x));
  1195. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_v_offset),
  1196. (MRV_ISP_HDR_EXP_V_OFFSET_MASK & hdrexp->window.y));
  1197. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_h_size),
  1198. (MRV_ISP_HDR_EXP_H_SIZE_MASK & hdrexp->window.width));
  1199. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_v_size),
  1200. (MRV_ISP_HDR_EXP_V_SIZE_MASK & hdrexp->window.height));
  1201. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_MEAS_MODE, hdrexp->mode);
  1202. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_SRC_SEL, 1); //hardware only support 1
  1203. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_START, 1);
  1204. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_conf), isp_hdr_exp_conf);
  1205. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc | 0x38);
  1206. return 0;
  1207. }
  1208. int isp_g_expmean(struct isp_ic_dev *dev, u8 *mean)
  1209. {
  1210. int i = 0;
  1211. /* isp_info("enter %s\n", __func__); */
  1212. if (!dev || !mean)
  1213. return -EINVAL;
  1214. for (; i < 25; i++) {
  1215. mean[i] = isp_read_reg(dev, REG_ADDR(isp_exp_mean_00) + i * 4);
  1216. }
  1217. return 0;
  1218. }
  1219. int isp_g_hdrexpmean(struct isp_ic_dev *dev, u8 * mean)
  1220. {
  1221. int i = 0;
  1222. isp_info("enter %s\n", __func__);
  1223. if (!dev || !mean)
  1224. return -EINVAL;
  1225. for (; i < 75; i++) {
  1226. mean[i] = isp_read_reg(dev, REG_ADDR(isp_hdr_exp_statistics[i]));
  1227. }
  1228. return 0;
  1229. }
  1230. #ifdef ISP_HIST256
  1231. #define HIST_BIN_TOTAL 256
  1232. #else
  1233. #define HIST_BIN_TOTAL 16
  1234. #endif
  1235. int isp_s_hist(struct isp_ic_dev *dev)
  1236. {
  1237. struct isp_hist_context *hist = &dev->hist;
  1238. #ifdef ISP_HIST256
  1239. u32 isp_hist256_prop = isp_read_reg(dev, REG_ADDR(isp_hist256_prop));
  1240. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1241. int i;
  1242. if (!hist->enable) {
  1243. REG_SET_SLICE(isp_hist256_prop, MRV_HIST_MODE,
  1244. MRV_HIST_MODE_NONE);
  1245. isp_write_reg(dev, REG_ADDR(isp_hist256_prop),
  1246. isp_hist256_prop);
  1247. //isp_write_reg(dev, REG_ADDR(isp_imsc),
  1248. // isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1249. return 0;
  1250. }
  1251. isp_write_reg(dev, REG_ADDR(isp_hist256_h_offs),
  1252. (MRV_HIST_H_OFFSET_MASK & hist->window.x));
  1253. isp_write_reg(dev, REG_ADDR(isp_hist256_v_offs),
  1254. (MRV_HIST_V_OFFSET_MASK & hist->window.y));
  1255. isp_write_reg(dev, REG_ADDR(isp_hist256_h_size),
  1256. (MRV_HIST_H_SIZE_MASK & hist->window.width));
  1257. isp_write_reg(dev, REG_ADDR(isp_hist256_v_size),
  1258. (MRV_HIST_V_SIZE_MASK & hist->window.height));
  1259. for (i = 0; i < 24; i += 4) {
  1260. isp_write_reg(dev, REG_ADDR(isp_hist256_weight_00to30) + i,
  1261. hist->weight[i +
  1262. 0] | (hist->weight[i +
  1263. 1] << 8) |
  1264. (hist->weight[i + 2] << 16) | (hist->weight[i +
  1265. 3] <<
  1266. 24));
  1267. }
  1268. isp_write_reg(dev, REG_ADDR(isp_hist256_weight_44), hist->weight[24]);
  1269. REG_SET_SLICE(isp_hist256_prop, MRV_HIST_STEPSIZE, hist->step_size);
  1270. REG_SET_SLICE(isp_hist256_prop, MRV_HIST_MODE, hist->mode);
  1271. isp_write_reg(dev, REG_ADDR(isp_hist256_prop), isp_hist256_prop);
  1272. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1273. isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1274. #else
  1275. u32 isp_hist_prop = isp_read_reg(dev, REG_ADDR(isp_hist_prop));
  1276. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1277. int i;
  1278. isp_info("enter %s\n", __func__);
  1279. if (!hist->enable) {
  1280. REG_SET_SLICE(isp_hist_prop, MRV_HIST_MODE, MRV_HIST_MODE_NONE);
  1281. isp_write_reg(dev, REG_ADDR(isp_hist_prop), isp_hist_prop);
  1282. //isp_write_reg(dev, REG_ADDR(isp_imsc),
  1283. // isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1284. return 0;
  1285. }
  1286. isp_write_reg(dev, REG_ADDR(isp_hist_h_offs),
  1287. (MRV_HIST_H_OFFSET_MASK & hist->window.x));
  1288. isp_write_reg(dev, REG_ADDR(isp_hist_v_offs),
  1289. (MRV_HIST_V_OFFSET_MASK & hist->window.y));
  1290. isp_write_reg(dev, REG_ADDR(isp_hist_h_size),
  1291. (MRV_HIST_H_SIZE_MASK & hist->window.width));
  1292. isp_write_reg(dev, REG_ADDR(isp_hist_v_size),
  1293. (MRV_HIST_V_SIZE_MASK & hist->window.height));
  1294. for (i = 0; i < 24; i += 4) {
  1295. isp_write_reg(dev, REG_ADDR(isp_hist_weight_00to30) + i,
  1296. hist->weight[i + 0] |
  1297. (hist->weight[i + 1] << 8) |
  1298. (hist->weight[i + 2] << 16) |
  1299. (hist->weight[i + 3] << 24));
  1300. }
  1301. isp_write_reg(dev, REG_ADDR(isp_hist_weight_44), hist->weight[24]);
  1302. REG_SET_SLICE(isp_hist_prop, MRV_HIST_STEPSIZE, hist->step_size);
  1303. REG_SET_SLICE(isp_hist_prop, MRV_HIST_MODE, hist->mode);
  1304. isp_write_reg(dev, REG_ADDR(isp_hist_prop), isp_hist_prop);
  1305. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1306. isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1307. isp_info("exit %s\n", __func__);
  1308. #endif
  1309. return 0;
  1310. }
  1311. int isp_s_hdrhist(struct isp_ic_dev *dev)
  1312. {
  1313. struct isp_hist_context *hdrhist = &dev->hdrhist;
  1314. u32 isp_hdr_hist_prop = isp_read_reg(dev, REG_ADDR(isp_hdr_hist_prop));
  1315. u32 isp_stitching_imsc = isp_read_reg(dev, REG_ADDR(isp_stitching_imsc));
  1316. isp_info("enter %s\n", __func__);
  1317. if (!dev->hdrhist.enable) {
  1318. isp_info("%s, hdr disable\n", __func__);
  1319. REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_MODE, MRV_HIST_MODE_NONE);
  1320. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_prop), isp_hdr_hist_prop);
  1321. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc),
  1322. isp_stitching_imsc & ~0x1c0);
  1323. return 0;
  1324. }
  1325. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_h_offs),
  1326. (MRV_HIST_H_OFFSET_MASK & hdrhist->window.x));
  1327. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_v_offs),
  1328. (MRV_HIST_V_OFFSET_MASK & hdrhist->window.y));
  1329. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_h_size),
  1330. (MRV_HIST_H_SIZE_MASK & hdrhist->window.width));
  1331. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_v_size),
  1332. (MRV_HIST_V_SIZE_MASK & hdrhist->window.height));
  1333. REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_STEPSIZE, hdrhist->step_size);
  1334. REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_MODE, hdrhist->mode);
  1335. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_prop), isp_hdr_hist_prop);
  1336. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc | 0x1c0);
  1337. return 0;
  1338. }
  1339. int isp_g_histmean(struct isp_ic_dev *dev, u32 *mean)
  1340. {
  1341. int i = 0;
  1342. /* isp_info("enter %s\n", __func__); */
  1343. if (!dev || !mean)
  1344. return -EINVAL;
  1345. #ifdef ISP_HIST256
  1346. for (; i < HIST_BIN_TOTAL; i++) {
  1347. mean[i] = isp_read_reg(dev, REG_ADDR(isp_hist256_bin_n));
  1348. }
  1349. #else
  1350. for (; i < HIST_BIN_TOTAL; i++) {
  1351. mean[i] = isp_read_reg(dev,
  1352. REG_ADDR(histogram_measurement_result_arr[i]));
  1353. }
  1354. #endif
  1355. return 0;
  1356. }
  1357. int isp_g_hdrhistmean(struct isp_ic_dev *dev, u32 * mean)
  1358. {
  1359. int i = 0;
  1360. isp_info("enter %s\n", __func__);
  1361. if (!dev || !mean)
  1362. return -EINVAL;
  1363. // size is fixed 48 now, contain 3 channels
  1364. for (; i < 48; i++) {
  1365. mean[i] = isp_read_reg(dev, REG_ADDR(isp_hdr_hist_statistics[i]));
  1366. }
  1367. return 0;
  1368. }
  1369. int isp_s_hist64(struct isp_ic_dev *dev)
  1370. {
  1371. #ifndef ISP_HIST64
  1372. //isp_err("Not supported hist64 module\n");
  1373. return -1;
  1374. #else
  1375. struct isp_hist64_context *hist64 = &dev->hist64;
  1376. u32 isp64_hist_prop = isp_read_reg(dev, REG_ADDR(isp64_hist_prop));
  1377. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1378. u32 isp64_hist_subsampling = isp_read_reg(dev, REG_ADDR(isp64_hist_subsampling));
  1379. u32 isp64_hist_sample_range = isp_read_reg(dev, REG_ADDR(isp64_hist_sample_range));
  1380. u32 isp64_hist_coeff_r = 0, isp64_hist_coeff_g = 0, isp64_hist_coeff_b = 0;
  1381. int i;
  1382. if (!hist64->enable) {
  1383. REG_SET_SLICE(isp64_hist_prop, MRV_HIST_MODE,
  1384. MRV_HIST_MODE_NONE);
  1385. isp_write_reg(dev, REG_ADDR(isp64_hist_prop),
  1386. isp64_hist_prop);
  1387. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1388. isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1389. //isp_write_reg(dev, REG_ADDR(isp64_hist_ctrl),
  1390. /// hist64->enable & ~MRV_HIST_UPDATE_ENABLE_MASK);
  1391. return 0;
  1392. }
  1393. isp_write_reg(dev, REG_ADDR(isp64_hist_h_offs),
  1394. (MRV_HIST_H_OFFSET_MASK & hist64->window.x));
  1395. isp_write_reg(dev, REG_ADDR(isp64_hist_v_offs),
  1396. (MRV_HIST_V_OFFSET_MASK & hist64->window.y));
  1397. isp_write_reg(dev, REG_ADDR(isp64_hist_h_size),
  1398. (MRV_HIST_H_SIZE_MASK & hist64->window.width));
  1399. isp_write_reg(dev, REG_ADDR(isp64_hist_v_size),
  1400. (MRV_HIST_V_SIZE_MASK & hist64->window.height));
  1401. for (i = 0; i < 24; i += 4) {
  1402. isp_write_reg(dev, REG_ADDR(isp64_hist_weight_00to30) + i,
  1403. hist64->weight[i +
  1404. 0] | (hist64->weight[i +
  1405. 1] << 8) |
  1406. (hist64->weight[i + 2] << 16) | (hist64->weight[i +
  1407. 3] <<
  1408. 24));
  1409. }
  1410. isp_write_reg(dev, REG_ADDR(isp64_hist_weight_44), hist64->weight[24]);
  1411. REG_SET_SLICE(isp64_hist_prop, MRV_HIST_CHANNEL_SELECT, hist64->channel);
  1412. REG_SET_SLICE(isp64_hist_prop, MRV_HIST_MODE, hist64->mode);
  1413. REG_SET_SLICE(isp64_hist_subsampling, MRV_HIST_V_STEPSIZE, hist64->vStepSize);
  1414. REG_SET_SLICE(isp64_hist_subsampling, MRV_HIST_H_STEP_INC, hist64->hStepInc);
  1415. REG_SET_SLICE(isp64_hist_sample_range, MRV_HIST_SAMPLE_OFFSET, hist64->sample_offset);
  1416. REG_SET_SLICE(isp64_hist_sample_range, MRV_HIST_SAMPLE_SHIFT, hist64->sample_shift);
  1417. REG_SET_SLICE(isp64_hist_coeff_r, MRV_HIST_COEFF_R, hist64->r_coeff);
  1418. REG_SET_SLICE(isp64_hist_coeff_g, MRV_HIST_COEFF_G, hist64->g_coeff);
  1419. REG_SET_SLICE(isp64_hist_coeff_b, MRV_HIST_COEFF_B, hist64->b_coeff);
  1420. isp_write_reg(dev, REG_ADDR(isp64_hist_subsampling), isp64_hist_subsampling);
  1421. isp_write_reg(dev, REG_ADDR(isp64_hist_sample_range), isp64_hist_sample_range);
  1422. isp_write_reg(dev, REG_ADDR(isp64_hist_prop), isp64_hist_prop);
  1423. isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_r), isp64_hist_coeff_r);
  1424. isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_g), isp64_hist_coeff_g);
  1425. isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_b), isp64_hist_coeff_b);
  1426. isp_write_reg(dev, REG_ADDR(isp64_hist_ctrl),
  1427. hist64->enable);
  1428. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1429. isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1430. return 0;
  1431. #endif
  1432. }
  1433. #define HIST64_BIN_TOTAL 32
  1434. int isp_g_hist64mean(struct isp_ic_dev *dev, u32 *mean)
  1435. {
  1436. #ifndef ISP_HIST64
  1437. //isp_err("Not supported hist64 module\n");
  1438. return -1;
  1439. #else
  1440. int i = 0;
  1441. isp_info("enter %s\n", __func__);
  1442. if (!dev || !mean)
  1443. return -EINVAL;
  1444. for (; i < HIST64_BIN_TOTAL; i++) {
  1445. mean[i] = isp_read_reg(dev,
  1446. REG_ADDR(isp64_histogram_measurement_result_arr[i]));
  1447. }
  1448. isp_info("exit %s\n", __func__);
  1449. return 0;
  1450. #endif
  1451. }
  1452. int isp_g_hist64_vstart_status(struct isp_ic_dev *dev, u32 *status)
  1453. {
  1454. #ifndef ISP_HIST64
  1455. //isp_err("Not supported hist64 module\n");
  1456. return -1;
  1457. #else
  1458. /* isp_info("enter %s\n", __func__); */
  1459. if (!dev || !status)
  1460. return -EINVAL;
  1461. *status = isp_read_reg(dev, REG_ADDR(isp64_hist_vstart_status));
  1462. return 0;
  1463. #endif
  1464. }
  1465. int isp_update_hist64(struct isp_ic_dev *dev)
  1466. {
  1467. #ifndef ISP_HIST64
  1468. //isp_err("Not supported hist64\n");
  1469. return -1;
  1470. #else
  1471. struct isp_hist64_context* hist64 =&dev->hist64;
  1472. isp_write_reg(dev, REG_ADDR(isp64_hist_forced_upd_start_line),hist64->forced_upd_start_line);
  1473. isp_write_reg(dev, REG_ADDR(isp64_hist_forced_update), hist64->forced_upd);
  1474. return 0;
  1475. #endif
  1476. }
  1477. int isp_s_ge(struct isp_ic_dev *dev)
  1478. {
  1479. #ifndef ISP_GREENEQUILIBRATE
  1480. //isp_err("unsupported function %s\n", __func__);
  1481. return -1;
  1482. #else
  1483. struct isp_ge_context *ge = &dev->ge;
  1484. u32 green_equilibrate_ctrl =
  1485. isp_read_reg(dev, REG_ADDR(green_equilibrate_ctrl));
  1486. u32 green_equilibrate_hcnt_dummy = 0;
  1487. isp_info("enter %s\n", __func__);
  1488. if (!ge->enable) {
  1489. REG_SET_SLICE(green_equilibrate_ctrl,
  1490. ISP_GREEN_EQUILIBTATE_ENABLE, 0);
  1491. isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl),
  1492. green_equilibrate_ctrl);
  1493. return 0;
  1494. }
  1495. REG_SET_SLICE(green_equilibrate_ctrl, ISP_GREEN_EQUILIBTATE_TH,
  1496. ge->threshold);
  1497. REG_SET_SLICE(green_equilibrate_ctrl, ISP_GREEN_EQUILIBTATE_ENABLE, 1);
  1498. REG_SET_SLICE(green_equilibrate_hcnt_dummy,
  1499. ISP_GREEN_EQUILIBTATE_HCNT_DUMMY, ge->h_dummy);
  1500. isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl),
  1501. green_equilibrate_ctrl);
  1502. isp_write_reg(dev, REG_ADDR(green_equilibrate_hcnt_dummy),
  1503. green_equilibrate_hcnt_dummy);
  1504. isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl_shd),
  1505. green_equilibrate_ctrl);
  1506. isp_info("exit %s\n", __func__);
  1507. return 0;
  1508. #endif
  1509. }
  1510. int isp_s_ca(struct isp_ic_dev *dev)
  1511. {
  1512. #ifndef ISP_CA
  1513. //isp_err("unsupported function %s\n", __func__);
  1514. return -1;
  1515. #else
  1516. struct isp_ca_context *ca = &dev->ca;
  1517. u32 isp_curve_ctrl = isp_read_reg(dev, REG_ADDR(isp_curve_ctrl));
  1518. // u32 isp_curve_lut_x_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_x_addr));
  1519. // u32 isp_curve_lut_luma_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_luma_addr));
  1520. // u32 isp_curve_lut_chroma_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_chroma_addr));
  1521. // u32 isp_curve_lut_shift_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_shift_addr));
  1522. int i = 0;
  1523. /*isp_info("enter %s\n", __func__);*/
  1524. if (!ca->enable) {
  1525. REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_ENABLE, 0);
  1526. isp_write_reg(dev, REG_ADDR(isp_curve_ctrl), isp_curve_ctrl);
  1527. return 0;
  1528. }
  1529. isp_write_reg(dev, REG_ADDR(isp_curve_lut_x_addr), 0);
  1530. isp_write_reg(dev, REG_ADDR(isp_curve_lut_luma_addr), 0);
  1531. isp_write_reg(dev, REG_ADDR(isp_curve_lut_chroma_addr), 0);
  1532. isp_write_reg(dev, REG_ADDR(isp_curve_lut_shift_addr), 0);
  1533. for (i = 0; i < CA_CURVE_DATA_TABLE_LEN; i++) {
  1534. isp_write_reg(dev, REG_ADDR(isp_curve_lut_x_write_data),
  1535. dev->ca.lut_x[i]);
  1536. isp_write_reg(dev, REG_ADDR(isp_curve_lut_luma_write_data),
  1537. dev->ca.lut_luma[i]);
  1538. isp_write_reg(dev, REG_ADDR(isp_curve_lut_chroma_write_data),
  1539. dev->ca.lut_chroma[i]);
  1540. isp_write_reg(dev, REG_ADDR(isp_curve_lut_shift_write_data),
  1541. dev->ca.lut_shift[i]);
  1542. }
  1543. REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_MODE, dev->ca.mode);
  1544. REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_ENABLE, 1);
  1545. isp_write_reg(dev, REG_ADDR(isp_curve_ctrl), isp_curve_ctrl);
  1546. /*isp_info("exit %s\n", __func__);*/
  1547. return 0;
  1548. #endif
  1549. }
  1550. int isp_s_dpcc(struct isp_ic_dev *dev)
  1551. {
  1552. struct isp_dpcc_context *dpcc = &dev->dpcc;
  1553. const u32 reg_gap = 20;
  1554. int i;
  1555. u32 isp_dpcc_mode = isp_read_reg(dev, REG_ADDR(isp_dpcc_mode));
  1556. isp_info("enter %s\n", __func__);
  1557. if (!dpcc->enable) {
  1558. REG_SET_SLICE(isp_dpcc_mode, MRV_DPCC_ISP_DPCC_ENABLE, 0);
  1559. } else {
  1560. REG_SET_SLICE(isp_dpcc_mode, MRV_DPCC_ISP_DPCC_ENABLE, 1);
  1561. }
  1562. isp_write_reg(dev, REG_ADDR(isp_dpcc_mode), dpcc->mode);
  1563. isp_write_reg(dev, REG_ADDR(isp_dpcc_output_mode), dpcc->outmode);
  1564. isp_write_reg(dev, REG_ADDR(isp_dpcc_set_use), dpcc->set_use);
  1565. for (i = 0; i < 3; i++) {
  1566. isp_write_reg(dev, REG_ADDR(isp_dpcc_methods_set_1) + i * 4,
  1567. 0x1FFF & dpcc->methods_set[i]);
  1568. isp_write_reg(dev,
  1569. REG_ADDR(isp_dpcc_line_thresh_1) + i * reg_gap,
  1570. 0xFFFF & dpcc->params[i].line_thresh);
  1571. isp_write_reg(dev,
  1572. REG_ADDR(isp_dpcc_line_mad_fac_1) + i * reg_gap,
  1573. 0x3F3F & dpcc->params[i].line_mad_fac);
  1574. isp_write_reg(dev, REG_ADDR(isp_dpcc_pg_fac_1) + i * reg_gap,
  1575. 0x3F3F & dpcc->params[i].pg_fac);
  1576. isp_write_reg(dev,
  1577. REG_ADDR(isp_dpcc_rnd_thresh_1) + i * reg_gap,
  1578. 0xFFFF & dpcc->params[i].rnd_thresh);
  1579. isp_write_reg(dev, REG_ADDR(isp_dpcc_rg_fac_1) + i * reg_gap,
  1580. 0x3F3F & dpcc->params[i].rg_fac);
  1581. }
  1582. isp_write_reg(dev, REG_ADDR(isp_dpcc_ro_limits), dpcc->ro_limits);
  1583. isp_write_reg(dev, REG_ADDR(isp_dpcc_rnd_offs), dpcc->rnd_offs);
  1584. isp_write_reg(dev, REG_ADDR(isp_dpcc_mode), isp_dpcc_mode);
  1585. isp_info("exit %s\n", __func__);
  1586. return 0;
  1587. }
  1588. int isp_s_flt(struct isp_ic_dev *dev)
  1589. {
  1590. struct flt_denoise_type {
  1591. u32 thresh_sh0;
  1592. u32 thresh_sh1;
  1593. u32 thresh_bl0;
  1594. u32 thresh_bl1;
  1595. u32 stage_select;
  1596. u32 vmode;
  1597. u32 hmode;
  1598. };
  1599. struct flt_sharpen_type {
  1600. u32 fac_sh0;
  1601. u32 fac_sh1;
  1602. u32 fac_mid;
  1603. u32 fac_bl0;
  1604. u32 fac_bl1;
  1605. };
  1606. static struct flt_denoise_type denoise_tbl[] = {
  1607. {0, 0, 0, 0, 6, MRV_FILT_FILT_CHR_V_MODE_STATIC8,
  1608. MRV_FILT_FILT_CHR_H_MODE_BYPASS},
  1609. {18, 33, 8, 2, 6, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1610. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1611. {26, 44, 13, 5, 4, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1612. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1613. {36, 51, 23, 10, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1614. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1615. {41, 67, 26, 15, 3, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1616. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1617. {75, 10, 50, 20, 3, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1618. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1619. {90, 120, 60, 26, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1620. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1621. {120, 150, 80, 51, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1622. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1623. {170, 200, 140, 100, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1624. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1625. {250, 300, 180, 150, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1626. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1627. {1023, 1023, 1023, 1023, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1628. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1629. {1023, 1023, 1023, 1023, 0, MRV_FILT_FILT_CHR_V_MODE_BYPASS,
  1630. MRV_FILT_FILT_CHR_H_MODE_BYPASS},
  1631. };
  1632. static struct flt_sharpen_type sharpen_tbl[] = {
  1633. {0x4, 0x4, 0x4, 0x2, 0x0},
  1634. {0x7, 0x8, 0x6, 0x2, 0x0},
  1635. {0xA, 0xC, 0x8, 0x4, 0x0},
  1636. {0xC, 0x10, 0xA, 0x6, 0x2},
  1637. {0x16, 0x16, 0xC, 0x8, 0x4},
  1638. {0x14, 0x1B, 0x10, 0xA, 0x4},
  1639. {0x1A, 0x20, 0x13, 0xC, 0x6},
  1640. {0x1E, 0x26, 0x17, 0x10, 0x8},
  1641. {0x24, 0x2C, 0x1D, 0x15, 0x0D},
  1642. {0x2A, 0x30, 0x22, 0x1A, 0x14},
  1643. {0x30, 0x3F, 0x28, 0x24, 0x20},
  1644. };
  1645. // isp_info("enter %s\n", __func__);
  1646. if(dev->flt.changed || !is_isp_enable(dev))
  1647. {
  1648. struct isp_flt_context *flt = &dev->flt;
  1649. u32 isp_flt_mode = isp_read_reg(dev, REG_ADDR(isp_filt_mode));
  1650. if (!flt->enable) {
  1651. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_ENABLE, 0);
  1652. isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode);
  1653. return 0;
  1654. }
  1655. if (flt->denoise >= 0) {
  1656. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_sh0),
  1657. denoise_tbl[flt->denoise].thresh_sh0);
  1658. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_sh1),
  1659. denoise_tbl[flt->denoise].thresh_sh1);
  1660. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_bl0),
  1661. denoise_tbl[flt->denoise].thresh_bl0);
  1662. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_bl1),
  1663. denoise_tbl[flt->denoise].thresh_bl1);
  1664. REG_SET_SLICE(isp_flt_mode, MRV_FILT_STAGE1_SELECT,
  1665. denoise_tbl[flt->denoise].stage_select);
  1666. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_CHR_V_MODE,
  1667. denoise_tbl[flt->denoise].vmode);
  1668. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_CHR_H_MODE,
  1669. denoise_tbl[flt->denoise].hmode);
  1670. }
  1671. if (flt->sharpen >= 0) {
  1672. isp_write_reg(dev, REG_ADDR(isp_filt_fac_sh0),
  1673. sharpen_tbl[flt->sharpen].fac_sh0);
  1674. isp_write_reg(dev, REG_ADDR(isp_filt_fac_sh1),
  1675. sharpen_tbl[flt->sharpen].fac_sh1);
  1676. isp_write_reg(dev, REG_ADDR(isp_filt_fac_mid),
  1677. sharpen_tbl[flt->sharpen].fac_mid);
  1678. isp_write_reg(dev, REG_ADDR(isp_filt_fac_bl0),
  1679. sharpen_tbl[flt->sharpen].fac_bl0);
  1680. isp_write_reg(dev, REG_ADDR(isp_filt_fac_bl1),
  1681. sharpen_tbl[flt->sharpen].fac_bl1);
  1682. }
  1683. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_MODE,
  1684. MRV_FILT_FILT_MODE_DYNAMIC);
  1685. isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode);
  1686. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_ENABLE, 1);
  1687. isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode);
  1688. isp_write_reg(dev, REG_ADDR(isp_filt_lum_weight), 0x00032040);
  1689. dev->flt.changed = false;
  1690. } else {
  1691. dev->flt.changed = true;
  1692. }
  1693. isp_info("exit %s\n", __func__);
  1694. return 0;
  1695. }
  1696. int isp_s_cac(struct isp_ic_dev *dev)
  1697. {
  1698. struct isp_cac_context *cac = &dev->cac;
  1699. u32 val = 0;
  1700. u32 isp_cac_ctrl = isp_read_reg(dev, REG_ADDR(isp_cac_ctrl));
  1701. isp_info("enter %s\n", __func__);
  1702. if (!cac->enable) {
  1703. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_CAC_EN, 0);
  1704. isp_write_reg(dev, REG_ADDR(isp_cac_ctrl), isp_cac_ctrl);
  1705. return 0;
  1706. }
  1707. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_H_CLIP_MODE, cac->hmode);
  1708. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_V_CLIP_MODE, cac->vmode);
  1709. isp_write_reg(dev, REG_ADDR(isp_cac_count_start),
  1710. cac->hstart | (cac->vstart << 16));
  1711. isp_write_reg(dev, REG_ADDR(isp_cac_a), cac->ar | (cac->ab << 16));
  1712. isp_write_reg(dev, REG_ADDR(isp_cac_b), cac->br | (cac->bb << 16));
  1713. isp_write_reg(dev, REG_ADDR(isp_cac_c), cac->cr | (cac->cb << 16));
  1714. REG_SET_SLICE(val, MRV_CAC_X_NS, cac->xns);
  1715. REG_SET_SLICE(val, MRV_CAC_X_NF, cac->xnf);
  1716. isp_write_reg(dev, REG_ADDR(isp_cac_x_norm), val);
  1717. val = 0;
  1718. REG_SET_SLICE(val, MRV_CAC_Y_NS, cac->yns);
  1719. REG_SET_SLICE(val, MRV_CAC_Y_NF, cac->ynf);
  1720. isp_write_reg(dev, REG_ADDR(isp_cac_y_norm), val);
  1721. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_CAC_EN, 1);
  1722. isp_write_reg(dev, REG_ADDR(isp_cac_ctrl), isp_cac_ctrl);
  1723. isp_info("exit %s\n", __func__);
  1724. return 0;
  1725. }
  1726. int isp_s_deg(struct isp_ic_dev *dev)
  1727. {
  1728. struct isp_deg_context *deg = &dev->deg;
  1729. int i;
  1730. u32 isp_gamma_dx_lo = 0;
  1731. u32 isp_gamma_dx_hi = 0;
  1732. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  1733. isp_info("enter %s\n", __func__);
  1734. if (!deg->enable) {
  1735. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_IN_ENABLE, 0);
  1736. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  1737. return 0;
  1738. }
  1739. for (i = 0; i < 8; i++) {
  1740. isp_gamma_dx_lo |= deg->segment[i] << (i * 4);
  1741. isp_gamma_dx_hi |= deg->segment[i + 8] << (i * 4);
  1742. }
  1743. isp_write_reg(dev, REG_ADDR(isp_gamma_dx_lo), isp_gamma_dx_lo);
  1744. isp_write_reg(dev, REG_ADDR(isp_gamma_dx_hi), isp_gamma_dx_hi);
  1745. for (i = 0; i < 17; i++) {
  1746. isp_write_reg(dev, REG_ADDR(degamma_r_y_block_arr[i]),
  1747. deg->r[i]);
  1748. isp_write_reg(dev, REG_ADDR(degamma_g_y_block_arr[i]),
  1749. deg->g[i]);
  1750. isp_write_reg(dev, REG_ADDR(degamma_b_y_block_arr[i]),
  1751. deg->b[i]);
  1752. }
  1753. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_IN_ENABLE, 1);
  1754. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  1755. isp_info("exit %s\n", __func__);
  1756. return 0;
  1757. }
  1758. static u32 get_eff_coeff(int decimal)
  1759. {
  1760. u32 value = 0;
  1761. if (decimal <= -6)
  1762. value = 15;
  1763. else if (decimal <= -3)
  1764. value = 14;
  1765. else if (decimal == -2)
  1766. value = 13;
  1767. else if (decimal == -1)
  1768. value = 12;
  1769. else if (decimal == 0)
  1770. value = 0;
  1771. else if (decimal == 1)
  1772. value = 8;
  1773. else if (decimal == 2)
  1774. value = 9;
  1775. else if (decimal < 6)
  1776. value = 10;
  1777. else
  1778. value = 11;
  1779. return value;
  1780. }
  1781. int isp_s_ie(struct isp_ic_dev *dev)
  1782. {
  1783. struct isp_ie_context *ie = &dev->ie;
  1784. u32 img_eff_ctrl = isp_read_reg(dev, REG_ADDR(img_eff_ctrl));
  1785. u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl));
  1786. u32 vi_ircl = isp_read_reg(dev, REG_ADDR(vi_ircl));
  1787. u32 img_eff_tint = isp_read_reg(dev, REG_ADDR(img_eff_tint));
  1788. u32 img_eff_color_sel = isp_read_reg(dev, REG_ADDR(img_eff_color_sel));
  1789. u32 mat[9];
  1790. u32 sharpen = 0;
  1791. int i;
  1792. isp_info("enter %s\n", __func__);
  1793. REG_SET_SLICE(vi_ircl, MRV_VI_IE_SOFT_RST, 1);
  1794. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  1795. if (!ie->enable) {
  1796. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_CFG_UPD,
  1797. MRV_IMGEFF_CFG_UPD_UPDATE);
  1798. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_BYPASS_MODE,
  1799. MRV_IMGEFF_BYPASS_MODE_BYPASS);
  1800. REG_SET_SLICE(vi_iccl, MRV_VI_IE_CLK_ENABLE, 0);
  1801. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  1802. isp_write_reg(dev, REG_ADDR(img_eff_ctrl), img_eff_ctrl);
  1803. return 0;
  1804. }
  1805. REG_SET_SLICE(vi_ircl, MRV_VI_IE_SOFT_RST, 0);
  1806. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  1807. REG_SET_SLICE(vi_iccl, MRV_VI_IE_CLK_ENABLE, 1);
  1808. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  1809. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_EFFECT_MODE, ie->mode);
  1810. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_FULL_RANGE, ie->full_range);
  1811. for (i = 0; i < 9; i++)
  1812. mat[i] = get_eff_coeff(ie->m[i]);
  1813. if (ie->mode == MRV_IMGEFF_EFFECT_MODE_SEPIA) {
  1814. img_eff_tint = isp_read_reg(dev, REG_ADDR(img_eff_tint));
  1815. REG_SET_SLICE(img_eff_tint, MRV_IMGEFF_INCR_CR, ie->tint_cr);
  1816. REG_SET_SLICE(img_eff_tint, MRV_IMGEFF_INCR_CB, ie->tint_cb);
  1817. isp_write_reg(dev, REG_ADDR(img_eff_tint), img_eff_tint);
  1818. } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_COLOR_SEL) {
  1819. REG_SET_SLICE(img_eff_color_sel, MRV_IMGEFF_COLOR_SELECTION,
  1820. ie->color_sel);
  1821. REG_SET_SLICE(img_eff_color_sel, MRV_IMGEFF_COLOR_THRESHOLD,
  1822. ie->color_thresh);
  1823. isp_write_reg(dev, REG_ADDR(img_eff_color_sel),
  1824. img_eff_color_sel);
  1825. } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_EMBOSS) {
  1826. isp_write_reg(dev, REG_ADDR(img_eff_mat_1),
  1827. mat[0] | (mat[1] << 4) | (mat[2] << 8) | (mat[3]
  1828. << 12));
  1829. isp_write_reg(dev, REG_ADDR(img_eff_mat_2),
  1830. mat[4] | (mat[5] << 4) | (mat[6] << 8) | (mat[7]
  1831. << 12));
  1832. isp_write_reg(dev, REG_ADDR(img_eff_mat_3), mat[8]);
  1833. } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_SKETCH ||
  1834. ie->mode == MRV_IMGEFF_EFFECT_MODE_SHARPEN) {
  1835. isp_write_reg(dev, REG_ADDR(img_eff_mat_3),
  1836. (mat[0] << 4) | (mat[1] << 8) | (mat[2] << 12));
  1837. isp_write_reg(dev, REG_ADDR(img_eff_mat_4),
  1838. mat[3] | (mat[4] << 4) | (mat[5] << 8) | (mat[6]
  1839. << 12));
  1840. isp_write_reg(dev, REG_ADDR(img_eff_mat_5),
  1841. mat[7] | (mat[8] << 4));
  1842. REG_SET_SLICE(sharpen, MRV_IMGEFF_SHARP_FACTOR,
  1843. ie->sharpen_factor);
  1844. REG_SET_SLICE(sharpen, MRV_IMGEFF_CORING_THR,
  1845. ie->sharpen_thresh);
  1846. isp_write_reg(dev, REG_ADDR(img_eff_sharpen), sharpen);
  1847. }
  1848. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_CFG_UPD,
  1849. MRV_IMGEFF_CFG_UPD_UPDATE);
  1850. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_BYPASS_MODE,
  1851. MRV_IMGEFF_BYPASS_MODE_PROCESS);
  1852. isp_write_reg(dev, REG_ADDR(img_eff_ctrl), img_eff_ctrl);
  1853. isp_info("exit %s\n", __func__);
  1854. return 0;
  1855. }
  1856. int isp_s_vsm(struct isp_ic_dev *dev)
  1857. {
  1858. struct isp_vsm_context *vsm = &dev->vsm;
  1859. u32 isp_vsm_mode = isp_read_reg(dev, REG_ADDR(isp_vsm_mode));
  1860. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1861. isp_info("enter %s\n", __func__);
  1862. if (!vsm->enable) {
  1863. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_EN, 0);
  1864. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_IRQ_ENABLE, 0);
  1865. isp_write_reg(dev, REG_ADDR(isp_vsm_mode), isp_vsm_mode);
  1866. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1867. isp_imsc & ~MRV_ISP_IMSC_VSM_END_MASK);
  1868. return 0;
  1869. }
  1870. isp_write_reg(dev, REG_ADDR(isp_vsm_h_offs), vsm->window.x);
  1871. isp_write_reg(dev, REG_ADDR(isp_vsm_v_offs), vsm->window.y);
  1872. isp_write_reg(dev, REG_ADDR(isp_vsm_h_size),
  1873. vsm->window.width & 0xFFFFE);
  1874. isp_write_reg(dev, REG_ADDR(isp_vsm_v_size),
  1875. vsm->window.height & 0xFFFFE);
  1876. isp_write_reg(dev, REG_ADDR(isp_vsm_h_segments), vsm->h_seg);
  1877. isp_write_reg(dev, REG_ADDR(isp_vsm_v_segments), vsm->v_seg);
  1878. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_EN, 1);
  1879. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_IRQ_ENABLE, 1);
  1880. isp_write_reg(dev, REG_ADDR(isp_vsm_mode), isp_vsm_mode);
  1881. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1882. isp_imsc | MRV_ISP_IMSC_VSM_END_MASK);
  1883. isp_info("exit %s\n", __func__);
  1884. return 0;
  1885. }
  1886. int isp_g_vsm(struct isp_ic_dev *dev, struct isp_vsm_result *vsm)
  1887. {
  1888. isp_info("enter %s\n", __func__);
  1889. vsm->x = isp_read_reg(dev, REG_ADDR(isp_vsm_delta_h));
  1890. vsm->y = isp_read_reg(dev, REG_ADDR(isp_vsm_delta_v));
  1891. isp_info("exit %s\n", __func__);
  1892. return 0;
  1893. }
  1894. #if 0
  1895. u32 get_afm_shift(u32 count, u32 thresh)
  1896. {
  1897. u32 grad = count;
  1898. u32 shift = 0;
  1899. while (grad > (thresh)) {
  1900. ++shift;
  1901. grad >>= 1;
  1902. }
  1903. return shift;
  1904. }
  1905. #endif
  1906. int isp_s_afm(struct isp_ic_dev *dev)
  1907. {
  1908. struct isp_afm_context *afm = &dev->afm;
  1909. u32 mask =
  1910. (MRV_ISP_IMSC_AFM_FIN_MASK | MRV_ISP_IMSC_AFM_LUM_OF_MASK |
  1911. MRV_ISP_IMSC_AFM_SUM_OF_MASK);
  1912. u32 shift = 0;
  1913. int i;
  1914. u32 isp_afm_ctrl = isp_read_reg(dev, REG_ADDR(isp_afm_ctrl));
  1915. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1916. if (!afm->enable) {
  1917. REG_SET_SLICE(isp_afm_ctrl, MRV_AFM_AFM_EN, 0);
  1918. isp_imsc &= ~mask;
  1919. isp_write_reg(dev, REG_ADDR(isp_afm_ctrl), isp_afm_ctrl);
  1920. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  1921. return 0;
  1922. }
  1923. for (i = 0; i < 3; i++) {
  1924. isp_write_reg(dev, REG_ADDR(isp_afm_lt_a) + i * 8,
  1925. (afm->window[i].x << 16) | afm->window[i].y);
  1926. isp_write_reg(dev, REG_ADDR(isp_afm_rb_a) + i * 8,
  1927. ((afm->window[i].x + afm->window[i].width -
  1928. 1) << 16) | ((afm->window[i].y +
  1929. afm->window[i].height - 1)));
  1930. }
  1931. REG_SET_SLICE(shift, MRV_AFM_LUM_VAR_SHIFT, afm->lum_shift);
  1932. REG_SET_SLICE(shift, MRV_AFM_AFM_VAR_SHIFT, afm->afm_shift);
  1933. isp_write_reg(dev, REG_ADDR(isp_afm_var_shift), shift);
  1934. isp_write_reg(dev, REG_ADDR(isp_afm_thres), afm->thresh);
  1935. REG_SET_SLICE(isp_afm_ctrl, MRV_AFM_AFM_EN, 1);
  1936. isp_imsc |= mask;
  1937. isp_write_reg(dev, REG_ADDR(isp_afm_ctrl), isp_afm_ctrl);
  1938. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  1939. return 0;
  1940. }
  1941. int isp_g_afm(struct isp_ic_dev *dev, struct isp_afm_result *afm)
  1942. {
  1943. afm->sum_a = isp_read_reg(dev, REG_ADDR(isp_afm_sum_a));
  1944. afm->sum_b = isp_read_reg(dev, REG_ADDR(isp_afm_sum_b));
  1945. afm->sum_c = isp_read_reg(dev, REG_ADDR(isp_afm_sum_c));
  1946. afm->lum_a = isp_read_reg(dev, REG_ADDR(isp_afm_lum_a));
  1947. afm->lum_b = isp_read_reg(dev, REG_ADDR(isp_afm_lum_b));
  1948. afm->lum_c = isp_read_reg(dev, REG_ADDR(isp_afm_lum_c));
  1949. return 0;
  1950. }
  1951. int isp_s_exp2_inputsel(struct isp_ic_dev *dev)
  1952. {
  1953. #ifndef ISP_AEV2
  1954. isp_err("unsupported function: %s\n", __func__);
  1955. return -EINVAL;
  1956. #else
  1957. struct isp_exp2_context *exp2 = &dev->exp2;
  1958. u32 isp_expv2_ctrl = isp_read_reg(dev, REG_ADDR(isp_expv2_ctrl));
  1959. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_INPUT_SELECT, exp2->input_select);
  1960. isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl);
  1961. return 0;
  1962. #endif
  1963. }
  1964. int isp_s_exp2_sizeratio(struct isp_ic_dev *dev, u32 h_size)
  1965. {
  1966. #ifndef ISP_AEV2
  1967. isp_err("unsupported function: %s\n", __func__);
  1968. return -EINVAL;
  1969. #else
  1970. u32 size_inv;
  1971. size_inv = isp_read_reg(dev, REG_ADDR(isp_expv2_size_invert));
  1972. REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_H, h_size);
  1973. isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert), size_inv);
  1974. return 0;
  1975. #endif
  1976. }
  1977. int isp_s_exp2(struct isp_ic_dev *dev)
  1978. {
  1979. #ifndef ISP_AEV2
  1980. //isp_err("unsupported function: %s\n", __func__);
  1981. return -EINVAL;
  1982. #else
  1983. u32 miv2_ctrl, miv2_mp_fmt, miv2_mp_bus_id, miv2_mp_ctrl, miv2_ctrl_shd;
  1984. struct isp_exp2_context *exp2 = &dev->exp2;
  1985. u32 isp_expv2_ctrl = isp_read_reg(dev, REG_ADDR(isp_expv2_ctrl));
  1986. u32 grid_w, grid_h;
  1987. u32 size, offset, size_inv, weight;
  1988. isp_info("enter %s\n", __func__);
  1989. grid_w = ((exp2->window.width - 1) >> 6) << 1;
  1990. grid_h = ((exp2->window.height - 1) >> 6) << 1;
  1991. if (!exp2->enable) {
  1992. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_ENABLE, 0);
  1993. isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl);
  1994. return 0;
  1995. }
  1996. size = 0;
  1997. REG_SET_SLICE(size, MRV_AE_ISP_EXPV2_SIZE_H, grid_w);
  1998. REG_SET_SLICE(size, MRV_AE_ISP_EXPV2_SIZE_V, grid_h);
  1999. offset = 0;
  2000. REG_SET_SLICE(offset, MRV_AE_ISP_EXPV2_OFFSET_H, exp2->window.x);
  2001. REG_SET_SLICE(offset, MRV_AE_ISP_EXPV2_OFFSET_V, exp2->window.y);
  2002. size_inv = 0;
  2003. REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_H, (65536 + grid_w/2) / grid_w);
  2004. REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_V, (65536 + grid_h/2) / grid_h);
  2005. weight = 0;
  2006. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_R, exp2->r)
  2007. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR, exp2->gr)
  2008. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB, exp2->gb)
  2009. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_B, exp2->b)
  2010. isp_write_reg(dev, REG_ADDR(isp_expv2_offset), offset);
  2011. isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert), size_inv);
  2012. isp_write_reg(dev, REG_ADDR(isp_expv2_size), size);
  2013. #ifdef ISP_AE_SHADOW
  2014. isp_write_reg(dev, REG_ADDR(isp_expv2_offset_shd), offset);
  2015. isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert_shd), size_inv);
  2016. isp_write_reg(dev, REG_ADDR(isp_expv2_size_shd), size);
  2017. #endif
  2018. isp_write_reg(dev, REG_ADDR(isp_expv2_pixel_weight), weight);
  2019. miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl));
  2020. REG_SET_SLICE(miv2_ctrl, MP_JDP_PATH_ENABLE, 1);
  2021. isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl);
  2022. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_base_ad_init), dev->exp2.pa);
  2023. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_size_init), AEV2_DMA_SIZE);
  2024. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_offs_cnt_init), 0);
  2025. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_llength), AEV2_DMA_SIZE);
  2026. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_width), 1024);
  2027. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_height), 1);
  2028. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_size), AEV2_DMA_SIZE);
  2029. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_ENABLE, 1);
  2030. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_INPUT_SELECT, exp2->input_select);
  2031. isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl);
  2032. miv2_ctrl_shd = isp_read_reg(dev, REG_ADDR(miv2_ctrl_shd));
  2033. if (!(miv2_ctrl_shd && MP_YCBCR_PATH_ENABLE_MASK) && !(miv2_ctrl_shd && MP_RAW_PATH_ENABLE_MASK)) {
  2034. miv2_mp_fmt = isp_read_reg(dev, REG_ADDR(miv2_mp_fmt));
  2035. #ifdef ISP_AEV2_V2
  2036. REG_SET_SLICE(miv2_mp_fmt, MP_WR_JDP_DP_BIT, 1);
  2037. #endif
  2038. REG_SET_SLICE(miv2_mp_fmt, MP_WR_JDP_FMT, 0);
  2039. isp_write_reg(dev, REG_ADDR(miv2_mp_fmt), miv2_mp_fmt);
  2040. miv2_mp_bus_id = isp_read_reg(dev, REG_ADDR(miv2_mp_bus_id));
  2041. REG_SET_SLICE(miv2_mp_bus_id, MP_BUS_SW_EN, 1);
  2042. REG_SET_SLICE(miv2_mp_bus_id, MP_WR_ID_EN, 1);
  2043. isp_write_reg(dev, REG_ADDR(miv2_mp_bus_id), miv2_mp_bus_id);
  2044. miv2_mp_ctrl = isp_read_reg(dev, REG_ADDR(miv2_mp_ctrl));
  2045. REG_SET_SLICE(miv2_mp_ctrl, MP_AUTO_UPDATE, 1);
  2046. REG_SET_SLICE(miv2_mp_ctrl, MP_INIT_BASE_EN, 1);
  2047. REG_SET_SLICE(miv2_mp_ctrl, MP_INIT_OFFSET_EN, 1);
  2048. isp_write_reg(dev, REG_ADDR(miv2_mp_ctrl), miv2_mp_ctrl);
  2049. }
  2050. isp_info("exit %s\n", __func__);
  2051. return 0;
  2052. #endif
  2053. }
  2054. int isp_s_2dnr(struct isp_ic_dev *dev)
  2055. {
  2056. #ifndef ISP_2DNR
  2057. //isp_err("unsupported function: %s\n", __func__);
  2058. return -EINVAL;
  2059. #else
  2060. struct isp_2dnr_context *dnr2 = &dev->dnr2;
  2061. u32 isp_denoise2d_control =
  2062. isp_read_reg(dev, REG_ADDR(isp_denoise2d_control));
  2063. u32 value, addr, strength;
  2064. u32 isp_ctrl;
  2065. int i;
  2066. /*isp_info("enter %s\n", __func__);*/
  2067. if (!dnr2->enable) {
  2068. #ifndef ISP_2DNR_V4
  2069. REG_SET_SLICE(isp_denoise2d_control, ISP_2DNR_ENABLE, 0);
  2070. isp_write_reg(dev, REG_ADDR(isp_denoise2d_control),
  2071. isp_denoise2d_control);
  2072. #else
  2073. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  2074. REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 0);
  2075. if((value & DENOISE3D_V20_TNR_ENABLE_MASK) == 0)
  2076. REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 0);
  2077. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl),
  2078. value);
  2079. #endif
  2080. return 0;
  2081. }
  2082. strength = isp_read_reg(dev, REG_ADDR(isp_denoise2d_strength));
  2083. REG_SET_SLICE(strength, ISP_2DNR_PRGAMMA_STRENGTH, dnr2->pre_gamma);
  2084. REG_SET_SLICE(strength, ISP_2DNR_STRENGTH, dnr2->strength);
  2085. isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength), strength);
  2086. addr = REG_ADDR(isp_denoise2d_sigma_y[0]);
  2087. for (i = 0; i < 60; i += 5) {
  2088. value = 0;
  2089. REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i]);
  2090. REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 1]);
  2091. REG_SET_SLICE(value, ISP_2DNR_SIGMAY2A,
  2092. dnr2->sigma[i + 2] >> 6);
  2093. isp_write_reg(dev, addr, value);
  2094. value = 0;
  2095. addr += 4;
  2096. REG_SET_SLICE(value, ISP_2DNR_SIGMAY2B,
  2097. dnr2->sigma[i + 2] & 0x3f);
  2098. REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i + 3]);
  2099. REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 4]);
  2100. isp_write_reg(dev, addr, value);
  2101. addr += 4;
  2102. }
  2103. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  2104. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  2105. REG_SET_SLICE(isp_denoise2d_control, ISP_2DNR_ENABLE, 1);
  2106. #if defined(ISP_2DNR_V2) || defined(ISP_2DNR_V4)
  2107. isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr), dnr2->sigma_sqr);
  2108. isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr_shd),
  2109. dnr2->sigma_sqr);
  2110. isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor),
  2111. dnr2->weight);
  2112. isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor_shd),
  2113. dnr2->weight);
  2114. /* refer to HW spec for HBLANK */
  2115. //isp_write_reg(dev, REG_ADDR(isp_denoise2d_dummy_hblank), 0);
  2116. isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength_shd), strength);
  2117. isp_write_reg(dev, REG_ADDR(isp_denoise2d_control_shd),
  2118. isp_denoise2d_control);
  2119. #endif
  2120. #ifndef ISP_2DNR_V4
  2121. isp_write_reg(dev, REG_ADDR(isp_denoise2d_control),
  2122. isp_denoise2d_control);
  2123. #else
  2124. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_blending));
  2125. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_OFFSET, dnr2->str_off);
  2126. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_MAX, dnr2->str_max);
  2127. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_SLOPE, dnr2->str_slope);
  2128. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_blending), value);
  2129. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  2130. REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 1);
  2131. REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 1);
  2132. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl),
  2133. value);
  2134. #endif
  2135. /*isp_info("exit %s\n", __func__);*/
  2136. return 0;
  2137. #endif
  2138. }
  2139. int isp_s_simp(struct isp_ic_dev *dev)
  2140. {
  2141. struct isp_simp_context *simp = &dev->simp;
  2142. u32 vi_ircl = isp_read_reg(dev, REG_ADDR(vi_ircl));
  2143. u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl));
  2144. u32 super_imp_ctrl = isp_read_reg(dev, REG_ADDR(super_imp_ctrl));
  2145. isp_info("enter %s\n", __func__);
  2146. REG_SET_SLICE(vi_ircl, MRV_VI_SIMP_SOFT_RST, 1);
  2147. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2148. if (!simp->enable) {
  2149. REG_SET_SLICE(vi_iccl, MRV_VI_SIMP_CLK_ENABLE, 0);
  2150. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  2151. return 0;
  2152. }
  2153. REG_SET_SLICE(vi_ircl, MRV_VI_SIMP_SOFT_RST, 0);
  2154. isp_write_reg(dev, REG_ADDR(super_imp_offset_x), simp->x);
  2155. isp_write_reg(dev, REG_ADDR(super_imp_offset_y), simp->y);
  2156. isp_write_reg(dev, REG_ADDR(super_imp_color_y), simp->r);
  2157. isp_write_reg(dev, REG_ADDR(super_imp_color_cb), simp->g);
  2158. isp_write_reg(dev, REG_ADDR(super_imp_color_cr), simp->b);
  2159. REG_SET_SLICE(super_imp_ctrl, MRV_SI_TRANSPARENCY_MODE,
  2160. simp->transparency_mode);
  2161. REG_SET_SLICE(super_imp_ctrl, MRV_SI_REF_IMAGE, simp->ref_image);
  2162. isp_write_reg(dev, REG_ADDR(super_imp_ctrl), super_imp_ctrl);
  2163. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2164. REG_SET_SLICE(vi_iccl, MRV_VI_SIMP_CLK_ENABLE, 1);
  2165. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  2166. isp_info("exit %s\n", __func__);
  2167. return 0;
  2168. }
  2169. int isp_s_cproc(struct isp_ic_dev *dev)
  2170. {
  2171. struct isp_cproc_context *cproc = &dev->cproc;
  2172. u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl));
  2173. u32 cproc_ctrl = isp_read_reg(dev, REG_ADDR(cproc_ctrl));
  2174. //REG_SET_SLICE(vi_ircl, MRV_VI_CP_SOFT_RST, 1);
  2175. //isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2176. //if there is no shd register. should update cporc register in isp frame end irq.
  2177. #ifndef ISP_CPROC_SHD
  2178. if(dev->cproc.changed || !is_isp_enable(dev))
  2179. {
  2180. #endif
  2181. /*isp_info("enter %s %d\n", __func__, cproc->enable);*/
  2182. if (!cproc->enable) {
  2183. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_ENABLE, 0);
  2184. /* REG_SET_SLICE(vi_iccl, MRV_VI_CP_CLK_ENABLE, 0); */
  2185. /* isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl); */
  2186. isp_write_reg(dev, REG_ADDR(cproc_ctrl), cproc_ctrl);
  2187. return 0;
  2188. }
  2189. //REG_SET_SLICE(vi_ircl, MRV_VI_CP_SOFT_RST, 0);
  2190. //isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2191. isp_write_reg(dev, REG_ADDR(cproc_contrast), cproc->contrast);
  2192. isp_write_reg(dev, REG_ADDR(cproc_brightness), cproc->brightness);
  2193. isp_write_reg(dev, REG_ADDR(cproc_saturation), cproc->saturation);
  2194. isp_write_reg(dev, REG_ADDR(cproc_hue), cproc->hue);
  2195. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_ENABLE, 1);
  2196. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_C_OUT_RANGE,
  2197. cproc->c_out_full);
  2198. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_Y_OUT_RANGE,
  2199. cproc->y_out_full);
  2200. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_Y_IN_RANGE, cproc->y_in_full);
  2201. REG_SET_SLICE(vi_iccl, MRV_VI_CP_CLK_ENABLE, 1);
  2202. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  2203. isp_write_reg(dev, REG_ADDR(cproc_ctrl), cproc_ctrl);
  2204. #ifndef ISP_CPROC_SHD
  2205. dev->cproc.changed = false;
  2206. } else {
  2207. dev->cproc.changed = true;
  2208. }
  2209. #endif
  2210. /*isp_info("exit %s\n", __func__);*/
  2211. return 0;
  2212. }
  2213. int isp_s_elawb(struct isp_ic_dev *dev)
  2214. {
  2215. struct isp_elawb_context *elawb = &dev->elawb;
  2216. u32 awb_meas_mode = isp_read_reg(dev, REG_ADDR(awb_meas_mode));
  2217. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  2218. u32 id = elawb->id;
  2219. u32 data;
  2220. if (!elawb->enable) {
  2221. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_IRQ_ENABLE, 0);
  2222. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_EN, 0);
  2223. isp_write_reg(dev, REG_ADDR(awb_meas_mode), awb_meas_mode);
  2224. isp_write_reg(dev, REG_ADDR(isp_imsc),
  2225. isp_imsc & ~MRV_ISP_IMSC_AWB_DONE_MASK);
  2226. return 0;
  2227. }
  2228. isp_write_reg(dev, REG_ADDR(awb_meas_h_offs), elawb->window.x);
  2229. isp_write_reg(dev, REG_ADDR(awb_meas_v_offs), elawb->window.y);
  2230. isp_write_reg(dev, REG_ADDR(awb_meas_h_size), elawb->window.width);
  2231. isp_write_reg(dev, REG_ADDR(awb_meas_v_size), elawb->window.height);
  2232. if (id > 0 && id < 9) {
  2233. isp_write_reg(dev, REG_ADDR(awb_meas_center[id - 1].x),
  2234. elawb->info[id - 1].x);
  2235. isp_write_reg(dev, REG_ADDR(awb_meas_center[id - 1].y),
  2236. elawb->info[id - 1].y);
  2237. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a1),
  2238. elawb->info[id - 1].a1);
  2239. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a2),
  2240. elawb->info[id - 1].a2);
  2241. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a3),
  2242. elawb->info[id - 1].a3);
  2243. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a4),
  2244. elawb->info[id - 1].a4);
  2245. isp_write_reg(dev, REG_ADDR(awb_meas_rmax[id - 1]),
  2246. elawb->info[id - 1].r_max_sqr);
  2247. }
  2248. data = 0;
  2249. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_R, elawb->r);
  2250. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_B, elawb->b);
  2251. isp_write_reg(dev, REG_ADDR(isp_awb_gain_rb), data);
  2252. data = 0;
  2253. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_GR, elawb->gr);
  2254. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_GB, elawb->gb);
  2255. isp_write_reg(dev, REG_ADDR(isp_awb_gain_g), data);
  2256. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_IRQ_ENABLE, 1);
  2257. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_EN, 1);
  2258. isp_write_reg(dev, REG_ADDR(awb_meas_mode), awb_meas_mode);
  2259. isp_write_reg(dev, REG_ADDR(isp_imsc),
  2260. isp_imsc | MRV_ISP_IMSC_AWB_DONE_MASK);
  2261. return 0;
  2262. }
  2263. int isp_ioc_qcap(struct isp_ic_dev *dev, void __user *args)
  2264. {
  2265. /* use public VIDIOC_QUERYCAP to query the type of v4l-subdevs. */
  2266. #ifdef __KERNEL__
  2267. #ifndef USE_FPGA
  2268. struct v4l2_capability *cap = (struct v4l2_capability *)args;
  2269. strcpy((char *)cap->driver, "viv_isp_subdev");
  2270. cap->bus_info[0] = (__u8)dev->id;//isp channel id
  2271. #else
  2272. struct v4l2_capability cap;
  2273. strcpy((char *)cap.driver, "viv_isp_subdev");
  2274. cap.bus_info[0] = (__u8)dev->id;//isp channel id
  2275. isp_info("enter %s viv_isp_subdev\n", __func__);
  2276. viv_check_retval(copy_to_user
  2277. ((struct v4l2_capability *)args, &cap, sizeof(cap)));
  2278. #endif
  2279. #endif
  2280. return 0;
  2281. }
  2282. int isp_ioc_g_status(struct isp_ic_dev *dev, void __user *args)
  2283. {
  2284. u32 val = 0;
  2285. /* val = isp_read_reg(REG_ADDR(isp_feature_version)); */
  2286. viv_check_retval(copy_to_user(args, &val, sizeof(val)));
  2287. return 0;
  2288. }
  2289. static u32 getScaleFactor(u32 src, u32 dst)
  2290. {
  2291. if (dst > src) {
  2292. return ((65536 * (src - 1)) / (dst - 1));
  2293. } else if (dst < src) {
  2294. return ((65536 * (dst - 1)) / (src - 1)) + 1;
  2295. }
  2296. return 65536;
  2297. }
  2298. int isp_set_scaling(int id, struct isp_ic_dev *dev, bool stabilization, bool crop)
  2299. {
  2300. u32 addr, ctrl;
  2301. u32 iw, ih, ow, oh;
  2302. u32 inputWidth, inputHeight, outputWidth, outputHeight;
  2303. u32 scale_hy, scale_hcb, scale_hcr, scale_vy, scale_vc;
  2304. struct isp_mi_data_path_context *path = &dev->mi.path[id];
  2305. if (crop) { //enabled crop.Do not need to scaler.
  2306. isp_info("%s:The crop enabled ,So does not need to do scaler.\n", __func__);
  2307. return 0;
  2308. }
  2309. if (id == IC_MI_PATH_MAIN) { /* mp */
  2310. addr = REG_ADDR(mrsz_ctrl);
  2311. } else if (id == IC_MI_PATH_SELF) { /* sp */
  2312. addr = REG_ADDR(srsz_ctrl);
  2313. } else if (id == IC_MI_PATH_SELF2) { /* sp2 */
  2314. addr = REG_ADDR(srsz2_ctrl);
  2315. } else {
  2316. return -EFAULT;
  2317. }
  2318. inputWidth = path->in_width;
  2319. inputHeight = path->in_height;
  2320. outputWidth = path->out_width;
  2321. outputHeight = path->out_height;
  2322. if (stabilization) { /* enabled image stabilization. */
  2323. inputWidth = isp_read_reg(dev, REG_ADDR(isp_is_h_size));
  2324. inputHeight = isp_read_reg(dev, REG_ADDR(isp_is_v_size));
  2325. }
  2326. ctrl = isp_read_reg(dev, addr);
  2327. iw = inputWidth / 2;
  2328. ih = inputHeight;
  2329. ow = outputWidth / 2;
  2330. oh = outputHeight;
  2331. switch (path->in_mode) {
  2332. case IC_MI_DATAMODE_YUV422:
  2333. oh = outputHeight;
  2334. break;
  2335. case IC_MI_DATAMODE_YUV420:
  2336. oh = outputHeight / 2; /* scale cbcr */
  2337. break;
  2338. case IC_MI_DATAMODE_YUV444:
  2339. oh = outputHeight;
  2340. break;
  2341. case IC_MI_DATAMODE_RGB888:
  2342. oh = outputHeight;
  2343. break;
  2344. default:
  2345. return -EFAULT;
  2346. }
  2347. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_ENABLE,
  2348. inputWidth != outputWidth);
  2349. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_ENABLE,
  2350. inputHeight != outputHeight);
  2351. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_UP, inputWidth < outputWidth);
  2352. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_UP, inputHeight < outputHeight);
  2353. scale_hy = getScaleFactor(inputWidth, outputWidth);
  2354. scale_vy = getScaleFactor(inputHeight, outputHeight);
  2355. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_ENABLE, iw != ow);
  2356. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_ENABLE, ih != oh);
  2357. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_UP, iw < ow);
  2358. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_UP, ih < oh);
  2359. scale_hcr = getScaleFactor(iw, ow);
  2360. scale_hcb = getScaleFactor(iw, ow);
  2361. scale_vc = getScaleFactor(ih, oh);
  2362. /*Need to update immediately*/
  2363. REG_SET_SLICE(ctrl, MRV_MRSZ_CFG_UPD, 1);
  2364. if (id == IC_MI_PATH_MAIN) {
  2365. isp_write_reg(dev, REG_ADDR(mrsz_scale_vc), scale_vc);
  2366. isp_write_reg(dev, REG_ADDR(mrsz_scale_vy), scale_vy);
  2367. isp_write_reg(dev, REG_ADDR(mrsz_scale_hcr), scale_hcr);
  2368. isp_write_reg(dev, REG_ADDR(mrsz_scale_hcb), scale_hcb);
  2369. isp_write_reg(dev, REG_ADDR(mrsz_scale_hy), scale_hy);
  2370. isp_write_reg(dev, REG_ADDR(mrsz_ctrl), ctrl);
  2371. } else if (id == IC_MI_PATH_SELF) {
  2372. isp_write_reg(dev, REG_ADDR(srsz_scale_vc), scale_vc);
  2373. isp_write_reg(dev, REG_ADDR(srsz_scale_vy), scale_vy);
  2374. isp_write_reg(dev, REG_ADDR(srsz_scale_hcr), scale_hcr);
  2375. isp_write_reg(dev, REG_ADDR(srsz_scale_hcb), scale_hcb);
  2376. isp_write_reg(dev, REG_ADDR(srsz_scale_hy), scale_hy);
  2377. isp_write_reg(dev, REG_ADDR(srsz_ctrl), ctrl);
  2378. } else if (id == IC_MI_PATH_SELF2) {
  2379. isp_write_reg(dev, REG_ADDR(srsz2_scale_vc), scale_vc);
  2380. isp_write_reg(dev, REG_ADDR(srsz2_scale_vy), scale_vy);
  2381. isp_write_reg(dev, REG_ADDR(srsz2_scale_hcr), scale_hcr);
  2382. isp_write_reg(dev, REG_ADDR(srsz2_scale_hcb), scale_hcb);
  2383. isp_write_reg(dev, REG_ADDR(srsz2_scale_hy), scale_hy);
  2384. isp_write_reg(dev, REG_ADDR(srsz2_ctrl), ctrl);
  2385. }
  2386. return 0;
  2387. }
  2388. typedef struct isp_crop_reg_s {
  2389. u32 crop_ctrl_addr;
  2390. u32 crop_x_dir_addr;
  2391. u32 crop_y_dir_addr;
  2392. } isp_crop_reg_t;
  2393. int isp_set_crop(struct isp_ic_dev *dev)
  2394. {
  2395. long ret = 0;
  2396. u32 crop_ctrl, crop_x_dir, crop_y_dir;
  2397. u8 i;
  2398. isp_crop_reg_t crop_reg[ISP_MI_PATH_SP2_BP + 1] = {
  2399. {
  2400. REG_ADDR(mrsz_ctrl),
  2401. REG_ADDR(mrsz_phase_crop_x),
  2402. REG_ADDR(mrsz_phase_crop_y)
  2403. },
  2404. {
  2405. REG_ADDR(srsz_ctrl),
  2406. REG_ADDR(srsz_phase_crop_x),
  2407. REG_ADDR(srsz_phase_crop_y)
  2408. },
  2409. {
  2410. REG_ADDR(srsz2_ctrl),
  2411. REG_ADDR(srsz2_phase_crop_x),
  2412. REG_ADDR(srsz2_phase_crop_y)
  2413. }
  2414. };
  2415. struct isp_crop_context *crop = dev->crop;
  2416. for ( i = 0; i <= ISP_MI_PATH_SP2_BP; i++) {
  2417. crop_ctrl = isp_read_reg(dev, crop_reg[i].crop_ctrl_addr);
  2418. crop_x_dir = isp_read_reg(dev, crop_reg[i].crop_x_dir_addr);
  2419. crop_y_dir = isp_read_reg(dev, crop_reg[i].crop_y_dir_addr);
  2420. if (!crop[i].enabled) {
  2421. #ifndef ISP8000NANO_BASE
  2422. REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CROP_ENABLE, 0);
  2423. #endif
  2424. isp_write_reg(dev, crop_reg[i].crop_ctrl_addr, crop_ctrl);
  2425. continue;
  2426. }
  2427. REG_SET_SLICE(crop_x_dir, MRV_MRSZ_PHASE_H_START, crop[i].window.x);
  2428. REG_SET_SLICE(crop_y_dir, MRV_MRSZ_PHASE_V_START, crop[i].window.y);
  2429. REG_SET_SLICE(crop_x_dir, MRV_MRSZ_PHASE_H_END, crop[i].window.width + crop[i].window.x - 1); //x_end = x + width -1
  2430. REG_SET_SLICE(crop_y_dir, MRV_MRSZ_PHASE_V_END, crop[i].window.height + crop[i].window.y - 1); //y_end = y + height -1
  2431. #ifndef ISP8000NANO_BASE
  2432. REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CROP_ENABLE, 1);
  2433. /*Need to update immediately*/
  2434. REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CFG_UPD, 1);
  2435. #endif
  2436. isp_write_reg(dev, crop_reg[i].crop_x_dir_addr, crop_x_dir);
  2437. isp_write_reg(dev, crop_reg[i].crop_y_dir_addr, crop_y_dir);
  2438. isp_write_reg(dev, crop_reg[i].crop_ctrl_addr, crop_ctrl);
  2439. }
  2440. return ret;
  2441. }
  2442. int isp_ioc_g_feature(struct isp_ic_dev *dev, void __user *args)
  2443. {
  2444. u32 val = 0;
  2445. #ifdef ISP_EE
  2446. val |= ISP_EE_SUPPORT;
  2447. #endif
  2448. #ifdef ISP_WDR3
  2449. val |= ISP_WDR3_SUPPORT;
  2450. #endif
  2451. #ifdef ISP_2DNR
  2452. val |= ISP_2DNR_SUPPORT;
  2453. #endif
  2454. #ifdef ISP_3DNR
  2455. val |= ISP_3DNR_SUPPORT;
  2456. #endif
  2457. #ifdef ISP_WDR_V3
  2458. val |= ISP_WDR3_SUPPORT;
  2459. #endif
  2460. #ifdef ISP_MIV2
  2461. val |= ISP_MIV2_SUPPORT;
  2462. #endif
  2463. #ifdef ISP_AEV2
  2464. val |= ISP_AEV2_SUPPORT;
  2465. #endif
  2466. #ifdef ISP_HDR_STITCH
  2467. val |= ISP_HDR_STITCH_SUPPORT;
  2468. #endif
  2469. viv_check_retval(copy_to_user(args, &val, sizeof(val)));
  2470. return 0;
  2471. }
  2472. int isp_ioc_g_feature_veresion(struct isp_ic_dev *dev, void __user *args)
  2473. {
  2474. u32 val = 0;
  2475. /* val = isp_read_reg(REG_ADDR(isp_feature_version)); */
  2476. viv_check_retval(copy_to_user(args, &val, sizeof(val)));
  2477. return 0;
  2478. }
  2479. static long isp_get_extmem(struct isp_ic_dev *dev, void __user *args)
  2480. {
  2481. #define UT_USED_SIZE 0x01000000
  2482. long ret = 0;
  2483. struct isp_extmem_info ext_mem;
  2484. dev->ut_addr = dma_alloc_coherent(dev->device, UT_USED_SIZE, &dev->ut_phy_addr, GFP_KERNEL);
  2485. if (dev->ut_addr != NULL) {
  2486. ext_mem.addr = dev->ut_phy_addr;
  2487. ext_mem.size = UT_USED_SIZE;
  2488. } else {
  2489. return -1;
  2490. }
  2491. ret = copy_to_user(args, &ext_mem, sizeof(struct isp_extmem_info));
  2492. return ret;
  2493. }
  2494. long isp_priv_ioctl(struct isp_ic_dev *dev, unsigned int cmd, void __user *args)
  2495. {
  2496. int ret = -1;
  2497. if (!dev) {
  2498. return ret;
  2499. }
  2500. /*isp_info("[%s:%d]cmd 0x%08x\n", __func__, __LINE__, cmd);*/
  2501. switch (cmd) {
  2502. case ISPIOC_RESET:
  2503. if((ret = isp_mi_stop(dev)) != 0 )
  2504. {
  2505. isp_err("[%s:%d]stop mi error before resetting!\n", __func__, __LINE__);
  2506. break;
  2507. }
  2508. if((ret = isp_stop_stream(dev)) != 0)
  2509. {
  2510. isp_err("[%s:%d]stop isp stream before resetting!\n", __func__, __LINE__);
  2511. break;
  2512. }
  2513. ret = isp_reset(dev);
  2514. break;
  2515. case ISPIOC_WRITE_REG:
  2516. ret = isp_ioc_write_reg(dev, args);
  2517. break;
  2518. case ISPIOC_READ_REG:
  2519. ret = isp_ioc_read_reg(dev, args);
  2520. break;
  2521. case ISPIOC_GET_MIS:
  2522. ret = isp_ioc_read_mis(dev, args);
  2523. break;
  2524. case ISPIOC_ENABLE_TPG:
  2525. ret = isp_enable_tpg(dev);
  2526. break;
  2527. case ISPIOC_DISABLE_TPG:
  2528. ret = isp_disable_tpg(dev);
  2529. break;
  2530. case ISPIOC_ENABLE_BLS:
  2531. ret = isp_enable_bls(dev);
  2532. break;
  2533. case ISPIOC_DISABLE_BLS:
  2534. ret = isp_disable_bls(dev);
  2535. break;
  2536. case ISPIOC_START_DMA_READ:
  2537. ret = isp_ioc_start_dma_read(dev, args);
  2538. break;
  2539. case ISPIOC_CFG_DMA:
  2540. ret = isp_ioc_cfg_dma(dev, args);
  2541. break;
  2542. case ISPIOC_MI_STOP:
  2543. ret = isp_mi_stop(dev);
  2544. break;
  2545. case ISPIOC_DISABLE_ISP_OFF:
  2546. ret = isp_ioc_disable_isp_off(dev, args);
  2547. break;
  2548. case ISPIOC_ISP_STOP:
  2549. ret = isp_stop_stream(dev);
  2550. if(!ret) {
  2551. dev->streaming = false;
  2552. }
  2553. break;
  2554. case ISPIOC_ENABLE:
  2555. ret = isp_enable(dev);
  2556. break;
  2557. case ISPIOC_DISABLE:
  2558. ret = isp_disable(dev);
  2559. break;
  2560. case ISPIOC_ISP_STATUS:{
  2561. bool enable = is_isp_enable(dev);
  2562. viv_check_retval(copy_to_user
  2563. (args, &enable, sizeof(bool)));
  2564. ret = 0;
  2565. break;
  2566. }
  2567. case ISPIOC_ENABLE_LSC:
  2568. ret = isp_enable_lsc(dev);
  2569. break;
  2570. case ISPIOC_DISABLE_LSC:
  2571. ret = isp_disable_lsc(dev);
  2572. break;
  2573. case ISPIOC_S_DIGITAL_GAIN:
  2574. viv_check_retval(copy_from_user
  2575. (&dev->dgain, args, sizeof(dev->dgain)));
  2576. ret = isp_s_digital_gain(dev);
  2577. break;
  2578. #ifdef ISP_DEMOSAIC2
  2579. case ISPIOC_S_DMSC_INTP:
  2580. viv_check_retval(copy_from_user
  2581. (&dev->demosaic.intp, args,
  2582. sizeof(dev->demosaic.intp)));
  2583. ret = isp_set_dmsc_intp(dev);
  2584. break;
  2585. case ISPIOC_S_DMSC_DMOI:
  2586. viv_check_retval(copy_from_user
  2587. (&dev->demosaic.demoire, args,
  2588. sizeof(dev->demosaic.demoire)));
  2589. ret = isp_set_dmsc_dmoi(dev);
  2590. break;
  2591. case ISPIOC_S_DMSC_SKIN:
  2592. viv_check_retval(copy_from_user
  2593. (&dev->demosaic.skin, args,
  2594. sizeof(dev->demosaic.skin)));
  2595. ret = isp_set_dmsc_skin(dev);
  2596. break;
  2597. case ISPIOC_S_DMSC_SHAP:
  2598. viv_check_retval(copy_from_user
  2599. (&dev->demosaic.sharpen, args,
  2600. sizeof(dev->demosaic.sharpen)));
  2601. ret = isp_set_dmsc_sharpen(dev);
  2602. break;
  2603. case ISPIOC_S_DMSC_SHAP_LINE:
  2604. viv_check_retval(copy_from_user
  2605. (&dev->demosaic.sharpenLine, args,
  2606. sizeof(dev->demosaic.sharpenLine)));
  2607. ret = isp_set_dmsc_sharpen_line(dev);
  2608. break;
  2609. case ISPIOC_S_DMSC_CAC:
  2610. viv_check_retval(copy_from_user
  2611. (&dev->cac, args, sizeof(dev->cac)));
  2612. ret = isp_set_dmsc_cac(dev);
  2613. break;
  2614. case ISPIOC_S_DMSC_DEPURPLE:
  2615. viv_check_retval(copy_from_user
  2616. (&dev->demosaic.depurple, args,
  2617. sizeof(dev->demosaic.depurple)));
  2618. ret = isp_set_dmsc_depurple(dev);
  2619. break;
  2620. case ISPIOC_S_DMSC_GFILTER:
  2621. viv_check_retval(copy_from_user
  2622. (&dev->demosaic.gFilter, args,
  2623. sizeof(dev->demosaic.gFilter)));
  2624. ret = isp_set_dmsc_gfilter(dev);
  2625. break;
  2626. case ISPIOC_S_DMSC:
  2627. viv_check_retval(copy_from_user
  2628. (&dev->demosaic, args, sizeof(dev->demosaic)));
  2629. ret = isp_s_dmsc(dev);
  2630. break;
  2631. #endif
  2632. case ISPIOC_ENABLE_AWB:
  2633. ret = isp_enable_awb(dev);
  2634. break;
  2635. case ISPIOC_DISABLE_AWB:
  2636. ret = isp_disable_awb(dev);
  2637. break;
  2638. case ISPIOC_ENABLE_WB:
  2639. ret = isp_enable_wb(dev, 1);
  2640. break;
  2641. case ISPIOC_DISABLE_WB:
  2642. ret = isp_enable_wb(dev, 0);
  2643. break;
  2644. case ISPIOC_ENABLE_GAMMA_OUT:
  2645. ret = isp_enable_gamma_out(dev, 1);
  2646. break;
  2647. case ISPIOC_DISABLE_GAMMA_OUT:
  2648. ret = isp_enable_gamma_out(dev, 0);
  2649. break;
  2650. #if defined(ISP_3DNR) || defined(ISP_3DNR_V2_V1)
  2651. case ISPIOC_R_3DNR:
  2652. viv_check_retval(copy_from_user
  2653. (&dev->dnr3, args, sizeof(dev->dnr3)));
  2654. ret = isp_r_3dnr(dev);
  2655. break;
  2656. #endif
  2657. case ISPIOC_S_IS:
  2658. viv_check_retval(copy_from_user
  2659. (&dev->is, args, sizeof(dev->is)));
  2660. ret = isp_s_is(dev);
  2661. break;
  2662. case ISPIOC_S_RAW_IS:
  2663. viv_check_retval(copy_from_user
  2664. (&dev->rawis, args, sizeof(dev->rawis)));
  2665. ret = isp_s_raw_is(dev);
  2666. break;
  2667. case ISPIOC_S_CC:
  2668. viv_check_retval(copy_from_user
  2669. (&dev->cc, args, sizeof(dev->cc)));
  2670. ret = isp_s_cc(dev);
  2671. break;
  2672. case ISPIOC_S_EE:
  2673. viv_check_retval(copy_from_user
  2674. (&dev->ee, args, sizeof(dev->ee)));
  2675. ret = isp_s_ee(dev);
  2676. break;
  2677. case ISPIOC_S_IE:
  2678. viv_check_retval(copy_from_user
  2679. (&dev->ie, args, sizeof(dev->ie)));
  2680. ret = isp_s_ie(dev);
  2681. break;
  2682. case ISPIOC_S_TPG:
  2683. viv_check_retval(copy_from_user
  2684. (&dev->tpg, args, sizeof(dev->tpg)));
  2685. ret = isp_s_tpg(dev);
  2686. break;
  2687. case ISPIOC_S_BLS:
  2688. viv_check_retval(copy_from_user
  2689. (&dev->bls, args, sizeof(dev->bls)));
  2690. ret = isp_s_bls(dev);
  2691. break;
  2692. case ISPIOC_BYPASS_MCM:
  2693. viv_check_retval(copy_from_user
  2694. (&dev->mcm, args, sizeof(dev->mcm)));
  2695. ret = isp_bypass_mcm(dev);
  2696. break;
  2697. case ISPIOC_S_MCM_WR:
  2698. viv_check_retval(copy_from_user
  2699. (&dev->mcm, args, sizeof(dev->mcm)));
  2700. ret = isp_s_mcm_wr(dev);
  2701. break;
  2702. case ISPIOC_S_MUX:
  2703. viv_check_retval(copy_from_user
  2704. (&dev->mux, args, sizeof(dev->mux)));
  2705. ret = isp_s_mux(dev);
  2706. break;
  2707. case ISPIOC_S_AWB:
  2708. viv_check_retval(copy_from_user
  2709. (&dev->awb, args, sizeof(dev->awb)));
  2710. ret = isp_s_awb(dev);
  2711. break;
  2712. case ISPIOC_S_LSC_TBL:
  2713. viv_check_retval(copy_from_user
  2714. (&dev->lsc, args, sizeof(dev->lsc)));
  2715. ret = isp_s_lsc_tbl(dev);
  2716. break;
  2717. case ISPIOC_S_LSC_SEC:
  2718. viv_check_retval(copy_from_user
  2719. (&dev->lsc, args, sizeof(dev->lsc)));
  2720. ret = isp_s_lsc_sec(dev);
  2721. break;
  2722. case ISPIOC_S_DPF:
  2723. viv_check_retval(copy_from_user
  2724. (&dev->dpf, args, sizeof(dev->dpf)));
  2725. ret = isp_s_dpf(dev);
  2726. break;
  2727. case ISPIOC_S_EXP:
  2728. viv_check_retval(copy_from_user
  2729. (&dev->exp, args, sizeof(dev->exp)));
  2730. ret = isp_s_exp(dev);
  2731. break;
  2732. case ISPIOC_S_HDREXP:
  2733. viv_check_retval(copy_from_user
  2734. (&dev->hdrexp, args, sizeof(dev->hdrexp)));
  2735. ret = isp_s_hdrexp(dev);
  2736. break;
  2737. case ISPIOC_S_CNR:
  2738. viv_check_retval(copy_from_user
  2739. (&dev->cnr, args, sizeof(dev->cnr)));
  2740. ret = isp_s_cnr(dev);
  2741. break;
  2742. case ISPIOC_S_FLT:
  2743. {
  2744. viv_check_retval(copy_from_user
  2745. (&dev->flt, args, sizeof(dev->flt)));
  2746. ret = isp_s_flt(dev);
  2747. break;
  2748. }
  2749. case ISPIOC_S_CAC:
  2750. viv_check_retval(copy_from_user
  2751. (&dev->cac, args, sizeof(dev->cac)));
  2752. ret = isp_s_cac(dev);
  2753. break;
  2754. case ISPIOC_S_DEG:
  2755. viv_check_retval(copy_from_user
  2756. (&dev->deg, args, sizeof(dev->deg)));
  2757. ret = isp_s_deg(dev);
  2758. break;
  2759. case ISPIOC_S_VSM:
  2760. viv_check_retval(copy_from_user
  2761. (&dev->vsm, args, sizeof(dev->vsm)));
  2762. ret = isp_s_vsm(dev);
  2763. break;
  2764. case ISPIOC_S_AFM:
  2765. viv_check_retval(copy_from_user
  2766. (&dev->afm, args, sizeof(dev->afm)));
  2767. ret = isp_s_afm(dev);
  2768. break;
  2769. case ISPIOC_S_HDR:
  2770. viv_check_retval(copy_from_user
  2771. (&dev->hdr, args, sizeof(dev->hdr)));
  2772. ret = isp_s_hdr(dev);
  2773. break;
  2774. case ISPIOC_ENABLE_HDR:
  2775. viv_check_retval(copy_from_user
  2776. (&dev->hdr, args, sizeof(dev->hdr)));
  2777. ret = isp_enable_hdr(dev);
  2778. break;
  2779. case ISPIOC_DISABLE_HDR:
  2780. viv_check_retval(copy_from_user
  2781. (&dev->hdr, args, sizeof(dev->hdr)));
  2782. ret = isp_disable_hdr(dev);
  2783. break;
  2784. case ISPIOC_S_HIST:
  2785. viv_check_retval(copy_from_user
  2786. (&dev->hist, args, sizeof(dev->hist)));
  2787. ret = isp_s_hist(dev);
  2788. break;
  2789. case ISPIOC_S_HDRHIST:
  2790. viv_check_retval(copy_from_user
  2791. (&dev->hdrhist, args, sizeof(dev->hdrhist)));
  2792. ret = isp_s_hdrhist(dev);
  2793. break;
  2794. #ifdef ISP_HIST64
  2795. case ISPIOC_S_HIST64:
  2796. viv_check_retval(copy_from_user
  2797. (&dev->hist64, args, sizeof(dev->hist64)));
  2798. ret = isp_s_hist64(dev);
  2799. break;
  2800. case ISPIOC_U_HIST64:
  2801. viv_check_retval(copy_from_user
  2802. (&dev->hist64, args, sizeof(dev->hist64)));
  2803. ret = isp_update_hist64(dev);
  2804. break;
  2805. #endif
  2806. case ISPIOC_S_DPCC:
  2807. viv_check_retval(copy_from_user
  2808. (&dev->dpcc, args, sizeof(dev->dpcc)));
  2809. ret = isp_s_dpcc(dev);
  2810. break;
  2811. case ISPIOC_ENABLE_WDR3:
  2812. ret = isp_enable_wdr3(dev);
  2813. break;
  2814. case ISPIOC_DISABLE_WDR3:
  2815. ret = isp_disable_wdr3(dev);
  2816. break;
  2817. case ISPIOC_U_WDR3:
  2818. viv_check_retval(copy_from_user
  2819. (&dev->wdr3, args, sizeof(dev->wdr3)));
  2820. ret = isp_u_wdr3(dev);
  2821. break;
  2822. case ISPIOC_S_WDR3:
  2823. viv_check_retval(copy_from_user
  2824. (&dev->wdr3, args, sizeof(dev->wdr3)));
  2825. ret = isp_s_wdr3(dev);
  2826. break;
  2827. #ifdef ISP_WDR_V4
  2828. case ISPIOC_ENABLE_WDR4:
  2829. ret = isp_enable_wdr4(dev);
  2830. break;
  2831. case ISPIOC_DISABLE_WDR4:
  2832. ret = isp_disable_wdr4(dev);
  2833. break;
  2834. case ISPIOC_U_WDR4:
  2835. viv_check_retval(copy_from_user
  2836. (&dev->wdr4, args, sizeof(dev->wdr4)));
  2837. ret = isp_u_wdr4(dev);
  2838. break;
  2839. case ISPIOC_S_WDR4:
  2840. viv_check_retval(copy_from_user
  2841. (&dev->wdr4, args, sizeof(dev->wdr4)));
  2842. ret = isp_s_wdr4(dev);
  2843. break;
  2844. #endif
  2845. case ISPIOC_S_EXP2:
  2846. viv_check_retval(copy_from_user
  2847. (&dev->exp2, args, sizeof(dev->exp2)));
  2848. ret = isp_s_exp2(dev);
  2849. break;
  2850. case ISPIOC_S_EXP2_INPUTSEL:
  2851. viv_check_retval(copy_from_user
  2852. (&dev->exp2.input_select, args,
  2853. sizeof(dev->exp2.input_select)));
  2854. ret = isp_s_exp2_inputsel(dev);
  2855. break;
  2856. case ISPIOC_S_EXP2_SIZERATIO: {
  2857. u32 ratio;
  2858. viv_check_retval(copy_from_user(&ratio, args, sizeof(ratio)));
  2859. ret = isp_s_exp2_sizeratio(dev, ratio);
  2860. break;
  2861. }
  2862. case ISPIOC_S_2DNR:
  2863. viv_check_retval(copy_from_user
  2864. (&dev->dnr2, args, sizeof(dev->dnr2)));
  2865. #ifdef ISP_2DNR_V5
  2866. ret = isp_tdnr_s_2dnr(dev);
  2867. #else
  2868. ret = isp_s_2dnr(dev);
  2869. #endif
  2870. break;
  2871. case ISPIOC_S_SIMP:
  2872. viv_check_retval(copy_from_user
  2873. (&dev->simp, args, sizeof(dev->simp)));
  2874. ret = isp_s_simp(dev);
  2875. break;
  2876. case ISPIOC_S_COMP:
  2877. viv_check_retval(copy_from_user
  2878. (&dev->comp, args, sizeof(dev->comp)));
  2879. ret = isp_s_comp(dev);
  2880. break;
  2881. case ISPIOC_S_CPROC:
  2882. viv_check_retval(copy_from_user
  2883. (&dev->cproc, args, sizeof(dev->cproc)));
  2884. ret = isp_s_cproc(dev);
  2885. break;
  2886. case ISPIOC_S_XTALK:
  2887. viv_check_retval(copy_from_user
  2888. (&dev->xtalk, args, sizeof(dev->xtalk)));
  2889. ret = isp_s_xtalk(dev);
  2890. break;
  2891. case ISPIOC_S_ELAWB:
  2892. viv_check_retval(copy_from_user
  2893. (&dev->elawb, args, sizeof(dev->elawb)));
  2894. ret = isp_s_elawb(dev);
  2895. break;
  2896. case ISPIOC_S_INPUT:
  2897. viv_check_retval(copy_from_user
  2898. (&dev->ctx, args, sizeof(dev->ctx)));
  2899. ret = isp_s_input(dev);
  2900. break;
  2901. case ISPIOC_S_DEMOSAIC:
  2902. viv_check_retval(copy_from_user
  2903. (&dev->ctx, args, sizeof(dev->ctx)));
  2904. ret = isp_s_demosaic(dev);
  2905. break;
  2906. case ISPIOC_MI_START:
  2907. viv_check_retval(copy_from_user
  2908. (&dev->mi, args, sizeof(dev->mi)));
  2909. ret = isp_mi_start(dev);
  2910. break;
  2911. case ISPIOC_S_HDR_WB:
  2912. viv_check_retval(copy_from_user
  2913. (&dev->hdr, args, sizeof(dev->hdr)));
  2914. ret = isp_s_hdr_wb(dev);
  2915. break;
  2916. case ISPIOC_S_HDR_BLS:
  2917. viv_check_retval(copy_from_user
  2918. (&dev->hdr, args, sizeof(dev->hdr)));
  2919. ret = isp_s_hdr_bls(dev);
  2920. break;
  2921. case ISPIOC_S_HDR_DIGITAL_GAIN:
  2922. viv_check_retval(copy_from_user
  2923. (&dev->hdr, args, sizeof(dev->hdr)));
  2924. // ret = isp_s_hdr_digal_gain(dev);
  2925. break;
  2926. case ISPIOC_S_GAMMA_OUT:{
  2927. viv_check_retval(copy_from_user
  2928. (&dev->gamma_out, args,
  2929. sizeof(dev->gamma_out)));
  2930. ret = isp_s_gamma_out(dev);
  2931. break;
  2932. }
  2933. case ISPIOC_SET_BUFFER:{
  2934. struct isp_buffer_context buf;
  2935. viv_check_retval(copy_from_user
  2936. (&buf, args, sizeof(buf)));
  2937. #if defined(__KERNEL__) && defined(ENABLE_IRQ)
  2938. if (dev->alloc)
  2939. ret = dev->alloc(dev, &buf);
  2940. #else
  2941. ret = isp_set_buffer(dev, &buf);
  2942. #endif
  2943. break;
  2944. }
  2945. case ISPIOC_SET_BP_BUFFER:{
  2946. struct isp_bp_buffer_context buf;
  2947. viv_check_retval(copy_from_user
  2948. (&buf, args, sizeof(buf)));
  2949. ret = isp_set_bp_buffer(dev, &buf);
  2950. break;
  2951. }
  2952. case ISPIOC_START_CAPTURE:{
  2953. u32 num;
  2954. viv_check_retval(copy_from_user
  2955. (&num, args, sizeof(num)));
  2956. ret = isp_start_stream(dev, num);
  2957. if(!ret) {
  2958. dev->streaming = true;
  2959. }
  2960. break;
  2961. }
  2962. #if defined(ISP_3DNR_V2) || defined(ISP_3DNR_V2_V1)
  2963. case ISPIOC_S_3DNR_CMP: {
  2964. viv_check_retval(
  2965. copy_from_user(&dev->dnr3.compress, args, sizeof(dev->dnr3.compress)));
  2966. ret = isp_s_3dnr_cmp(dev);
  2967. break;
  2968. }
  2969. #endif
  2970. #if defined(ISP_3DNR) || defined(ISP_3DNR_V2)
  2971. case ISPIOC_U_3DNR:{
  2972. struct isp_3dnr_update param;
  2973. viv_check_retval(copy_from_user
  2974. (&param, args, sizeof(param)));
  2975. ret = isp_u_3dnr(dev, &param);
  2976. break;
  2977. }
  2978. case ISPIOC_S_3DNR:
  2979. viv_check_retval(copy_from_user
  2980. (&dev->dnr3, args, sizeof(dev->dnr3)));
  2981. ret = isp_s_3dnr(dev);
  2982. break;
  2983. case ISPIOC_U_3DNR_STRENGTH: {
  2984. viv_check_retval(
  2985. copy_from_user(&dev->dnr3, args, sizeof(dev->dnr3)));
  2986. ret = isp_u_3dnr_strength(dev);
  2987. break;
  2988. }
  2989. case ISPIOC_S_3DNR_MOT:{
  2990. viv_check_retval(copy_from_user
  2991. (&dev->dnr3, args, sizeof(dev->dnr3)));
  2992. ret = isp_s_3dnr_motion(dev);
  2993. break;
  2994. }
  2995. case ISPIOC_S_3DNR_DLT:{
  2996. viv_check_retval(copy_from_user
  2997. (&dev->dnr3, args, sizeof(dev->dnr3)));
  2998. ret = isp_s_3dnr_delta(dev);
  2999. break;
  3000. }
  3001. case ISPIOC_G_3DNR:{
  3002. u32 avg;
  3003. ret = isp_g_3dnr(dev, &avg);
  3004. viv_check_retval(copy_to_user(args, &avg, sizeof(avg)));
  3005. break;
  3006. }
  3007. #endif
  3008. case ISPIOC_G_AWBMEAN:{
  3009. struct isp_awb_mean mean;
  3010. ret = isp_g_awbmean(dev, &mean);
  3011. viv_check_retval(copy_to_user
  3012. (args, &mean, sizeof(mean)));
  3013. break;
  3014. }
  3015. case ISPIOC_G_EXPMEAN:{
  3016. u8 mean[25];
  3017. ret = isp_g_expmean(dev, mean);
  3018. viv_check_retval(copy_to_user
  3019. (args, mean, sizeof(mean)));
  3020. break;
  3021. }
  3022. case ISPIOC_G_HDREXPMEAN:{
  3023. u8 mean[75];
  3024. ret = isp_g_hdrexpmean(dev, mean);
  3025. viv_check_retval(copy_to_user
  3026. (args, mean, sizeof(mean)));
  3027. break;
  3028. }
  3029. case ISPIOC_G_HISTMEAN:{
  3030. u32 mean[HIST_BIN_TOTAL];
  3031. ret = isp_g_histmean(dev, mean);
  3032. viv_check_retval(copy_to_user
  3033. (args, mean, sizeof(mean)));
  3034. break;
  3035. }
  3036. case ISPIOC_G_HDRHISTMEAN:{
  3037. u32 mean[48];
  3038. ret = isp_g_hdrhistmean(dev, mean);
  3039. viv_check_retval(copy_to_user
  3040. (args, mean, sizeof(mean)));
  3041. break;
  3042. }
  3043. #ifdef ISP_HIST64
  3044. case ISPIOC_G_HIST64MEAN:{
  3045. u32 mean[HIST64_BIN_TOTAL];
  3046. ret = isp_g_hist64mean(dev, mean);
  3047. viv_check_retval(copy_to_user
  3048. (args, mean, sizeof(mean)));
  3049. break;
  3050. }
  3051. case ISPIOC_G_HIST64VSTART_STATUS:{
  3052. u32 status = 0;
  3053. ret = isp_g_hist64_vstart_status(dev, &status);
  3054. viv_check_retval(copy_to_user
  3055. (args, &status, sizeof(status)));
  3056. break;
  3057. }
  3058. #endif
  3059. case ISPIOC_G_VSM:{
  3060. struct isp_vsm_result vsm;
  3061. ret = isp_g_vsm(dev, &vsm);
  3062. viv_check_retval(copy_to_user(args, &vsm, sizeof(vsm)));
  3063. break;
  3064. }
  3065. case ISPIOC_G_AFM:{
  3066. struct isp_afm_result afm;
  3067. ret = isp_g_afm(dev, &afm);
  3068. viv_check_retval(copy_to_user(args, &afm, sizeof(afm)));
  3069. break;
  3070. }
  3071. case ISPIOC_G_STATUS:
  3072. ret = isp_ioc_g_status(dev, args);
  3073. break;
  3074. case ISPIOC_G_FEATURE:
  3075. ret = isp_ioc_g_feature(dev, args);
  3076. break;
  3077. case ISPIOC_G_FEATURE_VERSION:
  3078. ret = isp_ioc_g_feature_veresion(dev, args);
  3079. break;
  3080. case ISPIOC_WDR_CONFIG:
  3081. viv_check_retval(copy_from_user
  3082. (&dev->wdr, args, sizeof(dev->wdr)));
  3083. ret = isp_s_wdr(dev);
  3084. break;
  3085. case ISPIOC_S_WDR_CURVE:
  3086. viv_check_retval(copy_from_user
  3087. (&dev->wdr, args, sizeof(dev->wdr)));
  3088. ret = isp_s_wdr_curve(dev);
  3089. break;
  3090. case ISPIOC_ENABLE_GCMONO:
  3091. viv_check_retval(copy_from_user
  3092. (&dev->gcmono.mode, args, sizeof(u32)));
  3093. ret = isp_enable_gcmono(dev);
  3094. break;
  3095. case ISPIOC_DISABLE_GCMONO:
  3096. ret = isp_disable_gcmono(dev);
  3097. break;
  3098. case ISPIOC_S_GCMONO:{
  3099. struct isp_gcmono_data *data;
  3100. #ifdef __KERNEL__
  3101. data = (struct isp_gcmono_data *)
  3102. kmalloc(sizeof(struct isp_gcmono_data), GFP_KERNEL);
  3103. #else
  3104. data = (struct isp_gcmono_data *)
  3105. malloc(sizeof(struct isp_gcmono_data));
  3106. #endif
  3107. if (data == NULL) {
  3108. isp_err("%s, malloc mem for rgb gamma failed.", __func__);
  3109. ret = -1;
  3110. } else {
  3111. viv_check_retval(copy_from_user
  3112. (data, args,
  3113. sizeof(struct
  3114. isp_gcmono_data)));
  3115. ret = isp_s_gcmono(dev, data);
  3116. #ifdef __KERNEL__
  3117. kfree(data);
  3118. #else
  3119. free(data);
  3120. #endif
  3121. }
  3122. break;
  3123. }
  3124. case ISPIOC_ENABLE_RGBGAMMA:
  3125. ret = isp_enable_rgbgamma(dev);
  3126. break;
  3127. case ISPIOC_DISABLE_RGBGAMMA:
  3128. ret = isp_disable_rgbgamma(dev);
  3129. break;
  3130. case ISPIOC_S_RGBGAMMA:{
  3131. struct isp_rgbgamma_data *data;
  3132. #ifdef __KERNEL__
  3133. data = (struct isp_rgbgamma_data *)
  3134. kmalloc(sizeof(struct isp_rgbgamma_data),
  3135. GFP_KERNEL);
  3136. #else
  3137. data = (struct isp_rgbgamma_data *)
  3138. malloc(sizeof(struct isp_rgbgamma_data));
  3139. #endif
  3140. if (data == NULL) {
  3141. isp_err("%s, malloc mem for rgb gamma failed.", __func__);
  3142. ret = -1;
  3143. } else {
  3144. viv_check_retval(copy_from_user
  3145. (data, args,
  3146. sizeof(struct
  3147. isp_rgbgamma_data)));
  3148. dev->rgbgamma.data = data;
  3149. ret = isp_s_rgbgamma(dev);
  3150. //#ifdef __KERNEL__
  3151. // kfree(data);
  3152. //#else
  3153. // free(data);
  3154. //#endif
  3155. }
  3156. break;
  3157. }
  3158. case ISPIOC_S_GREENEQUILIBRATE:
  3159. viv_check_retval(copy_from_user
  3160. (&dev->ge, args, sizeof(dev->ge)));
  3161. ret = isp_s_ge(dev);
  3162. break;
  3163. case ISPIOC_S_COLOR_ADJUST:
  3164. viv_check_retval(copy_from_user
  3165. (&dev->ca, args, sizeof(dev->ca)));
  3166. ret = isp_s_ca(dev);
  3167. break;
  3168. #ifdef __KERNEL__
  3169. case VIDIOC_QUERYCAP:
  3170. ret = isp_ioc_qcap(dev, args);
  3171. break;
  3172. #endif
  3173. case ISPIOC_G_QUERY_EXTMEM:
  3174. ret = isp_get_extmem(dev, args);
  3175. break;
  3176. case ISPIOC_ENABLE_RGBIR:
  3177. viv_check_retval(copy_from_user
  3178. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3179. ret = isp_enable_rgbir(dev);
  3180. break;
  3181. case ISPIOC_S_RGBIR:
  3182. viv_check_retval(copy_from_user
  3183. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3184. ret = isp_s_rgbir(dev);
  3185. break;
  3186. case ISPIOC_RGBIR_HW_INIT:
  3187. viv_check_retval(copy_from_user
  3188. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3189. ret = isp_rgbir_hw_init(dev);
  3190. break;
  3191. case ISPIOC_RGBIR_S_IR_DNR:
  3192. viv_check_retval(copy_from_user
  3193. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3194. ret = isp_rgbir_s_ir_dnr(dev);
  3195. break;
  3196. case ISPIOC_RGBIR_S_SHARPEN:
  3197. viv_check_retval(copy_from_user
  3198. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3199. ret = isp_rgbir_s_sharpen(dev);
  3200. break;
  3201. case ISPIOC_RGBIR_S_DES:
  3202. viv_check_retval(copy_from_user
  3203. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3204. ret = isp_rgbir_s_des(dev);
  3205. break;
  3206. case ISPIOC_RGBIR_S_CC_MATRIX:
  3207. viv_check_retval(copy_from_user
  3208. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3209. ret = isp_rgbir_s_cc_matrix(dev);
  3210. break;
  3211. case ISPIOC_RGBIR_S_DPCC:
  3212. viv_check_retval(copy_from_user
  3213. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3214. ret = isp_rgbir_s_dpcc(dev);
  3215. break;
  3216. case ISPIOC_RGBIR_S_GAIN:
  3217. viv_check_retval(copy_from_user
  3218. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3219. ret = isp_rgbir_s_gain(dev);
  3220. break;
  3221. case ISPIOC_RGBIR_S_BLS:
  3222. viv_check_retval(copy_from_user
  3223. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3224. ret = isp_rgbir_s_bls(dev);
  3225. break;
  3226. case ISPIOC_RGBIR_S_IR_RAW_OUT:
  3227. viv_check_retval(copy_from_user
  3228. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3229. ret = isp_rgbir_out_ir_raw(dev);
  3230. break;
  3231. case ISPIOC_S_CROP:
  3232. viv_check_retval(copy_from_user
  3233. (&dev->crop, args, sizeof(struct isp_crop_context) * 3));
  3234. ret = isp_set_crop(dev);
  3235. break;
  3236. #ifdef ISP_3DNR_V3
  3237. case ISPIOC_S_TDNR:
  3238. viv_check_retval(copy_from_user
  3239. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3240. ret = isp_s_tdnr(dev);
  3241. break;
  3242. case ISPIOC_TDNR_ENABLE:
  3243. ret = isp_tdnr_enable(dev);
  3244. break;
  3245. case ISPIOC_TDNR_DISABLE:
  3246. ret = isp_tdnr_disable(dev);
  3247. break;
  3248. case ISPIOC_TDNR_ENABLE_TDNR:
  3249. ret = isp_tdnr_enable_tdnr(dev);
  3250. break;
  3251. case ISPIOC_TDNR_DISABLE_TDNR:
  3252. ret = isp_tdnr_disable_tdnr(dev);
  3253. break;
  3254. case ISPIOC_TDNR_ENABLE_2DNR:
  3255. ret = isp_tdnr_enable_2dnr(dev);
  3256. break;
  3257. case ISPIOC_TDNR_DISABLE_2DNR:
  3258. ret = isp_tdnr_disable_2dnr(dev);
  3259. break;
  3260. case ISPIOC_S_TDNR_CURVE:
  3261. viv_check_retval(copy_from_user
  3262. (&dev->tdnr.curve, args, sizeof(dev->tdnr.curve)));
  3263. ret = isp_tdnr_cfg_gamma(dev);
  3264. break;
  3265. case ISPIOC_G_TDNR: {
  3266. struct isp_tdnr_stats stats;
  3267. ret = isp_tdnr_g_stats(dev, &stats);
  3268. viv_check_retval(copy_to_user(args, &stats, sizeof(stats)));
  3269. }
  3270. break;
  3271. case ISPIOC_S_TDNR_STRENGTH:
  3272. viv_check_retval(copy_from_user
  3273. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3274. ret = isp_tdnr_set_strength(dev);
  3275. break;
  3276. case ISPIOC_U_TDNR_NOISE:
  3277. viv_check_retval(copy_from_user
  3278. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3279. ret = isp_tdnr_u_noise(dev);
  3280. break;
  3281. case ISPIOC_U_TDNR_THR:
  3282. viv_check_retval(copy_from_user
  3283. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3284. ret = isp_tdnr_u_thr(dev);
  3285. break;
  3286. case ISPIOC_R_TDNR_REFER:
  3287. ret = isp_r_tdnr_refer(dev);
  3288. break;
  3289. case ISPIOC_R_TDNR_MOTION:
  3290. ret = isp_r_tdnr_motion(dev);
  3291. break;
  3292. case ISPIOC_S_TDNR_BUF:
  3293. viv_check_retval(copy_from_user
  3294. (&dev->tdnr.buf, args, sizeof(dev->tdnr.buf)));
  3295. ret = isp_tdnr_s_buf(dev);
  3296. break;
  3297. #endif
  3298. #ifdef ISP_MI_PP_WRITE
  3299. case ISPIOC_GET_PPW_LINE_CNT:
  3300. {
  3301. u16 ppw_pic_cnt;
  3302. ret = isp_get_ppw_pic_cnt(dev, &ppw_pic_cnt);
  3303. viv_check_retval(copy_to_user
  3304. (args, &ppw_pic_cnt, sizeof(ppw_pic_cnt)));
  3305. break;
  3306. }
  3307. case ISPIOC_SET_PPW_LINE_NUM:
  3308. {
  3309. viv_check_retval(copy_from_user
  3310. (&dev->pp_write, args, sizeof(dev->pp_write)));
  3311. ret = isp_set_ppw_line_num(dev);
  3312. break;
  3313. }
  3314. #endif
  3315. #ifdef ISP_MI_PP_READ
  3316. case ISPIOC_CFG_DMA_LINE_ENTRY:
  3317. viv_check_retval(copy_from_user
  3318. (&dev->pp_dma_line_entry, args, sizeof(dev->pp_dma_line_entry)));
  3319. ret = isp_cfg_pp_dma_line_entry(dev);
  3320. break;
  3321. #endif
  3322. case ISPIOC_GET_FRAME_MASK_INFO_ADDR: {
  3323. unsigned long addr;
  3324. addr = dev->frame_mark_info_addr;
  3325. isp_info("ISPIOC_GET_FRAME_MASK_INFO_ADDR %lx\n", addr);
  3326. viv_check_retval(copy_to_user(args, &addr, sizeof(addr)));
  3327. ret = 0;
  3328. }
  3329. break;
  3330. default:
  3331. isp_err("unsupported command %d", cmd);
  3332. break;
  3333. }
  3334. if (cmd != ISPIOC_WRITE_REG) //frame end isp update shd registers.
  3335. ISP_GEN_CFG_UPDATE(dev);
  3336. return ret;
  3337. }