isp_dmsc2.c 16 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. #ifdef __KERNEL__
  54. #include <linux/io.h>
  55. #include <linux/module.h>
  56. #endif
  57. #include "mrv_all_bits.h"
  58. #include "isp_ioctl.h"
  59. #include "isp_types.h"
  60. extern MrvAllRegister_t *all_regs;
  61. #ifdef ISP_DEMOSAIC2
  62. int isp_enable_dmsc(struct isp_ic_dev *dev)
  63. {
  64. u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  65. u32 isp_dmsc_size_ctrl =
  66. isp_read_reg(dev, REG_ADDR(isp_dmsc_size_ctrl));
  67. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_BYPASS, 0U);
  68. REG_SET_SLICE(isp_dmsc_size_ctrl, ISP_DMSC_IMAGE_H_SIZE,
  69. isp_read_reg(dev, REG_ADDR(isp_acq_h_size)));
  70. REG_SET_SLICE(isp_dmsc_size_ctrl, ISP_DMSC_IMAGE_H_BLANK, 0x039c);
  71. isp_write_reg(dev, REG_ADDR(isp_dmsc_size_ctrl), isp_dmsc_size_ctrl);
  72. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  73. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl_shd), isp_dmsc_ctrl);
  74. return 0;
  75. }
  76. int isp_disable_dmsc(struct isp_ic_dev *dev)
  77. {
  78. u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  79. isp_dmsc_ctrl = 0; //clear fpga default bit 3 and 13 to keep the same value with cmodel.
  80. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_BYPASS, 1U);
  81. /*clear the reg default val to keep weith cmodel */
  82. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_fact), 0);
  83. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_clip), 0);
  84. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_filt2), 0);
  85. isp_write_reg(dev, REG_ADDR(isp_dmsc_dpul_ctrl), 0);
  86. isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cb), 0);
  87. //isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_a), 0);
  88. //isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_c), 0);
  89. isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_ctrl), 0);
  90. isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_thr), 0);
  91. isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cr), 0);
  92. isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_y), 0);
  93. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  94. return 0;
  95. }
  96. int isp_set_dmsc_intp(struct isp_ic_dev *dev)
  97. {
  98. u32 isp_dmsc_intp_thr = isp_read_reg(dev, REG_ADDR(isp_dmsc_intp_thr));
  99. REG_SET_SLICE(isp_dmsc_intp_thr, ISP_DMSC_INTERPLATION_DIR_THR_MAX,
  100. dev->demosaic.intp.intp_dir_thr_max);
  101. REG_SET_SLICE(isp_dmsc_intp_thr, ISP_DMSC_INTERPLATION_DIR_THR_MIN,
  102. dev->demosaic.intp.intp_dir_thr_min);
  103. isp_write_reg(dev, REG_ADDR(isp_dmsc_intp_thr), isp_dmsc_intp_thr);
  104. return 0;
  105. }
  106. int isp_set_dmsc_dmoi(struct isp_ic_dev *dev)
  107. {
  108. struct isp_dmoi_context *pDemoire = &dev->demosaic.demoire;
  109. u32 isp_dmsc_dmoi_ctrl =
  110. isp_read_reg(dev, REG_ADDR(isp_dmsc_dmoi_ctrl));
  111. u32 isp_dmsc_dmoi_thr = isp_read_reg(dev, REG_ADDR(isp_dmsc_dmoi_thr));
  112. u32 isp_dmsc_dmoi_patn_thr =
  113. isp_read_reg(dev, REG_ADDR(isp_dmsc_dmoi_patn_thr));
  114. u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  115. if (!pDemoire->enable) {
  116. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEMOIRE_ENABLE, 0U);
  117. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  118. return 0;
  119. }
  120. REG_SET_SLICE(isp_dmsc_dmoi_ctrl, ISP_DMSC_DEMOIRE_AREA_THR,
  121. pDemoire->demoire_area_thr);
  122. REG_SET_SLICE(isp_dmsc_dmoi_ctrl, ISP_DMSC_DEMOIRE_SAT_SHRINK,
  123. pDemoire->demoire_sat_shrink);
  124. REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_R2,
  125. pDemoire->demoire_r2);
  126. REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_R1,
  127. pDemoire->demoire_r1);
  128. REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_T2_SHIFT,
  129. pDemoire->demoire_t2_shift);
  130. REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_T1,
  131. pDemoire->demoire_t1);
  132. REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_R2,
  133. pDemoire->demoire_edge_r2);
  134. REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_R1,
  135. pDemoire->demoire_edge_r1);
  136. REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_T2_SHIFT,
  137. pDemoire->demoire_edge_t2_shift);
  138. REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_T1,
  139. pDemoire->demoire_edge_t1);
  140. isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_ctrl), isp_dmsc_dmoi_ctrl);
  141. isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_thr), isp_dmsc_dmoi_thr);
  142. isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_patn_thr),
  143. isp_dmsc_dmoi_patn_thr);
  144. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEMOIRE_ENABLE, 1U);
  145. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  146. return 0;
  147. }
  148. int isp_set_dmsc_sharpen(struct isp_ic_dev *dev)
  149. {
  150. struct isp_shap_context *pSharpen = &dev->demosaic.sharpen;
  151. u32 isp_dmsc_shap_fact =
  152. isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_fact));
  153. u32 isp_dmsc_shap_clip =
  154. isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_clip));
  155. u32 isp_dmsc_shap_thr = isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_thr));
  156. u32 isp_dmsc_shap_ratio =
  157. isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_ratio));
  158. u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  159. if (!pSharpen->enable) {
  160. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_ENBALE, 0);
  161. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  162. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl_shd), isp_dmsc_ctrl);
  163. return 0;
  164. }
  165. REG_SET_SLICE(isp_dmsc_shap_fact, ISP_DMSC_SHARPEN_FACTOR_BLACK,
  166. pSharpen->sharpen_factor_black);
  167. REG_SET_SLICE(isp_dmsc_shap_fact, ISP_DMSC_SHARPEN_FACTOR_WHITE,
  168. pSharpen->sharpen_factor_white);
  169. REG_SET_SLICE(isp_dmsc_shap_clip, ISP_DMSC_SHARPEN_CLIP_BLACK,
  170. pSharpen->sharpen_clip_black);
  171. REG_SET_SLICE(isp_dmsc_shap_clip, ISP_DMSC_SHARPEN_CLIP_WHITE,
  172. pSharpen->sharpen_clip_white);
  173. REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T4_SHIFT,
  174. pSharpen->sharpen_t4_shift);
  175. REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T3,
  176. pSharpen->sharpen_t3);
  177. REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T2_SHIFT,
  178. pSharpen->sharpen_t2_shift);
  179. REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T1,
  180. pSharpen->sharpen_t1);
  181. REG_SET_SLICE(isp_dmsc_shap_ratio, ISP_DMSC_SHARPEN_R3,
  182. pSharpen->sharpen_r3);
  183. REG_SET_SLICE(isp_dmsc_shap_ratio, ISP_DMSC_SHARPEN_R2,
  184. pSharpen->sharpen_r2);
  185. REG_SET_SLICE(isp_dmsc_shap_ratio, ISP_DMSC_SHARPEN_R1,
  186. pSharpen->sharpen_r1);
  187. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_fact), isp_dmsc_shap_fact);
  188. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_clip), isp_dmsc_shap_clip);
  189. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_thr), isp_dmsc_shap_thr);
  190. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_ratio), isp_dmsc_shap_ratio);
  191. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_ENBALE, 1);
  192. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  193. return 0;
  194. }
  195. int isp_set_dmsc_gfilter(struct isp_ic_dev *dev)
  196. {
  197. struct isp_gfilter_context *pgfilter = &dev->demosaic.gFilter;
  198. u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  199. u32 isp_dmsc_shap_filt1 =
  200. isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_filt1));
  201. u32 isp_dmsc_shap_filt2 =
  202. isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_filt2));
  203. REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_00,
  204. pgfilter->hf_filt_00);
  205. REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_01,
  206. pgfilter->hf_filt_01);
  207. REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_02,
  208. pgfilter->hf_filt_02);
  209. REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_10,
  210. pgfilter->hf_filt_10);
  211. REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_11,
  212. pgfilter->hf_filt_11);
  213. REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_12,
  214. pgfilter->hf_filt_12);
  215. REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_20,
  216. pgfilter->hf_filt_20);
  217. REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_21,
  218. pgfilter->hf_filt_21);
  219. REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_22,
  220. pgfilter->hf_filt_22);
  221. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_filt1), isp_dmsc_shap_filt1);
  222. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_filt2), isp_dmsc_shap_filt2);
  223. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_SIZE, pgfilter->sharpen_size);
  224. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  225. return 0;
  226. }
  227. int isp_set_dmsc_sharpen_line(struct isp_ic_dev *dev)
  228. {
  229. struct isp_shap_line_context *sharpenLine = &dev->demosaic.sharpenLine;
  230. u32 isp_dmsc_shap_line_ctrl =
  231. isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_line_ctrl));
  232. u32 isp_dmsc_shap_line_ratio =
  233. isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_line_ratio));
  234. u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  235. if (!sharpenLine->enable) {
  236. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_LINE_ENABLE, 0);
  237. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  238. return 0;
  239. }
  240. REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_SHIFT2,
  241. sharpenLine->sharpen_line_shift2);
  242. REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_SHIFT1,
  243. sharpenLine->sharpen_line_shift1);
  244. REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_T1,
  245. sharpenLine->sharpen_line_t1);
  246. REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_STRENGTH,
  247. sharpenLine->sharpen_line_strength);
  248. REG_SET_SLICE(isp_dmsc_shap_line_ratio, ISP_DMSC_SHARPEN_LINE_R2,
  249. sharpenLine->sharpen_line_r2);
  250. REG_SET_SLICE(isp_dmsc_shap_line_ratio, ISP_DMSC_SHARPEN_LINE_R1,
  251. sharpenLine->sharpen_line_r1);
  252. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_line_ctrl),
  253. isp_dmsc_shap_line_ctrl);
  254. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_line_ratio),
  255. isp_dmsc_shap_line_ratio);
  256. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_LINE_ENABLE, 1);
  257. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  258. return 0;
  259. }
  260. int isp_set_dmsc_cac(struct isp_ic_dev *dev)
  261. {
  262. struct isp_cac_context *cac = &dev->cac;
  263. u32 val = 0;
  264. u32 isp_dmsc_cac_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_cac_ctrl));
  265. if (!cac->enable) {
  266. REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_CAC_EN, 0);
  267. isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_ctrl),
  268. isp_dmsc_cac_ctrl);
  269. return 0;
  270. }
  271. REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_H_CLIP_MODE, cac->hmode);
  272. REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_V_CLIP_MODE, cac->vmode);
  273. isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_count_start),
  274. cac->hstart | (cac->vstart << 16));
  275. isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_a), cac->ar | (cac->ab << 16));
  276. isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_b), cac->br | (cac->bb << 16));
  277. isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_c), cac->cr | (cac->cb << 16));
  278. REG_SET_SLICE(val, MRV_CAC_X_NS, cac->xns);
  279. REG_SET_SLICE(val, MRV_CAC_X_NF, cac->xnf);
  280. isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_x_norm), val);
  281. val = 0;
  282. REG_SET_SLICE(val, MRV_CAC_Y_NS, cac->yns);
  283. REG_SET_SLICE(val, MRV_CAC_Y_NF, cac->ynf);
  284. isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_y_norm), val);
  285. REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_CAC_EN, 1);
  286. isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_ctrl), isp_dmsc_cac_ctrl);
  287. return 0;
  288. }
  289. int isp_set_dmsc_depurple(struct isp_ic_dev *dev)
  290. {
  291. struct isp_depurple_context *depurple = &dev->demosaic.depurple;
  292. u32 isp_dmsc_dpul_ctrl =
  293. isp_read_reg(dev, REG_ADDR(isp_dmsc_dpul_ctrl));
  294. u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  295. if (!depurple->enable) {
  296. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEPURPLE_ENABLE, 0U);
  297. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  298. return 0;
  299. }
  300. REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_RED_SAT, depurple->red_sat);
  301. REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_BLUE_SAT, depurple->blue_sat);
  302. REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_SAT_SHRINK,
  303. depurple->depurple_sat_shrink);
  304. REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_THR,
  305. depurple->depurple_thr);
  306. isp_write_reg(dev, REG_ADDR(isp_dmsc_dpul_ctrl), isp_dmsc_dpul_ctrl);
  307. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEPURPLE_ENABLE, 1U);
  308. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  309. return 0;
  310. }
  311. int isp_set_dmsc_skin(struct isp_ic_dev *dev)
  312. {
  313. struct isp_skin_context *skin = &dev->demosaic.skin;
  314. u32 isp_dmsc_skin_thr_cb =
  315. isp_read_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cb));
  316. u32 isp_dmsc_skin_thr_cr =
  317. isp_read_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cr));
  318. u32 isp_dmsc_skin_thr_y =
  319. isp_read_reg(dev, REG_ADDR(isp_dmsc_skin_thr_y));
  320. u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  321. if (!skin->enable) {
  322. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SKIN_ENABLE, 0U);
  323. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  324. return 0;
  325. }
  326. REG_SET_SLICE(isp_dmsc_skin_thr_cb, ISP_DMSC_SKIN_CB_THR_MAX_2047,
  327. skin->cb_thr_max_2047);
  328. REG_SET_SLICE(isp_dmsc_skin_thr_cb, ISP_DMSC_SKIN_CB_THR_MIN_2047,
  329. skin->cb_thr_min_2047);
  330. REG_SET_SLICE(isp_dmsc_skin_thr_cr, ISP_DMSC_SKIN_CR_THR_MAX_2047,
  331. skin->cr_thr_max_2047);
  332. REG_SET_SLICE(isp_dmsc_skin_thr_cr, ISP_DMSC_SKIN_CR_THR_MIN_2047,
  333. skin->cr_thr_min_2047);
  334. REG_SET_SLICE(isp_dmsc_skin_thr_y, ISP_DMSC_SKIN_Y_THR_MAX,
  335. skin->y_thr_max_2047);
  336. REG_SET_SLICE(isp_dmsc_skin_thr_y, ISP_DMSC_SKIN_Y_THR_MIN,
  337. skin->y_thr_min_2047);
  338. isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cb),
  339. isp_dmsc_skin_thr_cb);
  340. isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cr),
  341. isp_dmsc_skin_thr_cr);
  342. isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_y), isp_dmsc_skin_thr_y);
  343. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SKIN_ENABLE, 1U);
  344. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  345. return 0;
  346. }
  347. int isp_s_dmsc(struct isp_ic_dev *dev)
  348. {
  349. u32 isp_dmsc_ctrl;
  350. /*Clear the cmodel register default value to match the fpga default value */
  351. isp_disable_dmsc(dev);
  352. isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  353. isp_info("enter %s\n", __func__);
  354. if (!dev->demosaic.enable) {
  355. isp_disable_dmsc(dev);
  356. return 0;
  357. }
  358. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_THR,
  359. dev->demosaic.demosaic_thr);
  360. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DENOISE_STRENGTH,
  361. dev->demosaic.denoise_stren);
  362. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  363. isp_set_dmsc_intp(dev);
  364. isp_enable_dmsc(dev);
  365. isp_set_dmsc_gfilter(dev);
  366. return 0;
  367. }
  368. #endif