platform_nwl_csi_driver.c 5.8 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. #include <linux/module.h>
  54. #include <linux/uaccess.h>
  55. #ifdef ISP8000L_V2008
  56. #include <linux/io.h> //Fix thead compile error.
  57. #endif
  58. #include "nwl_regs.h"
  59. #include "csi_ioctl.h"
  60. int vvnative_csi_module_init(void * dev);
  61. int vvnative_csi_module_exit(void * dev);
  62. int vvnative_csi_set_stream_control(void * dev);
  63. int vvnative_csi_set_cfg(void * dev);
  64. int vvnative_csi_set_bit_shift(void *dev);
  65. static int nwl_register_write(void * dev,unsigned int addr, unsigned int data)
  66. {
  67. void __iomem *base_addr;
  68. struct vvcam_csi_dev *nwl_csi_dev;
  69. if (dev == NULL)
  70. return -1;
  71. nwl_csi_dev = dev;
  72. base_addr = nwl_csi_dev->base;
  73. writel(data, base_addr + addr);
  74. return 0;
  75. }
  76. #if 0
  77. static int nwl_register_read(void * dev,unsigned int addr, unsigned int *data)
  78. {
  79. void __iomem *base_addr;
  80. struct vvcam_csi_dev *nwl_csi_dev;
  81. if (dev == NULL)
  82. return -1;
  83. nwl_csi_dev = dev;
  84. base_addr = nwl_csi_dev->base;
  85. *data = readl(base_addr + addr);
  86. return 0;
  87. }
  88. #endif
  89. int vvnative_csi_set_stream_control(void * dev)
  90. {
  91. struct vvcam_csi_dev *nwl_csi_dev;
  92. u32 clock_status;
  93. u32 data_status;
  94. if (dev == NULL)
  95. return -1;
  96. nwl_csi_dev = dev;
  97. if (nwl_csi_dev->streaming_enable)
  98. {
  99. clock_status = 0x01;
  100. data_status = 0xFF;
  101. }
  102. else
  103. {
  104. clock_status = 0x00;
  105. data_status = 0x00;
  106. }
  107. nwl_register_write(dev,MRV_MIPICSI_LANES_CLK, clock_status);
  108. nwl_register_write(dev,MRV_MIPICSI_LANES_DATA, data_status);
  109. return 0;
  110. }
  111. int vvnative_csi_set_cfg(void * dev)
  112. {
  113. struct vvcam_csi_dev *nwl_csi_dev;
  114. if (dev == NULL)
  115. return -1;
  116. nwl_csi_dev = dev;
  117. nwl_register_write(dev,MRV_MIPICSI_NUM_LANES, nwl_csi_dev->csi_lane_cfg.mipi_lane_num);
  118. switch (nwl_csi_dev->csi_lane_cfg.mipi_lane_num)
  119. {
  120. case 1:
  121. nwl_register_write(dev,MRV_MIPICSI_LANES_DATA, 0x01);
  122. break;
  123. case 2:
  124. nwl_register_write(dev,MRV_MIPICSI_LANES_DATA, 0x03);
  125. break;
  126. case 4:
  127. nwl_register_write(dev,MRV_MIPICSI_LANES_DATA, 0x0F);
  128. break;
  129. default:
  130. break;
  131. }
  132. return 0;
  133. }
  134. int vvnative_csi_set_bit_shift(void * dev)
  135. {
  136. struct vvcam_csi_dev *nwl_csi_dev;
  137. if (dev == NULL)
  138. return -1;
  139. nwl_csi_dev = dev;
  140. if (nwl_csi_dev->device_idx == 0)
  141. {
  142. #ifndef INPUT_SIGNAL_12_BIT
  143. nwl_register_write(dev,MRV_MIPICSI0_CTRL, 16 - nwl_csi_dev->bit_width); //16bit high-aligned
  144. #else
  145. nwl_register_write(dev,MRV_MIPICSI0_CTRL, 0x0); //input signal 12 bit does not need to shift
  146. #endif
  147. }else
  148. {
  149. #ifndef INPUT_SIGNAL_12_BIT
  150. nwl_register_write(dev,MRV_MIPICSI1_CTRL, 16 - nwl_csi_dev->bit_width); //16bit high-aligned
  151. #else
  152. nwl_register_write(dev,MRV_MIPICSI0_CTRL, 0x0); //input signal 12 bit does not need to shift
  153. #endif
  154. }
  155. return 0;
  156. }
  157. int vvnative_csi_module_init(void * dev)
  158. {
  159. struct vvcam_csi_dev *nwl_csi_dev;
  160. if (dev == NULL)
  161. return -1;
  162. nwl_csi_dev = dev;
  163. nwl_register_write(dev,MRV_MIPICSI_NUM_LANES, 0x04);
  164. nwl_register_write(dev,MRV_MIPICSI_LANES_CLK, 0x01);
  165. nwl_register_write(dev,MRV_MIPICSI_LANES_DATA, 0x0F);
  166. nwl_register_write(dev,MRV_MIPICSI_IGNORE_VC, 0x01);
  167. nwl_register_write(dev,MRV_MIPICSI_FIFO_SENSD_LEVEL, 0x41);
  168. nwl_register_write(dev,MRV_MIPICSI_VID_VSYNC, 0x20);
  169. nwl_register_write(dev,MRV_MIPICSI_VID_HSYNC_FP, 0x20);
  170. nwl_register_write(dev,MRV_MIPICSI_VID_HSYNC, 0x01);
  171. nwl_register_write(dev,MRV_MIPICSI_VID_HSYNC_BP, 0x20);
  172. if (nwl_csi_dev->device_idx == 0)
  173. {
  174. nwl_register_write(dev,MRV_MIPICSI0_CTRL, 0);
  175. }else
  176. {
  177. nwl_register_write(dev,MRV_MIPICSI1_CTRL, 0);
  178. }
  179. return 0;
  180. }
  181. int vvnative_csi_module_exit(void * dev)
  182. {
  183. return 0;
  184. }