dw-mipi-csi.h 5.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
  4. *
  5. * Synopsys DesignWare MIPI CSI-2 Host controller driver
  6. *
  7. * Author: Luis Oliveira <Luis.Oliveira@synopsys.com>
  8. */
  9. #ifndef _DW_MIPI_CSI_H__
  10. #define _DW_MIPI_CSI_H__
  11. #include <linux/delay.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/io.h>
  15. #include <linux/phy/phy.h>
  16. #include <linux/delay.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/of.h>
  19. #include <linux/of_graph.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/ratelimit.h>
  22. #include <linux/reset.h>
  23. #include <linux/videodev2.h>
  24. #include <linux/wait.h>
  25. #include <dw-mipi-csi-pltfrm.h>
  26. /* Advanced features */
  27. #define IPI_DT_OVERWRITE BIT(0)
  28. #define DATA_TYPE_OVERWRITE(dt) (((dt) & GENMASK(5, 0)) << 8)
  29. #define LINE_EVENT_SELECTION(n) ((n) << 16)
  30. enum line_event {
  31. EVSELAUTO = 0,
  32. EVSELPROG = 1,
  33. };
  34. #define EN_VIDEO BIT(17)
  35. #define EN_LINE_START BIT(18)
  36. #define EN_NULL BIT(19)
  37. #define EN_BLANKING BIT(20)
  38. #define EN_EMBEDDED BIT(21)
  39. #define IPI_SYNC_EVENT_MODE(n) ((n) << 24)
  40. enum sync_event {
  41. SYNCEVFSN = 0,
  42. SYNCEVFS = 1,
  43. };
  44. /* DW MIPI CSI-2 register addresses*/
  45. struct R_CSI2 {
  46. u16 VERSION;
  47. u16 N_LANES;
  48. u16 CTRL_RESETN;
  49. u16 INTERRUPT;
  50. u16 DATA_IDS_1;
  51. u16 DATA_IDS_2;
  52. u16 DATA_IDS_VC_1;
  53. u16 DATA_IDS_VC_2;
  54. u16 IPI_MODE;
  55. u16 IPI_VCID;
  56. u16 IPI_DATA_TYPE;
  57. u16 IPI_MEM_FLUSH;
  58. u16 IPI_HSA_TIME;
  59. u16 IPI_HBP_TIME;
  60. u16 IPI_HSD_TIME;
  61. u16 IPI_HLINE_TIME;
  62. u16 IPI_SOFTRSTN;
  63. u16 IPI_ADV_FEATURES;
  64. u16 IPI_VSA_LINES;
  65. u16 IPI_VBP_LINES;
  66. u16 IPI_VFP_LINES;
  67. u16 IPI_VACTIVE_LINES;
  68. u16 VC_EXTENSION;
  69. u16 INT_PHY_FATAL;
  70. u16 MASK_INT_PHY_FATAL;
  71. u16 FORCE_INT_PHY_FATAL;
  72. u16 INT_PKT_FATAL;
  73. u16 MASK_INT_PKT_FATAL;
  74. u16 FORCE_INT_PKT_FATAL;
  75. u16 INT_FRAME_FATAL;
  76. u16 MASK_INT_FRAME_FATAL;
  77. u16 FORCE_INT_FRAME_FATAL;
  78. u16 INT_PHY;
  79. u16 MASK_INT_PHY;
  80. u16 FORCE_INT_PHY;
  81. u16 INT_PKT;
  82. u16 MASK_INT_PKT;
  83. u16 FORCE_INT_PKT;
  84. u16 INT_LINE;
  85. u16 MASK_INT_LINE;
  86. u16 FORCE_INT_LINE;
  87. u16 INT_IPI;
  88. u16 MASK_INT_IPI;
  89. u16 FORCE_INT_IPI;
  90. u16 ST_BNDRY_FRAME_FATAL;
  91. u16 MSK_BNDRY_FRAME_FATAL;
  92. u16 FORCE_BNDRY_FRAME_FATAL;
  93. u16 ST_SEQ_FRAME_FATAL;
  94. u16 MSK_SEQ_FRAME_FATAL;
  95. u16 FORCE_SEQ_FRAME_FATAL;
  96. u16 ST_CRC_FRAME_FATAL;
  97. u16 MSK_CRC_FRAME_FATAL;
  98. u16 FORCE_CRC_FRAME_FATAL;
  99. u16 ST_PLD_CRC_FATAL;
  100. u16 MSK_PLD_CRC_FATAL;
  101. u16 FORCE_PLD_CRC_FATAL;
  102. u16 ST_DATA_ID;
  103. u16 MSK_DATA_ID;
  104. u16 FORCE_DATA_ID;
  105. u16 ST_ECC_CORRECT;
  106. u16 MSK_ECC_CORRECT;
  107. u16 FORCE_ECC_CORRECT;
  108. };
  109. /* Interrupt Masks */
  110. struct interrupt_type {
  111. u32 PHY_FATAL;
  112. u32 PKT_FATAL;
  113. u32 FRAME_FATAL;
  114. u32 PHY;
  115. u32 PKT;
  116. u32 LINE;
  117. u32 IPI;
  118. u32 BNDRY_FRAME_FATAL;
  119. u32 SEQ_FRAME_FATAL;
  120. u32 CRC_FRAME_FATAL;
  121. u32 PLD_CRC_FATAL;
  122. u32 DATA_ID;
  123. u32 ECC_CORRECTED;
  124. };
  125. /* IPI Data Types */
  126. enum data_type {
  127. CSI_2_YUV420_8 = 0x18,
  128. CSI_2_YUV420_10 = 0x19,
  129. CSI_2_YUV420_8_LEG = 0x1A,
  130. CSI_2_YUV420_8_SHIFT = 0x1C,
  131. CSI_2_YUV420_10_SHIFT = 0x1D,
  132. CSI_2_YUV422_8 = 0x1E,
  133. CSI_2_YUV422_10 = 0x1F,
  134. CSI_2_RGB444 = 0x20,
  135. CSI_2_RGB555 = 0x21,
  136. CSI_2_RGB565 = 0x22,
  137. CSI_2_RGB666 = 0x23,
  138. CSI_2_RGB888 = 0x24,
  139. CSI_2_RAW6 = 0x28,
  140. CSI_2_RAW7 = 0x29,
  141. CSI_2_RAW8 = 0x2A,
  142. CSI_2_RAW10 = 0x2B,
  143. CSI_2_RAW12 = 0x2C,
  144. CSI_2_RAW14 = 0x2D,
  145. CSI_2_RAW16 = 0x2E,
  146. CSI_2_RAW20 = 0x2F,
  147. USER_DEFINED_1 = 0x30,
  148. USER_DEFINED_2 = 0x31,
  149. USER_DEFINED_3 = 0x32,
  150. USER_DEFINED_4 = 0x33,
  151. USER_DEFINED_5 = 0x34,
  152. USER_DEFINED_6 = 0x35,
  153. USER_DEFINED_7 = 0x36,
  154. USER_DEFINED_8 = 0x37,
  155. };
  156. /* DWC MIPI CSI-2 output types */
  157. enum output {
  158. IPI_OUT = 0,
  159. IDI_OUT = 1,
  160. BOTH_OUT = 2
  161. };
  162. /* IPI color components */
  163. enum color_mode {
  164. COLOR48 = 0,
  165. COLOR16 = 1
  166. };
  167. /* IPI cut through */
  168. enum cut_through {
  169. CTINACTIVE = 0,
  170. CTACTIVE = 1
  171. };
  172. /* IPI output types */
  173. enum ipi_output {
  174. CAMERA_TIMING = 0,
  175. AUTO_TIMING = 1
  176. };
  177. /* Format template */
  178. struct mipi_fmt {
  179. u32 mbus_code;
  180. u8 depth;
  181. u32 width;
  182. u32 height;
  183. };
  184. struct mipi_dt {
  185. u32 hex;
  186. char *name;
  187. };
  188. /* CSI specific configuration */
  189. struct csi_data {
  190. u32 num_lanes;
  191. u32 dphy_freq; //MBPS
  192. u32 pclk;
  193. u32 fps;
  194. u32 bpp;
  195. u32 output;
  196. u32 ipi_mode;
  197. u32 ipi_adv_features;
  198. u32 ipi_cut_through;
  199. u32 ipi_color_mode;
  200. u32 ipi_auto_flush;
  201. u32 virtual_ch;
  202. u32 hsa;
  203. u32 hbp;
  204. u32 hsd;
  205. u32 htotal;
  206. u32 vsa;
  207. u32 vbp;
  208. u32 vfp;
  209. u32 vactive;
  210. };
  211. /* Structure to embed device driver information */
  212. struct dw_csi {
  213. //struct v4l2_subdev sd;
  214. //struct video_device vdev;
  215. //struct v4l2_device v4l2_dev;
  216. struct device *dev;
  217. //struct media_pad pads[CSI_PADS_NUM];
  218. struct mipi_fmt *fmt;
  219. //struct v4l2_mbus_framefmt format;
  220. void __iomem *base_address;
  221. void __iomem *demo;
  222. void __iomem *csc;
  223. int ctrl_irq_number;
  224. int demosaic_irq;
  225. struct csi_data hw;
  226. struct reset_control *rst;
  227. struct phy *phy;
  228. struct dw_csih_pdata *config;
  229. struct mutex lock; /* protect resources sharing */
  230. spinlock_t slock; /* interrupt handling lock */
  231. u8 ipi_dt;
  232. u8 index;
  233. u8 hw_version_major;
  234. u16 hw_version_minor;
  235. };
  236. void dw_mipi_csi_reset(struct dw_csi *csi_dev);
  237. int dw_mipi_csi_mask_irq_power_off(struct dw_csi *csi_dev);
  238. int dw_mipi_csi_hw_stdby(struct dw_csi *csi_dev);
  239. void dw_mipi_csi_set_ipi_fmt(struct dw_csi *csi_dev);
  240. void dw_mipi_csi_start(struct dw_csi *csi_dev);
  241. int dw_mipi_csi_irq_handler(struct dw_csi *csi_dev);
  242. void dw_mipi_csi_get_version(struct dw_csi *csi_dev);
  243. int dw_mipi_csi_specific_mappings(struct dw_csi *csi_dev);
  244. void dw_mipi_csi_fill_timings(struct dw_csi *dev, uint32_t width, uint32_t height);
  245. void dw_mipi_csi_dump(struct dw_csi *csi_dev);
  246. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  247. int dw_csi_create_capabilities_sysfs(struct platform_device *pdev);
  248. int dw_csi_remove_capabilities_sysfs(struct platform_device *pdev);
  249. #endif
  250. int dw_mipi_csi_s_power(struct dw_csi *dev, int on);
  251. int dw_mipi_csi_log_status(struct dw_csi *dev);
  252. static inline void dw_mipi_csi_write(struct dw_csi *dev,
  253. u32 address, u32 data)
  254. {
  255. writel(data, dev->base_address + address);
  256. }
  257. static inline u32 dw_mipi_csi_read(struct dw_csi *dev, u32 address)
  258. {
  259. return readl(dev->base_address + address);
  260. }
  261. #endif /*_DW_MIPI_CSI_H__ */