dw-mipi-csi.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
  4. *
  5. * Synopsys DesignWare MIPI CSI-2 Host controller driver
  6. * Core MIPI CSI-2 functions
  7. *
  8. * Author: Luis Oliveira <Luis.Oliveira@synopsys.com>
  9. */
  10. #include "dw-mipi-csi.h"
  11. static struct R_CSI2 reg = {
  12. .VERSION = 0x00,
  13. .N_LANES = 0x04,
  14. .CTRL_RESETN = 0x08,
  15. .INTERRUPT = 0x0C,
  16. .DATA_IDS_1 = 0x10,
  17. .DATA_IDS_2 = 0x14,
  18. .IPI_MODE = 0x80,
  19. .IPI_VCID = 0x84,
  20. .IPI_DATA_TYPE = 0x88,
  21. .IPI_MEM_FLUSH = 0x8C,
  22. .IPI_HSA_TIME = 0x90,
  23. .IPI_HBP_TIME = 0x94,
  24. .IPI_HSD_TIME = 0x98,
  25. .IPI_HLINE_TIME = 0x9C,
  26. .IPI_SOFTRSTN = 0xA0,
  27. .IPI_ADV_FEATURES = 0xAC,
  28. .IPI_VSA_LINES = 0xB0,
  29. .IPI_VBP_LINES = 0xB4,
  30. .IPI_VFP_LINES = 0xB8,
  31. .IPI_VACTIVE_LINES = 0xBC,
  32. .INT_PHY_FATAL = 0xe0,
  33. .MASK_INT_PHY_FATAL = 0xe4,
  34. .FORCE_INT_PHY_FATAL = 0xe8,
  35. .INT_PKT_FATAL = 0xf0,
  36. .MASK_INT_PKT_FATAL = 0xf4,
  37. .FORCE_INT_PKT_FATAL = 0xf8,
  38. .INT_PHY = 0x110,
  39. .MASK_INT_PHY = 0x114,
  40. .FORCE_INT_PHY = 0x118,
  41. .INT_LINE = 0x130,
  42. .MASK_INT_LINE = 0x134,
  43. .FORCE_INT_LINE = 0x138,
  44. .INT_IPI = 0x140,
  45. .MASK_INT_IPI = 0x144,
  46. .FORCE_INT_IPI = 0x148,
  47. };
  48. struct interrupt_type csi_int = {
  49. .PHY_FATAL = BIT(0),
  50. .PKT_FATAL = BIT(1),
  51. .PHY = BIT(16),
  52. };
  53. #define dw_print(VAR) \
  54. dev_info(csi_dev->dev, "%s: 0x%x: %X\n", "##VAR##",\
  55. VAR, dw_mipi_csi_read(csi_dev, VAR))
  56. void dw_mipi_csi_write_part(struct dw_csi *dev, u32 address, u32 data,
  57. u8 shift, u8 width)
  58. {
  59. u32 mask = (1 << width) - 1;
  60. u32 temp = dw_mipi_csi_read(dev, address);
  61. temp &= ~(mask << shift);
  62. temp |= (data & mask) << shift;
  63. dw_mipi_csi_write(dev, address, temp);
  64. }
  65. void dw_mipi_csi_reset(struct dw_csi *csi_dev)
  66. {
  67. dw_mipi_csi_write(csi_dev, reg.CTRL_RESETN, 0);
  68. usleep_range(100, 200);
  69. dw_mipi_csi_write(csi_dev, reg.CTRL_RESETN, 1);
  70. }
  71. int dw_mipi_csi_mask_irq_power_off(struct dw_csi *csi_dev)
  72. {
  73. if (csi_dev->hw_version_major == 1) {
  74. /* set only one lane (lane 0) as active (ON) */
  75. dw_mipi_csi_write(csi_dev, reg.N_LANES, 0);
  76. dw_mipi_csi_write(csi_dev, reg.MASK_INT_PHY_FATAL, 0);
  77. dw_mipi_csi_write(csi_dev, reg.MASK_INT_PKT_FATAL, 0);
  78. dw_mipi_csi_write(csi_dev, reg.MASK_INT_PHY, 0);
  79. dw_mipi_csi_write(csi_dev, reg.MASK_INT_LINE, 0);
  80. dw_mipi_csi_write(csi_dev, reg.MASK_INT_IPI, 0);
  81. /* only for version 1.30 */
  82. if (csi_dev->hw_version_minor == 30)
  83. dw_mipi_csi_write(csi_dev,
  84. reg.MASK_INT_FRAME_FATAL, 0);
  85. dw_mipi_csi_write(csi_dev, reg.CTRL_RESETN, 0);
  86. /* only for version 1.40 */
  87. if (csi_dev->hw_version_minor == 40) {
  88. dw_mipi_csi_write(csi_dev,
  89. reg.MSK_BNDRY_FRAME_FATAL, 0);
  90. dw_mipi_csi_write(csi_dev,
  91. reg.MSK_SEQ_FRAME_FATAL, 0);
  92. dw_mipi_csi_write(csi_dev,
  93. reg.MSK_CRC_FRAME_FATAL, 0);
  94. dw_mipi_csi_write(csi_dev, reg.MSK_PLD_CRC_FATAL, 0);
  95. dw_mipi_csi_write(csi_dev, reg.MSK_DATA_ID, 0);
  96. dw_mipi_csi_write(csi_dev, reg.MSK_ECC_CORRECT, 0);
  97. }
  98. }
  99. return 0;
  100. }
  101. int dw_mipi_csi_hw_stdby(struct dw_csi *csi_dev)
  102. {
  103. if (csi_dev->hw_version_major == 1) {
  104. /* set only one lane (lane 0) as active (ON) */
  105. dw_mipi_csi_reset(csi_dev);
  106. dw_mipi_csi_write(csi_dev, reg.N_LANES, 0);
  107. phy_init(csi_dev->phy);
  108. /* only for version 1.30 */
  109. if (csi_dev->hw_version_minor == 30)
  110. dw_mipi_csi_write(csi_dev,
  111. reg.MASK_INT_FRAME_FATAL,
  112. GENMASK(31, 0));
  113. /* common */
  114. dw_mipi_csi_write(csi_dev, reg.MASK_INT_PHY_FATAL,
  115. GENMASK(8, 0));
  116. dw_mipi_csi_write(csi_dev, reg.MASK_INT_PKT_FATAL,
  117. GENMASK(1, 0));
  118. dw_mipi_csi_write(csi_dev, reg.MASK_INT_PHY, GENMASK(23, 0));
  119. dw_mipi_csi_write(csi_dev, reg.MASK_INT_LINE, GENMASK(23, 0));
  120. dw_mipi_csi_write(csi_dev, reg.MASK_INT_IPI, GENMASK(5, 0));
  121. /* only for version 1.40 */
  122. if (csi_dev->hw_version_minor == 40) {
  123. dw_mipi_csi_write(csi_dev,
  124. reg.MSK_BNDRY_FRAME_FATAL,
  125. GENMASK(31, 0));
  126. dw_mipi_csi_write(csi_dev,
  127. reg.MSK_SEQ_FRAME_FATAL,
  128. GENMASK(31, 0));
  129. dw_mipi_csi_write(csi_dev,
  130. reg.MSK_CRC_FRAME_FATAL,
  131. GENMASK(31, 0));
  132. dw_mipi_csi_write(csi_dev,
  133. reg.MSK_PLD_CRC_FATAL,
  134. GENMASK(31, 0));
  135. dw_mipi_csi_write(csi_dev,
  136. reg.MSK_DATA_ID, GENMASK(31, 0));
  137. dw_mipi_csi_write(csi_dev,
  138. reg.MSK_ECC_CORRECT, GENMASK(31, 0));
  139. }
  140. }
  141. return 0;
  142. }
  143. void dw_mipi_csi_set_ipi_fmt(struct dw_csi *csi_dev)
  144. {
  145. struct device *dev = csi_dev->dev;
  146. if (csi_dev->ipi_dt) {
  147. dw_mipi_csi_write(csi_dev, reg.IPI_DATA_TYPE, csi_dev->ipi_dt);
  148. /*switch (csi_dev->ipi_dt) {
  149. case CSI_2_YUV420_8:
  150. //case CSI_2_YUV420_8_LEG:
  151. case CSI_2_YUV420_8_SHIFT:
  152. break;
  153. case CSI_2_YUV420_10:
  154. case CSI_2_YUV420_10_SHIFT:
  155. break;
  156. }*/
  157. } else {
  158. switch (csi_dev->fmt->mbus_code) {
  159. case MEDIA_BUS_FMT_RGB666_1X18:
  160. csi_dev->ipi_dt = CSI_2_RGB666;
  161. break;
  162. case MEDIA_BUS_FMT_RGB565_2X8_BE:
  163. case MEDIA_BUS_FMT_RGB565_2X8_LE:
  164. csi_dev->ipi_dt = CSI_2_RGB565;
  165. break;
  166. case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE:
  167. case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
  168. csi_dev->ipi_dt = CSI_2_RGB555;
  169. break;
  170. case MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE:
  171. case MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE:
  172. csi_dev->ipi_dt = CSI_2_RGB444;
  173. break;
  174. break;
  175. case MEDIA_BUS_FMT_RGB888_2X12_LE:
  176. case MEDIA_BUS_FMT_RGB888_2X12_BE:
  177. csi_dev->ipi_dt = CSI_2_RGB888;
  178. break;
  179. case MEDIA_BUS_FMT_SBGGR10_1X10:
  180. case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE:
  181. csi_dev->ipi_dt = CSI_2_RAW10;
  182. break;
  183. case MEDIA_BUS_FMT_SBGGR12_1X12:
  184. csi_dev->ipi_dt = CSI_2_RAW12;
  185. break;
  186. case MEDIA_BUS_FMT_SBGGR14_1X14:
  187. csi_dev->ipi_dt = CSI_2_RAW14;
  188. break;
  189. case MEDIA_BUS_FMT_SBGGR16_1X16:
  190. csi_dev->ipi_dt = CSI_2_RAW16;
  191. break;
  192. case MEDIA_BUS_FMT_SBGGR8_1X8:
  193. csi_dev->ipi_dt = CSI_2_RAW8;
  194. break;
  195. case MEDIA_BUS_FMT_YVYU8_1X16:
  196. csi_dev->ipi_dt = CSI_2_YUV422_8;
  197. break;
  198. case MEDIA_BUS_FMT_VYUY8_1X16:
  199. csi_dev->ipi_dt = CSI_2_YUV422_8;
  200. break;
  201. case MEDIA_BUS_FMT_UYVY10_1X20:
  202. csi_dev->ipi_dt = CSI_2_YUV422_10;
  203. break;
  204. case MEDIA_BUS_FMT_YUYV8_1X16:
  205. csi_dev->ipi_dt = CSI_2_YUV420_8_LEG;
  206. break;
  207. case MEDIA_BUS_FMT_UYVY8_1X16:
  208. csi_dev->ipi_dt = CSI_2_YUV420_8;
  209. break;
  210. case MEDIA_BUS_FMT_VUY8_1X24:
  211. csi_dev->ipi_dt = CSI_2_YUV420_10;
  212. break;
  213. case MEDIA_BUS_FMT_Y8_1X8:
  214. csi_dev->ipi_dt = CSI_2_RAW8;
  215. break;
  216. case MEDIA_BUS_FMT_Y10_1X10:
  217. csi_dev->ipi_dt = CSI_2_RAW8;
  218. break;
  219. case MEDIA_BUS_FMT_SBGGR6_1X8:
  220. csi_dev->ipi_dt = CSI_2_RAW6;
  221. break;
  222. case MEDIA_BUS_FMT_SBGGR7_1X8:
  223. csi_dev->ipi_dt = CSI_2_RAW7;
  224. break;
  225. default:
  226. break;
  227. }
  228. dw_mipi_csi_write(csi_dev, reg.IPI_DATA_TYPE, csi_dev->ipi_dt);
  229. }
  230. dev_info(dev, "Selected IPI Data Type 0x%X\n", csi_dev->ipi_dt);
  231. }
  232. void dw_mipi_csi_fill_timings(struct dw_csi *dev, uint32_t width, uint32_t height)
  233. {
  234. dev->hw.virtual_ch = 0;
  235. dev->hw.ipi_color_mode = COLOR48;
  236. dev->hw.ipi_auto_flush = 1;
  237. dev->hw.ipi_mode = CAMERA_TIMING;
  238. dev->hw.ipi_cut_through = CTINACTIVE;
  239. dev->hw.ipi_adv_features = LINE_EVENT_SELECTION(EVSELAUTO);
  240. dev->hw.htotal = width + dev->hw.hsa +
  241. dev->hw.hbp + dev->hw.hsd;
  242. dev->hw.vactive = height;
  243. dev->hw.output = 2;
  244. dev_dbg(dev->dev, "*********** timings *********\n");
  245. dev_dbg(dev->dev, "Horizontal Sync Active: %d\n", dev->hw.hsa);
  246. dev_dbg(dev->dev, "Horizontal Back Porch: %d\n", dev->hw.hbp);
  247. dev_dbg(dev->dev, "Horizontal Width: %d\n", width);
  248. dev_dbg(dev->dev, "Horizontal Total: %d\n", dev->hw.htotal);
  249. dev_dbg(dev->dev, "Vertical Sync Active: %d\n", dev->hw.vsa);
  250. dev_dbg(dev->dev, "Vertical Back Porch: %d\n", dev->hw.vbp);
  251. dev_dbg(dev->dev, "Vertical Front Porch: %d\n", dev->hw.vfp);
  252. dev_dbg(dev->dev, "Vertical Active: %d\n", dev->hw.vactive);
  253. }
  254. void dw_mipi_csi_start(struct dw_csi *csi_dev)
  255. {
  256. struct device *dev = csi_dev->dev;
  257. dw_mipi_csi_write(csi_dev, reg.N_LANES, (csi_dev->hw.num_lanes - 1));
  258. dev_info(dev, "number of lanes: %d\n", csi_dev->hw.num_lanes);
  259. /* IPI Related Configuration */
  260. if (csi_dev->hw.output == IPI_OUT || csi_dev->hw.output == BOTH_OUT) {
  261. if (csi_dev->hw_version_major >= 1) {
  262. if (csi_dev->hw_version_minor >= 20)
  263. dw_mipi_csi_write(csi_dev,
  264. reg.IPI_ADV_FEATURES,
  265. csi_dev->hw.ipi_adv_features);
  266. if (csi_dev->hw_version_minor >= 30)
  267. dw_mipi_csi_write(csi_dev,
  268. reg.IPI_SOFTRSTN, 0x1);
  269. }
  270. /* address | data, | shift | width */
  271. dw_mipi_csi_write_part(csi_dev, reg.IPI_MODE, 1, 24, 1);
  272. dw_mipi_csi_write_part(csi_dev,
  273. reg.IPI_MODE,
  274. csi_dev->hw.ipi_mode,
  275. 0, 1);
  276. if (csi_dev->hw.ipi_mode == CAMERA_TIMING) {
  277. dw_mipi_csi_write(csi_dev,
  278. reg.IPI_ADV_FEATURES,
  279. LINE_EVENT_SELECTION(EVSELPROG) |
  280. EN_VIDEO |
  281. EN_LINE_START |
  282. EN_NULL |
  283. EN_BLANKING |
  284. EN_EMBEDDED);
  285. }
  286. dw_mipi_csi_write_part(csi_dev,
  287. reg.IPI_MODE,
  288. csi_dev->hw.ipi_color_mode,
  289. 8, 1);
  290. dw_mipi_csi_write_part(csi_dev,
  291. reg.IPI_MODE,
  292. csi_dev->hw.ipi_cut_through,
  293. 16, 1);
  294. dw_mipi_csi_write_part(csi_dev,
  295. reg.IPI_VCID,
  296. csi_dev->hw.virtual_ch,
  297. 0, 2);
  298. dw_mipi_csi_write_part(csi_dev,
  299. reg.IPI_MEM_FLUSH,
  300. csi_dev->hw.ipi_auto_flush,
  301. 8, 1);
  302. dev_vdbg(dev, "*********** config *********\n");
  303. dev_vdbg(dev, "IPI enable: %s\n",
  304. csi_dev->hw.output ? "YES" : "NO");
  305. dev_vdbg(dev, "video mode transmission type: %s timming\n",
  306. csi_dev->hw.ipi_mode ? "controller" : "camera");
  307. dev_vdbg(dev, "Color Mode: %s\n",
  308. csi_dev->hw.ipi_color_mode ? "16 bits" : "48 bits");
  309. dev_vdbg(dev, "Cut Through Mode: %s\n",
  310. csi_dev->hw.ipi_cut_through ? "enable" : "disable");
  311. dev_vdbg(dev, "Virtual Channel: %d\n",
  312. csi_dev->hw.virtual_ch);
  313. dev_vdbg(dev, "Auto-flush: %d\n",
  314. csi_dev->hw.ipi_auto_flush);
  315. dw_mipi_csi_write(csi_dev, reg.IPI_SOFTRSTN, 1);
  316. if (csi_dev->hw.ipi_mode == AUTO_TIMING)
  317. phy_power_on(csi_dev->phy);
  318. dw_mipi_csi_write(csi_dev,
  319. reg.IPI_HSA_TIME, csi_dev->hw.hsa);
  320. dw_mipi_csi_write(csi_dev,
  321. reg.IPI_HBP_TIME, csi_dev->hw.hbp);
  322. dw_mipi_csi_write(csi_dev,
  323. reg.IPI_HSD_TIME, csi_dev->hw.hsd);
  324. dw_mipi_csi_write(csi_dev,
  325. reg.IPI_HLINE_TIME, csi_dev->hw.htotal);
  326. dw_mipi_csi_write(csi_dev,
  327. reg.IPI_VSA_LINES, csi_dev->hw.vsa);
  328. dw_mipi_csi_write(csi_dev,
  329. reg.IPI_VBP_LINES, csi_dev->hw.vbp);
  330. dw_mipi_csi_write(csi_dev,
  331. reg.IPI_VFP_LINES, csi_dev->hw.vfp);
  332. dw_mipi_csi_write(csi_dev,
  333. reg.IPI_VACTIVE_LINES, csi_dev->hw.vactive);
  334. }
  335. phy_power_on(csi_dev->phy);
  336. }
  337. int dw_mipi_csi_irq_handler(struct dw_csi *csi_dev)
  338. {
  339. struct device *dev = csi_dev->dev;
  340. u32 global_int_status, i_sts;
  341. unsigned long flags;
  342. spin_lock_irqsave(&csi_dev->slock, flags);
  343. global_int_status = dw_mipi_csi_read(csi_dev, reg.INTERRUPT);
  344. if (global_int_status & csi_int.PHY_FATAL) {
  345. i_sts = dw_mipi_csi_read(csi_dev, reg.INT_PHY_FATAL);
  346. dev_err_ratelimited(dev, "int %08X: PHY FATAL: %08X\n",
  347. reg.INT_PHY_FATAL, i_sts);
  348. }
  349. if (global_int_status & csi_int.PKT_FATAL) {
  350. i_sts = dw_mipi_csi_read(csi_dev, reg.INT_PKT_FATAL);
  351. dev_err_ratelimited(dev, "int %08X: PKT FATAL: %08X\n",
  352. reg.INT_PKT_FATAL, i_sts);
  353. }
  354. if (global_int_status & csi_int.FRAME_FATAL &&
  355. csi_dev->hw_version_major == 1 &&
  356. csi_dev->hw_version_minor == 30) {
  357. i_sts = dw_mipi_csi_read(csi_dev, reg.INT_FRAME_FATAL);
  358. dev_err_ratelimited(dev, "int %08X: FRAME FATAL: %08X\n",
  359. reg.INT_FRAME_FATAL, i_sts);
  360. }
  361. if (global_int_status & csi_int.PHY) {
  362. i_sts = dw_mipi_csi_read(csi_dev, reg.INT_PHY);
  363. dev_err_ratelimited(dev, "int %08X: PHY: %08X\n",
  364. reg.INT_PHY, i_sts);
  365. }
  366. if (global_int_status & csi_int.PKT &&
  367. csi_dev->hw_version_major == 1 &&
  368. csi_dev->hw_version_minor <= 30) {
  369. i_sts = dw_mipi_csi_read(csi_dev, reg.INT_PKT);
  370. dev_err_ratelimited(dev, "int %08X: PKT: %08X\n",
  371. reg.INT_PKT, i_sts);
  372. }
  373. if (global_int_status & csi_int.LINE) {
  374. i_sts = dw_mipi_csi_read(csi_dev, reg.INT_LINE);
  375. dev_err_ratelimited(dev, "int %08X: LINE: %08X\n",
  376. reg.INT_LINE, i_sts);
  377. }
  378. if (global_int_status & csi_int.IPI) {
  379. i_sts = dw_mipi_csi_read(csi_dev, reg.INT_IPI);
  380. dev_err_ratelimited(dev, "int %08X: IPI: %08X\n",
  381. reg.INT_IPI, i_sts);
  382. }
  383. if (global_int_status & csi_int.BNDRY_FRAME_FATAL) {
  384. i_sts = dw_mipi_csi_read(csi_dev, reg.ST_BNDRY_FRAME_FATAL);
  385. dev_err_ratelimited(dev,
  386. "int %08X: ST_BNDRY_FRAME_FATAL: %08X\n",
  387. reg.ST_BNDRY_FRAME_FATAL, i_sts);
  388. }
  389. if (global_int_status & csi_int.SEQ_FRAME_FATAL) {
  390. i_sts = dw_mipi_csi_read(csi_dev, reg.ST_SEQ_FRAME_FATAL);
  391. dev_err_ratelimited(dev,
  392. "int %08X: ST_SEQ_FRAME_FATAL: %08X\n",
  393. reg.ST_SEQ_FRAME_FATAL, i_sts);
  394. }
  395. if (global_int_status & csi_int.CRC_FRAME_FATAL) {
  396. i_sts = dw_mipi_csi_read(csi_dev, reg.ST_CRC_FRAME_FATAL);
  397. dev_err_ratelimited(dev,
  398. "int %08X: ST_CRC_FRAME_FATAL: %08X\n",
  399. reg.ST_CRC_FRAME_FATAL, i_sts);
  400. }
  401. if (global_int_status & csi_int.PLD_CRC_FATAL) {
  402. i_sts = dw_mipi_csi_read(csi_dev, reg.ST_PLD_CRC_FATAL);
  403. dev_err_ratelimited(dev,
  404. "int %08X: ST_PLD_CRC_FATAL: %08X\n",
  405. reg.ST_PLD_CRC_FATAL, i_sts);
  406. }
  407. if (global_int_status & csi_int.DATA_ID) {
  408. i_sts = dw_mipi_csi_read(csi_dev, reg.ST_DATA_ID);
  409. dev_err_ratelimited(dev, "int %08X: ST_DATA_ID: %08X\n",
  410. reg.ST_DATA_ID, i_sts);
  411. }
  412. if (global_int_status & csi_int.ECC_CORRECTED) {
  413. i_sts = dw_mipi_csi_read(csi_dev, reg.ST_ECC_CORRECT);
  414. dev_err_ratelimited(dev, "int %08X: ST_ECC_CORRECT: %08X\n",
  415. reg.ST_ECC_CORRECT, i_sts);
  416. }
  417. spin_unlock_irqrestore(&csi_dev->slock, flags);
  418. return 1;
  419. }
  420. void dw_mipi_csi_get_version(struct dw_csi *csi_dev)
  421. {
  422. u32 hw_version;
  423. hw_version = dw_mipi_csi_read(csi_dev, reg.VERSION);
  424. csi_dev->hw_version_major = (u8)((hw_version >> 24) - '0');
  425. csi_dev->hw_version_minor = (u8)((hw_version >> 16) - '0');
  426. csi_dev->hw_version_minor = csi_dev->hw_version_minor * 10;
  427. csi_dev->hw_version_minor += (u8)((hw_version >> 8) - '0');
  428. }
  429. int dw_mipi_csi_specific_mappings(struct dw_csi *csi_dev)
  430. {
  431. struct device *dev = csi_dev->dev;
  432. if (csi_dev->hw_version_major == 1) {
  433. if (csi_dev->hw_version_minor == 30) {
  434. /*
  435. * Hardware registers that were
  436. * exclusive to version < 1.40
  437. */
  438. reg.INT_FRAME_FATAL = 0x100;
  439. reg.MASK_INT_FRAME_FATAL = 0x104;
  440. reg.FORCE_INT_FRAME_FATAL = 0x108;
  441. reg.INT_PKT = 0x120;
  442. reg.MASK_INT_PKT = 0x124;
  443. reg.FORCE_INT_PKT = 0x128;
  444. /* interrupt source present until this release */
  445. csi_int.PKT = BIT(17);
  446. csi_int.LINE = BIT(18);
  447. csi_int.IPI = BIT(19);
  448. csi_int.FRAME_FATAL = BIT(2);
  449. } else if (csi_dev->hw_version_minor == 40) {
  450. /*
  451. * HW registers that were added
  452. * to version 1.40
  453. */
  454. reg.ST_BNDRY_FRAME_FATAL = 0x280;
  455. reg.MSK_BNDRY_FRAME_FATAL = 0x284;
  456. reg.FORCE_BNDRY_FRAME_FATAL = 0x288;
  457. reg.ST_SEQ_FRAME_FATAL = 0x290;
  458. reg.MSK_SEQ_FRAME_FATAL = 0x294;
  459. reg.FORCE_SEQ_FRAME_FATAL = 0x298;
  460. reg.ST_CRC_FRAME_FATAL = 0x2a0;
  461. reg.MSK_CRC_FRAME_FATAL = 0x2a4;
  462. reg.FORCE_CRC_FRAME_FATAL = 0x2a8;
  463. reg.ST_PLD_CRC_FATAL = 0x2b0;
  464. reg.MSK_PLD_CRC_FATAL = 0x2b4;
  465. reg.FORCE_PLD_CRC_FATAL = 0x2b8;
  466. reg.ST_DATA_ID = 0x2c0;
  467. reg.MSK_DATA_ID = 0x2c4;
  468. reg.FORCE_DATA_ID = 0x2c8;
  469. reg.ST_ECC_CORRECT = 0x2d0;
  470. reg.MSK_ECC_CORRECT = 0x2d4;
  471. reg.FORCE_ECC_CORRECT = 0x2d8;
  472. reg.DATA_IDS_VC_1 = 0x0;
  473. reg.DATA_IDS_VC_2 = 0x0;
  474. reg.VC_EXTENSION = 0x0;
  475. /* interrupts map were changed */
  476. csi_int.LINE = BIT(17);
  477. csi_int.IPI = BIT(18);
  478. csi_int.BNDRY_FRAME_FATAL = BIT(2);
  479. csi_int.SEQ_FRAME_FATAL = BIT(3);
  480. csi_int.CRC_FRAME_FATAL = BIT(4);
  481. csi_int.PLD_CRC_FATAL = BIT(5);
  482. csi_int.DATA_ID = BIT(6);
  483. csi_int.ECC_CORRECTED = BIT(7);
  484. } else {
  485. dev_info(dev, "Version minor not supported.");
  486. }
  487. } else {
  488. dev_info(dev, "Version major not supported.");
  489. }
  490. return 0;
  491. }
  492. void dw_mipi_csi_dump(struct dw_csi *csi_dev)
  493. {
  494. dw_print(reg.VERSION);
  495. dw_print(reg.N_LANES);
  496. dw_print(reg.CTRL_RESETN);
  497. dw_print(reg.INTERRUPT);
  498. dw_print(reg.DATA_IDS_1);
  499. dw_print(reg.DATA_IDS_2);
  500. dw_print(reg.IPI_MODE);
  501. dw_print(reg.IPI_VCID);
  502. dw_print(reg.IPI_DATA_TYPE);
  503. dw_print(reg.IPI_MEM_FLUSH);
  504. dw_print(reg.IPI_HSA_TIME);
  505. dw_print(reg.IPI_HBP_TIME);
  506. dw_print(reg.IPI_HSD_TIME);
  507. dw_print(reg.IPI_HLINE_TIME);
  508. dw_print(reg.IPI_SOFTRSTN);
  509. dw_print(reg.IPI_ADV_FEATURES);
  510. dw_print(reg.IPI_VSA_LINES);
  511. dw_print(reg.IPI_VBP_LINES);
  512. dw_print(reg.IPI_VFP_LINES);
  513. dw_print(reg.IPI_VACTIVE_LINES);
  514. dw_print(reg.IPI_DATA_TYPE);
  515. dw_print(reg.VERSION);
  516. dw_print(reg.IPI_ADV_FEATURES);
  517. }