dw-dphy-rx.h 5.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
  4. *
  5. * Synopsys DesignWare MIPI D-PHY controller driver
  6. *
  7. * Author: Luis Oliveira <luis.oliveira@synopsys.com>
  8. */
  9. #ifndef __PHY_SNPS_DPHY_RX_H__
  10. #define __PHY_SNPS_DPHY_RX_H__
  11. #include <linux/debugfs.h>
  12. #include <linux/delay.h>
  13. #include <linux/gpio.h>
  14. #include <linux/io.h>
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/of_address.h>
  19. #include <linux/of_gpio.h>
  20. #include <linux/phy/phy.h>
  21. #include <linux/phy/phy-mipi-dphy.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/spinlock.h>
  24. /* DPHY interface register bank*/
  25. #define R_CSI2_DPHY_SHUTDOWNZ 0x0
  26. #define R_CSI2_DPHY_RSTZ 0x4
  27. #define R_CSI2_DPHY_RX 0x8
  28. #define R_CSI2_DPHY_STOPSTATE 0xC
  29. #define R_CSI2_DPHY_TST_CTRL0 0x10
  30. #define R_CSI2_DPHY_TST_CTRL1 0x14
  31. #define R_CSI2_DPHY2_TST_CTRL0 0x18
  32. #define R_CSI2_DPHY2_TST_CTRL1 0x1C
  33. enum dphy_id_mask {
  34. DPHY_ID_LANE_SUPPORT = 0,
  35. DPHY_ID_IF = 4,
  36. DPHY_ID_GEN = 8,
  37. };
  38. enum dphy_gen_values {
  39. GEN1,
  40. GEN2,
  41. GEN3,
  42. };
  43. enum dphy_interface_length {
  44. BIT8 = 8,
  45. BIT12 = 12,
  46. };
  47. enum tst_ctrl0 {
  48. PHY_TESTCLR,
  49. PHY_TESTCLK,
  50. };
  51. enum tst_ctrl1 {
  52. PHY_TESTDIN = 0,
  53. PHY_TESTDOUT = 8,
  54. PHY_TESTEN = 16,
  55. };
  56. enum lanes_config_values {
  57. CTRL_4_LANES,
  58. CTRL_8_LANES,
  59. };
  60. enum dphy_tc {
  61. CFGCLKFREQRANGE_TX = 0x02,
  62. CFGCLKFREQRANGE_RX = 0x05,
  63. BYPASS = 0x20,
  64. IO_DS = 0x30,
  65. };
  66. enum dphy_8bit_interface_addr {
  67. BANDGAP_CTRL = 0x24,
  68. HS_RX_CTRL_LANE0 = 0x42,
  69. HSFREQRANGE_8BIT = 0x44,
  70. OSC_FREQ_TARGET_RX0_LSB = 0x4e,
  71. OSC_FREQ_TARGET_RX0_MSB = 0x4f,
  72. HS_RX_CTRL_LANE1 = 0x52,
  73. OSC_FREQ_TARGET_RX1_LSB = 0x5e,
  74. OSC_FREQ_TARGET_RX1_MSB = 0x5f,
  75. RX_SKEW_CAL = 0x7e,
  76. HS_RX_CTRL_LANE2 = 0x82,
  77. OSC_FREQ_TARGET_RX2_LSB = 0x8e,
  78. OSC_FREQ_TARGET_RX2_MSB = 0x8f,
  79. HS_RX_CTRL_LANE3 = 0x92,
  80. OSC_FREQ_TARGET_RX3_LSB = 0x9e,
  81. OSC_FREQ_TARGET_RX3_MSB = 0x9f,
  82. };
  83. enum dphy_12bit_interface_addr {
  84. RX_SYS_0 = 0x01,
  85. RX_SYS_1 = 0x02,
  86. RX_SYS_7 = 0x08,
  87. RX_RX_STARTUP_OVR_0 = 0xe0,
  88. RX_RX_STARTUP_OVR_1 = 0xe1,
  89. RX_RX_STARTUP_OVR_2 = 0xe2,
  90. RX_RX_STARTUP_OVR_3 = 0xe3,
  91. RX_RX_STARTUP_OVR_4 = 0xe4,
  92. RX_RX_STARTUP_OVR_17 = 0xf1,
  93. };
  94. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  95. /* Testchip interface register bank */
  96. #define IDLYCFG 0x00
  97. #define IDLYSEL 0x04
  98. #define IDLYCNTINVAL 0x08
  99. #define IDLYCNTOUTVAL 0x0c
  100. #define DPHY1REGRSTN 0x10
  101. #define DPHYZCALSTAT 0x14
  102. #define DPHYZCALCTRL 0x18
  103. #define DPHYLANE0STAT 0x1c
  104. #define DPHYLANE1STAT 0x20
  105. #define DPHYLANE2STAT 0x24
  106. #define DPHYLANE3STAT 0x28
  107. #define DPHYCLKSTAT 0x2c
  108. #define DPHYZCLKCTRL 0x30
  109. #define TCGENPURPOSOUT 0x34
  110. #define TCGENPURPOSIN 0x38
  111. #define DPHYGENERICOUT 0x3c
  112. #define DPHYGENERICIN 0x40
  113. #define DPHYGLUEIFTESTER 0x180
  114. #define DPHYID 0x100
  115. #define DPHY_DEFAULT_FREQ 300000
  116. enum glueiftester {
  117. RESET = 0,
  118. TX_PHY = 0x100 | (0x1 << 4),
  119. RX_PHY = 0x100 | (0x2 << 4),
  120. GLUELOGIC = 0x100 | (0x4 << 4),
  121. };
  122. #endif
  123. /**
  124. * struct phy specifies associated phy component
  125. * struct cfg to pass mipi dphy specific configurations
  126. * @lanes_config lanes configuration
  127. * @dphy_freq operating frequency of the d-phy (mbps)
  128. * @phy_type dphy can be of two types, passed here
  129. * @dphy_gen dphy can be of three generations, passed here
  130. * @dphy_te_len bus width
  131. * @max_lanes maximum number of lanes
  132. * @lp_time time in low-power
  133. * @base_address memmory address of dphy test interface
  134. * @dphy1_if_addr gluelogic dphy 1 memmory address of interface
  135. * @dphy2_if_addr gluelogic dphy 2 memmory address of interface
  136. * @config_8l eight lanes configuration
  137. */
  138. struct dw_dphy_rx {
  139. struct phy *phy;
  140. struct phy_configure_opts_mipi_dphy *cfg;
  141. u32 lanes_config;
  142. u32 dphy_freq; //MBPS
  143. u32 phy_type;
  144. u32 dphy_gen;
  145. u32 dphy_te_len;
  146. u32 max_lanes;
  147. u32 lp_time;
  148. void __iomem *base_address;
  149. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  150. void __iomem *dphy1_if_addr;
  151. void __iomem *dphy2_if_addr;
  152. u8 config_8l;
  153. u8 (*get_config_8l)(struct device *dev, struct dw_dphy_rx *dphy);
  154. #endif
  155. u8 (*phy_register)(struct device *dev);
  156. void (*phy_unregister)(struct device *dev);
  157. };
  158. int dw_dphy_init(struct phy *phy);
  159. int dw_dphy_reset(struct phy *phy);
  160. int dw_dphy_power_off(struct phy *phy);
  161. int dw_dphy_power_on(struct phy *phy);
  162. u8 dw_dphy_setup_config(struct dw_dphy_rx *dphy);
  163. void dw_dphy_write(struct dw_dphy_rx *dphy, u32 address, u32 data);
  164. u32 dw_dphy_read(struct dw_dphy_rx *dphy, u32 address);
  165. int dw_dphy_te_read(struct dw_dphy_rx *dphy, u32 addr);
  166. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  167. u32 dw_dphy_if_read(struct dw_dphy_rx *dphy, u32 address);
  168. int dw_dphy_if_get_idelay(struct dw_dphy_rx *dphy);
  169. int dw_dphy_if_set_idelay_lane(struct dw_dphy_rx *dphy, u8 dly, u8 lane);
  170. int dw_dphy_create_capabilities_sysfs(struct platform_device *pdev);
  171. int dw_dphy_remove_capabilities_sysfs(struct platform_device *pdev);
  172. static inline
  173. u32 dw_dphy_if_read_msk(struct dw_dphy_rx *dphy,
  174. u32 address, u8 shift, u8 width)
  175. {
  176. return (dw_dphy_if_read(dphy, address) >> shift) & ((1 << width) - 1);
  177. }
  178. #endif /*IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)*/
  179. static inline struct phy *dw_dphy_xlate(struct device *dev,
  180. struct of_phandle_args *args)
  181. {
  182. struct dw_dphy_rx *dphy = dev_get_drvdata(dev);
  183. return dphy->phy;
  184. }
  185. static inline
  186. u32 dw_dphy_read_msk(struct dw_dphy_rx *dev, u32 address, u8 shift, u8 width)
  187. {
  188. return (dw_dphy_read(dev, address) >> shift) & ((1 << width) - 1);
  189. }
  190. #endif /*__PHY_SNPS_DPHY_RX_H__*/