dw-dphy-rx.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
  4. *
  5. * Synopsys DesignWare MIPI D-PHY controller driver
  6. * Core functions
  7. *
  8. * Author: Luis Oliveira <luis.oliveira@synopsys.com>
  9. */
  10. #include "dw-dphy-rx.h"
  11. #include "bm_csi_dphy.h"
  12. #include "bm_printk.h"
  13. struct range_dphy_gen2 {
  14. u32 freq;
  15. u8 hsfregrange;
  16. };
  17. struct range_dphy_gen2 range_gen2[] = {
  18. { 80, 0x00 }, { 90, 0x10 }, { 100, 0x20 }, { 110, 0x30 },
  19. { 120, 0x01 }, { 130, 0x11 }, { 140, 0x21 }, { 150, 0x31 },
  20. { 160, 0x02 }, { 170, 0x12 }, { 180, 0x22 }, { 190, 0x32 },
  21. { 205, 0x03 }, { 220, 0x13 }, { 235, 0x23 }, { 250, 0x33 },
  22. { 275, 0x04 }, { 300, 0x14 }, { 325, 0x05 }, { 350, 0x15 },
  23. { 400, 0x25 }, { 450, 0x06 }, { 500, 0x16 }, { 550, 0x07 },
  24. { 600, 0x17 }, { 650, 0x08 }, { 700, 0x18 }, { 750, 0x09 },
  25. { 800, 0x19 }, { 850, 0x29 }, { 900, 0x39 }, { 950, 0x0A },
  26. { 1000, 0x1A }, { 1050, 0x2A }, { 1100, 0x3A }, { 1150, 0x0B },
  27. { 1200, 0x1B }, { 1250, 0x2B }, { 1300, 0x3B }, { 1350, 0x0C },
  28. { 1400, 0x1C }, { 1450, 0x2C }, { 1500, 0x3C }, { 1550, 0x0D },
  29. { 1600, 0x1D }, { 1650, 0x2D }, { 1700, 0x0E }, { 1750, 0x1E },
  30. { 1800, 0x2E }, { 1850, 0x3E }, { 1900, 0x0F }, { 1950, 0x1F },
  31. { 2000, 0x2F },
  32. };
  33. struct range_dphy_gen3 {
  34. u32 freq;
  35. u8 hsfregrange;
  36. u32 osc_freq_target;
  37. };
  38. struct range_dphy_gen3 range_gen3[] = {
  39. { 80, 0x00, 0x1B6 }, { 90, 0x10, 0x1B6 }, { 100, 0x20, 0x1B6 },
  40. { 110, 0x30, 0x1B6 }, { 120, 0x01, 0x1B6 }, { 130, 0x11, 0x1B6 },
  41. { 140, 0x21, 0x1B6 }, { 150, 0x31, 0x1B6 }, { 160, 0x02, 0x1B6 },
  42. { 170, 0x12, 0x1B6 }, { 180, 0x22, 0x1B6 }, { 190, 0x32, 0x1B6 },
  43. { 205, 0x03, 0x1B6 }, { 220, 0x13, 0x1B6 }, { 235, 0x23, 0x1B6 },
  44. { 250, 0x33, 0x1B6 }, { 275, 0x04, 0x1B6 }, { 300, 0x14, 0x1B6 },
  45. { 325, 0x25, 0x1B6 }, { 350, 0x35, 0x1B6 }, { 400, 0x05, 0x1B6 },
  46. { 450, 0x16, 0x1B6 }, { 500, 0x26, 0x1B6 }, { 550, 0x37, 0x1B6 },
  47. { 600, 0x07, 0x1B6 }, { 650, 0x18, 0x1B6 }, { 700, 0x28, 0x1B6 },
  48. { 750, 0x39, 0x1B6 }, { 800, 0x09, 0x1B6 }, { 850, 0x19, 0x1B6 },
  49. { 900, 0x29, 0x1B6 }, { 950, 0x3A, 0x1B6 }, { 1000, 0x0A, 0x1B6 },
  50. { 1050, 0x1A, 0x1B6 }, { 1100, 0x2A, 0x1B6 }, { 1150, 0x3B, 0x1B6 },
  51. { 1200, 0x0B, 0x1B6 }, { 1250, 0x1B, 0x1B6 }, { 1300, 0x2B, 0x1B6 },
  52. { 1350, 0x3C, 0x1B6 }, { 1400, 0x0C, 0x1B6 }, { 1450, 0x1C, 0x1B6 },
  53. { 1500, 0x2C, 0x1B6 }, { 1550, 0x3D, 0x10F }, { 1600, 0x0D, 0x118 },
  54. { 1650, 0x1D, 0x121 }, { 1700, 0x2E, 0x12A }, { 1750, 0x3E, 0x132 },
  55. { 1800, 0x0E, 0x13B }, { 1850, 0x1E, 0x144 }, { 1900, 0x2F, 0x14D },
  56. { 1950, 0x3F, 0x155 }, { 2000, 0x0F, 0x15E }, { 2050, 0x40, 0x167 },
  57. { 2100, 0x41, 0x170 }, { 2150, 0x42, 0x178 }, { 2200, 0x43, 0x181 },
  58. { 2250, 0x44, 0x18A }, { 2300, 0x45, 0x193 }, { 2350, 0x46, 0x19B },
  59. { 2400, 0x47, 0x1A4 }, { 2450, 0x48, 0x1AD }, { 2500, 0x49, 0x1B6 }
  60. };
  61. u8 dw_dphy_setup_config(struct dw_dphy_rx *dphy)
  62. {
  63. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  64. #if 0
  65. int ret;
  66. if (dphy->max_lanes == CTRL_4_LANES) {
  67. dev_vdbg(&dphy->phy->dev, "CONFIG 4L\n");
  68. return CTRL_4_LANES;
  69. }
  70. if (IS_ENABLED(CONFIG_OF)) {
  71. ret = gpio_request(dphy->config_8l, "config");
  72. if (ret < 0) {
  73. dev_vdbg(&dphy->phy->dev,
  74. "could not acquire config (err=%d)\n", ret);
  75. return ret;
  76. }
  77. ret = gpio_get_value(dphy->config_8l);
  78. gpio_free(dphy->config_8l);
  79. } else {
  80. ret = dphy->config_8l;
  81. }
  82. dev_vdbg(&dphy->phy->dev,
  83. "Booting in [%s] mode\n",
  84. ret == CTRL_8_LANES ? "8L" : "4+4L");
  85. return ret;
  86. #endif
  87. #endif /* CONFIG_DWC_MIPI_TC_DPHY_GEN3 */
  88. return CTRL_4_LANES;
  89. }
  90. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  91. //extern int k_bm_visys_write_reg(uint32_t offset, uint32_t value);
  92. //extern int k_bm_visys_read_reg(uint32_t offset, uint32_t *value);
  93. void dw_dphy_if_write(struct dw_dphy_rx *dphy, u32 address, u32 data)
  94. {
  95. writel(data, dphy->dphy1_if_addr + address);
  96. //k_bm_visys_write_reg(address, data);
  97. }
  98. u32 dw_dphy_if_read(struct dw_dphy_rx *dphy, u32 address)
  99. {
  100. u32 if1 = 0;
  101. if1 = readl(dphy->dphy1_if_addr + address);
  102. //k_bm_visys_read_reg(address, &if1);
  103. return if1;
  104. }
  105. #endif
  106. void dw_dphy_write(struct dw_dphy_rx *dphy, u32 address, u32 data)
  107. {
  108. iowrite32(data, dphy->base_address + address);
  109. if (dphy->lanes_config == CTRL_4_LANES)
  110. return;
  111. return;
  112. if (address == R_CSI2_DPHY_TST_CTRL0)
  113. iowrite32(data, dphy->base_address + R_CSI2_DPHY2_TST_CTRL0);
  114. else if (address == R_CSI2_DPHY_TST_CTRL1)
  115. iowrite32(data, dphy->base_address + R_CSI2_DPHY2_TST_CTRL1);
  116. }
  117. u32 dw_dphy_read(struct dw_dphy_rx *dphy, u32 address)
  118. {
  119. int dphy1 = 0, dphy2 = 0;
  120. dphy1 = ioread32(dphy->base_address + address);
  121. if (dphy->lanes_config == CTRL_4_LANES)
  122. goto end;
  123. goto end;
  124. if (address == R_CSI2_DPHY_TST_CTRL0)
  125. dphy2 = ioread32(dphy->base_address + R_CSI2_DPHY2_TST_CTRL0);
  126. else if (address == R_CSI2_DPHY_TST_CTRL1)
  127. dphy2 = ioread32(dphy->base_address + R_CSI2_DPHY2_TST_CTRL1);
  128. else
  129. return -ENODEV;
  130. end:
  131. return dphy1;
  132. }
  133. void dw_dphy_write_msk(struct dw_dphy_rx *dev, u32 address, u32 data, u8 shift,
  134. u8 width)
  135. {
  136. u32 temp = dw_dphy_read(dev, address);
  137. u32 mask = (1 << width) - 1;
  138. temp &= ~(mask << shift);
  139. temp |= (data & mask) << shift;
  140. dw_dphy_write(dev, address, temp);
  141. }
  142. static void dw_dphy_te_12b_write(struct dw_dphy_rx *dphy, u16 addr, u8 data)
  143. {
  144. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1);
  145. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  146. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1);
  147. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  148. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0x00, PHY_TESTDIN, 8);
  149. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  150. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1);
  151. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)(addr >> 8),
  152. PHY_TESTDIN, 8);
  153. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  154. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  155. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1);
  156. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  157. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)addr, PHY_TESTDIN,
  158. 8);
  159. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  160. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1);
  161. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)data, PHY_TESTDIN,
  162. 8);
  163. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  164. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  165. }
  166. static void dw_dphy_te_8b_write(struct dw_dphy_rx *dphy, u8 addr, u8 data)
  167. {
  168. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  169. dw_dphy_write(dphy, R_CSI2_DPHY_TST_CTRL1, addr);
  170. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1);
  171. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  172. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1);
  173. dw_dphy_write(dphy, R_CSI2_DPHY_TST_CTRL1, data);
  174. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  175. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  176. }
  177. static void dw_dphy_te_write(struct dw_dphy_rx *dphy, u16 addr, u8 data)
  178. {
  179. dphy->dphy_te_len = BIT12;
  180. if (dphy->dphy_te_len == BIT12)
  181. dw_dphy_te_12b_write(dphy, addr, data);
  182. else
  183. dw_dphy_te_8b_write(dphy, addr, data);
  184. }
  185. static int dw_dphy_te_12b_read(struct dw_dphy_rx *dphy, u32 addr)
  186. {
  187. u8 ret;
  188. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 1);
  189. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1);
  190. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  191. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1);
  192. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1);
  193. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  194. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0x00, PHY_TESTDIN, 8);
  195. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  196. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1);
  197. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)(addr >> 8),
  198. PHY_TESTDIN, 8);
  199. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  200. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  201. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1);
  202. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  203. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, (u8)addr, PHY_TESTDIN,
  204. 8);
  205. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  206. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0x00, 0, PHY_TESTDIN);
  207. ret = dw_dphy_read_msk(dphy, R_CSI2_DPHY_TST_CTRL1, PHY_TESTDOUT, 8);
  208. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1);
  209. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1);
  210. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 1);
  211. return ret;
  212. }
  213. static int dw_dphy_te_8b_read(struct dw_dphy_rx *dphy, u32 addr)
  214. {
  215. u8 ret;
  216. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 0);
  217. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0);
  218. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 1, PHY_TESTEN, 1);
  219. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  220. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, addr, PHY_TESTDIN, 8);
  221. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  222. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTEN, 1);
  223. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL1, 0, PHY_TESTDIN, 8);
  224. ret = dw_dphy_read_msk(dphy, R_CSI2_DPHY_TST_CTRL1, PHY_TESTDOUT, 8);
  225. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1);
  226. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 1);
  227. return ret;
  228. }
  229. int dw_dphy_te_read(struct dw_dphy_rx *dphy, u32 addr)
  230. {
  231. int ret;
  232. if (dphy->dphy_te_len == BIT12)
  233. ret = dw_dphy_te_12b_read(dphy, addr);
  234. else
  235. ret = dw_dphy_te_12b_read(dphy, addr);
  236. //ret = dw_dphy_te_8b_read(dphy, addr);
  237. return ret;
  238. }
  239. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  240. static void dw_dphy_if_init(struct dw_dphy_rx *dphy)
  241. {
  242. bm_info("enter %s\n", __func__);
  243. //dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET);
  244. //dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, TX_PHY);
  245. //dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLR, 1);
  246. //dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLR, 1);
  247. //dw_dphy_if_write(dphy, DPHYZCALCTRL, 0);
  248. //dw_dphy_if_write(dphy, DPHYZCALCTRL, 1);
  249. dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET);
  250. dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, GLUELOGIC);
  251. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLR, 1);
  252. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLR, 1);
  253. //dw_dphy_if_write(dphy, DPHYZCALCTRL, 0);
  254. //dw_dphy_if_write(dphy, DPHYZCALCTRL, 1);
  255. dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET);
  256. dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RX_PHY);
  257. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLR, 1);
  258. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLR, 1);
  259. //dw_dphy_if_write(dphy, DPHYZCALCTRL, 0);
  260. //dw_dphy_if_write(dphy, DPHYZCALCTRL, 1);
  261. }
  262. #endif
  263. static void dw_dphy_gen3_12bit_tc_power_up(struct dw_dphy_rx *dphy, uint8_t hsfregrange)
  264. {
  265. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  266. dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET);
  267. dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, GLUELOGIC);
  268. #endif
  269. dw_dphy_te_write(dphy, CFGCLKFREQRANGE_RX, 0x1C);
  270. dw_dphy_te_write(dphy, 0x6, hsfregrange);
  271. /* CLKSEL | UPDATEPLL | SHADOW_CLEAR | SHADOW_CTRL | FORCEPLL */
  272. //dw_dphy_te_write(dphy, BYPASS, 0x3F);
  273. /* IO_DS3 | IO_DS2 | IO_DS1 | IO_DS0 */
  274. if (dphy->dphy_freq > 1500)
  275. dw_dphy_te_write(dphy, IO_DS, 0x0F);
  276. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  277. dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET);
  278. dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RX_PHY | 0x2);
  279. #endif
  280. }
  281. static void dw_dphy_gen3_8bit_tc_power_up(struct dw_dphy_rx *dphy)
  282. {
  283. u32 input_freq = dphy->dphy_freq / 1000;
  284. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  285. dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET);
  286. dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, GLUELOGIC);
  287. dw_dphy_te_write(dphy, CFGCLKFREQRANGE_RX, 0x1C);
  288. dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RESET);
  289. dw_dphy_if_write(dphy, DPHYGLUEIFTESTER, RX_PHY);
  290. #endif
  291. dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX0_MSB, 0x03);
  292. dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX0_LSB, 0x02);
  293. dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX1_MSB, 0x03);
  294. dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX1_LSB, 0x02);
  295. dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX2_MSB, 0x03);
  296. dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX2_LSB, 0x02);
  297. dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX3_MSB, 0x03);
  298. dw_dphy_te_write(dphy, OSC_FREQ_TARGET_RX3_LSB, 0x02);
  299. dw_dphy_te_write(dphy, BANDGAP_CTRL, 0x80);
  300. if (input_freq < 2000)
  301. dw_dphy_te_write(dphy, HS_RX_CTRL_LANE0, 0xC0);
  302. if (input_freq < 1000) {
  303. dw_dphy_te_write(dphy, HS_RX_CTRL_LANE1, 0xC0);
  304. dw_dphy_te_write(dphy, HS_RX_CTRL_LANE2, 0xC0);
  305. dw_dphy_te_write(dphy, HS_RX_CTRL_LANE3, 0xC0);
  306. }
  307. }
  308. int dw_dphy_g118_settle(struct dw_dphy_rx *dphy)
  309. {
  310. u32 input_freq, total_settle, settle_time, byte_clk, lp_time;
  311. lp_time = dphy->lp_time;
  312. input_freq = dphy->dphy_freq / 1000;
  313. settle_time = (8 * (1000000 / (input_freq))) + 115000;
  314. byte_clk = (8000000 / (input_freq));
  315. total_settle = (settle_time + lp_time * 1000) / byte_clk;
  316. if (total_settle > 0xFF)
  317. total_settle = 0xFF;
  318. return total_settle;
  319. }
  320. static void dw_dphy_pwr_down(struct dw_dphy_rx *dphy)
  321. {
  322. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0);
  323. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLK, 1);
  324. if (dphy->lanes_config == CTRL_8_LANES)
  325. dw_dphy_write_msk(dphy, R_CSI2_DPHY2_TST_CTRL0, 0, PHY_TESTCLK,
  326. 1);
  327. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 0);
  328. }
  329. static void dw_dphy_pwr_up(struct dw_dphy_rx *dphy)
  330. {
  331. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLK, 1);
  332. if (dphy->lanes_config == CTRL_8_LANES)
  333. dw_dphy_write_msk(dphy, R_CSI2_DPHY2_TST_CTRL0, 1, PHY_TESTCLK,
  334. 1);
  335. dev_vdbg(&dphy->phy->dev, "DPHY power up.\n");
  336. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 1);
  337. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1);
  338. }
  339. static int dw_dphy_gen3_12bit_configure(struct dw_dphy_rx *dphy)
  340. {
  341. u32 input_freq = dphy->dphy_freq;
  342. u8 range = 0;
  343. dev_vdbg(&dphy->phy->dev, "12bit: PHY GEN 3: Freq: %u\n", input_freq);
  344. for (range = 0; (range < ARRAY_SIZE(range_gen3) - 1) &&
  345. ((input_freq / 1000) > range_gen3[range].freq);
  346. range++)
  347. ;
  348. dw_dphy_gen3_12bit_tc_power_up(dphy, range_gen3[range].hsfregrange);
  349. uint8_t lp_time = dphy->lp_time;
  350. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_17, lp_time);//SET SETTLE TIME
  351. dw_dphy_te_write(dphy, RX_SYS_1, range_gen3[range].hsfregrange);
  352. dw_dphy_te_write(dphy, RX_SYS_0, 0x20);
  353. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_2,
  354. (u8)range_gen3[range].osc_freq_target);
  355. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_3,
  356. (u8)(range_gen3[range].osc_freq_target >> 8));
  357. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_4, 0x01);
  358. if (dphy->phy_type) {
  359. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_1, 0x01);
  360. dw_dphy_te_write(dphy, RX_RX_STARTUP_OVR_0, 0x80);
  361. }
  362. if (dphy->phy_type || input_freq <= 1500)
  363. dw_dphy_te_write(dphy, RX_SYS_7, 0x38);
  364. return 0;
  365. }
  366. static int dw_dphy_gen3_8bit_configure(struct dw_dphy_rx *dphy)
  367. {
  368. u32 input_freq = dphy->dphy_freq;
  369. u8 data;
  370. u8 range = 0;
  371. dev_vdbg(&dphy->phy->dev, "8bit: PHY GEN 3: Freq: %u\n", input_freq);
  372. for (range = 0; (range < ARRAY_SIZE(range_gen3) - 1) &&
  373. ((input_freq / 1000) > range_gen3[range].freq);
  374. range++)
  375. ;
  376. dw_dphy_te_write(dphy, RX_SKEW_CAL, dw_dphy_g118_settle(dphy));
  377. data = 1 << 7 | range_gen3[range].hsfregrange;
  378. dw_dphy_te_write(dphy, HSFREQRANGE_8BIT, data);
  379. dw_dphy_gen3_8bit_tc_power_up(dphy);
  380. return 0;
  381. }
  382. static int dw_dphy_gen2_configure(struct dw_dphy_rx *dphy)
  383. {
  384. u32 input_freq = dphy->dphy_freq;
  385. u8 data;
  386. u8 range = 0;
  387. /* provide an initial active-high test clear pulse in TESTCLR */
  388. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 1, PHY_TESTCLR, 1);
  389. dw_dphy_write_msk(dphy, R_CSI2_DPHY_TST_CTRL0, 0, PHY_TESTCLR, 1);
  390. dev_vdbg(&dphy->phy->dev, "PHY GEN 2: Freq: %u\n", input_freq);
  391. for (range = 0; (range < ARRAY_SIZE(range_gen2) - 1) &&
  392. ((input_freq / 1000) > range_gen2[range].freq); range++)
  393. ;
  394. data = range_gen2[range].hsfregrange << 1;
  395. dw_dphy_te_write(dphy, HSFREQRANGE_8BIT, data);
  396. return 0;
  397. }
  398. static int dw_dphy_configure(struct dw_dphy_rx *dphy)
  399. {
  400. bm_info("enter %s\n", __func__);
  401. dw_dphy_pwr_down(dphy);
  402. dphy->dphy_gen = GEN3;
  403. if (dphy->dphy_gen == GEN3) {
  404. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  405. dw_dphy_if_init(dphy);
  406. #endif
  407. dphy->dphy_te_len = BIT12;
  408. if (dphy->dphy_te_len == BIT12)
  409. dw_dphy_gen3_12bit_configure(dphy);
  410. else
  411. dw_dphy_gen3_8bit_configure(dphy);
  412. } else {
  413. dw_dphy_gen2_configure(dphy);
  414. }
  415. dw_dphy_pwr_up(dphy);
  416. return 0;
  417. }
  418. #if IS_ENABLED(CONFIG_DWC_MIPI_TC_DPHY_GEN3)
  419. #if 0
  420. int dw_dphy_if_set_idelay(struct dw_dphy_rx *dphy, u8 dly, u8 cells)
  421. {
  422. u32 val = 0;
  423. dw_dphy_if_write(dphy, IDLYCFG, 0);
  424. dw_dphy_if_write(dphy, IDLYSEL, cells);
  425. dw_dphy_if_write(dphy, IDLYCNTINVAL, dly);
  426. /* Pulse Value Set */
  427. dw_dphy_if_write(dphy, IDLYCFG, 1);
  428. usleep_range(10, 20);
  429. dw_dphy_if_write(dphy, IDLYCFG, 0);
  430. /* Pulse IDELAY CTRL Reset */
  431. dw_dphy_if_write(dphy, DPHY1REGRSTN, 0);
  432. usleep_range(10, 20);
  433. dw_dphy_if_write(dphy, DPHY1REGRSTN, 1);
  434. /* Get Value*/
  435. val = dw_dphy_if_read(dphy, IDLYCNTOUTVAL);
  436. if (val != dly) {
  437. dev_vdbg(&dphy->phy->dev,
  438. "odelay config failed, set %d get %d", dly, val);
  439. return -EINVAL;
  440. }
  441. return 0;
  442. }
  443. int dw_dphy_if_get_idelay(struct dw_dphy_rx *dphy)
  444. {
  445. return dw_dphy_if_read(dphy, IDLYCNTOUTVAL);
  446. }
  447. int dw_dphy_if_set_idelay_lane(struct dw_dphy_rx *dphy, u8 dly, u8 lane)
  448. {
  449. int cell;
  450. switch (lane) {
  451. case 0:
  452. for (cell = 3; cell <= 10; cell++)
  453. dw_dphy_if_set_idelay(dphy, dly, cell);
  454. break;
  455. case 1:
  456. for (cell = 14; cell <= 21; cell++)
  457. dw_dphy_if_set_idelay(dphy, dly, cell);
  458. break;
  459. case 2:
  460. for (cell = 24; cell <= 31; cell++)
  461. dw_dphy_if_set_idelay(dphy, dly, cell);
  462. break;
  463. case 3:
  464. for (cell = 34; cell <= 41; cell++)
  465. dw_dphy_if_set_idelay(dphy, dly, cell);
  466. break;
  467. case 4: /* ALL */
  468. dw_dphy_if_set_idelay(dphy, dly, 0x7F);
  469. break;
  470. default:
  471. dev_err(&dphy->phy->dev, "Lane Value not recognized\n");
  472. return -1;
  473. }
  474. return 0;
  475. }
  476. #endif
  477. #endif
  478. int dw_dphy_init(struct phy *phy)
  479. {
  480. struct dw_dphy_rx *dphy = phy_get_drvdata(phy);
  481. dev_warn(&dphy->phy->dev, "Init DPHY.\n");
  482. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0);
  483. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 0);
  484. return 0;
  485. }
  486. static int dw_dphy_set_phy_state(struct dw_dphy_rx *dphy, u32 on)
  487. {
  488. u8 hs_freq;
  489. bm_info("enter %s\n", __func__);
  490. dphy->lanes_config = dw_dphy_setup_config(dphy);
  491. if (dphy->dphy_te_len == BIT12)
  492. hs_freq = RX_SYS_1;
  493. else
  494. hs_freq = HSFREQRANGE_8BIT;
  495. if (on) {
  496. dw_dphy_configure(dphy);
  497. dev_info(&dphy->phy->dev,
  498. "HS Code: 0X%x\n", dw_dphy_te_read(dphy, hs_freq));
  499. } else {
  500. dw_dphy_write(dphy, R_CSI2_DPHY_SHUTDOWNZ, 0);
  501. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0);
  502. }
  503. return 0;
  504. }
  505. int dw_dphy_power_on(struct phy *phy)
  506. {
  507. struct dw_dphy_rx *dphy = phy_get_drvdata(phy);
  508. dev_info(&dphy->phy->dev, "DPHY Power ON\n");
  509. bm_info("enter %s\n", __func__);
  510. return dw_dphy_set_phy_state(dphy, 1);
  511. }
  512. int dw_dphy_power_off(struct phy *phy)
  513. {
  514. struct dw_dphy_rx *dphy = phy_get_drvdata(phy);
  515. return dw_dphy_set_phy_state(dphy, 0);
  516. }
  517. int dw_dphy_reset(struct phy *phy)
  518. {
  519. struct dw_dphy_rx *dphy = phy_get_drvdata(phy);
  520. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 0);
  521. usleep_range(100, 200);
  522. dw_dphy_write(dphy, R_CSI2_DPHY_RSTZ, 1);
  523. return 0;
  524. }