mrv_dec_all_regs.h 70 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. /**
  54. *-----------------------------------------------------------------------------
  55. * $HeadURL$
  56. * $Author$
  57. * $Rev$
  58. * $Date$
  59. *-----------------------------------------------------------------------------
  60. * @file mrv_dec_all_regs.h
  61. *
  62. * <pre>
  63. *
  64. * Description:
  65. * This header file exports the module register structure and masks.
  66. * it should not be included directly by your driver/application, it will be
  67. * exported by the <TOP>_regs_io.h header file.
  68. *
  69. * </pre>
  70. */
  71. /*****************************************************************************/
  72. #ifndef _MRV_DEC_ALL_REGS_H
  73. #define _MRV_DEC_ALL_REGS_H
  74. /*! Mrv Dec All Register layout */
  75. typedef struct {
  76. uint32_t _notused_0[(0x24 - 0x00) / 4];
  77. uint32_t isp_dec_chipRev; /*!<(r) */
  78. uint32_t isp_dec_chipDate; /*!<(r) */
  79. uint32_t _notused_1[(0x98 - 0x2c) / 4];
  80. uint32_t isp_dec_hichipPatchRev; /*!<(r) */
  81. uint32_t _notused_2[(0xA8 - 0x9c) / 4];
  82. uint32_t isp_dec_productId; /*!<(r) */
  83. uint32_t _notused_3[(0x800 - 0xAc) / 4];
  84. uint32_t isp_dec_ctrl; /*!<(rw), DEC_BASE + 0x00000000 */
  85. uint32_t isp_dec_ctrl_ex; /*!<(rw), DEC_BASE + 0x00000004 */
  86. uint32_t isp_dec_ctrl_ex2; /*!<(rw), DEC_BASE + 0x00000008 */
  87. uint32_t isp_dec_intr_enbl; /*!<(rw), DEC_BASE + 0x0000000C */
  88. uint32_t isp_dec_intr_enbl_ex; /*!<(rw), DEC_BASE + 0x00000010 */
  89. uint32_t isp_dec_intr_enbl_ex2; /*!<(rw), DEC_BASE + 0x00000014 */
  90. uint32_t isp_dec_intr_acknowledge; /*!<(ro), DEC_BASE + 0x00000018 */
  91. uint32_t isp_dec_intr_acknowledge_ex; /*!<(ro), DEC_BASE + 0x0000001C */
  92. uint32_t isp_dec_intr_acknowledge_ex2; /*!<(ro), DEC_BASE + 0x00000020 */
  93. uint32_t isp_dec_tile_status_debug; /*!<(ro), DEC_BASE + 0x00000024 */
  94. uint32_t isp_dec_encoder_debug; /*!<(ro), DEC_BASE + 0x00000028 */
  95. uint32_t isp_dec_decoder_debug; /*!<(ro), DEC_BASE + 0x0000002C */
  96. uint32_t isp_dec_total_reads_in; /*!<(ro), DEC_BASE + 0x00000030 */
  97. uint32_t isp_dec_total_writes_in; /*!<(ro), DEC_BASE + 0x00000034 */
  98. uint32_t isp_dec_total_read_bursts_in; /*!<(ro), DEC_BASE + 0x00000038 */
  99. uint32_t isp_dec_total_write_bursts_in; /*!<(ro), DEC_BASE + 0x0000003C */
  100. uint32_t isp_dec_total_read_reqs_in; /*!<(ro), DEC_BASE + 0x00000040 */
  101. uint32_t isp_dec_total_write_reqs_in; /*!<(ro), DEC_BASE + 0x00000044 */
  102. uint32_t isp_dec_total_read_lasts_in; /*!<(ro), DEC_BASE + 0x00000048 */
  103. uint32_t isp_dec_total_write_lasts_in; /*!<(ro), DEC_BASE + 0x0000004C */
  104. uint32_t isp_dec_total_write_response_in; /*!<(ro), DEC_BASE + 0x00000050 */
  105. uint32_t isp_dec_total_reads_out; /*!<(ro), DEC_BASE + 0x00000054 */
  106. uint32_t isp_dec_total_writes_out; /*!<(ro), DEC_BASE + 0x00000058 */
  107. uint32_t isp_dec_total_read_bursts_out; /*!<(ro), DEC_BASE + 0x0000005C */
  108. uint32_t isp_dec_total_write_bursts_out; /*!<(ro), DEC_BASE + 0x00000060 */
  109. uint32_t isp_dec_total_read_reqs_out; /*!<(ro), DEC_BASE + 0x00000064 */
  110. uint32_t isp_dec_total_write_reqs_out; /*!<(ro), DEC_BASE + 0x00000068 */
  111. uint32_t isp_dec_total_read_lasts_out; /*!<(ro), DEC_BASE + 0x0000006C */
  112. uint32_t isp_dec_total_write_lasts_out; /*!<(ro), DEC_BASE + 0x00000070 */
  113. uint32_t isp_dec_total_write_response_out; /*!<(ro), DEC_BASE + 0x00000074 */
  114. uint32_t isp_dec_status; /*!<(ro), DEC_BASE + 0x00000078 */
  115. uint32_t isp_dec_debug_info_select; /*!<(rw), DEC_BASE + 0x0000007C */
  116. uint32_t isp_dec_read_config_0; /*!<(rw), DEC_BASE + 0x00000080 */
  117. uint32_t isp_dec_read_config_1; /*!<(rw), DEC_BASE + 0x00000084 */
  118. uint32_t isp_dec_read_config_2; /*!<(rw), DEC_BASE + 0x00000088 */
  119. uint32_t isp_dec_read_config_3; /*!<(rw), DEC_BASE + 0x0000008C */
  120. uint32_t isp_dec_read_config_4; /*!<(rw), DEC_BASE + 0x00000090 */
  121. uint32_t isp_dec_read_config_5; /*!<(rw), DEC_BASE + 0x00000094 */
  122. uint32_t isp_dec_read_config_6; /*!<(rw), DEC_BASE + 0x00000098 */
  123. uint32_t isp_dec_read_config_7; /*!<(rw), DEC_BASE + 0x0000009C */
  124. uint32_t isp_dec_read_config_8; /*!<(rw), DEC_BASE + 0x000000A0 */
  125. uint32_t isp_dec_read_config_9; /*!<(rw), DEC_BASE + 0x000000A4 */
  126. uint32_t isp_dec_read_config_10; /*!<(rw), DEC_BASE + 0x000000A8 */
  127. uint32_t isp_dec_read_config_11; /*!<(rw), DEC_BASE + 0x000000AC */
  128. uint32_t isp_dec_read_config_12; /*!<(rw), DEC_BASE + 0x000000B0 */
  129. uint32_t isp_dec_read_config_13; /*!<(rw), DEC_BASE + 0x000000B4 */
  130. uint32_t isp_dec_read_config_14; /*!<(rw), DEC_BASE + 0x000000B8 */
  131. uint32_t isp_dec_read_config_15; /*!<(rw), DEC_BASE + 0x000000BC */
  132. uint32_t isp_dec_read_config_16; /*!<(rw), DEC_BASE + 0x000000C0 */
  133. uint32_t isp_dec_read_config_17; /*!<(rw), DEC_BASE + 0x000000C4 */
  134. uint32_t isp_dec_read_config_18; /*!<(rw), DEC_BASE + 0x000000C8 */
  135. uint32_t isp_dec_read_config_19; /*!<(rw), DEC_BASE + 0x000000CC */
  136. uint32_t isp_dec_read_config_20; /*!<(rw), DEC_BASE + 0x000000D0 */
  137. uint32_t isp_dec_read_config_21; /*!<(rw), DEC_BASE + 0x000000D4 */
  138. uint32_t isp_dec_read_config_22; /*!<(rw), DEC_BASE + 0x000000D8 */
  139. uint32_t isp_dec_read_config_23; /*!<(rw), DEC_BASE + 0x000000DC */
  140. uint32_t isp_dec_read_config_24; /*!<(rw), DEC_BASE + 0x000000E0 */
  141. uint32_t isp_dec_read_config_25; /*!<(rw), DEC_BASE + 0x000000E4 */
  142. uint32_t isp_dec_read_config_26; /*!<(rw), DEC_BASE + 0x000000E8 */
  143. uint32_t isp_dec_read_config_27; /*!<(rw), DEC_BASE + 0x000000EC */
  144. uint32_t isp_dec_read_config_28; /*!<(rw), DEC_BASE + 0x000000F0 */
  145. uint32_t isp_dec_read_config_29; /*!<(rw), DEC_BASE + 0x000000F4 */
  146. uint32_t isp_dec_read_config_30; /*!<(rw), DEC_BASE + 0x000000F8 */
  147. uint32_t isp_dec_read_config_31; /*!<(rw), DEC_BASE + 0x000000FC */
  148. uint32_t isp_dec_read_ex_config_0; /*!<(rw), DEC_BASE + 0x00000100 */
  149. uint32_t isp_dec_read_ex_config_1; /*!<(rw), DEC_BASE + 0x00000104 */
  150. uint32_t isp_dec_read_ex_config_2; /*!<(rw), DEC_BASE + 0x00000108 */
  151. uint32_t isp_dec_read_ex_config_3; /*!<(rw), DEC_BASE + 0x0000010C */
  152. uint32_t isp_dec_read_ex_config_4; /*!<(rw), DEC_BASE + 0x00000110 */
  153. uint32_t isp_dec_read_ex_config_5; /*!<(rw), DEC_BASE + 0x00000114 */
  154. uint32_t isp_dec_read_ex_config_6; /*!<(rw), DEC_BASE + 0x00000118 */
  155. uint32_t isp_dec_read_ex_config_7; /*!<(rw), DEC_BASE + 0x0000011C */
  156. uint32_t isp_dec_read_ex_config_8; /*!<(rw), DEC_BASE + 0x00000120 */
  157. uint32_t isp_dec_read_ex_config_9; /*!<(rw), DEC_BASE + 0x00000124 */
  158. uint32_t isp_dec_read_ex_config_10; /*!<(rw), DEC_BASE + 0x00000128 */
  159. uint32_t isp_dec_read_ex_config_11; /*!<(rw), DEC_BASE + 0x0000012C */
  160. uint32_t isp_dec_read_ex_config_12; /*!<(rw), DEC_BASE + 0x00000130 */
  161. uint32_t isp_dec_read_ex_config_13; /*!<(rw), DEC_BASE + 0x00000134 */
  162. uint32_t isp_dec_read_ex_config_14; /*!<(rw), DEC_BASE + 0x00000138 */
  163. uint32_t isp_dec_read_ex_config_15; /*!<(rw), DEC_BASE + 0x0000013C */
  164. uint32_t isp_dec_read_ex_config_16; /*!<(rw), DEC_BASE + 0x00000140 */
  165. uint32_t isp_dec_read_ex_config_17; /*!<(rw), DEC_BASE + 0x00000144 */
  166. uint32_t isp_dec_read_ex_config_18; /*!<(rw), DEC_BASE + 0x00000148 */
  167. uint32_t isp_dec_read_ex_config_19; /*!<(rw), DEC_BASE + 0x0000014C */
  168. uint32_t isp_dec_read_ex_config_20; /*!<(rw), DEC_BASE + 0x00000150 */
  169. uint32_t isp_dec_read_ex_config_21; /*!<(rw), DEC_BASE + 0x00000154 */
  170. uint32_t isp_dec_read_ex_config_22; /*!<(rw), DEC_BASE + 0x00000158 */
  171. uint32_t isp_dec_read_ex_config_23; /*!<(rw), DEC_BASE + 0x0000015C */
  172. uint32_t isp_dec_read_ex_config_24; /*!<(rw), DEC_BASE + 0x00000160 */
  173. uint32_t isp_dec_read_ex_config_25; /*!<(rw), DEC_BASE + 0x00000164 */
  174. uint32_t isp_dec_read_ex_config_26; /*!<(rw), DEC_BASE + 0x00000168 */
  175. uint32_t isp_dec_read_ex_config_27; /*!<(rw), DEC_BASE + 0x0000016C */
  176. uint32_t isp_dec_read_ex_config_28; /*!<(rw), DEC_BASE + 0x00000170 */
  177. uint32_t isp_dec_read_ex_config_29; /*!<(rw), DEC_BASE + 0x00000174 */
  178. uint32_t isp_dec_read_ex_config_30; /*!<(rw), DEC_BASE + 0x00000178 */
  179. uint32_t isp_dec_read_ex_config_31; /*!<(rw), DEC_BASE + 0x0000017C */
  180. uint32_t isp_dec_write_config_0; /*!<(rw), DEC_BASE + 0x00000180 */
  181. uint32_t isp_dec_write_config_1; /*!<(rw), DEC_BASE + 0x00000184 */
  182. uint32_t isp_dec_write_config_2; /*!<(rw), DEC_BASE + 0x00000188 */
  183. uint32_t isp_dec_write_config_3; /*!<(rw), DEC_BASE + 0x0000018C */
  184. uint32_t isp_dec_write_config_4; /*!<(rw), DEC_BASE + 0x00000190 */
  185. uint32_t isp_dec_write_config_5; /*!<(rw), DEC_BASE + 0x00000194 */
  186. uint32_t isp_dec_write_config_6; /*!<(rw), DEC_BASE + 0x00000198 */
  187. uint32_t isp_dec_write_config_7; /*!<(rw), DEC_BASE + 0x0000019C */
  188. uint32_t isp_dec_write_config_8; /*!<(rw), DEC_BASE + 0x000001A0 */
  189. uint32_t isp_dec_write_config_9; /*!<(rw), DEC_BASE + 0x000001A4 */
  190. uint32_t isp_dec_write_config_10; /*!<(rw), DEC_BASE + 0x000001A8 */
  191. uint32_t isp_dec_write_config_11; /*!<(rw), DEC_BASE + 0x000001AC */
  192. uint32_t isp_dec_write_config_12; /*!<(rw), DEC_BASE + 0x000001B0 */
  193. uint32_t isp_dec_write_config_13; /*!<(rw), DEC_BASE + 0x000001B4 */
  194. uint32_t isp_dec_write_config_14; /*!<(rw), DEC_BASE + 0x000001B8 */
  195. uint32_t isp_dec_write_config_15; /*!<(rw), DEC_BASE + 0x000001BC */
  196. uint32_t isp_dec_write_config_16; /*!<(rw), DEC_BASE + 0x000001C0 */
  197. uint32_t isp_dec_write_config_17; /*!<(rw), DEC_BASE + 0x000001C4 */
  198. uint32_t isp_dec_write_config_18; /*!<(rw), DEC_BASE + 0x000001C8 */
  199. uint32_t isp_dec_write_config_19; /*!<(rw), DEC_BASE + 0x000001CC */
  200. uint32_t isp_dec_write_config_20; /*!<(rw), DEC_BASE + 0x000001D0 */
  201. uint32_t isp_dec_write_config_21; /*!<(rw), DEC_BASE + 0x000001D4 */
  202. uint32_t isp_dec_write_config_22; /*!<(rw), DEC_BASE + 0x000001D8 */
  203. uint32_t isp_dec_write_config_23; /*!<(rw), DEC_BASE + 0x000001DC */
  204. uint32_t isp_dec_write_config_24; /*!<(rw), DEC_BASE + 0x000001E0 */
  205. uint32_t isp_dec_write_config_25; /*!<(rw), DEC_BASE + 0x000001E4 */
  206. uint32_t isp_dec_write_config_26; /*!<(rw), DEC_BASE + 0x000001E8 */
  207. uint32_t isp_dec_write_config_27; /*!<(rw), DEC_BASE + 0x000001EC */
  208. uint32_t isp_dec_write_config_28; /*!<(rw), DEC_BASE + 0x000001F0 */
  209. uint32_t isp_dec_write_config_29; /*!<(rw), DEC_BASE + 0x000001F4 */
  210. uint32_t isp_dec_write_config_30; /*!<(rw), DEC_BASE + 0x000001F8 */
  211. uint32_t isp_dec_write_config_31; /*!<(rw), DEC_BASE + 0x000001FC */
  212. uint32_t isp_dec_write_ex_config_0; /*!<(rw), DEC_BASE + 0x00000200 */
  213. uint32_t isp_dec_write_ex_config_1; /*!<(rw), DEC_BASE + 0x00000204 */
  214. uint32_t isp_dec_write_ex_config_2; /*!<(rw), DEC_BASE + 0x00000208 */
  215. uint32_t isp_dec_write_ex_config_3; /*!<(rw), DEC_BASE + 0x0000020C */
  216. uint32_t isp_dec_write_ex_config_4; /*!<(rw), DEC_BASE + 0x00000210 */
  217. uint32_t isp_dec_write_ex_config_5; /*!<(rw), DEC_BASE + 0x00000214 */
  218. uint32_t isp_dec_write_ex_config_6; /*!<(rw), DEC_BASE + 0x00000218 */
  219. uint32_t isp_dec_write_ex_config_7; /*!<(rw), DEC_BASE + 0x0000021C */
  220. uint32_t isp_dec_write_ex_config_8; /*!<(rw), DEC_BASE + 0x00000220 */
  221. uint32_t isp_dec_write_ex_config_9; /*!<(rw), DEC_BASE + 0x00000224 */
  222. uint32_t isp_dec_write_ex_config_10; /*!<(rw), DEC_BASE + 0x00000228 */
  223. uint32_t isp_dec_write_ex_config_11; /*!<(rw), DEC_BASE + 0x0000022C */
  224. uint32_t isp_dec_write_ex_config_12; /*!<(rw), DEC_BASE + 0x00000230 */
  225. uint32_t isp_dec_write_ex_config_13; /*!<(rw), DEC_BASE + 0x00000234 */
  226. uint32_t isp_dec_write_ex_config_14; /*!<(rw), DEC_BASE + 0x00000238 */
  227. uint32_t isp_dec_write_ex_config_15; /*!<(rw), DEC_BASE + 0x0000023C */
  228. uint32_t isp_dec_write_ex_config_16; /*!<(rw), DEC_BASE + 0x00000240 */
  229. uint32_t isp_dec_write_ex_config_17; /*!<(rw), DEC_BASE + 0x00000244 */
  230. uint32_t isp_dec_write_ex_config_18; /*!<(rw), DEC_BASE + 0x00000248 */
  231. uint32_t isp_dec_write_ex_config_19; /*!<(rw), DEC_BASE + 0x0000024C */
  232. uint32_t isp_dec_write_ex_config_20; /*!<(rw), DEC_BASE + 0x00000250 */
  233. uint32_t isp_dec_write_ex_config_21; /*!<(rw), DEC_BASE + 0x00000254 */
  234. uint32_t isp_dec_write_ex_config_22; /*!<(rw), DEC_BASE + 0x00000258 */
  235. uint32_t isp_dec_write_ex_config_23; /*!<(rw), DEC_BASE + 0x0000025C */
  236. uint32_t isp_dec_write_ex_config_24; /*!<(rw), DEC_BASE + 0x00000260 */
  237. uint32_t isp_dec_write_ex_config_25; /*!<(rw), DEC_BASE + 0x00000264 */
  238. uint32_t isp_dec_write_ex_config_26; /*!<(rw), DEC_BASE + 0x00000268 */
  239. uint32_t isp_dec_write_ex_config_27; /*!<(rw), DEC_BASE + 0x0000026C */
  240. uint32_t isp_dec_write_ex_config_28; /*!<(rw), DEC_BASE + 0x00000270 */
  241. uint32_t isp_dec_write_ex_config_29; /*!<(rw), DEC_BASE + 0x00000274 */
  242. uint32_t isp_dec_write_ex_config_30; /*!<(rw), DEC_BASE + 0x00000278 */
  243. uint32_t isp_dec_write_ex_config_31; /*!<(rw), DEC_BASE + 0x0000027C */
  244. uint32_t isp_dec_read_buffer_base_0; /*!<(rw), DEC_BASE + 0x00000280 */
  245. uint32_t isp_dec_read_buffer_base_1; /*!<(rw), DEC_BASE + 0x00000284 */
  246. uint32_t isp_dec_read_buffer_base_2; /*!<(rw), DEC_BASE + 0x00000288 */
  247. uint32_t isp_dec_read_buffer_base_3; /*!<(rw), DEC_BASE + 0x0000028C */
  248. uint32_t isp_dec_read_buffer_base_4; /*!<(rw), DEC_BASE + 0x00000290 */
  249. uint32_t isp_dec_read_buffer_base_5; /*!<(rw), DEC_BASE + 0x00000294 */
  250. uint32_t isp_dec_read_buffer_base_6; /*!<(rw), DEC_BASE + 0x00000298 */
  251. uint32_t isp_dec_read_buffer_base_7; /*!<(rw), DEC_BASE + 0x0000029C */
  252. uint32_t isp_dec_read_buffer_base_8; /*!<(rw), DEC_BASE + 0x000002A0 */
  253. uint32_t isp_dec_read_buffer_base_9; /*!<(rw), DEC_BASE + 0x000002A4 */
  254. uint32_t isp_dec_read_buffer_base_10; /*!<(rw), DEC_BASE + 0x000002A8 */
  255. uint32_t isp_dec_read_buffer_base_11; /*!<(rw), DEC_BASE + 0x000002AC */
  256. uint32_t isp_dec_read_buffer_base_12; /*!<(rw), DEC_BASE + 0x000002B0 */
  257. uint32_t isp_dec_read_buffer_base_13; /*!<(rw), DEC_BASE + 0x000002B4 */
  258. uint32_t isp_dec_read_buffer_base_14; /*!<(rw), DEC_BASE + 0x000002B8 */
  259. uint32_t isp_dec_read_buffer_base_15; /*!<(rw), DEC_BASE + 0x000002BC */
  260. uint32_t isp_dec_read_buffer_base_16; /*!<(rw), DEC_BASE + 0x000002C0 */
  261. uint32_t isp_dec_read_buffer_base_17; /*!<(rw), DEC_BASE + 0x000002C4 */
  262. uint32_t isp_dec_read_buffer_base_18; /*!<(rw), DEC_BASE + 0x000002C8 */
  263. uint32_t isp_dec_read_buffer_base_19; /*!<(rw), DEC_BASE + 0x000002CC */
  264. uint32_t isp_dec_read_buffer_base_20; /*!<(rw), DEC_BASE + 0x000002D0 */
  265. uint32_t isp_dec_read_buffer_base_21; /*!<(rw), DEC_BASE + 0x000002D4 */
  266. uint32_t isp_dec_read_buffer_base_22; /*!<(rw), DEC_BASE + 0x000002D8 */
  267. uint32_t isp_dec_read_buffer_base_23; /*!<(rw), DEC_BASE + 0x000002DC */
  268. uint32_t isp_dec_read_buffer_base_24; /*!<(rw), DEC_BASE + 0x000002E0 */
  269. uint32_t isp_dec_read_buffer_base_25; /*!<(rw), DEC_BASE + 0x000002E4 */
  270. uint32_t isp_dec_read_buffer_base_26; /*!<(rw), DEC_BASE + 0x000002E8 */
  271. uint32_t isp_dec_read_buffer_base_27; /*!<(rw), DEC_BASE + 0x000002EC */
  272. uint32_t isp_dec_read_buffer_base_28; /*!<(rw), DEC_BASE + 0x000002F0 */
  273. uint32_t isp_dec_read_buffer_base_29; /*!<(rw), DEC_BASE + 0x000002F4 */
  274. uint32_t isp_dec_read_buffer_base_30; /*!<(rw), DEC_BASE + 0x000002F8 */
  275. uint32_t isp_dec_read_buffer_base_31; /*!<(rw), DEC_BASE + 0x000002FC */
  276. uint32_t isp_dec_read_buffer_base_ex_0; /*!<(rw), DEC_BASE + 0x00000300 */
  277. uint32_t isp_dec_read_buffer_base_ex_1; /*!<(rw), DEC_BASE + 0x00000304 */
  278. uint32_t isp_dec_read_buffer_base_ex_2; /*!<(rw), DEC_BASE + 0x00000308 */
  279. uint32_t isp_dec_read_buffer_base_ex_3; /*!<(rw), DEC_BASE + 0x0000030C */
  280. uint32_t isp_dec_read_buffer_base_ex_4; /*!<(rw), DEC_BASE + 0x00000310 */
  281. uint32_t isp_dec_read_buffer_base_ex_5; /*!<(rw), DEC_BASE + 0x00000314 */
  282. uint32_t isp_dec_read_buffer_base_ex_6; /*!<(rw), DEC_BASE + 0x00000318 */
  283. uint32_t isp_dec_read_buffer_base_ex_7; /*!<(rw), DEC_BASE + 0x0000031C */
  284. uint32_t isp_dec_read_buffer_base_ex_8; /*!<(rw), DEC_BASE + 0x00000320 */
  285. uint32_t isp_dec_read_buffer_base_ex_9; /*!<(rw), DEC_BASE + 0x00000324 */
  286. uint32_t isp_dec_read_buffer_base_ex_10; /*!<(rw), DEC_BASE + 0x00000328 */
  287. uint32_t isp_dec_read_buffer_base_ex_11; /*!<(rw), DEC_BASE + 0x0000032C */
  288. uint32_t isp_dec_read_buffer_base_ex_12; /*!<(rw), DEC_BASE + 0x00000330 */
  289. uint32_t isp_dec_read_buffer_base_ex_13; /*!<(rw), DEC_BASE + 0x00000334 */
  290. uint32_t isp_dec_read_buffer_base_ex_14; /*!<(rw), DEC_BASE + 0x00000338 */
  291. uint32_t isp_dec_read_buffer_base_ex_15; /*!<(rw), DEC_BASE + 0x0000033C */
  292. uint32_t isp_dec_read_buffer_base_ex_16; /*!<(rw), DEC_BASE + 0x00000340 */
  293. uint32_t isp_dec_read_buffer_base_ex_17; /*!<(rw), DEC_BASE + 0x00000344 */
  294. uint32_t isp_dec_read_buffer_base_ex_18; /*!<(rw), DEC_BASE + 0x00000348 */
  295. uint32_t isp_dec_read_buffer_base_ex_19; /*!<(rw), DEC_BASE + 0x0000034C */
  296. uint32_t isp_dec_read_buffer_base_ex_20; /*!<(rw), DEC_BASE + 0x00000350 */
  297. uint32_t isp_dec_read_buffer_base_ex_21; /*!<(rw), DEC_BASE + 0x00000354 */
  298. uint32_t isp_dec_read_buffer_base_ex_22; /*!<(rw), DEC_BASE + 0x00000358 */
  299. uint32_t isp_dec_read_buffer_base_ex_23; /*!<(rw), DEC_BASE + 0x0000035C */
  300. uint32_t isp_dec_read_buffer_base_ex_24; /*!<(rw), DEC_BASE + 0x00000360 */
  301. uint32_t isp_dec_read_buffer_base_ex_25; /*!<(rw), DEC_BASE + 0x00000364 */
  302. uint32_t isp_dec_read_buffer_base_ex_26; /*!<(rw), DEC_BASE + 0x00000368 */
  303. uint32_t isp_dec_read_buffer_base_ex_27; /*!<(rw), DEC_BASE + 0x0000036C */
  304. uint32_t isp_dec_read_buffer_base_ex_28; /*!<(rw), DEC_BASE + 0x00000370 */
  305. uint32_t isp_dec_read_buffer_base_ex_29; /*!<(rw), DEC_BASE + 0x00000374 */
  306. uint32_t isp_dec_read_buffer_base_ex_30; /*!<(rw), DEC_BASE + 0x00000378 */
  307. uint32_t isp_dec_read_buffer_base_ex_31; /*!<(rw), DEC_BASE + 0x0000037C */
  308. uint32_t isp_dec_read_buffer_end_0; /*!<(rw), DEC_BASE + 0x00000380 */
  309. uint32_t isp_dec_read_buffer_end_1; /*!<(rw), DEC_BASE + 0x00000384 */
  310. uint32_t isp_dec_read_buffer_end_2; /*!<(rw), DEC_BASE + 0x00000388 */
  311. uint32_t isp_dec_read_buffer_end_3; /*!<(rw), DEC_BASE + 0x0000038C */
  312. uint32_t isp_dec_read_buffer_end_4; /*!<(rw), DEC_BASE + 0x00000390 */
  313. uint32_t isp_dec_read_buffer_end_5; /*!<(rw), DEC_BASE + 0x00000394 */
  314. uint32_t isp_dec_read_buffer_end_6; /*!<(rw), DEC_BASE + 0x00000398 */
  315. uint32_t isp_dec_read_buffer_end_7; /*!<(rw), DEC_BASE + 0x0000039C */
  316. uint32_t isp_dec_read_buffer_end_8; /*!<(rw), DEC_BASE + 0x000003A0 */
  317. uint32_t isp_dec_read_buffer_end_9; /*!<(rw), DEC_BASE + 0x000003A4 */
  318. uint32_t isp_dec_read_buffer_end_10; /*!<(rw), DEC_BASE + 0x000003A8 */
  319. uint32_t isp_dec_read_buffer_end_11; /*!<(rw), DEC_BASE + 0x000003AC */
  320. uint32_t isp_dec_read_buffer_end_12; /*!<(rw), DEC_BASE + 0x000003B0 */
  321. uint32_t isp_dec_read_buffer_end_13; /*!<(rw), DEC_BASE + 0x000003B4 */
  322. uint32_t isp_dec_read_buffer_end_14; /*!<(rw), DEC_BASE + 0x000003B8 */
  323. uint32_t isp_dec_read_buffer_end_15; /*!<(rw), DEC_BASE + 0x000003BC */
  324. uint32_t isp_dec_read_buffer_end_16; /*!<(rw), DEC_BASE + 0x000003C0 */
  325. uint32_t isp_dec_read_buffer_end_17; /*!<(rw), DEC_BASE + 0x000003C4 */
  326. uint32_t isp_dec_read_buffer_end_18; /*!<(rw), DEC_BASE + 0x000003C8 */
  327. uint32_t isp_dec_read_buffer_end_19; /*!<(rw), DEC_BASE + 0x000003CC */
  328. uint32_t isp_dec_read_buffer_end_20; /*!<(rw), DEC_BASE + 0x000003D0 */
  329. uint32_t isp_dec_read_buffer_end_21; /*!<(rw), DEC_BASE + 0x000003D4 */
  330. uint32_t isp_dec_read_buffer_end_22; /*!<(rw), DEC_BASE + 0x000003D8 */
  331. uint32_t isp_dec_read_buffer_end_23; /*!<(rw), DEC_BASE + 0x000003DC */
  332. uint32_t isp_dec_read_buffer_end_24; /*!<(rw), DEC_BASE + 0x000003E0 */
  333. uint32_t isp_dec_read_buffer_end_25; /*!<(rw), DEC_BASE + 0x000003E4 */
  334. uint32_t isp_dec_read_buffer_end_26; /*!<(rw), DEC_BASE + 0x000003E8 */
  335. uint32_t isp_dec_read_buffer_end_27; /*!<(rw), DEC_BASE + 0x000003EC */
  336. uint32_t isp_dec_read_buffer_end_28; /*!<(rw), DEC_BASE + 0x000003F0 */
  337. uint32_t isp_dec_read_buffer_end_29; /*!<(rw), DEC_BASE + 0x000003F4 */
  338. uint32_t isp_dec_read_buffer_end_30; /*!<(rw), DEC_BASE + 0x000003F8 */
  339. uint32_t isp_dec_read_buffer_end_31; /*!<(rw), DEC_BASE + 0x000003FC */
  340. uint32_t isp_dec_read_buffer_end_ex_0; /*!<(rw), DEC_BASE + 0x00000400 */
  341. uint32_t isp_dec_read_buffer_end_ex_1; /*!<(rw), DEC_BASE + 0x00000404 */
  342. uint32_t isp_dec_read_buffer_end_ex_2; /*!<(rw), DEC_BASE + 0x00000408 */
  343. uint32_t isp_dec_read_buffer_end_ex_3; /*!<(rw), DEC_BASE + 0x0000040C */
  344. uint32_t isp_dec_read_buffer_end_ex_4; /*!<(rw), DEC_BASE + 0x00000410 */
  345. uint32_t isp_dec_read_buffer_end_ex_5; /*!<(rw), DEC_BASE + 0x00000414 */
  346. uint32_t isp_dec_read_buffer_end_ex_6; /*!<(rw), DEC_BASE + 0x00000418 */
  347. uint32_t isp_dec_read_buffer_end_ex_7; /*!<(rw), DEC_BASE + 0x0000041C */
  348. uint32_t isp_dec_read_buffer_end_ex_8; /*!<(rw), DEC_BASE + 0x00000420 */
  349. uint32_t isp_dec_read_buffer_end_ex_9; /*!<(rw), DEC_BASE + 0x00000424 */
  350. uint32_t isp_dec_read_buffer_end_ex_10; /*!<(rw), DEC_BASE + 0x00000428 */
  351. uint32_t isp_dec_read_buffer_end_ex_11; /*!<(rw), DEC_BASE + 0x0000042C */
  352. uint32_t isp_dec_read_buffer_end_ex_12; /*!<(rw), DEC_BASE + 0x00000430 */
  353. uint32_t isp_dec_read_buffer_end_ex_13; /*!<(rw), DEC_BASE + 0x00000434 */
  354. uint32_t isp_dec_read_buffer_end_ex_14; /*!<(rw), DEC_BASE + 0x00000438 */
  355. uint32_t isp_dec_read_buffer_end_ex_15; /*!<(rw), DEC_BASE + 0x0000043C */
  356. uint32_t isp_dec_read_buffer_end_ex_16; /*!<(rw), DEC_BASE + 0x00000440 */
  357. uint32_t isp_dec_read_buffer_end_ex_17; /*!<(rw), DEC_BASE + 0x00000444 */
  358. uint32_t isp_dec_read_buffer_end_ex_18; /*!<(rw), DEC_BASE + 0x00000448 */
  359. uint32_t isp_dec_read_buffer_end_ex_19; /*!<(rw), DEC_BASE + 0x0000044C */
  360. uint32_t isp_dec_read_buffer_end_ex_20; /*!<(rw), DEC_BASE + 0x00000450 */
  361. uint32_t isp_dec_read_buffer_end_ex_21; /*!<(rw), DEC_BASE + 0x00000454 */
  362. uint32_t isp_dec_read_buffer_end_ex_22; /*!<(rw), DEC_BASE + 0x00000458 */
  363. uint32_t isp_dec_read_buffer_end_ex_23; /*!<(rw), DEC_BASE + 0x0000045C */
  364. uint32_t isp_dec_read_buffer_end_ex_24; /*!<(rw), DEC_BASE + 0x00000460 */
  365. uint32_t isp_dec_read_buffer_end_ex_25; /*!<(rw), DEC_BASE + 0x00000464 */
  366. uint32_t isp_dec_read_buffer_end_ex_26; /*!<(rw), DEC_BASE + 0x00000468 */
  367. uint32_t isp_dec_read_buffer_end_ex_27; /*!<(rw), DEC_BASE + 0x0000046C */
  368. uint32_t isp_dec_read_buffer_end_ex_28; /*!<(rw), DEC_BASE + 0x00000470 */
  369. uint32_t isp_dec_read_buffer_end_ex_29; /*!<(rw), DEC_BASE + 0x00000474 */
  370. uint32_t isp_dec_read_buffer_end_ex_30; /*!<(rw), DEC_BASE + 0x00000478 */
  371. uint32_t isp_dec_read_buffer_end_ex_31; /*!<(rw), DEC_BASE + 0x0000047C */
  372. uint32_t isp_dec_read_flush_cache_0; /*!<(rw), DEC_BASE + 0x00000480 */
  373. uint32_t isp_dec_read_flush_cache_1; /*!<(rw), DEC_BASE + 0x00000484 */
  374. uint32_t isp_dec_read_flush_cache_2; /*!<(rw), DEC_BASE + 0x00000488 */
  375. uint32_t isp_dec_read_flush_cache_3; /*!<(rw), DEC_BASE + 0x0000048C */
  376. uint32_t isp_dec_read_flush_cache_4; /*!<(rw), DEC_BASE + 0x00000490 */
  377. uint32_t isp_dec_read_flush_cache_5; /*!<(rw), DEC_BASE + 0x00000494 */
  378. uint32_t isp_dec_read_flush_cache_6; /*!<(rw), DEC_BASE + 0x00000498 */
  379. uint32_t isp_dec_read_flush_cache_7; /*!<(rw), DEC_BASE + 0x0000049C */
  380. uint32_t isp_dec_read_flush_cache_8; /*!<(rw), DEC_BASE + 0x000004A0 */
  381. uint32_t isp_dec_read_flush_cache_9; /*!<(rw), DEC_BASE + 0x000004A4 */
  382. uint32_t isp_dec_read_flush_cache_10; /*!<(rw), DEC_BASE + 0x000004A8 */
  383. uint32_t isp_dec_read_flush_cache_11; /*!<(rw), DEC_BASE + 0x000004AC */
  384. uint32_t isp_dec_read_flush_cache_12; /*!<(rw), DEC_BASE + 0x000004B0 */
  385. uint32_t isp_dec_read_flush_cache_13; /*!<(rw), DEC_BASE + 0x000004B4 */
  386. uint32_t isp_dec_read_flush_cache_14; /*!<(rw), DEC_BASE + 0x000004B8 */
  387. uint32_t isp_dec_read_flush_cache_15; /*!<(rw), DEC_BASE + 0x000004BC */
  388. uint32_t isp_dec_read_flush_cache_16; /*!<(rw), DEC_BASE + 0x000004C0 */
  389. uint32_t isp_dec_read_flush_cache_17; /*!<(rw), DEC_BASE + 0x000004C4 */
  390. uint32_t isp_dec_read_flush_cache_18; /*!<(rw), DEC_BASE + 0x000004C8 */
  391. uint32_t isp_dec_read_flush_cache_19; /*!<(rw), DEC_BASE + 0x000004CC */
  392. uint32_t isp_dec_read_flush_cache_20; /*!<(rw), DEC_BASE + 0x000004D0 */
  393. uint32_t isp_dec_read_flush_cache_21; /*!<(rw), DEC_BASE + 0x000004D4 */
  394. uint32_t isp_dec_read_flush_cache_22; /*!<(rw), DEC_BASE + 0x000004D8 */
  395. uint32_t isp_dec_read_flush_cache_23; /*!<(rw), DEC_BASE + 0x000004DC */
  396. uint32_t isp_dec_read_flush_cache_24; /*!<(rw), DEC_BASE + 0x000004E0 */
  397. uint32_t isp_dec_read_flush_cache_25; /*!<(rw), DEC_BASE + 0x000004E4 */
  398. uint32_t isp_dec_read_flush_cache_26; /*!<(rw), DEC_BASE + 0x000004E8 */
  399. uint32_t isp_dec_read_flush_cache_27; /*!<(rw), DEC_BASE + 0x000004EC */
  400. uint32_t isp_dec_read_flush_cache_28; /*!<(rw), DEC_BASE + 0x000004F0 */
  401. uint32_t isp_dec_read_flush_cache_29; /*!<(rw), DEC_BASE + 0x000004F4 */
  402. uint32_t isp_dec_read_flush_cache_30; /*!<(rw), DEC_BASE + 0x000004F8 */
  403. uint32_t isp_dec_read_flush_cache_31; /*!<(rw), DEC_BASE + 0x000004FC */
  404. uint32_t isp_dec_read_flush_cache_ex_0; /*!<(rw), DEC_BASE + 0x00000500 */
  405. uint32_t isp_dec_read_flush_cache_ex_1; /*!<(rw), DEC_BASE + 0x00000504 */
  406. uint32_t isp_dec_read_flush_cache_ex_2; /*!<(rw), DEC_BASE + 0x00000508 */
  407. uint32_t isp_dec_read_flush_cache_ex_3; /*!<(rw), DEC_BASE + 0x0000050C */
  408. uint32_t isp_dec_read_flush_cache_ex_4; /*!<(rw), DEC_BASE + 0x00000510 */
  409. uint32_t isp_dec_read_flush_cache_ex_5; /*!<(rw), DEC_BASE + 0x00000514 */
  410. uint32_t isp_dec_read_flush_cache_ex_6; /*!<(rw), DEC_BASE + 0x00000518 */
  411. uint32_t isp_dec_read_flush_cache_ex_7; /*!<(rw), DEC_BASE + 0x0000051C */
  412. uint32_t isp_dec_read_flush_cache_ex_8; /*!<(rw), DEC_BASE + 0x00000520 */
  413. uint32_t isp_dec_read_flush_cache_ex_9; /*!<(rw), DEC_BASE + 0x00000524 */
  414. uint32_t isp_dec_read_flush_cache_ex_10; /*!<(rw), DEC_BASE + 0x00000528 */
  415. uint32_t isp_dec_read_flush_cache_ex_11; /*!<(rw), DEC_BASE + 0x0000052C */
  416. uint32_t isp_dec_read_flush_cache_ex_12; /*!<(rw), DEC_BASE + 0x00000530 */
  417. uint32_t isp_dec_read_flush_cache_ex_13; /*!<(rw), DEC_BASE + 0x00000534 */
  418. uint32_t isp_dec_read_flush_cache_ex_14; /*!<(rw), DEC_BASE + 0x00000538 */
  419. uint32_t isp_dec_read_flush_cache_ex_15; /*!<(rw), DEC_BASE + 0x0000053C */
  420. uint32_t isp_dec_read_flush_cache_ex_16; /*!<(rw), DEC_BASE + 0x00000540 */
  421. uint32_t isp_dec_read_flush_cache_ex_17; /*!<(rw), DEC_BASE + 0x00000544 */
  422. uint32_t isp_dec_read_flush_cache_ex_18; /*!<(rw), DEC_BASE + 0x00000548 */
  423. uint32_t isp_dec_read_flush_cache_ex_19; /*!<(rw), DEC_BASE + 0x0000054C */
  424. uint32_t isp_dec_read_flush_cache_ex_20; /*!<(rw), DEC_BASE + 0x00000550 */
  425. uint32_t isp_dec_read_flush_cache_ex_21; /*!<(rw), DEC_BASE + 0x00000554 */
  426. uint32_t isp_dec_read_flush_cache_ex_22; /*!<(rw), DEC_BASE + 0x00000558 */
  427. uint32_t isp_dec_read_flush_cache_ex_23; /*!<(rw), DEC_BASE + 0x0000055C */
  428. uint32_t isp_dec_read_flush_cache_ex_24; /*!<(rw), DEC_BASE + 0x00000560 */
  429. uint32_t isp_dec_read_flush_cache_ex_25; /*!<(rw), DEC_BASE + 0x00000564 */
  430. uint32_t isp_dec_read_flush_cache_ex_26; /*!<(rw), DEC_BASE + 0x00000568 */
  431. uint32_t isp_dec_read_flush_cache_ex_27; /*!<(rw), DEC_BASE + 0x0000056C */
  432. uint32_t isp_dec_read_flush_cache_ex_28; /*!<(rw), DEC_BASE + 0x00000570 */
  433. uint32_t isp_dec_read_flush_cache_ex_29; /*!<(rw), DEC_BASE + 0x00000574 */
  434. uint32_t isp_dec_read_flush_cache_ex_30; /*!<(rw), DEC_BASE + 0x00000578 */
  435. uint32_t isp_dec_read_flush_cache_ex_31; /*!<(rw), DEC_BASE + 0x0000057C */
  436. uint32_t isp_dec_write_buffer_base_0; /*!<(rw), DEC_BASE + 0x00000580 */
  437. uint32_t isp_dec_write_buffer_base_1; /*!<(rw), DEC_BASE + 0x00000584 */
  438. uint32_t isp_dec_write_buffer_base_2; /*!<(rw), DEC_BASE + 0x00000588 */
  439. uint32_t isp_dec_write_buffer_base_3; /*!<(rw), DEC_BASE + 0x0000058C */
  440. uint32_t isp_dec_write_buffer_base_4; /*!<(rw), DEC_BASE + 0x00000590 */
  441. uint32_t isp_dec_write_buffer_base_5; /*!<(rw), DEC_BASE + 0x00000594 */
  442. uint32_t isp_dec_write_buffer_base_6; /*!<(rw), DEC_BASE + 0x00000598 */
  443. uint32_t isp_dec_write_buffer_base_7; /*!<(rw), DEC_BASE + 0x0000059C */
  444. uint32_t isp_dec_write_buffer_base_8; /*!<(rw), DEC_BASE + 0x000005A0 */
  445. uint32_t isp_dec_write_buffer_base_9; /*!<(rw), DEC_BASE + 0x000005A4 */
  446. uint32_t isp_dec_write_buffer_base_10; /*!<(rw), DEC_BASE + 0x000005A8 */
  447. uint32_t isp_dec_write_buffer_base_11; /*!<(rw), DEC_BASE + 0x000005AC */
  448. uint32_t isp_dec_write_buffer_base_12; /*!<(rw), DEC_BASE + 0x000005B0 */
  449. uint32_t isp_dec_write_buffer_base_13; /*!<(rw), DEC_BASE + 0x000005B4 */
  450. uint32_t isp_dec_write_buffer_base_14; /*!<(rw), DEC_BASE + 0x000005B8 */
  451. uint32_t isp_dec_write_buffer_base_15; /*!<(rw), DEC_BASE + 0x000005BC */
  452. uint32_t isp_dec_write_buffer_base_16; /*!<(rw), DEC_BASE + 0x000005C0 */
  453. uint32_t isp_dec_write_buffer_base_17; /*!<(rw), DEC_BASE + 0x000005C4 */
  454. uint32_t isp_dec_write_buffer_base_18; /*!<(rw), DEC_BASE + 0x000005C8 */
  455. uint32_t isp_dec_write_buffer_base_19; /*!<(rw), DEC_BASE + 0x000005CC */
  456. uint32_t isp_dec_write_buffer_base_20; /*!<(rw), DEC_BASE + 0x000005D0 */
  457. uint32_t isp_dec_write_buffer_base_21; /*!<(rw), DEC_BASE + 0x000005D4 */
  458. uint32_t isp_dec_write_buffer_base_22; /*!<(rw), DEC_BASE + 0x000005D8 */
  459. uint32_t isp_dec_write_buffer_base_23; /*!<(rw), DEC_BASE + 0x000005DC */
  460. uint32_t isp_dec_write_buffer_base_24; /*!<(rw), DEC_BASE + 0x000005E0 */
  461. uint32_t isp_dec_write_buffer_base_25; /*!<(rw), DEC_BASE + 0x000005E4 */
  462. uint32_t isp_dec_write_buffer_base_26; /*!<(rw), DEC_BASE + 0x000005E8 */
  463. uint32_t isp_dec_write_buffer_base_27; /*!<(rw), DEC_BASE + 0x000005EC */
  464. uint32_t isp_dec_write_buffer_base_28; /*!<(rw), DEC_BASE + 0x000005F0 */
  465. uint32_t isp_dec_write_buffer_base_29; /*!<(rw), DEC_BASE + 0x000005F4 */
  466. uint32_t isp_dec_write_buffer_base_30; /*!<(rw), DEC_BASE + 0x000005F8 */
  467. uint32_t isp_dec_write_buffer_base_31; /*!<(rw), DEC_BASE + 0x000005FC */
  468. uint32_t isp_dec_write_buffer_base_ex_0; /*!<(rw), DEC_BASE + 0x00000600 */
  469. uint32_t isp_dec_write_buffer_base_ex_1; /*!<(rw), DEC_BASE + 0x00000604 */
  470. uint32_t isp_dec_write_buffer_base_ex_2; /*!<(rw), DEC_BASE + 0x00000608 */
  471. uint32_t isp_dec_write_buffer_base_ex_3; /*!<(rw), DEC_BASE + 0x0000060C */
  472. uint32_t isp_dec_write_buffer_base_ex_4; /*!<(rw), DEC_BASE + 0x00000610 */
  473. uint32_t isp_dec_write_buffer_base_ex_5; /*!<(rw), DEC_BASE + 0x00000614 */
  474. uint32_t isp_dec_write_buffer_base_ex_6; /*!<(rw), DEC_BASE + 0x00000618 */
  475. uint32_t isp_dec_write_buffer_base_ex_7; /*!<(rw), DEC_BASE + 0x0000061C */
  476. uint32_t isp_dec_write_buffer_base_ex_8; /*!<(rw), DEC_BASE + 0x00000620 */
  477. uint32_t isp_dec_write_buffer_base_ex_9; /*!<(rw), DEC_BASE + 0x00000624 */
  478. uint32_t isp_dec_write_buffer_base_ex_10; /*!<(rw), DEC_BASE + 0x00000628 */
  479. uint32_t isp_dec_write_buffer_base_ex_11; /*!<(rw), DEC_BASE + 0x0000062C */
  480. uint32_t isp_dec_write_buffer_base_ex_12; /*!<(rw), DEC_BASE + 0x00000630 */
  481. uint32_t isp_dec_write_buffer_base_ex_13; /*!<(rw), DEC_BASE + 0x00000634 */
  482. uint32_t isp_dec_write_buffer_base_ex_14; /*!<(rw), DEC_BASE + 0x00000638 */
  483. uint32_t isp_dec_write_buffer_base_ex_15; /*!<(rw), DEC_BASE + 0x0000063C */
  484. uint32_t isp_dec_write_buffer_base_ex_16; /*!<(rw), DEC_BASE + 0x00000640 */
  485. uint32_t isp_dec_write_buffer_base_ex_17; /*!<(rw), DEC_BASE + 0x00000644 */
  486. uint32_t isp_dec_write_buffer_base_ex_18; /*!<(rw), DEC_BASE + 0x00000648 */
  487. uint32_t isp_dec_write_buffer_base_ex_19; /*!<(rw), DEC_BASE + 0x0000064C */
  488. uint32_t isp_dec_write_buffer_base_ex_20; /*!<(rw), DEC_BASE + 0x00000650 */
  489. uint32_t isp_dec_write_buffer_base_ex_21; /*!<(rw), DEC_BASE + 0x00000654 */
  490. uint32_t isp_dec_write_buffer_base_ex_22; /*!<(rw), DEC_BASE + 0x00000658 */
  491. uint32_t isp_dec_write_buffer_base_ex_23; /*!<(rw), DEC_BASE + 0x0000065C */
  492. uint32_t isp_dec_write_buffer_base_ex_24; /*!<(rw), DEC_BASE + 0x00000660 */
  493. uint32_t isp_dec_write_buffer_base_ex_25; /*!<(rw), DEC_BASE + 0x00000664 */
  494. uint32_t isp_dec_write_buffer_base_ex_26; /*!<(rw), DEC_BASE + 0x00000668 */
  495. uint32_t isp_dec_write_buffer_base_ex_27; /*!<(rw), DEC_BASE + 0x0000066C */
  496. uint32_t isp_dec_write_buffer_base_ex_28; /*!<(rw), DEC_BASE + 0x00000670 */
  497. uint32_t isp_dec_write_buffer_base_ex_29; /*!<(rw), DEC_BASE + 0x00000674 */
  498. uint32_t isp_dec_write_buffer_base_ex_30; /*!<(rw), DEC_BASE + 0x00000678 */
  499. uint32_t isp_dec_write_buffer_base_ex_31; /*!<(rw), DEC_BASE + 0x0000067C */
  500. uint32_t isp_dec_write_buffer_end_0; /*!<(rw), DEC_BASE + 0x00000680 */
  501. uint32_t isp_dec_write_buffer_end_1; /*!<(rw), DEC_BASE + 0x00000684 */
  502. uint32_t isp_dec_write_buffer_end_2; /*!<(rw), DEC_BASE + 0x00000688 */
  503. uint32_t isp_dec_write_buffer_end_3; /*!<(rw), DEC_BASE + 0x0000068C */
  504. uint32_t isp_dec_write_buffer_end_4; /*!<(rw), DEC_BASE + 0x00000690 */
  505. uint32_t isp_dec_write_buffer_end_5; /*!<(rw), DEC_BASE + 0x00000694 */
  506. uint32_t isp_dec_write_buffer_end_6; /*!<(rw), DEC_BASE + 0x00000698 */
  507. uint32_t isp_dec_write_buffer_end_7; /*!<(rw), DEC_BASE + 0x0000069C */
  508. uint32_t isp_dec_write_buffer_end_8; /*!<(rw), DEC_BASE + 0x000006A0 */
  509. uint32_t isp_dec_write_buffer_end_9; /*!<(rw), DEC_BASE + 0x000006A4 */
  510. uint32_t isp_dec_write_buffer_end_10; /*!<(rw), DEC_BASE + 0x000006A8 */
  511. uint32_t isp_dec_write_buffer_end_11; /*!<(rw), DEC_BASE + 0x000006AC */
  512. uint32_t isp_dec_write_buffer_end_12; /*!<(rw), DEC_BASE + 0x000006B0 */
  513. uint32_t isp_dec_write_buffer_end_13; /*!<(rw), DEC_BASE + 0x000006B4 */
  514. uint32_t isp_dec_write_buffer_end_14; /*!<(rw), DEC_BASE + 0x000006B8 */
  515. uint32_t isp_dec_write_buffer_end_15; /*!<(rw), DEC_BASE + 0x000006BC */
  516. uint32_t isp_dec_write_buffer_end_16; /*!<(rw), DEC_BASE + 0x000006C0 */
  517. uint32_t isp_dec_write_buffer_end_17; /*!<(rw), DEC_BASE + 0x000006C4 */
  518. uint32_t isp_dec_write_buffer_end_18; /*!<(rw), DEC_BASE + 0x000006C8 */
  519. uint32_t isp_dec_write_buffer_end_19; /*!<(rw), DEC_BASE + 0x000006CC */
  520. uint32_t isp_dec_write_buffer_end_20; /*!<(rw), DEC_BASE + 0x000006D0 */
  521. uint32_t isp_dec_write_buffer_end_21; /*!<(rw), DEC_BASE + 0x000006D4 */
  522. uint32_t isp_dec_write_buffer_end_22; /*!<(rw), DEC_BASE + 0x000006D8 */
  523. uint32_t isp_dec_write_buffer_end_23; /*!<(rw), DEC_BASE + 0x000006DC */
  524. uint32_t isp_dec_write_buffer_end_24; /*!<(rw), DEC_BASE + 0x000006E0 */
  525. uint32_t isp_dec_write_buffer_end_25; /*!<(rw), DEC_BASE + 0x000006E4 */
  526. uint32_t isp_dec_write_buffer_end_26; /*!<(rw), DEC_BASE + 0x000006E8 */
  527. uint32_t isp_dec_write_buffer_end_27; /*!<(rw), DEC_BASE + 0x000006EC */
  528. uint32_t isp_dec_write_buffer_end_28; /*!<(rw), DEC_BASE + 0x000006F0 */
  529. uint32_t isp_dec_write_buffer_end_29; /*!<(rw), DEC_BASE + 0x000006F4 */
  530. uint32_t isp_dec_write_buffer_end_30; /*!<(rw), DEC_BASE + 0x000006F8 */
  531. uint32_t isp_dec_write_buffer_end_31; /*!<(rw), DEC_BASE + 0x000006FC */
  532. uint32_t isp_dec_write_buffer_end_ex_0; /*!<(rw), DEC_BASE + 0x00000700 */
  533. uint32_t isp_dec_write_buffer_end_ex_1; /*!<(rw), DEC_BASE + 0x00000704 */
  534. uint32_t isp_dec_write_buffer_end_ex_2; /*!<(rw), DEC_BASE + 0x00000708 */
  535. uint32_t isp_dec_write_buffer_end_ex_3; /*!<(rw), DEC_BASE + 0x0000070C */
  536. uint32_t isp_dec_write_buffer_end_ex_4; /*!<(rw), DEC_BASE + 0x00000710 */
  537. uint32_t isp_dec_write_buffer_end_ex_5; /*!<(rw), DEC_BASE + 0x00000714 */
  538. uint32_t isp_dec_write_buffer_end_ex_6; /*!<(rw), DEC_BASE + 0x00000718 */
  539. uint32_t isp_dec_write_buffer_end_ex_7; /*!<(rw), DEC_BASE + 0x0000071C */
  540. uint32_t isp_dec_write_buffer_end_ex_8; /*!<(rw), DEC_BASE + 0x00000720 */
  541. uint32_t isp_dec_write_buffer_end_ex_9; /*!<(rw), DEC_BASE + 0x00000724 */
  542. uint32_t isp_dec_write_buffer_end_ex_10; /*!<(rw), DEC_BASE + 0x00000728 */
  543. uint32_t isp_dec_write_buffer_end_ex_11; /*!<(rw), DEC_BASE + 0x0000072C */
  544. uint32_t isp_dec_write_buffer_end_ex_12; /*!<(rw), DEC_BASE + 0x00000730 */
  545. uint32_t isp_dec_write_buffer_end_ex_13; /*!<(rw), DEC_BASE + 0x00000734 */
  546. uint32_t isp_dec_write_buffer_end_ex_14; /*!<(rw), DEC_BASE + 0x00000738 */
  547. uint32_t isp_dec_write_buffer_end_ex_15; /*!<(rw), DEC_BASE + 0x0000073C */
  548. uint32_t isp_dec_write_buffer_end_ex_16; /*!<(rw), DEC_BASE + 0x00000740 */
  549. uint32_t isp_dec_write_buffer_end_ex_17; /*!<(rw), DEC_BASE + 0x00000744 */
  550. uint32_t isp_dec_write_buffer_end_ex_18; /*!<(rw), DEC_BASE + 0x00000748 */
  551. uint32_t isp_dec_write_buffer_end_ex_19; /*!<(rw), DEC_BASE + 0x0000074C */
  552. uint32_t isp_dec_write_buffer_end_ex_20; /*!<(rw), DEC_BASE + 0x00000750 */
  553. uint32_t isp_dec_write_buffer_end_ex_21; /*!<(rw), DEC_BASE + 0x00000754 */
  554. uint32_t isp_dec_write_buffer_end_ex_22; /*!<(rw), DEC_BASE + 0x00000758 */
  555. uint32_t isp_dec_write_buffer_end_ex_23; /*!<(rw), DEC_BASE + 0x0000075C */
  556. uint32_t isp_dec_write_buffer_end_ex_24; /*!<(rw), DEC_BASE + 0x00000760 */
  557. uint32_t isp_dec_write_buffer_end_ex_25; /*!<(rw), DEC_BASE + 0x00000764 */
  558. uint32_t isp_dec_write_buffer_end_ex_26; /*!<(rw), DEC_BASE + 0x00000768 */
  559. uint32_t isp_dec_write_buffer_end_ex_27; /*!<(rw), DEC_BASE + 0x0000076C */
  560. uint32_t isp_dec_write_buffer_end_ex_28; /*!<(rw), DEC_BASE + 0x00000770 */
  561. uint32_t isp_dec_write_buffer_end_ex_29; /*!<(rw), DEC_BASE + 0x00000774 */
  562. uint32_t isp_dec_write_buffer_end_ex_30; /*!<(rw), DEC_BASE + 0x00000778 */
  563. uint32_t isp_dec_write_buffer_end_ex_31; /*!<(rw), DEC_BASE + 0x0000077C */
  564. uint32_t isp_dec_write_flush_cache_0; /*!<(rw), DEC_BASE + 0x00000780 */
  565. uint32_t isp_dec_write_flush_cache_1; /*!<(rw), DEC_BASE + 0x00000784 */
  566. uint32_t isp_dec_write_flush_cache_2; /*!<(rw), DEC_BASE + 0x00000788 */
  567. uint32_t isp_dec_write_flush_cache_3; /*!<(rw), DEC_BASE + 0x0000078C */
  568. uint32_t isp_dec_write_flush_cache_4; /*!<(rw), DEC_BASE + 0x00000790 */
  569. uint32_t isp_dec_write_flush_cache_5; /*!<(rw), DEC_BASE + 0x00000794 */
  570. uint32_t isp_dec_write_flush_cache_6; /*!<(rw), DEC_BASE + 0x00000798 */
  571. uint32_t isp_dec_write_flush_cache_7; /*!<(rw), DEC_BASE + 0x0000079C */
  572. uint32_t isp_dec_write_flush_cache_8; /*!<(rw), DEC_BASE + 0x000007A0 */
  573. uint32_t isp_dec_write_flush_cache_9; /*!<(rw), DEC_BASE + 0x000007A4 */
  574. uint32_t isp_dec_write_flush_cache_10; /*!<(rw), DEC_BASE + 0x000007A8 */
  575. uint32_t isp_dec_write_flush_cache_11; /*!<(rw), DEC_BASE + 0x000007AC */
  576. uint32_t isp_dec_write_flush_cache_12; /*!<(rw), DEC_BASE + 0x000007B0 */
  577. uint32_t isp_dec_write_flush_cache_13; /*!<(rw), DEC_BASE + 0x000007B4 */
  578. uint32_t isp_dec_write_flush_cache_14; /*!<(rw), DEC_BASE + 0x000007B8 */
  579. uint32_t isp_dec_write_flush_cache_15; /*!<(rw), DEC_BASE + 0x000007BC */
  580. uint32_t isp_dec_write_flush_cache_16; /*!<(rw), DEC_BASE + 0x000007C0 */
  581. uint32_t isp_dec_write_flush_cache_17; /*!<(rw), DEC_BASE + 0x000007C4 */
  582. uint32_t isp_dec_write_flush_cache_18; /*!<(rw), DEC_BASE + 0x000007C8 */
  583. uint32_t isp_dec_write_flush_cache_19; /*!<(rw), DEC_BASE + 0x000007CC */
  584. uint32_t isp_dec_write_flush_cache_20; /*!<(rw), DEC_BASE + 0x000007D0 */
  585. uint32_t isp_dec_write_flush_cache_21; /*!<(rw), DEC_BASE + 0x000007D4 */
  586. uint32_t isp_dec_write_flush_cache_22; /*!<(rw), DEC_BASE + 0x000007D8 */
  587. uint32_t isp_dec_write_flush_cache_23; /*!<(rw), DEC_BASE + 0x000007DC */
  588. uint32_t isp_dec_write_flush_cache_24; /*!<(rw), DEC_BASE + 0x000007E0 */
  589. uint32_t isp_dec_write_flush_cache_25; /*!<(rw), DEC_BASE + 0x000007E4 */
  590. uint32_t isp_dec_write_flush_cache_26; /*!<(rw), DEC_BASE + 0x000007E8 */
  591. uint32_t isp_dec_write_flush_cache_27; /*!<(rw), DEC_BASE + 0x000007EC */
  592. uint32_t isp_dec_write_flush_cache_28; /*!<(rw), DEC_BASE + 0x000007F0 */
  593. uint32_t isp_dec_write_flush_cache_29; /*!<(rw), DEC_BASE + 0x000007F4 */
  594. uint32_t isp_dec_write_flush_cache_30; /*!<(rw), DEC_BASE + 0x000007F8 */
  595. uint32_t isp_dec_write_flush_cache_31; /*!<(rw), DEC_BASE + 0x000007FC */
  596. uint32_t isp_dec_write_flush_cache_ex_0; /*!<(rw), DEC_BASE + 0x00000800 */
  597. uint32_t isp_dec_write_flush_cache_ex_1; /*!<(rw), DEC_BASE + 0x00000804 */
  598. uint32_t isp_dec_write_flush_cache_ex_2; /*!<(rw), DEC_BASE + 0x00000808 */
  599. uint32_t isp_dec_write_flush_cache_ex_3; /*!<(rw), DEC_BASE + 0x0000080C */
  600. uint32_t isp_dec_write_flush_cache_ex_4; /*!<(rw), DEC_BASE + 0x00000810 */
  601. uint32_t isp_dec_write_flush_cache_ex_5; /*!<(rw), DEC_BASE + 0x00000814 */
  602. uint32_t isp_dec_write_flush_cache_ex_6; /*!<(rw), DEC_BASE + 0x00000818 */
  603. uint32_t isp_dec_write_flush_cache_ex_7; /*!<(rw), DEC_BASE + 0x0000081C */
  604. uint32_t isp_dec_write_flush_cache_ex_8; /*!<(rw), DEC_BASE + 0x00000820 */
  605. uint32_t isp_dec_write_flush_cache_ex_9; /*!<(rw), DEC_BASE + 0x00000824 */
  606. uint32_t isp_dec_write_flush_cache_ex_10; /*!<(rw), DEC_BASE + 0x00000828 */
  607. uint32_t isp_dec_write_flush_cache_ex_11; /*!<(rw), DEC_BASE + 0x0000082C */
  608. uint32_t isp_dec_write_flush_cache_ex_12; /*!<(rw), DEC_BASE + 0x00000830 */
  609. uint32_t isp_dec_write_flush_cache_ex_13; /*!<(rw), DEC_BASE + 0x00000834 */
  610. uint32_t isp_dec_write_flush_cache_ex_14; /*!<(rw), DEC_BASE + 0x00000838 */
  611. uint32_t isp_dec_write_flush_cache_ex_15; /*!<(rw), DEC_BASE + 0x0000083C */
  612. uint32_t isp_dec_write_flush_cache_ex_16; /*!<(rw), DEC_BASE + 0x00000840 */
  613. uint32_t isp_dec_write_flush_cache_ex_17; /*!<(rw), DEC_BASE + 0x00000844 */
  614. uint32_t isp_dec_write_flush_cache_ex_18; /*!<(rw), DEC_BASE + 0x00000848 */
  615. uint32_t isp_dec_write_flush_cache_ex_19; /*!<(rw), DEC_BASE + 0x0000084C */
  616. uint32_t isp_dec_write_flush_cache_ex_20; /*!<(rw), DEC_BASE + 0x00000850 */
  617. uint32_t isp_dec_write_flush_cache_ex_21; /*!<(rw), DEC_BASE + 0x00000854 */
  618. uint32_t isp_dec_write_flush_cache_ex_22; /*!<(rw), DEC_BASE + 0x00000858 */
  619. uint32_t isp_dec_write_flush_cache_ex_23; /*!<(rw), DEC_BASE + 0x0000085C */
  620. uint32_t isp_dec_write_flush_cache_ex_24; /*!<(rw), DEC_BASE + 0x00000860 */
  621. uint32_t isp_dec_write_flush_cache_ex_25; /*!<(rw), DEC_BASE + 0x00000864 */
  622. uint32_t isp_dec_write_flush_cache_ex_26; /*!<(rw), DEC_BASE + 0x00000868 */
  623. uint32_t isp_dec_write_flush_cache_ex_27; /*!<(rw), DEC_BASE + 0x0000086C */
  624. uint32_t isp_dec_write_flush_cache_ex_28; /*!<(rw), DEC_BASE + 0x00000870 */
  625. uint32_t isp_dec_write_flush_cache_ex_29; /*!<(rw), DEC_BASE + 0x00000874 */
  626. uint32_t isp_dec_write_flush_cache_ex_30; /*!<(rw), DEC_BASE + 0x00000878 */
  627. uint32_t isp_dec_write_flush_cache_ex_31; /*!<(rw), DEC_BASE + 0x0000087C */
  628. uint32_t isp_dec_read_cache_base_0; /*!<(rw), DEC_BASE + 0x00000880 */
  629. uint32_t isp_dec_read_cache_base_1; /*!<(rw), DEC_BASE + 0x00000884 */
  630. uint32_t isp_dec_read_cache_base_2; /*!<(rw), DEC_BASE + 0x00000888 */
  631. uint32_t isp_dec_read_cache_base_3; /*!<(rw), DEC_BASE + 0x0000088C */
  632. uint32_t isp_dec_read_cache_base_4; /*!<(rw), DEC_BASE + 0x00000890 */
  633. uint32_t isp_dec_read_cache_base_5; /*!<(rw), DEC_BASE + 0x00000894 */
  634. uint32_t isp_dec_read_cache_base_6; /*!<(rw), DEC_BASE + 0x00000898 */
  635. uint32_t isp_dec_read_cache_base_7; /*!<(rw), DEC_BASE + 0x0000089C */
  636. uint32_t isp_dec_read_cache_base_8; /*!<(rw), DEC_BASE + 0x000008A0 */
  637. uint32_t isp_dec_read_cache_base_9; /*!<(rw), DEC_BASE + 0x000008A4 */
  638. uint32_t isp_dec_read_cache_base_10; /*!<(rw), DEC_BASE + 0x000008A8 */
  639. uint32_t isp_dec_read_cache_base_11; /*!<(rw), DEC_BASE + 0x000008AC */
  640. uint32_t isp_dec_read_cache_base_12; /*!<(rw), DEC_BASE + 0x000008B0 */
  641. uint32_t isp_dec_read_cache_base_13; /*!<(rw), DEC_BASE + 0x000008B4 */
  642. uint32_t isp_dec_read_cache_base_14; /*!<(rw), DEC_BASE + 0x000008B8 */
  643. uint32_t isp_dec_read_cache_base_15; /*!<(rw), DEC_BASE + 0x000008BC */
  644. uint32_t isp_dec_read_cache_base_16; /*!<(rw), DEC_BASE + 0x000008C0 */
  645. uint32_t isp_dec_read_cache_base_17; /*!<(rw), DEC_BASE + 0x000008C4 */
  646. uint32_t isp_dec_read_cache_base_18; /*!<(rw), DEC_BASE + 0x000008C8 */
  647. uint32_t isp_dec_read_cache_base_19; /*!<(rw), DEC_BASE + 0x000008CC */
  648. uint32_t isp_dec_read_cache_base_20; /*!<(rw), DEC_BASE + 0x000008D0 */
  649. uint32_t isp_dec_read_cache_base_21; /*!<(rw), DEC_BASE + 0x000008D4 */
  650. uint32_t isp_dec_read_cache_base_22; /*!<(rw), DEC_BASE + 0x000008D8 */
  651. uint32_t isp_dec_read_cache_base_23; /*!<(rw), DEC_BASE + 0x000008DC */
  652. uint32_t isp_dec_read_cache_base_24; /*!<(rw), DEC_BASE + 0x000008E0 */
  653. uint32_t isp_dec_read_cache_base_25; /*!<(rw), DEC_BASE + 0x000008E4 */
  654. uint32_t isp_dec_read_cache_base_26; /*!<(rw), DEC_BASE + 0x000008E8 */
  655. uint32_t isp_dec_read_cache_base_27; /*!<(rw), DEC_BASE + 0x000008EC */
  656. uint32_t isp_dec_read_cache_base_28; /*!<(rw), DEC_BASE + 0x000008F0 */
  657. uint32_t isp_dec_read_cache_base_29; /*!<(rw), DEC_BASE + 0x000008F4 */
  658. uint32_t isp_dec_read_cache_base_30; /*!<(rw), DEC_BASE + 0x000008F8 */
  659. uint32_t isp_dec_read_cache_base_31; /*!<(rw), DEC_BASE + 0x000008FC */
  660. uint32_t isp_dec_read_cache_base_ex_0; /*!<(rw), DEC_BASE + 0x00000900 */
  661. uint32_t isp_dec_read_cache_base_ex_1; /*!<(rw), DEC_BASE + 0x00000904 */
  662. uint32_t isp_dec_read_cache_base_ex_2; /*!<(rw), DEC_BASE + 0x00000908 */
  663. uint32_t isp_dec_read_cache_base_ex_3; /*!<(rw), DEC_BASE + 0x0000090C */
  664. uint32_t isp_dec_read_cache_base_ex_4; /*!<(rw), DEC_BASE + 0x00000910 */
  665. uint32_t isp_dec_read_cache_base_ex_5; /*!<(rw), DEC_BASE + 0x00000914 */
  666. uint32_t isp_dec_read_cache_base_ex_6; /*!<(rw), DEC_BASE + 0x00000918 */
  667. uint32_t isp_dec_read_cache_base_ex_7; /*!<(rw), DEC_BASE + 0x0000091C */
  668. uint32_t isp_dec_read_cache_base_ex_8; /*!<(rw), DEC_BASE + 0x00000920 */
  669. uint32_t isp_dec_read_cache_base_ex_9; /*!<(rw), DEC_BASE + 0x00000924 */
  670. uint32_t isp_dec_read_cache_base_ex_10; /*!<(rw), DEC_BASE + 0x00000928 */
  671. uint32_t isp_dec_read_cache_base_ex_11; /*!<(rw), DEC_BASE + 0x0000092C */
  672. uint32_t isp_dec_read_cache_base_ex_12; /*!<(rw), DEC_BASE + 0x00000930 */
  673. uint32_t isp_dec_read_cache_base_ex_13; /*!<(rw), DEC_BASE + 0x00000934 */
  674. uint32_t isp_dec_read_cache_base_ex_14; /*!<(rw), DEC_BASE + 0x00000938 */
  675. uint32_t isp_dec_read_cache_base_ex_15; /*!<(rw), DEC_BASE + 0x0000093C */
  676. uint32_t isp_dec_read_cache_base_ex_16; /*!<(rw), DEC_BASE + 0x00000940 */
  677. uint32_t isp_dec_read_cache_base_ex_17; /*!<(rw), DEC_BASE + 0x00000944 */
  678. uint32_t isp_dec_read_cache_base_ex_18; /*!<(rw), DEC_BASE + 0x00000948 */
  679. uint32_t isp_dec_read_cache_base_ex_19; /*!<(rw), DEC_BASE + 0x0000094C */
  680. uint32_t isp_dec_read_cache_base_ex_20; /*!<(rw), DEC_BASE + 0x00000950 */
  681. uint32_t isp_dec_read_cache_base_ex_21; /*!<(rw), DEC_BASE + 0x00000954 */
  682. uint32_t isp_dec_read_cache_base_ex_22; /*!<(rw), DEC_BASE + 0x00000958 */
  683. uint32_t isp_dec_read_cache_base_ex_23; /*!<(rw), DEC_BASE + 0x0000095C */
  684. uint32_t isp_dec_read_cache_base_ex_24; /*!<(rw), DEC_BASE + 0x00000960 */
  685. uint32_t isp_dec_read_cache_base_ex_25; /*!<(rw), DEC_BASE + 0x00000964 */
  686. uint32_t isp_dec_read_cache_base_ex_26; /*!<(rw), DEC_BASE + 0x00000968 */
  687. uint32_t isp_dec_read_cache_base_ex_27; /*!<(rw), DEC_BASE + 0x0000096C */
  688. uint32_t isp_dec_read_cache_base_ex_28; /*!<(rw), DEC_BASE + 0x00000970 */
  689. uint32_t isp_dec_read_cache_base_ex_29; /*!<(rw), DEC_BASE + 0x00000974 */
  690. uint32_t isp_dec_read_cache_base_ex_30; /*!<(rw), DEC_BASE + 0x00000978 */
  691. uint32_t isp_dec_read_cache_base_ex_31; /*!<(rw), DEC_BASE + 0x0000097C */
  692. uint32_t isp_dec_write_cache_base_0; /*!<(rw), DEC_BASE + 0x00000980 */
  693. uint32_t isp_dec_write_cache_base_1; /*!<(rw), DEC_BASE + 0x00000984 */
  694. uint32_t isp_dec_write_cache_base_2; /*!<(rw), DEC_BASE + 0x00000988 */
  695. uint32_t isp_dec_write_cache_base_3; /*!<(rw), DEC_BASE + 0x0000098C */
  696. uint32_t isp_dec_write_cache_base_4; /*!<(rw), DEC_BASE + 0x00000990 */
  697. uint32_t isp_dec_write_cache_base_5; /*!<(rw), DEC_BASE + 0x00000994 */
  698. uint32_t isp_dec_write_cache_base_6; /*!<(rw), DEC_BASE + 0x00000998 */
  699. uint32_t isp_dec_write_cache_base_7; /*!<(rw), DEC_BASE + 0x0000099C */
  700. uint32_t isp_dec_write_cache_base_8; /*!<(rw), DEC_BASE + 0x000009A0 */
  701. uint32_t isp_dec_write_cache_base_9; /*!<(rw), DEC_BASE + 0x000009A4 */
  702. uint32_t isp_dec_write_cache_base_10; /*!<(rw), DEC_BASE + 0x000009A8 */
  703. uint32_t isp_dec_write_cache_base_11; /*!<(rw), DEC_BASE + 0x000009AC */
  704. uint32_t isp_dec_write_cache_base_12; /*!<(rw), DEC_BASE + 0x000009B0 */
  705. uint32_t isp_dec_write_cache_base_13; /*!<(rw), DEC_BASE + 0x000009B4 */
  706. uint32_t isp_dec_write_cache_base_14; /*!<(rw), DEC_BASE + 0x000009B8 */
  707. uint32_t isp_dec_write_cache_base_15; /*!<(rw), DEC_BASE + 0x000009BC */
  708. uint32_t isp_dec_write_cache_base_16; /*!<(rw), DEC_BASE + 0x000009C0 */
  709. uint32_t isp_dec_write_cache_base_17; /*!<(rw), DEC_BASE + 0x000009C4 */
  710. uint32_t isp_dec_write_cache_base_18; /*!<(rw), DEC_BASE + 0x000009C8 */
  711. uint32_t isp_dec_write_cache_base_19; /*!<(rw), DEC_BASE + 0x000009CC */
  712. uint32_t isp_dec_write_cache_base_20; /*!<(rw), DEC_BASE + 0x000009D0 */
  713. uint32_t isp_dec_write_cache_base_21; /*!<(rw), DEC_BASE + 0x000009D4 */
  714. uint32_t isp_dec_write_cache_base_22; /*!<(rw), DEC_BASE + 0x000009D8 */
  715. uint32_t isp_dec_write_cache_base_23; /*!<(rw), DEC_BASE + 0x000009DC */
  716. uint32_t isp_dec_write_cache_base_24; /*!<(rw), DEC_BASE + 0x000009E0 */
  717. uint32_t isp_dec_write_cache_base_25; /*!<(rw), DEC_BASE + 0x000009E4 */
  718. uint32_t isp_dec_write_cache_base_26; /*!<(rw), DEC_BASE + 0x000009E8 */
  719. uint32_t isp_dec_write_cache_base_27; /*!<(rw), DEC_BASE + 0x000009EC */
  720. uint32_t isp_dec_write_cache_base_28; /*!<(rw), DEC_BASE + 0x000009F0 */
  721. uint32_t isp_dec_write_cache_base_29; /*!<(rw), DEC_BASE + 0x000009F4 */
  722. uint32_t isp_dec_write_cache_base_30; /*!<(rw), DEC_BASE + 0x000009F8 */
  723. uint32_t isp_dec_write_cache_base_31; /*!<(rw), DEC_BASE + 0x000009FC */
  724. uint32_t isp_dec_write_cache_base_ex_0; /*!<(rw), DEC_BASE + 0x00000A00 */
  725. uint32_t isp_dec_write_cache_base_ex_1; /*!<(rw), DEC_BASE + 0x00000A04 */
  726. uint32_t isp_dec_write_cache_base_ex_2; /*!<(rw), DEC_BASE + 0x00000A08 */
  727. uint32_t isp_dec_write_cache_base_ex_3; /*!<(rw), DEC_BASE + 0x00000A0C */
  728. uint32_t isp_dec_write_cache_base_ex_4; /*!<(rw), DEC_BASE + 0x00000A10 */
  729. uint32_t isp_dec_write_cache_base_ex_5; /*!<(rw), DEC_BASE + 0x00000A14 */
  730. uint32_t isp_dec_write_cache_base_ex_6; /*!<(rw), DEC_BASE + 0x00000A18 */
  731. uint32_t isp_dec_write_cache_base_ex_7; /*!<(rw), DEC_BASE + 0x00000A1C */
  732. uint32_t isp_dec_write_cache_base_ex_8; /*!<(rw), DEC_BASE + 0x00000A20 */
  733. uint32_t isp_dec_write_cache_base_ex_9; /*!<(rw), DEC_BASE + 0x00000A24 */
  734. uint32_t isp_dec_write_cache_base_ex_10; /*!<(rw), DEC_BASE + 0x00000A28 */
  735. uint32_t isp_dec_write_cache_base_ex_11; /*!<(rw), DEC_BASE + 0x00000A2C */
  736. uint32_t isp_dec_write_cache_base_ex_12; /*!<(rw), DEC_BASE + 0x00000A30 */
  737. uint32_t isp_dec_write_cache_base_ex_13; /*!<(rw), DEC_BASE + 0x00000A34 */
  738. uint32_t isp_dec_write_cache_base_ex_14; /*!<(rw), DEC_BASE + 0x00000A38 */
  739. uint32_t isp_dec_write_cache_base_ex_15; /*!<(rw), DEC_BASE + 0x00000A3C */
  740. uint32_t isp_dec_write_cache_base_ex_16; /*!<(rw), DEC_BASE + 0x00000A40 */
  741. uint32_t isp_dec_write_cache_base_ex_17; /*!<(rw), DEC_BASE + 0x00000A44 */
  742. uint32_t isp_dec_write_cache_base_ex_18; /*!<(rw), DEC_BASE + 0x00000A48 */
  743. uint32_t isp_dec_write_cache_base_ex_19; /*!<(rw), DEC_BASE + 0x00000A4C */
  744. uint32_t isp_dec_write_cache_base_ex_20; /*!<(rw), DEC_BASE + 0x00000A50 */
  745. uint32_t isp_dec_write_cache_base_ex_21; /*!<(rw), DEC_BASE + 0x00000A54 */
  746. uint32_t isp_dec_write_cache_base_ex_22; /*!<(rw), DEC_BASE + 0x00000A58 */
  747. uint32_t isp_dec_write_cache_base_ex_23; /*!<(rw), DEC_BASE + 0x00000A5C */
  748. uint32_t isp_dec_write_cache_base_ex_24; /*!<(rw), DEC_BASE + 0x00000A60 */
  749. uint32_t isp_dec_write_cache_base_ex_25; /*!<(rw), DEC_BASE + 0x00000A64 */
  750. uint32_t isp_dec_write_cache_base_ex_26; /*!<(rw), DEC_BASE + 0x00000A68 */
  751. uint32_t isp_dec_write_cache_base_ex_27; /*!<(rw), DEC_BASE + 0x00000A6C */
  752. uint32_t isp_dec_write_cache_base_ex_28; /*!<(rw), DEC_BASE + 0x00000A70 */
  753. uint32_t isp_dec_write_cache_base_ex_29; /*!<(rw), DEC_BASE + 0x00000A74 */
  754. uint32_t isp_dec_write_cache_base_ex_30; /*!<(rw), DEC_BASE + 0x00000A78 */
  755. uint32_t isp_dec_write_cache_base_ex_31; /*!<(rw), DEC_BASE + 0x00000A7C */
  756. uint32_t isp_dec_debug_info_out; /*!<(ro), DEC_BASE + 0x00000A80 */
  757. uint32_t isp_dec_debug_0; /*!<(ro), DEC_BASE + 0x00000A84 */
  758. uint32_t isp_dec_debug_1; /*!<(ro), DEC_BASE + 0x00000A88 */
  759. uint32_t isp_dec_debug_2; /*!<(ro), DEC_BASE + 0x00000A8C */
  760. uint32_t isp_dec_debug_3; /*!<(ro), DEC_BASE + 0x00000A90 */
  761. uint32_t isp_dec_debug_4; /*!<(ro), DEC_BASE + 0x00000A94 */
  762. uint32_t isp_dec_debug_5; /*!<(ro), DEC_BASE + 0x00000A98 */
  763. uint32_t isp_dec_state_commit; /*!<(ro), DEC_BASE + 0x00000A9C */
  764. uint32_t isp_dec_debug_6; /*!<(ro), DEC_BASE + 0x00000AA0 */
  765. uint32_t isp_dec_debug_7; /*!<(ro), DEC_BASE + 0x00000AA4 */
  766. uint32_t isp_dec_tile_128_type_0; /*!<(ro), DEC_BASE + 0x00000AA8 */
  767. uint32_t isp_dec_tile_128_type_1; /*!<(ro), DEC_BASE + 0x00000AAC */
  768. uint32_t isp_dec_tile_128_type_2; /*!<(ro), DEC_BASE + 0x00000AB0 */
  769. uint32_t isp_dec_tile_128_type_3; /*!<(ro), DEC_BASE + 0x00000AB4 */
  770. uint32_t isp_dec_tile_256_type_0; /*!<(ro), DEC_BASE + 0x00000AB8 */
  771. uint32_t isp_dec_tile_256_type_1; /*!<(ro), DEC_BASE + 0x00000ABC */
  772. uint32_t isp_dec_tile_256_type_2; /*!<(ro), DEC_BASE + 0x00000AC0 */
  773. uint32_t isp_dec_tile_256_type_3; /*!<(ro), DEC_BASE + 0x00000AC4 */
  774. uint32_t isp_dec_tile_256_type_4; /*!<(ro), DEC_BASE + 0x00000AC8 */
  775. uint32_t isp_dec_tile_256_type_5; /*!<(ro), DEC_BASE + 0x00000ACC */
  776. uint32_t isp_dec_tile_256_type_6; /*!<(ro), DEC_BASE + 0x00000AD0 */
  777. uint32_t isp_dec_tile_256_type_7; /*!<(ro), DEC_BASE + 0x00000AD4 */
  778. uint32_t isp_dec_debug_read_gate_domain_clk_counter; /*!<(ro), DEC_BASE + 0x00000AD8 */
  779. uint32_t isp_dec_debug_write_gate_domain_clk_counter; /*!<(ro), DEC_BASE + 0x00000ADC */
  780. uint32_t isp_dec_debug_other_gate_domain_clk_counter; /*!<(ro), DEC_BASE + 0x00000AE0 */
  781. uint32_t isp_dec_fast_clear_value_0; /*!<(rw), DEC_BASE + 0x00000B00 */
  782. uint32_t isp_dec_fast_clear_value_1; /*!<(rw), DEC_BASE + 0x00000B04 */
  783. uint32_t isp_dec_fast_clear_value_2; /*!<(rw), DEC_BASE + 0x00000B08 */
  784. uint32_t isp_dec_fast_clear_value_3; /*!<(rw), DEC_BASE + 0x00000B0C */
  785. uint32_t isp_dec_fast_clear_value_4; /*!<(rw), DEC_BASE + 0x00000B10 */
  786. uint32_t isp_dec_fast_clear_value_5; /*!<(rw), DEC_BASE + 0x00000B14 */
  787. uint32_t isp_dec_fast_clear_value_6; /*!<(rw), DEC_BASE + 0x00000B18 */
  788. uint32_t isp_dec_fast_clear_value_7; /*!<(rw), DEC_BASE + 0x00000B1C */
  789. uint32_t isp_dec_fast_clear_value_8; /*!<(rw), DEC_BASE + 0x00000B20 */
  790. uint32_t isp_dec_fast_clear_value_9; /*!<(rw), DEC_BASE + 0x00000B24 */
  791. uint32_t isp_dec_fast_clear_value_10; /*!<(rw), DEC_BASE + 0x00000B28 */
  792. uint32_t isp_dec_fast_clear_value_11; /*!<(rw), DEC_BASE + 0x00000B2C */
  793. uint32_t isp_dec_fast_clear_value_12; /*!<(rw), DEC_BASE + 0x00000B30 */
  794. uint32_t isp_dec_fast_clear_value_13; /*!<(rw), DEC_BASE + 0x00000B34 */
  795. uint32_t isp_dec_fast_clear_value_14; /*!<(rw), DEC_BASE + 0x00000B38 */
  796. uint32_t isp_dec_fast_clear_value_15; /*!<(rw), DEC_BASE + 0x00000B3C */
  797. uint32_t isp_dec_fast_clear_value_16; /*!<(rw), DEC_BASE + 0x00000B40 */
  798. uint32_t isp_dec_fast_clear_value_17; /*!<(rw), DEC_BASE + 0x00000B44 */
  799. uint32_t isp_dec_fast_clear_value_18; /*!<(rw), DEC_BASE + 0x00000B48 */
  800. uint32_t isp_dec_fast_clear_value_19; /*!<(rw), DEC_BASE + 0x00000B4C */
  801. uint32_t isp_dec_fast_clear_value_20; /*!<(rw), DEC_BASE + 0x00000B50 */
  802. uint32_t isp_dec_fast_clear_value_21; /*!<(rw), DEC_BASE + 0x00000B54 */
  803. uint32_t isp_dec_fast_clear_value_22; /*!<(rw), DEC_BASE + 0x00000B58 */
  804. uint32_t isp_dec_fast_clear_value_23; /*!<(rw), DEC_BASE + 0x00000B5C */
  805. uint32_t isp_dec_fast_clear_value_24; /*!<(rw), DEC_BASE + 0x00000B60 */
  806. uint32_t isp_dec_fast_clear_value_25; /*!<(rw), DEC_BASE + 0x00000B64 */
  807. uint32_t isp_dec_fast_clear_value_26; /*!<(rw), DEC_BASE + 0x00000B68 */
  808. uint32_t isp_dec_fast_clear_value_27; /*!<(rw), DEC_BASE + 0x00000B6C */
  809. uint32_t isp_dec_fast_clear_value_28; /*!<(rw), DEC_BASE + 0x00000B70 */
  810. uint32_t isp_dec_fast_clear_value_29; /*!<(rw), DEC_BASE + 0x00000B74 */
  811. uint32_t isp_dec_fast_clear_value_30; /*!<(rw), DEC_BASE + 0x00000B78 */
  812. uint32_t isp_dec_fast_clear_value_31; /*!<(rw), DEC_BASE + 0x00000B7C */
  813. uint32_t isp_dec_fast_clear_value_ex_0; /*!<(rw), DEC_BASE + 0x00000B80 */
  814. uint32_t isp_dec_fast_clear_value_ex_1; /*!<(rw), DEC_BASE + 0x00000B84 */
  815. uint32_t isp_dec_fast_clear_value_ex_2; /*!<(rw), DEC_BASE + 0x00000B88 */
  816. uint32_t isp_dec_fast_clear_value_ex_3; /*!<(rw), DEC_BASE + 0x00000B8C */
  817. uint32_t isp_dec_fast_clear_value_ex_4; /*!<(rw), DEC_BASE + 0x00000B90 */
  818. uint32_t isp_dec_fast_clear_value_ex_5; /*!<(rw), DEC_BASE + 0x00000B94 */
  819. uint32_t isp_dec_fast_clear_value_ex_6; /*!<(rw), DEC_BASE + 0x00000B98 */
  820. uint32_t isp_dec_fast_clear_value_ex_7; /*!<(rw), DEC_BASE + 0x00000B9C */
  821. uint32_t isp_dec_fast_clear_value_ex_8; /*!<(rw), DEC_BASE + 0x00000BA0 */
  822. uint32_t isp_dec_fast_clear_value_ex_9; /*!<(rw), DEC_BASE + 0x00000BA4 */
  823. uint32_t isp_dec_fast_clear_value_ex_10; /*!<(rw), DEC_BASE + 0x00000BA8 */
  824. uint32_t isp_dec_fast_clear_value_ex_11; /*!<(rw), DEC_BASE + 0x00000BAC */
  825. uint32_t isp_dec_fast_clear_value_ex_12; /*!<(rw), DEC_BASE + 0x00000BB0 */
  826. uint32_t isp_dec_fast_clear_value_ex_13; /*!<(rw), DEC_BASE + 0x00000BB4 */
  827. uint32_t isp_dec_fast_clear_value_ex_14; /*!<(rw), DEC_BASE + 0x00000BB8 */
  828. uint32_t isp_dec_fast_clear_value_ex_15; /*!<(rw), DEC_BASE + 0x00000BBC */
  829. uint32_t isp_dec_fast_clear_value_ex_16; /*!<(rw), DEC_BASE + 0x00000BC0 */
  830. uint32_t isp_dec_fast_clear_value_ex_17; /*!<(rw), DEC_BASE + 0x00000BC4 */
  831. uint32_t isp_dec_fast_clear_value_ex_18; /*!<(rw), DEC_BASE + 0x00000BC8 */
  832. uint32_t isp_dec_fast_clear_value_ex_19; /*!<(rw), DEC_BASE + 0x00000BCC */
  833. uint32_t isp_dec_fast_clear_value_ex_20; /*!<(rw), DEC_BASE + 0x00000BD0 */
  834. uint32_t isp_dec_fast_clear_value_ex_21; /*!<(rw), DEC_BASE + 0x00000BD4 */
  835. uint32_t isp_dec_fast_clear_value_ex_22; /*!<(rw), DEC_BASE + 0x00000BD8 */
  836. uint32_t isp_dec_fast_clear_value_ex_23; /*!<(rw), DEC_BASE + 0x00000BDC */
  837. uint32_t isp_dec_fast_clear_value_ex_24; /*!<(rw), DEC_BASE + 0x00000BE0 */
  838. uint32_t isp_dec_fast_clear_value_ex_25; /*!<(rw), DEC_BASE + 0x00000BE4 */
  839. uint32_t isp_dec_fast_clear_value_ex_26; /*!<(rw), DEC_BASE + 0x00000BE8 */
  840. uint32_t isp_dec_fast_clear_value_ex_27; /*!<(rw), DEC_BASE + 0x00000BEC */
  841. uint32_t isp_dec_fast_clear_value_ex_28; /*!<(rw), DEC_BASE + 0x00000BF0 */
  842. uint32_t isp_dec_fast_clear_value_ex_29; /*!<(rw), DEC_BASE + 0x00000BF4 */
  843. uint32_t isp_dec_fast_clear_value_ex_30; /*!<(rw), DEC_BASE + 0x00000BF8 */
  844. uint32_t isp_dec_fast_clear_value_ex_31; /*!<(rw), DEC_BASE + 0x00000BFC */
  845. } MrvDecAllRegister_t;
  846. /*! Register: isp_dec_ctrl (DEC_BASE + 0x00000000)*/
  847. /*! Slice: isp_dec_ctrl_flush:*/
  848. #define DEC_CTRL_FLUSH
  849. #define DEC_CTRL_FLUSH_MASK 0x00000001U
  850. #define DEC_CTRL_FLUSH_SHIFT 0U
  851. /*! Slice: isp_dec_ctrl_disable_compression:*/
  852. #define DEC_CTRL_DISABLE_COMPRESSION
  853. #define DEC_CTRL_DISABLE_COMPRESSION_MASK 0x00000002U
  854. #define DEC_CTRL_DISABLE_COMPRESSION_SHIFT 1U
  855. /*! Slice: isp_dec_ctrl_disable_ram_clock_gating:*/
  856. #define DEC_CTRL_DISABLE_RAM_CLOCK_GATING
  857. #define DEC_CTRL_DISABLE_RAM_CLOCK_GATING_MASK 0x00000004U
  858. #define DEC_CTRL_DISABLE_RAM_CLOCK_GATING_SHIFT 2U
  859. /*! Slice: isp_dec_ctrl_disable_debug_registers:*/
  860. #define DEC_CTRL_DISABLE_DEBUG_REGISTERS
  861. #define DEC_CTRL_DISABLE_DEBUG_REGISTERS_MASK 0x00000008U
  862. #define DEC_CTRL_DISABLE_DEBUG_REGISTERS_SHIFT 3U
  863. /*! Slice: isp_dec_ctrl_soft_reset:*/
  864. #define DEC_CTRL_SOFT_RESET
  865. #define DEC_CTRL_SOFT_RESET_MASK 0x00000010U
  866. #define DEC_CTRL_SOFT_RESET_SHIFT 4U
  867. /*! Slice: isp_dec_ctrl_flush_dcache:*/
  868. #define DEC_CTRL_FLUSH_DCACHE
  869. #define DEC_CTRL_FLUSH_DCACHE_MASK 0x00000040U
  870. #define DEC_CTRL_FLUSH_DCACHE_SHIFT 6U
  871. /*! Slice: isp_dec_ctrl_disable_dcache:*/
  872. #define DEC_CTRL_DISABLE_DCACHE
  873. #define DEC_CTRL_DISABLE_DCACHE_MASK 0x00000080U
  874. #define DEC_CTRL_DISABLE_DCACHE_SHIFT 7U
  875. /*! Slice: isp_dec_ctrl_disable_hw_flush:*/
  876. #define DEC_CTRL_DISABLE_HW_FLUSH
  877. #define DEC_CTRL_DISABLE_HW_FLUSH_MASK 0x00010000U
  878. #define DEC_CTRL_DISABLE_HW_FLUSH_SHIFT 16U
  879. /*! Slice: isp_dec_ctrl_clk_dis:*/
  880. #define DEC_CTRL_CLK_DIS
  881. #define DEC_CTRL_CLK_DIS_MASK 0x00FC0000U
  882. #define DEC_CTRL_CLK_DIS_SHIFT 17U
  883. /*! Slice: isp_dec_ctrl_sw_flush_id:*/
  884. #define DEC_CTRL_SW_FLUSH_ID
  885. #define DEC_CTRL_SW_FLUSH_ID_MASK 0x00020000U
  886. #define DEC_CTRL_SW_FLUSH_ID_SHIFT 18U
  887. /*! Slice: isp_dec_ctrl_disable_cache_prefetch:*/
  888. #define DEC_CTRL_DISABLE_CACHE_PREFETCH
  889. #define DEC_CTRL_DISABLE_CACHE_PREFETCH_MASK 0x02000000U
  890. #define DEC_CTRL_DISABLE_CACHE_PREFETCH_SHIFT 25U
  891. /*! Slice: isp_dec_ctrl_hw_update_shadow_reg_mode:*/
  892. #define DEC_CTRL_HW_UPDATE_SHADOW_REG_MODE
  893. #define DEC_CTRL_HW_UPDATE_SHADOW_REG_MODE_MASK 0x10000000U
  894. #define DEC_CTRL_HW_UPDATE_SHADOW_REG_MODE_SHIFT 28U
  895. /*! Slice: isp_dec_ctrl_soft_update_shadow_reg:*/
  896. #define DEC_CTRL_SOFT_UPDATE_SHADOW_REG
  897. #define DEC_CTRL_SOFT_UPDATE_SHADOW_REG_MASK 0x20000000U
  898. #define DEC_CTRL_SOFT_UPDATE_SHADOW_REG_SHIFT 29U
  899. /*! Slice: isp_dec_ctrl_disable_module_clock_gating:*/
  900. #define DEC_CTRL_DISABLE_MODULE_CLOCK_GATING
  901. #define DEC_CTRL_DISABLE_MODULE_CLOCK_GATING_MASK 0x40000000U
  902. #define DEC_CTRL_DISABLE_MODULE_CLOCK_GATING_SHIFT 30U
  903. /*! Slice: isp_dec_ctrl_disable_global_clock_gating:*/
  904. #define DEC_CTRL_DISABLE_GLOBAL_CLOCK_GATING
  905. #define DEC_CTRL_DISABLE_GLOBAL_CLOCK_GATING_MASK 0x80000000U
  906. #define DEC_CTRL_DISABLE_GLOBAL_CLOCK_GATING_SHIFT 31U
  907. /*! Register: isp_dec_ctrl_ex (DEC_BASE + 0x00000004)*/
  908. /*! Slice: isp_dec_ctrl_ex_enable_burst_split:*/
  909. #define DEC_CTRL_EX_ENABLE_BURST_SPLIT
  910. #define DEC_CTRL_EX_ENABLE_BURST_SPLIT_MASK 0x00010000U
  911. #define DEC_CTRL_EX_ENABLE_BURST_SPLIT_SHIFT 16U
  912. /*! Slice: isp_dec_ctrl_ex_enable_end_address_check:*/
  913. #define DEC_CTRL_EX_ENABLE_END_ADDRESS_RANGE_CHECK
  914. #define DEC_CTRL_EX_ENABLE_END_ADDRESS_RANGE_CHECK_MASK 0x00020000U
  915. #define DEC_CTRL_EX_ENABLE_END_ADDRESS_RANGE_CHECK_SHIFT 17U
  916. /*! Slice: isp_dec_ctrl_ex_write_miss_policy:*/
  917. #define DEC_CTRL_EX_WRITE_MISS_POLICY
  918. #define DEC_CTRL_EX_WRITE_MISS_POLICY_MASK 0x00080000U
  919. #define DEC_CTRL_EX_WRITE_MISS_POLICY_SHIFT 19U
  920. /*! Slice: isp_dec_ctrl_ex_read_miss_policy:*/
  921. #define DEC_CTRL_EX_READ_MISS_POLICY
  922. #define DEC_CTRL_EX_READ_MISS_POLICY_MASK 0x20000000U
  923. #define DEC_CTRL_EX_READ_MISS_POLICY_SHIFT 29U
  924. /*! Register: isp_dec_ctrl_ex2 (DEC_BASE + 0x00000008)*/
  925. /*! Slice: isp_dec_ctrl_ex2_tile_status_read_id:*/
  926. #define DEC_CTRL_EX2_TILE_STATUS_READ_ID
  927. #define DEC_CTRL_EX2_TILE_STATUS_READ_ID_MASK 0x0000007FU
  928. #define DEC_CTRL_EX2_TILE_STATUS_READ_ID_SHIFT 0U
  929. /*! Slice: isp_dec_ctrl_ex2_tile_status_write_id:*/
  930. #define DEC_CTRL_EX2_TILE_STATUS_WRITE_ID
  931. #define DEC_CTRL_EX2_TILE_STATUS_WRITE_ID_MASK 0x0003F80U
  932. #define DEC_CTRL_EX2_TILE_STATUS_WRITE_ID_SHIFT 7U
  933. /*! Register: isp_dec_intr_enbl (DEC_BASE + 0x0000000C)*/
  934. /*! Slice: isp_dec_intr_enbl_vec:*/
  935. #define DEC_INTR_ENBL_VEC
  936. #define DEC_INTR_ENBL_VEC_MASK 0xFFFFFFFFU
  937. #define DEC_INTR_ENBL_VEC_SHIFT 0U
  938. /*! Register: isp_dec_intr_enbl_ex (DEC_BASE + 0x00000010)*/
  939. /*! Slice: isp_dec_intr_enbl_ex_vec:*/
  940. #define DEC_INTR_ENBL_EX_VEC
  941. #define DEC_INTR_ENBL_EX_VEC_MASK 0xFFFFFFFFU
  942. #define DEC_INTR_ENBL_EX_VEC_SHIFT 0U
  943. /*! Register: isp_dec_intr_enbl_ex2 (DEC_BASE + 0x00000014)*/
  944. /*! Slice: isp_dec_intr_enbl_ex2_vec:*/
  945. #define DEC_INTR_ENBL_EX2_VEC
  946. #define DEC_INTR_ENBL_EX2_VEC_MASK 0xFFFFFFFFU
  947. #define DEC_INTR_ENBL_EX2_VEC_SHIFT 0U
  948. /*! Register: isp_dec_read_config (DEC_BASE + 0x00000080)*/
  949. /*! Slice: isp_dec_read_config_compression_enable:*/
  950. #define DEC_READ_CONFIG_COMPRESSION_ENABLE
  951. #define DEC_READ_CONFIG_COMPRESSION_ENABLE_MASK 0x00000001U
  952. #define DEC_READ_CONFIG_COMPRESSION_ENABLE_SHIFT 0U
  953. /*! Slice: isp_dec_read_config_compression_format:*/
  954. #define DEC_READ_CONFIG_COMPRESSION_FORMAT
  955. #define DEC_READ_CONFIG_COMPRESSION_FORMAT_MASK 0x000000F8U
  956. #define DEC_READ_CONFIG_COMPRESSION_FORMAT_SHIFT 3U
  957. /*! Slice: isp_dec_read_config_compression_align_mode:*/
  958. #define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE
  959. #define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE_MASK 0x00030000U
  960. #define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE_SHIFT 16U
  961. /*! Slice: isp_dec_read_config_compression_align_mode1:*/
  962. #define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE1
  963. #define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE1_MASK 0x001C0000U
  964. #define DEC_READ_CONFIG_COMPRESSION_ALIGN_MODE1_SHIFT 18U
  965. /*! Slice: isp_dec_read_config_tile_mode:*/
  966. #define DEC_READ_CONFIG_TILE_MODE
  967. #define DEC_READ_CONFIG_TILE_MODE_MASK 0x7E000000U
  968. #define DEC_READ_CONFIG_TILE_MODE_SHIFT 25U
  969. /*! Register: isp_dec_read_ex_config (DEC_BASE + 0x00000100)*/
  970. /*! Slice: isp_dec_read_ex_config_bit_depth:*/
  971. #define DEC_READ_EX_CONFIG_BIT_DEPTH
  972. #define DEC_READ_EX_CONFIG_BIT_DEPTH_MASK 0x00070000U
  973. #define DEC_READ_EX_CONFIG_BIT_DEPTH_SHIFT 16U
  974. /*! Slice: isp_dec_read_ex_config_tile_y:*/
  975. #define DEC_READ_EX_CONFIG_TILE_Y
  976. #define DEC_READ_EX_CONFIG_TILE_Y_MASK 0x00080000U
  977. #define DEC_READ_EX_CONFIG_TILE_Y_SHIFT 19U
  978. /*! Register: isp_dec_write_config (DEC_BASE + 0x00000180)*/
  979. /*! Slice: isp_dec_write_config_compression_enable:*/
  980. #define DEC_WRITE_CONFIG_COMPRESSION_ENABLE
  981. #define DEC_WRITE_CONFIG_COMPRESSION_ENABLE_MASK 0x00000001U
  982. #define DEC_WRITE_CONFIG_COMPRESSION_ENABLE_SHIFT 0U
  983. /*! Slice: isp_dec_write_config_compression_format:*/
  984. #define DEC_WRITE_CONFIG_COMPRESSION_FORMAT
  985. #define DEC_WRITE_CONFIG_COMPRESSION_FORMAT_MASK 0x000000F8U
  986. #define DEC_WRITE_CONFIG_COMPRESSION_FORMAT_SHIFT 3U
  987. /*! Slice: isp_dec_write_config_compression_align_mode:*/
  988. #define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE
  989. #define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE_MASK 0x00030000U
  990. #define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE_SHIFT 16U
  991. /*! Slice: isp_dec_write_config_compression_align_mode1:*/
  992. #define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE1
  993. #define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE1_MASK 0x001C0000U
  994. #define DEC_WRITE_CONFIG_COMPRESSION_ALIGN_MODE1_SHIFT 18U
  995. /*! Slice: isp_dec_write_config_tile_mode:*/
  996. #define DEC_WRITE_CONFIG_TILE_MODE
  997. #define DEC_WRITE_CONFIG_TILE_MODE_MASK 0x7E000000U
  998. #define DEC_WRITE_CONFIG_TILE_MODE_SHIFT 25U
  999. /*! Register: isp_dec_write_ex_config (DEC_BASE + 0x00000200)*/
  1000. /*! Slice: isp_dec_write_ex_config_bit_depth:*/
  1001. #define DEC_WRITE_EX_CONFIG_BIT_DEPTH
  1002. #define DEC_WRITE_EX_CONFIG_BIT_DEPTH_MASK 0x00070000U
  1003. #define DEC_WRITE_EX_CONFIG_BIT_DEPTH_SHIFT 16U
  1004. /*! Slice: isp_dec_write_ex_config_tile_y:*/
  1005. #define DEC_WRITE_EX_CONFIG_TILE_Y
  1006. #define DEC_WRITE_EX_CONFIG_TILE_Y_MASK 0x00080000U
  1007. #define DEC_WRITE_EX_CONFIG_TILE_Y_SHIFT 19U
  1008. /*! Register: isp_dec_read_buffer_base (DEC_BASE + 0x00000280)*/
  1009. /*! Slice: isp_dec_read_buffer_base:*/
  1010. #define DEC_READ_BUFFER_BASE
  1011. #define DEC_READ_BUFFER_BASE_MASK 0xFFFFFFFFU
  1012. #define DEC_READ_BUFFER_BASE_SHIFT 0U
  1013. /*! Register: isp_dec_read_buffer_base_ex (DEC_BASE + 0x00000300)*/
  1014. /*! Slice: isp_dec_read_buffer_base_ex:*/
  1015. #define DEC_READ_BUFFER_BASE_EX
  1016. #define DEC_READ_BUFFER_BASE_EX_MASK 0x000000FFU
  1017. #define DEC_READ_BUFFER_BASE_EX_SHIFT 0U
  1018. /*! Register: isp_dec_read_buffer_end (DEC_BASE + 0x00000380)*/
  1019. /*! Slice: isp_dec_read_buffer_end:*/
  1020. #define DEC_READ_BUFFER_END
  1021. #define DEC_READ_BUFFER_END_MASK 0xFFFFFFFFU
  1022. #define DEC_READ_BUFFER_END_SHIFT 0U
  1023. /*! Register: isp_dec_read_buffer_end_ex (DEC_BASE + 0x00000400)*/
  1024. /*! Slice: isp_dec_read_buffer_end_ex:*/
  1025. #define DEC_READ_BUFFER_END_EX
  1026. #define DEC_READ_BUFFER_END_EX_MASK 0x000000FFU
  1027. #define DEC_READ_BUFFER_END_EX_SHIFT 0U
  1028. /*! Register: isp_dec_read_flush_cache (DEC_BASE + 0x00000480)*/
  1029. /*! Slice: isp_dec_read_flush_cache:*/
  1030. #define DEC_READ_FLUSH_CACHE
  1031. #define DEC_READ_FLUSH_CACHE_MASK 0xFFFFFFFFU
  1032. #define DEC_READ_FLUSH_CACHE_SHIFT 0U
  1033. /*! Register: isp_dec_read_flush_cache_ex (DEC_BASE + 0x00000500)*/
  1034. /*! Slice: isp_dec_read_flush_cache_ex:*/
  1035. #define DEC_READ_FLUSH_CACHE_EX
  1036. #define DEC_READ_FLUSH_CACHE_EX_MASK 0xFFFFFFFFU
  1037. #define DEC_READ_FLUSH_CACHE_EX_SHIFT 0U
  1038. /*! Register: isp_dec_write_buffer_base (DEC_BASE + 0x00000580)*/
  1039. /*! Slice: isp_dec_write_buffer_base:*/
  1040. #define DEC_WRITE_BUFFER_BASE
  1041. #define DEC_WRITE_BUFFER_BASE_MASK 0xFFFFFFFFU
  1042. #define DEC_WRITE_BUFFER_BASE_SHIFT 0U
  1043. /*! Register: isp_dec_write_buffer_base_ex (DEC_BASE + 0x00000600)*/
  1044. /*! Slice: isp_dec_write_buffer_base_ex:*/
  1045. #define DEC_WRITE_BUFFER_BASE_EX
  1046. #define DEC_WRITE_BUFFER_BASE_EX_MASK 0x000000FFU
  1047. #define DEC_WRITE_BUFFER_BASE_EX_SHIFT 0U
  1048. /*! Register: isp_dec_write_buffer_end (DEC_BASE + 0x00000680)*/
  1049. /*! Slice: isp_dec_write_buffer_end:*/
  1050. #define DEC_WRITE_BUFFER_END
  1051. #define DEC_WRITE_BUFFER_END_MASK 0xFFFFFFFFU
  1052. #define DEC_WRITE_BUFFER_END_SHIFT 0U
  1053. /*! Register: isp_dec_write_buffer_end_ex (DEC_BASE + 0x00000700)*/
  1054. /*! Slice: isp_dec_write_buffer_end_ex:*/
  1055. #define DEC_WRITE_BUFFER_END_EX
  1056. #define DEC_WRITE_BUFFER_END_EX_MASK 0x000000FFU
  1057. #define DEC_WRITE_BUFFER_END_EX_SHIFT 0U
  1058. /*! Register: isp_dec_write_flush_cache (DEC_BASE + 0x00000780)*/
  1059. /*! Slice: isp_dec_write_flush_cache:*/
  1060. #define DEC_WRITE_FLUSH_CACHE
  1061. #define DEC_WRITE_FLUSH_CACHE_MASK 0xFFFFFFFFU
  1062. #define DEC_WRITE_FLUSH_CACHE_SHIFT 0U
  1063. /*! Register: isp_dec_write_flush_cache_ex (DEC_BASE + 0x00000800)*/
  1064. /*! Slice: isp_dec_write_flush_cache_ex:*/
  1065. #define DEC_WRITE_FLUSH_CACHE_EX
  1066. #define DEC_WRITE_FLUSH_CACHE_EX_MASK 0xFFFFFFFFU
  1067. #define DEC_WRITE_FLUSH_CACHE_EX_SHIFT 0U
  1068. /*! Register: isp_dec_read_cache_base (DEC_BASE + 0x00000880)*/
  1069. /*! Slice: isp_dec_read_cache_base:*/
  1070. #define DEC_READ_CACHE_BASE
  1071. #define DEC_READ_CACHE_BASE_MASK 0xFFFFFFFFU
  1072. #define DEC_READ_CACHE_BASE_SHIFT 0U
  1073. /*! Register: isp_dec_read_cache_base_ex (DEC_BASE + 0x00000900)*/
  1074. /*! Slice: isp_dec_read_cache_base_ex:*/
  1075. #define DEC_READ_CACHE_BASE_EX
  1076. #define DEC_READ_CACHE_BASE_EX_MASK 0xFFFFFFFFU
  1077. #define DEC_READ_CACHE_BASE_EX_SHIFT 0U
  1078. /*! Register: isp_dec_write_cache_base (DEC_BASE + 0x00000980)*/
  1079. /*! Slice: isp_dec_write_cache_base:*/
  1080. #define DEC_WRITE_CACHE_BASE
  1081. #define DEC_WRITE_CACHE_BASE_MASK 0xFFFFFFFFU
  1082. #define DEC_WRITE_CACHE_BASE_SHIFT 0U
  1083. /*! Register: isp_dec_write_cache_base_ex (DEC_BASE + 0x00000A00)*/
  1084. /*! Slice: isp_dec_write_cache_base_ex:*/
  1085. #define DEC_WRITE_CACHE_BASE_EX
  1086. #define DEC_WRITE_CACHE_BASE_EX_MASK 0xFFFFFFFFU
  1087. #define DEC_WRITE_CACHE_BASE_EX_SHIFT 0U
  1088. #endif /* _MRV_DEC_DEC_ALL_REGS_H */