mrv_all_regs.h 864 KB

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  1. /*****************************************************************************
  2. *
  3. * Copyright 2013, Dream Chip Technologies GmbH. All rights reserved.
  4. *
  5. ****************************************************************************
  6. *
  7. * The MIT License (MIT)
  8. *
  9. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  10. *
  11. * Permission is hereby granted, free of charge, to any person obtaining a
  12. * copy of this software and associated documentation files (the "Software"),
  13. * to deal in the Software without restriction, including without limitation
  14. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  15. * and/or sell copies of the Software, and to permit persons to whom the
  16. * Software is furnished to do so, subject to the following conditions:
  17. *
  18. * The above copyright notice and this permission notice shall be included in
  19. * all copies or substantial portions of the Software.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  22. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  23. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  24. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  25. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  26. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  27. * DEALINGS IN THE SOFTWARE.
  28. *
  29. *****************************************************************************
  30. *
  31. * The GPL License (GPL)
  32. *
  33. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  34. *
  35. * This program is free software; you can redistribute it and/or
  36. * modify it under the terms of the GNU General Public License
  37. * as published by the Free Software Foundation; either version 2
  38. * of the License, or (at your option) any later version.
  39. *
  40. * This program is distributed in the hope that it will be useful,
  41. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  42. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  43. * GNU General Public License for more details.
  44. *
  45. * You should have received a copy of the GNU General Public License
  46. * along with this program;
  47. *
  48. *****************************************************************************
  49. *
  50. * Note: This software is released under dual MIT and GPL licenses. A
  51. * recipient may use this file under the terms of either the MIT license or
  52. * GPL License. If you wish to use only one license not the other, you can
  53. * indicate your decision by deleting one of the above license notices in your
  54. * version of this file.
  55. *
  56. *****************************************************************************/
  57. /*
  58. * NOTE: This file is automaticaly generated by sig of theflow Rev.: 1.1_dev_koehler.
  59. * Modifications can be lost.
  60. *
  61. *****************************************************************************/
  62. /**
  63. *-----------------------------------------------------------------------------
  64. * $HeadURL$
  65. * $Author$
  66. * $Rev$
  67. * $Date$
  68. *-----------------------------------------------------------------------------
  69. * @file mrv_all_regs.h
  70. *
  71. * <pre>
  72. *
  73. * Description:
  74. * This header file exports the module register structure and masks.
  75. * It should not be included directly by your driver/application, it will be
  76. * exported by the <TOP>_regs_io.h header file.
  77. *
  78. * </pre>
  79. */
  80. /*****************************************************************************/
  81. #ifndef _MRV_ALL_REGS_H
  82. #define _MRV_ALL_REGS_H
  83. /* Definitions of block register sizes */
  84. #define DEGAMMA_R_Y_BLOCK_ARR_SIZE 17
  85. #define DEGAMMA_G_Y_BLOCK_ARR_SIZE 17
  86. #define DEGAMMA_B_Y_BLOCK_ARR_SIZE 17
  87. #define CROSS_TALK_COEF_BLOCK_ARR_SIZE 9
  88. #define GAMMA_OUT_Y_BLOCK_ARR_SIZE 17
  89. #define HISTOGRAM_MEASUREMENT_RESULT_ARR_SIZE 16
  90. #define NLF_LOOKUP_TABLE_BLOCK_ARR_SIZE 17
  91. #define WDR_TONE_MAPPING_CURVE_Y_BLOCK_ARR_SIZE 33
  92. #define WDR_TONE_MAPPING_CURVE_Y_SHD_BLOCK_ARR_SIZE 33
  93. #define AWB_MEAS_ACCU_ARR_SIZE 24
  94. #define ISP64_HISTOGRAM_MEASUREMENT_RESULT_ARR_SIZE 32
  95. #define ISP_HDREXP_MEASUREMENT_RESULT_ARR_SIZE 25
  96. /*! degamma_r_y_block register layout */
  97. typedef struct {
  98. uint32_t isp_gamma_r_y; /*!< De-Gamma Curve definition y red (rw) MRV_ISP_BASE + 0x448 + (n*0x4) (n=0..16) */
  99. } degamma_r_y_block_t;
  100. /*! degamma_g_y_block register layout */
  101. typedef struct {
  102. uint32_t isp_gamma_g_y; /*!< De-Gamma Curve definition y green (rw) MRV_ISP_BASE + 0x490 + (n*0x4) (n=0..16) */
  103. } degamma_g_y_block_t;
  104. /*! degamma_b_y_block register layout */
  105. typedef struct {
  106. uint32_t isp_gamma_b_y; /*!< De-Gamma Curve definition y blue (rw) MRV_ISP_BASE + 0x4D8 + (n*0x4) (n=0..16) */
  107. } degamma_b_y_block_t;
  108. /*! cross_talk_coef_block register layout */
  109. typedef struct {
  110. uint32_t isp_ct_coeff; /*!< cross-talk configuration register (color correction matrix) (rw) MRV_ISP_BASE + 0x7A0 + (n*0x4) (n=0..8) */
  111. } cross_talk_coef_block_t;
  112. /*! gamma_out_y_block register layout */
  113. typedef struct {
  114. uint32_t isp_gamma_out_y; /*!< Gamma Out Curve definition y_ (rw) MRV_ISP_BASE + 0x7F0 + (n*0x4) (n=0..16) */
  115. } gamma_out_y_block_t;
  116. /*! histogram_measurement_result register layout */
  117. typedef struct {
  118. uint32_t isp_hist_bin; /*!< histogram measurement result bin (r) MRV_HIST_BASE + 0x2428 + (n*0x4) (n=0..15) */
  119. } histogram_measurement_result_t;
  120. /*! nlf_lookup_table_block register layout */
  121. typedef struct {
  122. uint32_t isp_dpf_nll_coeff; /*!< Noise Level Lookup Coefficient (rw) MRV_DPF_BASE + 0x2840 + (n*0x4) (n=0..16) */
  123. } nlf_lookup_table_block_t;
  124. /*! wdr_tone_mapping_curve_y_block register layout */
  125. typedef struct {
  126. uint32_t isp_wdr_tonecurve_ym; /*!< Tonemapping curve coefficient Ym_ (rw) MRV_WDR_BASE + 0x2A28 + (n*0x4) (n=0..32) */
  127. } wdr_tone_mapping_curve_y_block_t;
  128. /*! wdr_tone_mapping_curve_y_shd_block register layout */
  129. typedef struct {
  130. uint32_t isp_wdr_tonecurve_ym_shd; /*!< Tonemapping curve coefficient shadow register (r) MRV_WDR_BASE + 0x2B60 + (n*0x4) (n=0..32) */
  131. } wdr_tone_mapping_curve_y_shd_block_t;
  132. /*! AWB_MEAS_ACCU register layout */
  133. typedef struct {
  134. uint32_t awb_meas_accu; /*!< AWB Accu Read (r) ISP_AWB_BASE + 0x2E90 + (n*0x4) (n=0..23) */
  135. } AWB_MEAS_ACCU_t;
  136. /*! isp64_histogram_measurement_result register layout */
  137. typedef struct {
  138. uint32_t isp64_hist_bin; /*!< histogram measurement result bin (sh_r) MRV_HIST_BASE + 0x2EA8 + (n*0x4) (n=0..31) */
  139. } isp64_histogram_measurement_result_t;
  140. typedef struct {
  141. uint32_t x, y;
  142. } elawb_ellipse_pt;
  143. typedef struct {
  144. uint32_t a1, a2, a3, a4;
  145. } elawb_ellipse_axis;
  146. /*! MrvAll Register layout */
  147. typedef struct {
  148. uint32_t vi_ccl; /*!< Clock control register (rw) MRV_BASE + 0x00000000 */
  149. uint32_t _notused_0[(0x00000008 - 0x00000004) / 4]; /* gap in address space */
  150. uint32_t vi_id; /*!< Revision identification register (r) MRV_BASE + 0x00000008 */
  151. uint32_t _notused_1[(0x00000010 - 0x0000000c) / 4]; /* gap in address space */
  152. uint32_t vi_iccl; /*!< Internal clock control register (rw) MRV_BASE + 0x00000010 */
  153. uint32_t vi_ircl; /*!< Internal reset control register (rw) MRV_BASE + 0x00000014 */
  154. uint32_t vi_dpcl; /*!< Data path control register (rw) MRV_BASE + 0x00000018 */
  155. uint32_t _notused_2[(0x00000200 - 0x0000001c) / 4]; /* gap in address space */
  156. uint32_t img_eff_ctrl; /*!< Global control register (rw) MRV_IMGEFF_BASE + 0x00000000 */
  157. uint32_t img_eff_color_sel; /*!< Color selection register (for color selection effect) (rw) MRV_IMGEFF_BASE + 0x00000004 */
  158. uint32_t img_eff_mat_1; /*!< 3x3 matrix coefficients for emboss effect (1) (rw) MRV_IMGEFF_BASE + 0x00000008 */
  159. uint32_t img_eff_mat_2; /*!< 3x3 matrix coefficients for emboss effect (2) (rw) MRV_IMGEFF_BASE + 0x0000000c */
  160. uint32_t img_eff_mat_3; /*!< 3x3 matrix coefficients for emboss(3) effect / sketch/sharpen(1) effect (rw) MRV_IMGEFF_BASE + 0x00000010 */
  161. uint32_t img_eff_mat_4; /*!< 3x3 matrix coefficients for sketch/sharpen effect (2) (rw) MRV_IMGEFF_BASE + 0x00000014 */
  162. uint32_t img_eff_mat_5; /*!< 3x3 matrix coefficients for sketch/sharpen effect (3) (rw) MRV_IMGEFF_BASE + 0x00000018 */
  163. uint32_t img_eff_tint; /*!< Chrominance increment values of a tint (used for sepia effect) (rw) MRV_IMGEFF_BASE + 0x0000001c */
  164. uint32_t img_eff_ctrl_shd; /*!< Shadow register for control register (r) MRV_IMGEFF_BASE + 0x00000020 */
  165. uint32_t img_eff_sharpen; /*!< Factor and threshold for sharpen effect (rw) MRV_IMGEFF_BASE + 0x00000024 */
  166. uint32_t _notused_3[(0x00000300 - 0x00000228) / 4]; /* gap in address space */
  167. uint32_t super_imp_ctrl; /*!< Global control register (rw) MRV_SI_BASE + 0x00000000 */
  168. uint32_t super_imp_offset_x; /*!< Offset x register (rw) MRV_SI_BASE + 0x00000004 */
  169. uint32_t super_imp_offset_y; /*!< Offset y register (rw) MRV_SI_BASE + 0x00000008 */
  170. uint32_t super_imp_color_y; /*!< Y component of transparent key color (rw) MRV_SI_BASE + 0x0000000c */
  171. uint32_t super_imp_color_cb; /*!< Cb component of transparent key color (rw) MRV_SI_BASE + 0x00000010 */
  172. uint32_t super_imp_color_cr; /*!< Cr component of transparent key color (rw) MRV_SI_BASE + 0x00000014 */
  173. uint32_t _notused_4[(0x00000400 - 0x00000318) / 4]; /* gap in address space */
  174. uint32_t isp_ctrl; /*!< global control register (rw) MRV_ISP_BASE + 0x00000000 */
  175. uint32_t isp_acq_prop; /*!< ISP acquisition properties (rw) MRV_ISP_BASE + 0x00000004 */
  176. uint32_t isp_acq_h_offs; /*!< horizontal input offset (rw) MRV_ISP_BASE + 0x00000008 */
  177. uint32_t isp_acq_v_offs; /*!< vertical input offset (rw) MRV_ISP_BASE + 0x0000000c */
  178. uint32_t isp_acq_h_size; /*!< horizontal input size (rw) MRV_ISP_BASE + 0x00000010 */
  179. uint32_t isp_acq_v_size; /*!< vertical input size (rw) MRV_ISP_BASE + 0x00000014 */
  180. uint32_t isp_acq_nr_frames; /*!< Number of frames to be captured (rw) MRV_ISP_BASE + 0x00000018 */
  181. uint32_t isp_gamma_dx_lo; /*!< De-Gamma Curve definition lower x increments (sampling points) (rw) MRV_ISP_BASE + 0x0000001c */
  182. uint32_t isp_gamma_dx_hi; /*!< De-Gamma Curve definition higher x increments (sampling points) (rw) MRV_ISP_BASE + 0x00000020 */
  183. degamma_r_y_block_t degamma_r_y_block_arr[DEGAMMA_R_Y_BLOCK_ARR_SIZE]; /*!< degamma_r_y_block MRV_ISP_BASE + 36 + (n*0x4) (n=0..16) */
  184. degamma_g_y_block_t degamma_g_y_block_arr[DEGAMMA_G_Y_BLOCK_ARR_SIZE]; /*!< degamma_g_y_block MRV_ISP_BASE + 104 + (n*0x4) (n=0..16) */
  185. degamma_b_y_block_t degamma_b_y_block_arr[DEGAMMA_B_Y_BLOCK_ARR_SIZE]; /*!< degamma_b_y_block MRV_ISP_BASE + 172 + (n*0x4) (n=0..16) */
  186. uint32_t isp_dgain_rb; /*!< (rw) MRV_ISP_BASE + 0x000000f0 */
  187. uint32_t isp_dgain_g; /*!< (rw) MRV_ISP_BASE + 0x000000f4 */
  188. uint32_t _notused_5[(0x00000510 - 0x000004f8) / 4]; /* gap in address space */
  189. uint32_t isp_awb_prop; /*!< Auto white balance properties (rw) MRV_ISP_BASE + 0x00000110 */
  190. uint32_t isp_awb_h_offs; /*!< Auto white balance horizontal offset of measure window (rw) MRV_ISP_BASE + 0x00000114 */
  191. uint32_t isp_awb_v_offs; /*!< Auto white balance vertical offset of measure window (rw) MRV_ISP_BASE + 0x00000118 */
  192. uint32_t isp_awb_h_size; /*!< Auto white balance horizontal window size (rw) MRV_ISP_BASE + 0x0000011c */
  193. uint32_t isp_awb_v_size; /*!< Auto white balance vertical window size (rw) MRV_ISP_BASE + 0x00000120 */
  194. uint32_t isp_awb_frames; /*!< Auto white balance mean value over multiple frames (rw) MRV_ISP_BASE + 0x00000124 */
  195. uint32_t isp_awb_ref; /*!< Auto white balance reference Cb/Cr values (rw) MRV_ISP_BASE + 0x00000128 */
  196. uint32_t isp_awb_thresh; /*!< Auto white balance threshold values (rw) MRV_ISP_BASE + 0x0000012c */
  197. uint32_t _notused_6[(0x00000538 - 0x00000530) / 4]; /* gap in address space */
  198. uint32_t isp_awb_gain_g; /*!< Auto white balance gain green (rw) MRV_ISP_BASE + 0x00000138 */
  199. uint32_t isp_awb_gain_rb; /*!< Auto white balance gain red and blue (rw) MRV_ISP_BASE + 0x0000013c */
  200. uint32_t isp_awb_white_cnt; /*!< Auto white balance white pixel count (r) MRV_ISP_BASE + 0x00000140 */
  201. uint32_t isp_awb_mean; /*!< Auto white balance measured mean value (r) MRV_ISP_BASE + 0x00000144 */
  202. uint32_t _notused_7[(0x00000570 - 0x00000548) / 4]; /* gap in address space */
  203. uint32_t isp_cc_coeff_0; /*!< Color conversion coefficient 0 (rw) MRV_ISP_BASE + 0x00000170 */
  204. uint32_t isp_cc_coeff_1; /*!< Color conversion coefficient 1 (rw) MRV_ISP_BASE + 0x00000174 */
  205. uint32_t isp_cc_coeff_2; /*!< Color conversion coefficient 2 (rw) MRV_ISP_BASE + 0x00000178 */
  206. uint32_t isp_cc_coeff_3; /*!< Color conversion coefficient 3 (rw) MRV_ISP_BASE + 0x0000017c */
  207. uint32_t isp_cc_coeff_4; /*!< Color conversion coefficient 4 (rw) MRV_ISP_BASE + 0x00000180 */
  208. uint32_t isp_cc_coeff_5; /*!< Color conversion coefficient 5 (rw) MRV_ISP_BASE + 0x00000184 */
  209. uint32_t isp_cc_coeff_6; /*!< Color conversion coefficient 6 (rw) MRV_ISP_BASE + 0x00000188 */
  210. uint32_t isp_cc_coeff_7; /*!< Color conversion coefficient 7 (rw) MRV_ISP_BASE + 0x0000018c */
  211. uint32_t isp_cc_coeff_8; /*!< Color conversion coefficient 8 (rw) MRV_ISP_BASE + 0x00000190 */
  212. uint32_t isp_out_h_offs; /*!< Horizontal offset of output window (rw) MRV_ISP_BASE + 0x00000194 */
  213. uint32_t isp_out_v_offs; /*!< Vertical offset of output window (rw) MRV_ISP_BASE + 0x00000198 */
  214. uint32_t isp_out_h_size; /*!< Output horizontal picture size (rw) MRV_ISP_BASE + 0x0000019c */
  215. uint32_t isp_out_v_size; /*!< Output vertical picture size (rw) MRV_ISP_BASE + 0x000001a0 */
  216. uint32_t isp_demosaic; /*!< Demosaic parameters (rw) MRV_ISP_BASE + 0x000001a4 */
  217. uint32_t isp_flags_shd; /*!< Flags (current status) of certain signals and Shadow regs for enable signals (r) MRV_ISP_BASE + 0x000001a8 */
  218. uint32_t isp_out_h_offs_shd; /*!< current horizontal offset of output window (shadow register) (r) MRV_ISP_BASE + 0x000001ac */
  219. uint32_t isp_out_v_offs_shd; /*!< current vertical offset of output window (shadow register) (r) MRV_ISP_BASE + 0x000001b0 */
  220. uint32_t isp_out_h_size_shd; /*!< current output horizontal picture size (shadow register) (r) MRV_ISP_BASE + 0x000001b4 */
  221. uint32_t isp_out_v_size_shd; /*!< current output vertical picture size (shadow register) (r) MRV_ISP_BASE + 0x000001b8 */
  222. uint32_t isp_imsc; /*!< Interrupt mask (rw) MRV_ISP_BASE + 0x000001bc */
  223. uint32_t isp_ris; /*!< Raw interrupt status (r) MRV_ISP_BASE + 0x000001c0 */
  224. uint32_t isp_mis; /*!< Masked interrupt status (r) MRV_ISP_BASE + 0x000001c4 */
  225. uint32_t isp_icr; /*!< Interrupt clear register (w) MRV_ISP_BASE + 0x000001c8 */
  226. uint32_t isp_isr; /*!< Interrupt set register (w) MRV_ISP_BASE + 0x000001cc */
  227. cross_talk_coef_block_t cross_talk_coef_block_arr[CROSS_TALK_COEF_BLOCK_ARR_SIZE]; /*!< cross_talk_coef_block MRV_ISP_BASE + 464 + (n*0x4) (n=0..8) */
  228. uint32_t isp_gamma_out_mode; /*!< gamma segmentation mode register for output gamma (rw) MRV_ISP_BASE + 0x000001f4 */
  229. gamma_out_y_block_t gamma_out_y_block_arr[GAMMA_OUT_Y_BLOCK_ARR_SIZE]; /*!< gamma_out_y_block MRV_ISP_BASE + 504 + (n*0x4) (n=0..16) */
  230. uint32_t isp_err; /*!< ISP error register (r) MRV_ISP_BASE + 0x0000023c */
  231. uint32_t isp_err_clr; /*!< ISP error clear register (w) MRV_ISP_BASE + 0x00000240 */
  232. uint32_t isp_frame_count; /*!< Frame counter (r) MRV_ISP_BASE + 0x00000244 */
  233. uint32_t isp_ct_offset_r; /*!< cross-talk offset red (rw) MRV_ISP_BASE + 0x00000248 */
  234. uint32_t isp_ct_offset_g; /*!< cross-talk offset green (rw) MRV_ISP_BASE + 0x0000024c */
  235. uint32_t isp_ct_offset_b; /*!< cross-talk offset blue (rw) MRV_ISP_BASE + 0x00000250 */
  236. uint32_t isp_cnr_linesize; /*!< chroma noise reduction line size (rw) MRV_ISP_BASE + 0x00000254 */
  237. uint32_t isp_cnr_threshold_c1; /*!< chroma noise reduction C1 Threshold (rw) MRV_ISP_BASE + 0x00000258 */
  238. uint32_t isp_cnr_threshold_c2; /*!< chroma noise reduction C2 Threshold (rw) MRV_ISP_BASE + 0x0000025c */
  239. uint32_t isp_flash_cmd; /*!< Flash command (w) MRV_FLASH_BASE + 0x00000000 */
  240. uint32_t isp_flash_config; /*!< Flash config (rw) MRV_FLASH_BASE + 0x00000004 */
  241. uint32_t isp_flash_prediv; /*!< Flash Counter Pre-Divider (rw) MRV_FLASH_BASE + 0x00000008 */
  242. uint32_t isp_flash_delay; /*!< Flash Delay (rw) MRV_FLASH_BASE + 0x0000000c */
  243. uint32_t isp_flash_time; /*!< Flash time (rw) MRV_FLASH_BASE + 0x00000010 */
  244. uint32_t isp_flash_maxp; /*!< Maximum value for flash or preflash (rw) MRV_FLASH_BASE + 0x00000014 */
  245. uint32_t _notused_8[(0x00000680 - 0x00000678) / 4]; /* gap in address space */
  246. uint32_t isp_sh_ctrl; /*!< mechanical shutter control (rw) MRV_SHUT_BASE + 0x00000000 */
  247. uint32_t isp_sh_prediv; /*!< Mech. Shutter Counter Pre-Divider (rw) MRV_SHUT_BASE + 0x00000004 */
  248. uint32_t isp_sh_delay; /*!< Delay register (rw) MRV_SHUT_BASE + 0x00000008 */
  249. uint32_t isp_sh_time; /*!< Time register (rw) MRV_SHUT_BASE + 0x0000000c */
  250. /* TPG */
  251. uint32_t _notused_pre_tpg[(0x00000700 - 0x00000690) / 4]; /* gap in address space */
  252. uint32_t isp_tpg_ctrl; /*!<(rw), 0x00000700 */
  253. uint32_t isp_tpg_total_in; /*!<(rw), 0x00000704 */
  254. uint32_t isp_tpg_act_in; /*!<(rw), 0x00000708 */
  255. uint32_t isp_tpg_fp_in; /*!<(rw), 0x0000070C */
  256. uint32_t isp_tpg_bp_in; /*!<(rw), 0x00000710 */
  257. uint32_t isp_tpg_w_in; /*!<(rw), 0x00000714 */
  258. uint32_t isp_tpg_gap_in; /*!<(rw), 0x00000718 */
  259. uint32_t isp_tpg_gap_std_in; /*!<(rw), 0x0000071C */
  260. uint32_t isp_tpg_random_seed; /*!<(rw), 0x00000720 */
  261. uint32_t _notused_mid_tpg1[(0x00000730 - 0x00000724) / 4]; /* gap in address space */
  262. uint32_t isp_vsync_delay; /*!<(rw), 0x00000730 */
  263. uint32_t _notused_mid_tpg2[(0x00000750 - 0x00000734) / 4]; /* gap in address space */
  264. uint32_t green_equilibrate_ctrl; /*!<(rw), 0x00000750 */
  265. uint32_t green_equilibrate_hcnt_dummy; /*!<(rw), 0x00000754 */
  266. uint32_t green_equilibrate_ctrl_shd; /*!<(rw), 0x00000758 */
  267. uint32_t _notused_after_tpg[(0x00000800 - 0x0000075c) / 4]; /* gap in address space */
  268. /* uint32_t _notused_9[(0x00000800-0x00000690)/4]; gap in address space */
  269. uint32_t cproc_ctrl; /*!< Global control register (rw) MRV_CPROC_BASE + 0x00000000 */
  270. uint32_t cproc_contrast; /*!< Color Processing contrast register (rw) MRV_CPROC_BASE + 0x00000004 */
  271. uint32_t cproc_brightness; /*!< Color Processing brightness register (rw) MRV_CPROC_BASE + 0x00000008 */
  272. uint32_t cproc_saturation; /*!< Color Processing saturation register (rw) MRV_CPROC_BASE + 0x0000000c */
  273. uint32_t cproc_hue; /*!< Color Processing hue register (rw) MRV_CPROC_BASE + 0x00000010 */
  274. #ifdef ISP_RGBGC
  275. uint32_t _notused_10_0[(0x00000900 - 0x00000814) / 4]; /* gap in address space */
  276. uint32_t isp_gcrgb_r_px_0; /*!<Gamma Correction for rgb register 0x00000900 */
  277. uint32_t isp_gcrgb_r_px_1; /*!<Gamma Correction for rgb register 0x00000904 */
  278. uint32_t isp_gcrgb_r_px_2; /*!<Gamma Correction for rgb register 0x00000908 */
  279. uint32_t isp_gcrgb_r_px_3; /*!<Gamma Correction for rgb register 0x0000090C */
  280. uint32_t isp_gcrgb_r_px_4; /*!<Gamma Correction for rgb register 0x00000910 */
  281. uint32_t isp_gcrgb_r_px_5; /*!<Gamma Correction for rgb register 0x00000914 */
  282. uint32_t isp_gcrgb_r_px_6; /*!<Gamma Correction for rgb register 0x00000918 */
  283. uint32_t isp_gcrgb_r_px_7; /*!<Gamma Correction for rgb register 0x0000091C */
  284. uint32_t isp_gcrgb_r_px_8; /*!<Gamma Correction for rgb register 0x00000920 */
  285. uint32_t isp_gcrgb_r_px_9; /*!<Gamma Correction for rgb register 0x00000924 */
  286. uint32_t isp_gcrgb_r_px_10; /*!<Gamma Correction for rgb register 0x00000928 */
  287. uint32_t isp_gcrgb_r_y_addr; /*!<Gamma Correction for rgb register 0x0000092C */
  288. uint32_t isp_gcrgb_r_y_write_data; /*!<Gamma Correction for rgb register 0x00000930 */
  289. uint32_t isp_gcrgb_r_x_addr; /*!<Gamma Correction for rgb register 0x00000934 */
  290. uint32_t isp_gcrgb_r_x_write_data; /*!<Gamma Correction for rgb register 0x00000938 */
  291. uint32_t _notused_10_1; /* gap in address space */
  292. uint32_t isp_gcrgb_g_px_0; /*!<Gamma Correction for rgb register 0x00000940 */
  293. uint32_t isp_gcrgb_g_px_1; /*!<Gamma Correction for rgb register 0x00000944 */
  294. uint32_t isp_gcrgb_g_px_2; /*!<Gamma Correction for rgb register 0x00000948 */
  295. uint32_t isp_gcrgb_g_px_3; /*!<Gamma Correction for rgb register 0x0000094C */
  296. uint32_t isp_gcrgb_g_px_4; /*!<Gamma Correction for rgb register 0x00000950 */
  297. uint32_t isp_gcrgb_g_px_5; /*!<Gamma Correction for rgb register 0x00000954 */
  298. uint32_t isp_gcrgb_g_px_6; /*!<Gamma Correction for rgb register 0x00000958 */
  299. uint32_t isp_gcrgb_g_px_7; /*!<Gamma Correction for rgb register 0x0000095C */
  300. uint32_t isp_gcrgb_g_px_8; /*!<Gamma Correction for rgb register 0x00000960 */
  301. uint32_t isp_gcrgb_g_px_9; /*!<Gamma Correction for rgb register 0x00000964 */
  302. uint32_t isp_gcrgb_g_px_10; /*!<Gamma Correction for rgb register 0x00000968 */
  303. uint32_t isp_gcrgb_g_y_addr; /*!<Gamma Correction for rgb register 0x0000096C */
  304. uint32_t isp_gcrgb_g_y_write_data; /*!<Gamma Correction for rgb register 0x00000970 */
  305. uint32_t isp_gcrgb_g_x_addr; /*!<Gamma Correction for rgb register 0x00000974 */
  306. uint32_t isp_gcrgb_g_x_write_data; /*!<Gamma Correction for rgb register 0x00000978 */
  307. uint32_t _notused_10_2; /* gap in address space */
  308. uint32_t isp_gcrgb_b_px_0; /*!<Gamma Correction for rgb register 0x00000980 */
  309. uint32_t isp_gcrgb_b_px_1; /*!<Gamma Correction for rgb register 0x00000984 */
  310. uint32_t isp_gcrgb_b_px_2; /*!<Gamma Correction for rgb register 0x00000988 */
  311. uint32_t isp_gcrgb_b_px_3; /*!<Gamma Correction for rgb register 0x0000098C */
  312. uint32_t isp_gcrgb_b_px_4; /*!<Gamma Correction for rgb register 0x00000990 */
  313. uint32_t isp_gcrgb_b_px_5; /*!<Gamma Correction for rgb register 0x00000994 */
  314. uint32_t isp_gcrgb_b_px_6; /*!<Gamma Correction for rgb register 0x00000998 */
  315. uint32_t isp_gcrgb_b_px_7; /*!<Gamma Correction for rgb register 0x0000099C */
  316. uint32_t isp_gcrgb_b_px_8; /*!<Gamma Correction for rgb register 0x000009A0 */
  317. uint32_t isp_gcrgb_b_px_9; /*!<Gamma Correction for rgb register 0x000009A4 */
  318. uint32_t isp_gcrgb_b_px_10; /*!<Gamma Correction for rgb register 0x000009A8 */
  319. uint32_t isp_gcrgb_b_y_addr; /*!<Gamma Correction for rgb register 0x000009AC */
  320. uint32_t isp_gcrgb_b_y_write_data; /*!<Gamma Correction for rgb register 0x000009B0 */
  321. uint32_t isp_gcrgb_b_x_addr; /*!<Gamma Correction for rgb register 0x000009B4 */
  322. uint32_t isp_gcrgb_b_x_write_data; /*!<Gamma Correction for rgb register 0x000009B8 */
  323. uint32_t _notused_10[(0x00000c00 - 0x000009bc) / 4]; /* gap in address space */
  324. #else
  325. uint32_t _notused_10[(0x00000c00 - 0x00000814) / 4]; /* gap in address space */
  326. #endif
  327. uint32_t mrsz_ctrl; /*!< global control register (rw) MRV_MRSZ_BASE + 0x00000000 */
  328. uint32_t mrsz_scale_hy; /*!< horizontal luminance scale factor register (rw) MRV_MRSZ_BASE + 0x00000004 */
  329. uint32_t mrsz_scale_hcb; /*!< horizontal Cb scale factor register (rw) MRV_MRSZ_BASE + 0x00000008 */
  330. uint32_t mrsz_scale_hcr; /*!< horizontal Cr scale factor register (rw) MRV_MRSZ_BASE + 0x0000000c */
  331. uint32_t mrsz_scale_vy; /*!< vertical luminance scale factor register (rw) MRV_MRSZ_BASE + 0x00000010 */
  332. uint32_t mrsz_scale_vc; /*!< vertical chrominance scale factor register (rw) MRV_MRSZ_BASE + 0x00000014 */
  333. uint32_t mrsz_phase_hy; /*!< horizontal luminance phase register (rw) MRV_MRSZ_BASE + 0x00000018 */
  334. uint32_t mrsz_phase_hc; /*!< horizontal chrominance phase register (rw) MRV_MRSZ_BASE + 0x0000001c */
  335. uint32_t mrsz_phase_vy; /*!< vertical luminance phase register (rw) MRV_MRSZ_BASE + 0x00000020 */
  336. uint32_t mrsz_phase_vc; /*!< vertical chrominance phase register (rw) MRV_MRSZ_BASE + 0x00000024 */
  337. uint32_t mrsz_scale_lut_addr; /*!< Address pointer of up-scaling look up table (rw) MRV_MRSZ_BASE + 0x00000028 */
  338. uint32_t mrsz_scale_lut; /*!< Entry of up-scaling look up table (rw) MRV_MRSZ_BASE + 0x0000002c */
  339. uint32_t mrsz_ctrl_shd; /*!< global control shadow register (r) MRV_MRSZ_BASE + 0x00000030 */
  340. uint32_t mrsz_scale_hy_shd; /*!< horizontal luminance scale factor shadow register (r) MRV_MRSZ_BASE + 0x00000034 */
  341. uint32_t mrsz_scale_hcb_shd; /*!< horizontal Cb scale factor shadow register (r) MRV_MRSZ_BASE + 0x00000038 */
  342. uint32_t mrsz_scale_hcr_shd; /*!< horizontal Cr scale factor shadow register (r) MRV_MRSZ_BASE + 0x0000003c */
  343. uint32_t mrsz_scale_vy_shd; /*!< vertical luminance scale factor shadow register (r) MRV_MRSZ_BASE + 0x00000040 */
  344. uint32_t mrsz_scale_vc_shd; /*!< vertical chrominance scale factor shadow register (r) MRV_MRSZ_BASE + 0x00000044 */
  345. uint32_t mrsz_phase_hy_shd; /*!< horizontal luminance phase shadow register (r) MRV_MRSZ_BASE + 0x00000048 */
  346. uint32_t mrsz_phase_hc_shd; /*!< horizontal chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x0000004c */
  347. uint32_t mrsz_phase_vy_shd; /*!< vertical luminance phase shadow register (r) MRV_MRSZ_BASE + 0x00000050 */
  348. uint32_t mrsz_phase_vc_shd; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000054 */
  349. uint32_t mrsz_phase_crop_x; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000058 */
  350. uint32_t mrsz_phase_crop_y; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x0000005c */
  351. uint32_t mrsz_phase_crop_x_shd; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000060 */
  352. uint32_t mrsz_phase_crop_y_shd; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000064 */
  353. uint32_t mrsz_phase_frame_rate; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000068 */
  354. uint32_t mrsz_format_conv_ctrl; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x0000006c */
  355. uint32_t _notused_11_0[(0x00001000 - 0x00000c70) / 4]; /* gap in address space */
  356. uint32_t srsz_ctrl; /*!< global control register (rw) MRV_SRSZ_BASE + 0x00000000 */
  357. uint32_t srsz_scale_hy; /*!< horizontal luminance scale factor register (rw) MRV_SRSZ_BASE + 0x00000004 */
  358. uint32_t srsz_scale_hcb; /*!< horizontal chrominance scale factor register (rw) MRV_SRSZ_BASE + 0x00000008 */
  359. uint32_t srsz_scale_hcr; /*!< horizontal chrominance scale factor register (rw) MRV_SRSZ_BASE + 0x0000000c */
  360. uint32_t srsz_scale_vy; /*!< vertical luminance scale factor register (rw) MRV_SRSZ_BASE + 0x00000010 */
  361. uint32_t srsz_scale_vc; /*!< vertical chrominance scale factor register (rw) MRV_SRSZ_BASE + 0x00000014 */
  362. uint32_t srsz_phase_hy; /*!< horizontal luminance phase register (rw) MRV_SRSZ_BASE + 0x00000018 */
  363. uint32_t srsz_phase_hc; /*!< horizontal chrominance phase register (rw) MRV_SRSZ_BASE + 0x0000001c */
  364. uint32_t srsz_phase_vy; /*!< vertical luminance phase register (rw) MRV_SRSZ_BASE + 0x00000020 */
  365. uint32_t srsz_phase_vc; /*!< vertical chrominance phase register (rw) MRV_SRSZ_BASE + 0x00000024 */
  366. uint32_t srsz_scale_lut_addr; /*!< Address pointer of up-scaling look up table (rw) MRV_SRSZ_BASE + 0x00000028 */
  367. uint32_t srsz_scale_lut; /*!< Entry of up-scaling look up table (rw) MRV_SRSZ_BASE + 0x0000002c */
  368. uint32_t srsz_ctrl_shd; /*!< global control shadow register (r) MRV_SRSZ_BASE + 0x00000030 */
  369. uint32_t srsz_scale_hy_shd; /*!< horizontal luminance scale factor shadow register (r) MRV_SRSZ_BASE + 0x00000034 */
  370. uint32_t srsz_scale_hcb_shd; /*!< horizontal Cb scale factor shadow register (r) MRV_SRSZ_BASE + 0x00000038 */
  371. uint32_t srsz_scale_hcr_shd; /*!< horizontal Cr scale factor shadow register (r) MRV_SRSZ_BASE + 0x0000003c */
  372. uint32_t srsz_scale_vy_shd; /*!< vertical luminance scale factor shadow register (r) MRV_SRSZ_BASE + 0x00000040 */
  373. uint32_t srsz_scale_vc_shd; /*!< vertical chrominance scale factor shadow register (r) MRV_SRSZ_BASE + 0x00000044 */
  374. uint32_t srsz_phase_hy_shd; /*!< horizontal luminance phase shadow register (r) MRV_SRSZ_BASE + 0x00000048 */
  375. uint32_t srsz_phase_hc_shd; /*!< horizontal chrominance phase shadow register (r) MRV_SRSZ_BASE + 0x0000004c */
  376. uint32_t srsz_phase_vy_shd; /*!< vertical luminance phase shadow register (r) MRV_SRSZ_BASE + 0x00000050 */
  377. uint32_t srsz_phase_vc_shd; /*!< vertical chrominance phase shadow register (r) MRV_SRSZ_BASE + 0x00000054 */
  378. uint32_t srsz_phase_crop_x; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000058 */
  379. uint32_t srsz_phase_crop_y; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x0000005c */
  380. uint32_t srsz_phase_crop_x_shd; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000060 */
  381. uint32_t srsz_phase_crop_y_shd; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000064 */
  382. uint32_t srsz_phase_frame_rate; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000068 */
  383. uint32_t srsz_phase_format_conv_ctr; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x0000006c */
  384. uint32_t _notused_11_1[(0x00001100 - 0x00001070) / 4]; /* gap in address space */
  385. uint32_t srsz2_ctrl; /*!< global control register (rw) MRV_SRSZ_BASE + 0x00000000 */
  386. uint32_t srsz2_scale_hy; /*!< horizontal luminance scale factor register (rw) MRV_SRSZ_BASE + 0x00000004 */
  387. uint32_t srsz2_scale_hcb; /*!< horizontal chrominance scale factor register (rw) MRV_SRSZ_BASE + 0x00000008 */
  388. uint32_t srsz2_scale_hcr; /*!< horizontal chrominance scale factor register (rw) MRV_SRSZ_BASE + 0x0000000c */
  389. uint32_t srsz2_scale_vy; /*!< vertical luminance scale factor register (rw) MRV_SRSZ_BASE + 0x00000010 */
  390. uint32_t srsz2_scale_vc; /*!< vertical chrominance scale factor register (rw) MRV_SRSZ_BASE + 0x00000014 */
  391. uint32_t srsz2_phase_hy; /*!< horizontal luminance phase register (rw) MRV_SRSZ_BASE + 0x00000018 */
  392. uint32_t srsz2_phase_hc; /*!< horizontal chrominance phase register (rw) MRV_SRSZ_BASE + 0x0000001c */
  393. uint32_t srsz2_phase_vy; /*!< vertical luminance phase register (rw) MRV_SRSZ_BASE + 0x00000020 */
  394. uint32_t srsz2_phase_vc; /*!< vertical chrominance phase register (rw) MRV_SRSZ_BASE + 0x00000024 */
  395. uint32_t srsz2_scale_lut_addr; /*!< Address pointer of up-scaling look up table (rw) MRV_SRSZ_BASE + 0x00000028 */
  396. uint32_t srsz2_scale_lut; /*!< Entry of up-scaling look up table (rw) MRV_SRSZ_BASE + 0x0000002c */
  397. uint32_t srsz2_ctrl_shd; /*!< global control shadow register (r) MRV_SRSZ_BASE + 0x00000030 */
  398. uint32_t srsz2_scale_hy_shd; /*!< horizontal luminance scale factor shadow register (r) MRV_SRSZ_BASE + 0x00000034 */
  399. uint32_t srsz2_scale_hcb_shd; /*!< horizontal Cb scale factor shadow register (r) MRV_SRSZ_BASE + 0x00000038 */
  400. uint32_t srsz2_scale_hcr_shd; /*!< horizontal Cr scale factor shadow register (r) MRV_SRSZ_BASE + 0x0000003c */
  401. uint32_t srsz2_scale_vy_shd; /*!< vertical luminance scale factor shadow register (r) MRV_SRSZ_BASE + 0x00000040 */
  402. uint32_t srsz2_scale_vc_shd; /*!< vertical chrominance scale factor shadow register (r) MRV_SRSZ_BASE + 0x00000044 */
  403. uint32_t srsz2_phase_hy_shd; /*!< horizontal luminance phase shadow register (r) MRV_SRSZ_BASE + 0x00000048 */
  404. uint32_t srsz2_phase_hc_shd; /*!< horizontal chrominance phase shadow register (r) MRV_SRSZ_BASE + 0x0000004c */
  405. uint32_t srsz2_phase_vy_shd; /*!< vertical luminance phase shadow register (r) MRV_SRSZ_BASE + 0x00000050 */
  406. uint32_t srsz2_phase_vc_shd; /*!< vertical chrominance phase shadow register (r) MRV_SRSZ_BASE + 0x00000054 */
  407. uint32_t srsz2_phase_crop_x; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000058 */
  408. uint32_t srsz2_phase_crop_y; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x0000005c */
  409. uint32_t srsz2_phase_crop_x_shd; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000060 */
  410. uint32_t srsz2_phase_crop_y_shd; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000064 */
  411. uint32_t srsz2_phase_frame_rate; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x00000068 */
  412. uint32_t srsz2_phase_format_conv_ctr; /*!< vertical chrominance phase shadow register (r) MRV_MRSZ_BASE + 0x0000006c */
  413. uint32_t _notused_11_2[(0x00001200 - 0x00001170) / 4]; /* gap in address space */
  414. uint32_t mcm_ctrl; /*!<(rw), (0x00001200) */
  415. uint32_t mcm_size0; /*!<(rw), (0x00001204) */
  416. uint32_t mcm_size1; /*!<(rw), (0x00001208) */
  417. uint32_t mcm_g2_size0; /*!<(rw), (0x0000120c) */
  418. uint32_t mcm_g2_size1; /*!<(rw), (0x00001210) */
  419. uint32_t _notused_11_3[(0x00001280 - 0x00001214) / 4]; /* gap in address space */
  420. uint32_t mcm_rd_cfg; /*!<(rw), (0x00001280) */
  421. uint32_t mcm_retiming0; /*!<(rw), (0x00001284) */
  422. uint32_t mcm_retiming1; /*!<(rw), (0x00001288) */
  423. uint32_t mcm_hsync_preample_ext; /*!<(rw), (0x0000128c) */
  424. uint32_t mcm_wr_retiming0; /*!<(rw), (0x00001290) */
  425. uint32_t mcm_wr_retiming1; /*!<(rw), (0x00001294) */
  426. #ifdef ISP_MIV1
  427. uint32_t _notused_12[(0x00001400 - 0x00001298) / 4]; /* gap in address space */
  428. uint32_t mi_ctrl; /*!< Global control register (rw) MRV_MI_BASE + 0x00000000 */
  429. uint32_t mi_init; /*!< Control register for address init and skip function (w) MRV_MI_BASE + 0x00000004 */
  430. uint32_t mi_mp_y_base_ad_init; /*!< Base address for main picture Y component, JPEG or raw data (rw) MRV_MI_BASE + 0x00000008 */
  431. uint32_t mi_mp_y_size_init; /*!< Size of main picture Y component, JPEG or raw data (rw) MRV_MI_BASE + 0x0000000c */
  432. uint32_t mi_mp_y_offs_cnt_init; /*!< Offset counter init value for main picture Y, JPEG or raw data (rw) MRV_MI_BASE + 0x00000010 */
  433. uint32_t mi_mp_y_offs_cnt_start; /*!< Offset counter start value for main picture Y, JPEG or raw data (r) MRV_MI_BASE + 0x00000014 */
  434. uint32_t mi_mp_y_irq_offs_init; /*!< Fill level interrupt offset value for main picture Y, JPEG or raw data (rw) MRV_MI_BASE + 0x00000018 */
  435. uint32_t mi_mp_cb_base_ad_init; /*!< Base address for main picture Cb component ring buffer (rw) MRV_MI_BASE + 0x0000001c */
  436. uint32_t mi_mp_cb_size_init; /*!< Size of main picture Cb component ring buffer (rw) MRV_MI_BASE + 0x00000020 */
  437. uint32_t mi_mp_cb_offs_cnt_init; /*!< Offset counter init value for main picture Cb component ring buffer (rw) MRV_MI_BASE + 0x00000024 */
  438. uint32_t mi_mp_cb_offs_cnt_start; /*!< Offset counter start value for main picture Cb component ring buffer (r) MRV_MI_BASE + 0x00000028 */
  439. uint32_t mi_mp_cr_base_ad_init; /*!< Base address for main picture Cr component ring buffer (rw) MRV_MI_BASE + 0x0000002c */
  440. uint32_t mi_mp_cr_size_init; /*!< Size of main picture Cr component ring buffer (rw) MRV_MI_BASE + 0x00000030 */
  441. uint32_t mi_mp_cr_offs_cnt_init; /*!< Offset counter init value for main picture Cr component ring buffer (rw) MRV_MI_BASE + 0x00000034 */
  442. uint32_t mi_mp_cr_offs_cnt_start; /*!< Offset counter start value for main picture Cr component ring buffer (r) MRV_MI_BASE + 0x00000038 */
  443. uint32_t mi_sp_y_base_ad_init; /*!< Base address for self picture Y component ring buffer (rw) MRV_MI_BASE + 0x0000003c */
  444. uint32_t mi_sp_y_size_init; /*!< Size of self picture Y component ring buffer (rw) MRV_MI_BASE + 0x00000040 */
  445. uint32_t mi_sp_y_offs_cnt_init; /*!< Offset counter init value for self picture Y component ring buffer (rw) MRV_MI_BASE + 0x00000044 */
  446. uint32_t mi_sp_y_offs_cnt_start; /*!< Offset counter start value for self picture Y component ring buffer (r) MRV_MI_BASE + 0x00000048 */
  447. uint32_t mi_sp_y_llength; /*!< Line length of self picture Y component (rw) MRV_MI_BASE + 0x0000004c */
  448. uint32_t mi_sp_cb_base_ad_init; /*!< Base address for self picture Cb component ring buffer (rw) MRV_MI_BASE + 0x00000050 */
  449. uint32_t mi_sp_cb_size_init; /*!< Size of self picture Cb component ring buffer (rw) MRV_MI_BASE + 0x00000054 */
  450. uint32_t mi_sp_cb_offs_cnt_init; /*!< Offset counter init value for self picture Cb component ring buffer (rw) MRV_MI_BASE + 0x00000058 */
  451. uint32_t mi_sp_cb_offs_cnt_start; /*!< Offset counter start value for self picture Cb component ring buffer (r) MRV_MI_BASE + 0x0000005c */
  452. uint32_t mi_sp_cr_base_ad_init; /*!< Base address for self picture Cr component ring buffer (rw) MRV_MI_BASE + 0x00000060 */
  453. uint32_t mi_sp_cr_size_init; /*!< Size of self picture Cr component ring buffer (rw) MRV_MI_BASE + 0x00000064 */
  454. uint32_t mi_sp_cr_offs_cnt_init; /*!< Offset counter init value for self picture Cr component ring buffer (rw) MRV_MI_BASE + 0x00000068 */
  455. uint32_t mi_sp_cr_offs_cnt_start; /*!< Offset counter start value for self picture Cr component ring buffer (r) MRV_MI_BASE + 0x0000006c */
  456. uint32_t mi_byte_cnt; /*!< Counter value of JPEG or RAW data bytes (r) MRV_MI_BASE + 0x00000070 */
  457. uint32_t mi_ctrl_shd; /*!< global control internal shadow register (r) MRV_MI_BASE + 0x00000074 */
  458. uint32_t mi_mp_y_base_ad_shd; /*!< Base address shadow register for main picture Y component, JPEG or raw data ring buffer (r) MRV_MI_BASE + 0x00000078 */
  459. uint32_t mi_mp_y_size_shd; /*!< Size shadow register of main picture Y component, JPEG or raw data (r) MRV_MI_BASE + 0x0000007c */
  460. uint32_t mi_mp_y_offs_cnt_shd; /*!< Current offset counter of main picture Y component, JPEG or raw data ring buffer (r) MRV_MI_BASE + 0x00000080 */
  461. uint32_t mi_mp_y_irq_offs_shd; /*!< Shadow register of fill level interrupt offset value for main picture Y component, JPEG or raw data (r) MRV_MI_BASE + 0x00000084 */
  462. uint32_t mi_mp_cb_base_ad_shd; /*!< Base address shadow register for main picture Cb component ring buffer (r) MRV_MI_BASE + 0x00000088 */
  463. uint32_t mi_mp_cb_size_shd; /*!< Size shadow register of main picture Cb component ring buffer (r) MRV_MI_BASE + 0x0000008c */
  464. uint32_t mi_mp_cb_offs_cnt_shd; /*!< Current offset counter of main picture Cb component ring buffer (r) MRV_MI_BASE + 0x00000090 */
  465. uint32_t mi_mp_cr_base_ad_shd; /*!< Base address shadow register for main picture Cr component ring buffer (r) MRV_MI_BASE + 0x00000094 */
  466. uint32_t mi_mp_cr_size_shd; /*!< Size shadow register of main picture Cr component ring buffer (r) MRV_MI_BASE + 0x00000098 */
  467. uint32_t mi_mp_cr_offs_cnt_shd; /*!< Current offset counter of main picture Cr component ring buffer (r) MRV_MI_BASE + 0x0000009c */
  468. uint32_t mi_sp_y_base_ad_shd; /*!< Base address shadow register for self picture Y component ring buffer (r) MRV_MI_BASE + 0x000000a0 */
  469. uint32_t mi_sp_y_size_shd; /*!< Size shadow register of self picture Y component ring buffer (r) MRV_MI_BASE + 0x000000a4 */
  470. uint32_t mi_sp_y_offs_cnt_shd; /*!< Current offset counter of self picture Y component ring buffer (r) MRV_MI_BASE + 0x000000a8 */
  471. uint32_t _notused_13[(0x000014b0 - 0x000014ac) / 4]; /* gap in address space */
  472. uint32_t mi_sp_cb_base_ad_shd; /*!< Base address shadow register for self picture Cb component ring buffer (r) MRV_MI_BASE + 0x000000b0 */
  473. uint32_t mi_sp_cb_size_shd; /*!< Size shadow register of self picture Cb component ring buffer (r) MRV_MI_BASE + 0x000000b4 */
  474. uint32_t mi_sp_cb_offs_cnt_shd; /*!< Current offset counter of self picture Cb component ring buffer (r) MRV_MI_BASE + 0x000000b8 */
  475. uint32_t mi_sp_cr_base_ad_shd; /*!< Base address shadow register for self picture Cr component ring buffer (r) MRV_MI_BASE + 0x000000bc */
  476. uint32_t mi_sp_cr_size_shd; /*!< Size shadow register of self picture Cr component ring buffer (r) MRV_MI_BASE + 0x000000c0 */
  477. uint32_t mi_sp_cr_offs_cnt_shd; /*!< Current offset counter of self picture Cr component ring buffer (r) MRV_MI_BASE + 0x000000c4 */
  478. uint32_t mi_dma_y_pic_start_ad; /*!< Y component image start address (rw) MRV_MI_BASE + 0x000000c8 */
  479. uint32_t mi_dma_y_pic_width; /*!< Y component image width (rw) MRV_MI_BASE + 0x000000cc */
  480. uint32_t mi_dma_y_llength; /*!< Y component original line length (rw) MRV_MI_BASE + 0x000000d0 */
  481. uint32_t mi_dma_y_pic_size; /*!< Y component image size (rw) MRV_MI_BASE + 0x000000d4 */
  482. uint32_t mi_dma_cb_pic_start_ad; /*!< Cb component image start address (rw) MRV_MI_BASE + 0x000000d8 */
  483. uint32_t _notused_14[(0x000014e8 - 0x000014dc) / 4]; /* gap in address space */
  484. uint32_t mi_dma_cr_pic_start_ad; /*!< Cr component image start address (rw) MRV_MI_BASE + 0x000000e8 */
  485. uint32_t _notused_15[(0x000014f8 - 0x000014ec) / 4]; /* gap in address space */
  486. uint32_t mi_imsc; /*!< Interrupt Mask (‘1’: interrupt active, ‘0’: interrupt masked) (rw) MRV_MI_BASE + 0x000000f8 */
  487. uint32_t mi_ris; /*!< Raw Interrupt Status (r) MRV_MI_BASE + 0x000000fc */
  488. uint32_t mi_mis; /*!< Masked Interrupt Status (r) MRV_MI_BASE + 0x00000100 */
  489. uint32_t mi_icr; /*!< Interrupt Clear Register (w) MRV_MI_BASE + 0x00000104 */
  490. uint32_t mi_isr; /*!< Interrupt Set Register (w) MRV_MI_BASE + 0x00000108 */
  491. uint32_t mi_status; /*!< MI Status Register (r) MRV_MI_BASE + 0x0000010c */
  492. uint32_t mi_status_clr; /*!< MI Status Clear Register (w) MRV_MI_BASE + 0x00000110 */
  493. uint32_t mi_sp_y_pic_width; /*!< Y component image width (rw) MRV_MI_BASE + 0x00000114 */
  494. uint32_t mi_sp_y_pic_height; /*!< Y component image height (rw) MRV_MI_BASE + 0x00000118 */
  495. uint32_t mi_sp_y_pic_size; /*!< Y component image size (rw) MRV_MI_BASE + 0x0000011c */
  496. uint32_t mi_dma_ctrl; /*!< DMA control register (rw) MRV_MI_BASE + 0x00000120 */
  497. uint32_t mi_dma_start; /*!< DMA start register (w) MRV_MI_BASE + 0x00000124 */
  498. uint32_t mi_dma_status; /*!< DMA status register (r) MRV_MI_BASE + 0x00000128 */
  499. uint32_t mi_pixel_cnt; /*!< Counter value for defect pixel list (r) MRV_MI_BASE + 0x0000012c */
  500. uint32_t mi_mp_y_base_ad_init2; /*!< Base address 2 (ping pong) for main picture Y component, JPEG or raw data (rw) MRV_MI_BASE + 0x00000130 */
  501. uint32_t mi_mp_cb_base_ad_init2; /*!< Base address 2 (pingpong) for main picture Cb component (rw) MRV_MI_BASE + 0x00000134 */
  502. uint32_t mi_mp_cr_base_ad_init2; /*!< Base address 2 (pingpong) for main picture Cr component ring buffer (rw) MRV_MI_BASE + 0x00000138 */
  503. uint32_t mi_sp_y_base_ad_init2; /*!< Base address 2 (ping pong) for main picture Y component, JPEG or raw data (rw) MRV_MI_BASE + 0x0000013c */
  504. uint32_t mi_sp_cb_base_ad_init2; /*!< Base address 2 (pingpong) for main picture Cb component (rw) MRV_MI_BASE + 0x00000140 */
  505. uint32_t mi_sp_cr_base_ad_init2; /*!< Base address 2 (pingpong) for main picture Cr component ring buffer (rw) MRV_MI_BASE + 0x00000144 */
  506. uint32_t mi_reserved_1; /*!< MI_RESERVED_1 (rw) MRV_MI_BASE + 0x00000148 */
  507. #ifdef ISP_MI_HANDSHAKE_NANO
  508. uint32_t mi_mp_handshake; /*!< MI mp handshake control for Nano handshake, (rw) MRV_MI_BASE + 0x0000014C */
  509. #else
  510. uint32_t mi_reserved_1_1; /*!< MI_RESERVED_1 (rw) MRV_MI_BASE + 0x0000014c */
  511. #endif
  512. uint32_t mi_mp_y_llength; /*!< MI mp y llength for Nano handshake, (rw) MRV_MI_BASE + 0x00000150 */
  513. uint32_t mi_mp_y_slice_offset; /*!< MI mp y slice offset for Nano handshake, (rw) MRV_MI_BASE + 0x00000154 */
  514. uint32_t mi_mp_c_slice_offset; /*!< MI mp c slice offset for Nano handshare, (rw) MRV_MI_BASE + 0x00000158 */
  515. uint32_t mi_output_align_format; /*!< MI output byte swap and LSB alignment control for Nano, (rw) MRV_MI_BASE + 0x0000015C */
  516. uint32_t mi_mp_output_fifo_size; /*!< MI mp output fifo control for Nano, (rw) MRV_MI_BASE + 0x00000160 */
  517. uint32_t mi_mp_y_pic_width; /*!< MI mp y width pix for Nano handshake, (rw) MRV_MI_BASE + 0x00000164 */
  518. uint32_t mi_mp_y_pic_height; /*!< MI mp y height pix for Nano handshake, (rw) MRV_MI_BASE + 0x00000168 */
  519. uint32_t mi_mp_y_pic_size; /*!< MI mp y pix size for Nano handshare, (rw) MRV_MI_BASE + 0x0000016C */
  520. #ifdef ISP_MI_BP
  521. uint32_t _notused_16_0[(0x00001580 - 0x00001570) / 4];
  522. uint32_t mi_bp_ctrl; /*!<(rw), (0x00001580) */
  523. uint32_t mi_bp_r_base_ad_shd; /*!<(rw), (0x00001584) */
  524. uint32_t mi_bp_gr_base_ad_shd; /*!<(rw), (0x00001588) */
  525. uint32_t mi_bp_gb_base_ad_shd; /*!<(rw), (0x0000158C) */
  526. uint32_t mi_bp_b_base_ad_shd; /*!<(rw), (0x00001590) */
  527. uint32_t mi_bp_r_offs_cnt_shd; /*!<(rw), (0x00001594) */
  528. uint32_t mi_bp_gr_offs_cnt_shd; /*!<(rw), (0x00001598) */
  529. uint32_t mi_bp_gb_offs_cnt_shd; /*!<(rw), (0x0000159C) */
  530. uint32_t mi_bp_b_offs_cnt_shd; /*!<(rw), (0x000015A0) */
  531. uint32_t mi_bp_wr_offs_cnt_init; /*!<(rw), (0x000015A4) */
  532. uint32_t mi_bp_wr_irq_offs_shd; /*!<(rw), (0x000015A8) */
  533. uint32_t mi_bp_wr_irq_offs_init; /*!<(rw), (0x000015AC) */
  534. uint32_t mi_bp_wr_size_shd; /*!<(rw), (0x000015B0) */
  535. uint32_t mi_bp_wr_size_init; /*!<(rw), (0x000015B4) */
  536. uint32_t mi_bp_wr_llength; /*!<(rw), (0x000015B8) */
  537. uint32_t mi_bp_pic_width; /*!<(rw), (0x000015BC) */
  538. uint32_t mi_bp_pic_height; /*!<(rw), (0x000015C0) */
  539. uint32_t mi_bp_pic_size; /*!<(rw), (0x000015C4) */
  540. uint32_t mi_bp_r_offs_cnt_start; /*!<(rw), (0x000015C8) */
  541. uint32_t mi_bp_gr_offs_cnt_start; /*!<(rw), (0x000015CC) */
  542. uint32_t mi_bp_gb_offs_cnt_start; /*!<(rw), (0x000015D0) */
  543. uint32_t mi_bp_b_offs_cnt_start; /*!<(rw), (0x000015D4) */
  544. uint32_t mi_bp_r_base_ad_init; /*!<(rw), (0x000015D8) */
  545. uint32_t mi_bp_gr_base_ad_init; /*!<(rw), (0x000015DC) */
  546. uint32_t mi_bp_gb_base_ad_init; /*!<(rw), (0x000015E0) */
  547. uint32_t mi_bp_b_base_ad_init; /*!<(rw), (0x000015E4) */
  548. #else
  549. uint32_t _notused_16[(0x000015e8 - 0x00001570) / 4]; /* gap in address space */
  550. #endif
  551. uint32_t mi_dma_y_raw_fmt; /*!<(rw), (0x000015E8) */
  552. uint32_t mi_dma_y_raw_lval; /*!<(rw), (0x000015EC) */
  553. uint32_t _notused_16_1[(0x00001800 - 0x000015f0) / 4]; /* gap in address space */
  554. #elif defined (ISP_MIV2)
  555. uint32_t _notused_12[(0x00001300 - 0x00001298) / 4]; /* gap in address space */
  556. uint32_t miv2_ctrl; /*!<(rw), (0x00001300) */
  557. uint32_t miv2_ctrl_shd; /*!<(rw), (0x00001304) */
  558. uint32_t _notused_13[(0x00001310 - 0x00001308) / 4]; /* gap in address space */
  559. uint32_t miv2_mp_ctrl; /*!<(rw), (0x00001310) */
  560. uint32_t miv2_mp_fmt; /*!<(rw), (0x00001314) */
  561. uint32_t miv2_mp_bus_cfg; /*!<(rw), (0x00001318) */
  562. uint32_t miv2_mp_bus_id; /*!<(rw), (0x0000131c) */
  563. uint32_t miv2_mp_bus_timeo; /*!<(rw), (0x00001320) */
  564. uint32_t miv2_mp_y_base_ad_init; /*!<(rw), (0x00001324) */
  565. uint32_t miv2_mp_y_size_init; /*!<(rw), (0x00001328) */
  566. uint32_t miv2_mp_y_offs_cnt_init; /*!<(rw), (0x0000132c) */
  567. uint32_t miv2_mp_y_llength; /*!<(rw), (0x00001330) */
  568. uint32_t miv2_mp_y_pic_width; /*!<(rw), (0x00001334) */
  569. uint32_t miv2_mp_y_pic_height; /*!<(rw), (0x00001338) */
  570. uint32_t miv2_mp_y_pic_size; /*!<(rw), (0x0000133c) */
  571. uint32_t miv2_mp_cb_base_ad_init; /*!<(rw), (0x00001340) */
  572. uint32_t miv2_mp_cb_size_init; /*!<(rw), (0x00001344) */
  573. uint32_t miv2_mp_cb_offs_cnt_init; /*!<(rw), (0x00001348) */
  574. uint32_t miv2_mp_cr_base_ad_init; /*!<(rw), (0x0000134c) */
  575. uint32_t miv2_mp_cr_size_init; /*!<(rw), (0x00001350) */
  576. uint32_t miv2_mp_cr_offs_cnt_init; /*!<(rw), (0x00001354) */
  577. uint32_t miv2_mp_y_base_ad_init2; /*!<(rw), (0x00001358) */
  578. uint32_t miv2_mp_cb_base_ad_init2; /*!<(rw), (0x0000135c) */
  579. uint32_t miv2_mp_cr_base_ad_init2; /*!<(rw), (0x00001360) */
  580. uint32_t miv2_mp_y_offs_cnt_start; /*!<(ro), (0x00001364) */
  581. uint32_t miv2_mp_cb_offs_cnt_start; /*!<(ro), (0x00001368) */
  582. uint32_t miv2_mp_cr_offs_cnt_start; /*!<(ro), (0x0000136c) */
  583. uint32_t miv2_mp_y_base_ad_shd; /*!<(ro), (0x00001370) */
  584. uint32_t miv2_mp_y_size_shd; /*!<(ro), (0x00001374) */
  585. uint32_t miv2_mp_y_offs_cnt_shd; /*!<(ro), (0x00001378) */
  586. uint32_t miv2_mp_cb_base_ad_shd; /*!<(ro), (0x0000137c) */
  587. uint32_t miv2_mp_cb_size_shd; /*!<(ro), (0x00001380) */
  588. uint32_t miv2_mp_cb_offs_cnt_shd; /*!<(ro), (0x00001384) */
  589. uint32_t miv2_mp_cr_base_ad_shd; /*!<(ro), (0x00001388) */
  590. uint32_t miv2_mp_cr_size_shd; /*!<(ro), (0x0000138c) */
  591. uint32_t miv2_mp_cr_offs_cnt_shd; /*!<(ro), (0x00001390) */
  592. uint32_t miv2_mp_raw_base_ad_init; /*!<(rw), (0x00001394) */
  593. uint32_t miv2_mp_raw_size_init; /*!<(rw), (0x00001398) */
  594. uint32_t miv2_mp_raw_offs_cnt_init; /*!<(rw), (0x0000139c) */
  595. uint32_t miv2_mp_raw_llength; /*!<(rw), (0x000013a0) */
  596. uint32_t miv2_mp_raw_pic_width; /*!<(rw), (0x000013a4) */
  597. uint32_t miv2_mp_raw_pic_height; /*!<(rw), (0x000013a8) */
  598. uint32_t miv2_mp_raw_pic_size; /*!<(rw), (0x000013ac) */
  599. uint32_t miv2_mp_raw_offs_cnt_start; /*!<(ro), (0x000013b0) */
  600. uint32_t miv2_mp_raw_base_ad_shd; /*!<(ro), (0x000013b4) */
  601. uint32_t miv2_mp_raw_size_shd; /*!<(ro), (0x000013b8) */
  602. uint32_t miv2_mp_raw_offs_cnt_shd; /*!<(ro), (0x000013bc) */
  603. uint32_t miv2_mp_jdp_base_ad_init; /*!<(rw), (0x000013c0) */
  604. uint32_t miv2_mp_jdp_size_init; /*!<(rw), (0x000013c4) */
  605. uint32_t miv2_mp_jdp_offs_cnt_init; /*!<(rw), (0x000013c8) */
  606. uint32_t miv2_mp_jdp_llength; /*!<(rw), (0x000013cc) */
  607. uint32_t miv2_mp_jdp_pic_width; /*!<(rw), (0x000013d0) */
  608. uint32_t miv2_mp_jdp_pic_height; /*!<(rw), (0x000013d4) */
  609. uint32_t miv2_mp_jdp_pic_size; /*!<(rw), (0x000013d8) */
  610. uint32_t miv2_mp_jdp_offs_cnt_start; /*!<(ro), (0x000013dc) */
  611. uint32_t miv2_mp_jdp_base_ad_shd; /*!<(ro), (0x000013e0) */
  612. uint32_t miv2_mp_jdp_size_shd; /*!<(ro), (0x000013e4) */
  613. uint32_t miv2_mp_jdp_offs_cnt_shd; /*!<(ro), (0x000013e8) */
  614. uint32_t miv2_mp_status_clr; /*!<(rw), (0x000013ec) */
  615. uint32_t miv2_mp_ctrl_status; /*!<(ro), (0x000013f0) */
  616. uint32_t miv2_mp_axi_status; /*!<(ro), (0x000013f4) */
  617. uint32_t miv2_mp_raw_byte_cnt_status; /*!<(rw), (0x000013f8) */
  618. uint32_t miv2_mp_jdp_byte_cnt_status; /*!<(rw), (0x000013fc) */
  619. uint32_t miv2_mp_dp_byte_cnt_status; /*!<(rw), (0x00001400) */
  620. uint32_t _notused_14[(0x0000142c - 0x00001404) / 4]; /* gap in address space */
  621. uint32_t miv2_sp1_ctrl; /*!<(rw), (0x0000142c) */
  622. uint32_t miv2_sp1_fmt; /*!<(rw), (0x00001430) */
  623. uint32_t miv2_sp1_bus_cfg; /*!<(rw), (0x00001434) */
  624. uint32_t miv2_sp1_bus_id; /*!<(rw), (0x00001438) */
  625. uint32_t miv2_sp1_bus_timeo; /*!<(rw), (0x0000143c) */
  626. uint32_t miv2_sp1_y_base_ad_init; /*!<(rw), (0x00001440) */
  627. uint32_t miv2_sp1_y_size_init; /*!<(rw), (0x00001444) */
  628. uint32_t miv2_sp1_y_offs_cnt_init; /*!<(rw), (0x00001448) */
  629. uint32_t miv2_sp1_y_llength; /*!<(rw), (0x0000144c) */
  630. uint32_t miv2_sp1_y_pic_width; /*!<(rw), (0x00001450) */
  631. uint32_t miv2_sp1_y_pic_height; /*!<(rw), (0x00001454) */
  632. uint32_t miv2_sp1_y_pic_size; /*!<(rw), (0x00001458) */
  633. uint32_t miv2_sp1_cb_base_ad_init; /*!<(rw), (0x0000145c) */
  634. uint32_t miv2_sp1_cb_size_init; /*!<(rw), (0x00001460) */
  635. uint32_t miv2_sp1_cb_offs_cnt_init; /*!<(rw), (0x00001464) */
  636. uint32_t miv2_sp1_cr_base_ad_init; /*!<(rw), (0x00001468) */
  637. uint32_t miv2_sp1_cr_size_init; /*!<(rw), (0x0000146c) */
  638. uint32_t miv2_sp1_cr_offs_cnt_init; /*!<(rw), (0x00001470) */
  639. uint32_t miv2_sp1_y_base_ad_init2; /*!<(rw), (0x00001474) */
  640. uint32_t miv2_sp1_cb_base_ad_init2; /*!<(rw), (0x00001478) */
  641. uint32_t miv2_sp1_cr_base_ad_init2; /*!<(rw), (0x0000147c) */
  642. uint32_t miv2_sp1_y_offs_cnt_start; /*!<(ro), (0x00001480) */
  643. uint32_t miv2_sp1_cb_offs_cnt_start; /*!<(ro), (0x00001484) */
  644. uint32_t miv2_sp1_cr_offs_cnt_start; /*!<(ro), (0x00001488) */
  645. uint32_t miv2_sp1_y_base_ad_shd; /*!<(ro), (0x0000148c) */
  646. uint32_t miv2_sp1_y_size_shd; /*!<(ro), (0x00001490) */
  647. uint32_t miv2_sp1_y_offs_cnt_shd; /*!<(ro), (0x00001494) */
  648. uint32_t miv2_sp1_cb_base_ad_shd; /*!<(ro), (0x00001498) */
  649. uint32_t miv2_sp1_cb_size_shd; /*!<(ro), (0x0000149c) */
  650. uint32_t miv2_sp1_cb_offs_cnt_shd; /*!<(ro), (0x000014a0) */
  651. uint32_t miv2_sp1_cr_base_ad_shd; /*!<(ro), (0x000014a4) */
  652. uint32_t miv2_sp1_cr_size_shd; /*!<(ro), (0x000014a8) */
  653. uint32_t miv2_sp1_cr_offs_cnt_shd; /*!<(ro), (0x000014ac) */
  654. uint32_t miv2_sp1_status_clr; /*!<(rw), (0x000014b0) */
  655. uint32_t miv2_sp1_ctrl_status; /*!<(ro), (0x000014b4) */
  656. uint32_t miv2_sp1_axi_status; /*!<(ro), (0x000014b8) */
  657. uint32_t _notused_15[(0x000014e4 - 0x000014bc) / 4]; /* gap in address space */
  658. uint32_t miv2_sp2_ctrl; /*!<(rw), (0x000014e4) */
  659. uint32_t miv2_sp2_fmt; /*!<(rw), (0x000014e8) */
  660. uint32_t miv2_sp2_bus_cfg; /*!<(rw), (0x000014ec) */
  661. uint32_t miv2_sp2_bus_id; /*!<(rw), (0x000014f0) */
  662. uint32_t miv2_sp2_bus_timeo; /*!<(rw), (0x000014f4) */
  663. uint32_t miv2_sp2_y_base_ad_init; /*!<(rw), (0x000014f8) */
  664. uint32_t miv2_sp2_y_size_init; /*!<(rw), (0x000014fc) */
  665. uint32_t miv2_sp2_y_offs_cnt_init; /*!<(rw), (0x00001500) */
  666. uint32_t miv2_sp2_y_llength; /*!<(rw), (0x00001504) */
  667. uint32_t miv2_sp2_y_pic_width; /*!<(rw), (0x00001508) */
  668. uint32_t miv2_sp2_y_pic_height; /*!<(rw), (0x0000150c) */
  669. uint32_t miv2_sp2_y_pic_size; /*!<(rw), (0x00001510) */
  670. uint32_t miv2_sp2_cb_base_ad_init; /*!<(rw), (0x00001514) */
  671. uint32_t miv2_sp2_cb_size_init; /*!<(rw), (0x00001518) */
  672. uint32_t miv2_sp2_cb_offs_cnt_init; /*!<(rw), (0x0000151c) */
  673. uint32_t miv2_sp2_cr_base_ad_init; /*!<(rw), (0x00001520) */
  674. uint32_t miv2_sp2_cr_size_init; /*!<(rw), (0x00001524) */
  675. uint32_t miv2_sp2_cr_offs_cnt_init; /*!<(rw), (0x00001528) */
  676. uint32_t miv2_sp2_y_base_ad_init2; /*!<(rw), (0x0000152c) */
  677. uint32_t miv2_sp2_cb_base_ad_init2; /*!<(rw), (0x00001530) */
  678. uint32_t miv2_sp2_cr_base_ad_init2; /*!<(rw), (0x00001534) */
  679. uint32_t miv2_sp2_y_offs_cnt_start; /*!<(ro), (0x00001538) */
  680. uint32_t miv2_sp2_cb_offs_cnt_start; /*!<(ro), (0x0000153c) */
  681. uint32_t miv2_sp2_cr_offs_cnt_start; /*!<(ro), (0x00001540) */
  682. uint32_t miv2_sp2_y_base_ad_shd; /*!<(ro), (0x00001544) */
  683. uint32_t miv2_sp2_y_size_shd; /*!<(ro), (0x00001548) */
  684. uint32_t miv2_sp2_y_offs_cnt_shd; /*!<(ro), (0x0000154c) */
  685. uint32_t miv2_sp2_cb_base_ad_shd; /*!<(ro), (0x00001550) */
  686. uint32_t miv2_sp2_cb_size_shd; /*!<(ro), (0x00001554) */
  687. uint32_t miv2_sp2_cb_offs_cnt_shd; /*!<(ro), (0x00001558) */
  688. uint32_t miv2_sp2_cr_base_ad_shd; /*!<(ro), (0x0000155c) */
  689. uint32_t miv2_sp2_cr_size_shd; /*!<(ro), (0x00001560) */
  690. uint32_t miv2_sp2_cr_offs_cnt_shd; /*!<(ro), (0x00001564) */
  691. uint32_t miv2_sp2_raw_base_ad_init; /*!<(rw), (0x00001568) */
  692. uint32_t miv2_sp2_raw_size_init; /*!<(rw), (0x0000156c) */
  693. uint32_t miv2_sp2_raw_offs_cnt_init; /*!<(rw), (0x00001570) */
  694. uint32_t miv2_sp2_raw_llength; /*!<(rw), (0x00001574) */
  695. uint32_t miv2_sp2_raw_pic_width; /*!<(rw), (0x00001578) */
  696. uint32_t miv2_sp2_raw_pic_height; /*!<(rw), (0x0000157c) */
  697. uint32_t miv2_sp2_raw_pic_size; /*!<(rw), (0x00001580) */
  698. uint32_t miv2_sp2_raw_offs_cnt_start; /*!<(ro), (0x00001584) */
  699. uint32_t _notused_16_0[(0x0000158c - 0x00001588) / 4]; /* gap in address space */
  700. uint32_t miv2_sp2_raw_base_ad_shd; /*!<(ro), (0x0000158c) */
  701. uint32_t miv2_sp2_raw_size_shd; /*!<(ro), (0x00001590) */
  702. uint32_t miv2_sp2_raw_offs_cnt_shd; /*!<(ro), (0x00001594) */
  703. uint32_t miv2_sp2_dma_y_pic_start_ad; /*!<(rw), (0x00001598) */
  704. uint32_t miv2_sp2_dma_y_pic_width; /*!<(rw), (0x0000159c) */
  705. uint32_t miv2_sp2_dma_y_pic_llength; /*!<(rw), (0x000015a0) */
  706. uint32_t miv2_sp2_dma_y_pic_size; /*!<(rw), (0x000015a4) */
  707. uint32_t miv2_sp2_dma_cb_pic_start_ad; /*!<(rw), (0x000015a8) */
  708. uint32_t miv2_sp2_dma_cr_pic_start_ad; /*!<(rw), (0x000015ac) */
  709. uint32_t miv2_sp2_dma_y_pic_start_ad_shd; /*!<(ro), (0x000015b0) */
  710. uint32_t miv2_sp2_dma_cb_pic_start_ad_shd; /*!<(ro), (0x000015b4) */
  711. uint32_t miv2_sp2_dma_cr_pic_start_ad_shd; /*!<(ro), (0x000015b8) */
  712. uint32_t miv2_sp2_dma_raw_pic_start_ad; /*!<(rw), (0x000015bc) */
  713. uint32_t miv2_sp2_dma_raw_pic_width; /*!<(rw), (0x000015c0) */
  714. uint32_t miv2_sp2_dma_raw_pic_llength; /*!<(rw), (0x000015c4) */
  715. uint32_t miv2_sp2_dma_raw_pic_size; /*!<(rw), (0x000015c8) */
  716. uint32_t miv2_sp2_dma_raw_pic_start_ad_shd; /*!<(ro), (0x000015cc) */
  717. uint32_t miv2_sp2_status_clr; /*!<(rw), (0x000015d0) */
  718. uint32_t miv2_sp2_ctrl_status; /*!<(ro), (0x000015d4) */
  719. uint32_t miv2_sp2_axi_status; /*!<(ro), (0x000015d8) */
  720. uint32_t miv2_sp2_dma_yuv_status; /*!<(ro), (0x000015dc) */
  721. uint32_t miv2_sp2_dma_raw_status; /*!<(ro), (0x000015e0) */
  722. uint32_t miv2_sp2_dma_y_pic_lval; /*!<(rw), (0x000015e4) */
  723. uint32_t _notused_16_1[(0x000015ec - 0x000015e8) / 4]; /* gap in address space */
  724. uint32_t miv2_sp2_dma_raw_pic_lval; /*!<(rw), (0x000015ec) */
  725. uint32_t _notused_16_2[(0x00001600 - 0x000015f0) / 4]; /* gap in address space */
  726. uint32_t miv2_mcm_ctrl; /*!<(rw), (0x00001600) */
  727. uint32_t miv2_mcm_fmt; /*!<(rw), (0x00001604) */
  728. uint32_t miv2_mcm_bus_cfg; /*!<(rw), (0x00001608) */
  729. uint32_t miv2_mcm_bus_id; /*!<(rw), (0x0000160c) */
  730. uint32_t miv2_mcm_bus_timeo; /*!<(rw), (0x00001610) */
  731. uint32_t miv2_mcm_raw0_base_ad_init; /*!<(rw), (0x00001614) */
  732. uint32_t miv2_mcm_raw0_size_init; /*!<(rw), (0x00001618) */
  733. uint32_t miv2_mcm_raw0_offs_cnt_init; /*!<(rw), (0x0000161c) */
  734. uint32_t miv2_mcm_raw0_llength; /*!<(rw), (0x00001620) */
  735. uint32_t miv2_mcm_raw0_pic_width; /*!<(rw), (0x00001624) */
  736. uint32_t miv2_mcm_raw0_pic_height; /*!<(rw), (0x00001628) */
  737. uint32_t miv2_mcm_raw0_pic_size; /*!<(rw), (0x0000162c) */
  738. uint32_t miv2_mcm_raw0_offs_cnt_start; /*!<(ro), (0x00001630) */
  739. uint32_t miv2_mcm_raw0_base_ad_shd; /*!<(ro), (0x00001634) */
  740. uint32_t miv2_mcm_raw0_size_shd; /*!<(ro), (0x00001638) */
  741. uint32_t miv2_mcm_raw0_offs_cnt_shd; /*!<(ro), (0x0000163c) */
  742. uint32_t miv2_mcm_raw1_base_ad_init; /*!<(rw), (0x00001640) */
  743. uint32_t miv2_mcm_raw1_size_init; /*!<(rw), (0x00001644) */
  744. uint32_t miv2_mcm_raw1_offs_cnt_init; /*!<(rw), (0x00001648) */
  745. uint32_t miv2_mcm_raw1_llength; /*!<(rw), (0x0000164c) */
  746. uint32_t miv2_mcm_raw1_pic_width; /*!<(rw), (0x00001650) */
  747. uint32_t miv2_mcm_raw1_pic_height; /*!<(rw), (0x00001654) */
  748. uint32_t miv2_mcm_raw1_pic_size; /*!<(rw), (0x00001658) */
  749. uint32_t miv2_mcm_raw1_offs_cnt_start; /*!<(ro), (0x0000165c) */
  750. uint32_t miv2_mcm_raw1_base_ad_shd; /*!<(ro), (0x00001660) */
  751. uint32_t miv2_mcm_raw1_size_shd; /*!<(ro), (0x00001664) */
  752. uint32_t miv2_mcm_raw1_offs_cnt_shd; /*!<(ro), (0x00001668) */
  753. uint32_t miv2_mcm_dma_raw_pic_start_ad; /*!<(rw), (0x0000166c) */
  754. uint32_t miv2_mcm_dma_raw_pic_width; /*!<(rw), (0x00001670) */
  755. uint32_t miv2_mcm_dma_raw_pic_llength; /*!<(rw), (0x00001674) */
  756. uint32_t miv2_mcm_dma_raw_pic_size; /*!<(rw), (0x00001678) */
  757. uint32_t miv2_mcm_dma_raw_pic_start_ad_shd; /*!<(ro), (0x0000167c) */
  758. uint32_t miv2_mcm_status_clr; /*!<(rw), (0x00001680) */
  759. uint32_t miv2_mcm_ctrl_status; /*!<(ro), (0x00001684) */
  760. uint32_t miv2_mcm_axi_status; /*!<(ro), (0x00001688) */
  761. uint32_t miv2_mcm_dma_status; /*!<(ro), (0x0000168c) */
  762. uint32_t miv2_mcm_dma_raw_pic_lval; /*!<(ro), (0x00001690) */
  763. uint32_t miv2_mcm_raw0_lval_bytes; /*!<(ro), (0x00001694) */
  764. uint32_t _notused_16_3[(0x000016c0 - 0x00001698) / 4]; /* gap in address space */
  765. uint32_t miv2_imsc; /*!<(rw), (0x000016c0) */
  766. uint32_t miv2_imsc1; /*!<(rw), (0x000016c4) */
  767. uint32_t miv2_isr; /*!<(rw), (0x000016c8) */
  768. uint32_t miv2_isr1; /*!<(rw), (0x000016cc) */
  769. uint32_t miv2_mis; /*!<(rw), (0x000016d0) */
  770. uint32_t miv2_mis1; /*!<(rw), (0x000016d4) */
  771. uint32_t miv2_icr; /*!<(rw), (0x000016d8) */
  772. uint32_t miv2_icr1; /*!<(rw), (0x000016dc) */
  773. uint32_t miv2_ris; /*!<(rw), (0x000016e0) */
  774. uint32_t miv2_ris1; /*!<(rw), (0x000016e4) */
  775. uint32_t miv2_imsc2; /*!<(rw), (0x000016e8) */
  776. uint32_t miv2_isr2; /*!<(rw), (0x000016ec) */
  777. uint32_t miv2_mis2; /*!<(rw), (0x000016f0) */
  778. uint32_t miv2_icr2; /*!<(rw), (0x000016f4) */
  779. uint32_t miv2_ris2; /*!<(rw), (0x000016f8) */
  780. uint32_t _notused_16_4;
  781. uint32_t miv2_mp_y_irq_offs_init; /*!<(rw), (0x00001700) */
  782. uint32_t miv2_mp_jdp_irq_offs_init; /*!<(rw), (0x00001704) */
  783. uint32_t miv2_mp_raw_irq_offs_init; /*!<(rw), (0x00001708) */
  784. uint32_t miv2_sp1_y_irq_offs_init; /*!<(rw), (0x0000170c) */
  785. uint32_t miv2_sp2_y_irq_offs_init; /*!<(rw), (0x00001710) */
  786. uint32_t miv2_sp2_raw_irq_offs_init; /*!<(rw), (0x00001714) */
  787. uint32_t miv2_mcm_raw0_irq_offs_init; /*!<(rw), (0x00001718) */
  788. uint32_t miv2_mcm_raw1_irq_offs_init; /*!<(rw), (0x0000171c) */
  789. uint32_t miv2_mp_y_irq_offs_shd; /*!<(ro), (0x00001720) */
  790. uint32_t miv2_mp_jdp_irq_offs_shd; /*!<(ro), (0x00001724) */
  791. uint32_t miv2_mp_raw_irq_offs_shd; /*!<(ro), (0x00001728) */
  792. uint32_t miv2_sp1_y_irq_offs_shd; /*!<(ro), (0x0000172c) */
  793. uint32_t miv2_sp2_y_irq_offs_shd; /*!<(ro), (0x00001730) */
  794. uint32_t miv2_sp2_raw_irq_offs_shd; /*!<(ro), (0x00001734) */
  795. uint32_t miv2_mcm_raw0_irq_offs_shd; /*!<(ro), (0x00001738) */
  796. uint32_t miv2_mcm_raw1_irq_offs_shd; /*!<(ro), (0x0000173c) */
  797. uint32_t _notused_16[(0x00001800 - 0x00001740) / 4]; /* gap in address space */
  798. #endif
  799. uint32_t jpe_gen_header; /*!< command to start stream header generation (w) MRV_JPE_BASE + 0x00000000 */
  800. uint32_t jpe_encode; /*!< Start command to start JFIF stream encoding (w) MRV_JPE_BASE + 0x00000004 */
  801. uint32_t jpe_init; /*!< Automatic configuration update (INIT) (w) MRV_JPE_BASE + 0x00000008 */
  802. uint32_t jpe_y_scale_en; /*!< Y value scaling control register (rw) MRV_JPE_BASE + 0x0000000c */
  803. uint32_t jpe_cbcr_scale_en; /*!< Cb/Cr value scaling control register (rw) MRV_JPE_BASE + 0x00000010 */
  804. uint32_t jpe_table_flush; /*!< header generation debug register (rw) MRV_JPE_BASE + 0x00000014 */
  805. uint32_t jpe_enc_hsize; /*!< JPEG codec horizontal image size for encoding (rw) MRV_JPE_BASE + 0x00000018 */
  806. uint32_t jpe_enc_vsize; /*!< JPEG codec vertical image size for encoding (rw) MRV_JPE_BASE + 0x0000001c */
  807. uint32_t jpe_pic_format; /*!< JPEG picture encoding format (rw) MRV_JPE_BASE + 0x00000020 */
  808. uint32_t jpe_restart_interval; /*!< restart marker insertion register (rw) MRV_JPE_BASE + 0x00000024 */
  809. uint32_t jpe_tq_y_select; /*!< Q- table selector 0, quant. table for Y component (rw) MRV_JPE_BASE + 0x00000028 */
  810. uint32_t jpe_tq_u_select; /*!< Q- table selector 1, quant. table for U component (rw) MRV_JPE_BASE + 0x0000002c */
  811. uint32_t jpe_tq_v_select; /*!< Q- table selector 2, quant. table for V component (rw) MRV_JPE_BASE + 0x00000030 */
  812. uint32_t jpe_dc_table_select; /*!< Huffman table selector for DC values (r) MRV_JPE_BASE + 0x00000034 */
  813. uint32_t jpe_ac_table_select; /*!< Huffman table selector for AC values (r) MRV_JPE_BASE + 0x00000038 */
  814. uint32_t jpe_table_data; /*!< table programming register (w) MRV_JPE_BASE + 0x0000003c */
  815. uint32_t jpe_table_id; /*!< table programming select register (rw) MRV_JPE_BASE + 0x00000040 */
  816. uint32_t jpe_tac0_len; /*!< Huffman AC table 0 length (rw) MRV_JPE_BASE + 0x00000044 */
  817. uint32_t jpe_tdc0_len; /*!< Huffman DC table 0 length (rw) MRV_JPE_BASE + 0x00000048 */
  818. uint32_t jpe_tac1_len; /*!< Huffman AC table 1 length (rw) MRV_JPE_BASE + 0x0000004c */
  819. uint32_t jpe_tdc1_len; /*!< Huffman DC table 1 length (rw) MRV_JPE_BASE + 0x00000050 */
  820. uint32_t _notused_17[(0x00001858 - 0x00001854) / 4]; /* gap in address space */
  821. uint32_t jpe_encoder_busy; /*!< encoder status flag (r) MRV_JPE_BASE + 0x00000058 */
  822. uint32_t jpe_header_mode; /*!< header mode definition (rw) MRV_JPE_BASE + 0x0000005c */
  823. uint32_t jpe_encode_mode; /*!< encode mode (r) MRV_JPE_BASE + 0x00000060 */
  824. uint32_t jpe_debug; /*!< debug information register (r) MRV_JPE_BASE + 0x00000064 */
  825. uint32_t jpe_error_imr; /*!< JPEG error interrupt mask register (rw) MRV_JPE_BASE + 0x00000068 */
  826. uint32_t jpe_error_ris; /*!< JPEG error raw interrupt status register (r) MRV_JPE_BASE + 0x0000006c */
  827. uint32_t jpe_error_mis; /*!< JPEG error masked interrupt status register (r) MRV_JPE_BASE + 0x00000070 */
  828. uint32_t jpe_error_icr; /*!< JPEG error interrupt set register (w) MRV_JPE_BASE + 0x00000074 */
  829. uint32_t jpe_error_isr; /*!< JPEG error interrupt clear register (w) MRV_JPE_BASE + 0x00000078 */
  830. uint32_t jpe_status_imr; /*!< JPEG status interrupt mask register (rw) MRV_JPE_BASE + 0x0000007c */
  831. uint32_t jpe_status_ris; /*!< JPEG status raw interrupt status register (r) MRV_JPE_BASE + 0x00000080 */
  832. uint32_t jpe_status_mis; /*!< JPEG status masked interrupt status register (r) MRV_JPE_BASE + 0x00000084 */
  833. uint32_t jpe_status_icr; /*!< JPEG status interrupt clear register (w) MRV_JPE_BASE + 0x00000088 */
  834. uint32_t jpe_status_isr; /*!< JPEG status interrupt set register (w) MRV_JPE_BASE + 0x0000008c */
  835. uint32_t jpe_config; /*!< JPEG configuration register (rw) MRV_JPE_BASE + 0x00000090 */
  836. uint32_t _notused_18[(0x00001a00 - 0x00001894) / 4]; /* gap in address space */
  837. uint32_t smia_ctrl; /*!< global control register (rw) MRV_SMIA_BASE + 0x00000000 */
  838. uint32_t smia_status; /*!< global status register (r) MRV_SMIA_BASE + 0x00000004 */
  839. uint32_t smia_imsc; /*!< Interrupt mask (rw) MRV_SMIA_BASE + 0x00000008 */
  840. uint32_t smia_ris; /*!< Raw interrupt status (r) MRV_SMIA_BASE + 0x0000000c */
  841. uint32_t smia_mis; /*!< Masked interrupt status (r) MRV_SMIA_BASE + 0x00000010 */
  842. uint32_t smia_icr; /*!< Interrupt clear register (w) MRV_SMIA_BASE + 0x00000014 */
  843. uint32_t smia_isr; /*!< Interrupt set register (w) MRV_SMIA_BASE + 0x00000018 */
  844. uint32_t smia_data_format_sel; /*!< data format selector register (rw) MRV_SMIA_BASE + 0x0000001c */
  845. uint32_t smia_sof_emb_data_lines; /*!< start of frame embedded data lines register (rw) MRV_SMIA_BASE + 0x00000020 */
  846. uint32_t smia_emb_hstart; /*!< embedded data hstart register (rw) MRV_SMIA_BASE + 0x00000024 */
  847. uint32_t smia_emb_hsize; /*!< embedded data hsize register (rw) MRV_SMIA_BASE + 0x00000028 */
  848. uint32_t smia_emb_vstart; /*!< embedded data vstart register (rw) MRV_SMIA_BASE + 0x0000002c */
  849. uint32_t smia_num_lines; /*!< image data lines register (rw) MRV_SMIA_BASE + 0x00000030 */
  850. uint32_t smia_emb_data_fifo; /*!< Embedded Data Fifo (r) MRV_SMIA_BASE + 0x00000034 */
  851. uint32_t smia_fifo_fill_level; /*!< Embedded Data FIFO Fill Level (rw) MRV_SMIA_BASE + 0x00000038 */
  852. uint32_t _notused_19[(0x00001c00 - 0x00001a3c) / 4]; /* gap in address space */
  853. uint32_t mipi_ctrl; /*!< global control register (rw) MRV_MIPI_BASE + 0x00000000 */
  854. uint32_t mipi_status; /*!< global status register (r) MRV_MIPI_BASE + 0x00000004 */
  855. uint32_t mipi_imsc; /*!< Interrupt mask (rw) MRV_MIPI_BASE + 0x00000008 */
  856. uint32_t mipi_ris; /*!< Raw interrupt status (r) MRV_MIPI_BASE + 0x0000000c */
  857. uint32_t mipi_mis; /*!< Masked interrupt status (r) MRV_MIPI_BASE + 0x00000010 */
  858. uint32_t mipi_icr; /*!< Interrupt clear register (w) MRV_MIPI_BASE + 0x00000014 */
  859. uint32_t mipi_isr; /*!< Interrupt set register (w) MRV_MIPI_BASE + 0x00000018 */
  860. uint32_t mipi_cur_data_id; /*!< Current Data Identifier (r) MRV_MIPI_BASE + 0x0000001c */
  861. uint32_t mipi_img_data_sel; /*!< Image Data Selector (rw) MRV_MIPI_BASE + 0x00000020 */
  862. uint32_t mipi_add_data_sel_1; /*!< Additional Data Selector 1 (rw) MRV_MIPI_BASE + 0x00000024 */
  863. uint32_t mipi_add_data_sel_2; /*!< Additional Data Selector 2 (rw) MRV_MIPI_BASE + 0x00000028 */
  864. uint32_t mipi_add_data_sel_3; /*!< Additional Data Selector 3 (rw) MRV_MIPI_BASE + 0x0000002c */
  865. uint32_t mipi_add_data_sel_4; /*!< Additional Data Selector 4 (rw) MRV_MIPI_BASE + 0x00000030 */
  866. uint32_t mipi_add_data_fifo; /*!< Additional Data Fifo (r) MRV_MIPI_BASE + 0x00000034 */
  867. uint32_t mipi_add_data_fill_level; /*!< Additional Data FIFO Fill Level (rw) MRV_MIPI_BASE + 0x00000038 */
  868. uint32_t mipi_compressed_mode; /*!< controls processing of compressed raw data types (rw) MRV_MIPI_BASE + 0x0000003c */
  869. uint32_t mipi_frame; /*!< frame number from frame start and frame end short packets (r) MRV_MIPI_BASE + 0x00000040 */
  870. uint32_t mipi_gen_short_dt; /*!< data type flags for received generic short packets (r) MRV_MIPI_BASE + 0x00000044 */
  871. uint32_t mipi_gen_short_8_9; /*!< data field for generic short packets of data type 0x8 and 0x9 (r) MRV_MIPI_BASE + 0x00000048 */
  872. uint32_t mipi_gen_short_a_b; /*!< data field for generic short packets of data type 0xA and 0xB (r) MRV_MIPI_BASE + 0x0000004c */
  873. uint32_t mipi_gen_short_c_d; /*!< data field for generic short packets of data type 0xC and 0xD (r) MRV_MIPI_BASE + 0x00000050 */
  874. uint32_t mipi_gen_short_e_f; /*!< data field for generic short packets of data type 0xE and 0xF (r) MRV_MIPI_BASE + 0x00000054 */
  875. uint32_t _notused_21[(0x00002000 - 0x00001c58) / 4]; /* gap in address space */
  876. uint32_t isp_afm_ctrl; /*!< This is the control register for AF measurement unit (rw) MRV_AFM_BASE + 0x00000000 */
  877. uint32_t isp_afm_lt_a; /*!< Top Left corner of measure window A (rw) MRV_AFM_BASE + 0x00000004 */
  878. uint32_t isp_afm_rb_a; /*!< Bottom right corner of measure window A (rw) MRV_AFM_BASE + 0x00000008 */
  879. uint32_t isp_afm_lt_b; /*!< Top left corner of measure window B (rw) MRV_AFM_BASE + 0x0000000c */
  880. uint32_t isp_afm_rb_b; /*!< Bottom right corner of measure window B (rw) MRV_AFM_BASE + 0x00000010 */
  881. uint32_t isp_afm_lt_c; /*!< Top left corner of measure window C (rw) MRV_AFM_BASE + 0x00000014 */
  882. uint32_t isp_afm_rb_c; /*!< Bottom right corner of measure window C (rw) MRV_AFM_BASE + 0x00000018 */
  883. uint32_t isp_afm_thres; /*!< Threshold register (rw) MRV_AFM_BASE + 0x0000001c */
  884. uint32_t isp_afm_var_shift; /*!< Variable shift register (rw) MRV_AFM_BASE + 0x00000020 */
  885. uint32_t isp_afm_sum_a; /*!< Sharpness Value Status Register of Window A (r) MRV_AFM_BASE + 0x00000024 */
  886. uint32_t isp_afm_sum_b; /*!< Sharpness Value Status Register of Window B (r) MRV_AFM_BASE + 0x00000028 */
  887. uint32_t isp_afm_sum_c; /*!< Sharpness Value Status Register of Window C (r) MRV_AFM_BASE + 0x0000002c */
  888. uint32_t isp_afm_lum_a; /*!< Luminance Value Status Register of Window A (r) MRV_AFM_BASE + 0x00000030 */
  889. uint32_t isp_afm_lum_b; /*!< Luminance Value Status Register of Window B (r) MRV_AFM_BASE + 0x00000034 */
  890. uint32_t isp_afm_lum_c; /*!< Luminance Value Status Register of Window C (r) MRV_AFM_BASE + 0x00000038 */
  891. #ifdef ISP_HIST256
  892. uint32_t _notused_22_0[(0x00002100 - 0x0000203c) / 4]; /* gap in address space */
  893. uint32_t isp_hist256_prop; /*!< Register of hist 256, address 0x00002100 */
  894. uint32_t isp_hist256_h_offs; /*!< Register of hist 256, address 0x00002104 */
  895. uint32_t isp_hist256_v_offs; /*!< Register of hist 256, address 0x00002108 */
  896. uint32_t isp_hist256_h_size; /*!< Register of hist 256, address 0x0000210c */
  897. uint32_t isp_hist256_v_size; /*!< Register of hist 256, address 0x00002110 */
  898. uint32_t isp_hist256_bin_n; /*!< Register of hist 256, address 0x00002114 */
  899. uint32_t _notused_22_1[(0x00002154 - 0x00002118) / 4]; /* gap in address space */
  900. uint32_t isp_hist256_weight_00to30; /*!< Register of hist 256, address 0x00002154 */
  901. uint32_t isp_hist256_weight_40to21; /*!< Register of hist 256, address 0x00002158 */
  902. uint32_t isp_hist256_weight_31to12; /*!< Register of hist 256, address 0x0000215C */
  903. uint32_t isp_hist256_weight_22to03; /*!< Register of hist 256, address 0x00002160 */
  904. uint32_t isp_hist256_weight_13to43; /*!< Register of hist 256, address 0x00002164 */
  905. uint32_t isp_hist256_weight_04to34; /*!< Register of hist 256, address 0x00002168; */
  906. uint32_t isp_hist256_weight_44; /*!< Register of hist 256, address 0x0000216C */
  907. uint32_t _notused_22[(0x00002200 - 0x00002170) / 4]; /* gap in address space */
  908. #else
  909. uint32_t _notused_22[(0x00002200 - 0x0000203c) / 4]; /* gap in address space */
  910. #endif
  911. uint32_t isp_lsc_ctrl; /*!< Lens shade control (rw) MRV_LSC_BASE + 0x00000000 */
  912. uint32_t isp_lsc_r_table_addr; /*!< Table RAM Address for red component (rwhh) MRV_LSC_BASE + 0x00000004 */
  913. uint32_t isp_lsc_gr_table_addr; /*!< Table RAM Address for green (red) component (rwhh) MRV_LSC_BASE + 0x00000008 */
  914. uint32_t isp_lsc_b_table_addr; /*!< Table RAM Address for blue component (rwhh) MRV_LSC_BASE + 0x0000000c */
  915. uint32_t isp_lsc_gb_table_addr; /*!< Table RAM Address for green (blue) component (rwhh) MRV_LSC_BASE + 0x00000010 */
  916. uint32_t isp_lsc_r_table_data; /*!< Sample table red (rw) MRV_LSC_BASE + 0x00000014 */
  917. uint32_t isp_lsc_gr_table_data; /*!< Sample table green (red) (rw) MRV_LSC_BASE + 0x00000018 */
  918. uint32_t isp_lsc_b_table_data; /*!< Sample table blue (rw) MRV_LSC_BASE + 0x0000001c */
  919. uint32_t isp_lsc_gb_table_data; /*!< Sample table green (blue) (rw) MRV_LSC_BASE + 0x00000020 */
  920. uint32_t isp_lsc_xgrad_01; /*!< Gradient table x (rw) MRV_LSC_BASE + 0x00000024 */
  921. uint32_t isp_lsc_xgrad_23; /*!< Gradient table x (rw) MRV_LSC_BASE + 0x00000028 */
  922. uint32_t isp_lsc_xgrad_45; /*!< Gradient table x (rw) MRV_LSC_BASE + 0x0000002c */
  923. uint32_t isp_lsc_xgrad_67; /*!< Gradient table x (rw) MRV_LSC_BASE + 0x00000030 */
  924. uint32_t isp_lsc_ygrad_01; /*!< Gradient table y (rw) MRV_LSC_BASE + 0x00000034 */
  925. uint32_t isp_lsc_ygrad_23; /*!< Gradient table y (rw) MRV_LSC_BASE + 0x00000038 */
  926. uint32_t isp_lsc_ygrad_45; /*!< Gradient table y (rw) MRV_LSC_BASE + 0x0000003c */
  927. uint32_t isp_lsc_ygrad_67; /*!< Gradient table y (rw) MRV_LSC_BASE + 0x00000040 */
  928. uint32_t isp_lsc_xsize_01; /*!< Size table (rw) MRV_LSC_BASE + 0x00000044 */
  929. uint32_t isp_lsc_xsize_23; /*!< Size table (rw) MRV_LSC_BASE + 0x00000048 */
  930. uint32_t isp_lsc_xsize_45; /*!< Size table (rw) MRV_LSC_BASE + 0x0000004c */
  931. uint32_t isp_lsc_xsize_67; /*!< Size table (rw) MRV_LSC_BASE + 0x00000050 */
  932. uint32_t isp_lsc_ysize_01; /*!< Size table (rw) MRV_LSC_BASE + 0x00000054 */
  933. uint32_t isp_lsc_ysize_23; /*!< Size table (rw) MRV_LSC_BASE + 0x00000058 */
  934. uint32_t isp_lsc_ysize_45; /*!< Size table (rw) MRV_LSC_BASE + 0x0000005c */
  935. uint32_t isp_lsc_ysize_67; /*!< Size table (rw) MRV_LSC_BASE + 0x00000060 */
  936. uint32_t isp_lsc_table_sel; /*!< Lens shade table set selection (rw) MRV_LSC_BASE + 0x00000064 */
  937. uint32_t isp_lsc_status; /*!< Lens shade status (r) MRV_LSC_BASE + 0x00000068 */
  938. uint32_t _notused_23[(0x00002300 - 0x0000226c) / 4]; /* gap in address space */
  939. uint32_t isp_is_ctrl; /*!< Image Stabilization Control Register (rw) MRV_IS_BASE + 0x00000000 */
  940. uint32_t isp_is_recenter; /*!< Recenter register (rw) MRV_IS_BASE + 0x00000004 */
  941. uint32_t isp_is_h_offs; /*!< Horizontal offset of output window (rw) MRV_IS_BASE + 0x00000008 */
  942. uint32_t isp_is_v_offs; /*!< Vertical offset of output window (rw) MRV_IS_BASE + 0x0000000c */
  943. uint32_t isp_is_h_size; /*!< Output horizontal picture size (rw) MRV_IS_BASE + 0x00000010 */
  944. uint32_t isp_is_v_size; /*!< Output vertical picture size (rw) MRV_IS_BASE + 0x00000014 */
  945. uint32_t isp_is_max_dx; /*!< Maximum Horizontal Displacement (rw) MRV_IS_BASE + 0x00000018 */
  946. uint32_t isp_is_max_dy; /*!< Maximum Vertical Displacement (rw) MRV_IS_BASE + 0x0000001c */
  947. uint32_t isp_is_displace; /*!< Camera displacement (rw) MRV_IS_BASE + 0x00000020 */
  948. uint32_t isp_is_h_offs_shd; /*!< current horizontal offset of output window (shadow register) (r) MRV_IS_BASE + 0x00000024 */
  949. uint32_t isp_is_v_offs_shd; /*!< current vertical offset of output window (shadow register) (r) MRV_IS_BASE + 0x00000028 */
  950. uint32_t isp_is_h_size_shd; /*!< current output horizontal picture size (shadow register) (r) MRV_IS_BASE + 0x0000002c */
  951. uint32_t isp_is_v_size_shd; /*!< current output vertical picture size (shadow register) (r) MRV_IS_BASE + 0x00000030 */
  952. #ifdef ISP_RAWIS
  953. uint32_t _notused_23_1[(0x00002340 - 0x00002334) / 4]; /* gap in address space */
  954. uint32_t isp_raw_is_ctrl; /*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002340 */
  955. uint32_t isp_raw_is_recenter; /*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002344 */
  956. uint32_t isp_raw_is_h_offs; /*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002348 */
  957. uint32_t isp_raw_is_v_offs; /*!< current output vertical picture size shadow register r MRV_IS_BASE0x0000234c */
  958. uint32_t isp_raw_is_h_size; /*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002350 */
  959. uint32_t isp_raw_is_v_size; /*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002354 */
  960. uint32_t isp_raw_is_max_dx; /*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002358 */
  961. uint32_t isp_raw_is_max_dy; /*!< current output vertical picture size shadow register r MRV_IS_BASE0x0000235c */
  962. uint32_t isp_raw_is_displace; /*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002360 */
  963. uint32_t isp_raw_is_h_offs_shd; /*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002364 */
  964. uint32_t isp_raw_is_v_offs_shd; /*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002368 */
  965. uint32_t isp_raw_is_h_size_shd; /*!< current output vertical picture size shadow register r MRV_IS_BASE0x0000236c */
  966. uint32_t isp_raw_is_v_size_shd; /*!< current output vertical picture size shadow register r MRV_IS_BASE0x00002370 */
  967. uint32_t _notused_24[(0x00002400 - 0x00002374) / 4]; /* gap in address space */
  968. #else
  969. uint32_t _notused_24[(0x00002400 - 0x00002334) / 4]; /* gap in address space */
  970. #endif
  971. uint32_t isp_hist_prop; /*!< Histogram properties (rw) MRV_HIST_BASE + 0x00000000 */
  972. uint32_t isp_hist_h_offs; /*!< Histogram window horizontal offset for first window of 25 sub-windows (rw) MRV_HIST_BASE + 0x00000004 */
  973. uint32_t isp_hist_v_offs; /*!< Histogram window vertical offset for first window of 25 sub-windows (rw) MRV_HIST_BASE + 0x00000008 */
  974. uint32_t isp_hist_h_size; /*!< Horizontal (sub-)window size (rw) MRV_HIST_BASE + 0x0000000c */
  975. uint32_t isp_hist_v_size; /*!< Vertical (sub-)window size (rw) MRV_HIST_BASE + 0x00000010 */
  976. histogram_measurement_result_t histogram_measurement_result_arr[HISTOGRAM_MEASUREMENT_RESULT_ARR_SIZE]; /*!< histogram_measurement_result MRV_HIST_BASE + 20 + (n*0x4) (n=0..15) */
  977. uint32_t isp_hist_weight_00to30; /*!< Weighting factor for sub-windows (rw) MRV_HIST_BASE + 0x00000054 */
  978. uint32_t isp_hist_weight_40to21; /*!< Weighting factor for sub-windows (rw) MRV_HIST_BASE + 0x00000058 */
  979. uint32_t isp_hist_weight_31to12; /*!< Weighting factor for sub-windows (rw) MRV_HIST_BASE + 0x0000005c */
  980. uint32_t isp_hist_weight_22to03; /*!< Weighting factor for sub-windows (rw) MRV_HIST_BASE + 0x00000060 */
  981. uint32_t isp_hist_weight_13to43; /*!< Weighting factor for sub-windows (rw) MRV_HIST_BASE + 0x00000064 */
  982. uint32_t isp_hist_weight_04to34; /*!< Weighting factor for sub-windows (rw) MRV_HIST_BASE + 0x00000068 */
  983. uint32_t isp_hist_weight_44; /*!< Weighting factor for sub-windows (rw) MRV_HIST_BASE + 0x0000006c */
  984. uint32_t _notused_25[(0x00002500 - 0x00002470) / 4]; /* gap in address space */
  985. uint32_t isp_filt_mode; /*!< mode control register for the filter block (rw) MRV_FILT_BASE + 0x00000000 */
  986. uint32_t _notused_26[(0x00002528 - 0x00002504) / 4]; /* gap in address space */
  987. uint32_t isp_filt_thresh_bl0; /*!< Blurring threshold 0 (rw) MRV_FILT_BASE + 0x00000028 */
  988. uint32_t isp_filt_thresh_bl1; /*!< Blurring threshold 1 (rw) MRV_FILT_BASE + 0x0000002c */
  989. uint32_t isp_filt_thresh_sh0; /*!< Sharpening threshold 0 (rw) MRV_FILT_BASE + 0x00000030 */
  990. uint32_t isp_filt_thresh_sh1; /*!< Sharpening threshold 1 (rw) MRV_FILT_BASE + 0x00000034 */
  991. uint32_t isp_filt_lum_weight; /*!< Parameters for luminance weight function (rw) MRV_FILT_BASE + 0x00000038 */
  992. uint32_t isp_filt_fac_sh1; /*!< filter factor sharp1 (rw) MRV_FILT_BASE + 0x0000003c */
  993. uint32_t isp_filt_fac_sh0; /*!< filter factor sharp0 (rw) MRV_FILT_BASE + 0x00000040 */
  994. uint32_t isp_filt_fac_mid; /*!< filter factor middle (rw) MRV_FILT_BASE + 0x00000044 */
  995. uint32_t isp_filt_fac_bl0; /*!< Parameter for blur 0 filter (rw) MRV_FILT_BASE + 0x00000048 */
  996. uint32_t isp_filt_fac_bl1; /*!< Parameter for blur 1 filter (rw) MRV_FILT_BASE + 0x0000004c */
  997. uint32_t _notused_27[(0x00002580 - 0x00002550) / 4]; /* gap in address space */
  998. uint32_t isp_cac_ctrl; /*!< Control register for chromatic aberration correction (rw) MRV_CAC_BASE + 0x00000000 */
  999. uint32_t isp_cac_count_start; /*!< Preload values for CAC pixel and line counter (rw) MRV_CAC_BASE + 0x00000004 */
  1000. uint32_t isp_cac_a; /*!< Linear Parameters for radial shift calculation (rw) MRV_CAC_BASE + 0x00000008 */
  1001. uint32_t isp_cac_b; /*!< Square Parameters for radial shift calculation (rw) MRV_CAC_BASE + 0x0000000c */
  1002. uint32_t isp_cac_c; /*!< Cubical Parameters for radial shift calculation (rw) MRV_CAC_BASE + 0x00000010 */
  1003. uint32_t isp_cac_x_norm; /*!< Normalization parameters for calculation of image coordinate x_d relative to optical center (rw) MRV_CAC_BASE + 0x00000014 */
  1004. uint32_t isp_cac_y_norm; /*!< Normalization parameters for calculation of image coordinate y_d relative to optical center (rw) MRV_CAC_BASE + 0x00000018 */
  1005. uint32_t _notused_28[(0x00002600 - 0x0000259c) / 4]; /* gap in address space */
  1006. uint32_t isp_exp_ctrl; /*!< Exposure control (rw) MRV_AE_BASE + 0x00000000 */
  1007. uint32_t isp_exp_h_offset; /*!< Horizontal offset for first block (rw) MRV_AE_BASE + 0x00000004 */
  1008. uint32_t isp_exp_v_offset; /*!< Vertical offset for first block (rw) MRV_AE_BASE + 0x00000008 */
  1009. uint32_t isp_exp_h_size; /*!< Horizontal size of one block (rw) MRV_AE_BASE + 0x0000000c */
  1010. uint32_t isp_exp_v_size; /*!< Vertical size of one block (rw) MRV_AE_BASE + 0x00000010 */
  1011. uint32_t isp_exp_mean_00; /*!< Mean luminance value of block 00 (r) MRV_AE_BASE + 0x00000014 */
  1012. uint32_t isp_exp_mean_10; /*!< Mean luminance value of block 10 (r) MRV_AE_BASE + 0x00000018 */
  1013. uint32_t isp_exp_mean_20; /*!< Mean luminance value of block 20 (r) MRV_AE_BASE + 0x0000001c */
  1014. uint32_t isp_exp_mean_30; /*!< Mean luminance value of block 30 (r) MRV_AE_BASE + 0x00000020 */
  1015. uint32_t isp_exp_mean_40; /*!< Mean luminance value of block 40 (r) MRV_AE_BASE + 0x00000024 */
  1016. uint32_t isp_exp_mean_01; /*!< Mean luminance value of block 01 (r) MRV_AE_BASE + 0x00000028 */
  1017. uint32_t isp_exp_mean_11; /*!< Mean luminance value of block 11 (r) MRV_AE_BASE + 0x0000002c */
  1018. uint32_t isp_exp_mean_21; /*!< Mean luminance value of block 21 (r) MRV_AE_BASE + 0x00000030 */
  1019. uint32_t isp_exp_mean_31; /*!< Mean luminance value of block 31 (r) MRV_AE_BASE + 0x00000034 */
  1020. uint32_t isp_exp_mean_41; /*!< Mean luminance value of block 41 (r) MRV_AE_BASE + 0x00000038 */
  1021. uint32_t isp_exp_mean_02; /*!< Mean luminance value of block 02 (r) MRV_AE_BASE + 0x0000003c */
  1022. uint32_t isp_exp_mean_12; /*!< Mean luminance value of block 12 (r) MRV_AE_BASE + 0x00000040 */
  1023. uint32_t isp_exp_mean_22; /*!< Mean luminance value of block 22 (r) MRV_AE_BASE + 0x00000044 */
  1024. uint32_t isp_exp_mean_32; /*!< Mean luminance value of block 32 (r) MRV_AE_BASE + 0x00000048 */
  1025. uint32_t isp_exp_mean_42; /*!< Mean luminance value of block 42 (r) MRV_AE_BASE + 0x0000004c */
  1026. uint32_t isp_exp_mean_03; /*!< Mean luminance value of block 03 (r) MRV_AE_BASE + 0x00000050 */
  1027. uint32_t isp_exp_mean_13; /*!< Mean luminance value of block 13 (r) MRV_AE_BASE + 0x00000054 */
  1028. uint32_t isp_exp_mean_23; /*!< Mean luminance value of block 23 (r) MRV_AE_BASE + 0x00000058 */
  1029. uint32_t isp_exp_mean_33; /*!< Mean luminance value of block 33 (r) MRV_AE_BASE + 0x0000005c */
  1030. uint32_t isp_exp_mean_43; /*!< Mean luminance value of block 43 (r) MRV_AE_BASE + 0x00000060 */
  1031. uint32_t isp_exp_mean_04; /*!< Mean luminance value of block 04 (r) MRV_AE_BASE + 0x00000064 */
  1032. uint32_t isp_exp_mean_14; /*!< Mean luminance value of block 14 (r) MRV_AE_BASE + 0x00000068 */
  1033. uint32_t isp_exp_mean_24; /*!< Mean luminance value of block 24 (r) MRV_AE_BASE + 0x0000006c */
  1034. uint32_t isp_exp_mean_34; /*!< Mean luminance value of block 34 (r) MRV_AE_BASE + 0x00000070 */
  1035. uint32_t isp_exp_mean_44; /*!< Mean luminance value of block 44 (r) MRV_AE_BASE + 0x00000074 */
  1036. #ifdef ISP_AE_SHADOW
  1037. uint32_t isp_exp_h_offset_shd; /*!< Mean luminance value of block 44 (r) MRV_AE_BASE + 0x00000078 */
  1038. uint32_t isp_exp_v_offset_shd; /*!< Mean luminance value of block 44 (r) MRV_AE_BASE + 0x0000007C */
  1039. uint32_t isp_exp_h_size_shd; /*!< Mean luminance value of block 44 (r) MRV_AE_BASE + 0x00000080 */
  1040. uint32_t isp_exp_v_size_shd; /*!< Mean luminance value of block 44 (r) MRV_AE_BASE + 0x00000084 */
  1041. uint32_t _notused_isp_exp[(0x000026A0 - 0x00002688) / 4];
  1042. uint32_t isp_expv2_ctrl; /* 0x000026A0; */
  1043. uint32_t isp_expv2_offset; /* 0x000026A4; */
  1044. uint32_t isp_expv2_size; /* 0x000026A8; */
  1045. uint32_t isp_expv2_size_invert; /* 0x000026AC; */
  1046. uint32_t isp_expv2_pixel_weight; /* 0x000026B0; */
  1047. uint32_t isp_expv2_offset_shd; /* 0x000026B4; */
  1048. uint32_t isp_expv2_size_shd; /* 0x000026B8; */
  1049. uint32_t isp_expv2_size_invert_shd; /* 0x000026BC; */
  1050. uint32_t _notused_29[(0x00002700 - 0x000026C0) / 4]; /* gap in address space */
  1051. #else
  1052. uint32_t _notused_isp_exp[(0x00002680 - 0x00002678) / 4];
  1053. uint32_t isp_expv2_ctrl; /* 0x00002680; */
  1054. uint32_t isp_expv2_offset; /* 0x00002684; */
  1055. uint32_t isp_expv2_size; /* 0x00002688; */
  1056. uint32_t isp_expv2_size_invert; /* 0x0000268c; */
  1057. uint32_t isp_expv2_pixel_weight; /* 0x00002690; */
  1058. uint32_t _notused_29[(0x00002700 - 0x00002694) / 4]; /* gap in address space */
  1059. #endif
  1060. uint32_t isp_bls_ctrl; /*!< global control register (rw) MRV_BLS_BASE + 0x00000000 */
  1061. uint32_t isp_bls_samples; /*!< samples register (rw) MRV_BLS_BASE + 0x00000004 */
  1062. uint32_t isp_bls_h1_start; /*!< window 1 horizontal start (rw) MRV_BLS_BASE + 0x00000008 */
  1063. uint32_t isp_bls_h1_stop; /*!< window 1 horizontal stop (rw) MRV_BLS_BASE + 0x0000000c */
  1064. uint32_t isp_bls_v1_start; /*!< window 1 vertical start (rw) MRV_BLS_BASE + 0x00000010 */
  1065. uint32_t isp_bls_v1_stop; /*!< window 1 vertical stop (rw) MRV_BLS_BASE + 0x00000014 */
  1066. uint32_t isp_bls_h2_start; /*!< window 2 horizontal start (rw) MRV_BLS_BASE + 0x00000018 */
  1067. uint32_t isp_bls_h2_stop; /*!< window 2 horizontal stop (rw) MRV_BLS_BASE + 0x0000001c */
  1068. uint32_t isp_bls_v2_start; /*!< window 2 vertical start (rw) MRV_BLS_BASE + 0x00000020 */
  1069. uint32_t isp_bls_v2_stop; /*!< window 2 vertical stop (rw) MRV_BLS_BASE + 0x00000024 */
  1070. uint32_t isp_bls_a_fixed; /*!< fixed black level A (rw) MRV_BLS_BASE + 0x00000028 */
  1071. uint32_t isp_bls_b_fixed; /*!< fixed black level B (rw) MRV_BLS_BASE + 0x0000002c */
  1072. uint32_t isp_bls_c_fixed; /*!< fixed black level C (rw) MRV_BLS_BASE + 0x00000030 */
  1073. uint32_t isp_bls_d_fixed; /*!< fixed black level D (rw) MRV_BLS_BASE + 0x00000034 */
  1074. uint32_t isp_bls_a_measured; /*!< measured black level A (r) MRV_BLS_BASE + 0x00000038 */
  1075. uint32_t isp_bls_b_measured; /*!< measured black level B (r) MRV_BLS_BASE + 0x0000003c */
  1076. uint32_t isp_bls_c_measured; /*!< measured black level C (r) MRV_BLS_BASE + 0x00000040 */
  1077. uint32_t isp_bls_d_measured; /*!< measured black level D (r) MRV_BLS_BASE + 0x00000044 */
  1078. uint32_t _notused_30[(0x00002800 - 0x00002748) / 4]; /* gap in address space */
  1079. uint32_t isp_dpf_mode; /*!< Mode control for Denoising Pre-Filter block (rw) MRV_DPF_BASE + 0x00000000 */
  1080. uint32_t isp_dpf_strength_r; /*!< filter strength of the RED filter (rw) MRV_DPF_BASE + 0x00000004 */
  1081. uint32_t isp_dpf_strength_g; /*!< filter strength of the GREEN filter (rw) MRV_DPF_BASE + 0x00000008 */
  1082. uint32_t isp_dpf_strength_b; /*!< filter strength of the BLUE filter (rw) MRV_DPF_BASE + 0x0000000c */
  1083. uint32_t isp_dpf_s_weight_g_1_4; /*!< Spatial Weights green channel 1 2 3 4 (rw) MRV_DPF_BASE + 0x00000010 */
  1084. uint32_t isp_dpf_s_weight_g_5_6; /*!< Spatial Weights green channel 5 6 (rw) MRV_DPF_BASE + 0x00000014 */
  1085. uint32_t isp_dpf_s_weight_rb_1_4; /*!< Spatial Weights red/blue channels 1 2 3 4 (rw) MRV_DPF_BASE + 0x00000018 */
  1086. uint32_t isp_dpf_s_weight_rb_5_6; /*!< Spatial Weights red/blue channels 5 6 (rw) MRV_DPF_BASE + 0x0000001c */
  1087. nlf_lookup_table_block_t nlf_lookup_table_block_arr[NLF_LOOKUP_TABLE_BLOCK_ARR_SIZE]; /*!< nlf_lookup_table_block MRV_DPF_BASE + 32 + (n*0x4) (n=0..16) */
  1088. uint32_t isp_dpf_nf_gain_r; /*!< noise function gain for red pixels (rw) MRV_DPF_BASE + 0x00000064 */
  1089. uint32_t isp_dpf_nf_gain_gr; /*!< noise function gain for green in red pixels (rw) MRV_DPF_BASE + 0x00000068 */
  1090. uint32_t isp_dpf_nf_gain_gb; /*!< noise function gain for green in blue pixels (rw) MRV_DPF_BASE + 0x0000006c */
  1091. uint32_t isp_dpf_nf_gain_b; /*!< noise function gain for blue pixels (rw) MRV_DPF_BASE + 0x00000070 */
  1092. uint32_t _notused_31[(0x00002900 - 0x00002874) / 4]; /* gap in address space */
  1093. uint32_t isp_dpcc_mode; /*!< Mode control for DPCC detection unit (rw) MRV_DPCC_BASE + 0x00000000 */
  1094. uint32_t isp_dpcc_output_mode; /*!< Interpolation mode for correction unit (rw) MRV_DPCC_BASE + 0x00000004 */
  1095. uint32_t isp_dpcc_set_use; /*!< DPCC methods set usage for detection (rw) MRV_DPCC_BASE + 0x00000008 */
  1096. uint32_t isp_dpcc_methods_set_1; /*!< Methods enable bits for SET_1 (rw) MRV_DPCC_BASE + 0x0000000c */
  1097. uint32_t isp_dpcc_methods_set_2; /*!< Methods enable bits for SET_2 (rw) MRV_DPCC_BASE + 0x00000010 */
  1098. uint32_t isp_dpcc_methods_set_3; /*!< Methods enable bits for SET_3 (rw) MRV_DPCC_BASE + 0x00000014 */
  1099. uint32_t isp_dpcc_line_thresh_1; /*!< Line threshold SET_1 (rw) MRV_DPCC_BASE + 0x00000018 */
  1100. uint32_t isp_dpcc_line_mad_fac_1; /*!< Mean Absolute Difference (MAD) factor for Line check set 1 (rw) MRV_DPCC_BASE + 0x0000001c */
  1101. uint32_t isp_dpcc_pg_fac_1; /*!< Peak gradient factor for set 1 (rw) MRV_DPCC_BASE + 0x00000020 */
  1102. uint32_t isp_dpcc_rnd_thresh_1; /*!< Rank Neighbor Difference threshold for set 1 (rw) MRV_DPCC_BASE + 0x00000024 */
  1103. uint32_t isp_dpcc_rg_fac_1; /*!< Rank gradient factor for set 1 (rw) MRV_DPCC_BASE + 0x00000028 */
  1104. uint32_t isp_dpcc_line_thresh_2; /*!< Line threshold set 2 (rw) MRV_DPCC_BASE + 0x0000002c */
  1105. uint32_t isp_dpcc_line_mad_fac_2; /*!< Mean Absolute Difference (MAD) factor for Line check set 2 (rw) MRV_DPCC_BASE + 0x00000030 */
  1106. uint32_t isp_dpcc_pg_fac_2; /*!< Peak gradient factor for set 2 (rw) MRV_DPCC_BASE + 0x00000034 */
  1107. uint32_t isp_dpcc_rnd_thresh_2; /*!< Rank Neighbor Difference threshold for set 2 (rw) MRV_DPCC_BASE + 0x00000038 */
  1108. uint32_t isp_dpcc_rg_fac_2; /*!< Rank gradient factor for set 2 (rw) MRV_DPCC_BASE + 0x0000003c */
  1109. uint32_t isp_dpcc_line_thresh_3; /*!< Line threshold set 3 (rw) MRV_DPCC_BASE + 0x00000040 */
  1110. uint32_t isp_dpcc_line_mad_fac_3; /*!< Mean Absolute Difference (MAD) factor for Line check set 3 (rw) MRV_DPCC_BASE + 0x00000044 */
  1111. uint32_t isp_dpcc_pg_fac_3; /*!< Peak gradient factor for set 3 (rw) MRV_DPCC_BASE + 0x00000048 */
  1112. uint32_t isp_dpcc_rnd_thresh_3; /*!< Rank Neighbor Difference threshold for set 3 (rw) MRV_DPCC_BASE + 0x0000004c */
  1113. uint32_t isp_dpcc_rg_fac_3; /*!< Rank gradient factor for set 3 (rw) MRV_DPCC_BASE + 0x00000050 */
  1114. uint32_t isp_dpcc_ro_limits; /*!< Rank Order Limits (rw) MRV_DPCC_BASE + 0x00000054 */
  1115. uint32_t isp_dpcc_rnd_offs; /*!< Differential Rank Offsets for Rank Neighbor Difference (rw) MRV_DPCC_BASE + 0x00000058 */
  1116. uint32_t isp_dpcc_bpt_ctrl; /*!< bad pixel table settings (rw) MRV_DPCC_BASE + 0x0000005c */
  1117. uint32_t isp_dpcc_bpt_number; /*!< Number of entries for bad pixel table (table based correction) (rw) MRV_DPCC_BASE + 0x00000060 */
  1118. uint32_t isp_dpcc_bpt_addr; /*!< TABLE Start Address for table-based correction algorithm (rwhh) MRV_DPCC_BASE + 0x00000064 */
  1119. uint32_t isp_dpcc_bpt_data; /*!< TABLE DATA register for read and write access of table RAM (rwhh) MRV_DPCC_BASE + 0x00000068 */
  1120. uint32_t _notused_32[(0x00002a00 - 0x0000296c) / 4]; /* gap in address space */
  1121. uint32_t isp_wdr_ctrl; /*!< Control Bits for Wide Dynamic Range Unit (rw) MRV_WDR_BASE + 0x00000000 */
  1122. uint32_t isp_wdr_tonecurve_1; /*!< Tone Curve sample points dYn definition (part 1) (rw) MRV_WDR_BASE + 0x00000004 */
  1123. uint32_t isp_wdr_tonecurve_2; /*!< Tone Curve sample points dYn definition (part 2) (rw) MRV_WDR_BASE + 0x00000008 */
  1124. uint32_t isp_wdr_tonecurve_3; /*!< Tone Curve sample points dYn definition (part 3) (rw) MRV_WDR_BASE + 0x0000000c */
  1125. uint32_t isp_wdr_tonecurve_4; /*!< Tone Curve sample points dYn definition (part 4) (rw) MRV_WDR_BASE + 0x00000010 */
  1126. wdr_tone_mapping_curve_y_block_t wdr_tone_mapping_curve_y_block_arr[WDR_TONE_MAPPING_CURVE_Y_BLOCK_ARR_SIZE]; /*!< wdr_tone_mapping_curve_y_block MRV_WDR_BASE + 20 + (n*0x4) (n=0..32) */
  1127. uint32_t isp_wdr_offset; /*!< Offset values for RGB path (rw) MRV_WDR_BASE + 0x00000098 */
  1128. uint32_t isp_wdr_deltamin; /*!< DeltaMin Threshold and Strength factor (rw) MRV_WDR_BASE + 0x0000009c */
  1129. uint32_t isp_wdr_tonecurve_1_shd; /*!< Tone Curve sample points dYn definition shadow register (part 1) (r) MRV_WDR_BASE + 0x000000a0 */
  1130. uint32_t isp_wdr_tonecurve_2_shd; /*!< Tone Curve sample points dYn definition shadow register (part 2) (r) MRV_WDR_BASE + 0x000000a4 */
  1131. uint32_t isp_wdr_tonecurve_3_shd; /*!< Tone Curve sample points dYn definition shadow register (part 3) (r) MRV_WDR_BASE + 0x000000a8 */
  1132. uint32_t isp_wdr_tonecurve_4_shd; /*!< Tone Curve sample points dYn definition shadow register(part 4) (r) MRV_WDR_BASE + 0x000000ac */
  1133. wdr_tone_mapping_curve_y_shd_block_t wdr_tone_mapping_curve_y_shd_block_arr[WDR_TONE_MAPPING_CURVE_Y_SHD_BLOCK_ARR_SIZE]; /*!< wdr_tone_mapping_curve_y_shd_block MRV_WDR_BASE + 176 + (n*0x4) (n=0..32) */
  1134. uint32_t _notused_33[(0x00002c00 - 0x00002b34) / 4]; /* gap in address space */
  1135. uint32_t awb_meas_mode; /*!< AWB Measure Mode (rw) ISP_AWB_BASE + 0x00000000 */
  1136. uint32_t awb_meas_h_offs; /*!< AWB window horizontal offset (rw) ISP_AWB_BASE + 0x00000004 */
  1137. uint32_t awb_meas_v_offs; /*!< AWB window vertical offset (rw) ISP_AWB_BASE + 0x00000008 */
  1138. uint32_t awb_meas_h_size; /*!< Horizontal window size (rw) ISP_AWB_BASE + 0x0000000c */
  1139. uint32_t awb_meas_v_size; /*!< Vertical window size (rw) ISP_AWB_BASE + 0x00000010 */
  1140. uint32_t awb_meas_r_min_max; /*!< Min Max Compare Red (rw) ISP_AWB_BASE + 0x00000014 */
  1141. uint32_t awb_meas_g_min_max; /*!< Min Max Compare Green (rw) ISP_AWB_BASE + 0x00000018 */
  1142. uint32_t awb_meas_b_min_max; /*!< Min Max Compare Blue (rw) ISP_AWB_BASE + 0x0000001c */
  1143. uint32_t awb_meas_divider_min; /*!< Min Compare Divider (rw) ISP_AWB_BASE + 0x00000020 */
  1144. uint32_t awb_meas_csc_coeff[9]; /*!< Color conversion coefficient 0 (rw) ISP_AWB_BASE + 0x00000024 */
  1145. elawb_ellipse_pt awb_meas_center[8]; /*!< Ellipse 1 Center X (rw) ISP_AWB_BASE + 0x00000048 */
  1146. elawb_ellipse_axis awb_meas_axis[8]; /*!< Ellipse 1 coefficient a1 (rw) ISP_AWB_BASE + 0x00000088 */
  1147. uint32_t awb_meas_rmax[8]; /*!< Ellipse 1 r_max (rw) ISP_AWB_BASE + 0x00000108 */
  1148. uint32_t awb_meas_counter[8]; /*!< AWB Counter 1 (r) ISP_AWB_BASE + 0x00000128 */
  1149. AWB_MEAS_ACCU_t AWB_MEAS_ACCU_arr[AWB_MEAS_ACCU_ARR_SIZE]; /*!< AWB_MEAS_ACCU ISP_AWB_BASE + 328 + (n*0x4) (n=0..23) */
  1150. uint32_t _notused_34[(0x00002e00 - 0x00002da8) / 4]; /* gap in address space */
  1151. uint32_t isp64_hist_ctrl; /*!< Histogram control (rw) MRV_HIST_BASE + 0x00000000 */
  1152. uint32_t isp64_hist_prop; /*!< Histogram properties (sh_rw) MRV_HIST_BASE + 0x00000004 */
  1153. uint32_t isp64_hist_subsampling; /*!< Subsampling properties (sh_rw) MRV_HIST_BASE + 0x00000008 */
  1154. uint32_t isp64_hist_coeff_r; /*!< Color conversion coefficient for red (sh_rw) MRV_HIST_BASE + 0x0000000c */
  1155. uint32_t isp64_hist_coeff_g; /*!< Color conversion coefficient for green (sh_rw) MRV_HIST_BASE + 0x00000010 */
  1156. uint32_t isp64_hist_coeff_b; /*!< Color conversion coefficient for blue (sh_rw) MRV_HIST_BASE + 0x00000014 */
  1157. uint32_t isp64_hist_h_offs; /*!< Histogram window horizontal offset for first window of 25 sub-windows (sh_rw) MRV_HIST_BASE + 0x00000018 */
  1158. uint32_t isp64_hist_v_offs; /*!< Histogram window vertical offset for first window of 25 sub-windows (sh_rw) MRV_HIST_BASE + 0x0000001c */
  1159. uint32_t isp64_hist_h_size; /*!< Horizontal (sub-)window size (sh_rw) MRV_HIST_BASE + 0x00000020 */
  1160. uint32_t isp64_hist_v_size; /*!< Vertical (sub-)window size (sh_rw) MRV_HIST_BASE + 0x00000024 */
  1161. uint32_t isp64_hist_sample_range; /*!< Weighting factor for sub-windows (sh_rw) MRV_HIST_BASE + 0x00000028 */
  1162. uint32_t isp64_hist_weight_00to30; /*!< Weighting factor for sub-windows (sh_rw) MRV_HIST_BASE + 0x0000002c */
  1163. uint32_t isp64_hist_weight_40to21; /*!< Weighting factor for sub-windows (sh_rw) MRV_HIST_BASE + 0x00000030 */
  1164. uint32_t isp64_hist_weight_31to12; /*!< Weighting factor for sub-windows (sh_rw) MRV_HIST_BASE + 0x00000034 */
  1165. uint32_t isp64_hist_weight_22to03; /*!< Weighting factor for sub-windows (sh_rw) MRV_HIST_BASE + 0x00000038 */
  1166. uint32_t isp64_hist_weight_13to43; /*!< Weighting factor for sub-windows (sh_rw) MRV_HIST_BASE + 0x0000003c */
  1167. uint32_t isp64_hist_weight_04to34; /*!< Weighting factor for sub-windows (sh_rw) MRV_HIST_BASE + 0x00000040 */
  1168. uint32_t isp64_hist_weight_44; /*!< Weighting factor for sub-windows (sh_rw) MRV_HIST_BASE + 0x00000044 */
  1169. uint32_t isp64_hist_forced_upd_start_line; /*!< Forced update start line limit (rw) MRV_HIST_BASE + 0x00000048 */
  1170. uint32_t isp64_hist_forced_update; /*!< Histogram forced update (w) MRV_HIST_BASE + 0x0000004c */
  1171. uint32_t isp64_hist_vstart_status; /*!< Forced update start line status (sh_r) MRV_HIST_BASE + 0x00000050 */
  1172. isp64_histogram_measurement_result_t isp64_histogram_measurement_result_arr[ISP64_HISTOGRAM_MEASUREMENT_RESULT_ARR_SIZE]; /*!< isp64_histogram_measurement_result MRV_HIST_BASE + 84 + (n*0x4) (n=0..31) */
  1173. uint32_t _notused_35[(0x00002f00 - 0x00002ed4) / 4]; /* gap in address space */
  1174. uint32_t isp_vsm_mode; /*!< VS Measure Mode (rw) ISP_VSM_BASE + 0x00000000 */
  1175. uint32_t isp_vsm_h_offs; /*!< VSM window horizontal offset (rw) ISP_VSM_BASE + 0x00000004 */
  1176. uint32_t isp_vsm_v_offs; /*!< VSM window vertical offset (rw) ISP_VSM_BASE + 0x00000008 */
  1177. uint32_t isp_vsm_h_size; /*!< Horizontal measure window size (rw) ISP_VSM_BASE + 0x0000000c */
  1178. uint32_t isp_vsm_v_size; /*!< Vertical measure window size (rw) ISP_VSM_BASE + 0x00000010 */
  1179. uint32_t isp_vsm_h_segments; /*!< Iteration 1 horizontal segments (rw) ISP_VSM_BASE + 0x00000014 */
  1180. uint32_t isp_vsm_v_segments; /*!< Iteration 1 vertical segments (rw) ISP_VSM_BASE + 0x00000018 */
  1181. uint32_t isp_vsm_delta_h; /*!< estimated horizontal displacement (r) ISP_VSM_BASE + 0x0000001c */
  1182. uint32_t isp_vsm_delta_v; /*!< estimated vertical displacement (r) ISP_VSM_BASE + 0x00000020 */
  1183. uint32_t _notused_36[(0x00003000 - 0x00002f24) / 4]; /* gap in address space */
  1184. #ifdef ISP_GCMONO
  1185. uint32_t isp_gcmono_ctrl; /*!< GCMONO CTRL for ISP Nano MRV_GCMONO_BASE + 0x00000000 */
  1186. uint32_t isp_gcmono_para_base; /*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE + 0x00000004 */
  1187. uint32_t _notused_37_0[(0x00003040 - 0x00003008) / 4]; /* gap in address space */
  1188. uint32_t isp_gcmono_px_0; /*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003040 */
  1189. uint32_t isp_gcmono_px_1; /*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003044 */
  1190. uint32_t isp_gcmono_px_2; /*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003048 */
  1191. uint32_t isp_gcmono_px_3; /*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x0000304C */
  1192. uint32_t isp_gcmono_px_4; /*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003050 */
  1193. uint32_t isp_gcmono_px_5; /*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003054 */
  1194. uint32_t isp_gcmono_px_6; /*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003058 */
  1195. uint32_t isp_gcmono_px_7; /*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x0000305C */
  1196. uint32_t isp_gcmono_px_8; /*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003060 */
  1197. uint32_t isp_gcmono_px_9; /*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003064 */
  1198. uint32_t isp_gcmono_px_10; /*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003068 */
  1199. uint32_t isp_gcmono_y_addr; /*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x0000306C */
  1200. uint32_t isp_gcmono_y_write_data; /*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003070 */
  1201. uint32_t isp_gcmono_x_addr; /*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003074 */
  1202. uint32_t isp_gcmono_x_write_data; /*!< GCMONO curve lut base for ISP Nano MRV_GCMONO_BASE +0x00003078 */
  1203. uint32_t _notused_37_1[(0x00003100 - 0x0000307c) / 4]; /* gap in address space */
  1204. #else
  1205. uint32_t _notused_37[(0x00003100 - 0x00003000) / 4]; /* gap in address space */
  1206. #endif
  1207. /* WDR2 */
  1208. uint32_t isp_wdr2_ctrl; /*!<(rw), 0x00003100 */
  1209. uint32_t isp_wdr2_blk_siz; /*!<(rw), 0x00003104 */
  1210. uint32_t isp_wdr2_color_weight; /*!<(rw), 0x00003108 */
  1211. uint32_t isp_wdr2_blt_sigma; /*!<(rw), 0x0000310C */
  1212. uint32_t isp_wdr2_blt_kernel_0; /*!<(rw), 0x00003110 */
  1213. uint32_t isp_wdr2_blt_kernel_1; /*!<(rw), 0x00003114 */
  1214. uint32_t isp_wdr2_vol_shift_bit; /*!<(rw), 0x00003118 */
  1215. uint32_t isp_wdr2_bin_dist_0; /*!<(rw), 0x0000311C */
  1216. uint32_t isp_wdr2_bin_dist_1; /*!<(rw), 0x00003120 */
  1217. uint32_t isp_wdr2_bin_dist_2; /*!<(rw), 0x00003124 */
  1218. uint32_t isp_wdr2_bin_dist_3; /*!<(rw), 0x00003128 */
  1219. uint32_t isp_wdr2_hist_norm_fac; /*!<(rw), 0x0000312C */
  1220. uint32_t _notused_38[(0x00003138 - 0x00003130) / 4]; /* gap in address space */
  1221. uint32_t isp_wdr2_pre_gamma_lut; /*!<(rw), 0x00003138 */
  1222. uint32_t isp_wdr2_pre_gamma_write_data; /*!<(rw), 0x0000313C */
  1223. uint32_t isp_wdr2_tone_curve_lut; /*!<(rw), 0x00003140 */
  1224. uint32_t isp_wdr2_tone_curve_write_data; /*!<(rw), 0x00003144 */
  1225. uint32_t isp_wdr2_merge_coeff_lut; /*!<(rw), 0x00003148 */
  1226. uint32_t isp_wdr2_merge_coeff_write_data; /*!<(rw), 0x0000314C */
  1227. uint32_t isp_wdr2_pre_gamma_cx_0; /*!<(rw), 0x00003150 */
  1228. uint32_t isp_wdr2_pre_gamma_cx_1; /*!<(rw), 0x00003154 */
  1229. uint32_t isp_wdr2_pre_gamma_cx_2; /*!<(rw), 0x00003158 */
  1230. uint32_t isp_wdr2_pre_gamma_cx_3; /*!<(rw), 0x0000315C */
  1231. uint32_t isp_wdr2_pre_gamma_cx_4; /*!<(rw), 0x00003160 */
  1232. uint32_t isp_wdr2_pre_gamma_cx_5; /*!<(rw), 0x00003164 */
  1233. uint32_t isp_wdr2_pre_gamma_cx_6; /*!<(rw), 0x00003168 */
  1234. uint32_t isp_wdr2_pre_gamma_cx_7; /*!<(rw), 0x0000316C */
  1235. uint32_t isp_wdr2_pre_gamma_cx_8; /*!<(rw), 0x00003170 */
  1236. uint32_t isp_wdr2_pre_gamma_cx_9; /*!<(rw), 0x00003174 */
  1237. uint32_t isp_wdr2_pre_gamma_cx_10; /*!<(rw), 0x00003178 */
  1238. uint32_t isp_wdr2_tone_curve_cx_0; /*!<(rw), 0x0000317C */
  1239. uint32_t isp_wdr2_tone_curve_cx_1; /*!<(rw), 0x00003180 */
  1240. uint32_t isp_wdr2_tone_curve_cx_2; /*!<(rw), 0x00003184 */
  1241. uint32_t isp_wdr2_tone_curve_cx_3; /*!<(rw), 0x00003188 */
  1242. uint32_t isp_wdr2_merge_coeff_cx_0; /*!<(rw), 0x0000318C */
  1243. uint32_t isp_wdr2_merge_coeff_cx_1; /*!<(rw), 0x00003190 */
  1244. uint32_t _notused_39[(0x000031A8 - 0x00003194) / 4]; /* gap in address space */
  1245. uint32_t isp_wdr2_max_gain_cx; /*!<(rw), 0x000031A8 */
  1246. uint32_t isp_wdr2_max_gain_slope_0; /*!<(rw), 0x000031AC */
  1247. uint32_t isp_wdr2_max_gain_slope_1; /*!<(rw), 0x000031B0 */
  1248. uint32_t isp_wdr2_max_gain_slope_2; /*!<(rw), 0x000031B4 */
  1249. uint32_t isp_wdr2_max_gain_cy_0; /*!<(rw), 0x000031B8 */
  1250. uint32_t isp_wdr2_max_gain_cy_1; /*!<(rw), 0x000031BC */
  1251. uint32_t isp_wdr2_max_gain_cy_2; /*!<(rw), 0x000031C0 */
  1252. uint32_t isp_wdr2_norm_factor_mul_0; /*!<(rw), 0x000031C4 */
  1253. uint32_t isp_wdr2_norm_factor_mul_1; /*!<(rw), 0x000031C8 */
  1254. uint32_t isp_wdr2_norm_factor_shift_bit_0; /*!<(rw), 0x000031CC */
  1255. uint32_t isp_wdr2_norm_factor_shift_bit_1; /*!<(rw), 0x000031D0 */
  1256. uint32_t isp_wdr2_bin_range_0; /*!<(rw), 0x000031D4 */
  1257. uint32_t isp_wdr2_bin_range_1; /*!<(rw), 0x000031D8 */
  1258. uint32_t isp_wdr2_bin_range_2; /*!<(rw), 0x000031DC */
  1259. uint32_t isp_wdr2_bin_range_3; /*!<(rw), 0x000031E0 */
  1260. uint32_t isp_wdr2_hist_data_0; /*!<(ro), 0x000031E4 */
  1261. uint32_t isp_wdr2_hist_data_1; /*!<(ro), 0x000031E8 */
  1262. uint32_t _notused_40[(0x00003200 - 0x000031EC) / 4]; /* gap in address space */
  1263. /* Compand */
  1264. uint32_t isp_compand_ctrl; /*!<(rw), 0x00003200 */
  1265. uint32_t isp_compand_bls_a_fixed; /*!<(rw), 0x00003204 */
  1266. uint32_t isp_compand_bls_b_fixed; /*!<(rw), 0x00003208 */
  1267. uint32_t isp_compand_bls_c_fixed; /*!<(rw), 0x0000320C */
  1268. uint32_t isp_compand_bls_d_fixed; /*!<(rw), 0x00003210 */
  1269. uint32_t isp_compand_expand_px_0; /*!<(rw), 0x00003214 */
  1270. uint32_t isp_compand_expand_px_1; /*!<(rw), 0x00003218 */
  1271. uint32_t isp_compand_expand_px_2; /*!<(rw), 0x0000321C */
  1272. uint32_t isp_compand_expand_px_3; /*!<(rw), 0x00003220 */
  1273. uint32_t isp_compand_expand_px_4; /*!<(rw), 0x00003224 */
  1274. uint32_t isp_compand_expand_px_5; /*!<(rw), 0x00003228 */
  1275. uint32_t isp_compand_expand_px_6; /*!<(rw), 0x0000322C */
  1276. uint32_t isp_compand_expand_px_7; /*!<(rw), 0x00003230 */
  1277. uint32_t isp_compand_expand_px_8; /*!<(rw), 0x00003234 */
  1278. uint32_t isp_compand_expand_px_9; /*!<(rw), 0x00003238 */
  1279. uint32_t isp_compand_expand_px_10; /*!<(rw), 0x0000323C */
  1280. uint32_t isp_compand_compress_px_0; /*!<(rw), 0x00003240 */
  1281. uint32_t isp_compand_compress_px_1; /*!<(rw), 0x00003244 */
  1282. uint32_t isp_compand_compress_px_2; /*!<(rw), 0x00003248 */
  1283. uint32_t isp_compand_compress_px_3; /*!<(rw), 0x0000324C */
  1284. uint32_t isp_compand_compress_px_4; /*!<(rw), 0x00003250 */
  1285. uint32_t isp_compand_compress_px_5; /*!<(rw), 0x00003254 */
  1286. uint32_t isp_compand_compress_px_6; /*!<(rw), 0x00003258 */
  1287. uint32_t isp_compand_compress_px_7; /*!<(rw), 0x0000325C */
  1288. uint32_t isp_compand_compress_px_8; /*!<(rw), 0x00003260 */
  1289. uint32_t isp_compand_compress_px_9; /*!<(rw), 0x00003264 */
  1290. uint32_t isp_compand_compress_px_10; /*!<(rw), 0x00003268 */
  1291. uint32_t isp_compand_expand_y_addr; /*!<(rw), 0x0000326C */
  1292. uint32_t isp_compand_expand_y_write_data; /*!<(rw), 0x00003270 */
  1293. uint32_t isp_compand_compress_y_addr; /*!<(rw), 0x00003274 */
  1294. uint32_t isp_compand_compress_y_write_data; /*!<(rw), 0x00003278 */
  1295. uint32_t isp_compand_expand_x_addr; /*!<(rw), 0x0000327C */
  1296. uint32_t isp_compand_expand_x_write_data; /*!<(rw), 0x00003280 */
  1297. uint32_t isp_compand_compress_x_addr; /*!<(rw), 0x00003284 */
  1298. uint32_t isp_compand_compress_x_write_data; /*!<(rw), 0x00003288 */
  1299. uint32_t _notused_41[(0x00003300 - 0x0000328C) / 4]; /* gap in address space */
  1300. uint32_t isp_stitching_ctrl; /*!<(rw), 0x00003300 */
  1301. uint32_t isp_stitching_frame_width; /*!<(rw), 0x00003304 */
  1302. uint32_t isp_stitching_frame_height; /*!<(rw), 0x00003308 */
  1303. uint32_t isp_stitching_exposure_bit; /*!<(rw), 0x0000330C */
  1304. uint32_t isp_stitching_color_weight; /*!<(rw), 0x00003310 */
  1305. uint32_t isp_stitching_bls_exp_0_a; /*!<(rw), 0x00003314 */
  1306. uint32_t isp_stitching_bls_exp_0_b; /*!<(rw), 0x00003318 */
  1307. uint32_t isp_stitching_bls_exp_0_c; /*!<(rw), 0x0000331C */
  1308. uint32_t isp_stitching_bls_exp_0_d; /*!<(rw), 0x00003320 */
  1309. uint32_t isp_stitching_bls_exp_1_a; /*!<(rw), 0x00003324 */
  1310. uint32_t isp_stitching_bls_exp_1_b; /*!<(rw), 0x00003328 */
  1311. uint32_t isp_stitching_bls_exp_1_c; /*!<(rw), 0x0000332C */
  1312. uint32_t isp_stitching_bls_exp_1_d; /*!<(rw), 0x00003330 */
  1313. uint32_t isp_stitching_bls_exp_2_a; /*!<(rw), 0x00003334 */
  1314. uint32_t isp_stitching_bls_exp_2_b; /*!<(rw), 0x00003338 */
  1315. uint32_t isp_stitching_bls_exp_2_c; /*!<(rw), 0x0000333C */
  1316. uint32_t isp_stitching_bls_exp_2_d; /*!<(rw), 0x00003340 */
  1317. uint32_t isp_stitching_ratio_ls; /*!<(rw), 0x00003344 */
  1318. uint32_t isp_stitching_ratio_vs; /*!<(rw), 0x00003348 */
  1319. uint32_t isp_stitching_ratio_ls_shd; /*!<(ro), 0x0000334C */
  1320. uint32_t isp_stitching_ratio_vs_shd; /*!<(ro), 0x00003350 */
  1321. uint32_t isp_stitching_trans_range_linear; /*!<(rw), 0x00003354 */
  1322. uint32_t isp_stitching_trans_range_nonlinear; /*!<(rw), 0x00003358 */
  1323. uint32_t isp_stitching_sat_level; /*!<(rw), 0x0000335C */
  1324. uint32_t isp_stitching_long_exposure; /*!<(rw), 0x00003360 */
  1325. uint32_t isp_stitching_short_exposure; /*!<(rw), 0x00003364 */
  1326. uint32_t isp_stitching_very_short_exposure; /*!<(rw), 0x00003368 */
  1327. uint32_t isp_stitching_hdr_mode; /*!<(rw), 0x0000336C */
  1328. uint32_t isp_stitching_out_hblank; /*!<(rw), 0x00003370 */
  1329. uint32_t isp_stitching_out_vblank; /*!<(rw), 0x00003374 */
  1330. uint32_t isp_stitching_interrupt_status; /*!<(rw), 0x00003378 */
  1331. uint32_t isp_stitching_compress_x0; /*!<(rw), 0x0000337c */
  1332. uint32_t isp_stitching_compress_x0_shd; /*!<(rw), 0x00003380 */
  1333. uint32_t isp_stitching_exposure_mean_0; /*!<(rw), 0x00003384 */
  1334. uint32_t isp_stitching_exposure_mean_1; /*!<(rw), 0x00003388 */
  1335. uint32_t _notused_42[(0x000033A0 - 0x0000338C) / 4]; /* gap in address space */
  1336. uint32_t isp_stitching_compress_lut_0; /*!<(rw), 0x000033A0 */
  1337. uint32_t isp_stitching_compress_lut_1; /*!<(rw), 0x000033A4 */
  1338. uint32_t isp_stitching_compress_lut_2; /*!<(rw), 0x000033A8 */
  1339. uint32_t isp_stitching_compress_lut_3; /*!<(rw), 0x000033AC */
  1340. uint32_t isp_stitching_compress_lut_4; /*!<(rw), 0x000033B0 */
  1341. /* uint32_t isp_stitching_compress_lut_shd_0; //!<(ro), 0x000033B4 */
  1342. /* uint32_t isp_stitching_compress_lut_shd_1; //!<(ro), 0x000033B8 */
  1343. /* uint32_t isp_stitching_compress_lut_shd_2; //!<(ro), 0x000033BC */
  1344. /* uint32_t isp_stitching_compress_lut_shd_3; //!<(ro), 0x000033C0 */
  1345. /* uint32_t isp_stitching_compress_lut_shd_4; //!<(ro), 0x000033C4 */
  1346. uint32_t _notused_43[(0x000033C8 - 0x000033B4) / 4]; /* gap in address space */
  1347. uint32_t isp_stitching_exp0_awb_gain_g; /*!<(ro), 0x000033C8 */
  1348. uint32_t isp_stitching_exp0_awb_gain_rb; /*!<(ro), 0x000033CC */
  1349. uint32_t isp_stitching_exp1_awb_gain_g; /*!<(ro), 0x000033D0 */
  1350. uint32_t isp_stitching_exp1_awb_gain_rb; /*!<(ro), 0x000033D4 */
  1351. uint32_t isp_stitching_exp2_awb_gain_g; /*!<(ro), 0x000033D8 */
  1352. uint32_t isp_stitching_exp2_awb_gain_rb; /*!<(ro), 0x000033DC */
  1353. uint32_t isp_stitching_long_sat_params; /*!<(ro), 0x000033E0 */
  1354. uint32_t isp_stitching_imsc; /*!<(rw), 0x000033e4 */
  1355. uint32_t isp_stitching_ris; /*!<(ro), 0x000033e8 */
  1356. uint32_t isp_stitching_mis; /*!<(ro), 0x000033ec */
  1357. uint32_t isp_stitching_icr; /*!<(wo), 0x000033f0 */
  1358. uint32_t isp_stitching_isr; /*!<(wo), 0x000033f4 */
  1359. uint32_t isp_stitching_bls_exp_out_0; /*!<(rw), 0x000033f8 */
  1360. uint32_t isp_stitching_bls_exp_out_1; /*!<(rw), 0x000033fc */
  1361. uint32_t _notused_44[(0x00003500 - 0x00003400) / 4]; /* gap in address space */
  1362. /* WDR3 */
  1363. uint32_t isp_wdr3_ctrl; /*!<(rw), 0x00003500 */
  1364. uint32_t isp_wdr3_shift; /*!<(rw), 0x00003504 */
  1365. uint32_t isp_wdr3_block_size; /*!<(rw), 0x00003508 */
  1366. uint32_t isp_wdr3_block_area_factor; /*!<(rw), 0x0000350C */
  1367. uint32_t isp_wdr3_value_weight; /*!<(rw), 0x00003510 */
  1368. uint32_t isp_wdr3_strength; /*!<(rw), 0x00003514 */
  1369. uint32_t isp_wdr3_pixel_slope; /*!<(rw), 0x00003518 */
  1370. uint32_t isp_wdr3_entropy_slope; /*!<(rw), 0x0000351C */
  1371. uint32_t isp_wdr3_sigma_width; /*!<(rw), 0x00003520 */
  1372. uint32_t isp_wdr3_sigma_height; /*!<(rw), 0x00003524 */
  1373. uint32_t isp_wdr3_sigma_value; /*!<(rw), 0x00003528 */
  1374. uint32_t isp_wdr3_block_flag_width; /*!<(rw), 0x0000352C */
  1375. uint32_t isp_wdr3_block_flag_height; /*!<(rw), 0x00003530 */
  1376. uint32_t isp_wdr3_frame_average; /*!<(ro), 0x00003534 */
  1377. uint32_t isp_wdr3_frame_std; /*!<(ro), 0x00003538 */
  1378. uint32_t isp_wdr3_histogram[5]; /*!<(rw), 0x0000353C */
  1379. uint32_t isp_wdr3_entropy[5]; /*!<(rw), 0x00003550 */
  1380. uint32_t isp_wdr3_gamma_pre[5]; /*!<(rw), 0x00003564 */
  1381. uint32_t isp_wdr3_gamma_up[5]; /*!<(rw), 0x00003578 */
  1382. uint32_t isp_wdr3_gamma_down[5]; /*!<(rw), 0x0000358C */
  1383. uint32_t isp_wdr3_distance_weight[5]; /*!<(rw), 0x000035A0 */
  1384. uint32_t isp_wdr3_difference_weight[5]; /*!<(rw), 0x000035B4 */
  1385. uint32_t isp_wdr3_invert_curve[7]; /*!<(rw), 0x000035C8 */
  1386. uint32_t isp_wdr3_invert_linear[7]; /*!<(rw), 0x000035E4 */
  1387. uint32_t isp_wdr3_shift_0; /*!<(rw), 0x00003600 */
  1388. uint32_t isp_wdr3_shift_1; /*!<(rw), 0x00003604 */
  1389. uint32_t isp_wdr3_strength_shd; /*!<(ro), 0x00003608 */
  1390. uint32_t isp_wdr3_pixel_slope_shd; /*!<(ro), 0x0000360C */
  1391. uint32_t isp_wdr3_entropy_slope_shd; /*!<(ro), 0x00003610 */
  1392. uint32_t _notused_44_3dnr[(0x00003700 - 0x00003614) / 4]; /* gap in address space */
  1393. /* 3DNR */
  1394. uint32_t isp_denoise3d_ctrl; /* 0x00003700 */
  1395. uint32_t isp_denoise3d_strength; /* 0x00003704 */
  1396. uint32_t isp_denoise3d_edge_h; /* 0x00003708 */
  1397. uint32_t isp_denoise3d_edge_v; /* 0x0000370C */
  1398. uint32_t isp_denoise3d_range_s; /* 0x00003710 */
  1399. uint32_t isp_denoise3d_range_t; /* 0x00003714 */
  1400. uint32_t isp_denoise3d_motion; /* 0x00003718 */
  1401. uint32_t isp_denoise3d_delta_inv; /* 0x0000371C */
  1402. uint32_t isp_denoise3d_curve_s[6]; /* 0x00003720 */
  1403. uint32_t isp_denoise3d_curve_t[6]; /* 0x00003738 */
  1404. uint32_t isp_denoise3d_average; /* 0x00003750 */
  1405. uint32_t isp_denoise3d_strength_shd; /* 0x00003754 */
  1406. uint32_t isp_denoise3d_edge_h_shd; /* 0x00003758 */
  1407. uint32_t isp_denoise3d_edge_v_shd; /* 0x0000375C */
  1408. uint32_t isp_denoise3d_range_s_shd; /* 0x00003760 */
  1409. uint32_t isp_denoise3d_range_t_shd; /* 0x00003764 */
  1410. uint32_t isp_denoise3d_motion_shd; /* 0x00003768 */
  1411. uint32_t isp_denoise3d_delta_inv_shd; /* 0x0000376C */
  1412. uint32_t isp_denoise3d_dummy_hblank; /* 0x00003770 */
  1413. uint32_t isp_denoise3d_ctrl_shd; /* ro 0x00003774 */
  1414. uint32_t isp_denoise3d_weight1; /* rw 0x00003778 */
  1415. uint32_t isp_denoise3d_weight2; /* rw 0x0000377c */
  1416. uint32_t isp_denoise3d_weight1_shd; /* rw 0x00003780 */
  1417. uint32_t isp_denoise3d_weight2_shd; /* rw 0x00003784 */
  1418. uint32_t _notused_45[(0x00003900 - 0x00003788) / 4]; /* gap in address space */
  1419. uint32_t isp_ee_ctrl; /*!<(rw), 0x00003900 */
  1420. uint32_t isp_ee_y_gain; /*!<(rw), 0x00003904 */
  1421. uint32_t isp_ee_uv_gain; /*!<(ro), 0x00003908 */
  1422. uint32_t isp_ee_ctrl_shd; /*!<(ro), 0x0000390C */
  1423. uint32_t isp_ee_y_gain_shd; /*!<(ro), 0x00003910 */
  1424. uint32_t isp_ee_uv_gain_shd; /*!<(ro), 0x00003914 */
  1425. uint32_t isp_ee_dummy_hblank; /*!<(rw), 0x00003918 */
  1426. uint32_t isp_curve_ctrl; /*!<(rw), 0x0000391c */
  1427. uint32_t isp_curve_lut_x_addr; /*!<(rw), 0x00003920 */
  1428. uint32_t isp_curve_lut_x_write_data; /*!<(rw), 0x00003924 */
  1429. uint32_t isp_curve_lut_luma_addr; /*!<(rw), 0x00003928 */
  1430. uint32_t isp_curve_lut_luma_write_data; /*!<(rw), 0x0000392c */
  1431. uint32_t isp_curve_lut_chroma_addr; /*!<(rw), 0x00003930 */
  1432. uint32_t isp_curve_lut_chroma_write_data; /*!<(rw), 0x00003934 */
  1433. uint32_t isp_curve_lut_shift_addr; /*!<(rw), 0x00003938 */
  1434. uint32_t isp_curve_lut_shift_write_data; /*!<(rw), 0x0000393c */
  1435. uint32_t isp_curve_ctrl_shd; /*!<(ro), 0x00003940 */
  1436. uint32_t isp_curve_lut_luma_addr_shd; /*!<(ro), 0x00003944 */
  1437. uint32_t isp_curve_lut_luma_write_data_shd; /*!<(ro), 0x00003948 */
  1438. uint32_t isp_curve_lut_chroma_addr_shd; /*!<(ro), 0x0000394c */
  1439. uint32_t isp_curve_lut_chroma_write_data_shd; /*!<(ro), 0x00003950 */
  1440. uint32_t isp_curve_lut_shift_addr_shd; /*!<(ro), 0x00003954 */
  1441. uint32_t isp_curve_lut_shift_write_data_shd; /*!<(ro), 0x00003958 */
  1442. uint32_t _notused_46[(0x00003A00 - 0x0000395c) / 4]; /* gap in address space */
  1443. uint32_t isp_denoise2d_control; /*!<(rw), 0x00003A00 */
  1444. uint32_t isp_denoise2d_strength; /*!<(rw), 0x00003A04 */
  1445. uint32_t isp_denoise2d_sigma_y[24]; /*!<(rw), 0x00003A08 */
  1446. uint32_t isp_denoise2d_sigma_y_shd[24]; /*!<(ro), 0x00003A68 */
  1447. #if defined(ISP_2DNR_V2) || defined(ISP_2DNR_V4) || defined(ISP_2DNR_V5)
  1448. uint32_t isp_denoise2d_control_shd; /*!<(ro), 0x00003AC8 */
  1449. uint32_t isp_denoise2d_strength_shd; /*!<(ro), 0x00003ACC */
  1450. uint32_t isp_denoise2d_sigma_sqr; /*!<(rw), 0x00003AD0 */
  1451. uint32_t isp_denoise2d_weight_mul_factor; /*!<(rw), 0x00003AD4 */
  1452. uint32_t isp_denoise2d_sigma_sqr_shd; /*!<(rw), 0x00003AD8 */
  1453. uint32_t isp_denoise2d_weight_mul_factor_shd; /*!<(rw), 0x00003ADC */
  1454. uint32_t isp_denoise2d_dummy_hblank; /*!<(rw), 0x00003AE0 */
  1455. uint32_t isp_denoise2d_motionless_control_curve; /*!<(rw), 0x00003ae4 */
  1456. uint32_t isp_denoise2d_motion_inv; /*!<(rw), 0x00003ae8 */
  1457. uint32_t isp_denoise3d2_blending; /*!<(rw), 0x00003aec */
  1458. uint32_t isp_denoise3d2_blending_shd; /*!<(ro), 0x00003af0 */
  1459. uint32_t _notused_47[(0x00003B00 - 0x00003af4) / 4]; // gap in address space
  1460. #else
  1461. uint32_t _notused_47[(0x00003B00 - 0x00003ac8) / 4]; // gap in address space
  1462. #endif
  1463. uint32_t isp_hdr_hist_prop; /*!< Histogram properties (rw) MRV_HIST_BASE + 0x00000000 */
  1464. uint32_t isp_hdr_hist_h_offs; /*!< Histogram window horizontal offset for first window of 25 sub-windows (rw) MRV_HIST_BASE + 0x00000004 */
  1465. uint32_t isp_hdr_hist_v_offs; /*!< Histogram window vertical offset for first window of 25 sub-windows (rw) MRV_HIST_BASE + 0x00000008 */
  1466. uint32_t isp_hdr_hist_h_size; /*!< Horizontal (sub-)window size (rw) MRV_HIST_BASE + 0x0000000c */
  1467. uint32_t isp_hdr_hist_v_size; /*!< Vertical (sub-)window size (rw) MRV_HIST_BASE + 0x00000010 */
  1468. uint32_t isp_hdr_hist_statistics[48]; /*! 16 x 3 channels l/s/vs */
  1469. uint32_t _notused_48 [(0x00003C00 - 0x00003BD4) / 4]; // gap in address space
  1470. uint32_t isp_hdr_exp_conf; //!<(rw), 0x00003C00
  1471. uint32_t isp_hdr_exp_h_offset; //!<(rw), 0x00003C04
  1472. uint32_t isp_hdr_exp_v_offset; //!<(rw), 0x00003C08
  1473. uint32_t isp_hdr_exp_h_size; //!<(rw), 0x00003C0C
  1474. uint32_t isp_hdr_exp_v_size; //!<(rw), 0x00003C10
  1475. uint32_t isp_hdr_exp_statistics[75]; /*! 25 x 3 channels l/s/vs */
  1476. uint32_t isp_hdr_exp_h_offset_shd; //!<(ro), 0x00003D40
  1477. uint32_t isp_hdr_exp_v_offset_shd; //!<(ro), 0x00003D44
  1478. uint32_t isp_hdr_exp_h_size_shd; //!<(ro), 0x00003D48
  1479. uint32_t isp_hdr_exp_v_size_shd; //!<(ro), 0x00003D4C
  1480. uint32_t _notused_49[(0x00003E00 - 0x00003d50) / 4];
  1481. uint32_t isp_dmsc_ctrl; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000000
  1482. uint32_t isp_dmsc_intp_thr; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000004
  1483. uint32_t isp_dmsc_dmoi_ctrl; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000008
  1484. uint32_t isp_dmsc_dmoi_thr; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x0000000c
  1485. uint32_t isp_dmsc_dmoi_patn_thr; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000010
  1486. uint32_t isp_dmsc_shap_fact; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000014
  1487. uint32_t isp_dmsc_shap_clip; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000018
  1488. uint32_t isp_dmsc_shap_thr; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x0000001c
  1489. uint32_t isp_dmsc_shap_ratio; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000020
  1490. uint32_t isp_dmsc_shap_line_ctrl; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000024
  1491. uint32_t isp_dmsc_shap_line_ratio; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000028
  1492. uint32_t isp_dmsc_shap_filt1; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x0000002c
  1493. uint32_t isp_dmsc_shap_filt2; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000030
  1494. uint32_t isp_dmsc_dpul_ctrl; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000034
  1495. uint32_t isp_dmsc_skin_thr_cb; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000038
  1496. uint32_t isp_dmsc_skin_thr_cr; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x0000003c
  1497. uint32_t isp_dmsc_skin_thr_y; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000040
  1498. uint32_t isp_dmsc_cac_ctrl; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000044
  1499. uint32_t isp_dmsc_cac_count_start; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000048
  1500. uint32_t isp_dmsc_cac_a; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x0000004C
  1501. uint32_t isp_dmsc_cac_b; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000050
  1502. uint32_t isp_dmsc_cac_c; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000054
  1503. uint32_t isp_dmsc_cac_x_norm; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x00000058
  1504. uint32_t isp_dmsc_cac_y_norm; //!< demosaic V20 (rw) ISP_DEMOSAIC_BASE + 0x0000005C
  1505. uint32_t isp_dmsc_size_ctrl; //!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000060
  1506. uint32_t isp_dmsc_ctrl_shd; //!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000064
  1507. uint32_t isp_dmsc_shap_fact_shd; //!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000068
  1508. uint32_t isp_dmsc_shap_clip_shd; //!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x0000006c
  1509. uint32_t isp_dmsc_dpul_ctrl_shd; //!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000070
  1510. uint32_t isp_dmsc_cac_ctrl_shd; //!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000074
  1511. uint32_t isp_dmsc_cac_count_start_shd; //!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000078
  1512. uint32_t isp_dmsc_cac_a_shd; //!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x0000007c
  1513. uint32_t isp_dmsc_cac_b_shd; //!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000080
  1514. uint32_t isp_dmsc_cac_c_shd; //!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000084
  1515. uint32_t isp_dmsc_cac_x_norm_shd; //!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x00000088
  1516. uint32_t isp_dmsc_cac_y_norm_shd; //!< demosaic V20 (r) ISP_DEMOSAIC_BASE + 0x0000008c
  1517. uint32_t _notused_50[(0x00004000 - 0x00003e90) / 4];
  1518. uint32_t isp_pre_filt_ctrl; //!< isp_pre_file_base_addres + 0x0000
  1519. uint32_t isp_pre_filt_bls_a; //!< isp_pre_file_base_addres + 0x0004
  1520. uint32_t isp_pre_filt_bls_b; //!< isp_pre_file_base_addres + 0x0008
  1521. uint32_t isp_pre_filt_bls_c; //!< isp_pre_file_base_addres + 0x000c
  1522. uint32_t isp_pre_filt_bls_d; //!< isp_pre_file_base_addres + 0x0010
  1523. uint32_t isp_pre_filt_gain_r; //!< isp_pre_file_base_addres + 0x0014
  1524. uint32_t isp_pre_filt_gain_g; //!< isp_pre_file_base_addres + 0x0018
  1525. uint32_t isp_pre_filt_gain_b; //!< isp_pre_file_base_addres + 0x001c
  1526. uint32_t isp_pre_filt_dpc_th_r; //!< isp_pre_file_base_addres + 0x0020
  1527. uint32_t isp_pre_filt_dpc_th_g; //!< isp_pre_file_base_addres + 0x0024
  1528. uint32_t isp_pre_filt_dpc_th_b; //!< isp_pre_file_base_addres + 0x0028
  1529. uint32_t isp_pre_filt_dpc_th_ir; //!< isp_pre_file_base_addres + 0x002c
  1530. uint32_t isp_pre_filt_cc_00_01; //!< isp_pre_file_base_addres + 0x0030
  1531. uint32_t isp_pre_filt_cc_02_03; //!< isp_pre_file_base_addres + 0x0034
  1532. uint32_t isp_pre_filt_cc_10_11; //!< isp_pre_file_base_addres + 0x0038
  1533. uint32_t isp_pre_filt_cc_12_13; //!< isp_pre_file_base_addres + 0x003c
  1534. uint32_t isp_pre_filt_cc_20_21; //!< isp_pre_file_base_addres + 0x0040
  1535. uint32_t isp_pre_filt_cc_22_23; //!< isp_pre_file_base_addres + 0x0044
  1536. uint32_t isp_pre_filt_cc_00_01_shd; //!< isp_pre_file_base_addres + 0x0048
  1537. uint32_t isp_pre_filt_cc_02_03_shd; //!< isp_pre_file_base_addres + 0x004c
  1538. uint32_t isp_pre_filt_cc_10_11_shd; //!< isp_pre_file_base_addres + 0x0050
  1539. uint32_t isp_pre_filt_cc_12_13_shd; //!< isp_pre_file_base_addres + 0x0054
  1540. uint32_t isp_pre_filt_cc_20_21_shd; //!< isp_pre_file_base_addres + 0x0058
  1541. uint32_t isp_pre_filt_cc_22_23_shd; //!< isp_pre_file_base_addres + 0x05c
  1542. uint32_t isp_pre_filt_ir_des_px1; //!< isp_pre_file_base_addres + 0x0060
  1543. uint32_t _notused_51[(0x00004080 - 0x00004064) / 4];
  1544. uint32_t isp_pre_filt_ir_des_py1; //!< isp_pre_file_base_addres + 0x0080
  1545. uint32_t isp_pre_filt_ir_des_py2; //!< isp_pre_file_base_addres + 0x0084
  1546. uint32_t isp_pre_filt_ir_des_py3; //!< isp_pre_file_base_addres + 0x0088
  1547. uint32_t isp_pre_filt_ir_des_py4; //!< isp_pre_file_base_addres + 0x008c
  1548. uint32_t isp_pre_filt_ir_des_py5; //!< isp_pre_file_base_addres + 0x0090
  1549. uint32_t isp_pre_filt_ir_des_py6; //!< isp_pre_file_base_addres + 0x0094
  1550. uint32_t isp_pre_filt_ir_des_py7; //!< isp_pre_file_base_addres + 0x0098
  1551. uint32_t isp_pre_filt_ir_des_py8; //!< isp_pre_file_base_addres + 0x009c
  1552. uint32_t isp_pre_filt_ir_des_pd1; //!< isp_pre_file_base_addres + 0x00a0
  1553. uint32_t isp_pre_filt_ir_des_pd2; //!< isp_pre_file_base_addres + 0x00a4
  1554. uint32_t isp_pre_filt_ir_des_pd3; //!< isp_pre_file_base_addres + 0x00a8
  1555. uint32_t isp_pre_filt_ir_des_pd4; //!< isp_pre_file_base_addres + 0x00ac
  1556. uint32_t isp_pre_filt_l_des_px1; //!< isp_pre_file_base_addres + 0x00b0
  1557. uint32_t _notused_52[(0x000040d0 - 0x000040b4) / 4];
  1558. uint32_t isp_pre_filt_l_des_py1; //!< isp_pre_file_base_addres + 0x00d0
  1559. uint32_t isp_pre_filt_l_des_py2; //!< isp_pre_file_base_addres + 0x00d4
  1560. uint32_t isp_pre_filt_l_des_py3; //!< isp_pre_file_base_addres + 0x00d8
  1561. uint32_t isp_pre_filt_l_des_py4; //!< isp_pre_file_base_addres + 0x00dc
  1562. uint32_t isp_pre_filt_l_des_py5; //!< isp_pre_file_base_addres + 0x00e0
  1563. uint32_t isp_pre_filt_l_des_py6; //!< isp_pre_file_base_addres + 0x00e4
  1564. uint32_t isp_pre_filt_l_des_py7; //!< isp_pre_file_base_addres + 0x00e8
  1565. uint32_t isp_pre_filt_l_des_py8; //!< isp_pre_file_base_addres + 0x00ec
  1566. uint32_t isp_pre_filt_l_des_pd1; //!< isp_pre_file_base_addres + 0x00f0
  1567. uint32_t isp_pre_filt_l_des_pd2; //!< isp_pre_file_base_addres + 0x00f4
  1568. uint32_t isp_pre_filt_l_des_pd3; //!< isp_pre_file_base_addres + 0x00f8
  1569. uint32_t isp_pre_filt_l_des_pd4; //!< isp_pre_file_base_addres + 0x00fc
  1570. uint32_t isp_pre_filt_thresh_bl0; //!< isp_pre_file_base_addres + 0x0100
  1571. uint32_t isp_pre_filt_thresh_bl1; //!< isp_pre_file_base_addres + 0x0104
  1572. uint32_t isp_pre_filt_thresh_sh0; //!< isp_pre_file_base_addres + 0x0108
  1573. uint32_t isp_pre_filt_thresh_sh1; //!< isp_pre_file_base_addres + 0x010c
  1574. uint32_t isp_pre_filt_lum_weight; //!< isp_pre_file_base_addres + 0x0110
  1575. uint32_t isp_pre_filt_fac_sh1; //!< isp_pre_file_base_addres + 0x0114
  1576. uint32_t isp_pre_filt_fac_sh0; //!< isp_pre_file_base_addres + 0x0118
  1577. uint32_t isp_pre_filt_fac_mid; //!< isp_pre_file_base_addres + 0x011c
  1578. uint32_t isp_pre_filt_fac_bl0; //!< isp_pre_file_base_addres + 0x0120
  1579. uint32_t isp_pre_filt_fac_bl1; //!< isp_pre_file_base_addres + 0x0124
  1580. uint32_t isp_pre_filt_ir_denoise_sw_03; //!< isp_pre_file_base_addres + 0x0128
  1581. uint32_t isp_pre_filt_ir_denoise_sw_45; //!< isp_pre_file_base_addres + 0x012c
  1582. uint32_t isp_pre_filt_h_size; //!< isp_pre_file_base_addres + 0x0130
  1583. uint32_t isp_pre_filt_v_size; //!< isp_pre_file_base_addres + 0x0134
  1584. uint32_t isp_pre_filt_dmy_hblank; //!< isp_pre_file_base_addres + 0x0138
  1585. uint32_t isp_pre_filt_ctrl_shd; //!< isp_pre_file_base_addres + 0x013c
  1586. uint32_t _notused_53[(0x00005100 - 0x00004140) / 4];
  1587. uint32_t isp_wdr4_ctrl ; //!<isp_wdr4_base_addr + 0x000,
  1588. uint32_t isp_wdr4_shift ; //!<isp_wdr4_base_addr + 0x004,
  1589. uint32_t isp_wdr4_block_size ; //!<isp_wdr4_base_addr + 0x008,
  1590. uint32_t isp_wdr4_block_area_factor ; //!<isp_wdr4_base_addr + 0x00c,
  1591. uint32_t isp_wdr4_value_weight ; //!<isp_wdr4_base_addr + 0x010,
  1592. uint32_t isp_wdr4_strength_0 ; //!<isp_wdr4_base_addr + 0x014,
  1593. uint32_t isp_wdr4_strength_1 ; //!<isp_wdr4_base_addr + 0x018,
  1594. uint32_t isp_wdr4_contrast ; //!<isp_wdr4_base_addr + 0x01c,
  1595. uint32_t isp_wdr4_pixel_slope ; //!<isp_wdr4_base_addr + 0x020,
  1596. uint32_t isp_wdr4_entropy_slope ; //!<isp_wdr4_base_addr + 0x024,
  1597. uint32_t isp_wdr4_sigma_width ; //!<isp_wdr4_base_addr + 0x028,
  1598. uint32_t isp_wdr4_sigma_height ; //!<isp_wdr4_base_addr + 0x02c,
  1599. uint32_t isp_wdr4_sigma_value ; //!<isp_wdr4_base_addr + 0x030,
  1600. uint32_t isp_wdr4_block_flag_width ; //!<isp_wdr4_base_addr + 0x034,
  1601. uint32_t isp_wdr4_block_flag_height ; //!<isp_wdr4_base_addr + 0x038,
  1602. uint32_t isp_wdr4_frame_average ; //!<isp_wdr4_base_addr + 0x03c,
  1603. uint32_t isp_wdr4_frame_std ; //!<isp_wdr4_base_addr + 0x040,
  1604. uint32_t isp_wdr4_histogram_0 ; //!<isp_wdr4_base_addr + 0x044,
  1605. uint32_t isp_wdr4_histogram_1 ; //!<isp_wdr4_base_addr + 0x048,
  1606. uint32_t isp_wdr4_histogram_2 ; //!<isp_wdr4_base_addr + 0x04c,
  1607. uint32_t isp_wdr4_histogram_3 ; //!<isp_wdr4_base_addr + 0x050,
  1608. uint32_t isp_wdr4_histogram_4 ; //!<isp_wdr4_base_addr + 0x054,
  1609. uint32_t isp_wdr4_histogram_5 ; //!<isp_wdr4_base_addr + 0x058,
  1610. uint32_t isp_wdr4_histogram_6 ; //!<isp_wdr4_base_addr + 0x05c,
  1611. uint32_t isp_wdr4_histogram_7 ; //!<isp_wdr4_base_addr + 0x060,
  1612. uint32_t isp_wdr4_histogram_8 ; //!<isp_wdr4_base_addr + 0x064,
  1613. uint32_t isp_wdr4_histogram_9 ; //!<isp_wdr4_base_addr + 0x068,
  1614. uint32_t isp_wdr4_histogram_10 ; //!<isp_wdr4_base_addr + 0x06c,
  1615. uint32_t isp_wdr4_histogram_11 ; //!<isp_wdr4_base_addr + 0x070,
  1616. uint32_t isp_wdr4_histogram_12 ; //!<isp_wdr4_base_addr + 0x074,
  1617. uint32_t isp_wdr4_histogram_13 ; //!<isp_wdr4_base_addr + 0x078,
  1618. uint32_t isp_wdr4_entropy_0 ; //!<isp_wdr4_base_addr + 0x07c,
  1619. uint32_t isp_wdr4_entropy_1 ; //!<isp_wdr4_base_addr + 0x080,
  1620. uint32_t isp_wdr4_entropy_2 ; //!<isp_wdr4_base_addr + 0x084,
  1621. uint32_t isp_wdr4_entropy_3 ; //!<isp_wdr4_base_addr + 0x088,
  1622. uint32_t isp_wdr4_entropy_4 ; //!<isp_wdr4_base_addr + 0x08c,
  1623. uint32_t isp_wdr4_entropy_5 ; //!<isp_wdr4_base_addr + 0x090,
  1624. uint32_t isp_wdr4_entropy_6 ; //!<isp_wdr4_base_addr + 0x094,
  1625. uint32_t isp_wdr4_gamma_pre_0 ; //!<isp_wdr4_base_addr + 0x098,
  1626. uint32_t isp_wdr4_gamma_pre_1 ; //!<isp_wdr4_base_addr + 0x09c,
  1627. uint32_t isp_wdr4_gamma_pre_2 ; //!<isp_wdr4_base_addr + 0x0a0,
  1628. uint32_t isp_wdr4_gamma_pre_3 ; //!<isp_wdr4_base_addr + 0x0a4,
  1629. uint32_t isp_wdr4_gamma_pre_4 ; //!<isp_wdr4_base_addr + 0x0a8,
  1630. uint32_t isp_wdr4_gamma_pre_5 ; //!<isp_wdr4_base_addr + 0x0ac,
  1631. uint32_t isp_wdr4_gamma_pre_6 ; //!<isp_wdr4_base_addr + 0x0b0,
  1632. uint32_t isp_wdr4_gamma_pre_7 ; //!<isp_wdr4_base_addr + 0x0b4,
  1633. uint32_t isp_wdr4_gamma_pre_8 ; //!<isp_wdr4_base_addr + 0x0b8,
  1634. uint32_t isp_wdr4_gamma_pre_9 ; //!<isp_wdr4_base_addr + 0x0bc,
  1635. uint32_t isp_wdr4_gamma_pre_10 ; //!<isp_wdr4_base_addr + 0x0c0,
  1636. uint32_t isp_wdr4_gamma_pre_11 ; //!<isp_wdr4_base_addr + 0x0c4,
  1637. uint32_t isp_wdr4_gamma_pre_12 ; //!<isp_wdr4_base_addr + 0x0c8,
  1638. uint32_t isp_wdr4_gamma_pre_13 ; //!<isp_wdr4_base_addr + 0x0cc,
  1639. uint32_t isp_wdr4_gamma_up_0 ; //!<isp_wdr4_base_addr + 0x0d0,
  1640. uint32_t isp_wdr4_gamma_up_1 ; //!<isp_wdr4_base_addr + 0x0d4,
  1641. uint32_t isp_wdr4_gamma_up_2 ; //!<isp_wdr4_base_addr + 0x0d8,
  1642. uint32_t isp_wdr4_gamma_up_3 ; //!<isp_wdr4_base_addr + 0x0dc,
  1643. uint32_t isp_wdr4_gamma_up_4 ; //!<isp_wdr4_base_addr + 0x0e0,
  1644. uint32_t isp_wdr4_gamma_up_5 ; //!<isp_wdr4_base_addr + 0x0e4,
  1645. uint32_t isp_wdr4_gamma_up_6 ; //!<isp_wdr4_base_addr + 0x0e8,
  1646. uint32_t isp_wdr4_gamma_up_7 ; //!<isp_wdr4_base_addr + 0x0ec,
  1647. uint32_t isp_wdr4_gamma_up_8 ; //!<isp_wdr4_base_addr + 0x0f0,
  1648. uint32_t isp_wdr4_gamma_up_9 ; //!<isp_wdr4_base_addr + 0x0f4,
  1649. uint32_t isp_wdr4_gamma_up_10 ; //!<isp_wdr4_base_addr + 0x0f8,
  1650. uint32_t isp_wdr4_gamma_up_11 ; //!<isp_wdr4_base_addr + 0x0fc,
  1651. uint32_t isp_wdr4_gamma_up_12 ; //!<isp_wdr4_base_addr + 0x100,
  1652. uint32_t isp_wdr4_gamma_up_13 ; //!<isp_wdr4_base_addr + 0x104,
  1653. uint32_t isp_wdr4_gamma_down_0 ; //!<isp_wdr4_base_addr + 0x108,
  1654. uint32_t isp_wdr4_gamma_down_1 ; //!<isp_wdr4_base_addr + 0x10c,
  1655. uint32_t isp_wdr4_gamma_down_2 ; //!<isp_wdr4_base_addr + 0x110,
  1656. uint32_t isp_wdr4_gamma_down_3 ; //!<isp_wdr4_base_addr + 0x114,
  1657. uint32_t isp_wdr4_gamma_down_4 ; //!<isp_wdr4_base_addr + 0x118,
  1658. uint32_t isp_wdr4_gamma_down_5 ; //!<isp_wdr4_base_addr + 0x11c,
  1659. uint32_t isp_wdr4_gamma_down_6 ; //!<isp_wdr4_base_addr + 0x120,
  1660. uint32_t isp_wdr4_distance_weight_0 ; //!<isp_wdr4_base_addr + 0x124,
  1661. uint32_t isp_wdr4_distance_weight_1 ; //!<isp_wdr4_base_addr + 0x128,
  1662. uint32_t isp_wdr4_distance_weight_2 ; //!<isp_wdr4_base_addr + 0x12c,
  1663. uint32_t isp_wdr4_distance_weight_3 ; //!<isp_wdr4_base_addr + 0x130,
  1664. uint32_t isp_wdr4_distance_weight_4 ; //!<isp_wdr4_base_addr + 0x134,
  1665. uint32_t isp_wdr4_difference_weight_0 ; //!<isp_wdr4_base_addr + 0x138,
  1666. uint32_t isp_wdr4_difference_weight_1 ; //!<isp_wdr4_base_addr + 0x13c,
  1667. uint32_t isp_wdr4_difference_weight_2 ; //!<isp_wdr4_base_addr + 0x140,
  1668. uint32_t isp_wdr4_difference_weight_3 ; //!<isp_wdr4_base_addr + 0x144,
  1669. uint32_t isp_wdr4_difference_weight_4 ; //!<isp_wdr4_base_addr + 0x148,
  1670. uint32_t isp_wdr4_invert_curve_0 ; //!<isp_wdr4_base_addr + 0x14c,
  1671. uint32_t isp_wdr4_invert_curve_1 ; //!<isp_wdr4_base_addr + 0x150,
  1672. uint32_t isp_wdr4_invert_curve_2 ; //!<isp_wdr4_base_addr + 0x154,
  1673. uint32_t isp_wdr4_invert_curve_3 ; //!<isp_wdr4_base_addr + 0x158,
  1674. uint32_t isp_wdr4_invert_curve_4 ; //!<isp_wdr4_base_addr + 0x15c,
  1675. uint32_t isp_wdr4_invert_curve_5 ; //!<isp_wdr4_base_addr + 0x160,
  1676. uint32_t isp_wdr4_invert_curve_6 ; //!<isp_wdr4_base_addr + 0x164,
  1677. uint32_t isp_wdr4_invert_curve_7 ; //!<isp_wdr4_base_addr + 0x168,
  1678. uint32_t isp_wdr4_invert_curve_8 ; //!<isp_wdr4_base_addr + 0x16c,
  1679. uint32_t isp_wdr4_invert_curve_9 ; //!<isp_wdr4_base_addr + 0x170,
  1680. uint32_t isp_wdr4_invert_linear_0 ; //!<isp_wdr4_base_addr + 0x174,
  1681. uint32_t isp_wdr4_invert_linear_1 ; //!<isp_wdr4_base_addr + 0x178,
  1682. uint32_t isp_wdr4_invert_linear_2 ; //!<isp_wdr4_base_addr + 0x17c,
  1683. uint32_t isp_wdr4_invert_linear_3 ; //!<isp_wdr4_base_addr + 0x180,
  1684. uint32_t isp_wdr4_invert_linear_4 ; //!<isp_wdr4_base_addr + 0x184,
  1685. uint32_t isp_wdr4_invert_linear_5 ; //!<isp_wdr4_base_addr + 0x188,
  1686. uint32_t isp_wdr4_invert_linear_6 ; //!<isp_wdr4_base_addr + 0x18c,
  1687. uint32_t isp_wdr4_invert_linear_7 ; //!<isp_wdr4_base_addr + 0x190,
  1688. uint32_t isp_wdr4_invert_linear_8 ; //!<isp_wdr4_base_addr + 0x194,
  1689. uint32_t isp_wdr4_invert_linear_9 ; //!<isp_wdr4_base_addr + 0x198,
  1690. uint32_t isp_wdr4_invert_linear_10 ; //!<isp_wdr4_base_addr + 0x19c,
  1691. uint32_t isp_wdr4_invert_linear_11 ; //!<isp_wdr4_base_addr + 0x1a0,
  1692. uint32_t isp_wdr4_invert_linear_12 ; //!<isp_wdr4_base_addr + 0x1a4,
  1693. uint32_t isp_wdr4_invert_linear_13 ; //!<isp_wdr4_base_addr + 0x1a8,
  1694. uint32_t isp_wdr4_smooth_invert_0 ; //!<isp_wdr4_base_addr + 0x1ac,
  1695. uint32_t isp_wdr4_smooth_invert_1 ; //!<isp_wdr4_base_addr + 0x1b0,
  1696. uint32_t isp_wdr4_smooth_invert_2 ; //!<isp_wdr4_base_addr + 0x1b4,
  1697. uint32_t isp_wdr4_smooth_invert_3 ; //!<isp_wdr4_base_addr + 0x1b8,
  1698. uint32_t isp_wdr4_smooth_invert_4 ; //!<isp_wdr4_base_addr + 0x1bc,
  1699. uint32_t isp_wdr4_shift_0 ; //!<isp_wdr4_base_addr + 0x1c0,
  1700. uint32_t isp_wdr4_shift_1 ; //!<isp_wdr4_base_addr + 0x1c4,
  1701. uint32_t isp_wdr4_shift_2 ; //!<isp_wdr4_base_addr + 0x1c8,
  1702. uint32_t isp_wdr4_shift_3 ; //!<isp_wdr4_base_addr + 0x1cc,
  1703. uint32_t isp_wdr4_shift0_0 ; //!<isp_wdr4_base_addr + 0x1d0,
  1704. uint32_t isp_wdr4_shift0_1 ; //!<isp_wdr4_base_addr + 0x1d4,
  1705. uint32_t isp_wdr4_shift0_2 ; //!<isp_wdr4_base_addr + 0x1d8,
  1706. uint32_t isp_wdr4_strength_0_shd ; //!<isp_wdr4_base_addr + 0x1dc,
  1707. uint32_t isp_wdr4_strength_1_shd ; //!<isp_wdr4_base_addr + 0x1e0,
  1708. uint32_t isp_wdr4_contrast_shd ; //!<isp_wdr4_base_addr + 0x1e4,
  1709. uint32_t isp_wdr4_pixel_slope_shd ; //!<isp_wdr4_base_addr + 0x1e8,
  1710. uint32_t isp_wdr4_entropy_slope_shd ; //!<isp_wdr4_base_addr + 0x1ec,
  1711. uint32_t _notused_54[(0x00005300 - 0x000052f0) / 4];
  1712. uint32_t isp_denoise3d2_ctrl; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0000,//0x00005300
  1713. uint32_t isp_denoise3d2_strength; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0004,//0x00005304
  1714. uint32_t isp_denoise3d2_noise; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0008,//0x00005308
  1715. uint32_t isp_denoise3d2_motion; //!< denoise3d V2 isp_denoise3d2_base_addr+0x000c,//0x0000530c
  1716. uint32_t isp_denoise3d2_range; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0010,//0x00005310
  1717. uint32_t isp_denoise3d2_motion_inv; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0014,//0x00005314
  1718. uint32_t isp_denoise3d2_update; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0018,//0x00005318
  1719. uint32_t isp_denoise3d2_tnr; //!< denoise3d V2 isp_denoise3d2_base_addr+0x001c,//0x0000531c
  1720. uint32_t isp_denoise3d2_shift; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0020,//0x00005320
  1721. uint32_t isp_denoise3d2_luma; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0024,//0x00005324
  1722. uint32_t isp_denoise3d2_ctrl_shd; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0028,//0x00005328
  1723. uint32_t isp_denoise3d2_strength_shd; //!< denoise3d V2 isp_denoise3d2_base_addr+0x002c,//0x0000532c
  1724. uint32_t isp_denoise3d2_noise_shd; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0030,//0x00005330
  1725. uint32_t isp_denoise3d2_motion_shd; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0034,//0x00005334
  1726. uint32_t isp_denoise3d2_range_shd; //!< denoise3d V2 isp_denoise3d2_base_addr+0x00038,//0x00005338
  1727. uint32_t isp_denoise3d2_motion_inv_shd; //!< denoise3d V2 isp_denoise3d2_base_addr+0x003c,//0x0000533c
  1728. uint32_t isp_denoise3d2_update_shd; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0040,//0x00005340
  1729. uint32_t isp_denoise3d2_tnr_shd; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0044,//0x00005344
  1730. uint32_t isp_denoise3d2_shift_shd; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0048,//0x00005348
  1731. uint32_t isp_denoise3d2_luma_shd; //!< denoise3d V2 isp_denoise3d2_base_addr+0x004c,//0x0000534c
  1732. uint32_t isp_denoise3d2_bg_val_sum; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0050,//0x00005350
  1733. uint32_t isp_denoise3d2_mo_val_sum; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0054,//0x00005354
  1734. uint32_t isp_denoise3d2_bg_cnt; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0058,//0x00005358
  1735. uint32_t isp_denoise3d2_mo_cnt; //!< denoise3d V2 isp_denoise3d2_base_addr+0x005c,//0x0000535c
  1736. uint32_t isp_denoise3d2_frame_avg; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0060,//0x00005360
  1737. uint32_t isp_denoise3d2_dummy_hblank; //!< denoise3d V2 isp_denoise3d2_base_addr+0x0060,//0x00005364
  1738. uint32_t _notused_54_1[(0x00005400 - 0x00005368) / 4];
  1739. uint32_t isp_denoise3d2_pregamma_y_0; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0000,//0x00005400
  1740. uint32_t isp_denoise3d2_pregamma_y_1; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0004,//0x00005404
  1741. uint32_t isp_denoise3d2_pregamma_y_2; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0008,//0x00005408
  1742. uint32_t isp_denoise3d2_pregamma_y_3; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x000c,//0x0000540c
  1743. uint32_t isp_denoise3d2_pregamma_y_4; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0010,//0x00005410
  1744. uint32_t isp_denoise3d2_pregamma_y_5; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0014,//0x00005414
  1745. uint32_t isp_denoise3d2_pregamma_y_6; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0018,//0x00005418
  1746. uint32_t isp_denoise3d2_pregamma_y_7; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x001c,//0x0000541c
  1747. uint32_t isp_denoise3d2_pregamma_y_8; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0020,//0x00005420
  1748. uint32_t isp_denoise3d2_pregamma_y_9; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0024,//0x00005424
  1749. uint32_t isp_denoise3d2_pregamma_y_10; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0028,//0x00005428
  1750. uint32_t isp_denoise3d2_pregamma_y_11; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x002c,//0x0000542c
  1751. uint32_t isp_denoise3d2_pregamma_y_12; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0030,//0x00005430
  1752. uint32_t isp_denoise3d2_pregamma_y_13; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0034,//0x00005434
  1753. uint32_t isp_denoise3d2_pregamma_y_0_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0038,//0x00005438
  1754. uint32_t isp_denoise3d2_pregamma_y_1_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x003c,//0x0000543c
  1755. uint32_t isp_denoise3d2_pregamma_y_2_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0040,//0x00005440
  1756. uint32_t isp_denoise3d2_pregamma_y_3_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0044,//0x00005444
  1757. uint32_t isp_denoise3d2_pregamma_y_4_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0048,//0x00005448
  1758. uint32_t isp_denoise3d2_pregamma_y_5_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x004c,//0x0000544c
  1759. uint32_t isp_denoise3d2_pregamma_y_6_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0050,//0x00005450
  1760. uint32_t isp_denoise3d2_pregamma_y_7_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0054,//0x00005454
  1761. uint32_t isp_denoise3d2_pregamma_y_8_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0058,//0x00005458
  1762. uint32_t isp_denoise3d2_pregamma_y_9_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x005c,//0x0000545c
  1763. uint32_t isp_denoise3d2_pregamma_y_10_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0060,//0x00005460
  1764. uint32_t isp_denoise3d2_pregamma_y_11_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0064,//0x00005464
  1765. uint32_t isp_denoise3d2_pregamma_y_12_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0068,//0x00005468
  1766. uint32_t isp_denoise3d2_pregamma_y_13_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x006c,//0x0000546c
  1767. uint32_t isp_denoise3d2_invgamma_y_0; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0070,//0x00005470
  1768. uint32_t isp_denoise3d2_invgamma_y_1; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0074,//0x00005474
  1769. uint32_t isp_denoise3d2_invgamma_y_2; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0078,//0x00005478
  1770. uint32_t isp_denoise3d2_invgamma_y_3; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x007c,//0x0000547c
  1771. uint32_t isp_denoise3d2_invgamma_y_4; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0080,//0x00005480
  1772. uint32_t isp_denoise3d2_invgamma_y_5; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0084,//0x00005484
  1773. uint32_t isp_denoise3d2_invgamma_y_6; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0088,//0x00005488
  1774. uint32_t isp_denoise3d2_invgamma_y_7; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x008c,//0x0000548c
  1775. uint32_t isp_denoise3d2_invgamma_y_8; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0090,//0x00005490
  1776. uint32_t isp_denoise3d2_invgamma_y_9; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0094,//0x00005494
  1777. uint32_t isp_denoise3d2_invgamma_y_10; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x0098,//0x00005498
  1778. uint32_t isp_denoise3d2_invgamma_y_11; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x009c,//0x0000549c
  1779. uint32_t isp_denoise3d2_invgamma_y_12; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x00a0,//0x000054a0
  1780. uint32_t isp_denoise3d2_invgamma_y_13; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x00a4,//0x000054a4
  1781. uint32_t isp_denoise3d2_invgamma_y_0_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x00a8,//0x000054a8
  1782. uint32_t isp_denoise3d2_invgamma_y_1_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x00ac,//0x000054ac
  1783. uint32_t isp_denoise3d2_invgamma_y_2_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x00b0,//0x000054b0
  1784. uint32_t isp_denoise3d2_invgamma_y_3_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x00b4,//0x000054b4
  1785. uint32_t isp_denoise3d2_invgamma_y_4_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x00b8,//0x000054b8
  1786. uint32_t isp_denoise3d2_invgamma_y_5_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x00bc,//0x000054bc
  1787. uint32_t isp_denoise3d2_invgamma_y_6_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x00c0,//0x000054c0
  1788. uint32_t isp_denoise3d2_invgamma_y_7_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x00c4,//0x000054c4
  1789. uint32_t isp_denoise3d2_invgamma_y_8_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x00c8,//0x000054c8
  1790. uint32_t isp_denoise3d2_invgamma_y_9_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x00cc,//0x000054cc
  1791. uint32_t isp_denoise3d2_invgamma_y_10_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x00d0,//0x000054d0
  1792. uint32_t isp_denoise3d2_invgamma_y_11_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x00d4,//0x000054d4
  1793. uint32_t isp_denoise3d2_invgamma_y_12_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x00d8,//0x000054d8
  1794. uint32_t isp_denoise3d2_invgamma_y_13_shd; //!< denoise3d V2 isp_denoise3d2_curve_base_addr+0x00dc,//0x000054dc
  1795. uint32_t _notused_55[(0x00005500 - 0x000054e0) / 4];
  1796. uint32_t isp_mi_pp_ctrl; //!<0x00 isp_mi_pp_base
  1797. uint32_t isp_mi_pp_fmt; //!<0x04 isp_mi_pp_base
  1798. uint32_t isp_mi_pp_data_swap; //!<0x08 isp_mi_pp_base
  1799. uint32_t _notused_55_1[(0x00005520 - 0x0000550c) / 4];
  1800. uint32_t isp_mi_pp_y_base_ad_init; //!<0x20 isp_mi_pp_base
  1801. uint32_t isp_mi_pp_y_size_init; //!<0x24 isp_mi_pp_base
  1802. uint32_t isp_mi_pp_y_offs_cnt_init; //!<0x28 isp_mi_pp_base
  1803. uint32_t isp_mi_pp_y_llength; //!<0x2c isp_mi_pp_base
  1804. uint32_t isp_mi_pp_y_pic_width; //!<0x30 isp_mi_pp_base
  1805. uint32_t isp_mi_pp_y_pic_height; //!<0x34 isp_mi_pp_base
  1806. uint32_t isp_mi_pp_y_pic_size; //!<0x38 isp_mi_pp_base
  1807. uint32_t isp_mi_pp_cb_base_ad_init; //!<0x3c isp_mi_pp_base
  1808. uint32_t isp_mi_pp_cb_size_init; //!<0x40 isp_mi_pp_base
  1809. uint32_t isp_mi_pp_cb_offs_cnt_init; //!<0x44 isp_mi_pp_base
  1810. uint32_t isp_mi_pp_cr_base_ad_init; //!<0x48 isp_mi_pp_base
  1811. uint32_t isp_mi_pp_cr_size_init; //!<0x4c isp_mi_pp_base
  1812. uint32_t isp_mi_pp_cr_offs_cnt_init; //!<0x50 isp_mi_pp_base
  1813. uint32_t isp_mi_pp_y_base_ad_init2; //!<0x54 isp_mi_pp_base
  1814. uint32_t isp_mi_pp_cb_base_ad_init2; //!<0x58 isp_mi_pp_base
  1815. uint32_t isp_mi_pp_cr_base_ad_init2; //!<0x5c isp_mi_pp_base
  1816. uint32_t isp_mi_pp_y_offs_cnt_start; //!<0x60 isp_mi_pp_base
  1817. uint32_t isp_mi_pp_cb_offs_cnt_start; //!<0x64 isp_mi_pp_base
  1818. uint32_t isp_mi_pp_cr_offs_cnt_start; //!<0x68 isp_mi_pp_base
  1819. uint32_t isp_mi_pp_y_base_ad_shd; //!<0x6c isp_mi_pp_base
  1820. uint32_t isp_mi_pp_y_size_shd; //!<0x70 isp_mi_pp_base
  1821. uint32_t isp_mi_pp_y_offs_cnt_shd; //!<0x74 isp_mi_pp_base
  1822. uint32_t isp_mi_pp_cb_base_ad_shd; //!<0x78 isp_mi_pp_base
  1823. uint32_t isp_mi_pp_cb_size_shd; //!<0x7c isp_mi_pp_base
  1824. uint32_t isp_mi_pp_cb_offs_cnt_shd; //!<0x80 isp_mi_pp_base
  1825. uint32_t isp_mi_pp_cr_base_ad_shd; //!<0x84 isp_mi_pp_base
  1826. uint32_t isp_mi_pp_cr_size_shd; //!<0x88 isp_mi_pp_base
  1827. uint32_t isp_mi_pp_cr_offs_cnt_shd; //!<0x8c isp_mi_pp_base
  1828. uint32_t _notused_55_2[(0x00005598 - 0x00005590) / 4];
  1829. uint32_t isp_mi_pp_dma_y_pic_start_ad; //!<0x98 isp_mi_pp_base
  1830. uint32_t isp_mi_pp_dma_y_pic_width; //!<0x9c isp_mi_pp_base
  1831. uint32_t isp_mi_pp_dma_y_pic_llength; //!<0xa0 isp_mi_pp_base
  1832. uint32_t isp_mi_pp_dma_y_pic_size; //!<0xa4 isp_mi_pp_base
  1833. uint32_t isp_mi_pp_dma_cb_pic_start_ad; //!<0xa8 isp_mi_pp_base
  1834. uint32_t isp_mi_pp_dma_cr_pic_start_ad; //!<0xac isp_mi_pp_base
  1835. uint32_t isp_mi_pp_dma_y_pic_start_ad_shd; //!<0xb0 isp_mi_pp_base
  1836. uint32_t isp_mi_pp_dma_cb_pic_start_ad_shd; //!<0xb4 isp_mi_pp_base
  1837. uint32_t isp_mi_pp_dma_cr_pic_start_ad_shd; //!<0xb8 isp_mi_pp_base
  1838. uint32_t isp_mi_pp_dma_y_pic_lval; //!<0xbc isp_mi_pp_base
  1839. uint32_t mi_pp_dma_y_entry_line_num;
  1840. uint32_t mi_pp_dma_y_buf_line_num;
  1841. uint32_t mi_pp_dma_y_pic_height;
  1842. uint32_t mi_pp_y_lval_bytes;
  1843. uint32_t _notused_56[(0x00005600 - 0x000055d0) / 4];
  1844. uint32_t isp_mi_sp2_raw2_ctrl; //!<0x00 isp_mi_sp2_raw2_base
  1845. uint32_t isp_mi_sp2_raw2_fmt; //!<0x04 isp_mi_sp2_raw2_base
  1846. uint32_t _notused_56_2[(0x00005620 - 0x00005608) / 4];
  1847. uint32_t isp_mi_sp2_raw2_base_ad_init; //!<0x20 isp_mi_sp2_raw2_base
  1848. uint32_t isp_mi_sp2_raw2_size_init; //!<0x24 isp_mi_sp2_raw2_base
  1849. uint32_t isp_mi_sp2_raw2_offs_cnt_init; //!<0x28 isp_mi_sp2_raw2_base
  1850. uint32_t isp_mi_sp2_raw2_llength; //!<0x2c isp_mi_sp2_raw2_base
  1851. uint32_t isp_mi_sp2_raw2_pic_width; //!<0x30 isp_mi_sp2_raw2_base
  1852. uint32_t isp_mi_sp2_raw2_pic_height; //!<0x34 isp_mi_sp2_raw2_base
  1853. uint32_t isp_mi_sp2_raw2_pic_size; //!<0x38 isp_mi_sp2_raw2_base
  1854. uint32_t isp_mi_sp2_raw2_offs_cnt_start; //!<0x3c isp_mi_sp2_raw2_base
  1855. uint32_t isp_mi_sp2_raw2_base_ad_shd; //!<0x40 isp_mi_sp2_raw2_base
  1856. uint32_t isp_mi_sp2_raw2_size_shd; //!<0x44 isp_mi_sp2_raw2_base
  1857. uint32_t isp_mi_sp2_raw2_offs_cnt_shd; //!<0x48 isp_mi_sp2_raw2_base
  1858. uint32_t _notused_56_3[(0x00005660 - 0x0000564c) / 4];
  1859. uint32_t isp_mi_sp2_dma_raw2_pic_start_ad; //!<0x60 isp_mi_sp2_raw2_base
  1860. uint32_t isp_mi_sp2_dma_raw2_pic_width; //!<0x64 isp_mi_sp2_raw2_base
  1861. uint32_t isp_mi_sp2_dma_raw2_pic_llength; //!<0x68 isp_mi_sp2_raw2_base
  1862. uint32_t isp_mi_sp2_dma_raw2_pic_size; //!<0x6c isp_mi_sp2_raw2_base
  1863. uint32_t isp_mi_sp2_dma_raw2_pic_start_ad_shd; //!<0x70 isp_mi_sp2_raw2_base
  1864. uint32_t isp_mi_sp2_dma_raw2_pic_width_shd; //!<0x74 isp_mi_sp2_raw2_base
  1865. uint32_t isp_mi_sp2_dma_raw2_pic_llength_shd; //!<0x78 isp_mi_sp2_raw2_base
  1866. uint32_t isp_mi_sp2_dma_raw2_pic_size_shd; //!<0x7c isp_mi_sp2_raw2_base
  1867. uint32_t isp_mi_sp2_dma_raw2_pic_lval; //!<0x80 isp_mi_sp2_raw2_base
  1868. uint32_t mi_sp2_dma_raw2_pic_lval_shd;
  1869. uint32_t _notused_56_4[(0x00005690 - 0x00005688) / 4];
  1870. uint32_t mi_mp_ycbcr_entry_line_num;
  1871. uint32_t mi_mp_ycbcr_entry_pic_cnt;
  1872. uint32_t mi_mp_ycbcr_entry_y_cnt;
  1873. uint32_t mi_mp_ycbcr_entry_cb_cnt;
  1874. uint32_t mi_mp_ycbcr_entry_cr_cnt;
  1875. uint32_t mi_mp_raw_entry_line_num;
  1876. uint32_t mi_mp_raw_entry_pic_cnt;
  1877. uint32_t mi_sp1_ppw_ycbcr_entry_line_num;
  1878. uint32_t mi_sp1_ppw_ycbcr_entry_pic_cnt;
  1879. uint32_t mi_mcm_raw0_entry_line_num;
  1880. uint32_t mi_mcm_raw0_entry_pic_cnt;
  1881. uint32_t _notused_56_5[(0x000056d0 - 0x000056bc) / 4];
  1882. uint32_t miv2_imsc3;
  1883. uint32_t miv2_isr3;
  1884. uint32_t miv2_mis3;
  1885. uint32_t miv2_icr3;
  1886. uint32_t miv2_ris3;
  1887. uint32_t _notused_57[(0x00005700 - 0x000056e4) / 4];
  1888. uint32_t isp_mi_hdr_ctrl; //!<0x00 isp_mi_hdr_base
  1889. uint32_t isp_mi_hdr_fmt; //!<0x04 isp_mi_hdr_base
  1890. uint32_t isp_mi_hdr_dma_start_by_lines; //!<0x08 isp_mi_hdr_base
  1891. uint32_t isp_mi_hdr_ret_bus_cfg; //!<0x0c isp_mi_hdr_base
  1892. uint32_t isp_mi_hdr_ret_bus_id; //!<0x10 isp_mi_hdr_base
  1893. uint32_t isp_mi_hdr_ret_bus_timeo; //!<0x14 isp_mi_hdr_base
  1894. uint32_t _notused_57_2[(0x00005720 - 0x00005718) / 4];
  1895. uint32_t isp_mi_hdr_pic_width; //!<0x20 isp_mi_hdr_base
  1896. uint32_t isp_mi_hdr_pic_height; //!<0x24 isp_mi_hdr_base
  1897. uint32_t _notused_57_3[(0x00005740 - 0x00005728) / 4];
  1898. uint32_t isp_mi_hdr_l_base_ad_init; //!<0x40 isp_mi_hdr_base
  1899. uint32_t isp_mi_hdr_l_size_init; //!<0x44 isp_mi_hdr_base
  1900. uint32_t isp_mi_hdr_l_offs_cnt_init; //!<0x48 isp_mi_hdr_base
  1901. uint32_t isp_mi_hdr_l_llength; //!<0x4c isp_mi_hdr_base
  1902. uint32_t isp_mi_hdr_l_pic_lval; //!<0x50 isp_mi_hdr_base
  1903. uint32_t isp_mi_hdr_l_irq_offs_init; //!<0x54 isp_mi_hdr_base
  1904. uint32_t isp_mi_hdr_l_offs_cnt_start; //!<0x58 isp_mi_hdr_base
  1905. uint32_t isp_mi_hdr_l_base_ad_shd; //!<0x5c isp_mi_hdr_base
  1906. uint32_t isp_mi_hdr_l_size_shd; //!<0x60 isp_mi_hdr_base
  1907. uint32_t isp_mi_hdr_l_offs_cnt_shd; //!<0x64 isp_mi_hdr_base
  1908. uint32_t isp_mi_hdr_l_irq_offs_shd; //!<0x68 isp_mi_hdr_base
  1909. uint32_t _notused_57_4[(0x00005780 - 0x0000576c) / 4];
  1910. uint32_t isp_mi_hdr_s_base_ad_init; //!<0x80 isp_mi_hdr_base
  1911. uint32_t isp_mi_hdr_s_size_init; //!<0x84 isp_mi_hdr_base
  1912. uint32_t isp_mi_hdr_s_offs_cnt_init; //!<0x88 isp_mi_hdr_base
  1913. uint32_t isp_mi_hdr_s_llength; //!<0x8c isp_mi_hdr_base
  1914. uint32_t isp_mi_hdr_s_pic_lval; //!<0x90 isp_mi_hdr_base
  1915. uint32_t isp_mi_hdr_s_irq_offs_init; //!<0x94 isp_mi_hdr_base
  1916. uint32_t isp_mi_hdr_s_offs_cnt_start; //!<0x98 isp_mi_hdr_base
  1917. uint32_t isp_mi_hdr_s_base_ad_shd; //!<0x9c isp_mi_hdr_base
  1918. uint32_t isp_mi_hdr_s_size_shd; //!<0xa0 isp_mi_hdr_base
  1919. uint32_t isp_mi_hdr_s_offs_cnt_shd; //!<0xa4 isp_mi_hdr_base
  1920. uint32_t isp_mi_hdr_s_irq_offs_shd; //!<0xa8 isp_mi_hdr_base
  1921. uint32_t _notused_57_5[(0x000057c0 - 0x000057ac) / 4];
  1922. uint32_t isp_mi_hdr_vs_base_ad_init; //!<0xc0 isp_mi_hdr_base
  1923. uint32_t isp_mi_hdr_vs_size_init; //!<0xc4 isp_mi_hdr_base
  1924. uint32_t isp_mi_hdr_vs_offs_cnt_init; //!<0xc8 isp_mi_hdr_base
  1925. uint32_t isp_mi_hdr_vs_llength; //!<0xcc isp_mi_hdr_base
  1926. uint32_t isp_mi_hdr_vs_pic_lval; //!<0xd0 isp_mi_hdr_base
  1927. uint32_t isp_mi_hdr_vs_irq_offs_init; //!<0xd4 isp_mi_hdr_base
  1928. uint32_t isp_mi_hdr_vs_offs_cnt_start; //!<0xd8 isp_mi_hdr_base
  1929. uint32_t isp_mi_hdr_vs_base_ad_shd; //!<0xdc isp_mi_hdr_base
  1930. uint32_t isp_mi_hdr_vs_size_shd; //!<0xe0 isp_mi_hdr_base
  1931. uint32_t isp_mi_hdr_vs_offs_cnt_shd; //!<0xe4 isp_mi_hdr_base
  1932. uint32_t isp_mi_hdr_vs_irq_offs_shd; //!<0xe8 isp_mi_hdr_base
  1933. uint32_t _notused_58[(0x00005800 - 0x000057ec) / 4];
  1934. uint32_t isp_mi_hdr_dma_pic_width; //!<0x00 isp_mi_hdr_dma_base
  1935. uint32_t isp_mi_hdr_dma_pic_height; //!<0x04 isp_mi_hdr_dma_base
  1936. uint32_t _notused_58_1[(0x00005820 - 0x00005808) / 4];
  1937. uint32_t isp_mi_hdr_dma_l_base_ad_init; //!<0x20 isp_mi_hdr_dma_base
  1938. uint32_t isp_mi_hdr_dma_l_size_init; //!<0x24 isp_mi_hdr_dma_base
  1939. uint32_t isp_mi_hdr_dma_l_llength; //!<0x28 isp_mi_hdr_dma_base
  1940. uint32_t isp_mi_hdr_dma_l_lval; //!<0x2c isp_mi_hdr_dma_base
  1941. uint32_t isp_mi_hdr_dma_l_base_ad_shd; //!<0x30 isp_mi_hdr_dma_base
  1942. uint32_t isp_mi_hdr_dma_l_size_shd; //!<0x34 isp_mi_hdr_dma_base
  1943. uint32_t _notused_58_2[(0x00005850 - 0x00005838) / 4];
  1944. uint32_t isp_mi_hdr_dma_s_base_ad_init; //!<0x50 isp_mi_hdr_dma_base
  1945. uint32_t isp_mi_hdr_dma_s_size_init; //!<0x54 isp_mi_hdr_dma_base
  1946. uint32_t isp_mi_hdr_dma_s_llength; //!<0x58 isp_mi_hdr_dma_base
  1947. uint32_t isp_mi_hdr_dma_s_lval; //!<0x5c isp_mi_hdr_dma_base
  1948. uint32_t isp_mi_hdr_dma_s_base_ad_shd; //!<0x60 isp_mi_hdr_dma_base
  1949. uint32_t isp_mi_hdr_dma_s_size_shd; //!<0x64 isp_mi_hdr_dma_base
  1950. uint32_t _notused_58_3[(0x00005880 - 0x00005868) / 4];
  1951. uint32_t isp_mi_hdr_dma_vs_base_ad_init; //!<0x80 isp_mi_hdr_dma_base
  1952. uint32_t isp_mi_hdr_dma_vs_size_init; //!<0x84 isp_mi_hdr_dma_base
  1953. uint32_t isp_mi_hdr_dma_vs_llength; //!<0x88 isp_mi_hdr_dma_base
  1954. uint32_t isp_mi_hdr_dma_vs_lval; //!<0x8c isp_mi_hdr_dma_base
  1955. uint32_t isp_mi_hdr_dma_vs_base_ad_shd; //!<0x90 isp_mi_hdr_dma_base
  1956. uint32_t isp_mi_hdr_dma_vs_size_shd; //!<0x94 isp_mi_hdr_dma_base
  1957. uint32_t _notused_58_4[(0x00005900 - 0x00005898) / 4];
  1958. uint32_t isp_hdr_ret_ctrl; //!<0x00 isp_hdr_ret_base
  1959. uint32_t isp_hdr_interval; //!<0x04 isp_hdr_ret_base
  1960. uint32_t isp_hdr_ret_h_blank; //!<0x08 isp_hdr_ret_h_blank
  1961. uint32_t isp_hdr_ret_v_blank; //!<0x0c isp_hdr_ret_v_blank
  1962. uint32_t isp_hdr_ret_h_size; //!<0x010 isp_hdr_ret_h_size
  1963. uint32_t isp_hdr_ret_v_size; //!<0x014 isp_hdr_ret_v_size
  1964. } MrvAllRegister_t;
  1965. /* - MASK AND SHIFT MARCOS ----------------------------------------------------------*/
  1966. /*! Register: vi_ccl: Clock control register (0x00000000)*/
  1967. /*! Slice: vi_ccl_dis:*/
  1968. /*! Clock Control Logic disable */
  1969. /* 0: processing/cfg-clocks for all marvin sub modules enabled */
  1970. /* 1: processing/cfg-clocks for all marvin sub modules disabled w/o access to ID and VI_CCL register */
  1971. #define MRV_VI_CCL_DIS
  1972. #define MRV_VI_CCL_DIS_MASK 0x00000004U
  1973. #define MRV_VI_CCL_DIS_SHIFT 2U
  1974. /*! Slice: vi_ccl_dis_status:*/
  1975. /*! Status of vi_ccl[2] bit (copy of vi_ccl[2])*/
  1976. #define MRV_VI_CCL_DIS_STATUS
  1977. #define MRV_VI_CCL_DIS_STATUS_MASK 0x00000002U
  1978. #define MRV_VI_CCL_DIS_STATUS_SHIFT 1U
  1979. /*! Register: vi_id: Revision identification register (0x00000008)*/
  1980. /*! Slice: rev_id:*/
  1981. /*! MARVIN5 revision IDs:*/
  1982. /* M5_v1 id = 0x0015'3010 release 1.0 */
  1983. /* M5_v1 id = 0x1015'3010 release 1.1 */
  1984. /* M5_v2 id = 0x0025'3010 */
  1985. /* M5_v2 id = 0x0075'3010 release 2.0 (full feature set)*/
  1986. /* M5_v3 id = 0x0035'3010 */
  1987. /* M5_v3 id = 0x2035'3010 with bug fixes in MIPI, MI, LSC */
  1988. /* M5_v4 id = 0x0045'3010 */
  1989. /* M5_v4 id = 0x1045'3010 with bug fixes in MIPI, MI, LSC */
  1990. /* M5_v6 id = 0x0055'3010 */
  1991. /* M5_v7 id = 0x0065'3010 */
  1992. /* M12_v1 id (Rel. 1.0) = 0x0015'3017 */
  1993. /* M12_v1 id (Rel. 1.2) = 0x1015'3017 */
  1994. /* M12_v1 id (Rel. 2.0) = 0x2015'3017 */
  1995. /* M12_v1 id (Rel. 2.1) = 0x3015'3017 */
  1996. /* M12_v2 id = 0x0025'3017 */
  1997. /* M12_v3 id (Rel. 1.0) = 0x0065'3017 */
  1998. /* M12_v3 id (Rel. 1.1) = 0x1065'3017 */
  1999. /* M14_v1 id (Rel. 1.0) = 0x0075'3017 */
  2000. /* M14_v1 id (Rel. 1.1) = 0x1075'3017 */
  2001. /* M14_v2 id (Rel. 1.0) = 0x0085'3017 */
  2002. /* M18_v1 id = 0x0035'3017 (MarvinBase)*/
  2003. /* M20_v1 id (Rel. 1.0) = 0x0055'3017 */
  2004. /* M20_v1 id (Rel. 1.1) = 0x1055'3017 */
  2005. /* M20_v1 id (Rel. 1.2) = 0x2055'3017 */
  2006. /* M20_v2 id (Rel. 1.0) = 0x0095'3017 */
  2007. /* M64_v1 id = 0x0045'3017 */
  2008. #define MRV_REV_ID
  2009. #define MRV_REV_ID_MASK 0xFFFFFFFFU
  2010. #define MRV_REV_ID_SHIFT 0U
  2011. /*! Register: vi_iccl: Internal clock control register (0x00000010)*/
  2012. /*! Slice: vi_mipi_clk_enable:*/
  2013. /*! MIPI interface clock enable */
  2014. /* 1: processing mode */
  2015. /* 0: power safe */
  2016. #define MRV_VI_MIPI_CLK_ENABLE
  2017. #define MRV_VI_MIPI_CLK_ENABLE_MASK 0x00000800U
  2018. #define MRV_VI_MIPI_CLK_ENABLE_SHIFT 11U
  2019. /*! Slice: vi_smia_clk_enable:*/
  2020. /*! SMIA interface clock enable */
  2021. /* 1: processing mode */
  2022. /* 0: power safe */
  2023. #define MRV_VI_SMIA_CLK_ENABLE
  2024. #define MRV_VI_SMIA_CLK_ENABLE_MASK 0x00000400U
  2025. #define MRV_VI_SMIA_CLK_ENABLE_SHIFT 10U
  2026. /*! Slice: vi_simp_clk_enable:*/
  2027. /*! Superimpose clock enable */
  2028. /* 1: processing mode */
  2029. /* 0: power safe */
  2030. #define MRV_VI_SIMP_CLK_ENABLE
  2031. #define MRV_VI_SIMP_CLK_ENABLE_MASK 0x00000200U
  2032. #define MRV_VI_SIMP_CLK_ENABLE_SHIFT 9U
  2033. /*! Slice: vi_ie_clk_enable:*/
  2034. /*! Image effect clock enable */
  2035. /* 1: processing mode */
  2036. /* 0: power safe */
  2037. #define MRV_VI_IE_CLK_ENABLE
  2038. #define MRV_VI_IE_CLK_ENABLE_MASK 0x00000100U
  2039. #define MRV_VI_IE_CLK_ENABLE_SHIFT 8U
  2040. /*! Slice: vi_mi_clk_enable:*/
  2041. /*! memory interface clock enable */
  2042. /* 1: processing mode */
  2043. /* 0: power safe */
  2044. #define MRV_VI_MI_CLK_ENABLE
  2045. #define MRV_VI_MI_CLK_ENABLE_MASK 0x00000040U
  2046. #define MRV_VI_MI_CLK_ENABLE_SHIFT 6U
  2047. /*! Slice: vi_jpeg_clk_enable:*/
  2048. /*! JPEG encoder clock enable */
  2049. /* 1: processing mode */
  2050. /* 0: power safe */
  2051. #define MRV_VI_JPEG_CLK_ENABLE
  2052. #define MRV_VI_JPEG_CLK_ENABLE_MASK 0x00000020U
  2053. #define MRV_VI_JPEG_CLK_ENABLE_SHIFT 5U
  2054. /*! Slice: vi_srsz_clk_enable:*/
  2055. /*! self picture resize clock enable */
  2056. /* 1: processing mode */
  2057. /* 0: power safe */
  2058. #define MRV_VI_SRSZ_CLK_ENABLE
  2059. #define MRV_VI_SRSZ_CLK_ENABLE_MASK 0x00000010U
  2060. #define MRV_VI_SRSZ_CLK_ENABLE_SHIFT 4U
  2061. /*! Slice: vi_mrsz_clk_enable:*/
  2062. /*! main picture resize clock enable */
  2063. /* 1: processing mode */
  2064. /* 0: power safe */
  2065. #define MRV_VI_MRSZ_CLK_ENABLE
  2066. #define MRV_VI_MRSZ_CLK_ENABLE_MASK 0x00000008U
  2067. #define MRV_VI_MRSZ_CLK_ENABLE_SHIFT 3U
  2068. /*! Slice: vi_cp_clk_enable:*/
  2069. /*! color processing clock enable */
  2070. /* 1: processing mode */
  2071. /* 0: power safe */
  2072. #define MRV_VI_CP_CLK_ENABLE
  2073. #define MRV_VI_CP_CLK_ENABLE_MASK 0x00000002U
  2074. #define MRV_VI_CP_CLK_ENABLE_SHIFT 1U
  2075. /*! Slice: vi_isp_clk_enable:*/
  2076. /*! isp processing clock enable */
  2077. /* 1: processing mode */
  2078. /* 0: power safe */
  2079. #define MRV_VI_ISP_CLK_ENABLE
  2080. #define MRV_VI_ISP_CLK_ENABLE_MASK 0x00000001U
  2081. #define MRV_VI_ISP_CLK_ENABLE_SHIFT 0U
  2082. /*! Register: vi_ircl: Internal reset control register (0x00000014)*/
  2083. /*! Slice: vi_mipi_soft_rst:*/
  2084. /*! MIPI Interface software reset */
  2085. /* 0: processing mode */
  2086. /* 1: reset state */
  2087. #define MRV_VI_MIPI_SOFT_RST
  2088. #define MRV_VI_MIPI_SOFT_RST_MASK 0x00000800U
  2089. #define MRV_VI_MIPI_SOFT_RST_SHIFT 11U
  2090. /*! Slice: vi_smia_soft_rst:*/
  2091. /*! SMIA Interface software reset */
  2092. /* 0: processing mode */
  2093. /* 1: reset state */
  2094. #define MRV_VI_SMIA_SOFT_RST
  2095. #define MRV_VI_SMIA_SOFT_RST_MASK 0x00000400U
  2096. #define MRV_VI_SMIA_SOFT_RST_SHIFT 10U
  2097. /*! Slice: vi_simp_soft_rst:*/
  2098. /*! Superimpose software reset */
  2099. /* 0: processing mode */
  2100. /* 1: reset state */
  2101. #define MRV_VI_SIMP_SOFT_RST
  2102. #define MRV_VI_SIMP_SOFT_RST_MASK 0x00000200U
  2103. #define MRV_VI_SIMP_SOFT_RST_SHIFT 9U
  2104. /*! Slice: vi_ie_soft_rst:*/
  2105. /*! Image effect software reset */
  2106. /* 0: processing mode */
  2107. /* 1: reset state */
  2108. #define MRV_VI_IE_SOFT_RST
  2109. #define MRV_VI_IE_SOFT_RST_MASK 0x00000100U
  2110. #define MRV_VI_IE_SOFT_RST_SHIFT 8U
  2111. /*! Slice: vi_marvin_rst:*/
  2112. /*! hardware reset of entire marvin */
  2113. /* 0: processing mode */
  2114. /* 1: reset state */
  2115. #define MRV_VI_MARVIN_RST
  2116. #define MRV_VI_MARVIN_RST_MASK 0x00000080U
  2117. #define MRV_VI_MARVIN_RST_SHIFT 7U
  2118. /*! Slice: vi_mi_soft_rst:*/
  2119. /*! memory interface software reset */
  2120. /* 0: processing mode */
  2121. /* 1: reset state */
  2122. #define MRV_VI_MI_SOFT_RST
  2123. #define MRV_VI_MI_SOFT_RST_MASK 0x00000040U
  2124. #define MRV_VI_MI_SOFT_RST_SHIFT 6U
  2125. /*! Slice: vi_jpeg_soft_rst:*/
  2126. /*! JPEG encoder software reset */
  2127. /* 0: processing mode */
  2128. /* 1: reset state */
  2129. #define MRV_VI_JPEG_SOFT_RST
  2130. #define MRV_VI_JPEG_SOFT_RST_MASK 0x00000020U
  2131. #define MRV_VI_JPEG_SOFT_RST_SHIFT 5U
  2132. /*! Slice: vi_srsz_soft_rst:*/
  2133. /*! Self-picture resize software reset */
  2134. /* 0: processing mode */
  2135. /* 1: reset state */
  2136. #define MRV_VI_SRSZ_SOFT_RST
  2137. #define MRV_VI_SRSZ_SOFT_RST_MASK 0x00000010U
  2138. #define MRV_VI_SRSZ_SOFT_RST_SHIFT 4U
  2139. /*! Slice: vi_mrsz_soft_rst:*/
  2140. /*! Main-picture resize software reset */
  2141. /* 0: processing mode */
  2142. /* 1: reset state */
  2143. #define MRV_VI_MRSZ_SOFT_RST
  2144. #define MRV_VI_MRSZ_SOFT_RST_MASK 0x00000008U
  2145. #define MRV_VI_MRSZ_SOFT_RST_SHIFT 3U
  2146. /*! Slice: vi_ycs_soft_rst:*/
  2147. /*! y/c splitter software reset */
  2148. /* 0: processing mode */
  2149. /* 1: reset state */
  2150. #define MRV_VI_YCS_SOFT_RST
  2151. #define MRV_VI_YCS_SOFT_RST_MASK 0x00000004U
  2152. #define MRV_VI_YCS_SOFT_RST_SHIFT 2U
  2153. /*! Slice: vi_cp_soft_rst:*/
  2154. /*! color processing software reset */
  2155. /* 0: processing mode */
  2156. /* 1: reset state */
  2157. #define MRV_VI_CP_SOFT_RST
  2158. #define MRV_VI_CP_SOFT_RST_MASK 0x00000002U
  2159. #define MRV_VI_CP_SOFT_RST_SHIFT 1U
  2160. /*! Slice: vi_isp_soft_rst:*/
  2161. /*! isp software reset */
  2162. /* 0: processing mode */
  2163. /* 1: reset state */
  2164. #define MRV_VI_ISP_SOFT_RST
  2165. #define MRV_VI_ISP_SOFT_RST_MASK 0x00000001U
  2166. #define MRV_VI_ISP_SOFT_RST_SHIFT 0U
  2167. /*! Register: vi_dpcl: Data path control register (0x00000018)*/
  2168. /*! Slice: vi_dma_spmux:*/
  2169. /*! 0: data from camera interface to self resize */
  2170. /* 1: data from DMA read port to self resize */
  2171. #define MRV_VI_DMA_SPMUX
  2172. #define MRV_VI_DMA_SPMUX_MASK 0x00000800U
  2173. #define MRV_VI_DMA_SPMUX_SHIFT 11U
  2174. /*! Slice: vi_dma_iemux:*/
  2175. /*! 0: data from camera interface to image effects */
  2176. /* 1: data from DMA read port to image effects */
  2177. #define MRV_VI_DMA_IEMUX
  2178. #define MRV_VI_DMA_IEMUX_MASK 0x00000400U
  2179. #define MRV_VI_DMA_IEMUX_SHIFT 10U
  2180. /*! Slice: if_select:*/
  2181. /*! selects input interface */
  2182. /* 0: parallel interface */
  2183. /* 1: SMIA-interface */
  2184. /* 2: MIPI-interface */
  2185. /* 3: HDR-interface */
  2186. #define MRV_IF_SELECT
  2187. #define MRV_IF_SELECT_MASK 0x00000300U
  2188. #define MRV_IF_SELECT_SHIFT 8U
  2189. /*! Slice: vi_dma_switch:*/
  2190. /*! DMA read data path selector */
  2191. /* 0: path to SPMUX */
  2192. /* 1: path to Superimpose */
  2193. /* 2: path to Image Effects */
  2194. /* 3: path to JPEG encoder */
  2195. /* 4: path to ISP Bayer RGB */
  2196. /* 5..7: reserved */
  2197. #define MRV_VI_DMA_SWITCH
  2198. #define MRV_VI_DMA_SWITCH_MASK 0x00000070U
  2199. #define MRV_VI_DMA_SWITCH_SHIFT 4U
  2200. /*! Slice: vi_chan_mode:*/
  2201. /*! Y/C splitter channel mode */
  2202. /* 0: disabled */
  2203. /* 1: main path and raw data mode */
  2204. /* 2: self path mode */
  2205. /* 3: main and self path mode */
  2206. #define MRV_VI_CHAN_MODE
  2207. #ifdef ISPVI_EXPAND_CHAN
  2208. #define MRV_VI_CHAN_MODE_MASK 0x00007000U
  2209. #define MRV_VI_CHAN_MODE_SHIFT 12U
  2210. #else
  2211. #define MRV_VI_CHAN_MODE_MASK 0x0000000CU
  2212. #define MRV_VI_CHAN_MODE_SHIFT 2U
  2213. #endif
  2214. /*! Slice: vi_mp_mux:*/
  2215. /*! data path selector for main path */
  2216. /* 00: data from DMA read port to JPEG encoder */
  2217. /* 01: data from main resize to MI, uncompressed */
  2218. /* 10: data from main resize to JPEG encoder */
  2219. /* 11: reserved */
  2220. #define MRV_VI_MP_MUX
  2221. #define MRV_VI_MP_MUX_MASK 0x00000003U
  2222. #define MRV_VI_MP_MUX_SHIFT 0U
  2223. #define MRV_VI_DPCL_STRM_MUX
  2224. #define MRV_VI_DPCL_STRM_MUX_MASK 0x00040000U
  2225. #define MRV_VI_DPCL_STRM_MUX_SHIFT 18U
  2226. /*! Register: img_eff_ctrl: Global control register (0x00000000)*/
  2227. /*! Slice: full_range:*/
  2228. /*! '0': pixel value range according to BT.601 */
  2229. /* '1': YCbCr full range 0...255 */
  2230. #define MRV_IMGEFF_FULL_RANGE
  2231. #define MRV_IMGEFF_FULL_RANGE_MASK 0x00000020U
  2232. #define MRV_IMGEFF_FULL_RANGE_SHIFT 5U
  2233. /*! Slice: cfg_upd:*/
  2234. /*! write '0': nothing happens */
  2235. /* write '1': update shadow registers */
  2236. /* read: always '0'*/
  2237. #define MRV_IMGEFF_CFG_UPD
  2238. #define MRV_IMGEFF_CFG_UPD_MASK 0x00000010U
  2239. #define MRV_IMGEFF_CFG_UPD_SHIFT 4U
  2240. /*! Slice: effect_mode:*/
  2241. /*! effect mode */
  2242. /* 000: black & white effect (grayscale)*/
  2243. /* 001: negative */
  2244. /* 010: sepia effect */
  2245. /* 011: color selection effect */
  2246. /* 100: emboss effect */
  2247. /* 101: sketch effect */
  2248. /* 110: sharpen effect */
  2249. /* 111: reserved */
  2250. #define MRV_IMGEFF_EFFECT_MODE
  2251. #define MRV_IMGEFF_EFFECT_MODE_MASK 0x0000000EU
  2252. #define MRV_IMGEFF_EFFECT_MODE_SHIFT 1U
  2253. /*! Slice: bypass_mode:*/
  2254. /*! bypass mode */
  2255. /* 1: processing is activated */
  2256. /* 0: processing is deactivated, bypass mode is selected */
  2257. #define MRV_IMGEFF_BYPASS_MODE
  2258. #define MRV_IMGEFF_BYPASS_MODE_MASK 0x00000001U
  2259. #define MRV_IMGEFF_BYPASS_MODE_SHIFT 0U
  2260. /*! Register: img_eff_color_sel: Color selection register (for color selection effect) (0x00000004)*/
  2261. /*! Slice: color_threshold:*/
  2262. /*! Threshold value of the RGB colors for the color selection effect.*/
  2263. #define MRV_IMGEFF_COLOR_THRESHOLD
  2264. #define MRV_IMGEFF_COLOR_THRESHOLD_MASK 0x0000FF00U
  2265. #define MRV_IMGEFF_COLOR_THRESHOLD_SHIFT 8U
  2266. /*! Slice: color_selection:*/
  2267. /*! Defining the maintained color:*/
  2268. /* 000: red green and blue */
  2269. /* 001: blue */
  2270. /* 010: green */
  2271. /* 011: green and blue */
  2272. /* 100: red */
  2273. /* 101: red and blue */
  2274. /* 110: red and green */
  2275. /* 111: red green and blue */
  2276. #define MRV_IMGEFF_COLOR_SELECTION
  2277. #define MRV_IMGEFF_COLOR_SELECTION_MASK 0x00000007U
  2278. #define MRV_IMGEFF_COLOR_SELECTION_SHIFT 0U
  2279. /*! Register: img_eff_mat_1: 3x3 matrix coefficients for emboss effect (1) (0x00000008)*/
  2280. /*! Slice: emb_coef_21_en:*/
  2281. /*! 0: entry not used (coefficient is zero)*/
  2282. /* 1: entry used */
  2283. #define MRV_IMGEFF_EMB_COEF_21_EN
  2284. #define MRV_IMGEFF_EMB_COEF_21_EN_MASK 0x00008000U
  2285. #define MRV_IMGEFF_EMB_COEF_21_EN_SHIFT 15U
  2286. /*! Slice: emb_coef_21:*/
  2287. /*! second line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  2288. #define MRV_IMGEFF_EMB_COEF_21
  2289. #define MRV_IMGEFF_EMB_COEF_21_MASK 0x00007000U
  2290. #define MRV_IMGEFF_EMB_COEF_21_SHIFT 12U
  2291. /*! Slice: emb_coef_13_en:*/
  2292. /*! 0: entry not used (coefficient is zero)*/
  2293. /* 1: entry used */
  2294. #define MRV_IMGEFF_EMB_COEF_13_EN
  2295. #define MRV_IMGEFF_EMB_COEF_13_EN_MASK 0x00000800U
  2296. #define MRV_IMGEFF_EMB_COEF_13_EN_SHIFT 11U
  2297. /*! Slice: emb_coef_13:*/
  2298. /*! first line, right entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  2299. #define MRV_IMGEFF_EMB_COEF_13
  2300. #define MRV_IMGEFF_EMB_COEF_13_MASK 0x00000700U
  2301. #define MRV_IMGEFF_EMB_COEF_13_SHIFT 8U
  2302. /*! Slice: emb_coef_12_en:*/
  2303. /*! 0: entry not used (coefficient is zero)*/
  2304. /* 1: entry used */
  2305. #define MRV_IMGEFF_EMB_COEF_12_EN
  2306. #define MRV_IMGEFF_EMB_COEF_12_EN_MASK 0x00000080U
  2307. #define MRV_IMGEFF_EMB_COEF_12_EN_SHIFT 7U
  2308. /*! Slice: emb_coef_12:*/
  2309. /*! first line, middle entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  2310. #define MRV_IMGEFF_EMB_COEF_12
  2311. #define MRV_IMGEFF_EMB_COEF_12_MASK 0x00000070U
  2312. #define MRV_IMGEFF_EMB_COEF_12_SHIFT 4U
  2313. /*! Slice: emb_coef_11_en:*/
  2314. /*! 0: entry not used (coefficient is zero)*/
  2315. /* 1: entry used */
  2316. #define MRV_IMGEFF_EMB_COEF_11_EN
  2317. #define MRV_IMGEFF_EMB_COEF_11_EN_MASK 0x00000008U
  2318. #define MRV_IMGEFF_EMB_COEF_11_EN_SHIFT 3U
  2319. /*! Slice: emb_coef_11:*/
  2320. /*! first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  2321. #define MRV_IMGEFF_EMB_COEF_11
  2322. #define MRV_IMGEFF_EMB_COEF_11_MASK 0x00000007U
  2323. #define MRV_IMGEFF_EMB_COEF_11_SHIFT 0U
  2324. /*! Register: img_eff_mat_2: 3x3 matrix coefficients for emboss effect (2) (0x0000000c)*/
  2325. /*! Slice: emb_coef_32_en:*/
  2326. /*! 0: entry not used (coefficient is zero)*/
  2327. /* 1: entry used */
  2328. #define MRV_IMGEFF_EMB_COEF_32_EN
  2329. #define MRV_IMGEFF_EMB_COEF_32_EN_MASK 0x00008000U
  2330. #define MRV_IMGEFF_EMB_COEF_32_EN_SHIFT 15U
  2331. /*! Slice: emb_coef_32:*/
  2332. /*! third line, middle entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  2333. #define MRV_IMGEFF_EMB_COEF_32
  2334. #define MRV_IMGEFF_EMB_COEF_32_MASK 0x00007000U
  2335. #define MRV_IMGEFF_EMB_COEF_32_SHIFT 12U
  2336. /*! Slice: emb_coef_31_en:*/
  2337. /*! 0: entry not used (coefficient is zero)*/
  2338. /* 1: entry used */
  2339. #define MRV_IMGEFF_EMB_COEF_31_EN
  2340. #define MRV_IMGEFF_EMB_COEF_31_EN_MASK 0x00000800U
  2341. #define MRV_IMGEFF_EMB_COEF_31_EN_SHIFT 11U
  2342. /*! Slice: emb_coef_31:*/
  2343. /*! third line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  2344. #define MRV_IMGEFF_EMB_COEF_31
  2345. #define MRV_IMGEFF_EMB_COEF_31_MASK 0x00000700U
  2346. #define MRV_IMGEFF_EMB_COEF_31_SHIFT 8U
  2347. /*! Slice: emb_coef_23_en:*/
  2348. /*! 0: entry not used (coefficient is zero)*/
  2349. /* 1: entry used */
  2350. #define MRV_IMGEFF_EMB_COEF_23_EN
  2351. #define MRV_IMGEFF_EMB_COEF_23_EN_MASK 0x00000080U
  2352. #define MRV_IMGEFF_EMB_COEF_23_EN_SHIFT 7U
  2353. /*! Slice: emb_coef_23:*/
  2354. /*! second line, right entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  2355. #define MRV_IMGEFF_EMB_COEF_23
  2356. #define MRV_IMGEFF_EMB_COEF_23_MASK 0x00000070U
  2357. #define MRV_IMGEFF_EMB_COEF_23_SHIFT 4U
  2358. /*! Slice: emb_coef_22_en:*/
  2359. /*! 0: entry not used (coefficient is zero)*/
  2360. /* 1: entry used */
  2361. #define MRV_IMGEFF_EMB_COEF_22_EN
  2362. #define MRV_IMGEFF_EMB_COEF_22_EN_MASK 0x00000008U
  2363. #define MRV_IMGEFF_EMB_COEF_22_EN_SHIFT 3U
  2364. /*! Slice: emb_coef_22:*/
  2365. /*! second line, middle entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  2366. #define MRV_IMGEFF_EMB_COEF_22
  2367. #define MRV_IMGEFF_EMB_COEF_22_MASK 0x00000007U
  2368. #define MRV_IMGEFF_EMB_COEF_22_SHIFT 0U
  2369. /*! Register: img_eff_mat_3: 3x3 matrix coefficients for emboss(3) effect / sketch/sharpen(1) effect (0x00000010)*/
  2370. /*! Slice: sket_coef_13_en:*/
  2371. /*! 0: entry not used (coefficient is zero)*/
  2372. /* 1: entry used */
  2373. #define MRV_IMGEFF_SKET_COEF_13_EN
  2374. #define MRV_IMGEFF_SKET_COEF_13_EN_MASK 0x00008000U
  2375. #define MRV_IMGEFF_SKET_COEF_13_EN_SHIFT 15U
  2376. /*! Slice: sket_coef_13:*/
  2377. /*! first line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  2378. #define MRV_IMGEFF_SKET_COEF_13
  2379. #define MRV_IMGEFF_SKET_COEF_13_MASK 0x00007000U
  2380. #define MRV_IMGEFF_SKET_COEF_13_SHIFT 12U
  2381. /*! Slice: sket_coef_12_en:*/
  2382. /*! 0: entry not used (coefficient is zero)*/
  2383. /* 1: entry used */
  2384. #define MRV_IMGEFF_SKET_COEF_12_EN
  2385. #define MRV_IMGEFF_SKET_COEF_12_EN_MASK 0x00000800U
  2386. #define MRV_IMGEFF_SKET_COEF_12_EN_SHIFT 11U
  2387. /*! Slice: sket_coef_12:*/
  2388. /*! first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  2389. #define MRV_IMGEFF_SKET_COEF_12
  2390. #define MRV_IMGEFF_SKET_COEF_12_MASK 0x00000700U
  2391. #define MRV_IMGEFF_SKET_COEF_12_SHIFT 8U
  2392. /*! Slice: sket_coef_11_en:*/
  2393. /*! 0: entry not used (coefficient is zero)*/
  2394. /* 1: entry used */
  2395. #define MRV_IMGEFF_SKET_COEF_11_EN
  2396. #define MRV_IMGEFF_SKET_COEF_11_EN_MASK 0x00000080U
  2397. #define MRV_IMGEFF_SKET_COEF_11_EN_SHIFT 7U
  2398. /*! Slice: sket_coef_11:*/
  2399. /*! first line, left entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  2400. #define MRV_IMGEFF_SKET_COEF_11
  2401. #define MRV_IMGEFF_SKET_COEF_11_MASK 0x00000070U
  2402. #define MRV_IMGEFF_SKET_COEF_11_SHIFT 4U
  2403. /*! Slice: emb_coef_33_en:*/
  2404. /*! 0: entry not used (coefficient is zero)*/
  2405. /* 1: entry used */
  2406. #define MRV_IMGEFF_EMB_COEF_33_EN
  2407. #define MRV_IMGEFF_EMB_COEF_33_EN_MASK 0x00000008U
  2408. #define MRV_IMGEFF_EMB_COEF_33_EN_SHIFT 3U
  2409. /*! Slice: emb_coef_33:*/
  2410. /*! third line, right entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  2411. #define MRV_IMGEFF_EMB_COEF_33
  2412. #define MRV_IMGEFF_EMB_COEF_33_MASK 0x00000007U
  2413. #define MRV_IMGEFF_EMB_COEF_33_SHIFT 0U
  2414. /*! Register: img_eff_mat_4: 3x3 matrix coefficients for sketch/sharpen effect (2) (0x00000014)*/
  2415. /*! Slice: sket_coef_31_en:*/
  2416. /*! 0: entry not used (coefficient is zero)*/
  2417. /* 1: entry used */
  2418. #define MRV_IMGEFF_SKET_COEF_31_EN
  2419. #define MRV_IMGEFF_SKET_COEF_31_EN_MASK 0x00008000U
  2420. #define MRV_IMGEFF_SKET_COEF_31_EN_SHIFT 15U
  2421. /*! Slice: sket_coef_31:*/
  2422. /*! third line, left entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  2423. #define MRV_IMGEFF_SKET_COEF_31
  2424. #define MRV_IMGEFF_SKET_COEF_31_MASK 0x00007000U
  2425. #define MRV_IMGEFF_SKET_COEF_31_SHIFT 12U
  2426. /*! Slice: sket_coef_23_en:*/
  2427. /*! 0: entry not used (coefficient is zero)*/
  2428. /* 1: entry used */
  2429. #define MRV_IMGEFF_SKET_COEF_23_EN
  2430. #define MRV_IMGEFF_SKET_COEF_23_EN_MASK 0x00000800U
  2431. #define MRV_IMGEFF_SKET_COEF_23_EN_SHIFT 11U
  2432. /*! Slice: sket_coef_23:*/
  2433. /*! second line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  2434. #define MRV_IMGEFF_SKET_COEF_23
  2435. #define MRV_IMGEFF_SKET_COEF_23_MASK 0x00000700U
  2436. #define MRV_IMGEFF_SKET_COEF_23_SHIFT 8U
  2437. /*! Slice: sket_coef_22_en:*/
  2438. /*! 0: entry not used (coefficient is zero)*/
  2439. /* 1: entry used */
  2440. #define MRV_IMGEFF_SKET_COEF_22_EN
  2441. #define MRV_IMGEFF_SKET_COEF_22_EN_MASK 0x00000080U
  2442. #define MRV_IMGEFF_SKET_COEF_22_EN_SHIFT 7U
  2443. /*! Slice: sket_coef_22:*/
  2444. /*! second line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  2445. #define MRV_IMGEFF_SKET_COEF_22
  2446. #define MRV_IMGEFF_SKET_COEF_22_MASK 0x00000070U
  2447. #define MRV_IMGEFF_SKET_COEF_22_SHIFT 4U
  2448. /*! Slice: sket_coef_21_en:*/
  2449. /*! 0: entry not used (coefficient is zero)*/
  2450. /* 1: entry used */
  2451. #define MRV_IMGEFF_SKET_COEF_21_EN
  2452. #define MRV_IMGEFF_SKET_COEF_21_EN_MASK 0x00000008U
  2453. #define MRV_IMGEFF_SKET_COEF_21_EN_SHIFT 3U
  2454. /*! Slice: sket_coef_21:*/
  2455. /*! second line, left entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  2456. #define MRV_IMGEFF_SKET_COEF_21
  2457. #define MRV_IMGEFF_SKET_COEF_21_MASK 0x00000007U
  2458. #define MRV_IMGEFF_SKET_COEF_21_SHIFT 0U
  2459. /*! Register: img_eff_mat_5: 3x3 matrix coefficients for sketch/sharpen effect (3) (0x00000018)*/
  2460. /*! Slice: sket_coef_33_en:*/
  2461. /*! 0: entry not used (coefficient is zero)*/
  2462. /* 1: entry used */
  2463. #define MRV_IMGEFF_SKET_COEF_33_EN
  2464. #define MRV_IMGEFF_SKET_COEF_33_EN_MASK 0x00000080U
  2465. #define MRV_IMGEFF_SKET_COEF_33_EN_SHIFT 7U
  2466. /*! Slice: sket_coef_33:*/
  2467. /*! third line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  2468. #define MRV_IMGEFF_SKET_COEF_33
  2469. #define MRV_IMGEFF_SKET_COEF_33_MASK 0x00000070U
  2470. #define MRV_IMGEFF_SKET_COEF_33_SHIFT 4U
  2471. /*! Slice: sket_coef_32_en:*/
  2472. /*! 0: entry not used (coefficient is zero)*/
  2473. /* 1: entry used */
  2474. #define MRV_IMGEFF_SKET_COEF_32_EN
  2475. #define MRV_IMGEFF_SKET_COEF_32_EN_MASK 0x00000008U
  2476. #define MRV_IMGEFF_SKET_COEF_32_EN_SHIFT 3U
  2477. /*! Slice: sket_coef_32:*/
  2478. /*! third line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  2479. #define MRV_IMGEFF_SKET_COEF_32
  2480. #define MRV_IMGEFF_SKET_COEF_32_MASK 0x00000007U
  2481. #define MRV_IMGEFF_SKET_COEF_32_SHIFT 0U
  2482. /*! Register: img_eff_tint: Chrominance increment values of a tint (used for sepia effect) (0x0000001c)*/
  2483. /*! Slice: incr_cr:*/
  2484. /*! Cr increment value of a tint. 7 bits for value, 1 sign bit.*/
  2485. /* Default tint is R=162 G=138 B=101, which is used for the sepia effect. See below for the calculation of the entries.*/
  2486. #define MRV_IMGEFF_INCR_CR
  2487. #define MRV_IMGEFF_INCR_CR_MASK 0x0000FF00U
  2488. #define MRV_IMGEFF_INCR_CR_SHIFT 8U
  2489. /*! Slice: incr_cb:*/
  2490. /*! Cb increment value of a tint. 7 bits for value, 1 sign bit.*/
  2491. /* Default tint is R=162 G=138 B=101, which is used for the sepia effect. See below for the calculation of the entries.*/
  2492. #define MRV_IMGEFF_INCR_CB
  2493. #define MRV_IMGEFF_INCR_CB_MASK 0x000000FFU
  2494. #define MRV_IMGEFF_INCR_CB_SHIFT 0U
  2495. /*! Register: img_eff_ctrl_shd: Shadow register for control register (0x00000020)*/
  2496. /*! Slice: effect_mode_shd:*/
  2497. /*! effect mode */
  2498. /* 000: black & white effect (grayscale)*/
  2499. /* 001: negative */
  2500. /* 010: sepia effect */
  2501. /* 011: color selection effect */
  2502. /* 100: emboss effect */
  2503. /* 101: sketch effect */
  2504. /* 110: sharpen effect */
  2505. /* 111: reserved */
  2506. #define MRV_IMGEFF_EFFECT_MODE_SHD
  2507. #define MRV_IMGEFF_EFFECT_MODE_SHD_MASK 0x0000000EU
  2508. #define MRV_IMGEFF_EFFECT_MODE_SHD_SHIFT 1U
  2509. /*! Register: img_eff_sharpen: Factor and threshold for sharpen effect (0x00000024)*/
  2510. /*! Slice: sharp_factor:*/
  2511. /*! 6Bit Factor for sharpening function. Value range is from 0x0 to 0x3F. High value means strong sharpening. The resulting factors are for example:*/
  2512. /* 0x00 = 0 (no sharpen effect like bypass)*/
  2513. /* 0x01 = 0.25 */
  2514. /* 0x02 = 0.5 */
  2515. /* 0x03 = 0.75 */
  2516. /* 0x04 = 1.0 */
  2517. /* 0x05 = 1.25 */
  2518. /* 0x06 = 1.5 */
  2519. /* 0x08 = 2.0 */
  2520. /* 0x0A = 2.5 */
  2521. /* 0x0C = 3.0 */
  2522. /* 0x10 = 4.0 */
  2523. /* 0x18 = 6.0 */
  2524. /* 0x20 = 8.0 */
  2525. /* 0x30 = 12.0 */
  2526. /* 0x3F = 15.75 */
  2527. #define MRV_IMGEFF_SHARP_FACTOR
  2528. #define MRV_IMGEFF_SHARP_FACTOR_MASK 0x00003F00U
  2529. #define MRV_IMGEFF_SHARP_FACTOR_SHIFT 8U
  2530. /*! Slice: coring_thr:*/
  2531. /*! Threshold for coring function. This value is used to avoid amplifying noise too much by suppressing sharpening for small gradients. Higher value means less sharpening for smooth edges. Threshold zero means no coring, so all gradients are treated the same. Threshold 255 means nearly no sharpening. An absolute value for the highpass signal is defined here. The highpass signal is truncated at the defined level.*/
  2532. #define MRV_IMGEFF_CORING_THR
  2533. #define MRV_IMGEFF_CORING_THR_MASK 0x000000FFU
  2534. #define MRV_IMGEFF_CORING_THR_SHIFT 0U
  2535. /*! Register: super_imp_ctrl: Global control register (0x00000000)*/
  2536. /*! Slice: transparency_mode:*/
  2537. /*! transparency mode */
  2538. /* 1: transparency mode disabled */
  2539. /* 0: transparency mode enabled */
  2540. #define MRV_SI_TRANSPARENCY_MODE
  2541. #define MRV_SI_TRANSPARENCY_MODE_MASK 0x00000004U
  2542. #define MRV_SI_TRANSPARENCY_MODE_SHIFT 2U
  2543. /*! Slice: ref_image:*/
  2544. /*! define the reference image */
  2545. /* 1: superimpose bitmap from main memory */
  2546. /* 0: image from the Image Effect module */
  2547. /* Note: the reference image defines the size of the output image */
  2548. #define MRV_SI_REF_IMAGE
  2549. #define MRV_SI_REF_IMAGE_MASK 0x00000002U
  2550. #define MRV_SI_REF_IMAGE_SHIFT 1U
  2551. /*! Slice: bypass_mode:*/
  2552. /*! Bypass mode */
  2553. /* 0: bypass mode */
  2554. /* 1: normal operation */
  2555. /* Note: in the bypass mode the data stream from Image Effect is transmitted to MUX module without overlaying */
  2556. #define MRV_SI_BYPASS_MODE
  2557. #define MRV_SI_BYPASS_MODE_MASK 0x00000001U
  2558. #define MRV_SI_BYPASS_MODE_SHIFT 0U
  2559. /*! Register: super_imp_offset_x: Offset x register (0x00000004)*/
  2560. /*! Slice: offset_x:*/
  2561. /*! Offset X */
  2562. /* Note: the bit 0 is don’t care (write 1 doesn’t have any effect, the read access always gives ‘0’)*/
  2563. /* Note: the offset_x is positive and refers to the reference image */
  2564. #define MRV_SI_OFFSET_X
  2565. #define MRV_SI_OFFSET_X_MASK 0x00003FFEU
  2566. #define MRV_SI_OFFSET_X_SHIFT 1U
  2567. /*! Register: super_imp_offset_y: Offset y register (0x00000008)*/
  2568. /*! Slice: offset_y:*/
  2569. /*! Offset Y */
  2570. /* Note: the offset_y is positive and refers to the reference image */
  2571. #define MRV_SI_OFFSET_Y
  2572. #define MRV_SI_OFFSET_Y_MASK 0x00003FFFU
  2573. #define MRV_SI_OFFSET_Y_SHIFT 0U
  2574. /*! Register: super_imp_color_y: Y component of transparent key color (0x0000000c)*/
  2575. /*! Slice: y_comp:*/
  2576. /*! Y component of transparent key color */
  2577. #define MRV_SI_Y_COMP
  2578. #define MRV_SI_Y_COMP_MASK 0x000000FFU
  2579. #define MRV_SI_Y_COMP_SHIFT 0U
  2580. /*! Register: super_imp_color_cb: Cb component of transparent key color (0x00000010)*/
  2581. /*! Slice: cb_comp:*/
  2582. /*! Cb component of transparent key color */
  2583. #define MRV_SI_CB_COMP
  2584. #define MRV_SI_CB_COMP_MASK 0x000000FFU
  2585. #define MRV_SI_CB_COMP_SHIFT 0U
  2586. /*! Register: super_imp_color_cr: Cr component of transparent key color (0x00000014)*/
  2587. /*! Slice: cr_comp:*/
  2588. /*! Cr component of transparent key color */
  2589. #define MRV_SI_CR_COMP
  2590. #define MRV_SI_CR_COMP_MASK 0x000000FFU
  2591. #define MRV_SI_CR_COMP_SHIFT 0U
  2592. /*! Register: isp_ctrl: global control register (0x00000000)*/
  2593. #ifdef ISP_RGBIR
  2594. /*! Slice ISP_IR_RAW_OUT:*/
  2595. /*! 0: RGBIR IR RAW OUT is disable */
  2596. /*! 1: RGBIR IR RAW OUT is enable */
  2597. #define ISP_IR_RAW_OUT
  2598. #define ISP_IR_RAW_OUT_MASK 0x000400000U
  2599. #define ISP_IR_RAW_OUT_SHIFT 22U
  2600. #endif
  2601. /*! Slice PP_WRITE_SEL:*/
  2602. /*! 0: select yuv output */
  2603. /*! 1: select raw output */
  2604. #define PP_WRITE_SEL
  2605. #define PP_WRITE_SEL_MASK 0x1 << 23
  2606. #define PP_WRITE_SEL_SHIFT 23U
  2607. #ifdef ISP_DPF_RAW
  2608. /*! Slice MRV_ISP_DPF_RAW_OUT:*/
  2609. /*! 0: DPF RAW OUT is disable */
  2610. /*! 1: DPF RAW OUT is enable */
  2611. #define MRV_ISP_DPF_RAW_OUT
  2612. #define MRV_ISP_DPF_RAW_OUT_MASK 0x00040000U
  2613. #define MRV_ISP_DPF_RAW_OUT_SHIFT 18U
  2614. #endif
  2615. /*! Slice: digi_gain_EN:*/
  2616. /*! 0: is disbaled */
  2617. /* 1: is enabled.*/
  2618. #define MRV_ISP_DIGITAL_GAIN_EN
  2619. #define MRV_ISP_DIGITAL_GAIN_EN_MASK 0x00080000U
  2620. #define MRV_ISP_DIGITAL_GAIN_EN_SHIFT 19U
  2621. /*! Slice: CNR_EN:*/
  2622. /*! 0: CNR is disbaled */
  2623. /* 1: CNR is enabled.*/
  2624. #define MRV_ISP_CNR_EN
  2625. #define MRV_ISP_CNR_EN_MASK 0x00020000U
  2626. #define MRV_ISP_CNR_EN_SHIFT 17U
  2627. /*! Slice: CTRL_RESERVED_1:*/
  2628. /*! reserved */
  2629. #define MRV_ISP_CTRL_RESERVED_1
  2630. #define MRV_ISP_CTRL_RESERVED_1_MASK 0x00010000U
  2631. #define MRV_ISP_CTRL_RESERVED_1_SHIFT 16U
  2632. /*! Slice: CTRL_RESERVED_2:*/
  2633. /*! reserved */
  2634. #define MRV_ISP_CTRL_RESERVED_2
  2635. #define MRV_ISP_CTRL_RESERVED_2_MASK 0x00008000U
  2636. #define MRV_ISP_CTRL_RESERVED_2_SHIFT 15U
  2637. /*! Slice: ISP_CSM_C_RANGE:*/
  2638. /*! Color Space Matrix chrominance clipping range for ISP output */
  2639. /* 0: CbCr range 64..960 (16..240) according to ITU-R BT.601 standard */
  2640. /* 1: full UV range 0..1023 ( 0..255)*/
  2641. /* Numbers in brackets are for 8 bit resolution.*/
  2642. /* This bit also configures the YCbCr sequence align block accordingly.*/
  2643. #define MRV_ISP_ISP_CSM_C_RANGE
  2644. #define MRV_ISP_ISP_CSM_C_RANGE_MASK 0x00004000U
  2645. #define MRV_ISP_ISP_CSM_C_RANGE_SHIFT 14U
  2646. /*! Slice: ISP_CSM_Y_RANGE:*/
  2647. /*! Color Space Matrix luminance clipping range for ISP output */
  2648. /* 0: Y range 64..940 (16..235) according to ITU-R BT.601 standard */
  2649. /* 1: full Y range 0..1023 ( 0..255)*/
  2650. /* Numbers in brackets are for 8 bit resolution.*/
  2651. /* This bit also configures the YCbCr sequence align block accordingly.*/
  2652. #define MRV_ISP_ISP_CSM_Y_RANGE
  2653. #define MRV_ISP_ISP_CSM_Y_RANGE_MASK 0x00002000U
  2654. #define MRV_ISP_ISP_CSM_Y_RANGE_SHIFT 13U
  2655. /*! Slice: ISP_FLASH_MODE:*/
  2656. /*! 0: sensor interface works independently from flash control unit */
  2657. /* 1: one frame is captured when signaled by flash control unit */
  2658. #define MRV_ISP_ISP_FLASH_MODE
  2659. #define MRV_ISP_ISP_FLASH_MODE_MASK 0x00001000U
  2660. #define MRV_ISP_ISP_FLASH_MODE_SHIFT 12U
  2661. /*! Slice: ISP_GAMMA_OUT_ENABLE:*/
  2662. /*! gamma ON/OFF */
  2663. #define MRV_ISP_ISP_GAMMA_OUT_ENABLE
  2664. #define MRV_ISP_ISP_GAMMA_OUT_ENABLE_MASK 0x00000800U
  2665. #define MRV_ISP_ISP_GAMMA_OUT_ENABLE_SHIFT 11U
  2666. /*! Slice: ISP_GEN_CFG_UPD:*/
  2667. /*! 1: generate frame synchronous configuration signal at the output of ISP for shadow registers of the following processing modules, write only */
  2668. #define MRV_ISP_ISP_GEN_CFG_UPD
  2669. #define MRV_ISP_ISP_GEN_CFG_UPD_MASK 0x00000400U
  2670. #define MRV_ISP_ISP_GEN_CFG_UPD_SHIFT 10U
  2671. /*! Slice: ISP_CFG_UPD:*/
  2672. /*! 1: immediately configure (update) shadow registers, write only */
  2673. #define MRV_ISP_ISP_CFG_UPD
  2674. #define MRV_ISP_ISP_CFG_UPD_MASK 0x00000200U
  2675. #define MRV_ISP_ISP_CFG_UPD_SHIFT 9U
  2676. /*! Slice: ISP_CFG_UPD_PERMANENT:*/
  2677. /*! 1: permanent configure (update) shadow registers on frame end.*/
  2678. #define MRV_ISP_ISP_CFG_UPD_PERMANENT
  2679. #define MRV_ISP_ISP_CFG_UPD_PERMANENT_MASK 0x00000100U
  2680. #define MRV_ISP_ISP_CFG_UPD_PERMANENT_SHIFT 8U
  2681. /*! Slice: ISP_AWB_ENABLE:*/
  2682. /*! auto white balance ON/OFF */
  2683. #define MRV_ISP_ISP_AWB_ENABLE
  2684. #define MRV_ISP_ISP_AWB_ENABLE_MASK 0x00000080U
  2685. #define MRV_ISP_ISP_AWB_ENABLE_SHIFT 7U
  2686. /*! Slice: ISP_GAMMA_IN_ENABLE:*/
  2687. /*! Sensor De-gamma ON/OFF */
  2688. #define MRV_ISP_ISP_GAMMA_IN_ENABLE
  2689. #define MRV_ISP_ISP_GAMMA_IN_ENABLE_MASK 0x00000040U
  2690. #define MRV_ISP_ISP_GAMMA_IN_ENABLE_SHIFT 6U
  2691. /*! Slice: ISP_INFORM_ENABLE:*/
  2692. /*! 1: input formatter enabled */
  2693. /* 0: input formatter disabled */
  2694. /* The ISP input formatter is enabled or disabled by this bit immediately, but always starts or stops acquisition frame synchronously.*/
  2695. #define MRV_ISP_ISP_INFORM_ENABLE
  2696. #define MRV_ISP_ISP_INFORM_ENABLE_MASK 0x00000010U
  2697. #define MRV_ISP_ISP_INFORM_ENABLE_SHIFT 4U
  2698. /*! Slice: ISP_MODE:*/
  2699. /*! 000 - RAW picture with BT.601 sync (ISP bypass)*/
  2700. /* 001 - ITU-R BT.656 (YUV with embedded sync)*/
  2701. /* 010 - ITU-R BT.601 (YUV input with H and Vsync signals)*/
  2702. /* 011 - Bayer RGB processing with H and Vsync signals */
  2703. /* 100 - data mode (ISP bypass, sync signals interpreted as data enable)*/
  2704. /* 101 - Bayer RGB processing with BT.656 synchronization */
  2705. /* 110 - RAW picture with ITU-R BT.656 synchronization (ISP bypass)*/
  2706. /* 111 - reserved */
  2707. /**/
  2708. /* Side effect:*/
  2709. /* If RAW, BT.601, BT.656, or data mode is selected, the clock of the ISP SRAMs (ISP line buffer, Lens Shading, Bad Pixel) is switched off. Only in Bayer RGB mode the clock to the SRAMs is enabled. This further reduces power consumption.*/
  2710. #define MRV_ISP_ISP_MODE
  2711. #define MRV_ISP_ISP_MODE_MASK 0x0000000EU
  2712. #define MRV_ISP_ISP_MODE_SHIFT 1U
  2713. /*! Slice: ISP_ENABLE:*/
  2714. /*! 1: ISP data output enabled */
  2715. /* 0: ISP data output disabled */
  2716. /* Controls output formatter frame synchronously, if isp_gen_cfg_upd is used to activate this bit. For immediate update isp_cfg_upd must be used.*/
  2717. #define MRV_ISP_ISP_ENABLE
  2718. #define MRV_ISP_ISP_ENABLE_MASK 0x00000001U
  2719. #define MRV_ISP_ISP_ENABLE_SHIFT 0U
  2720. /*! Register: isp_acq_prop: ISP acquisition properties (0x00000004)*/
  2721. #ifdef ISP_DVP_PINMAPPING
  2722. /*! Slice: MRV_ISP_DVP_INPUT_PIN_MAPPING */
  2723. /*! Bit Mapping for LSB to MSP for ISPNano.*/
  2724. /*! 3'b000: normal 12-bit external interface */
  2725. /*! 3'b001: mapping low 10 bit to high 10 bits, append 2 zeros as LSBs.*/
  2726. /*! 3'b010: mapping low 8 bit to high 8 bits, append 4 zeros as LSBs.*/
  2727. /*! 3'b011: mapping middle 8 bit to high 8 bits, append 4 zeros as LSBs.*/
  2728. /*! 3'b100..3'b111: rsvd */
  2729. #define MRV_ISP_DVP_INPUT_PIN_MAPPING
  2730. #define MRV_ISP_DVP_INPUT_PIN_MAPPING_MASK 0x000E0000U
  2731. #define MRV_ISP_DVP_INPUT_PIN_MAPPING_SHIFT 17U
  2732. #endif
  2733. /*! Slice: DMA_YUV_SELECTION */
  2734. /*! 0: use align or conversion data for isp_is input */
  2735. /*! 1: use dma yuv read data for isp_is input */
  2736. #define MRV_ISP_DMA_YUV_SELECTION
  2737. #define MRV_ISP_DMA_YUV_SELECTION_MASK 0x00010000U
  2738. #define MRV_ISP_DMA_YUV_SELECTION_SHIFT 16U
  2739. /*! Slice: LATENCY_FIFO_SELECTION:*/
  2740. /*! 0: use input formatter input for latency fifo.*/
  2741. /* 1: use dma rgb read input for latency fifo.*/
  2742. #define MRV_ISP_LATENCY_FIFO_SELECTION
  2743. #define MRV_ISP_LATENCY_FIFO_SELECTION_MASK 0x00008000U
  2744. #define MRV_ISP_LATENCY_FIFO_SELECTION_SHIFT 15U
  2745. /*! Slice: INPUT_SELECTION:*/
  2746. /*! 000- 12Bit external Interface */
  2747. /* 001- 10Bit Interface, append 2 zeroes as LSBs */
  2748. /* 010- 10Bit Interface, append 2 MSBs as LSBs */
  2749. /* 011- 8Bit Interface, append 4 zeroes as LSBs */
  2750. /* 100- 8Bit Interface, append 4 MSBs as LSBs */
  2751. /* 101...111 reserved */
  2752. #define MRV_ISP_INPUT_SELECTION
  2753. #define MRV_ISP_INPUT_SELECTION_MASK 0x00007000U
  2754. #define MRV_ISP_INPUT_SELECTION_SHIFT 12U
  2755. /*! Slice: FIELD_INV:*/
  2756. /*! 1: swap odd and even fields */
  2757. /* 0: do not swap fields */
  2758. #define MRV_ISP_FIELD_INV
  2759. #define MRV_ISP_FIELD_INV_MASK 0x00000800U
  2760. #define MRV_ISP_FIELD_INV_SHIFT 11U
  2761. /*! Slice: FIELD_SELECTION:*/
  2762. /*! 00- sample all fields (don�t care about fields)*/
  2763. /* 01- sample only even fields */
  2764. /* 10- sample only odd fields */
  2765. /* 11- reserved */
  2766. #define MRV_ISP_FIELD_SELECTION
  2767. #define MRV_ISP_FIELD_SELECTION_MASK 0x00000600U
  2768. #define MRV_ISP_FIELD_SELECTION_SHIFT 9U
  2769. /*! Slice: CCIR_SEQ:*/
  2770. /*! 00- YCbYCr */
  2771. /* 01- YCrYCb */
  2772. /* 10- CbYCrY */
  2773. /* 11- CrYCbY */
  2774. #define MRV_ISP_CCIR_SEQ
  2775. #define MRV_ISP_CCIR_SEQ_MASK 0x00000180U
  2776. #define MRV_ISP_CCIR_SEQ_SHIFT 7U
  2777. /*! Slice: CONV_422:*/
  2778. /*! 00- co-sited color subsampling Y0Cb0Cr0 – Y1 */
  2779. /* 01- interleaved color subsampling Y0Cb0 – Y1Cr1 (not recommended)*/
  2780. /* 10- non-cosited color subsampling Y0Cb(0+1)/2 – Y1Cr(0+1)/2 */
  2781. /* 11- reserved */
  2782. #define MRV_ISP_CONV_422
  2783. #define MRV_ISP_CONV_422_MASK 0x00000060U
  2784. #define MRV_ISP_CONV_422_SHIFT 5U
  2785. /*! Slice: BAYER_PAT:*/
  2786. /*! color components from sensor, starting with top left position in sampled frame (reprogram with ISP_ACQ_H_OFFS, ISP_ACQ_V_OFFS)*/
  2787. /* 00- first line: RGRG..., second line: GBGB..., etc.*/
  2788. /* 01- first line: GRGR..., second line: BGBG..., etc.*/
  2789. /* 10- first line: GBGB..., second line: RGRG..., etc.*/
  2790. /* 11- first line: BGBG..., second line: GRGR..., etc.*/
  2791. /* This configuration applies for the black level area after cropping by the input formatter.*/
  2792. #define MRV_ISP_BAYER_PAT
  2793. #define MRV_ISP_BAYER_PAT_MASK 0x00000018U
  2794. #define MRV_ISP_BAYER_PAT_SHIFT 3U
  2795. /*! Slice: VSYNC_POL:*/
  2796. /*! vertical sync polarity */
  2797. /* 0: high active */
  2798. /* 1: low active */
  2799. #define MRV_ISP_VSYNC_POL
  2800. #define MRV_ISP_VSYNC_POL_MASK 0x00000004U
  2801. #define MRV_ISP_VSYNC_POL_SHIFT 2U
  2802. /*! Slice: HSYNC_POL:*/
  2803. /*! horizontal sync polarity */
  2804. /* 0: high active */
  2805. /* 1: low active */
  2806. #define MRV_ISP_HSYNC_POL
  2807. #define MRV_ISP_HSYNC_POL_MASK 0x00000002U
  2808. #define MRV_ISP_HSYNC_POL_SHIFT 1U
  2809. /*! Slice: SAMPLE_EDGE:*/
  2810. /*! 0- negative edge sampling */
  2811. /* 1- positive edge sampling */
  2812. #define MRV_ISP_SAMPLE_EDGE
  2813. #define MRV_ISP_SAMPLE_EDGE_MASK 0x00000001U
  2814. #define MRV_ISP_SAMPLE_EDGE_SHIFT 0U
  2815. /*! Register: isp_acq_h_offs: horizontal input offset (0x00000008)*/
  2816. /*! Slice: ACQ_H_OFFS:*/
  2817. /*! horizontal sample offset in 8-bit samples (yuv: 4 samples=2pix)*/
  2818. #define MRV_ISP_ACQ_H_OFFS
  2819. #define MRV_ISP_ACQ_H_OFFS_MASK 0x00007FFFU
  2820. #define MRV_ISP_ACQ_H_OFFS_SHIFT 0U
  2821. /*! Register: isp_acq_v_offs: vertical input offset (0x0000000c)*/
  2822. /*! Slice: ACQ_V_OFFS:*/
  2823. /*! vertical sample offset in lines */
  2824. #define MRV_ISP_ACQ_V_OFFS
  2825. #define MRV_ISP_ACQ_V_OFFS_MASK 0x00003FFFU
  2826. #define MRV_ISP_ACQ_V_OFFS_SHIFT 0U
  2827. /*! Register: isp_acq_h_size: horizontal input size (0x00000010)*/
  2828. /*! Slice: ACQ_H_SIZE:*/
  2829. /*! horizontal sample size in 12-bit samples */
  2830. /* YUV input: 2 samples = 1 pixel, else 1 sample = 1 pixel; So in YUV mode ACQ_H_SIZE must be twice as large as horizontal image size */
  2831. /* horizontal image size must always be even exept in raw picture mode; if an odd size is programmed the value will be truncated to even size */
  2832. #define MRV_ISP_ACQ_H_SIZE
  2833. #define MRV_ISP_ACQ_H_SIZE_MASK 0x00007FFFU
  2834. #define MRV_ISP_ACQ_H_SIZE_SHIFT 0U
  2835. /*! Register: isp_acq_v_size: vertical input size (0x00000014)*/
  2836. /*! Slice: ACQ_V_SIZE:*/
  2837. /*! vertical sample size in lines */
  2838. #define MRV_ISP_ACQ_V_SIZE
  2839. #define MRV_ISP_ACQ_V_SIZE_MASK 0x00003FFFU
  2840. #define MRV_ISP_ACQ_V_SIZE_SHIFT 0U
  2841. /*! Register: isp_acq_nr_frames: Number of frames to be captured (0x00000018)*/
  2842. /*! Slice: ACQ_NR_FRAMES:*/
  2843. /*! number of input frames to be sampled ( 0 = continuous )*/
  2844. #define MRV_ISP_ACQ_NR_FRAMES
  2845. #define MRV_ISP_ACQ_NR_FRAMES_MASK 0x000003FFU
  2846. #define MRV_ISP_ACQ_NR_FRAMES_SHIFT 0U
  2847. /*! Register: isp_gamma_dx_lo: De-Gamma Curve definition lower x increments (sampling points) (0x0000001c)*/
  2848. /*! Slice: GAMMA_DX_8:*/
  2849. /*! gamma curve sample point definition x-axis (input)*/
  2850. #define MRV_ISP_GAMMA_DX_8
  2851. #define MRV_ISP_GAMMA_DX_8_MASK 0x70000000U
  2852. #define MRV_ISP_GAMMA_DX_8_SHIFT 28U
  2853. /*! Slice: GAMMA_DX_7:*/
  2854. /*! gamma curve sample point definition x-axis (input)*/
  2855. #define MRV_ISP_GAMMA_DX_7
  2856. #define MRV_ISP_GAMMA_DX_7_MASK 0x07000000U
  2857. #define MRV_ISP_GAMMA_DX_7_SHIFT 24U
  2858. /*! Slice: GAMMA_DX_6:*/
  2859. /*! gamma curve sample point definition x-axis (input)*/
  2860. #define MRV_ISP_GAMMA_DX_6
  2861. #define MRV_ISP_GAMMA_DX_6_MASK 0x00700000U
  2862. #define MRV_ISP_GAMMA_DX_6_SHIFT 20U
  2863. /*! Slice: GAMMA_DX_5:*/
  2864. /*! gamma curve sample point definition x-axis (input)*/
  2865. #define MRV_ISP_GAMMA_DX_5
  2866. #define MRV_ISP_GAMMA_DX_5_MASK 0x00070000U
  2867. #define MRV_ISP_GAMMA_DX_5_SHIFT 16U
  2868. /*! Slice: GAMMA_DX_4:*/
  2869. /*! gamma curve sample point definition x-axis (input)*/
  2870. #define MRV_ISP_GAMMA_DX_4
  2871. #define MRV_ISP_GAMMA_DX_4_MASK 0x00007000U
  2872. #define MRV_ISP_GAMMA_DX_4_SHIFT 12U
  2873. /*! Slice: GAMMA_DX_3:*/
  2874. /*! gamma curve sample point definition x-axis (input)*/
  2875. #define MRV_ISP_GAMMA_DX_3
  2876. #define MRV_ISP_GAMMA_DX_3_MASK 0x00000700U
  2877. #define MRV_ISP_GAMMA_DX_3_SHIFT 8U
  2878. /*! Slice: GAMMA_DX_2:*/
  2879. /*! gamma curve sample point definition x-axis (input)*/
  2880. #define MRV_ISP_GAMMA_DX_2
  2881. #define MRV_ISP_GAMMA_DX_2_MASK 0x00000070U
  2882. #define MRV_ISP_GAMMA_DX_2_SHIFT 4U
  2883. /*! Slice: GAMMA_DX_1:*/
  2884. /*! gamma curve sample point definition x-axis (input)*/
  2885. #define MRV_ISP_GAMMA_DX_1
  2886. #define MRV_ISP_GAMMA_DX_1_MASK 0x00000007U
  2887. #define MRV_ISP_GAMMA_DX_1_SHIFT 0U
  2888. /*! Register: isp_gamma_dx_hi: De-Gamma Curve definition higher x increments (sampling points) (0x00000020)*/
  2889. /*! Slice: GAMMA_DX_16:*/
  2890. /*! gamma curve sample point definition x-axis (input)*/
  2891. #define MRV_ISP_GAMMA_DX_16
  2892. #define MRV_ISP_GAMMA_DX_16_MASK 0x70000000U
  2893. #define MRV_ISP_GAMMA_DX_16_SHIFT 28U
  2894. /*! Slice: GAMMA_DX_15:*/
  2895. /*! gamma curve sample point definition x-axis (input)*/
  2896. #define MRV_ISP_GAMMA_DX_15
  2897. #define MRV_ISP_GAMMA_DX_15_MASK 0x07000000U
  2898. #define MRV_ISP_GAMMA_DX_15_SHIFT 24U
  2899. /*! Slice: GAMMA_DX_14:*/
  2900. /*! gamma curve sample point definition x-axis (input)*/
  2901. #define MRV_ISP_GAMMA_DX_14
  2902. #define MRV_ISP_GAMMA_DX_14_MASK 0x00700000U
  2903. #define MRV_ISP_GAMMA_DX_14_SHIFT 20U
  2904. /*! Slice: GAMMA_DX_13:*/
  2905. /*! gamma curve sample point definition x-axis (input)*/
  2906. #define MRV_ISP_GAMMA_DX_13
  2907. #define MRV_ISP_GAMMA_DX_13_MASK 0x00070000U
  2908. #define MRV_ISP_GAMMA_DX_13_SHIFT 16U
  2909. /*! Slice: GAMMA_DX_12:*/
  2910. /*! gamma curve sample point definition x-axis (input)*/
  2911. #define MRV_ISP_GAMMA_DX_12
  2912. #define MRV_ISP_GAMMA_DX_12_MASK 0x00007000U
  2913. #define MRV_ISP_GAMMA_DX_12_SHIFT 12U
  2914. /*! Slice: GAMMA_DX_11:*/
  2915. /*! gamma curve sample point definition x-axis (input)*/
  2916. #define MRV_ISP_GAMMA_DX_11
  2917. #define MRV_ISP_GAMMA_DX_11_MASK 0x00000700U
  2918. #define MRV_ISP_GAMMA_DX_11_SHIFT 8U
  2919. /*! Slice: GAMMA_DX_10:*/
  2920. /*! gamma curve sample point definition x-axis (input)*/
  2921. #define MRV_ISP_GAMMA_DX_10
  2922. #define MRV_ISP_GAMMA_DX_10_MASK 0x00000070U
  2923. #define MRV_ISP_GAMMA_DX_10_SHIFT 4U
  2924. /*! Slice: GAMMA_DX_9:*/
  2925. /*! gamma curve sample point definition x-axis (input)*/
  2926. #define MRV_ISP_GAMMA_DX_9
  2927. #define MRV_ISP_GAMMA_DX_9_MASK 0x00000007U
  2928. #define MRV_ISP_GAMMA_DX_9_SHIFT 0U
  2929. /*! Register array: isp_gamma_r_y: De-Gamma Curve definition y red (0x0048 + n*0x4 (n=0..16))*/
  2930. /*! Slice: GAMMA_R_Y:*/
  2931. /* gamma curve point definition y-axis (output) for red */
  2932. /* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that the difference between successive Y values is 12-bit signed !)*/
  2933. #define MRV_ISP_GAMMA_R_Y
  2934. #define MRV_ISP_GAMMA_R_Y_MASK 0x00000FFFU
  2935. #define MRV_ISP_GAMMA_R_Y_SHIFT 0U
  2936. /*! Register array: isp_gamma_g_y: De-Gamma Curve definition y green (0x0090 + n*0x4 (n=0..16))*/
  2937. /*! Slice: GAMMA_G_Y:*/
  2938. /* gamma curve point definition y-axis (output) for green */
  2939. /* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that the difference between successive Y values is 12-bit signed !)*/
  2940. #define MRV_ISP_GAMMA_G_Y
  2941. #define MRV_ISP_GAMMA_G_Y_MASK 0x00000FFFU
  2942. #define MRV_ISP_GAMMA_G_Y_SHIFT 0U
  2943. /*! Register array: isp_gamma_b_y: De-Gamma Curve definition y blue (0x00D8 + n*0x4 (n=0..16))*/
  2944. /*! Slice: GAMMA_B_Y:*/
  2945. /* gamma curve point definition y-axis (output) for blue */
  2946. /* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that the difference between successive Y values is 12-bit signed !)*/
  2947. #define MRV_ISP_GAMMA_B_Y
  2948. #define MRV_ISP_GAMMA_B_Y_MASK 0x00000FFFU
  2949. #define MRV_ISP_GAMMA_B_Y_SHIFT 0U
  2950. /*! Register: isp_awb_prop: Auto white balance properties (0x00000110)*/
  2951. /*! Slice: AWB_MEAS_MODE:*/
  2952. /*! 1: RGB based measurement mode */
  2953. /* 0: near white discrimination mode using YCbCr color space */
  2954. #define MRV_ISP_AWB_MEAS_MODE
  2955. #define MRV_ISP_AWB_MEAS_MODE_MASK 0x80000000U
  2956. #define MRV_ISP_AWB_MEAS_MODE_SHIFT 31U
  2957. /*! Slice: AWB_MAX_EN:*/
  2958. /*! 1: enable Y_MAX compare */
  2959. /* 0: disable Y_MAX compare */
  2960. /* Not valid in RGB measurement mode.*/
  2961. #define MRV_ISP_AWB_MAX_EN
  2962. #define MRV_ISP_AWB_MAX_EN_MASK 0x00000004U
  2963. #define MRV_ISP_AWB_MAX_EN_SHIFT 2U
  2964. /*! Slice: AWB_MODE:*/
  2965. /*! AWB_MODE(1:0):*/
  2966. /* 11: reserved */
  2967. /* 10: measurement of YCbCr means (AWB_MEAS_MODE = 0) or RGB means (AWB_MEAS_MODE = 1)*/
  2968. /* 01: reserved */
  2969. /* 00: no measurement */
  2970. #define MRV_ISP_AWB_MODE
  2971. #define MRV_ISP_AWB_MODE_MASK 0x00000003U
  2972. #define MRV_ISP_AWB_MODE_SHIFT 0U
  2973. /*! Register: isp_awb_h_offs: Auto white balance horizontal offset of measure window (0x00000114)*/
  2974. /*! Slice: AWB_H_OFFS:*/
  2975. /*! horizontal window offset in pixel */
  2976. #define MRV_ISP_AWB_H_OFFS
  2977. #define MRV_ISP_AWB_H_OFFS_MASK 0x00001FFFU
  2978. #define MRV_ISP_AWB_H_OFFS_SHIFT 0U
  2979. /*! Register: isp_awb_v_offs: Auto white balance vertical offset of measure window (0x00000118)*/
  2980. /*! Slice: AWB_V_OFFS:*/
  2981. /*! vertical window offset in lines */
  2982. #define MRV_ISP_AWB_V_OFFS
  2983. #define MRV_ISP_AWB_V_OFFS_MASK 0x00001FFFU
  2984. #define MRV_ISP_AWB_V_OFFS_SHIFT 0U
  2985. /*! Register: isp_awb_h_size: Auto white balance horizontal window size (0x0000011c)*/
  2986. /*! Slice: AWB_H_SIZE:*/
  2987. /*! horizontal measurement window size in pixel */
  2988. #define MRV_ISP_AWB_H_SIZE
  2989. #define MRV_ISP_AWB_H_SIZE_MASK 0x00003FFFU
  2990. #define MRV_ISP_AWB_H_SIZE_SHIFT 0U
  2991. /*! Register: isp_awb_v_size: Auto white balance vertical window size (0x00000120)*/
  2992. /*! Slice: AWB_V_SIZE:*/
  2993. /*! vertical measurement window size in lines */
  2994. #define MRV_ISP_AWB_V_SIZE
  2995. #define MRV_ISP_AWB_V_SIZE_MASK 0x00003FFFU
  2996. #define MRV_ISP_AWB_V_SIZE_SHIFT 0U
  2997. /*! Register: isp_awb_frames: Auto white balance mean value over multiple frames (0x00000124)*/
  2998. /*! Slice: AWB_FRAMES:*/
  2999. /*! number of frames-1 used for mean value calculation (value of 0 means 1 frame, value of 7 means 8 frames)*/
  3000. #define MRV_ISP_AWB_FRAMES
  3001. #define MRV_ISP_AWB_FRAMES_MASK 0x00000007U
  3002. #define MRV_ISP_AWB_FRAMES_SHIFT 0U
  3003. /*! Register: isp_awb_ref: Auto white balance reference Cb/Cr values (0x00000128)*/
  3004. /*! Slice: AWB_REF_CR__MAX_R:*/
  3005. /*! - reference Cr value for AWB regulation, target for AWB */
  3006. /* - maximum red value, if RGB measurement mode is selected */
  3007. #define MRV_ISP_AWB_REF_CR__MAX_R
  3008. #define MRV_ISP_AWB_REF_CR__MAX_R_MASK 0x0000FF00U
  3009. #define MRV_ISP_AWB_REF_CR__MAX_R_SHIFT 8U
  3010. /*! Slice: AWB_REF_CB__MAX_B:*/
  3011. /*! - reference Cb value for AWB regulation, target for AWB */
  3012. /* - maximum blue value, if RGB measurement mode is selected */
  3013. #define MRV_ISP_AWB_REF_CB__MAX_B
  3014. #define MRV_ISP_AWB_REF_CB__MAX_B_MASK 0x000000FFU
  3015. #define MRV_ISP_AWB_REF_CB__MAX_B_SHIFT 0U
  3016. /*! Register: isp_awb_thresh: Auto white balance threshold values (0x0000012c)*/
  3017. /*! Slice: AWB_MAX_Y:*/
  3018. /*! Luminance maximum value, only consider pixels with luminance smaller than threshold for the WB measurement (must be enabled by register AWB_MODE bit AWB_MAX_EN). Not valid for RGB measurement mode.*/
  3019. #define MRV_ISP_AWB_MAX_Y
  3020. #define MRV_ISP_AWB_MAX_Y_MASK 0xFF000000U
  3021. #define MRV_ISP_AWB_MAX_Y_SHIFT 24U
  3022. /*! Slice: AWB_MIN_Y__MAX_G:*/
  3023. /*! - Luminance minimum value, only consider pixels with luminance greater than threshold for the WB measurement */
  3024. /* - maximum green value, if RGB measurement mode is selected */
  3025. #define MRV_ISP_AWB_MIN_Y__MAX_G
  3026. #define MRV_ISP_AWB_MIN_Y__MAX_G_MASK 0x00FF0000U
  3027. #define MRV_ISP_AWB_MIN_Y__MAX_G_SHIFT 16U
  3028. /*! Slice: AWB_MAX_CSUM:*/
  3029. /*! Chrominance sum maximum value, only consider pixels with Cb+Cr smaller than threshold for WB measurements */
  3030. #define MRV_ISP_AWB_MAX_CSUM
  3031. #define MRV_ISP_AWB_MAX_CSUM_MASK 0x0000FF00U
  3032. #define MRV_ISP_AWB_MAX_CSUM_SHIFT 8U
  3033. /*! Slice: AWB_MIN_C:*/
  3034. /*! Chrominance minimum value, only consider pixels with Cb/Cr each greater than threshold value for WB measurements */
  3035. #define MRV_ISP_AWB_MIN_C
  3036. #define MRV_ISP_AWB_MIN_C_MASK 0x000000FFU
  3037. #define MRV_ISP_AWB_MIN_C_SHIFT 0U
  3038. #ifdef ISP_AWB_0410 //This is Gain value component 4 bit int part and 10 bit fractional part
  3039. /*! Register: isp_awb_gain_g: Auto white balance gain green (0x00000138)*/
  3040. /*! Slice: AWB_GAIN_GR:*/
  3041. /*! gain value for green component in red line 1000h = 1, unsigned integer value, range 0 to 16 with 10 bit fractional part */
  3042. #define MRV_ISP_AWB_GAIN_GR
  3043. #define MRV_ISP_AWB_GAIN_GR_MASK 0x3FFF0000U
  3044. #define MRV_ISP_AWB_GAIN_GR_SHIFT 16U
  3045. /*! Slice: AWB_GAIN_GB:*/
  3046. /*! gain value for green component in blue line 1000h = 1, unsigned integer value, range 0 to 16 with 10 bit fractional part */
  3047. #define MRV_ISP_AWB_GAIN_GB
  3048. #define MRV_ISP_AWB_GAIN_GB_MASK 0x00003FFFU
  3049. #define MRV_ISP_AWB_GAIN_GB_SHIFT 0U
  3050. /*! Register: isp_awb_gain_rb: Auto white balance gain red and blue (0x0000013c)*/
  3051. /*! Slice: AWB_GAIN_R:*/
  3052. /*! gain value for red component 1000h = 1, unsigned integer value, range 0 to 16 with 10 bit fractional part */
  3053. #define MRV_ISP_AWB_GAIN_R
  3054. #define MRV_ISP_AWB_GAIN_R_MASK 0x3FFF0000U
  3055. #define MRV_ISP_AWB_GAIN_R_SHIFT 16U
  3056. /*! Slice: AWB_GAIN_B:*/
  3057. /*! gain value for blue component 1000h = 1, unsigned integer value, range 0 to 16 with 10 bit fractional part */
  3058. #define MRV_ISP_AWB_GAIN_B
  3059. #define MRV_ISP_AWB_GAIN_B_MASK 0x00003FFFU
  3060. #define MRV_ISP_AWB_GAIN_B_SHIFT 0U
  3061. #else//This is Gain value component 2 bit int part and 8 bit fractional part
  3062. /*! Register: isp_awb_gain_g: Auto white balance gain green (0x00000138)*/
  3063. /*! Slice: AWB_GAIN_GR:*/
  3064. /*! gain value for green component in red line 100h = 1, unsigned integer value, range 0 to 4 with 8 bit fractional part */
  3065. #define MRV_ISP_AWB_GAIN_GR
  3066. #define MRV_ISP_AWB_GAIN_GR_MASK 0x03FF0000U
  3067. #define MRV_ISP_AWB_GAIN_GR_SHIFT 16U
  3068. /*! Slice: AWB_GAIN_GB:*/
  3069. /*! gain value for green component in blue line 100h = 1, unsigned integer value, range 0 to 4 with 8 bit fractional part */
  3070. #define MRV_ISP_AWB_GAIN_GB
  3071. #define MRV_ISP_AWB_GAIN_GB_MASK 0x000003FFU
  3072. #define MRV_ISP_AWB_GAIN_GB_SHIFT 0U
  3073. /*! Register: isp_awb_gain_rb: Auto white balance gain red and blue (0x0000013c)*/
  3074. /*! Slice: AWB_GAIN_R:*/
  3075. /*! gain value for red component 100h = 1, unsigned integer value, range 0 to 4 with 8 bit fractional part */
  3076. #define MRV_ISP_AWB_GAIN_R
  3077. #define MRV_ISP_AWB_GAIN_R_MASK 0x03FF0000U
  3078. #define MRV_ISP_AWB_GAIN_R_SHIFT 16U
  3079. /*! Slice: AWB_GAIN_B:*/
  3080. /*! gain value for blue component 100h = 1, unsigned integer value, range 0 to 4 with 8 bit fractional part */
  3081. #define MRV_ISP_AWB_GAIN_B
  3082. #define MRV_ISP_AWB_GAIN_B_MASK 0x000003FFU
  3083. #define MRV_ISP_AWB_GAIN_B_SHIFT 0U
  3084. #endif
  3085. /*! Register: isp_awb_white_cnt: Auto white balance white pixel count (0x00000140)*/
  3086. /*! Slice: AWB_WHITE_CNT:*/
  3087. /*! White pixel count, number of "white pixels" found during last measurement, i.e. pixels included in mean value calculation */
  3088. #define MRV_ISP_AWB_WHITE_CNT
  3089. #define MRV_ISP_AWB_WHITE_CNT_MASK 0x03FFFFFFU
  3090. #define MRV_ISP_AWB_WHITE_CNT_SHIFT 0U
  3091. /*! Register: isp_awb_mean: Auto white balance measured mean value (0x00000144)*/
  3092. /*! Slice: AWB_MEAN_Y__G:*/
  3093. /*! - mean value of Y within window and frames */
  3094. /* - mean value of green, if RGB measurement mode is selected */
  3095. #define MRV_ISP_AWB_MEAN_Y__G
  3096. #define MRV_ISP_AWB_MEAN_Y__G_MASK 0x00FF0000U
  3097. #define MRV_ISP_AWB_MEAN_Y__G_SHIFT 16U
  3098. /*! Slice: AWB_MEAN_CB__B:*/
  3099. /*! - mean value of Cb within window and frames */
  3100. /* - mean value of blue, if RGB measurement mode is selected */
  3101. #define MRV_ISP_AWB_MEAN_CB__B
  3102. #define MRV_ISP_AWB_MEAN_CB__B_MASK 0x0000FF00U
  3103. #define MRV_ISP_AWB_MEAN_CB__B_SHIFT 8U
  3104. /*! Slice: AWB_MEAN_CR__R:*/
  3105. /*! - mean value of Cr within window and frames */
  3106. /* - mean value of red, if RGB measurement mode is selected */
  3107. #define MRV_ISP_AWB_MEAN_CR__R
  3108. #define MRV_ISP_AWB_MEAN_CR__R_MASK 0x000000FFU
  3109. #define MRV_ISP_AWB_MEAN_CR__R_SHIFT 0U
  3110. /*! Register: isp_cc_coeff_0: Color conversion coefficient 0 (0x00000170)*/
  3111. /*! Slice: cc_coeff_0:*/
  3112. /*! coefficient 0 for color space conversion */
  3113. #define MRV_ISP_CC_COEFF_0
  3114. #define MRV_ISP_CC_COEFF_0_MASK 0x000001FFU
  3115. #define MRV_ISP_CC_COEFF_0_SHIFT 0U
  3116. /*! Register: isp_cc_coeff_1: Color conversion coefficient 1 (0x00000174)*/
  3117. /*! Slice: cc_coeff_1:*/
  3118. /*! coefficient 1 for color space conversion */
  3119. #define MRV_ISP_CC_COEFF_1
  3120. #define MRV_ISP_CC_COEFF_1_MASK 0x000001FFU
  3121. #define MRV_ISP_CC_COEFF_1_SHIFT 0U
  3122. /*! Register: isp_cc_coeff_2: Color conversion coefficient 2 (0x00000178)*/
  3123. /*! Slice: cc_coeff_2:*/
  3124. /*! coefficient 2 for color space conversion */
  3125. #define MRV_ISP_CC_COEFF_2
  3126. #define MRV_ISP_CC_COEFF_2_MASK 0x000001FFU
  3127. #define MRV_ISP_CC_COEFF_2_SHIFT 0U
  3128. /*! Register: isp_cc_coeff_3: Color conversion coefficient 3 (0x0000017c)*/
  3129. /*! Slice: cc_coeff_3:*/
  3130. /*! coefficient 3 for color space conversion */
  3131. #define MRV_ISP_CC_COEFF_3
  3132. #define MRV_ISP_CC_COEFF_3_MASK 0x000001FFU
  3133. #define MRV_ISP_CC_COEFF_3_SHIFT 0U
  3134. /*! Register: isp_cc_coeff_4: Color conversion coefficient 4 (0x00000180)*/
  3135. /*! Slice: cc_coeff_4:*/
  3136. /*! coefficient 4 for color space conversion */
  3137. #define MRV_ISP_CC_COEFF_4
  3138. #define MRV_ISP_CC_COEFF_4_MASK 0x000001FFU
  3139. #define MRV_ISP_CC_COEFF_4_SHIFT 0U
  3140. /*! Register: isp_cc_coeff_5: Color conversion coefficient 5 (0x00000184)*/
  3141. /*! Slice: cc_coeff_5:*/
  3142. /*! coefficient 5 for color space conversion */
  3143. #define MRV_ISP_CC_COEFF_5
  3144. #define MRV_ISP_CC_COEFF_5_MASK 0x000001FFU
  3145. #define MRV_ISP_CC_COEFF_5_SHIFT 0U
  3146. /*! Register: isp_cc_coeff_6: Color conversion coefficient 6 (0x00000188)*/
  3147. /*! Slice: cc_coeff_6:*/
  3148. /*! coefficient 6 for color space conversion */
  3149. #define MRV_ISP_CC_COEFF_6
  3150. #define MRV_ISP_CC_COEFF_6_MASK 0x000001FFU
  3151. #define MRV_ISP_CC_COEFF_6_SHIFT 0U
  3152. /*! Register: isp_cc_coeff_7: Color conversion coefficient 7 (0x0000018c)*/
  3153. /*! Slice: cc_coeff_7:*/
  3154. /*! coefficient 7 for color space conversion */
  3155. #define MRV_ISP_CC_COEFF_7
  3156. #define MRV_ISP_CC_COEFF_7_MASK 0x000001FFU
  3157. #define MRV_ISP_CC_COEFF_7_SHIFT 0U
  3158. /*! Register: isp_cc_coeff_8: Color conversion coefficient 8 (0x00000190)*/
  3159. /*! Slice: cc_coeff_8:*/
  3160. /*! coefficient 8 for color space conversion */
  3161. #define MRV_ISP_CC_COEFF_8
  3162. #define MRV_ISP_CC_COEFF_8_MASK 0x000001FFU
  3163. #define MRV_ISP_CC_COEFF_8_SHIFT 0U
  3164. /*! Register: isp_out_h_offs: Horizontal offset of output window (0x00000194)*/
  3165. /*! Slice: ISP_OUT_H_OFFS:*/
  3166. /*! vertical pic offset in lines */
  3167. #define MRV_ISP_ISP_OUT_H_OFFS
  3168. #define MRV_ISP_ISP_OUT_H_OFFS_MASK 0x00003FFFU
  3169. #define MRV_ISP_ISP_OUT_H_OFFS_SHIFT 0U
  3170. /*! Register: isp_out_v_offs: Vertical offset of output window (0x00000198)*/
  3171. /*! Slice: ISP_OUT_V_OFFS:*/
  3172. /*! vertical pic offset in lines */
  3173. #define MRV_ISP_ISP_OUT_V_OFFS
  3174. #define MRV_ISP_ISP_OUT_V_OFFS_MASK 0x00003FFFU
  3175. #define MRV_ISP_ISP_OUT_V_OFFS_SHIFT 0U
  3176. /*! Register: isp_out_h_size: Output horizontal picture size (0x0000019c)*/
  3177. /*! Slice: ISP_OUT_H_SIZE:*/
  3178. /*! horizontal picture size in pixel */
  3179. /* if ISP_MODE is set to */
  3180. /* 001-(ITU-R BT.656 YUV),*/
  3181. /* 010-( ITU-R BT.601 YUV),*/
  3182. /* 011-( ITU-R BT.601 Bayer RGB),*/
  3183. /* 101-( ITU-R BT.656 Bayer RGB)*/
  3184. /* only even numbers are accepted, because complete quadruples of YUYV(YCbYCr) are needed for the 422 output. (if an odd size is programmed the value will be truncated to even size)*/
  3185. #define MRV_ISP_ISP_OUT_H_SIZE
  3186. #define MRV_ISP_ISP_OUT_H_SIZE_MASK 0x00007FFFU
  3187. #define MRV_ISP_ISP_OUT_H_SIZE_SHIFT 0U
  3188. /*! Register: isp_out_v_size: Output vertical picture size (0x000001a0)*/
  3189. /*! Slice: ISP_OUT_V_SIZE:*/
  3190. /*! vertical pic size in lines */
  3191. #define MRV_ISP_ISP_OUT_V_SIZE
  3192. #define MRV_ISP_ISP_OUT_V_SIZE_MASK 0x00003FFFU
  3193. #define MRV_ISP_ISP_OUT_V_SIZE_SHIFT 0U
  3194. /*! Register: isp_demosaic: Demosaic parameters (0x000001a4)*/
  3195. /*! Slice: DEMOSAIC_BYPASS:*/
  3196. /*! 0: normal operation for RGB Bayer Pattern input */
  3197. /* 1: demosaicing bypass for Black&White input data */
  3198. #define MRV_ISP_DEMOSAIC_BYPASS
  3199. #define MRV_ISP_DEMOSAIC_BYPASS_MASK 0x00000400U
  3200. #define MRV_ISP_DEMOSAIC_BYPASS_SHIFT 10U
  3201. /*! Slice: DEMOSAIC_TH:*/
  3202. /*! Threshold for Bayer demosaicing texture detection. This value shifted left 4bit is compared with the difference of the vertical and horizontal 12Bit wide texture indicators, to decide if the vertical or horizontal texture flag must be set.*/
  3203. /* 0xFF: no texture detection */
  3204. /* 0x00: maximum edge sensitivity */
  3205. #define MRV_ISP_DEMOSAIC_TH
  3206. #define MRV_ISP_DEMOSAIC_TH_MASK 0x000000FFU
  3207. #define MRV_ISP_DEMOSAIC_TH_SHIFT 0U
  3208. /*! Register: isp_flags_shd: Flags (current status) of certain signals and Shadow regs for enable signals (0x000001a8)*/
  3209. /*! Slice: S_HSYNC:*/
  3210. /*! state of ISP input port s_hsync, for test purposes */
  3211. #define MRV_ISP_S_HSYNC
  3212. #define MRV_ISP_S_HSYNC_MASK 0x80000000U
  3213. #define MRV_ISP_S_HSYNC_SHIFT 31U
  3214. /*! Slice: S_VSYNC:*/
  3215. /*! state of ISP input port s_vsync, for test purposes */
  3216. #define MRV_ISP_S_VSYNC
  3217. #define MRV_ISP_S_VSYNC_MASK 0x40000000U
  3218. #define MRV_ISP_S_VSYNC_SHIFT 30U
  3219. /*! Slice: S_DATA:*/
  3220. /*! state of ISP input port s_data, for test purposes */
  3221. #define MRV_ISP_S_DATA
  3222. #define MRV_ISP_S_DATA_MASK 0x0FFF0000U
  3223. #define MRV_ISP_S_DATA_SHIFT 16U
  3224. /*! Slice: INFORM_FIELD:*/
  3225. /*! current field information (0=odd, 1=even)*/
  3226. #define MRV_ISP_INFORM_FIELD
  3227. #define MRV_ISP_INFORM_FIELD_MASK 0x00000004U
  3228. #define MRV_ISP_INFORM_FIELD_SHIFT 2U
  3229. /*! Slice: ISP_INFORM_ENABLE_SHD:*/
  3230. /*! Input formatter enable shadow register */
  3231. #define MRV_ISP_ISP_INFORM_ENABLE_SHD
  3232. #define MRV_ISP_ISP_INFORM_ENABLE_SHD_MASK 0x00000002U
  3233. #define MRV_ISP_ISP_INFORM_ENABLE_SHD_SHIFT 1U
  3234. /*! Slice: ISP_ENABLE_SHD:*/
  3235. /*! ISP enable shadow register */
  3236. /* shows, if ISP currently outputs data (1) or not (0)*/
  3237. #define MRV_ISP_ISP_ENABLE_SHD
  3238. #define MRV_ISP_ISP_ENABLE_SHD_MASK 0x00000001U
  3239. #define MRV_ISP_ISP_ENABLE_SHD_SHIFT 0U
  3240. /*! Register: isp_out_h_offs_shd: current horizontal offset of output window (shadow register) (0x000001ac)*/
  3241. /*! Slice: ISP_OUT_H_OFFS_SHD:*/
  3242. /*! current vertical pic offset in lines */
  3243. #define MRV_ISP_ISP_OUT_H_OFFS_SHD
  3244. #define MRV_ISP_ISP_OUT_H_OFFS_SHD_MASK 0x00003FFFU
  3245. #define MRV_ISP_ISP_OUT_H_OFFS_SHD_SHIFT 0U
  3246. /*! Register: isp_out_v_offs_shd: current vertical offset of output window (shadow register) (0x000001b0)*/
  3247. /*! Slice: ISP_OUT_V_OFFS_SHD:*/
  3248. /*! current vertical pic offset in lines */
  3249. #define MRV_ISP_ISP_OUT_V_OFFS_SHD
  3250. #define MRV_ISP_ISP_OUT_V_OFFS_SHD_MASK 0x00003FFFU
  3251. #define MRV_ISP_ISP_OUT_V_OFFS_SHD_SHIFT 0U
  3252. /*! Register: isp_out_h_size_shd: current output horizontal picture size (shadow register) (0x000001b4)*/
  3253. /*! Slice: ISP_OUT_H_SIZE_SHD:*/
  3254. /*! current horizontal pic size in pixel */
  3255. #define MRV_ISP_ISP_OUT_H_SIZE_SHD
  3256. #define MRV_ISP_ISP_OUT_H_SIZE_SHD_MASK 0x00007FFFU
  3257. #define MRV_ISP_ISP_OUT_H_SIZE_SHD_SHIFT 0U
  3258. /*! Register: isp_out_v_size_shd: current output vertical picture size (shadow register) (0x000001b8)*/
  3259. /*! Slice: ISP_OUT_V_SIZE_SHD:*/
  3260. /*! vertical pic size in lines */
  3261. #define MRV_ISP_ISP_OUT_V_SIZE_SHD
  3262. #define MRV_ISP_ISP_OUT_V_SIZE_SHD_MASK 0x00003FFFU
  3263. #define MRV_ISP_ISP_OUT_V_SIZE_SHD_SHIFT 0U
  3264. /*! Register: isp_imsc: Interrupt mask (0x000001bc)*/
  3265. /*! Slice: IMSC_VSM_END:*/
  3266. /*! enable interrupt (1) or mask out (0)*/
  3267. #define MRV_ISP_IMSC_VSM_END
  3268. #define MRV_ISP_IMSC_VSM_END_MASK 0x00080000U
  3269. #define MRV_ISP_IMSC_VSM_END_SHIFT 19U
  3270. /*! Slice: IMSC_EXP_END:*/
  3271. /*! enable interrupt (1) or mask out (0)*/
  3272. #define MRV_ISP_IMSC_EXP_END
  3273. #define MRV_ISP_IMSC_EXP_END_MASK 0x00040000U
  3274. #define MRV_ISP_IMSC_EXP_END_SHIFT 18U
  3275. /*! Slice: IMSC_FLASH_CAP:*/
  3276. /*! enable interrupt (1) or mask out (0)*/
  3277. #define MRV_ISP_IMSC_FLASH_CAP
  3278. #define MRV_ISP_IMSC_FLASH_CAP_MASK 0x00020000U
  3279. #define MRV_ISP_IMSC_FLASH_CAP_SHIFT 17U
  3280. /*! Slice: IMSC_RESERVED_1:*/
  3281. /*! enable interrupt (1) or mask out (0)*/
  3282. #define MRV_ISP_IMSC_RESERVED_1
  3283. #define MRV_ISP_IMSC_RESERVED_1_MASK 0x00010000U
  3284. #define MRV_ISP_IMSC_RESERVED_1_SHIFT 16U
  3285. /*! Slice: IMSC_HIST_MEASURE_RDY:*/
  3286. /*! enable interrupt (1) or mask out (0)*/
  3287. #define MRV_ISP_IMSC_HIST_MEASURE_RDY
  3288. #define MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK 0x00008000U
  3289. #define MRV_ISP_IMSC_HIST_MEASURE_RDY_SHIFT 15U
  3290. /*! Slice: IMSC_AFM_FIN:*/
  3291. /*! enable interrupt (1) or mask out (0)*/
  3292. #define MRV_ISP_IMSC_AFM_FIN
  3293. #define MRV_ISP_IMSC_AFM_FIN_MASK 0x00004000U
  3294. #define MRV_ISP_IMSC_AFM_FIN_SHIFT 14U
  3295. /*! Slice: IMSC_AFM_LUM_OF:*/
  3296. /*! enable interrupt (1) or mask out (0)*/
  3297. #define MRV_ISP_IMSC_AFM_LUM_OF
  3298. #define MRV_ISP_IMSC_AFM_LUM_OF_MASK 0x00002000U
  3299. #define MRV_ISP_IMSC_AFM_LUM_OF_SHIFT 13U
  3300. /*! Slice: IMSC_AFM_SUM_OF:*/
  3301. /*! enable interrupt (1) or mask out (0)*/
  3302. #define MRV_ISP_IMSC_AFM_SUM_OF
  3303. #define MRV_ISP_IMSC_AFM_SUM_OF_MASK 0x00001000U
  3304. #define MRV_ISP_IMSC_AFM_SUM_OF_SHIFT 12U
  3305. /*! Slice: IMSC_SHUTTER_OFF:*/
  3306. /*! enable interrupt (1) or mask out (0)*/
  3307. #define MRV_ISP_IMSC_SHUTTER_OFF
  3308. #define MRV_ISP_IMSC_SHUTTER_OFF_MASK 0x00000800U
  3309. #define MRV_ISP_IMSC_SHUTTER_OFF_SHIFT 11U
  3310. /*! Slice: IMSC_SHUTTER_ON:*/
  3311. /*! enable interrupt (1) or mask out (0)*/
  3312. #define MRV_ISP_IMSC_SHUTTER_ON
  3313. #define MRV_ISP_IMSC_SHUTTER_ON_MASK 0x00000400U
  3314. #define MRV_ISP_IMSC_SHUTTER_ON_SHIFT 10U
  3315. /*! Slice: IMSC_FLASH_OFF:*/
  3316. /*! enable interrupt (1) or mask out (0)*/
  3317. #define MRV_ISP_IMSC_FLASH_OFF
  3318. #define MRV_ISP_IMSC_FLASH_OFF_MASK 0x00000200U
  3319. #define MRV_ISP_IMSC_FLASH_OFF_SHIFT 9U
  3320. /*! Slice: IMSC_FLASH_ON:*/
  3321. /*! enable interrupt (1) or mask out (0)*/
  3322. #define MRV_ISP_IMSC_FLASH_ON
  3323. #define MRV_ISP_IMSC_FLASH_ON_MASK 0x00000100U
  3324. #define MRV_ISP_IMSC_FLASH_ON_SHIFT 8U
  3325. /*! Slice: IMSC_H_START:*/
  3326. /*! enable interrupt (1) or mask out (0)*/
  3327. #define MRV_ISP_IMSC_H_START
  3328. #define MRV_ISP_IMSC_H_START_MASK 0x00000080U
  3329. #define MRV_ISP_IMSC_H_START_SHIFT 7U
  3330. /*! Slice: IMSC_V_START:*/
  3331. /*! enable interrupt (1) or mask out (0)*/
  3332. #define MRV_ISP_IMSC_V_START
  3333. #define MRV_ISP_IMSC_V_START_MASK 0x00000040U
  3334. #define MRV_ISP_IMSC_V_START_SHIFT 6U
  3335. /*! Slice: IMSC_FRAME_IN:*/
  3336. /*! enable interrupt (1) or mask out (0)*/
  3337. #define MRV_ISP_IMSC_FRAME_IN
  3338. #define MRV_ISP_IMSC_FRAME_IN_MASK 0x00000020U
  3339. #define MRV_ISP_IMSC_FRAME_IN_SHIFT 5U
  3340. /*! Slice: IMSC_AWB_DONE:*/
  3341. /*! enable interrupt (1) or mask out (0)*/
  3342. #define MRV_ISP_IMSC_AWB_DONE
  3343. #define MRV_ISP_IMSC_AWB_DONE_MASK 0x00000010U
  3344. #define MRV_ISP_IMSC_AWB_DONE_SHIFT 4U
  3345. /*! Slice: IMSC_PIC_SIZE_ERR:*/
  3346. /*! enable interrupt (1) or mask out (0)*/
  3347. #define MRV_ISP_IMSC_PIC_SIZE_ERR
  3348. #define MRV_ISP_IMSC_PIC_SIZE_ERR_MASK 0x00000008U
  3349. #define MRV_ISP_IMSC_PIC_SIZE_ERR_SHIFT 3U
  3350. /*! Slice: IMSC_DATA_LOSS:*/
  3351. /*! enable interrupt (1) or mask out (0)*/
  3352. #define MRV_ISP_IMSC_DATA_LOSS
  3353. #define MRV_ISP_IMSC_DATA_LOSS_MASK 0x00000004U
  3354. #define MRV_ISP_IMSC_DATA_LOSS_SHIFT 2U
  3355. /*! Slice: IMSC_FRAME:*/
  3356. /*! enable interrupt (1) or mask out (0)*/
  3357. #define MRV_ISP_IMSC_FRAME
  3358. #define MRV_ISP_IMSC_FRAME_MASK 0x00000002U
  3359. #define MRV_ISP_IMSC_FRAME_SHIFT 1U
  3360. /*! Slice: IMSC_ISP_OFF:*/
  3361. /*! enable interrupt (1) or mask out (0)*/
  3362. #define MRV_ISP_IMSC_ISP_OFF
  3363. #define MRV_ISP_IMSC_ISP_OFF_MASK 0x00000001U
  3364. #define MRV_ISP_IMSC_ISP_OFF_SHIFT 0U
  3365. /*! Register: isp_ris: Raw interrupt status (0x000001c0)*/
  3366. /*! Slice: RIS_VSM_END:*/
  3367. /*! VSM measurement complete */
  3368. #define MRV_ISP_RIS_VSM_END
  3369. #define MRV_ISP_RIS_VSM_END_MASK 0x00080000U
  3370. #define MRV_ISP_RIS_VSM_END_SHIFT 19U
  3371. /*! Slice: RIS_EXP_END:*/
  3372. /*! Exposure measurement complete */
  3373. #define MRV_ISP_RIS_EXP_END
  3374. #define MRV_ISP_RIS_EXP_END_MASK 0x00040000U
  3375. #define MRV_ISP_RIS_EXP_END_SHIFT 18U
  3376. /*! Slice: RIS_FLASH_CAP:*/
  3377. /*! Signaling captured frame */
  3378. #define MRV_ISP_RIS_FLASH_CAP
  3379. #define MRV_ISP_RIS_FLASH_CAP_MASK 0x00020000U
  3380. #define MRV_ISP_RIS_FLASH_CAP_SHIFT 17U
  3381. /*! Slice: RIS_RESERVED_1:*/
  3382. /*! reserved */
  3383. #define MRV_ISP_RIS_RESERVED_1
  3384. #define MRV_ISP_RIS_RESERVED_1_MASK 0x00010000U
  3385. #define MRV_ISP_RIS_RESERVED_1_SHIFT 16U
  3386. /*! Slice: RIS_HIST_MEASURE_RDY:*/
  3387. /*! Histogram measurement ready. (old or new histogram measurement)*/
  3388. #define MRV_ISP_RIS_HIST_MEASURE_RDY
  3389. #define MRV_ISP_RIS_HIST_MEASURE_RDY_MASK 0x00008000U
  3390. #define MRV_ISP_RIS_HIST_MEASURE_RDY_SHIFT 15U
  3391. /*! Slice: RIS_AFM_FIN:*/
  3392. /*! AF measurement finished: this interrupt is set when the first complete frame is calculated after enabling the AF measurement */
  3393. #define MRV_ISP_RIS_AFM_FIN
  3394. #define MRV_ISP_RIS_AFM_FIN_MASK 0x00004000U
  3395. #define MRV_ISP_RIS_AFM_FIN_SHIFT 14U
  3396. /*! Slice: RIS_AFM_LUM_OF:*/
  3397. /*! Auto focus luminance overflow */
  3398. #define MRV_ISP_RIS_AFM_LUM_OF
  3399. #define MRV_ISP_RIS_AFM_LUM_OF_MASK 0x00002000U
  3400. #define MRV_ISP_RIS_AFM_LUM_OF_SHIFT 13U
  3401. /*! Slice: RIS_AFM_SUM_OF:*/
  3402. /*! Auto focus sum overflow */
  3403. #define MRV_ISP_RIS_AFM_SUM_OF
  3404. #define MRV_ISP_RIS_AFM_SUM_OF_MASK 0x00001000U
  3405. #define MRV_ISP_RIS_AFM_SUM_OF_SHIFT 12U
  3406. /*! Slice: RIS_SHUTTER_OFF:*/
  3407. /*! Mechanical shutter is switched off */
  3408. #define MRV_ISP_RIS_SHUTTER_OFF
  3409. #define MRV_ISP_RIS_SHUTTER_OFF_MASK 0x00000800U
  3410. #define MRV_ISP_RIS_SHUTTER_OFF_SHIFT 11U
  3411. /*! Slice: RIS_SHUTTER_ON:*/
  3412. /*! Mechanical shutter is switched on */
  3413. #define MRV_ISP_RIS_SHUTTER_ON
  3414. #define MRV_ISP_RIS_SHUTTER_ON_MASK 0x00000400U
  3415. #define MRV_ISP_RIS_SHUTTER_ON_SHIFT 10U
  3416. /*! Slice: RIS_FLASH_OFF:*/
  3417. /*! Flash light is switched off */
  3418. #define MRV_ISP_RIS_FLASH_OFF
  3419. #define MRV_ISP_RIS_FLASH_OFF_MASK 0x00000200U
  3420. #define MRV_ISP_RIS_FLASH_OFF_SHIFT 9U
  3421. /*! Slice: RIS_FLASH_ON:*/
  3422. /*! Flash light is switched on */
  3423. #define MRV_ISP_RIS_FLASH_ON
  3424. #define MRV_ISP_RIS_FLASH_ON_MASK 0x00000100U
  3425. #define MRV_ISP_RIS_FLASH_ON_SHIFT 8U
  3426. /*! Slice: RIS_H_START:*/
  3427. /*! Start edge of h_sync */
  3428. #define MRV_ISP_RIS_H_START
  3429. #define MRV_ISP_RIS_H_START_MASK 0x00000080U
  3430. #define MRV_ISP_RIS_H_START_SHIFT 7U
  3431. /*! Slice: RIS_V_START:*/
  3432. /*! Start edge of v_sync */
  3433. #define MRV_ISP_RIS_V_START
  3434. #define MRV_ISP_RIS_V_START_MASK 0x00000040U
  3435. #define MRV_ISP_RIS_V_START_SHIFT 6U
  3436. /*! Slice: RIS_FRAME_IN:*/
  3437. /*! sampled input frame is complete */
  3438. #define MRV_ISP_RIS_FRAME_IN
  3439. #define MRV_ISP_RIS_FRAME_IN_MASK 0x00000020U
  3440. #define MRV_ISP_RIS_FRAME_IN_SHIFT 5U
  3441. /*! Slice: RIS_AWB_DONE:*/
  3442. /*! White balancing measurement cycle is complete, results can be read out */
  3443. #define MRV_ISP_RIS_AWB_DONE
  3444. #define MRV_ISP_RIS_AWB_DONE_MASK 0x00000010U
  3445. #define MRV_ISP_RIS_AWB_DONE_SHIFT 4U
  3446. /*! Slice: RIS_PIC_SIZE_ERR:*/
  3447. /*! pic size violation occurred, programming seems wrong */
  3448. #define MRV_ISP_RIS_PIC_SIZE_ERR
  3449. #define MRV_ISP_RIS_PIC_SIZE_ERR_MASK 0x00000008U
  3450. #define MRV_ISP_RIS_PIC_SIZE_ERR_SHIFT 3U
  3451. /*! Slice: RIS_DATA_LOSS:*/
  3452. /*! loss of data occurred within a line, processing failure */
  3453. #define MRV_ISP_RIS_DATA_LOSS
  3454. #define MRV_ISP_RIS_DATA_LOSS_MASK 0x00000004U
  3455. #define MRV_ISP_RIS_DATA_LOSS_SHIFT 2U
  3456. /*! Slice: RIS_FRAME:*/
  3457. /*! frame was completely put out */
  3458. #define MRV_ISP_RIS_FRAME
  3459. #define MRV_ISP_RIS_FRAME_MASK 0x00000002U
  3460. #define MRV_ISP_RIS_FRAME_SHIFT 1U
  3461. /*! Slice: RIS_ISP_OFF:*/
  3462. /*! isp output was disabled (vsynced) due to f_cnt reached or manual */
  3463. #define MRV_ISP_RIS_ISP_OFF
  3464. #define MRV_ISP_RIS_ISP_OFF_MASK 0x00000001U
  3465. #define MRV_ISP_RIS_ISP_OFF_SHIFT 0U
  3466. /*! Register: isp_mis: Masked interrupt status (0x000001c4)*/
  3467. /*! Slice: MIS_VSM_END:*/
  3468. /*! VSM measurement complete */
  3469. #define MRV_ISP_MIS_VSM_END
  3470. #define MRV_ISP_MIS_VSM_END_MASK 0x00080000U
  3471. #define MRV_ISP_MIS_VSM_END_SHIFT 19U
  3472. /*! Slice: MIS_EXP_END:*/
  3473. /*! Exposure measurement complete */
  3474. #define MRV_ISP_MIS_EXP_END
  3475. #define MRV_ISP_MIS_EXP_END_MASK 0x00040000U
  3476. #define MRV_ISP_MIS_EXP_END_SHIFT 18U
  3477. /*! Slice: MIS_FLASH_CAP:*/
  3478. /*! Captured is frame is detected */
  3479. #define MRV_ISP_MIS_FLASH_CAP
  3480. #define MRV_ISP_MIS_FLASH_CAP_MASK 0x00020000U
  3481. #define MRV_ISP_MIS_FLASH_CAP_SHIFT 17U
  3482. /*! Slice: MIS_RESERVED_1:*/
  3483. /*! reserved */
  3484. #define MRV_ISP_MIS_RESERVED_1
  3485. #define MRV_ISP_MIS_RESERVED_1_MASK 0x00010000U
  3486. #define MRV_ISP_MIS_RESERVED_1_SHIFT 16U
  3487. /*! Slice: MIS_HIST_MEASURE_RDY:*/
  3488. /*! Histogram measurement ready. (old or new histogram measurement)*/
  3489. #define MRV_ISP_MIS_HIST_MEASURE_RDY
  3490. #define MRV_ISP_MIS_HIST_MEASURE_RDY_MASK 0x00008000U
  3491. #define MRV_ISP_MIS_HIST_MEASURE_RDY_SHIFT 15U
  3492. /*! Slice: MIS_AFM_FIN:*/
  3493. /*! AF measurement finished: this interrupt is set when the first complete frame is calculated after enabling the AF measurement */
  3494. #define MRV_ISP_MIS_AFM_FIN
  3495. #define MRV_ISP_MIS_AFM_FIN_MASK 0x00004000U
  3496. #define MRV_ISP_MIS_AFM_FIN_SHIFT 14U
  3497. /*! Slice: MIS_AFM_LUM_OF:*/
  3498. /*! Luminance overflow */
  3499. #define MRV_ISP_MIS_AFM_LUM_OF
  3500. #define MRV_ISP_MIS_AFM_LUM_OF_MASK 0x00002000U
  3501. #define MRV_ISP_MIS_AFM_LUM_OF_SHIFT 13U
  3502. /*! Slice: MIS_AFM_SUM_OF:*/
  3503. /*! Sum overflow */
  3504. #define MRV_ISP_MIS_AFM_SUM_OF
  3505. #define MRV_ISP_MIS_AFM_SUM_OF_MASK 0x00001000U
  3506. #define MRV_ISP_MIS_AFM_SUM_OF_SHIFT 12U
  3507. /*! Slice: MIS_SHUTTER_OFF:*/
  3508. /*! Mechanical shutter is switched off */
  3509. #define MRV_ISP_MIS_SHUTTER_OFF
  3510. #define MRV_ISP_MIS_SHUTTER_OFF_MASK 0x00000800U
  3511. #define MRV_ISP_MIS_SHUTTER_OFF_SHIFT 11U
  3512. /*! Slice: MIS_SHUTTER_ON:*/
  3513. /*! Mechanical shutter is switched on */
  3514. #define MRV_ISP_MIS_SHUTTER_ON
  3515. #define MRV_ISP_MIS_SHUTTER_ON_MASK 0x00000400U
  3516. #define MRV_ISP_MIS_SHUTTER_ON_SHIFT 10U
  3517. /*! Slice: MIS_FLASH_OFF:*/
  3518. /*! Flash light is switched off */
  3519. #define MRV_ISP_MIS_FLASH_OFF
  3520. #define MRV_ISP_MIS_FLASH_OFF_MASK 0x00000200U
  3521. #define MRV_ISP_MIS_FLASH_OFF_SHIFT 9U
  3522. /*! Slice: MIS_FLASH_ON:*/
  3523. /*! Flash light is switched on */
  3524. #define MRV_ISP_MIS_FLASH_ON
  3525. #define MRV_ISP_MIS_FLASH_ON_MASK 0x00000100U
  3526. #define MRV_ISP_MIS_FLASH_ON_SHIFT 8U
  3527. /*! Slice: MIS_H_START:*/
  3528. /*! Start edge of h_sync */
  3529. #define MRV_ISP_MIS_H_START
  3530. #define MRV_ISP_MIS_H_START_MASK 0x00000080U
  3531. #define MRV_ISP_MIS_H_START_SHIFT 7U
  3532. /*! Slice: MIS_V_START:*/
  3533. /*! Start edge of v_sync */
  3534. #define MRV_ISP_MIS_V_START
  3535. #define MRV_ISP_MIS_V_START_MASK 0x00000040U
  3536. #define MRV_ISP_MIS_V_START_SHIFT 6U
  3537. /*! Slice: MIS_FRAME_IN:*/
  3538. /*! sampled input frame is complete */
  3539. #define MRV_ISP_MIS_FRAME_IN
  3540. #define MRV_ISP_MIS_FRAME_IN_MASK 0x00000020U
  3541. #define MRV_ISP_MIS_FRAME_IN_SHIFT 5U
  3542. /*! Slice: MIS_AWB_DONE:*/
  3543. /*! White balancing measurement cycle is complete, results can be read out */
  3544. #define MRV_ISP_MIS_AWB_DONE
  3545. #define MRV_ISP_MIS_AWB_DONE_MASK 0x00000010U
  3546. #define MRV_ISP_MIS_AWB_DONE_SHIFT 4U
  3547. /*! Slice: MIS_PIC_SIZE_ERR:*/
  3548. /*! pic size violation occurred, programming seems wrong */
  3549. #define MRV_ISP_MIS_PIC_SIZE_ERR
  3550. #define MRV_ISP_MIS_PIC_SIZE_ERR_MASK 0x00000008U
  3551. #define MRV_ISP_MIS_PIC_SIZE_ERR_SHIFT 3U
  3552. /*! Slice: MIS_DATA_LOSS:*/
  3553. /*! loss of data occurred within a line, processing failure */
  3554. #define MRV_ISP_MIS_DATA_LOSS
  3555. #define MRV_ISP_MIS_DATA_LOSS_MASK 0x00000004U
  3556. #define MRV_ISP_MIS_DATA_LOSS_SHIFT 2U
  3557. /*! Slice: MIS_FRAME:*/
  3558. /*! frame was completely put out */
  3559. #define MRV_ISP_MIS_FRAME
  3560. #define MRV_ISP_MIS_FRAME_MASK 0x00000002U
  3561. #define MRV_ISP_MIS_FRAME_SHIFT 1U
  3562. /*! Slice: MIS_ISP_OFF:*/
  3563. /*! isp was turned off (vsynced) due to f_cnt reached or manual */
  3564. #define MRV_ISP_MIS_ISP_OFF
  3565. #define MRV_ISP_MIS_ISP_OFF_MASK 0x00000001U
  3566. #define MRV_ISP_MIS_ISP_OFF_SHIFT 0U
  3567. /*! Register: isp_icr: Interrupt clear register (0x000001c8)*/
  3568. /*! Slice: ICR_VSM_END:*/
  3569. /*! clear interrupt */
  3570. #define MRV_ISP_ICR_VSM_END
  3571. #define MRV_ISP_ICR_VSM_END_MASK 0x00080000U
  3572. #define MRV_ISP_ICR_VSM_END_SHIFT 19U
  3573. /*! Slice: ICR_EXP_END:*/
  3574. /*! clear interrupt */
  3575. #define MRV_ISP_ICR_EXP_END
  3576. #define MRV_ISP_ICR_EXP_END_MASK 0x00040000U
  3577. #define MRV_ISP_ICR_EXP_END_SHIFT 18U
  3578. /*! Slice: ICR_FLASH_CAP:*/
  3579. /*! clear interrupt */
  3580. #define MRV_ISP_ICR_FLASH_CAP
  3581. #define MRV_ISP_ICR_FLASH_CAP_MASK 0x00020000U
  3582. #define MRV_ISP_ICR_FLASH_CAP_SHIFT 17U
  3583. /*! Slice: ICR_RESERVED_1:*/
  3584. /*! clear interrupt */
  3585. #define MRV_ISP_ICR_RESERVED_1
  3586. #define MRV_ISP_ICR_RESERVED_1_MASK 0x00010000U
  3587. #define MRV_ISP_ICR_RESERVED_1_SHIFT 16U
  3588. /*! Slice: ICR_HIST_MEASURE_RDY:*/
  3589. /*! clear interrupt */
  3590. #define MRV_ISP_ICR_HIST_MEASURE_RDY
  3591. #define MRV_ISP_ICR_HIST_MEASURE_RDY_MASK 0x00008000U
  3592. #define MRV_ISP_ICR_HIST_MEASURE_RDY_SHIFT 15U
  3593. /*! Slice: ICR_AFM_FIN:*/
  3594. /*! clear interrupt */
  3595. #define MRV_ISP_ICR_AFM_FIN
  3596. #define MRV_ISP_ICR_AFM_FIN_MASK 0x00004000U
  3597. #define MRV_ISP_ICR_AFM_FIN_SHIFT 14U
  3598. /*! Slice: ICR_AFM_LUM_OF:*/
  3599. /*! clear interrupt */
  3600. #define MRV_ISP_ICR_AFM_LUM_OF
  3601. #define MRV_ISP_ICR_AFM_LUM_OF_MASK 0x00002000U
  3602. #define MRV_ISP_ICR_AFM_LUM_OF_SHIFT 13U
  3603. /*! Slice: ICR_AFM_SUM_OF:*/
  3604. /*! clear interrupt */
  3605. #define MRV_ISP_ICR_AFM_SUM_OF
  3606. #define MRV_ISP_ICR_AFM_SUM_OF_MASK 0x00001000U
  3607. #define MRV_ISP_ICR_AFM_SUM_OF_SHIFT 12U
  3608. /*! Slice: ICR_SHUTTER_OFF:*/
  3609. /*! clear interrupt */
  3610. #define MRV_ISP_ICR_SHUTTER_OFF
  3611. #define MRV_ISP_ICR_SHUTTER_OFF_MASK 0x00000800U
  3612. #define MRV_ISP_ICR_SHUTTER_OFF_SHIFT 11U
  3613. /*! Slice: ICR_SHUTTER_ON:*/
  3614. /*! clear interrupt */
  3615. #define MRV_ISP_ICR_SHUTTER_ON
  3616. #define MRV_ISP_ICR_SHUTTER_ON_MASK 0x00000400U
  3617. #define MRV_ISP_ICR_SHUTTER_ON_SHIFT 10U
  3618. /*! Slice: ICR_FLASH_OFF:*/
  3619. /*! clear interrupt */
  3620. #define MRV_ISP_ICR_FLASH_OFF
  3621. #define MRV_ISP_ICR_FLASH_OFF_MASK 0x00000200U
  3622. #define MRV_ISP_ICR_FLASH_OFF_SHIFT 9U
  3623. /*! Slice: ICR_FLASH_ON:*/
  3624. /*! clear interrupt */
  3625. #define MRV_ISP_ICR_FLASH_ON
  3626. #define MRV_ISP_ICR_FLASH_ON_MASK 0x00000100U
  3627. #define MRV_ISP_ICR_FLASH_ON_SHIFT 8U
  3628. /*! Slice: ICR_H_START:*/
  3629. /*! clear interrupt */
  3630. #define MRV_ISP_ICR_H_START
  3631. #define MRV_ISP_ICR_H_START_MASK 0x00000080U
  3632. #define MRV_ISP_ICR_H_START_SHIFT 7U
  3633. /*! Slice: ICR_V_START:*/
  3634. /*! clear interrupt */
  3635. #define MRV_ISP_ICR_V_START
  3636. #define MRV_ISP_ICR_V_START_MASK 0x00000040U
  3637. #define MRV_ISP_ICR_V_START_SHIFT 6U
  3638. /*! Slice: ICR_FRAME_IN:*/
  3639. /*! clear interrupt */
  3640. #define MRV_ISP_ICR_FRAME_IN
  3641. #define MRV_ISP_ICR_FRAME_IN_MASK 0x00000020U
  3642. #define MRV_ISP_ICR_FRAME_IN_SHIFT 5U
  3643. /*! Slice: ICR_AWB_DONE:*/
  3644. /*! clear interrupt */
  3645. #define MRV_ISP_ICR_AWB_DONE
  3646. #define MRV_ISP_ICR_AWB_DONE_MASK 0x00000010U
  3647. #define MRV_ISP_ICR_AWB_DONE_SHIFT 4U
  3648. /*! Slice: ICR_PIC_SIZE_ERR:*/
  3649. /*! clear interrupt */
  3650. #define MRV_ISP_ICR_PIC_SIZE_ERR
  3651. #define MRV_ISP_ICR_PIC_SIZE_ERR_MASK 0x00000008U
  3652. #define MRV_ISP_ICR_PIC_SIZE_ERR_SHIFT 3U
  3653. /*! Slice: ICR_DATA_LOSS:*/
  3654. /*! clear interrupt */
  3655. #define MRV_ISP_ICR_DATA_LOSS
  3656. #define MRV_ISP_ICR_DATA_LOSS_MASK 0x00000004U
  3657. #define MRV_ISP_ICR_DATA_LOSS_SHIFT 2U
  3658. /*! Slice: ICR_FRAME:*/
  3659. /*! clear interrupt */
  3660. #define MRV_ISP_ICR_FRAME
  3661. #define MRV_ISP_ICR_FRAME_MASK 0x00000002U
  3662. #define MRV_ISP_ICR_FRAME_SHIFT 1U
  3663. /*! Slice: ICR_ISP_OFF:*/
  3664. /*! clear interrupt */
  3665. #define MRV_ISP_ICR_ISP_OFF
  3666. #define MRV_ISP_ICR_ISP_OFF_MASK 0x00000001U
  3667. #define MRV_ISP_ICR_ISP_OFF_SHIFT 0U
  3668. /*! Register: isp_isr: Interrupt set register (0x000001cc)*/
  3669. /*! Slice: ISR_VSM_END:*/
  3670. /*! set interrupt */
  3671. #define MRV_ISP_ISR_VSM_END
  3672. #define MRV_ISP_ISR_VSM_END_MASK 0x00080000U
  3673. #define MRV_ISP_ISR_VSM_END_SHIFT 19U
  3674. /*! Slice: ISR_EXP_END:*/
  3675. /*! set interrupt */
  3676. #define MRV_ISP_ISR_EXP_END
  3677. #define MRV_ISP_ISR_EXP_END_MASK 0x00040000U
  3678. #define MRV_ISP_ISR_EXP_END_SHIFT 18U
  3679. /*! Slice: ISR_FLASH_CAP:*/
  3680. /*! set interrupt */
  3681. #define MRV_ISP_ISR_FLASH_CAP
  3682. #define MRV_ISP_ISR_FLASH_CAP_MASK 0x00020000U
  3683. #define MRV_ISP_ISR_FLASH_CAP_SHIFT 17U
  3684. /*! Slice: ISR_RESERVED_1:*/
  3685. /*! set interrupt */
  3686. #define MRV_ISP_ISR_RESERVED_1
  3687. #define MRV_ISP_ISR_RESERVED_1_MASK 0x00010000U
  3688. #define MRV_ISP_ISR_RESERVED_1_SHIFT 16U
  3689. /*! Slice: ISR_HIST_MEASURE_RDY:*/
  3690. /*! set interrupt */
  3691. #define MRV_ISP_ISR_HIST_MEASURE_RDY
  3692. #define MRV_ISP_ISR_HIST_MEASURE_RDY_MASK 0x00008000U
  3693. #define MRV_ISP_ISR_HIST_MEASURE_RDY_SHIFT 15U
  3694. /*! Slice: ISR_AFM_FIN:*/
  3695. /*! set interrupt */
  3696. #define MRV_ISP_ISR_AFM_FIN
  3697. #define MRV_ISP_ISR_AFM_FIN_MASK 0x00004000U
  3698. #define MRV_ISP_ISR_AFM_FIN_SHIFT 14U
  3699. /*! Slice: ISR_AFM_LUM_OF:*/
  3700. /*! set interrupt */
  3701. #define MRV_ISP_ISR_AFM_LUM_OF
  3702. #define MRV_ISP_ISR_AFM_LUM_OF_MASK 0x00002000U
  3703. #define MRV_ISP_ISR_AFM_LUM_OF_SHIFT 13U
  3704. /*! Slice: ISR_AFM_SUM_OF:*/
  3705. /*! set interrupt */
  3706. #define MRV_ISP_ISR_AFM_SUM_OF
  3707. #define MRV_ISP_ISR_AFM_SUM_OF_MASK 0x00001000U
  3708. #define MRV_ISP_ISR_AFM_SUM_OF_SHIFT 12U
  3709. /*! Slice: ISR_SHUTTER_OFF:*/
  3710. /*! set interrupt */
  3711. #define MRV_ISP_ISR_SHUTTER_OFF
  3712. #define MRV_ISP_ISR_SHUTTER_OFF_MASK 0x00000800U
  3713. #define MRV_ISP_ISR_SHUTTER_OFF_SHIFT 11U
  3714. /*! Slice: ISR_SHUTTER_ON:*/
  3715. /*! set interrupt */
  3716. #define MRV_ISP_ISR_SHUTTER_ON
  3717. #define MRV_ISP_ISR_SHUTTER_ON_MASK 0x00000400U
  3718. #define MRV_ISP_ISR_SHUTTER_ON_SHIFT 10U
  3719. /*! Slice: ISR_FLASH_OFF:*/
  3720. /*! set interrupt */
  3721. #define MRV_ISP_ISR_FLASH_OFF
  3722. #define MRV_ISP_ISR_FLASH_OFF_MASK 0x00000200U
  3723. #define MRV_ISP_ISR_FLASH_OFF_SHIFT 9U
  3724. /*! Slice: ISR_FLASH_ON:*/
  3725. /*! set interrupt */
  3726. #define MRV_ISP_ISR_FLASH_ON
  3727. #define MRV_ISP_ISR_FLASH_ON_MASK 0x00000100U
  3728. #define MRV_ISP_ISR_FLASH_ON_SHIFT 8U
  3729. /*! Slice: ISR_H_START:*/
  3730. /*! set interrupt */
  3731. #define MRV_ISP_ISR_H_START
  3732. #define MRV_ISP_ISR_H_START_MASK 0x00000080U
  3733. #define MRV_ISP_ISR_H_START_SHIFT 7U
  3734. /*! Slice: ISR_V_START:*/
  3735. /*! set interrupt */
  3736. #define MRV_ISP_ISR_V_START
  3737. #define MRV_ISP_ISR_V_START_MASK 0x00000040U
  3738. #define MRV_ISP_ISR_V_START_SHIFT 6U
  3739. /*! Slice: ISR_FRAME_IN:*/
  3740. /*! set interrupt */
  3741. #define MRV_ISP_ISR_FRAME_IN
  3742. #define MRV_ISP_ISR_FRAME_IN_MASK 0x00000020U
  3743. #define MRV_ISP_ISR_FRAME_IN_SHIFT 5U
  3744. /*! Slice: ISR_AWB_DONE:*/
  3745. /*! set interrupt */
  3746. #define MRV_ISP_ISR_AWB_DONE
  3747. #define MRV_ISP_ISR_AWB_DONE_MASK 0x00000010U
  3748. #define MRV_ISP_ISR_AWB_DONE_SHIFT 4U
  3749. /*! Slice: ISR_PIC_SIZE_ERR:*/
  3750. /*! set interrupt */
  3751. #define MRV_ISP_ISR_PIC_SIZE_ERR
  3752. #define MRV_ISP_ISR_PIC_SIZE_ERR_MASK 0x00000008U
  3753. #define MRV_ISP_ISR_PIC_SIZE_ERR_SHIFT 3U
  3754. /*! Slice: ISR_DATA_LOSS:*/
  3755. /*! set interrupt */
  3756. #define MRV_ISP_ISR_DATA_LOSS
  3757. #define MRV_ISP_ISR_DATA_LOSS_MASK 0x00000004U
  3758. #define MRV_ISP_ISR_DATA_LOSS_SHIFT 2U
  3759. /*! Slice: ISR_FRAME:*/
  3760. /*! set interrupt */
  3761. #define MRV_ISP_ISR_FRAME
  3762. #define MRV_ISP_ISR_FRAME_MASK 0x00000002U
  3763. #define MRV_ISP_ISR_FRAME_SHIFT 1U
  3764. /*! Slice: ISR_ISP_OFF:*/
  3765. /*! set interrupt */
  3766. #define MRV_ISP_ISR_ISP_OFF
  3767. #define MRV_ISP_ISR_ISP_OFF_MASK 0x00000001U
  3768. #define MRV_ISP_ISR_ISP_OFF_SHIFT 0U
  3769. #ifdef ISP_CTM_0507 // Coefficient for cross talk matrix.Use bit 11,Values are 12-bit signed fixed-point numbers with 5 bit integer and 7 bit fractional part, ranging from -16 (0x800) to +15.992 (0x7FF).
  3770. /*! Register array: isp_ct_coeff: cross-talk configuration register (color correction matrix) (0x03A0 + n*0x4 (n=0..8))*/
  3771. /*! Slice: ct_coeff:*/
  3772. /* Coefficient n for cross talk matrix.*/
  3773. /**/
  3774. /* Values are 11-bit signed fixed-point numbers with 4 bit integer and 7 bit fractional part,*/
  3775. /* ranging from -16 (0x800) to +15.992 (0x7FF). */
  3776. #define MRV_ISP_CT_COEFF
  3777. #define MRV_ISP_CT_COEFF_MASK 0x00000FFFU
  3778. #define MRV_ISP_CT_COEFF_SHIFT 0U
  3779. #else // Coefficient for cross talk matrix.Values are 11-bit signed fixed-point numbers with 4 bit integer and 7 bit fractional part, ranging from -8 (0x400) to +7.992 (0x3FF).
  3780. /*! Register array: isp_ct_coeff: cross-talk configuration register (color correction matrix) (0x03A0 + n*0x4 (n=0..8))*/
  3781. /*! Slice: ct_coeff:*/
  3782. /* Coefficient n for cross talk matrix.*/
  3783. /**/
  3784. /* Values are 11-bit signed fixed-point numbers with 4 bit integer and 7 bit fractional part,*/
  3785. /* ranging from -8 (0x400) to +7.992 (0x3FF). 0 is reprsented by 0x000 and a coefficient value of 1 as 0x080.*/
  3786. #define MRV_ISP_CT_COEFF
  3787. #define MRV_ISP_CT_COEFF_MASK 0x000007FFU
  3788. #define MRV_ISP_CT_COEFF_SHIFT 0U
  3789. #endif //CTM_0507
  3790. /*! Register: isp_gamma_out_mode: gamma segmentation mode register for output gamma (0x000001f4)*/
  3791. /*! Slice: equ_segm:*/
  3792. /*! 0: logarithmic like segmentation of gamma curve (default after reset)*/
  3793. /* segmentation from 0 to 4095: 64 64 64 64 128 128 128 128 256 256 256 512 512 512 512 512 */
  3794. /* 1: equidistant segmentation (all 16 segments are 256 )*/
  3795. #define MRV_ISP_EQU_SEGM
  3796. #define MRV_ISP_EQU_SEGM_MASK 0x00000001U
  3797. #define MRV_ISP_EQU_SEGM_SHIFT 0U
  3798. /*! Register array: isp_gamma_out_y: Gamma Out Curve definition y_ (0x03F0 + n*0x4 (n=0..16))*/
  3799. /*! Slice: isp_gamma_out_y:*/
  3800. /* Gamma_out curve point definition y-axis (output) for all color components (red,green,blue)*/
  3801. /* RESTRICTION: The difference between two Y_n (dy = Y_n - Y_n-1) is restricted to +511/-512 (10 bit signed)!*/
  3802. #define MRV_ISP_ISP_GAMMA_OUT_Y
  3803. #define MRV_ISP_ISP_GAMMA_OUT_Y_MASK 0x000003FFU
  3804. #define MRV_ISP_ISP_GAMMA_OUT_Y_SHIFT 0U
  3805. /*! Register: isp_err: ISP error register (0x0000023c)*/
  3806. /*! Slice: outform_size_err:*/
  3807. /*! size error is generated in outmux submodule */
  3808. #define MRV_ISP_OUTFORM_SIZE_ERR
  3809. #define MRV_ISP_OUTFORM_SIZE_ERR_MASK 0x00000004U
  3810. #define MRV_ISP_OUTFORM_SIZE_ERR_SHIFT 2U
  3811. /*! Slice: is_size_err:*/
  3812. /*! size error is generated in image stabilization submodule */
  3813. #define MRV_ISP_IS_SIZE_ERR
  3814. #define MRV_ISP_IS_SIZE_ERR_MASK 0x00000002U
  3815. #define MRV_ISP_IS_SIZE_ERR_SHIFT 1U
  3816. #ifdef ISP_RAWIS
  3817. /*! Register: isp_raw_is_ctrl: Raw Image Stabilization Control Register (0x00000000)*/
  3818. /*! Slice: is_en:*/
  3819. /*! 1: image stabilization switched on */
  3820. /* 0: image stabilization switched off */
  3821. #define MRV_ISP_RAW_IS_EN
  3822. #define MRV_ISP_RAW_IS_EN_MASK 0x00000001U
  3823. #define MRV_ISP_RAW_IS_EN_SHIFT 0U
  3824. /*! Register: isp_raw_is_recenter: Recenter register (0x00000004)*/
  3825. /*! Slice: is_recenter:*/
  3826. /*! 000: recenter feature switched off */
  3827. /* 1..7: recentering by (cur_h/v_offs-H/V_OFFS)/2^RECENTER */
  3828. #define MRV_ISP_RAW_IS_RECENTER
  3829. #define MRV_ISP_RAW_IS_RECENTER_MASK 0x00000007U
  3830. #define MRV_ISP_RAW_IS_RECENTER_SHIFT 0U
  3831. /*! Register: isp_raw_is_h_offs: Horizontal offset of output window (0x00000008)*/
  3832. /*! Slice: is_h_offs:*/
  3833. /*! horizontal picture offset in pixel */
  3834. #define MRV_ISP_RAW_IS_H_OFFS
  3835. #define MRV_ISP_RAW_IS_H_OFFS_MASK 0x00001FFFU
  3836. #define MRV_ISP_RAW_IS_H_OFFS_SHIFT 0U
  3837. /*! Register: isp_raw_is_v_offs: Vertical offset of output window (0x0000000c)*/
  3838. /*! Slice: is_v_offs:*/
  3839. /*! vertical picture offset in lines */
  3840. #define MRV_ISP_RAW_IS_V_OFFS
  3841. #define MRV_ISP_RAW_IS_V_OFFS_MASK 0x00000FFFU
  3842. #define MRV_ISP_RAW_IS_V_OFFS_SHIFT 0U
  3843. /*! Register: isp_raw_is_h_size: Output horizontal picture size (0x00000010)*/
  3844. /*! Slice: is_h_size:*/
  3845. /*! horizontal picture size in pixel */
  3846. /* if ISP_MODE is set to */
  3847. /* 001-(ITU-R BT.656 YUV),*/
  3848. /* 010-( ITU-R BT.601 YUV),*/
  3849. /* 011-( ITU-R BT.601 Bayer RGB),*/
  3850. /* 101-( ITU-R BT.656 Bayer RGB)*/
  3851. /* only even numbers are accepted, because complete quadruples of YUYV(YCbYCr) are needed for the following modules. If an odd size is programmed the value will be truncated to even size.*/
  3852. #define MRV_ISP_RAW_IS_H_SIZE
  3853. #define MRV_ISP_RAW_IS_H_SIZE_MASK 0x00001FFFU
  3854. #define MRV_ISP_RAW_IS_H_SIZE_SHIFT 0U
  3855. /*! Register: isp_raw_is_v_size: Output vertical picture size (0x00000014)*/
  3856. /*! Slice: is_v_size:*/
  3857. /*! vertical picture size in lines */
  3858. #define MRV_ISP_RAW_IS_V_SIZE
  3859. #define MRV_ISP_RAW_IS_V_SIZE_MASK 0x00000FFFU
  3860. #define MRV_ISP_RAW_IS_V_SIZE_SHIFT 0U
  3861. /*! Register: isp_raw_is_max_dx: Maximum Horizontal Displacement (0x00000018)*/
  3862. /*! Slice: is_max_dx:*/
  3863. /*! maximum allowed accumulated horizontal displacement in pixels */
  3864. #define MRV_ISP_RAW_IS_MAX_DX
  3865. #define MRV_ISP_RAW_IS_MAX_DX_MASK 0x00000FFFU
  3866. #define MRV_ISP_RAW_IS_MAX_DX_SHIFT 0U
  3867. /*! Register: isp_raw_is_max_dy: Maximum Vertical Displacement (0x0000001c)*/
  3868. /*! Slice: is_max_dy:*/
  3869. /*! maximum allowed accumulated vertical displacement in lines */
  3870. #define MRV_ISP_RAW_IS_MAX_DY
  3871. #define MRV_ISP_RAW_IS_MAX_DY_MASK 0x00000FFFU
  3872. #define MRV_ISP_RAW_IS_MAX_DY_SHIFT 0U
  3873. /*! Register: isp_raw_is_displace: Camera displacement (0x00000020)*/
  3874. /*! Slice: dy:*/
  3875. /*! ISP_RAW_IS will compensate for vertical camera displacement of DY lines in the next frame */
  3876. #define MRV_ISP_RAW_IS_DY
  3877. #define MRV_ISP_RAW_IS_DY_MASK 0x0FFF0000U
  3878. #define MRV_ISP_RAW_IS_DY_SHIFT 16U
  3879. /*! Slice: dx:*/
  3880. /*! ISP_RAW_IS will compensate for horizontal camera displacement of DX pixels in the next frame */
  3881. #define MRV_ISP_RAW_IS_DX
  3882. #define MRV_ISP_RAW_IS_DX_MASK 0x00000FFFU
  3883. #define MRV_ISP_RAW_IS_DX_SHIFT 0U
  3884. #endif
  3885. /*! Slice: inform_size_err:*/
  3886. /*! size error is generated in inform submodule */
  3887. #define MRV_ISP_INFORM_SIZE_ERR
  3888. #define MRV_ISP_INFORM_SIZE_ERR_MASK 0x00000001U
  3889. #define MRV_ISP_INFORM_SIZE_ERR_SHIFT 0U
  3890. /*! Register: isp_err_clr: ISP error clear register (0x00000240)*/
  3891. /*! Slice: outform_size_err_clr:*/
  3892. /*! size error is cleared */
  3893. #define MRV_ISP_OUTFORM_SIZE_ERR_CLR
  3894. #define MRV_ISP_OUTFORM_SIZE_ERR_CLR_MASK 0x00000004U
  3895. #define MRV_ISP_OUTFORM_SIZE_ERR_CLR_SHIFT 2U
  3896. /*! Slice: is_size_err_clr:*/
  3897. /*! size error is cleared */
  3898. #define MRV_ISP_IS_SIZE_ERR_CLR
  3899. #define MRV_ISP_IS_SIZE_ERR_CLR_MASK 0x00000002U
  3900. #define MRV_ISP_IS_SIZE_ERR_CLR_SHIFT 1U
  3901. /*! Slice: inform_size_err_clr:*/
  3902. /*! size error is cleared */
  3903. #define MRV_ISP_INFORM_SIZE_ERR_CLR
  3904. #define MRV_ISP_INFORM_SIZE_ERR_CLR_MASK 0x00000001U
  3905. #define MRV_ISP_INFORM_SIZE_ERR_CLR_SHIFT 0U
  3906. /*! Register: isp_frame_count: Frame counter (0x00000244)*/
  3907. /*! Slice: frame_counter:*/
  3908. /*! Current frame count of processing */
  3909. #define MRV_ISP_FRAME_COUNTER
  3910. #define MRV_ISP_FRAME_COUNTER_MASK 0x000003FFU
  3911. #define MRV_ISP_FRAME_COUNTER_SHIFT 0U
  3912. /*! Register: isp_ct_offset_r: cross-talk offset red (0x00000248)*/
  3913. /*! Slice: ct_offset_r:*/
  3914. /*! Offset red for cross talk matrix. Two's complement integer number ranging from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/
  3915. #define MRV_ISP_CT_OFFSET_R
  3916. #define MRV_ISP_CT_OFFSET_R_MASK 0x00000FFFU
  3917. #define MRV_ISP_CT_OFFSET_R_SHIFT 0U
  3918. /*! Register: isp_ct_offset_g: cross-talk offset green (0x0000024c)*/
  3919. /*! Slice: ct_offset_g:*/
  3920. /*! Offset green for cross talk matrix. Two's complement integer number ranging from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/
  3921. #define MRV_ISP_CT_OFFSET_G
  3922. #define MRV_ISP_CT_OFFSET_G_MASK 0x00000FFFU
  3923. #define MRV_ISP_CT_OFFSET_G_SHIFT 0U
  3924. /*! Register: isp_ct_offset_b: cross-talk offset blue (0x00000250)*/
  3925. /*! Slice: ct_offset_b:*/
  3926. /*! Offset blue for cross talk matrix. Two's complement integer number ranging from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/
  3927. #define MRV_ISP_CT_OFFSET_B
  3928. #define MRV_ISP_CT_OFFSET_B_MASK 0x00000FFFU
  3929. #define MRV_ISP_CT_OFFSET_B_SHIFT 0U
  3930. /*! Register: isp_cnr_linesize: chroma noise reduction line size (0x00000254)*/
  3931. /*! Slice: cnr_linesize:*/
  3932. /*! horizontal image size for chroma noise reduction */
  3933. #define MRV_ISP_CNR_LINESIZE
  3934. #define MRV_ISP_CNR_LINESIZE_MASK 0x00003FFFU
  3935. #define MRV_ISP_CNR_LINESIZE_SHIFT 0U
  3936. /*! Register: isp_cnr_threshold_c1: chroma noise reduction C1 Threshold (0x00000258)*/
  3937. /*! Slice: cnr_threshold_c1:*/
  3938. /*! Avoid filtering at edges for C1 by using low threshold values for C1 chroma noise filtering.*/
  3939. /* 0: No filtering */
  3940. /* 32767: all samples are filtered.*/
  3941. #define MRV_ISP_CNR_THRESHOLD_C1
  3942. #define MRV_ISP_CNR_THRESHOLD_C1_MASK 0x00007FFFU
  3943. #define MRV_ISP_CNR_THRESHOLD_C1_SHIFT 0U
  3944. /*! Register: isp_cnr_threshold_c2: chroma noise reduction C2 Threshold (0x0000025c)*/
  3945. /*! Slice: cnr_threshold_c2:*/
  3946. /*! Avoid filtering at edges for C2 by using low threshold values for C2 chroma noise filtering.*/
  3947. /* 0: No filtering */
  3948. /* 32767: all samples are filtered.*/
  3949. #define MRV_ISP_CNR_THRESHOLD_C2
  3950. #define MRV_ISP_CNR_THRESHOLD_C2_MASK 0x00007FFFU
  3951. #define MRV_ISP_CNR_THRESHOLD_C2_SHIFT 0U
  3952. /*! Register: isp_flash_cmd: Flash command (0x00000000)*/
  3953. /*! Slice: preflash_on:*/
  3954. /*! preflash on */
  3955. /* 0: no effect */
  3956. /* 1: flash delay counter is started at next trigger event */
  3957. /* No capture event is signaled to the sensor interface block.*/
  3958. #define MRV_FLASH_PREFLASH_ON
  3959. #define MRV_FLASH_PREFLASH_ON_MASK 0x00000004U
  3960. #define MRV_FLASH_PREFLASH_ON_SHIFT 2U
  3961. /*! Slice: flash_on:*/
  3962. /*! flash on */
  3963. /* 0: no effect */
  3964. /* 1: flash delay counter is started at next trigger event */
  3965. /* A capture event is signaled to the sensor interface block.*/
  3966. #define MRV_FLASH_FLASH_ON
  3967. #define MRV_FLASH_FLASH_ON_MASK 0x00000002U
  3968. #define MRV_FLASH_FLASH_ON_SHIFT 1U
  3969. /*! Slice: prelight_on:*/
  3970. /*! prelight on */
  3971. /* 0: prelight is switched off at next trigger event */
  3972. /* 1: prelight is switched on at next trigger event */
  3973. #define MRV_FLASH_PRELIGHT_ON
  3974. #define MRV_FLASH_PRELIGHT_ON_MASK 0x00000001U
  3975. #define MRV_FLASH_PRELIGHT_ON_SHIFT 0U
  3976. /*! Register: isp_flash_config: Flash config (0x00000004)*/
  3977. /*! Slice: fl_cap_del:*/
  3978. /*! capture delay */
  3979. /* frame number (0 to 15) to be captured after trigger event */
  3980. #define MRV_FLASH_FL_CAP_DEL
  3981. #define MRV_FLASH_FL_CAP_DEL_MASK 0x000000F0U
  3982. #define MRV_FLASH_FL_CAP_DEL_SHIFT 4U
  3983. /*! Slice: fl_trig_src:*/
  3984. /*! trigger source for flash and prelight */
  3985. /* 0: use “vds_vsync” for trigger event (with evaluation of vs_in_edge)*/
  3986. /* 1: use “fl_trig” for trigger event (positive edge)*/
  3987. #define MRV_FLASH_FL_TRIG_SRC
  3988. #define MRV_FLASH_FL_TRIG_SRC_MASK 0x00000008U
  3989. #define MRV_FLASH_FL_TRIG_SRC_SHIFT 3U
  3990. /*! Slice: fl_pol:*/
  3991. /*! polarity of flash related signals */
  3992. /* 0: flash_trig, prelight_trig are high active */
  3993. /* 1: flash_trig, prelight_trig are low active */
  3994. #define MRV_FLASH_FL_POL
  3995. #define MRV_FLASH_FL_POL_MASK 0x00000004U
  3996. #define MRV_FLASH_FL_POL_SHIFT 2U
  3997. /*! Slice: vs_in_edge:*/
  3998. /*! VSYNC edge */
  3999. /* 0: use negative edge of “vds_vsync” if generating a trigger event */
  4000. /* 1: use positive edge of “vds_vsync” if generating a trigger event */
  4001. #define MRV_FLASH_VS_IN_EDGE
  4002. #define MRV_FLASH_VS_IN_EDGE_MASK 0x00000002U
  4003. #define MRV_FLASH_VS_IN_EDGE_SHIFT 1U
  4004. /*! Slice: prelight_mode:*/
  4005. /*! prelight mode */
  4006. /* 0: prelight is switched off at begin of flash */
  4007. /* 1: prelight is switched off at end of flash */
  4008. #define MRV_FLASH_PRELIGHT_MODE
  4009. #define MRV_FLASH_PRELIGHT_MODE_MASK 0x00000001U
  4010. #define MRV_FLASH_PRELIGHT_MODE_SHIFT 0U
  4011. /*! Register: isp_flash_prediv: Flash Counter Pre-Divider (0x00000008)*/
  4012. /*! Slice: fl_pre_div:*/
  4013. /*! pre-divider for flush/preflash counter */
  4014. #define MRV_FLASH_FL_PRE_DIV
  4015. #define MRV_FLASH_FL_PRE_DIV_MASK 0x000003FFU
  4016. #define MRV_FLASH_FL_PRE_DIV_SHIFT 0U
  4017. /*! Register: isp_flash_delay: Flash Delay (0x0000000c)*/
  4018. /*! Slice: fl_delay:*/
  4019. /*! counter value for flash/preflash delay */
  4020. /* open_delay = (fl_delay + 1) * (fl_pre_div+1) / clk_isp */
  4021. /* fl_delay = (open_delay * clk_isp) / (fl_pre_div+1) - 1 */
  4022. #define MRV_FLASH_FL_DELAY
  4023. #define MRV_FLASH_FL_DELAY_MASK 0x0003FFFFU
  4024. #define MRV_FLASH_FL_DELAY_SHIFT 0U
  4025. /*! Register: isp_flash_time: Flash time (0x00000010)*/
  4026. /*! Slice: fl_time:*/
  4027. /*! counter value for flash/preflash time */
  4028. /* open_time = (fl_time + 1) * (fl_pre_div+1) / clk_isp */
  4029. /* fl_time = (open_time * clk_isp) / (fl_pre_div+1) - 1 */
  4030. #define MRV_FLASH_FL_TIME
  4031. #define MRV_FLASH_FL_TIME_MASK 0x0003FFFFU
  4032. #define MRV_FLASH_FL_TIME_SHIFT 0U
  4033. /*! Register: isp_flash_maxp: Maximum value for flash or preflash (0x00000014)*/
  4034. /*! Slice: fl_maxp:*/
  4035. /*! maximum period value for flash or preflash */
  4036. /* max. flash/preflash period = 214 * (fl_maxp + 1) / clk_isp */
  4037. /* fl_maxp = (max_period * clk_isp) / 214 - 1 */
  4038. #define MRV_FLASH_FL_MAXP
  4039. #define MRV_FLASH_FL_MAXP_MASK 0x0000FFFFU
  4040. #define MRV_FLASH_FL_MAXP_SHIFT 0U
  4041. /*! Register: isp_sh_ctrl: mechanical shutter control (0x00000000)*/
  4042. /*! Slice: sh_open_pol:*/
  4043. /*! shutter_open polarity */
  4044. /* 0: shutter_open is high active */
  4045. /* 1: shutter_open is low active */
  4046. #define MRV_SHUT_SH_OPEN_POL
  4047. #define MRV_SHUT_SH_OPEN_POL_MASK 0x00000010U
  4048. #define MRV_SHUT_SH_OPEN_POL_SHIFT 4U
  4049. /*! Slice: sh_trig_en:*/
  4050. /*! mechanical shutter trigger edge */
  4051. /* 0: use negative edge of trigger signal */
  4052. /* 1: use positive edge of trigger signal */
  4053. #define MRV_SHUT_SH_TRIG_EN
  4054. #define MRV_SHUT_SH_TRIG_EN_MASK 0x00000008U
  4055. #define MRV_SHUT_SH_TRIG_EN_SHIFT 3U
  4056. /*! Slice: sh_trig_src:*/
  4057. /*! mechanical shutter trigger source */
  4058. /* 0: use “vds_vsync” for trigger event */
  4059. /* 1: use “shutter_trig” for trigger event */
  4060. #define MRV_SHUT_SH_TRIG_SRC
  4061. #define MRV_SHUT_SH_TRIG_SRC_MASK 0x00000004U
  4062. #define MRV_SHUT_SH_TRIG_SRC_SHIFT 2U
  4063. /*! Slice: sh_rep_en:*/
  4064. /*! mechanical shutter repetition enable */
  4065. /* 0: shutter is opened only once */
  4066. /* 1: shutter is opened with the repetition rate of the trigger signal */
  4067. #define MRV_SHUT_SH_REP_EN
  4068. #define MRV_SHUT_SH_REP_EN_MASK 0x00000002U
  4069. #define MRV_SHUT_SH_REP_EN_SHIFT 1U
  4070. /*! Slice: sh_en:*/
  4071. /*! mechanical shutter enable */
  4072. /* 0: mechanical shutter function is disabled */
  4073. /* 1: mechanical shutter function is enabled */
  4074. #define MRV_SHUT_SH_EN
  4075. #define MRV_SHUT_SH_EN_MASK 0x00000001U
  4076. #define MRV_SHUT_SH_EN_SHIFT 0U
  4077. /*! Register: isp_sh_prediv: Mech. Shutter Counter Pre-Divider (0x00000004)*/
  4078. /*! Slice: sh_pre_div:*/
  4079. /*! pre-divider for mechanical shutter open_delay and open_time counter */
  4080. #define MRV_SHUT_SH_PRE_DIV
  4081. #define MRV_SHUT_SH_PRE_DIV_MASK 0x000003FFU
  4082. #define MRV_SHUT_SH_PRE_DIV_SHIFT 0U
  4083. /*! Register: isp_sh_delay: Delay register (0x00000008)*/
  4084. /*! Slice: sh_delay:*/
  4085. /*! counter value for delay */
  4086. /* open_delay = (sh_delay + 1) * (fl_pre_div+1) / clk_isp */
  4087. /* sh_delay = (open_delay * clk_isp) / (sh_pre_div+1) – 1 */
  4088. #define MRV_SHUT_SH_DELAY
  4089. #define MRV_SHUT_SH_DELAY_MASK 0x000FFFFFU
  4090. #define MRV_SHUT_SH_DELAY_SHIFT 0U
  4091. /*! Register: isp_sh_time: Time register (0x0000000c)*/
  4092. /*! Slice: sh_time:*/
  4093. /*! counter value for time */
  4094. /* open_time = (sh_time + 1) * (fl_pre_div+1) / clk_isp */
  4095. /* sh_time = (open_time * clk_isp) / (sh_pre_div+1) - 1 */
  4096. #define MRV_SHUT_SH_TIME
  4097. #define MRV_SHUT_SH_TIME_MASK 0x000FFFFFU
  4098. #define MRV_SHUT_SH_TIME_SHIFT 0U
  4099. /*! Register: cproc_ctrl: Global control register (0x00000000)*/
  4100. /*! Slice: cproc_c_out_range:*/
  4101. /*! Color processing chrominance pixel clipping range at output */
  4102. /* 0: CbCr_out clipping range 16..240 according to ITU-R BT.601 standard */
  4103. /* 1: full UV_out clipping range 0..255 */
  4104. #define MRV_CPROC_CPROC_C_OUT_RANGE
  4105. #define MRV_CPROC_CPROC_C_OUT_RANGE_MASK 0x00000008U
  4106. #define MRV_CPROC_CPROC_C_OUT_RANGE_SHIFT 3U
  4107. /*! Slice: cproc_y_in_range:*/
  4108. /*! Color processing luminance input range (offset processing)*/
  4109. /* 0: Y_in range 64..940 according to ITU-R BT.601 standard;*/
  4110. /* offset of 64 will be subtracted from Y_in */
  4111. /* 1: Y_in full range 0..1023; no offset will be subtracted from Y_in */
  4112. #define MRV_CPROC_CPROC_Y_IN_RANGE
  4113. #define MRV_CPROC_CPROC_Y_IN_RANGE_MASK 0x00000004U
  4114. #define MRV_CPROC_CPROC_Y_IN_RANGE_SHIFT 2U
  4115. /*! Slice: cproc_y_out_range:*/
  4116. /*! Color processing luminance output clipping range */
  4117. /* 0: Y_out clipping range 16..235; offset of 16 is added to Y_out according to ITU-R BT.601 standard */
  4118. /* 1: Y_out clipping range 0..255; no offset is added to Y_out */
  4119. #define MRV_CPROC_CPROC_Y_OUT_RANGE
  4120. #define MRV_CPROC_CPROC_Y_OUT_RANGE_MASK 0x00000002U
  4121. #define MRV_CPROC_CPROC_Y_OUT_RANGE_SHIFT 1U
  4122. /*! Slice: cproc_enable:*/
  4123. /*! color processing enable */
  4124. /* 0: color processing is bypassed */
  4125. /* 2 * 10 Bit input data are truncated to 2 * 8Bit output data */
  4126. /* 1: color processing is active */
  4127. /* output data are rounded to 2 * 8Bit and clipping is active */
  4128. #define MRV_CPROC_CPROC_ENABLE
  4129. #define MRV_CPROC_CPROC_ENABLE_MASK 0x00000001U
  4130. #define MRV_CPROC_CPROC_ENABLE_SHIFT 0U
  4131. /*! Register: cproc_contrast: Color Processing contrast register (0x00000004)*/
  4132. /*! Slice: cproc_contrast:*/
  4133. /*! contrast adjustment value */
  4134. /* 00H equals x 0.0 */
  4135. /* …*/
  4136. /* 80H equals x 1.0 */
  4137. /* …*/
  4138. /* FFH equals x 1.992 */
  4139. #define MRV_CPROC_CPROC_CONTRAST
  4140. #define MRV_CPROC_CPROC_CONTRAST_MASK 0x000000FFU
  4141. #define MRV_CPROC_CPROC_CONTRAST_SHIFT 0U
  4142. /*! Register: cproc_brightness: Color Processing brightness register (0x00000008)*/
  4143. /*! Slice: cproc_brightness:*/
  4144. /*! brightness adjustment value */
  4145. /* 80H equals -128 */
  4146. /* …*/
  4147. /* 00H equals +0 */
  4148. /* …*/
  4149. /* 7FH equals +127 */
  4150. #define MRV_CPROC_CPROC_BRIGHTNESS
  4151. #define MRV_CPROC_CPROC_BRIGHTNESS_MASK 0x000000FFU
  4152. #define MRV_CPROC_CPROC_BRIGHTNESS_SHIFT 0U
  4153. /*! Register: cproc_saturation: Color Processing saturation register (0x0000000c)*/
  4154. /*! Slice: cproc_saturation:*/
  4155. /*! saturation adjustment value */
  4156. /* 00H equals x 0.0 */
  4157. /* …*/
  4158. /* 80H equals x 1.0 */
  4159. /* …*/
  4160. /* FFH equals x 1.992 */
  4161. #define MRV_CPROC_CPROC_SATURATION
  4162. #define MRV_CPROC_CPROC_SATURATION_MASK 0x000000FFU
  4163. #define MRV_CPROC_CPROC_SATURATION_SHIFT 0U
  4164. /*! Register: cproc_hue: Color Processing hue register (0x00000010)*/
  4165. /*! Slice: cproc_hue:*/
  4166. /*! hue adjustment value */
  4167. /* 80H equals -90 deg */
  4168. /* …*/
  4169. /* 00H equals 0 deg */
  4170. /* …*/
  4171. /* 7FH equals +87.188 deg */
  4172. #define MRV_CPROC_CPROC_HUE
  4173. #define MRV_CPROC_CPROC_HUE_MASK 0x000000FFU
  4174. #define MRV_CPROC_CPROC_HUE_SHIFT 0U
  4175. #ifdef ISP8000NANO_BASE
  4176. /*! Register: mrsz_ctrl: global control register (0x00000000)*/
  4177. /*! Slice: auto_upd:*/
  4178. /*! 1: automatic register update at frame end enabled.*/
  4179. /* 0: automatic register update at frame end disabled.*/
  4180. #define MRV_MRSZ_AUTO_UPD
  4181. #define MRV_MRSZ_AUTO_UPD_MASK 0x00000200U
  4182. #define MRV_MRSZ_AUTO_UPD_SHIFT 9U
  4183. /*! Slice: cfg_upd:*/
  4184. /*! write 0: nothing happens */
  4185. /* write 1: update shadow registers */
  4186. /* read: always 0 */
  4187. #define MRV_MRSZ_CFG_UPD
  4188. #define MRV_MRSZ_CFG_UPD_MASK 0x00000100U
  4189. #define MRV_MRSZ_CFG_UPD_SHIFT 8U
  4190. #else
  4191. /*! Register: mrsz_ctrl: global control register (0x00000000)*/
  4192. /*! Slice: auto_upd:*/
  4193. /*! 1: automatic register update at frame end enabled.*/
  4194. /* 0: automatic register update at frame end disabled.*/
  4195. #define MRV_MRSZ_AUTO_UPD
  4196. #define MRV_MRSZ_AUTO_UPD_MASK 0x00000400U
  4197. #define MRV_MRSZ_AUTO_UPD_SHIFT 10U
  4198. /*! Slice: cfg_upd:*/
  4199. /*! write 0: nothing happens */
  4200. /* write 1: update shadow registers */
  4201. /* read: always 0 */
  4202. #define MRV_MRSZ_CFG_UPD
  4203. #define MRV_MRSZ_CFG_UPD_MASK 0x00000200U
  4204. #define MRV_MRSZ_CFG_UPD_SHIFT 9U
  4205. /*! Slice: crop_enable:*/
  4206. #define MRV_MRSZ_CROP_ENABLE
  4207. #define MRV_MRSZ_CROP_ENABLE_MASK 0x00000100U
  4208. #define MRV_MRSZ_CROP_ENABLE_SHIFT 8U
  4209. #endif
  4210. /*! Slice: scale_vc_up:*/
  4211. /*! 1: vertical chrominance upscaling selected */
  4212. /* 0: vertical chrominance downscaling selected */
  4213. #define MRV_MRSZ_SCALE_VC_UP
  4214. #define MRV_MRSZ_SCALE_VC_UP_MASK 0x00000080U
  4215. #define MRV_MRSZ_SCALE_VC_UP_SHIFT 7U
  4216. /*! Slice: scale_vy_up:*/
  4217. /*! 1: vertical luminance upscaling selected */
  4218. /* 0: vertical luminance downscaling selected */
  4219. #define MRV_MRSZ_SCALE_VY_UP
  4220. #define MRV_MRSZ_SCALE_VY_UP_MASK 0x00000040U
  4221. #define MRV_MRSZ_SCALE_VY_UP_SHIFT 6U
  4222. /*! Slice: scale_hc_up:*/
  4223. /*! 1: horizontal chrominance upscaling selected */
  4224. /* 0: horizontal chrominance downscaling selected */
  4225. #define MRV_MRSZ_SCALE_HC_UP
  4226. #define MRV_MRSZ_SCALE_HC_UP_MASK 0x00000020U
  4227. #define MRV_MRSZ_SCALE_HC_UP_SHIFT 5U
  4228. /*! Slice: scale_hy_up:*/
  4229. /*! 1: horizontal luminance upscaling selected */
  4230. /* 0: horizontal luminance downscaling selected */
  4231. #define MRV_MRSZ_SCALE_HY_UP
  4232. #define MRV_MRSZ_SCALE_HY_UP_MASK 0x00000010U
  4233. #define MRV_MRSZ_SCALE_HY_UP_SHIFT 4U
  4234. /*! Slice: scale_vc_enable:*/
  4235. /*! 0: bypass vertical chrominance scaling unit */
  4236. /* 1: enable vertical chrominance scaling unit */
  4237. #define MRV_MRSZ_SCALE_VC_ENABLE
  4238. #define MRV_MRSZ_SCALE_VC_ENABLE_MASK 0x00000008U
  4239. #define MRV_MRSZ_SCALE_VC_ENABLE_SHIFT 3U
  4240. /*! Slice: scale_vy_enable:*/
  4241. /*! 0: bypass vertical luminance scaling unit */
  4242. /* 1: enable vertical luminance scaling unit */
  4243. #define MRV_MRSZ_SCALE_VY_ENABLE
  4244. #define MRV_MRSZ_SCALE_VY_ENABLE_MASK 0x00000004U
  4245. #define MRV_MRSZ_SCALE_VY_ENABLE_SHIFT 2U
  4246. /*! Slice: scale_hc_enable:*/
  4247. /*! 0: bypass horizontal chrominance scaling unit */
  4248. /* 1: enable horizontal chrominance scaling unit */
  4249. #define MRV_MRSZ_SCALE_HC_ENABLE
  4250. #define MRV_MRSZ_SCALE_HC_ENABLE_MASK 0x00000002U
  4251. #define MRV_MRSZ_SCALE_HC_ENABLE_SHIFT 1U
  4252. /*! Slice: scale_hy_enable:*/
  4253. /*! 0: bypass horizontal luminance scaling unit */
  4254. /* 1: enable horizontal luminance scaling unit */
  4255. #define MRV_MRSZ_SCALE_HY_ENABLE
  4256. #define MRV_MRSZ_SCALE_HY_ENABLE_MASK 0x00000001U
  4257. #define MRV_MRSZ_SCALE_HY_ENABLE_SHIFT 0U
  4258. /*! Register: mrsz_scale_hy: horizontal luminance scale factor register (0x00000004)*/
  4259. /*! Slice: scale_hy:*/
  4260. /*! This register is set to the horizontal luminance downscale factor or to the reciprocal of the horizontal luminance upscale factor */
  4261. #define MRV_MRSZ_SCALE_HY
  4262. #define MRV_MRSZ_SCALE_HY_MASK 0x0000FFFFU
  4263. #define MRV_MRSZ_SCALE_HY_SHIFT 0U
  4264. /*! Register: mrsz_scale_hcb: horizontal Cb scale factor register (0x00000008)*/
  4265. /*! Slice: scale_hcb:*/
  4266. /*! This register is set to the horizontal Cb downscale factor or to the reciprocal of the horizontal Cb upscale factor */
  4267. #define MRV_MRSZ_SCALE_HCB
  4268. #define MRV_MRSZ_SCALE_HCB_MASK 0x0000FFFFU
  4269. #define MRV_MRSZ_SCALE_HCB_SHIFT 0U
  4270. /*! Register: mrsz_scale_hcr: horizontal Cr scale factor register (0x0000000c)*/
  4271. /*! Slice: scale_hcr:*/
  4272. /*! This register is set to the horizontal Cr downscale factor or to the reciprocal of the horizontal Cr upscale factor */
  4273. #define MRV_MRSZ_SCALE_HCR
  4274. #define MRV_MRSZ_SCALE_HCR_MASK 0x0000FFFFU
  4275. #define MRV_MRSZ_SCALE_HCR_SHIFT 0U
  4276. /*! Register: mrsz_scale_vy: vertical luminance scale factor register (0x00000010)*/
  4277. /*! Slice: scale_vy:*/
  4278. /*! This register is set to the vertical luminance downscale factor or to the reciprocal of the vertical luminance upscale factor */
  4279. #define MRV_MRSZ_SCALE_VY
  4280. #define MRV_MRSZ_SCALE_VY_MASK 0x0000FFFFU
  4281. #define MRV_MRSZ_SCALE_VY_SHIFT 0U
  4282. /*! Register: mrsz_scale_vc: vertical chrominance scale factor register (0x00000014)*/
  4283. /*! Slice: scale_vc:*/
  4284. /*! This register is set to the vertical chrominance downscale factor or to the reciprocal of the vertical chrominance upscale factor */
  4285. #define MRV_MRSZ_SCALE_VC
  4286. #define MRV_MRSZ_SCALE_VC_MASK 0x0000FFFFU
  4287. #define MRV_MRSZ_SCALE_VC_SHIFT 0U
  4288. /*! Register: mrsz_phase_hy: horizontal luminance phase register (0x00000018)*/
  4289. /*! Slice: phase_hy:*/
  4290. /*! This register is set to the horizontal luminance phase offset */
  4291. #define MRV_MRSZ_PHASE_HY
  4292. #define MRV_MRSZ_PHASE_HY_MASK 0x0000FFFFU
  4293. #define MRV_MRSZ_PHASE_HY_SHIFT 0U
  4294. /*! Register: mrsz_phase_hc: horizontal chrominance phase register (0x0000001c)*/
  4295. /*! Slice: phase_hc:*/
  4296. /*! This register is set to the horizontal chrominance phase offset */
  4297. #define MRV_MRSZ_PHASE_HC
  4298. #define MRV_MRSZ_PHASE_HC_MASK 0x0000FFFFU
  4299. #define MRV_MRSZ_PHASE_HC_SHIFT 0U
  4300. /*! Register: mrsz_phase_vy: vertical luminance phase register (0x00000020)*/
  4301. /*! Slice: phase_vy:*/
  4302. /*! This register is set to the vertical luminance phase offset */
  4303. #define MRV_MRSZ_PHASE_VY
  4304. #define MRV_MRSZ_PHASE_VY_MASK 0x0000FFFFU
  4305. #define MRV_MRSZ_PHASE_VY_SHIFT 0U
  4306. /*! Register: mrsz_phase_vc: vertical chrominance phase register (0x00000024)*/
  4307. /*! Slice: phase_vc:*/
  4308. /*! This register is set to the vertical chrominance phase offset */
  4309. #define MRV_MRSZ_PHASE_VC
  4310. #define MRV_MRSZ_PHASE_VC_MASK 0x0000FFFFU
  4311. #define MRV_MRSZ_PHASE_VC_SHIFT 0U
  4312. /*! Register: mrsz_scale_lut_addr: Address pointer of up-scaling look up table (0x00000028)*/
  4313. /*! Slice: scale_lut_addr:*/
  4314. /*! Pointer to entry of lookup table */
  4315. #define MRV_MRSZ_SCALE_LUT_ADDR
  4316. #define MRV_MRSZ_SCALE_LUT_ADDR_MASK 0x0000003FU
  4317. #define MRV_MRSZ_SCALE_LUT_ADDR_SHIFT 0U
  4318. /*! Register: mrsz_scale_lut: Entry of up-scaling look up table (0x0000002c)*/
  4319. /*! Slice: scale_lut:*/
  4320. /*! Entry of lookup table at position scale_lut_addr. The lookup table must be filled with appropriate values before the up-scaling functionality can be used.*/
  4321. #define MRV_MRSZ_SCALE_LUT
  4322. #define MRV_MRSZ_SCALE_LUT_MASK 0x0000003FU
  4323. #define MRV_MRSZ_SCALE_LUT_SHIFT 0U
  4324. /*! Register: mrsz_ctrl_shd: global control shadow register (0x00000030)*/
  4325. /*! Slice: scale_vc_up_shd:*/
  4326. /*! 1: vertical chrominance upscaling selected */
  4327. /* 0: vertical chrominance downscaling selected */
  4328. #define MRV_MRSZ_SCALE_VC_UP_SHD
  4329. #define MRV_MRSZ_SCALE_VC_UP_SHD_MASK 0x00000080U
  4330. #define MRV_MRSZ_SCALE_VC_UP_SHD_SHIFT 7U
  4331. /*! Slice: scale_vy_up_shd:*/
  4332. /*! 1: vertical luminance upscaling selected */
  4333. /* 0: vertical luminance downscaling selected */
  4334. #define MRV_MRSZ_SCALE_VY_UP_SHD
  4335. #define MRV_MRSZ_SCALE_VY_UP_SHD_MASK 0x00000040U
  4336. #define MRV_MRSZ_SCALE_VY_UP_SHD_SHIFT 6U
  4337. /*! Slice: scale_hc_up_shd:*/
  4338. /*! 1: horizontal chrominance upscaling selected */
  4339. /* 0: horizontal chrominance downscaling selected */
  4340. #define MRV_MRSZ_SCALE_HC_UP_SHD
  4341. #define MRV_MRSZ_SCALE_HC_UP_SHD_MASK 0x00000020U
  4342. #define MRV_MRSZ_SCALE_HC_UP_SHD_SHIFT 5U
  4343. /*! Slice: scale_hy_up_shd:*/
  4344. /*! 1: horizontal luminance upscaling selected */
  4345. /* 0: horizontal luminance downscaling selected */
  4346. #define MRV_MRSZ_SCALE_HY_UP_SHD
  4347. #define MRV_MRSZ_SCALE_HY_UP_SHD_MASK 0x00000010U
  4348. #define MRV_MRSZ_SCALE_HY_UP_SHD_SHIFT 4U
  4349. /*! Slice: scale_vc_enable_shd:*/
  4350. /*! 0: bypass vertical chrominance scaling unit */
  4351. /* 1: enable vertical chrominance scaling unit */
  4352. #define MRV_MRSZ_SCALE_VC_ENABLE_SHD
  4353. #define MRV_MRSZ_SCALE_VC_ENABLE_SHD_MASK 0x00000008U
  4354. #define MRV_MRSZ_SCALE_VC_ENABLE_SHD_SHIFT 3U
  4355. /*! Slice: scale_vy_enable_shd:*/
  4356. /*! 0: bypass vertical luminance scaling unit */
  4357. /* 1: enable vertical luminance scaling unit */
  4358. #define MRV_MRSZ_SCALE_VY_ENABLE_SHD
  4359. #define MRV_MRSZ_SCALE_VY_ENABLE_SHD_MASK 0x00000004U
  4360. #define MRV_MRSZ_SCALE_VY_ENABLE_SHD_SHIFT 2U
  4361. /*! Slice: scale_hc_enable_shd:*/
  4362. /*! 0: bypass horizontal chrominance scaling unit */
  4363. /* 1: enable horizontal chrominance scaling unit */
  4364. #define MRV_MRSZ_SCALE_HC_ENABLE_SHD
  4365. #define MRV_MRSZ_SCALE_HC_ENABLE_SHD_MASK 0x00000002U
  4366. #define MRV_MRSZ_SCALE_HC_ENABLE_SHD_SHIFT 1U
  4367. /*! Slice: scale_hy_enable_shd:*/
  4368. /*! 0: bypass horizontal luminance scaling unit */
  4369. /* 1: enable horizontal luminance scaling unit */
  4370. #define MRV_MRSZ_SCALE_HY_ENABLE_SHD
  4371. #define MRV_MRSZ_SCALE_HY_ENABLE_SHD_MASK 0x00000001U
  4372. #define MRV_MRSZ_SCALE_HY_ENABLE_SHD_SHIFT 0U
  4373. /*! Register: mrsz_scale_hy_shd: horizontal luminance scale factor shadow register (0x00000034)*/
  4374. /*! Slice: scale_hy_shd:*/
  4375. /*! This register is set to the horizontal luminance downscale factor or to the reciprocal of the horizontal luminance upscale factor */
  4376. #define MRV_MRSZ_SCALE_HY_SHD
  4377. #define MRV_MRSZ_SCALE_HY_SHD_MASK 0x0000FFFFU
  4378. #define MRV_MRSZ_SCALE_HY_SHD_SHIFT 0U
  4379. /*! Register: mrsz_scale_hcb_shd: horizontal Cb scale factor shadow register (0x00000038)*/
  4380. /*! Slice: scale_hcb_shd:*/
  4381. /*! This register is set to the horizontal Cb downscale factor or to the reciprocal of the horizontal Cb upscale factor */
  4382. #define MRV_MRSZ_SCALE_HCB_SHD
  4383. #define MRV_MRSZ_SCALE_HCB_SHD_MASK 0x0000FFFFU
  4384. #define MRV_MRSZ_SCALE_HCB_SHD_SHIFT 0U
  4385. /*! Register: mrsz_scale_hcr_shd: horizontal Cr scale factor shadow register (0x0000003c)*/
  4386. /*! Slice: scale_hcr_shd:*/
  4387. /*! This register is set to the horizontal Cr downscale factor or to the reciprocal of the horizontal Cr upscale factor */
  4388. #define MRV_MRSZ_SCALE_HCR_SHD
  4389. #define MRV_MRSZ_SCALE_HCR_SHD_MASK 0x0000FFFFU
  4390. #define MRV_MRSZ_SCALE_HCR_SHD_SHIFT 0U
  4391. /*! Register: mrsz_scale_vy_shd: vertical luminance scale factor shadow register (0x00000040)*/
  4392. /*! Slice: scale_vy_shd:*/
  4393. /*! This register is set to the vertical luminance downscale factor or to the reciprocal of the vertical luminance upscale factor */
  4394. #define MRV_MRSZ_SCALE_VY_SHD
  4395. #define MRV_MRSZ_SCALE_VY_SHD_MASK 0x0000FFFFU
  4396. #define MRV_MRSZ_SCALE_VY_SHD_SHIFT 0U
  4397. /*! Register: mrsz_scale_vc_shd: vertical chrominance scale factor shadow register (0x00000044)*/
  4398. /*! Slice: scale_vc_shd:*/
  4399. /*! This register is set to the vertical chrominance downscale factor or to the reciprocal of the vertical chrominance upscale factor */
  4400. #define MRV_MRSZ_SCALE_VC_SHD
  4401. #define MRV_MRSZ_SCALE_VC_SHD_MASK 0x0000FFFFU
  4402. #define MRV_MRSZ_SCALE_VC_SHD_SHIFT 0U
  4403. /*! Register: mrsz_phase_hy_shd: horizontal luminance phase shadow register (0x00000048)*/
  4404. /*! Slice: phase_hy_shd:*/
  4405. /*! This register is set to the horizontal luminance phase offset */
  4406. #define MRV_MRSZ_PHASE_HY_SHD
  4407. #define MRV_MRSZ_PHASE_HY_SHD_MASK 0x0000FFFFU
  4408. #define MRV_MRSZ_PHASE_HY_SHD_SHIFT 0U
  4409. /*! Register: mrsz_phase_hc_shd: horizontal chrominance phase shadow register (0x0000004c)*/
  4410. /*! Slice: phase_hc_shd:*/
  4411. /*! This register is set to the horizontal chrominance phase offset */
  4412. #define MRV_MRSZ_PHASE_HC_SHD
  4413. #define MRV_MRSZ_PHASE_HC_SHD_MASK 0x0000FFFFU
  4414. #define MRV_MRSZ_PHASE_HC_SHD_SHIFT 0U
  4415. /*! Register: mrsz_phase_vy_shd: vertical luminance phase shadow register (0x00000050)*/
  4416. /*! Slice: phase_vy_shd:*/
  4417. /*! This register is set to the vertical luminance phase offset */
  4418. #define MRV_MRSZ_PHASE_VY_SHD
  4419. #define MRV_MRSZ_PHASE_VY_SHD_MASK 0x0000FFFFU
  4420. #define MRV_MRSZ_PHASE_VY_SHD_SHIFT 0U
  4421. /*! Register: mrsz_phase_crop_x_dir: Crop range in x direction register (0x00000058)*/
  4422. /*! Slice: crop_h_start:*/
  4423. /*! This slice is Selected picture start pixel position in the x-direction. */
  4424. #define MRV_MRSZ_PHASE_H_START
  4425. #define MRV_MRSZ_PHASE_H_START_MASK 0x00001FFFU
  4426. #define MRV_MRSZ_PHASE_H_START_SHIFT 0U
  4427. /*! Register: mrsz_phase_crop_x_dir: Crop range in x direction register (0x00000058)*/
  4428. /*! Slice: crop_h_end:*/
  4429. /*! This slice is Selected picture end pixel position in the x-direction.. */
  4430. #define MRV_MRSZ_PHASE_H_END
  4431. #define MRV_MRSZ_PHASE_H_END_MASK 0x1fff0000U
  4432. #define MRV_MRSZ_PHASE_H_END_SHIFT 16U
  4433. /*! Register: mrsz_phase_crop_y_dir: Crop range in y direction register (0x0000005c)*/
  4434. /*! Slice: crop_y_start:*/
  4435. /*! This slice is Selected picture start pixel position in the y-direction. */
  4436. #define MRV_MRSZ_PHASE_V_START
  4437. #define MRV_MRSZ_PHASE_V_START_MASK 0x00001FFFU
  4438. #define MRV_MRSZ_PHASE_V_START_SHIFT 0U
  4439. /*! Register: mrsz_phase_crop_y_dir: Crop range in y direction register (0x0000005c)*/
  4440. /*! Slice: crop_v_end:*/
  4441. /*! This slice is Selected picture end pixel position in the v-direction.. */
  4442. #define MRV_MRSZ_PHASE_V_END
  4443. #define MRV_MRSZ_PHASE_V_END_MASK 0x1fff0000U
  4444. #define MRV_MRSZ_PHASE_V_END_SHIFT 16U
  4445. /*! Register: mrsz_phase_vc_shd: vertical chrominance phase shadow register (0x00000054)*/
  4446. /*! Slice: phase_vc_shd:*/
  4447. /*! This register is set to the vertical chrominance phase offset */
  4448. #define MRV_MRSZ_PHASE_VC_SHD
  4449. #define MRV_MRSZ_PHASE_VC_SHD_MASK 0x0000FFFFU
  4450. #define MRV_MRSZ_PHASE_VC_SHD_SHIFT 0U
  4451. #define MRV_MRSZ_COVERT_OUTPUT
  4452. #define MRV_MRSZ_COVERT_OUTPUT_MASK 0x0000001CU
  4453. #define MRV_MRSZ_COVERT_OUTPUT_SHIFT 2U
  4454. #define MRV_MRSZ_COVERT_INPUT
  4455. #define MRV_MRSZ_COVERT_INPUT_MASK 0x00000003U
  4456. #define MRV_MRSZ_COVERT_INPUT_SHIFT 0U
  4457. #define MRV_MRSZ_COVERT_10_ENABLE
  4458. #define MRV_MRSZ_COVERT_10_ENABLE_MASK 0X00000100U
  4459. #define MRV_MRSZ_COVERT_10_ENABLE_SHIFT 8U
  4460. #define MRV_MRSZ_COVERT_10_METHOD
  4461. #define MRV_MRSZ_COVERT_10_METHOD_MASK 0X00000200U
  4462. #define MRV_MRSZ_COVERT_10_METHOD_SHIFT 9U
  4463. #define MRV_MRSZ_COVERT_PACK_FORMAT
  4464. #define MRV_MRSZ_COVERT_PACK_FORMAT_MASK 0x00000400U
  4465. #define MRV_MRSZ_COVERT_PACK_FORMAT_SHIFT 10U
  4466. /*! Register: srsz_ctrl: global control register (0x00000000)*/
  4467. /*! Slice: auto_upd:*/
  4468. /*! 1: automatic register update at frame end enabled.*/
  4469. /* 0: automatic register update at frame end disabled.*/
  4470. #define MRV_SRSZ_AUTO_UPD
  4471. #define MRV_SRSZ_AUTO_UPD_MASK 0x00000200U
  4472. #define MRV_SRSZ_AUTO_UPD_SHIFT 9U
  4473. /*! Slice: cfg_upd:*/
  4474. /*! write 0: nothing happens */
  4475. /* write 1: update shadow registers */
  4476. /* read: always 0 */
  4477. #define MRV_SRSZ_CFG_UPD
  4478. #define MRV_SRSZ_CFG_UPD_MASK 0x00000100U
  4479. #define MRV_SRSZ_CFG_UPD_SHIFT 8U
  4480. /*! Slice: scale_vc_up:*/
  4481. /*! 1: vertical chrominance upscaling selected */
  4482. /* 0: vertical chrominance downscaling selected */
  4483. #define MRV_SRSZ_SCALE_VC_UP
  4484. #define MRV_SRSZ_SCALE_VC_UP_MASK 0x00000080U
  4485. #define MRV_SRSZ_SCALE_VC_UP_SHIFT 7U
  4486. /*! Slice: scale_vy_up:*/
  4487. /*! 1: vertical luminance upscaling selected */
  4488. /* 0: vertical luminance downscaling selected */
  4489. #define MRV_SRSZ_SCALE_VY_UP
  4490. #define MRV_SRSZ_SCALE_VY_UP_MASK 0x00000040U
  4491. #define MRV_SRSZ_SCALE_VY_UP_SHIFT 6U
  4492. /*! Slice: scale_hc_up:*/
  4493. /*! 1: horizontal chrominance upscaling selected */
  4494. /* 0: horizontal chrominance downscaling selected */
  4495. #define MRV_SRSZ_SCALE_HC_UP
  4496. #define MRV_SRSZ_SCALE_HC_UP_MASK 0x00000020U
  4497. #define MRV_SRSZ_SCALE_HC_UP_SHIFT 5U
  4498. /*! Slice: scale_hy_up:*/
  4499. /*! 1: horizontal luminance upscaling selected */
  4500. /* 0: horizontal luminance downscaling selected */
  4501. #define MRV_SRSZ_SCALE_HY_UP
  4502. #define MRV_SRSZ_SCALE_HY_UP_MASK 0x00000010U
  4503. #define MRV_SRSZ_SCALE_HY_UP_SHIFT 4U
  4504. /*! Slice: scale_vc_enable:*/
  4505. /*! 0: bypass vertical chrominance scaling unit */
  4506. /* 1: enable vertical chrominance scaling unit */
  4507. #define MRV_SRSZ_SCALE_VC_ENABLE
  4508. #define MRV_SRSZ_SCALE_VC_ENABLE_MASK 0x00000008U
  4509. #define MRV_SRSZ_SCALE_VC_ENABLE_SHIFT 3U
  4510. /*! Slice: scale_vy_enable:*/
  4511. /*! 0: bypass vertical luminance scaling unit */
  4512. /* 1: enable vertical luminance scaling unit */
  4513. #define MRV_SRSZ_SCALE_VY_ENABLE
  4514. #define MRV_SRSZ_SCALE_VY_ENABLE_MASK 0x00000004U
  4515. #define MRV_SRSZ_SCALE_VY_ENABLE_SHIFT 2U
  4516. /*! Slice: scale_hc_enable:*/
  4517. /*! 0: bypass horizontal chrominance scaling unit */
  4518. /* 1: enable horizontal chrominance scaling unit */
  4519. #define MRV_SRSZ_SCALE_HC_ENABLE
  4520. #define MRV_SRSZ_SCALE_HC_ENABLE_MASK 0x00000002U
  4521. #define MRV_SRSZ_SCALE_HC_ENABLE_SHIFT 1U
  4522. /*! Slice: scale_hy_enable:*/
  4523. /*! 0: bypass horizontal luminance scaling unit */
  4524. /* 1: enable horizontal luminance scaling unit */
  4525. #define MRV_SRSZ_SCALE_HY_ENABLE
  4526. #define MRV_SRSZ_SCALE_HY_ENABLE_MASK 0x00000001U
  4527. #define MRV_SRSZ_SCALE_HY_ENABLE_SHIFT 0U
  4528. /*! Register: srsz_scale_hy: horizontal luminance scale factor register (0x00000004)*/
  4529. /*! Slice: scale_hy:*/
  4530. /*! This register is set to the horizontal luminance downscale factor or to the reciprocal of the horizontal luminance upscale factor */
  4531. #define MRV_SRSZ_SCALE_HY
  4532. #define MRV_SRSZ_SCALE_HY_MASK 0x0000FFFFU
  4533. #define MRV_SRSZ_SCALE_HY_SHIFT 0U
  4534. /*! Register: srsz_scale_hcb: horizontal chrominance scale factor register (0x00000008)*/
  4535. /*! Slice: scale_hcb:*/
  4536. /*! This register is set to the horizontal Cb downscale factor or to the reciprocal of the horizontal Cb upscale factor */
  4537. #define MRV_SRSZ_SCALE_HCB
  4538. #define MRV_SRSZ_SCALE_HCB_MASK 0x0000FFFFU
  4539. #define MRV_SRSZ_SCALE_HCB_SHIFT 0U
  4540. /*! Register: srsz_scale_hcr: horizontal chrominance scale factor register (0x0000000c)*/
  4541. /*! Slice: scale_hcr:*/
  4542. /*! This register is set to the horizontal Cr downscale factor or to the reciprocal of the horizontal Cr upscale factor */
  4543. #define MRV_SRSZ_SCALE_HCR
  4544. #define MRV_SRSZ_SCALE_HCR_MASK 0x0000FFFFU
  4545. #define MRV_SRSZ_SCALE_HCR_SHIFT 0U
  4546. /*! Register: srsz_scale_vy: vertical luminance scale factor register (0x00000010)*/
  4547. /*! Slice: scale_vy:*/
  4548. /*! This register is set to the vertical luminance downscale factor or to the reciprocal of the vertical luminance upscale factor */
  4549. #define MRV_SRSZ_SCALE_VY
  4550. #define MRV_SRSZ_SCALE_VY_MASK 0x0000FFFFU
  4551. #define MRV_SRSZ_SCALE_VY_SHIFT 0U
  4552. /*! Register: srsz_scale_vc: vertical chrominance scale factor register (0x00000014)*/
  4553. /*! Slice: scale_vc:*/
  4554. /*! This register is set to the vertical chrominance downscale factor or to the reciprocal of the vertical chrominance upscale factor */
  4555. #define MRV_SRSZ_SCALE_VC
  4556. #define MRV_SRSZ_SCALE_VC_MASK 0x0000FFFFU
  4557. #define MRV_SRSZ_SCALE_VC_SHIFT 0U
  4558. /*! Register: srsz_phase_hy: horizontal luminance phase register (0x00000018)*/
  4559. /*! Slice: phase_hy:*/
  4560. /*! This register is set to the horizontal luminance phase offset */
  4561. #define MRV_SRSZ_PHASE_HY
  4562. #define MRV_SRSZ_PHASE_HY_MASK 0x0000FFFFU
  4563. #define MRV_SRSZ_PHASE_HY_SHIFT 0U
  4564. /*! Register: srsz_phase_hc: horizontal chrominance phase register (0x0000001c)*/
  4565. /*! Slice: phase_hc:*/
  4566. /*! This register is set to the horizontal chrominance phase offset */
  4567. #define MRV_SRSZ_PHASE_HC
  4568. #define MRV_SRSZ_PHASE_HC_MASK 0x0000FFFFU
  4569. #define MRV_SRSZ_PHASE_HC_SHIFT 0U
  4570. /*! Register: srsz_phase_vy: vertical luminance phase register (0x00000020)*/
  4571. /*! Slice: phase_vy:*/
  4572. /*! This register is set to the vertical luminance phase offset */
  4573. #define MRV_SRSZ_PHASE_VY
  4574. #define MRV_SRSZ_PHASE_VY_MASK 0x0000FFFFU
  4575. #define MRV_SRSZ_PHASE_VY_SHIFT 0U
  4576. /*! Register: srsz_phase_vc: vertical chrominance phase register (0x00000024)*/
  4577. /*! Slice: phase_vc:*/
  4578. /*! This register is set to the vertical chrominance phase offset */
  4579. #define MRV_SRSZ_PHASE_VC
  4580. #define MRV_SRSZ_PHASE_VC_MASK 0x0000FFFFU
  4581. #define MRV_SRSZ_PHASE_VC_SHIFT 0U
  4582. /*! Register: srsz_scale_lut_addr: Address pointer of up-scaling look up table (0x00000028)*/
  4583. /*! Slice: scale_lut_addr:*/
  4584. /*! Pointer to entry of lookup table */
  4585. #define MRV_SRSZ_SCALE_LUT_ADDR
  4586. #define MRV_SRSZ_SCALE_LUT_ADDR_MASK 0x0000003FU
  4587. #define MRV_SRSZ_SCALE_LUT_ADDR_SHIFT 0U
  4588. /*! Register: srsz_scale_lut: Entry of up-scaling look up table (0x0000002c)*/
  4589. /*! Slice: scale_lut:*/
  4590. /*! Entry of lookup table at position scale_lut_addr. The lookup table must be filled with appropriate values before the up-scaling functionality can be used.*/
  4591. #define MRV_SRSZ_SCALE_LUT
  4592. #define MRV_SRSZ_SCALE_LUT_MASK 0x0000003FU
  4593. #define MRV_SRSZ_SCALE_LUT_SHIFT 0U
  4594. /*! Register: srsz_ctrl_shd: global control shadow register (0x00000030)*/
  4595. /*! Slice: scale_vc_up_shd:*/
  4596. /*! 1: vertical chrominance upscaling selected */
  4597. /* 0: vertical chrominance downscaling selected */
  4598. #define MRV_SRSZ_SCALE_VC_UP_SHD
  4599. #define MRV_SRSZ_SCALE_VC_UP_SHD_MASK 0x00000080U
  4600. #define MRV_SRSZ_SCALE_VC_UP_SHD_SHIFT 7U
  4601. /*! Slice: scale_vy_up_shd:*/
  4602. /*! 1: vertical luminance upscaling selected */
  4603. /* 0: vertical luminance downscaling selected */
  4604. #define MRV_SRSZ_SCALE_VY_UP_SHD
  4605. #define MRV_SRSZ_SCALE_VY_UP_SHD_MASK 0x00000040U
  4606. #define MRV_SRSZ_SCALE_VY_UP_SHD_SHIFT 6U
  4607. /*! Slice: scale_hc_up_shd:*/
  4608. /*! 1: horizontal chrominance upscaling selected */
  4609. /* 0: horizontal chrominance downscaling selected */
  4610. #define MRV_SRSZ_SCALE_HC_UP_SHD
  4611. #define MRV_SRSZ_SCALE_HC_UP_SHD_MASK 0x00000020U
  4612. #define MRV_SRSZ_SCALE_HC_UP_SHD_SHIFT 5U
  4613. /*! Slice: scale_hy_up_shd:*/
  4614. /*! 1: horizontal luminance upscaling selected */
  4615. /* 0: horizontal luminance downscaling selected */
  4616. #define MRV_SRSZ_SCALE_HY_UP_SHD
  4617. #define MRV_SRSZ_SCALE_HY_UP_SHD_MASK 0x00000010U
  4618. #define MRV_SRSZ_SCALE_HY_UP_SHD_SHIFT 4U
  4619. /*! Slice: scale_vc_enable_shd:*/
  4620. /*! 0: bypass vertical chrominance scaling unit */
  4621. /* 1: enable vertical chrominance scaling unit */
  4622. #define MRV_SRSZ_SCALE_VC_ENABLE_SHD
  4623. #define MRV_SRSZ_SCALE_VC_ENABLE_SHD_MASK 0x00000008U
  4624. #define MRV_SRSZ_SCALE_VC_ENABLE_SHD_SHIFT 3U
  4625. /*! Slice: scale_vy_enable_shd:*/
  4626. /*! 0: bypass vertical luminance scaling unit */
  4627. /* 1: enable vertical luminance scaling unit */
  4628. #define MRV_SRSZ_SCALE_VY_ENABLE_SHD
  4629. #define MRV_SRSZ_SCALE_VY_ENABLE_SHD_MASK 0x00000004U
  4630. #define MRV_SRSZ_SCALE_VY_ENABLE_SHD_SHIFT 2U
  4631. /*! Slice: scale_hc_enable_shd:*/
  4632. /*! 0: bypass horizontal chrominance scaling unit */
  4633. /* 1: enable horizontal chrominance scaling unit */
  4634. #define MRV_SRSZ_SCALE_HC_ENABLE_SHD
  4635. #define MRV_SRSZ_SCALE_HC_ENABLE_SHD_MASK 0x00000002U
  4636. #define MRV_SRSZ_SCALE_HC_ENABLE_SHD_SHIFT 1U
  4637. /*! Slice: scale_hy_enable_shd:*/
  4638. /*! 0: bypass horizontal luminance scaling unit */
  4639. /* 1: enable horizontal luminance scaling unit */
  4640. #define MRV_SRSZ_SCALE_HY_ENABLE_SHD
  4641. #define MRV_SRSZ_SCALE_HY_ENABLE_SHD_MASK 0x00000001U
  4642. #define MRV_SRSZ_SCALE_HY_ENABLE_SHD_SHIFT 0U
  4643. /*! Register: srsz_scale_hy_shd: horizontal luminance scale factor shadow register (0x00000034)*/
  4644. /*! Slice: scale_hy_shd:*/
  4645. /*! This register is set to the horizontal luminance downscale factor or to the reciprocal of the horizontal luminance upscale factor */
  4646. #define MRV_SRSZ_SCALE_HY_SHD
  4647. #define MRV_SRSZ_SCALE_HY_SHD_MASK 0x0000FFFFU
  4648. #define MRV_SRSZ_SCALE_HY_SHD_SHIFT 0U
  4649. /*! Register: srsz_scale_hcb_shd: horizontal Cb scale factor shadow register (0x00000038)*/
  4650. /*! Slice: scale_hcb_shd:*/
  4651. /*! This register is set to the horizontal Cb downscale factor or to the reciprocal of the horizontal Cb upscale factor */
  4652. #define MRV_SRSZ_SCALE_HCB_SHD
  4653. #define MRV_SRSZ_SCALE_HCB_SHD_MASK 0x0000FFFFU
  4654. #define MRV_SRSZ_SCALE_HCB_SHD_SHIFT 0U
  4655. /*! Register: srsz_scale_hcr_shd: horizontal Cr scale factor shadow register (0x0000003c)*/
  4656. /*! Slice: scale_hcr_shd:*/
  4657. /*! This register is set to the horizontal r downscale factor or to the reciprocal of the horizontal r upscale factor */
  4658. #define MRV_SRSZ_SCALE_HCR_SHD
  4659. #define MRV_SRSZ_SCALE_HCR_SHD_MASK 0x0000FFFFU
  4660. #define MRV_SRSZ_SCALE_HCR_SHD_SHIFT 0U
  4661. /*! Register: srsz_scale_vy_shd: vertical luminance scale factor shadow register (0x00000040)*/
  4662. /*! Slice: scale_vy_shd:*/
  4663. /*! This register is set to the vertical luminance downscale factor or to the reciprocal of the vertical luminance upscale factor */
  4664. #define MRV_SRSZ_SCALE_VY_SHD
  4665. #define MRV_SRSZ_SCALE_VY_SHD_MASK 0x0000FFFFU
  4666. #define MRV_SRSZ_SCALE_VY_SHD_SHIFT 0U
  4667. /*! Register: srsz_scale_vc_shd: vertical chrominance scale factor shadow register (0x00000044)*/
  4668. /*! Slice: scale_vc_shd:*/
  4669. /*! This register is set to the vertical chrominance downscale factor or to the reciprocal of the vertical chrominance upscale factor */
  4670. #define MRV_SRSZ_SCALE_VC_SHD
  4671. #define MRV_SRSZ_SCALE_VC_SHD_MASK 0x0000FFFFU
  4672. #define MRV_SRSZ_SCALE_VC_SHD_SHIFT 0U
  4673. /*! Register: srsz_phase_hy_shd: horizontal luminance phase shadow register (0x00000048)*/
  4674. /*! Slice: phase_hy_shd:*/
  4675. /*! This register is set to the horizontal luminance phase offset */
  4676. #define MRV_SRSZ_PHASE_HY_SHD
  4677. #define MRV_SRSZ_PHASE_HY_SHD_MASK 0x0000FFFFU
  4678. #define MRV_SRSZ_PHASE_HY_SHD_SHIFT 0U
  4679. /*! Register: srsz_phase_hc_shd: horizontal chrominance phase shadow register (0x0000004c)*/
  4680. /*! Slice: phase_hc_shd:*/
  4681. /*! This register is set to the horizontal chrominance phase offset */
  4682. #define MRV_SRSZ_PHASE_HC_SHD
  4683. #define MRV_SRSZ_PHASE_HC_SHD_MASK 0x0000FFFFU
  4684. #define MRV_SRSZ_PHASE_HC_SHD_SHIFT 0U
  4685. /*! Register: srsz_phase_vy_shd: vertical luminance phase shadow register (0x00000050)*/
  4686. /*! Slice: phase_vy_shd:*/
  4687. /*! This register is set to the vertical luminance phase offset */
  4688. #define MRV_SRSZ_PHASE_VY_SHD
  4689. #define MRV_SRSZ_PHASE_VY_SHD_MASK 0x0000FFFFU
  4690. #define MRV_SRSZ_PHASE_VY_SHD_SHIFT 0U
  4691. /*! Register: srsz_phase_vc_shd: vertical chrominance phase shadow register (0x00000054)*/
  4692. /*! Slice: phase_vc_shd:*/
  4693. /*! This register is set to the vertical chrominance phase offset */
  4694. #define MRV_SRSZ_PHASE_VC_SHD
  4695. #define MRV_SRSZ_PHASE_VC_SHD_MASK 0x0000FFFFU
  4696. #define MRV_SRSZ_PHASE_VC_SHD_SHIFT 0U
  4697. /*! Register: mi_ctrl: Global control register (0x00000000)*/
  4698. /*! Slice: sp_output_format:*/
  4699. /*! Selects output format of self picture. For possible restrictions see sub-chapter "Picture Orientation" in chapter "Self Path Output Programming".*/
  4700. /**/
  4701. /* 111: reserved */
  4702. /* 110: RGB 888 */
  4703. /* 101: RGB 666 */
  4704. /* 100: RGB 565 */
  4705. /**/
  4706. /* 011: YCbCr 4:4:4 */
  4707. /* 010: YCbCr 4:2:2 */
  4708. /* 001: YCbCr 4:2:0 */
  4709. /* 000: YCbCr 4:0:0 */
  4710. /**/
  4711. /* Note:*/
  4712. /* - Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
  4713. /* - for RGB output format the SP input format must be YCbCr 4:2:2 */
  4714. #define MRV_MI_SP_OUTPUT_FORMAT
  4715. #define MRV_MI_SP_OUTPUT_FORMAT_MASK 0x70000000U
  4716. #define MRV_MI_SP_OUTPUT_FORMAT_SHIFT 28U
  4717. /*! Slice: sp_input_format:*/
  4718. /*! Selects input format of self picture. For possible restrictions see sub-chapter "Picture Orientation" in chapter "Self Path Output Programming".*/
  4719. /**/
  4720. /* 11: YCbCr 4:4:4 */
  4721. /* 10: YCbCr 4:2:2 */
  4722. /* 01: YCbCr 4:2:0 */
  4723. /* 00: YCbCr 4:0:0 */
  4724. /**/
  4725. /* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
  4726. #define MRV_MI_SP_INPUT_FORMAT
  4727. #define MRV_MI_SP_INPUT_FORMAT_MASK 0x0C000000U
  4728. #define MRV_MI_SP_INPUT_FORMAT_SHIFT 26U
  4729. /*! Slice: sp_write_format:*/
  4730. /*! defines how YCbCr self picture data is written to memory.*/
  4731. /* Must be set to 00 if RGB conversion is active. Note that with RGB conversion active the output format is always interleaved.*/
  4732. /**/
  4733. /* 00: planar */
  4734. /* 01: semi planar, for YCbCr 4:2:x */
  4735. /* 10: interleaved (combined), for YCbCr 4:2:2 only */
  4736. /* 11: reserved */
  4737. /**/
  4738. /* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
  4739. #define MRV_MI_SP_WRITE_FORMAT
  4740. #define MRV_MI_SP_WRITE_FORMAT_MASK 0x03000000U
  4741. #define MRV_MI_SP_WRITE_FORMAT_SHIFT 24U
  4742. /*! Slice: mp_write_format:*/
  4743. /*! Defines how YCbCr main picture data is written to memory. Ignored if JPEG data is chosen.*/
  4744. /* In YCbCr mode the following meaning is applicable */
  4745. /* 00: planar */
  4746. /* 01: semi planar, for YCbCr 4:2:x */
  4747. /* 10: interleaved (combined), for YCbCr 4:2:2 only */
  4748. /* 11: reserved */
  4749. /* In RAW data mode the following meaning is applicable */
  4750. /* 00: RAW 8 bit */
  4751. /* 01: reserved */
  4752. /* 10: RAW 12 bit */
  4753. /* 11: reserved */
  4754. /* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the main path.*/
  4755. #define MRV_MI_MP_WRITE_FORMAT
  4756. #define MRV_MI_MP_WRITE_FORMAT_MASK 0x00C00000U
  4757. #define MRV_MI_MP_WRITE_FORMAT_SHIFT 22U
  4758. /*! Slice: init_offset_en:*/
  4759. /*! Enables updating of the offset counters shadow registers for main and self picture to the programmed register init values.*/
  4760. /* MI_MP/SP_Y/CB/CR_OFFS_CNT_INIT */
  4761. /* -> MI_MP/SP_Y/CB/CR_OFFS_CNT_SHD */
  4762. /* The update will be executed either when a forced software update occurs (in register MI_INIT bit cfg_upd = 1) or when an automatic config update signal arrives at the MI input port. The latter is split into main and self picture. So only the corresponding main/self shadow registers are affected.*/
  4763. /* After a picture skip has been performed init_offset_en selects between skip restart and skip init mode (see bit skip in register MI_INIT).*/
  4764. #define MRV_MI_INIT_OFFSET_EN
  4765. #define MRV_MI_INIT_OFFSET_EN_MASK 0x00200000U
  4766. #define MRV_MI_INIT_OFFSET_EN_SHIFT 21U
  4767. /*! Slice: init_base_en:*/
  4768. /*! Enables updating of the base address and buffer size shadow registers for main and self picture to the programmed register init values.*/
  4769. /* MI_MP/SP_Y/CB/CR_BASE_AD_INIT */
  4770. /* -> MI_MP/SP_Y/CB/CR_BASE_AD_SHD */
  4771. /* MI_MP/SP_Y/CB/CR_SIZE_INIT */
  4772. /* -> MI_MP/SP_Y/CB/CR_SIZE_SHD */
  4773. /* The update will be executed either when a forced software update occurs (in register MI_INIT bit cfg_upd = 1) or when an automatic config update signal arrives at the MI input port. The latter is split into main and self picture. So only the corresponding main/self shadow registers are affected.*/
  4774. #define MRV_MI_INIT_BASE_EN
  4775. #define MRV_MI_INIT_BASE_EN_MASK 0x00100000U
  4776. #define MRV_MI_INIT_BASE_EN_SHIFT 20U
  4777. /*! Slice: burst_len_chrom:*/
  4778. /*! Burst length for Cb or Cr data affecting write port.*/
  4779. /* 00: 4-beat bursts */
  4780. /* 01: 8-beat bursts */
  4781. /* 10: 16-beat bursts */
  4782. /* 11: reserved */
  4783. /* Ignored if 8- or 16-beat bursts are not supported. If rotation is active, then only 4-beat bursts will be generated in self path, regardless of the setting here.*/
  4784. /* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the main and self path.*/
  4785. #define MRV_MI_BURST_LEN_CHROM
  4786. #define MRV_MI_BURST_LEN_CHROM_MASK 0x000C0000U
  4787. #define MRV_MI_BURST_LEN_CHROM_SHIFT 18U
  4788. /*! Slice: burst_len_lum:*/
  4789. /*! Burst length for Y, JPEG, or raw data affecting write port.*/
  4790. /* 00: 4-beat bursts */
  4791. /* 01: 8-beat bursts */
  4792. /* 10: 16-beat bursts */
  4793. /* 11: reserved */
  4794. /* Ignored if 8- or 16-beat bursts are not supported.*/
  4795. /* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the main and self path.*/
  4796. #define MRV_MI_BURST_LEN_LUM
  4797. #define MRV_MI_BURST_LEN_LUM_MASK 0x00030000U
  4798. #define MRV_MI_BURST_LEN_LUM_SHIFT 16U
  4799. /*! Slice: last_pixel_sig_en:*/
  4800. /*! enables the last pixel signalization */
  4801. /* 1: enabled */
  4802. /* 0: disabled */
  4803. #define MRV_MI_LAST_PIXEL_SIG_EN
  4804. #define MRV_MI_LAST_PIXEL_SIG_EN_MASK 0x00008000U
  4805. #define MRV_MI_LAST_PIXEL_SIG_EN_SHIFT 15U
  4806. /*! Slice: sp_auto_update:*/
  4807. /*! automatic update of configuration registers for self path at frame end.*/
  4808. /* 1: enabled */
  4809. /* 0: disabled */
  4810. #define MRV_MI_SP_AUTO_UPDATE
  4811. #define MRV_MI_SP_AUTO_UPDATE_MASK 0x00004000U
  4812. #define MRV_MI_SP_AUTO_UPDATE_SHIFT 14U
  4813. /*! Slice: mp_auto_update:*/
  4814. /*! automatic update of configuration registers for main path at frame end.*/
  4815. /* 1: enabled */
  4816. /* 0: disabled */
  4817. #define MRV_MI_MP_AUTO_UPDATE
  4818. #define MRV_MI_MP_AUTO_UPDATE_MASK 0x00002000U
  4819. #define MRV_MI_MP_AUTO_UPDATE_SHIFT 13U
  4820. /*! Slice: sp_pingpong_enable:*/
  4821. /*! pingpong mode of configuration registers for self path at frame end.*/
  4822. /* 1: enabled */
  4823. /* 0: disabled */
  4824. #define MRV_MI_SP_PINGPONG_ENABLE
  4825. #define MRV_MI_SP_PINGPONG_ENABLE_MASK 0x00001000U
  4826. #define MRV_MI_SP_PINGPONG_ENABLE_SHIFT 12U
  4827. /*! Slice: mp_pingpong_enable:*/
  4828. /*! pingpong mode of configuration registers for main path at frame end.*/
  4829. /* 1: enabled */
  4830. /* 0: disabled */
  4831. #define MRV_MI_MP_PINGPONG_ENABLE
  4832. #define MRV_MI_MP_PINGPONG_ENABLE_MASK 0x00000800U
  4833. #define MRV_MI_MP_PINGPONG_ENABLE_SHIFT 11U
  4834. /*! Slice: 422noncosited:*/
  4835. /*! Enables self path YCbCr422non-co-sited -> YCbCr444 interpolation */
  4836. /* (M5_v6, M5_v7 only)*/
  4837. /* 1: YCbCr422 data are non_co-sited (Cb and Cr samples are centered between Y samples) so modified interpolation is activated */
  4838. /* 0: YCbCr422 data are co-sited (Y0 Cb0 and Cr0 are sampled at the same position)*/
  4839. /* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
  4840. #define MRV_MI_422NONCOSITED
  4841. #define MRV_MI_422NONCOSITED_MASK 0x00000400U
  4842. #define MRV_MI_422NONCOSITED_SHIFT 10U
  4843. /*! Slice: cbcr_full_range:*/
  4844. /*! Enables CbCr full range for self path YCbCr -> RGB conversion */
  4845. /* (M5_v6, M5_v7 only)*/
  4846. /* 1: CbCr have full range (0..255)*/
  4847. /* 0: CbCr have compressed range range (16..240)*/
  4848. /* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
  4849. #define MRV_MI_CBCR_FULL_RANGE
  4850. #define MRV_MI_CBCR_FULL_RANGE_MASK 0x00000200U
  4851. #define MRV_MI_CBCR_FULL_RANGE_SHIFT 9U
  4852. /*! Slice: y_full_range:*/
  4853. /*! Enables Y full range for self path YCbCr -> RGB conversion */
  4854. /* (M5_v6, M5_v7 only)*/
  4855. /* 1: Y has full range (0..255)*/
  4856. /* 0: Y has compressed range (16..235)*/
  4857. /* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
  4858. #define MRV_MI_Y_FULL_RANGE
  4859. #define MRV_MI_Y_FULL_RANGE_MASK 0x00000100U
  4860. #define MRV_MI_Y_FULL_RANGE_SHIFT 8U
  4861. /*! Slice: byte_swap:*/
  4862. /*! Enables change of byte order of the 32 bit output word at write port */
  4863. /* 1: byte order is mirrored but the bit order within one byte doesn’t change */
  4864. /* 0: no byte mirroring */
  4865. /* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the main and self path.*/
  4866. #define MRV_MI_BYTE_SWAP
  4867. #define MRV_MI_BYTE_SWAP_MASK 0x00000080U
  4868. #define MRV_MI_BYTE_SWAP_SHIFT 7U
  4869. /*! Slice: rot:*/
  4870. /*! Rotation 90 degree counter clockwise of self picture, only in RGB mode. For picture orientation and operation modes see sub-chapter "Picture Orientation" in chapter "Self Path Output Programming".*/
  4871. /* For RGB 565 format the line length must be a multiple of 2. There are no restrictions for RGB 888/666.*/
  4872. /* 1: enabled */
  4873. /* 0: disabled */
  4874. /* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path. In rotation mode only 4-beat bursts are supported for self-path.*/
  4875. #define MRV_MI_ROT
  4876. #define MRV_MI_ROT_MASK 0x00000040U
  4877. #define MRV_MI_ROT_SHIFT 6U
  4878. /*! Slice: v_flip:*/
  4879. /*! Vertical flipping of self picture. For picture orientation and operation modes see sub-chapter "Picture Orientation" in chapter "Self Path Output Programming".*/
  4880. /* For Y component the line length in 4:2:x planar mode must be a multiple of 8, for all other component modes a multiple of 4 and for RGB 565 a multiple of 2. There are no restrictions for RGB 888/666.*/
  4881. /* 1: enabled */
  4882. /* 0: disabled */
  4883. /* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
  4884. #define MRV_MI_V_FLIP
  4885. #define MRV_MI_V_FLIP_MASK 0x00000020U
  4886. #define MRV_MI_V_FLIP_SHIFT 5U
  4887. /*! Slice: h_flip:*/
  4888. /*! Horizontal flipping of self picture. For picture orientation and operation modes see sub-chapter "Picture Orientation" in chapter "Self Path Output Programming".*/
  4889. /* For Y component the line length in 4:2:x planar mode must be a multiple of 8, for all other component modes a multiple of 4 and for RGB 565 a multiple of 2. There are no restrictions for RGB 888/666.*/
  4890. /* 1: enabled */
  4891. /* 0: disabled */
  4892. /* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
  4893. #define MRV_MI_H_FLIP
  4894. #define MRV_MI_H_FLIP_MASK 0x00000010U
  4895. #define MRV_MI_H_FLIP_SHIFT 4U
  4896. /*! Slice: path_enable:*/
  4897. /*! Enables data pathes of MI according to the following table:*/
  4898. /**/
  4899. /* 0000: disabled, no data is transferred */
  4900. /* 0001: YUV data output, mainpath only (mp_enable only)*/
  4901. /* 0010: self-path only, output data format depending on other settings (sp_enable only)*/
  4902. /* 0011: YUV data output in mainpath and self-path image data active */
  4903. /* 0100: JPEG data output, mainpath only (jpeg_enable only)*/
  4904. /* 0101: not allowed */
  4905. /* 0110: JPEG data output in mainpath and self-path image data active */
  4906. /* 0111: not allowed */
  4907. /* 1000: RAW data output, mainpath only (raw_enable only)*/
  4908. /* 1001: defect pixel data on self-path, image data on mainpath */
  4909. /* 1010: defect pixel data on mainpath, image data on self-path */
  4910. /* 1011: not allowed */
  4911. /* 1100: defect pixel data on self-path, JPEG data on mainpath */
  4912. /* 1101: defect pixel data on mainpath only */
  4913. /* 1110: defect pixel data on self-path only */
  4914. /* 1111: defect pixel data on self-path, RAW data on mainpath */
  4915. /**/
  4916. /* Programmed value becomes effective (visible in shadow register) after a soft reset, a forced software update or an automatic config update. Affects MI_IN and MI_OUT module.*/
  4917. #define MRV_MI_PATH_ENABLE
  4918. #define MRV_MI_PATH_ENABLE_MASK 0x0000000FU
  4919. #define MRV_MI_PATH_ENABLE_SHIFT 0U
  4920. /*! Register: mi_init: Control register for address init and skip function (0x00000004)*/
  4921. /*! Slice: mi_output_format */
  4922. #define MRV_MI_MP_OUTPUT_FORMAT
  4923. #define MRV_MI_MP_OUTPUT_FORMAT_MASK 0x000001E0U
  4924. #define MRV_MI_MP_OUTPUT_FORMAT_SHIFT 5U
  4925. /*! Slice: mi_cfg_upd:*/
  4926. /*! Forced configuration update. Leads to an immediate update of the shadow registers.*/
  4927. /* Depending on the two init enable bits in the MI_CTRL register (init_offset_en and init_base_en) the offset counter, base address and buffer size shadow registers are also updated.*/
  4928. #define MRV_MI_MI_CFG_UPD
  4929. #define MRV_MI_MI_CFG_UPD_MASK 0x00000010U
  4930. #define MRV_MI_MI_CFG_UPD_SHIFT 4U
  4931. /*! Slice: mi_skip:*/
  4932. /*! Skip of current or next starting main picture:*/
  4933. /* Aborts writing of main picture image data of the current frame to RAM (after the current burst transmission has been completed). Further main picture data up to the end of the current frame are discarded.*/
  4934. /**/
  4935. /* No further makroblock line interrupt (mblk_line), no wrap around interrupt for main picture (wrap_mp_y/cb/cr) and no fill level interrupt (fill_mp_y) are generated.*/
  4936. /**/
  4937. /* Skip does not affect the generation of the main path frame end interrupt (mp_frame_end).*/
  4938. /* Skip does not affect the processing of self picture and its corresponding interrupts namely the self path frame end interrupt (sp_frame_end).*/
  4939. /**/
  4940. /* The byte counter (register MI_BYTE_CNT) is not affected. It produces the correct number of JPEG or RAW data bytes at the end of the current (skipped) frame.*/
  4941. /**/
  4942. /* After a skip has been performed the offset counter for the main picture at the start of the following frame are set depending on the bit init_offset_en in register MI_CTRL:*/
  4943. /**/
  4944. /* - Skip restart mode (init_offset_en = 0)*/
  4945. /* The offset counters of the main picture are restarted at the old start values of the previous skipped frame.*/
  4946. /**/
  4947. /* - Skip init mode (init_offset_en = 1)*/
  4948. /* The offset counters of the main picture are initialized with the register contents of the offset counter init registers without any additional forced software update or automatic config update.*/
  4949. #define MRV_MI_MI_SKIP
  4950. #define MRV_MI_MI_SKIP_MASK 0x00000004U
  4951. #define MRV_MI_MI_SKIP_SHIFT 2U
  4952. /*! Register: mi_mp_y_base_ad_init: Base address for main picture Y component, JPEG or raw data (0x00000008)*/
  4953. /*! Slice: mp_y_base_ad_init:*/
  4954. /*! Base address of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/
  4955. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  4956. #ifdef ISP_MP_34BIT
  4957. #define MRV_MI_MP_Y_BASE_AD_INIT
  4958. #define MRV_MI_MP_Y_BASE_AD_INIT_MASK 0xFFFFFFFEU
  4959. #define MRV_MI_MP_Y_BASE_AD_INIT_SHIFT 1U
  4960. #else
  4961. #define MRV_MI_MP_Y_BASE_AD_INIT
  4962. #define MRV_MI_MP_Y_BASE_AD_INIT_MASK 0xFFFFFFF8U
  4963. #define MRV_MI_MP_Y_BASE_AD_INIT_SHIFT 3U
  4964. #endif
  4965. /*! Register: mi_mp_y_size_init: Size of main picture Y component, JPEG or raw data (0x0000000c)*/
  4966. /*! Slice: mp_y_size_init:*/
  4967. /*! Size of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/
  4968. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  4969. #define MRV_MI_MP_Y_SIZE_INIT
  4970. #define MRV_MI_MP_Y_SIZE_INIT_MASK 0x1FFFFFF8U
  4971. #define MRV_MI_MP_Y_SIZE_INIT_SHIFT 3U
  4972. /*! Register: mi_mp_y_offs_cnt_init: Offset counter init value for main picture Y, JPEG or raw data (0x00000010)*/
  4973. /*! Slice: mp_y_offs_cnt_init:*/
  4974. /*! Offset counter init value of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/
  4975. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  4976. #define MRV_MI_MP_Y_OFFS_CNT_INIT
  4977. #define MRV_MI_MP_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF8U
  4978. #define MRV_MI_MP_Y_OFFS_CNT_INIT_SHIFT 3U
  4979. /*! Register: mi_mp_y_offs_cnt_start: Offset counter start value for main picture Y, JPEG or raw data (0x00000014)*/
  4980. /*! Slice: mp_y_offs_cnt_start:*/
  4981. /*! Offset counter value which points to the start address of the previously processed picture (main picture Y component, JPEG or raw data). Updated at frame end.*/
  4982. /* Note: A soft reset resets the contents to the reset value.*/
  4983. #define MRV_MI_MP_Y_OFFS_CNT_START
  4984. #define MRV_MI_MP_Y_OFFS_CNT_START_MASK 0x1FFFFFF8U
  4985. #define MRV_MI_MP_Y_OFFS_CNT_START_SHIFT 3U
  4986. /*! Register: mi_mp_y_irq_offs_init: Fill level interrupt offset value for main picture Y, JPEG or raw data (0x00000018)*/
  4987. /*! Slice: mp_y_irq_offs_init:*/
  4988. /*! Reaching this programmed value by the current offset counter for addressing main picture Y component, JPEG or raw data leads to generation of fill level interrupt fill_mp_y.*/
  4989. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  4990. #define MRV_MI_MP_Y_IRQ_OFFS_INIT
  4991. #define MRV_MI_MP_Y_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
  4992. #define MRV_MI_MP_Y_IRQ_OFFS_INIT_SHIFT 3U
  4993. /*! Register: mi_mp_cb_base_ad_init: Base address for main picture Cb component ring buffer (0x0000001c)*/
  4994. /*! Slice: mp_cb_base_ad_init:*/
  4995. /*! Base address of main picture Cb component ring buffer.*/
  4996. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  4997. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  4998. #ifdef ISP_MP_34BIT
  4999. #define MRV_MI_MP_CB_BASE_AD_INIT
  5000. #define MRV_MI_MP_CB_BASE_AD_INIT_MASK 0xFFFFFFFEU
  5001. #define MRV_MI_MP_CB_BASE_AD_INIT_SHIFT 1U
  5002. #else
  5003. #define MRV_MI_MP_CB_BASE_AD_INIT
  5004. #define MRV_MI_MP_CB_BASE_AD_INIT_MASK 0xFFFFFFF8U
  5005. #define MRV_MI_MP_CB_BASE_AD_INIT_SHIFT 3U
  5006. #endif
  5007. /*! Register: mi_mp_cb_size_init: Size of main picture Cb component ring buffer (0x00000020)*/
  5008. /*! Slice: mp_cb_size_init:*/
  5009. /*! Size of main picture Cb component ring buffer.*/
  5010. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5011. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5012. #define MRV_MI_MP_CB_SIZE_INIT
  5013. #define MRV_MI_MP_CB_SIZE_INIT_MASK 0x0FFFFFF8U
  5014. #define MRV_MI_MP_CB_SIZE_INIT_SHIFT 3U
  5015. /*! Register: mi_mp_cb_offs_cnt_init: Offset counter init value for main picture Cb component ring buffer (0x00000024)*/
  5016. /*! Slice: mp_cb_offs_cnt_init:*/
  5017. /*! Offset counter init value of main picture Cb component ring buffer.*/
  5018. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5019. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect. Check exceptional handling in skip modes.*/
  5020. #define MRV_MI_MP_CB_OFFS_CNT_INIT
  5021. #define MRV_MI_MP_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF8U
  5022. #define MRV_MI_MP_CB_OFFS_CNT_INIT_SHIFT 3U
  5023. /*! Register: mi_mp_cb_offs_cnt_start: Offset counter start value for main picture Cb component ring buffer (0x00000028)*/
  5024. /*! Slice: mp_cb_offs_cnt_start:*/
  5025. /*! Offset counter value which points to the start address of the previously processed picture (main picture Cb component). Updated at frame end.*/
  5026. #define MRV_MI_MP_CB_OFFS_CNT_START
  5027. #define MRV_MI_MP_CB_OFFS_CNT_START_MASK 0x0FFFFFF8U
  5028. #define MRV_MI_MP_CB_OFFS_CNT_START_SHIFT 3U
  5029. /*! Register: mi_mp_cr_base_ad_init: Base address for main picture Cr component ring buffer (0x0000002c)*/
  5030. /*! Slice: mp_cr_base_ad_init:*/
  5031. /*! Base address of main picture Cr component ring buffer.*/
  5032. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5033. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5034. #ifdef ISP_MP_34BIT
  5035. #define MRV_MI_MP_CR_BASE_AD_INIT
  5036. #define MRV_MI_MP_CR_BASE_AD_INIT_MASK 0xFFFFFFFEU
  5037. #define MRV_MI_MP_CR_BASE_AD_INIT_SHIFT 1U
  5038. #else
  5039. #define MRV_MI_MP_CR_BASE_AD_INIT
  5040. #define MRV_MI_MP_CR_BASE_AD_INIT_MASK 0xFFFFFFF8U
  5041. #define MRV_MI_MP_CR_BASE_AD_INIT_SHIFT 3U
  5042. #endif
  5043. /*! Register: mi_mp_cr_size_init: Size of main picture Cr component ring buffer (0x00000030)*/
  5044. /*! Slice: mp_cr_size_init:*/
  5045. /*! Size of main picture Cr component ring buffer.*/
  5046. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5047. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5048. #define MRV_MI_MP_CR_SIZE_INIT
  5049. #define MRV_MI_MP_CR_SIZE_INIT_MASK 0x0FFFFFF8U
  5050. #define MRV_MI_MP_CR_SIZE_INIT_SHIFT 3U
  5051. /*! Register: mi_mp_cr_offs_cnt_init: Offset counter init value for main picture Cr component ring buffer (0x00000034)*/
  5052. /*! Slice: mp_cr_offs_cnt_init:*/
  5053. /*! Offset counter init value of main picture Cr component ring buffer.*/
  5054. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5055. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect. Check exceptional handling in skip modes.*/
  5056. #define MRV_MI_MP_CR_OFFS_CNT_INIT
  5057. #define MRV_MI_MP_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF8U
  5058. #define MRV_MI_MP_CR_OFFS_CNT_INIT_SHIFT 3U
  5059. /*! Register: mi_mp_cr_offs_cnt_start: Offset counter start value for main picture Cr component ring buffer (0x00000038)*/
  5060. /*! Slice: mp_cr_offs_cnt_start:*/
  5061. /*! Offset counter value which points to the start address of the previously processed picture (main picture Cr component). Updated at frame end.*/
  5062. /* Note: Soft reset will reset the contents to reset value.*/
  5063. #define MRV_MI_MP_CR_OFFS_CNT_START
  5064. #define MRV_MI_MP_CR_OFFS_CNT_START_MASK 0x0FFFFFF8U
  5065. #define MRV_MI_MP_CR_OFFS_CNT_START_SHIFT 3U
  5066. /*! Register: mi_sp_y_base_ad_init: Base address for self picture Y component ring buffer (0x0000003c)*/
  5067. /*! Slice: sp_y_base_ad_init:*/
  5068. /*! Base address of self picture Y component ring buffer.*/
  5069. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5070. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5071. #define MRV_MI_SP_Y_BASE_AD_INIT
  5072. #define MRV_MI_SP_Y_BASE_AD_INIT_MASK 0xFFFFFFF8U
  5073. #define MRV_MI_SP_Y_BASE_AD_INIT_SHIFT 3U
  5074. /*! Register: mi_sp_y_size_init: Size of self picture Y component ring buffer (0x00000040)*/
  5075. /*! Slice: sp_y_size_init:*/
  5076. /*! Size of self picture Y component ring buffer.*/
  5077. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5078. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5079. #define MRV_MI_SP_Y_SIZE_INIT
  5080. #define MRV_MI_SP_Y_SIZE_INIT_MASK 0x1FFFFFF8U
  5081. #define MRV_MI_SP_Y_SIZE_INIT_SHIFT 3U
  5082. /*! Register: mi_sp_y_offs_cnt_init: Offset counter init value for self picture Y component ring buffer (0x00000044)*/
  5083. /*! Slice: sp_y_offs_cnt_init:*/
  5084. /*! Offset counter init value of self picture Y component ring buffer.*/
  5085. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5086. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5087. #define MRV_MI_SP_Y_OFFS_CNT_INIT
  5088. #define MRV_MI_SP_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF8U
  5089. #define MRV_MI_SP_Y_OFFS_CNT_INIT_SHIFT 3U
  5090. /*! Register: mi_sp_y_offs_cnt_start: Offset counter start value for self picture Y component ring buffer (0x00000048)*/
  5091. /*! Slice: sp_y_offs_cnt_start:*/
  5092. /*! Offset counter value which points to the start address of the previously processed picture (self picture Y component). Updated at frame end.*/
  5093. /* Note: Soft reset will reset the contents to reset value.*/
  5094. #define MRV_MI_SP_Y_OFFS_CNT_START
  5095. #define MRV_MI_SP_Y_OFFS_CNT_START_MASK 0x1FFFFFF8U
  5096. #define MRV_MI_SP_Y_OFFS_CNT_START_SHIFT 3U
  5097. /*! Register: mi_sp_y_llength: Line length of self picture Y component (0x0000004c)*/
  5098. /*! Slice: sp_y_llength:*/
  5099. /*! Line length of self picture Y component or RGB picture in pixel, also known as line stride.*/
  5100. /* If no line stride is used, line length must match image width.*/
  5101. /* For Y component the line length in 4:2:x planar mode must be a multiple of 8, for all other component modes a multiple of 4 and for RGB 565 a multiple of 2. There are no restrictions for RGB 888/666.*/
  5102. /* In planar mode the line length of the Cb and Cr component is assumed according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi planar 4:2:x mode the line length of the Cb and Cr component is assumed the same size.*/
  5103. /* Note: Line length always refers to the line length of the output image. This is particularly important when rotating.*/
  5104. /* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
  5105. #define MRV_MI_SP_Y_LLENGTH
  5106. #define MRV_MI_SP_Y_LLENGTH_MASK 0x00007FFFU
  5107. #define MRV_MI_SP_Y_LLENGTH_SHIFT 0U
  5108. /*! Register: mi_sp_cb_base_ad_init: Base address for self picture Cb component ring buffer (0x00000050)*/
  5109. /*! Slice: sp_cb_base_ad_init:*/
  5110. /*! Base address of self picture Cb component ring buffer.*/
  5111. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5112. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5113. #define MRV_MI_SP_CB_BASE_AD_INIT
  5114. #define MRV_MI_SP_CB_BASE_AD_INIT_MASK 0xFFFFFFF8U
  5115. #define MRV_MI_SP_CB_BASE_AD_INIT_SHIFT 3U
  5116. /*! Register: mi_sp_cb_size_init: Size of self picture Cb component ring buffer (0x00000054)*/
  5117. /*! Slice: sp_cb_size_init:*/
  5118. /*! Size of self picture Cb component ring buffer.*/
  5119. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5120. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5121. #define MRV_MI_SP_CB_SIZE_INIT
  5122. #define MRV_MI_SP_CB_SIZE_INIT_MASK 0x0FFFFFF8U
  5123. #define MRV_MI_SP_CB_SIZE_INIT_SHIFT 3U
  5124. /*! Register: mi_sp_cb_offs_cnt_init: Offset counter init value for self picture Cb component ring buffer (0x00000058)*/
  5125. /*! Slice: sp_cb_offs_cnt_init:*/
  5126. /*! Offset counter init value of self picture Cb component ring buffer.*/
  5127. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5128. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5129. #define MRV_MI_SP_CB_OFFS_CNT_INIT
  5130. #define MRV_MI_SP_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF8U
  5131. #define MRV_MI_SP_CB_OFFS_CNT_INIT_SHIFT 3U
  5132. /*! Register: mi_sp_cb_offs_cnt_start: Offset counter start value for self picture Cb component ring buffer (0x0000005c)*/
  5133. /*! Slice: sp_cb_offs_cnt_start:*/
  5134. /*! Offset counter value which points to the start address of the previously processed picture (self picture Cb component). Updated at frame end.*/
  5135. /* Note: Soft reset will reset the contents to reset value.*/
  5136. #define MRV_MI_SP_CB_OFFS_CNT_START
  5137. #define MRV_MI_SP_CB_OFFS_CNT_START_MASK 0x0FFFFFF8U
  5138. #define MRV_MI_SP_CB_OFFS_CNT_START_SHIFT 3U
  5139. /*! Register: mi_sp_cr_base_ad_init: Base address for self picture Cr component ring buffer (0x00000060)*/
  5140. /*! Slice: sp_cr_base_ad_init:*/
  5141. /*! Base address of self picture Cr component ring buffer.*/
  5142. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5143. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5144. #define MRV_MI_SP_CR_BASE_AD_INIT
  5145. #define MRV_MI_SP_CR_BASE_AD_INIT_MASK 0xFFFFFFF8U
  5146. #define MRV_MI_SP_CR_BASE_AD_INIT_SHIFT 3U
  5147. /*! Register: mi_sp_cr_size_init: Size of self picture Cr component ring buffer (0x00000064)*/
  5148. /*! Slice: sp_cr_size_init:*/
  5149. /*! Size of self picture Cr component ring buffer.*/
  5150. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5151. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5152. #define MRV_MI_SP_CR_SIZE_INIT
  5153. #define MRV_MI_SP_CR_SIZE_INIT_MASK 0x0FFFFFF8U
  5154. #define MRV_MI_SP_CR_SIZE_INIT_SHIFT 3U
  5155. /*! Register: mi_sp_cr_offs_cnt_init: Offset counter init value for self picture Cr component ring buffer (0x00000068)*/
  5156. /*! Slice: sp_cr_offs_cnt_init:*/
  5157. /*! Offset counter init value of self picture Cr component ring buffer.*/
  5158. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5159. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5160. #define MRV_MI_SP_CR_OFFS_CNT_INIT
  5161. #define MRV_MI_SP_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF8U
  5162. #define MRV_MI_SP_CR_OFFS_CNT_INIT_SHIFT 3U
  5163. /*! Register: mi_sp_cr_offs_cnt_start: Offset counter start value for self picture Cr component ring buffer (0x0000006c)*/
  5164. /*! Slice: sp_cr_offs_cnt_start:*/
  5165. /*! Offset counter value which points to the start address of the previously processed picture (self picture Cr component). Updated at frame end.*/
  5166. #define MRV_MI_SP_CR_OFFS_CNT_START
  5167. #define MRV_MI_SP_CR_OFFS_CNT_START_MASK 0x0FFFFFF8U
  5168. #define MRV_MI_SP_CR_OFFS_CNT_START_SHIFT 3U
  5169. /*! Register: mi_byte_cnt: Counter value of JPEG or RAW data bytes (0x00000070)*/
  5170. /*! Slice: byte_cnt:*/
  5171. /*! Counter value specifies the number of JPEG or RAW data bytes of the last transmitted frame. Updated at frame end.*/
  5172. /* A soft reset will set the byte counter to zero.*/
  5173. #define MRV_MI_BYTE_CNT
  5174. #define MRV_MI_BYTE_CNT_MASK 0x0FFFFFFFU
  5175. #define MRV_MI_BYTE_CNT_SHIFT 0U
  5176. /*! Register: mi_ctrl_shd: global control internal shadow register (0x00000074)*/
  5177. /*! Slice: path_enable_out:*/
  5178. /*! path_enable shadow register for module MI_OUT (former raw_enable_out, jpeg_enable_out, sp_enable_out, mp_enable_out)*/
  5179. #define MRV_MI_PATH_ENABLE_OUT
  5180. #define MRV_MI_PATH_ENABLE_OUT_MASK 0x000F0000U
  5181. #define MRV_MI_PATH_ENABLE_OUT_SHIFT 16U
  5182. /*! Slice: path_enable_in:*/
  5183. /*! path_enable shadow register for module MI_IN (former raw_enable_in, jpeg_enable_in, sp_enable_in, mp_enable_in)*/
  5184. #define MRV_MI_PATH_ENABLE_IN
  5185. #define MRV_MI_PATH_ENABLE_IN_MASK 0x0000000FU
  5186. #define MRV_MI_PATH_ENABLE_IN_SHIFT 0U
  5187. /*! Register: mi_mp_y_base_ad_shd: Base address shadow register for main picture Y component, JPEG or raw data ring buffer (0x00000078)*/
  5188. /*! Slice: mp_y_base_ad:*/
  5189. /*! Base address of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/
  5190. #define MRV_MI_MP_Y_BASE_AD
  5191. #define MRV_MI_MP_Y_BASE_AD_MASK 0xFFFFFFF8U
  5192. #define MRV_MI_MP_Y_BASE_AD_SHIFT 3U
  5193. /*! Register: mi_mp_y_size_shd: Size shadow register of main picture Y component, JPEG or raw data (0x0000007c)*/
  5194. /*! Slice: mp_y_size:*/
  5195. /*! Size of main picture Y component ring buffer, JPEG ring buffer or raw data ring buffer.*/
  5196. #define MRV_MI_MP_Y_SIZE
  5197. #define MRV_MI_MP_Y_SIZE_MASK 0x1FFFFFF8U
  5198. #define MRV_MI_MP_Y_SIZE_SHIFT 3U
  5199. /*! Register: mi_mp_y_offs_cnt_shd: Current offset counter of main picture Y component, JPEG or raw data ring buffer (0x00000080)*/
  5200. /*! Slice: mp_y_offs_cnt:*/
  5201. /*! Current offset counter of main picture Y component, JPEG or raw data ring buffer for address generation */
  5202. /* Note: Soft reset will reset the contents to reset value.*/
  5203. #define MRV_MI_MP_Y_OFFS_CNT
  5204. #define MRV_MI_MP_Y_OFFS_CNT_MASK 0x1FFFFFF8U
  5205. #define MRV_MI_MP_Y_OFFS_CNT_SHIFT 3U
  5206. /*! Register: mi_mp_y_irq_offs_shd: Shadow register of fill level interrupt offset value for main picture Y component, JPEG or raw data (0x00000084)*/
  5207. /*! Slice: mp_y_irq_offs:*/
  5208. /*! Reaching this offset value by the current offset counter for addressing main picture Y component, JPEG or raw data leads to generation of fill level interrupt fill_mp_y.*/
  5209. #define MRV_MI_MP_Y_IRQ_OFFS
  5210. #define MRV_MI_MP_Y_IRQ_OFFS_MASK 0x1FFFFFF8U
  5211. #define MRV_MI_MP_Y_IRQ_OFFS_SHIFT 3U
  5212. /*! Register: mi_mp_cb_base_ad_shd: Base address shadow register for main picture Cb component ring buffer (0x00000088)*/
  5213. /*! Slice: mp_cb_base_ad:*/
  5214. /*! Base address of main picture Cb component ring buffer.*/
  5215. #define MRV_MI_MP_CB_BASE_AD
  5216. #define MRV_MI_MP_CB_BASE_AD_MASK 0xFFFFFFF8U
  5217. #define MRV_MI_MP_CB_BASE_AD_SHIFT 3U
  5218. /*! Register: mi_mp_cb_size_shd: Size shadow register of main picture Cb component ring buffer (0x0000008c)*/
  5219. /*! Slice: mp_cb_size:*/
  5220. /*! Size of main picture Cb component ring buffer.*/
  5221. #define MRV_MI_MP_CB_SIZE
  5222. #define MRV_MI_MP_CB_SIZE_MASK 0x0FFFFFF8U
  5223. #define MRV_MI_MP_CB_SIZE_SHIFT 3U
  5224. /*! Register: mi_mp_cb_offs_cnt_shd: Current offset counter of main picture Cb component ring buffer (0x00000090)*/
  5225. /*! Slice: mp_cb_offs_cnt:*/
  5226. /*! Current offset counter of main picture Cb component ring buffer for address generation */
  5227. /* Note: Soft reset will reset the contents to reset value.*/
  5228. #define MRV_MI_MP_CB_OFFS_CNT
  5229. #define MRV_MI_MP_CB_OFFS_CNT_MASK 0x0FFFFFF8U
  5230. #define MRV_MI_MP_CB_OFFS_CNT_SHIFT 3U
  5231. /*! Register: mi_mp_cr_base_ad_shd: Base address shadow register for main picture Cr component ring buffer (0x00000094)*/
  5232. /*! Slice: mp_cr_base_ad:*/
  5233. /*! Base address of main picture Cr component ring buffer.*/
  5234. #define MRV_MI_MP_CR_BASE_AD
  5235. #define MRV_MI_MP_CR_BASE_AD_MASK 0xFFFFFFF8U
  5236. #define MRV_MI_MP_CR_BASE_AD_SHIFT 3U
  5237. /*! Register: mi_mp_cr_size_shd: Size shadow register of main picture Cr component ring buffer (0x00000098)*/
  5238. /*! Slice: mp_cr_size:*/
  5239. /*! Size of main picture Cr component ring buffer.*/
  5240. #define MRV_MI_MP_CR_SIZE
  5241. #define MRV_MI_MP_CR_SIZE_MASK 0x0FFFFFF8U
  5242. #define MRV_MI_MP_CR_SIZE_SHIFT 3U
  5243. /*! Register: mi_mp_cr_offs_cnt_shd: Current offset counter of main picture Cr component ring buffer (0x0000009c)*/
  5244. /*! Slice: mp_cr_offs_cnt:*/
  5245. /*! Current offset counter of main picture Cr component ring buffer for address generation */
  5246. /* Note: Soft reset will reset the contents to reset value.*/
  5247. #define MRV_MI_MP_CR_OFFS_CNT
  5248. #define MRV_MI_MP_CR_OFFS_CNT_MASK 0x0FFFFFF8U
  5249. #define MRV_MI_MP_CR_OFFS_CNT_SHIFT 3U
  5250. /*! Register: mi_sp_y_base_ad_shd: Base address shadow register for self picture Y component ring buffer (0x000000a0)*/
  5251. /*! Slice: sp_y_base_ad:*/
  5252. /*! Base address of self picture Y component ring buffer.*/
  5253. #define MRV_MI_SP_Y_BASE_AD
  5254. #define MRV_MI_SP_Y_BASE_AD_MASK 0xFFFFFFF8U
  5255. #define MRV_MI_SP_Y_BASE_AD_SHIFT 3U
  5256. /*! Register: mi_sp_y_size_shd: Size shadow register of self picture Y component ring buffer (0x000000a4)*/
  5257. /*! Slice: sp_y_size:*/
  5258. /*! Size of self picture Y component ring buffer.*/
  5259. #define MRV_MI_SP_Y_SIZE
  5260. #define MRV_MI_SP_Y_SIZE_MASK 0x1FFFFFF8U
  5261. #define MRV_MI_SP_Y_SIZE_SHIFT 3U
  5262. /*! Register: mi_sp_y_offs_cnt_shd: Current offset counter of self picture Y component ring buffer (0x000000a8)*/
  5263. /*! Slice: sp_y_offs_cnt:*/
  5264. /*! Current offset counter of self picture Y component ring buffer for address generation */
  5265. /* Note: Soft reset will reset the contents to reset value.*/
  5266. #define MRV_MI_SP_Y_OFFS_CNT
  5267. #define MRV_MI_SP_Y_OFFS_CNT_MASK 0x1FFFFFF8U
  5268. #define MRV_MI_SP_Y_OFFS_CNT_SHIFT 3U
  5269. /*! Register: mi_sp_cb_base_ad_shd: Base address shadow register for self picture Cb component ring buffer (0x000000b0)*/
  5270. /*! Slice: sp_cb_base_ad:*/
  5271. /*! Base address of self picture Cb component ring buffer.*/
  5272. #define MRV_MI_SP_CB_BASE_AD
  5273. #define MRV_MI_SP_CB_BASE_AD_MASK 0xFFFFFFF8U
  5274. #define MRV_MI_SP_CB_BASE_AD_SHIFT 3U
  5275. /*! Register: mi_sp_cb_size_shd: Size shadow register of self picture Cb component ring buffer (0x000000b4)*/
  5276. /*! Slice: sp_cb_size:*/
  5277. /*! Size of self picture Cb component ring buffer.*/
  5278. #define MRV_MI_SP_CB_SIZE
  5279. #define MRV_MI_SP_CB_SIZE_MASK 0x0FFFFFF8U
  5280. #define MRV_MI_SP_CB_SIZE_SHIFT 3U
  5281. /*! Register: mi_sp_cb_offs_cnt_shd: Current offset counter of self picture Cb component ring buffer (0x000000b8)*/
  5282. /*! Slice: sp_cb_offs_cnt:*/
  5283. /*! Current offset counter of self picture Cb component ring buffer for address generation */
  5284. /* Note: Soft reset will reset the contents to reset value.*/
  5285. #define MRV_MI_SP_CB_OFFS_CNT
  5286. #define MRV_MI_SP_CB_OFFS_CNT_MASK 0x0FFFFFF8U
  5287. #define MRV_MI_SP_CB_OFFS_CNT_SHIFT 3U
  5288. /*! Register: mi_sp_cr_base_ad_shd: Base address shadow register for self picture Cr component ring buffer (0x000000bc)*/
  5289. /*! Slice: sp_cr_base_ad:*/
  5290. /*! Base address of self picture Cr component ring buffer.*/
  5291. #define MRV_MI_SP_CR_BASE_AD
  5292. #define MRV_MI_SP_CR_BASE_AD_MASK 0xFFFFFFF8U
  5293. #define MRV_MI_SP_CR_BASE_AD_SHIFT 3U
  5294. /*! Register: mi_sp_cr_size_shd: Size shadow register of self picture Cr component ring buffer (0x000000c0)*/
  5295. /*! Slice: sp_cr_size:*/
  5296. /*! Size of self picture Cr component ring buffer.*/
  5297. #define MRV_MI_SP_CR_SIZE
  5298. #define MRV_MI_SP_CR_SIZE_MASK 0x0FFFFFF8U
  5299. #define MRV_MI_SP_CR_SIZE_SHIFT 3U
  5300. /*! Register: mi_sp_cr_offs_cnt_shd: Current offset counter of self picture Cr component ring buffer (0x000000c4)*/
  5301. /*! Slice: sp_cr_offs_cnt:*/
  5302. /*! Current offset counter of self picture Cr component ring buffer for address generation */
  5303. /* Note: Soft reset will reset the contents to reset value.*/
  5304. #define MRV_MI_SP_CR_OFFS_CNT
  5305. #define MRV_MI_SP_CR_OFFS_CNT_MASK 0x0FFFFFF8U
  5306. #define MRV_MI_SP_CR_OFFS_CNT_SHIFT 3U
  5307. /*! Register: mi_dma_y_pic_start_ad: Y component image start address (0x000000c8)*/
  5308. /*! Slice: dma_y_pic_start_ad:*/
  5309. /*! Image start address of the y component */
  5310. /* Note: Must be multiple of 4 in interleaved mode.*/
  5311. #define MRV_MI_DMA_Y_PIC_START_AD
  5312. #define MRV_MI_DMA_Y_PIC_START_AD_MASK 0xFFFFFFFFU
  5313. #define MRV_MI_DMA_Y_PIC_START_AD_SHIFT 0U
  5314. /*! Register: mi_dma_y_pic_width: Y component image width (0x000000cc)*/
  5315. /*! Slice: dma_y_pic_width:*/
  5316. /*! Image width of the Y component in pixel.*/
  5317. /* For YCbCr 4:2:x the image width must be a multiple of 2.*/
  5318. /* In planar mode the image width of the Cb and Cr component is assumed according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi planar 4:2:x mode the image width of the Cb component (which includes Cr) is assumed the same size. In interleave mode no Cb/Cr image width is used.*/
  5319. #define MRV_MI_DMA_Y_PIC_WIDTH
  5320. #define MRV_MI_DMA_Y_PIC_WIDTH_MASK 0x00007FFFU
  5321. #define MRV_MI_DMA_Y_PIC_WIDTH_SHIFT 0U
  5322. /*! Register: mi_dma_y_llength: Y component original line length (0x000000d0)*/
  5323. /*! Slice: dma_y_llength:*/
  5324. /*! Line length of the Y component of the original image in memory */
  5325. /* For an uncropped image, where lines follow each other without offset (no line stride), line length must match image width.*/
  5326. /* For Y component the line length in 4:2:x planar mode must be a multiple of 8, for all other component modes a multiple of 4.*/
  5327. /* In planar mode the line length of the Cb and Cr component is assumed according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi planar 4:2:x mode the line length of the Cb component (which includes Cr) is assumed the same size. In interleave mode no Cb/Cr line length is used.*/
  5328. #define MRV_MI_DMA_Y_LLENGTH
  5329. #define MRV_MI_DMA_Y_LLENGTH_MASK 0x00007FFFU
  5330. #define MRV_MI_DMA_Y_LLENGTH_SHIFT 0U
  5331. /*! Register: mi_dma_y_pic_size: Y component image size (0x000000d4)*/
  5332. /*! Slice: dma_y_pic_size:*/
  5333. /*! Image size of the Y component in pixel which has to be the Y line length multiplied by the Y image height (dma_y_llength * dma_y_pic_height).*/
  5334. /* In planar mode the image size of the Cb and Cr component is assumed according to the YCbCr format, i.e. a quarter for 4:2:0, half for 4:2:2 and the same for 4:4:4. In semi planar mode the image size of the Cb component (which includes Cr) is assumed half for 4:2:0 and the same size for 4:2:2. In interleave mode no Cb/Cr image size is used.*/
  5335. #define MRV_MI_DMA_Y_PIC_SIZE
  5336. #define MRV_MI_DMA_Y_PIC_SIZE_MASK 0x0FFFFFFFU
  5337. #define MRV_MI_DMA_Y_PIC_SIZE_SHIFT 0U
  5338. /*! Register: mi_dma_cb_pic_start_ad: Cb component image start address (0x000000d8)*/
  5339. /*! Slice: dma_cb_pic_start_ad:*/
  5340. /*! Image start address of the Cb component */
  5341. /* Note: Must be multiple of 2 in semi-planar mode.*/
  5342. #define MRV_MI_DMA_CB_PIC_START_AD
  5343. #define MRV_MI_DMA_CB_PIC_START_AD_MASK 0xFFFFFFFFU
  5344. #define MRV_MI_DMA_CB_PIC_START_AD_SHIFT 0U
  5345. /*! Register: mi_dma_cr_pic_start_ad: Cr component image start address (0x000000e8)*/
  5346. /*! Slice: dma_cr_pic_start_ad:*/
  5347. /*! Image start address of the Cr component */
  5348. #define MRV_MI_DMA_CR_PIC_START_AD
  5349. #define MRV_MI_DMA_CR_PIC_START_AD_MASK 0xFFFFFFFFU
  5350. #define MRV_MI_DMA_CR_PIC_START_AD_SHIFT 0U
  5351. /*! Register: mi_imsc: Interrupt Mask (‘1’: interrupt active, ‘0’: interrupt masked) (0x000000f8)*/
  5352. #ifdef ISP_MI_HANDSHAKE_NANO
  5353. /*! Slice mp_handshk_int:*/
  5354. /*! Mask bit for mp handshake interrupt */
  5355. #define MRV_MI_MP_HANDSHK_INT
  5356. #define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U
  5357. #define MRV_MI_MP_HANDSHK_INT_SHIFT 12U
  5358. #endif
  5359. /*! Slice: dma_ready:*/
  5360. /*! Mask bit for dma ready interrupt */
  5361. #define MRV_MI_DMA_READY
  5362. #define MRV_MI_DMA_READY_MASK 0x00000800U
  5363. #define MRV_MI_DMA_READY_SHIFT 11U
  5364. /*! Slice: wrap_sp_cr:*/
  5365. /*! Mask bit for self picture Cr address wrap interrupt */
  5366. #define MRV_MI_WRAP_SP_CR
  5367. #define MRV_MI_WRAP_SP_CR_MASK 0x00000200U
  5368. #define MRV_MI_WRAP_SP_CR_SHIFT 9U
  5369. /*! Slice: wrap_sp_cb:*/
  5370. /*! Mask bit for self picture Cb address wrap interrupt */
  5371. #define MRV_MI_WRAP_SP_CB
  5372. #define MRV_MI_WRAP_SP_CB_MASK 0x00000100U
  5373. #define MRV_MI_WRAP_SP_CB_SHIFT 8U
  5374. /*! Slice: wrap_sp_y:*/
  5375. /*! Mask bit for self picture Y address wrap interrupt */
  5376. #define MRV_MI_WRAP_SP_Y
  5377. #define MRV_MI_WRAP_SP_Y_MASK 0x00000080U
  5378. #define MRV_MI_WRAP_SP_Y_SHIFT 7U
  5379. /*! Slice: wrap_mp_cr:*/
  5380. /*! Mask bit for main picture Cr address wrap interrupt */
  5381. #define MRV_MI_WRAP_MP_CR
  5382. #define MRV_MI_WRAP_MP_CR_MASK 0x00000040U
  5383. #define MRV_MI_WRAP_MP_CR_SHIFT 6U
  5384. /*! Slice: wrap_mp_cb:*/
  5385. /*! Mask bit for main picture Cb address wrap interrupt */
  5386. #define MRV_MI_WRAP_MP_CB
  5387. #define MRV_MI_WRAP_MP_CB_MASK 0x00000020U
  5388. #define MRV_MI_WRAP_MP_CB_SHIFT 5U
  5389. /*! Slice: wrap_mp_y:*/
  5390. /*! Mask bit for main picture Y address wrap interrupt */
  5391. #define MRV_MI_WRAP_MP_Y
  5392. #define MRV_MI_WRAP_MP_Y_MASK 0x00000010U
  5393. #define MRV_MI_WRAP_MP_Y_SHIFT 4U
  5394. /*! Slice: fill_mp_y:*/
  5395. /*! Mask bit for fill level interrupt of main picture Y, JPEG or raw data */
  5396. #define MRV_MI_FILL_MP_Y
  5397. #define MRV_MI_FILL_MP_Y_MASK 0x00000008U
  5398. #define MRV_MI_FILL_MP_Y_SHIFT 3U
  5399. /*! Slice: mblk_line:*/
  5400. /*! Mask bit for makroblock line interrupt of main picture (16 lines of Y, 8 lines of Cb and 8 lines of Cr are written into RAM)*/
  5401. #define MRV_MI_MBLK_LINE
  5402. #define MRV_MI_MBLK_LINE_MASK 0x00000004U
  5403. #define MRV_MI_MBLK_LINE_SHIFT 2U
  5404. /*! Slice: sp_frame_end:*/
  5405. /*! Mask self picture end of frame interrupt */
  5406. #define MRV_MI_SP_FRAME_END
  5407. #define MRV_MI_SP_FRAME_END_MASK 0x00000002U
  5408. #define MRV_MI_SP_FRAME_END_SHIFT 1U
  5409. /*! Slice: mp_frame_end:*/
  5410. /*! Mask main picture end of frame interrupt */
  5411. #define MRV_MI_MP_FRAME_END
  5412. #define MRV_MI_MP_FRAME_END_MASK 0x00000001U
  5413. #define MRV_MI_MP_FRAME_END_SHIFT 0U
  5414. /*! Register: mi_ris: Raw Interrupt Status (0x000000fc)*/
  5415. #ifdef ISP_MI_HANDSHAKE_NANO
  5416. /*! Slice mp_handshk_int:*/
  5417. /*! Raw status of mp handshake interrupt */
  5418. #define MRV_MI_MP_HANDSHK_INT
  5419. #define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U
  5420. #define MRV_MI_MP_HANDSHK_INT_SHIFT 12U
  5421. #endif
  5422. /*! Slice: dma_ready:*/
  5423. /*! Raw status of dma ready interrupt */
  5424. #define MRV_MI_DMA_READY
  5425. #define MRV_MI_DMA_READY_MASK 0x00000800U
  5426. #define MRV_MI_DMA_READY_SHIFT 11U
  5427. /*! Slice: wrap_sp_cr:*/
  5428. /*! Raw status of self picture Cr address wrap interrupt */
  5429. #define MRV_MI_WRAP_SP_CR
  5430. #define MRV_MI_WRAP_SP_CR_MASK 0x00000200U
  5431. #define MRV_MI_WRAP_SP_CR_SHIFT 9U
  5432. /*! Slice: wrap_sp_cb:*/
  5433. /*! Raw status of self picture Cb address wrap interrupt */
  5434. #define MRV_MI_WRAP_SP_CB
  5435. #define MRV_MI_WRAP_SP_CB_MASK 0x00000100U
  5436. #define MRV_MI_WRAP_SP_CB_SHIFT 8U
  5437. /*! Slice: wrap_sp_y:*/
  5438. /*! Raw status of self picture Y address wrap interrupt */
  5439. #define MRV_MI_WRAP_SP_Y
  5440. #define MRV_MI_WRAP_SP_Y_MASK 0x00000080U
  5441. #define MRV_MI_WRAP_SP_Y_SHIFT 7U
  5442. /*! Slice: wrap_mp_cr:*/
  5443. /*! Raw status of main picture Cr address wrap interrupt */
  5444. #define MRV_MI_WRAP_MP_CR
  5445. #define MRV_MI_WRAP_MP_CR_MASK 0x00000040U
  5446. #define MRV_MI_WRAP_MP_CR_SHIFT 6U
  5447. /*! Slice: wrap_mp_cb:*/
  5448. /*! Raw status of main picture Cb address wrap interrupt */
  5449. #define MRV_MI_WRAP_MP_CB
  5450. #define MRV_MI_WRAP_MP_CB_MASK 0x00000020U
  5451. #define MRV_MI_WRAP_MP_CB_SHIFT 5U
  5452. /*! Slice: wrap_mp_y:*/
  5453. /*! Raw status of main picture Y address wrap interrupt */
  5454. #define MRV_MI_WRAP_MP_Y
  5455. #define MRV_MI_WRAP_MP_Y_MASK 0x00000010U
  5456. #define MRV_MI_WRAP_MP_Y_SHIFT 4U
  5457. /*! Slice: fill_mp_y:*/
  5458. /*! Raw status of fill level interrupt of main picture Y, JPEG or raw data */
  5459. #define MRV_MI_FILL_MP_Y
  5460. #define MRV_MI_FILL_MP_Y_MASK 0x00000008U
  5461. #define MRV_MI_FILL_MP_Y_SHIFT 3U
  5462. /*! Slice: mblk_line:*/
  5463. /*! Raw status of makroblock line interrupt of main picture (16 lines of Y, 8 lines of Cb and 8 lines of Cr are written into RAM, valid only for planar and semi-planar mode)*/
  5464. #define MRV_MI_MBLK_LINE
  5465. #define MRV_MI_MBLK_LINE_MASK 0x00000004U
  5466. #define MRV_MI_MBLK_LINE_SHIFT 2U
  5467. /*! Slice: sp_frame_end:*/
  5468. /*! Raw status of self picture end of frame interrupt */
  5469. #define MRV_MI_SP_FRAME_END
  5470. #define MRV_MI_SP_FRAME_END_MASK 0x00000002U
  5471. #define MRV_MI_SP_FRAME_END_SHIFT 1U
  5472. /*! Slice: mp_frame_end:*/
  5473. /*! Raw status of main picture end of frame interrupt */
  5474. #define MRV_MI_MP_FRAME_END
  5475. #define MRV_MI_MP_FRAME_END_MASK 0x00000001U
  5476. #define MRV_MI_MP_FRAME_END_SHIFT 0U
  5477. #ifdef ISP_MI_BP
  5478. /*! Slice: bp_frame_end:*/
  5479. /*! Raw status of bp picture end of frame interrupt */
  5480. #define MRV_MI_BP_FRAME_END
  5481. #define MRV_MI_BP_FRAME_END_MASK 0x00004000U
  5482. #define MRV_MI_BP_FRAME_END_SHIFT 14U
  5483. /*! Slice: bp_wr_raw_aligned:*/
  5484. #define BP_WR_RAW_ALIGNED
  5485. #define BP_WR_RAW_ALIGNED_MASK 0x000000c0U
  5486. #define BP_WR_RAW_ALIGNED_SHIFT 6U
  5487. /*! Slice: bp_wr_byte_swap:*/
  5488. #define BP_WR_BYTE_SWAP
  5489. #define BP_WR_BYTE_SWAP_MASK 0x00007000U
  5490. #define BP_WR_BYTE_SWAP_SHIFT 12U
  5491. /*! Slice: bp_fill_r */
  5492. #define MRV_MI_BP_FILL_R
  5493. #define MRV_MI_BP_FILL_R_MASK 0x00008000U
  5494. #define MRV_MI_BP_FILL_R_SHIFT 15U
  5495. /*! Slice: wrap_bp_r:*/
  5496. #define MRV_MI_BP_WRAP_R
  5497. #define MRV_MI_BP_WRAP_R_MASK 0x00010000U
  5498. #define MRV_MI_BP_WRAP_R_SHIFT 16U
  5499. /*! Slice: wrap_bp_r:*/
  5500. #define MRV_MI_BP_WRAP_R
  5501. #define MRV_MI_BP_WRAP_R_MASK 0x00010000U
  5502. #define MRV_MI_BP_WRAP_R_SHIFT 16U
  5503. /*! Slice: wrap_bp_gr:*/
  5504. #define MRV_MI_BP_WRAP_GR
  5505. #define MRV_MI_BP_WRAP_GR_MASK 0x00020000U
  5506. #define MRV_MI_BP_WRAP_GR_SHIFT 17U
  5507. /*! Slice: wrap_bp_gb:*/
  5508. #define MRV_MI_BP_WRAP_GB
  5509. #define MRV_MI_BP_WRAP_GB_MASK 0x00040000U
  5510. #define MRV_MI_BP_WRAP_GB_SHIFT 18U
  5511. /*! Slice: wrap_bp_b:*/
  5512. #define MRV_MI_BP_WRAP_B
  5513. #define MRV_MI_BP_WRAP_B_MASK 0x00080000U
  5514. #define MRV_MI_BP_WRAP_B_SHIFT 19U
  5515. /*! Register: miv1_bp_r_base_ad_init (0x000015d8)*/
  5516. /*! Slice: bp_r_base_ad_init:*/
  5517. #define BP_R_BASE_AD_INIT
  5518. #define BP_R_BASE_AD_INIT_MASK 0xFFFFFFF8U
  5519. #define BP_R_BASE_AD_INIT_SHIFT 3U
  5520. /*! Register: miv1_bp_gr_base_ad_init (0x000015dc)*/
  5521. /*! Slice: bp_gr_base_ad_init:*/
  5522. #define BP_GR_BASE_AD_INIT
  5523. #define BP_GR_BASE_AD_INIT_MASK 0xFFFFFFF8U
  5524. #define BP_GR_BASE_AD_INIT_SHIFT 3U
  5525. /*! Register: miv1_bp_gb_base_ad_init (0x000015e0)*/
  5526. /*! Slice: bp_gb_base_ad_init:*/
  5527. #define BP_GB_BASE_AD_INIT
  5528. #define BP_GB_BASE_AD_INIT_MASK 0xFFFFFFF8U
  5529. #define BP_GB_BASE_AD_INIT_SHIFT 3U
  5530. /*! Register: miv1_bp_b_base_ad_init (0x000015e4)*/
  5531. /*! Slice: bp_b_base_ad_init:*/
  5532. #define BP_B_BASE_AD_INIT
  5533. #define BP_B_BASE_AD_INIT_MASK 0xFFFFFFF8U
  5534. #define BP_B_BASE_AD_INIT_SHIFT 3U
  5535. /*! Register: miv1_bp_r_offs_cnt_init (0x000015c8)*/
  5536. /*! Slice: bp_r_offs_cnt_init:*/
  5537. #define BP_R_OFFS_CNT_INIT
  5538. #define BP_R_OFFS_CNT_INIT_MASK 0x1FFFFFF8U
  5539. #define BP_R_OFFS_CNT_INIT_SHIFT 3U
  5540. /*! Register: miv1_bp_gr_offs_cnt_init (0x000015cc)*/
  5541. /*! Slice: bp_gr_offs_cnt_init:*/
  5542. #define BP_GR_OFFS_CNT_INIT
  5543. #define BP_GR_OFFS_CNT_INIT_MASK 0x1FFFFFF8U
  5544. #define BP_GR_OFFS_CNT_INIT_SHIFT 3U
  5545. /*! Register: miv1_bp_gb_offs_cnt_init (0x000015d0)*/
  5546. /*! Slice: bp_gb_offs_cnt_init:*/
  5547. #define BP_GB_OFFS_CNT_INIT
  5548. #define BP_GB_OFFS_CNT_INIT_MASK 0x1FFFFFF8U
  5549. #define BP_GB_OFFS_CNT_INIT_SHIFT 3U
  5550. /*! Register: miv1_bp_b_offs_cnt_init (0x000015d4)*/
  5551. /*! Slice: bp_b_offs_cnt_init:*/
  5552. #define BP_B_OFFS_CNT_INIT
  5553. #define BP_B_OFFS_CNT_INIT_MASK 0x1FFFFFF8U
  5554. #define BP_B_OFFS_CNT_INIT_SHIFT 3U
  5555. /*! Register: miv1_bp_wr_offs_cnt_init (0x000015A4)*/
  5556. /*! Slice: mi_bp_wr_offs_cnt_init:*/
  5557. #define BP_PIC_WR_OFFS_CNT_INIT
  5558. #define BP_PIC_WR_OFFS_CNT_INIT_MASK 0x1FFFFFF8U
  5559. #define BP_PIC_WR_OFFS_CNT_INIT_SHIFT 3U
  5560. /*! Register: miv1_bp_wr_irq_offs_init (0x000015AC)*/
  5561. /*! Slice: mi_bp_wr_irq_offs_init:*/
  5562. #define BP_PIC_IRQ_OFFS_INIT
  5563. #define BP_PIC_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
  5564. #define BP_PIC_IRQ_OFFS_INIT_SHIFT 3U
  5565. /*! Register: miv1_bp_wr_size_init (0x000015B4)*/
  5566. /*! Slice: mi_bp_wr_size_init:*/
  5567. #define BP_PIC_WR_SIZE_INIT
  5568. #define BP_PIC_WR_SIZE_INIT_MASK 0x1FFFFFF8U
  5569. #define BP_PIC_WR_SIZE_INIT_SHIFT 3U
  5570. /*! Register: miv1_bp_pic_width (0x000015bc)*/
  5571. /*! Slice: bp_pic_width:*/
  5572. #define BP_PIC_WIDTH
  5573. #define BP_PIC_WIDTH_MASK 0x4FFFU
  5574. #define BP_PIC_WIDTH_SHIFT 0U
  5575. /*! Register: miv1_bp_pic_height (0x000015c0)*/
  5576. /*! Slice: bp_pic_height:*/
  5577. #define BP_PIC_HEIGHT
  5578. #define BP_PIC_HEIGHT_MASK 0x4FFFU
  5579. #define BP_PIC_HEIGHT_SHIFT 0U
  5580. /*! Register: miv1_bp_pic_size (0x000015c4)*/
  5581. /*! Slice: bp_pic_size:*/
  5582. #define BP_PIC_SIZE
  5583. #define BP_PIC_SIZE_MASK 0x1FFFFFFU
  5584. #define BP_PIC_SIZE_SHIFT 0U
  5585. #endif
  5586. /*! Register: mi_mis: Masked Interrupt Status (0x00000100)*/
  5587. #ifdef ISP_MI_HANDSHAKE_NANO
  5588. /*! Slice mp_handshk_int:*/
  5589. /*! Masked status for mp handshake interrupt */
  5590. #define MRV_MI_MP_HANDSHK_INT
  5591. #define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U
  5592. #define MRV_MI_MP_HANDSHK_INT_SHIFT 12U
  5593. #endif
  5594. /*! Slice: dma_ready:*/
  5595. /*! Masked status of dma ready interrupt */
  5596. #define MRV_MI_DMA_READY
  5597. #define MRV_MI_DMA_READY_MASK 0x00000800U
  5598. #define MRV_MI_DMA_READY_SHIFT 11U
  5599. /*! Slice: wrap_sp_cr:*/
  5600. /*! Masked status of self picture Cr address wrap interrupt */
  5601. #define MRV_MI_WRAP_SP_CR
  5602. #define MRV_MI_WRAP_SP_CR_MASK 0x00000200U
  5603. #define MRV_MI_WRAP_SP_CR_SHIFT 9U
  5604. /*! Slice: wrap_sp_cb:*/
  5605. /*! Masked status of self picture Cb address wrap interrupt */
  5606. #define MRV_MI_WRAP_SP_CB
  5607. #define MRV_MI_WRAP_SP_CB_MASK 0x00000100U
  5608. #define MRV_MI_WRAP_SP_CB_SHIFT 8U
  5609. /*! Slice: wrap_sp_y:*/
  5610. /*! Masked status of self picture Y address wrap interrupt */
  5611. #define MRV_MI_WRAP_SP_Y
  5612. #define MRV_MI_WRAP_SP_Y_MASK 0x00000080U
  5613. #define MRV_MI_WRAP_SP_Y_SHIFT 7U
  5614. /*! Slice: wrap_mp_cr:*/
  5615. /*! Masked status of main picture Cr address wrap interrupt */
  5616. #define MRV_MI_WRAP_MP_CR
  5617. #define MRV_MI_WRAP_MP_CR_MASK 0x00000040U
  5618. #define MRV_MI_WRAP_MP_CR_SHIFT 6U
  5619. /*! Slice: wrap_mp_cb:*/
  5620. /*! Masked status of main picture Cb address wrap interrupt */
  5621. #define MRV_MI_WRAP_MP_CB
  5622. #define MRV_MI_WRAP_MP_CB_MASK 0x00000020U
  5623. #define MRV_MI_WRAP_MP_CB_SHIFT 5U
  5624. /*! Slice: wrap_mp_y:*/
  5625. /*! Masked status of main picture Y address wrap interrupt */
  5626. #define MRV_MI_WRAP_MP_Y
  5627. #define MRV_MI_WRAP_MP_Y_MASK 0x00000010U
  5628. #define MRV_MI_WRAP_MP_Y_SHIFT 4U
  5629. /*! Slice: fill_mp_y:*/
  5630. /*! Masked status of fill level interrupt of main picture Y, JPEG or raw data */
  5631. #define MRV_MI_FILL_MP_Y
  5632. #define MRV_MI_FILL_MP_Y_MASK 0x00000008U
  5633. #define MRV_MI_FILL_MP_Y_SHIFT 3U
  5634. /*! Slice: mblk_line:*/
  5635. /*! Masked status of makroblock line interrupt of main picture (16 lines of Y, 8 lines of Cb and 8 lines of Cr are written into RAM, valid only for planar and semi-planar mode)*/
  5636. #define MRV_MI_MBLK_LINE
  5637. #define MRV_MI_MBLK_LINE_MASK 0x00000004U
  5638. #define MRV_MI_MBLK_LINE_SHIFT 2U
  5639. /*! Slice: sp_frame_end:*/
  5640. /*! Masked status of self picture end of frame interrupt */
  5641. #define MRV_MI_SP_FRAME_END
  5642. #define MRV_MI_SP_FRAME_END_MASK 0x00000002U
  5643. #define MRV_MI_SP_FRAME_END_SHIFT 1U
  5644. /*! Slice: mp_frame_end:*/
  5645. /*! Masked status of main picture end of frame interrupt */
  5646. #define MRV_MI_MP_FRAME_END
  5647. #define MRV_MI_MP_FRAME_END_MASK 0x00000001U
  5648. #define MRV_MI_MP_FRAME_END_SHIFT 0U
  5649. /*! Register: mi_icr: Interrupt Clear Register (0x00000104)*/
  5650. #ifdef ISP_MI_HANDSHAKE_NANO
  5651. /*! Slice mp_handshk_int:*/
  5652. /*! clear mp handshake interrupt */
  5653. #define MRV_MI_MP_HANDSHK_INT
  5654. #define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U
  5655. #define MRV_MI_MP_HANDSHK_INT_SHIFT 12U
  5656. #endif
  5657. /*! Slice: dma_ready:*/
  5658. /*! Clear dma ready interrupt */
  5659. #define MRV_MI_DMA_READY
  5660. #define MRV_MI_DMA_READY_MASK 0x00000800U
  5661. #define MRV_MI_DMA_READY_SHIFT 11U
  5662. /*! Slice: wrap_sp_cr:*/
  5663. /*! Clear self picture Cr address wrap interrupt */
  5664. #define MRV_MI_WRAP_SP_CR
  5665. #define MRV_MI_WRAP_SP_CR_MASK 0x00000200U
  5666. #define MRV_MI_WRAP_SP_CR_SHIFT 9U
  5667. /*! Slice: wrap_sp_cb:*/
  5668. /*! Clear self picture Cb address wrap interrupt */
  5669. #define MRV_MI_WRAP_SP_CB
  5670. #define MRV_MI_WRAP_SP_CB_MASK 0x00000100U
  5671. #define MRV_MI_WRAP_SP_CB_SHIFT 8U
  5672. /*! Slice: wrap_sp_y:*/
  5673. /*! Clear self picture Y address wrap interrupt */
  5674. #define MRV_MI_WRAP_SP_Y
  5675. #define MRV_MI_WRAP_SP_Y_MASK 0x00000080U
  5676. #define MRV_MI_WRAP_SP_Y_SHIFT 7U
  5677. /*! Slice: wrap_mp_cr:*/
  5678. /*! Clear main picture Cr address wrap interrupt */
  5679. #define MRV_MI_WRAP_MP_CR
  5680. #define MRV_MI_WRAP_MP_CR_MASK 0x00000040U
  5681. #define MRV_MI_WRAP_MP_CR_SHIFT 6U
  5682. /*! Slice: wrap_mp_cb:*/
  5683. /*! Clear main picture Cb address wrap interrupt */
  5684. #define MRV_MI_WRAP_MP_CB
  5685. #define MRV_MI_WRAP_MP_CB_MASK 0x00000020U
  5686. #define MRV_MI_WRAP_MP_CB_SHIFT 5U
  5687. /*! Slice: wrap_mp_y:*/
  5688. /*! Clear main picture Y address wrap interrupt */
  5689. #define MRV_MI_WRAP_MP_Y
  5690. #define MRV_MI_WRAP_MP_Y_MASK 0x00000010U
  5691. #define MRV_MI_WRAP_MP_Y_SHIFT 4U
  5692. /*! Slice: fill_mp_y:*/
  5693. /*! Clear fill level interrupt */
  5694. #define MRV_MI_FILL_MP_Y
  5695. #define MRV_MI_FILL_MP_Y_MASK 0x00000008U
  5696. #define MRV_MI_FILL_MP_Y_SHIFT 3U
  5697. /*! Slice: mblk_line:*/
  5698. /*! Clear makroblock line interrupt */
  5699. #define MRV_MI_MBLK_LINE
  5700. #define MRV_MI_MBLK_LINE_MASK 0x00000004U
  5701. #define MRV_MI_MBLK_LINE_SHIFT 2U
  5702. /*! Slice: sp_frame_end:*/
  5703. /*! Clear self picture end of frame interrupt */
  5704. #define MRV_MI_SP_FRAME_END
  5705. #define MRV_MI_SP_FRAME_END_MASK 0x00000002U
  5706. #define MRV_MI_SP_FRAME_END_SHIFT 1U
  5707. /*! Slice: mp_frame_end:*/
  5708. /*! Clear main picture end of frame interrupt */
  5709. #define MRV_MI_MP_FRAME_END
  5710. #define MRV_MI_MP_FRAME_END_MASK 0x00000001U
  5711. #define MRV_MI_MP_FRAME_END_SHIFT 0U
  5712. /*! Register: mi_isr: Interrupt Set Register (0x00000108)*/
  5713. #ifdef ISP_MI_HANDSHAKE_NANO
  5714. /*! Slice mp_handshk_int:*/
  5715. /*! Set mp handshake interrupt */
  5716. #define MRV_MI_MP_HANDSHK_INT
  5717. #define MRV_MI_MP_HANDSHK_INT_MASK 0x00001000U
  5718. #define MRV_MI_MP_HANDSHK_INT_SHIFT 12U
  5719. #endif
  5720. /*! Slice: dma_ready:*/
  5721. /*! Set dma ready interrupt */
  5722. #define MRV_MI_DMA_READY
  5723. #define MRV_MI_DMA_READY_MASK 0x00000800U
  5724. #define MRV_MI_DMA_READY_SHIFT 11U
  5725. /*! Slice: wrap_sp_cr:*/
  5726. /*! Set self picture Cr address wrap interrupt */
  5727. #define MRV_MI_WRAP_SP_CR
  5728. #define MRV_MI_WRAP_SP_CR_MASK 0x00000200U
  5729. #define MRV_MI_WRAP_SP_CR_SHIFT 9U
  5730. /*! Slice: wrap_sp_cb:*/
  5731. /*! Set self picture Cb address wrap interrupt */
  5732. #define MRV_MI_WRAP_SP_CB
  5733. #define MRV_MI_WRAP_SP_CB_MASK 0x00000100U
  5734. #define MRV_MI_WRAP_SP_CB_SHIFT 8U
  5735. /*! Slice: wrap_sp_y:*/
  5736. /*! Set self picture Y address wrap interrupt */
  5737. #define MRV_MI_WRAP_SP_Y
  5738. #define MRV_MI_WRAP_SP_Y_MASK 0x00000080U
  5739. #define MRV_MI_WRAP_SP_Y_SHIFT 7U
  5740. /*! Slice: wrap_mp_cr:*/
  5741. /*! Set main picture Cr address wrap interrupt */
  5742. #define MRV_MI_WRAP_MP_CR
  5743. #define MRV_MI_WRAP_MP_CR_MASK 0x00000040U
  5744. #define MRV_MI_WRAP_MP_CR_SHIFT 6U
  5745. /*! Slice: wrap_mp_cb:*/
  5746. /*! Set main picture Cb address wrap interrupt */
  5747. #define MRV_MI_WRAP_MP_CB
  5748. #define MRV_MI_WRAP_MP_CB_MASK 0x00000020U
  5749. #define MRV_MI_WRAP_MP_CB_SHIFT 5U
  5750. /*! Slice: wrap_mp_y:*/
  5751. /*! Set main picture Y address wrap interrupt */
  5752. #define MRV_MI_WRAP_MP_Y
  5753. #define MRV_MI_WRAP_MP_Y_MASK 0x00000010U
  5754. #define MRV_MI_WRAP_MP_Y_SHIFT 4U
  5755. /*! Slice: fill_mp_y:*/
  5756. /*! Set fill level interrupt */
  5757. #define MRV_MI_FILL_MP_Y
  5758. #define MRV_MI_FILL_MP_Y_MASK 0x00000008U
  5759. #define MRV_MI_FILL_MP_Y_SHIFT 3U
  5760. /*! Slice: mblk_line:*/
  5761. /*! Set makroblock line interrupt */
  5762. #define MRV_MI_MBLK_LINE
  5763. #define MRV_MI_MBLK_LINE_MASK 0x00000004U
  5764. #define MRV_MI_MBLK_LINE_SHIFT 2U
  5765. /*! Slice: sp_frame_end:*/
  5766. /*! Set self picture end of frame interrupt */
  5767. #define MRV_MI_SP_FRAME_END
  5768. #define MRV_MI_SP_FRAME_END_MASK 0x00000002U
  5769. #define MRV_MI_SP_FRAME_END_SHIFT 1U
  5770. /*! Slice: mp_frame_end:*/
  5771. /*! Set main picture end of frame interrupt */
  5772. #define MRV_MI_MP_FRAME_END
  5773. #define MRV_MI_MP_FRAME_END_MASK 0x00000001U
  5774. #define MRV_MI_MP_FRAME_END_SHIFT 0U
  5775. /*! Register: mi_status: MI Status Register (0x0000010c)*/
  5776. /*! Slice: sp_cr_fifo_full:*/
  5777. /*! FIFO full flag of Cr FIFO in self path asserted since last clear */
  5778. #define MRV_MI_SP_CR_FIFO_FULL
  5779. #define MRV_MI_SP_CR_FIFO_FULL_MASK 0x00000040U
  5780. #define MRV_MI_SP_CR_FIFO_FULL_SHIFT 6U
  5781. /*! Slice: sp_cb_fifo_full:*/
  5782. /*! FIFO full flag of Cb FIFO in self path asserted since last clear */
  5783. #define MRV_MI_SP_CB_FIFO_FULL
  5784. #define MRV_MI_SP_CB_FIFO_FULL_MASK 0x00000020U
  5785. #define MRV_MI_SP_CB_FIFO_FULL_SHIFT 5U
  5786. /*! Slice: sp_y_fifo_full:*/
  5787. /*! FIFO full flag of Y FIFO in self path asserted since last clear */
  5788. #define MRV_MI_SP_Y_FIFO_FULL
  5789. #define MRV_MI_SP_Y_FIFO_FULL_MASK 0x00000010U
  5790. #define MRV_MI_SP_Y_FIFO_FULL_SHIFT 4U
  5791. /*! Slice: mp_cr_fifo_full:*/
  5792. /*! FIFO full flag of Cr FIFO in main path asserted since last clear */
  5793. #define MRV_MI_MP_CR_FIFO_FULL
  5794. #define MRV_MI_MP_CR_FIFO_FULL_MASK 0x00000004U
  5795. #define MRV_MI_MP_CR_FIFO_FULL_SHIFT 2U
  5796. /*! Slice: mp_cb_fifo_full:*/
  5797. /*! FIFO full flag of Cb FIFO in main path asserted since last clear */
  5798. #define MRV_MI_MP_CB_FIFO_FULL
  5799. #define MRV_MI_MP_CB_FIFO_FULL_MASK 0x00000002U
  5800. #define MRV_MI_MP_CB_FIFO_FULL_SHIFT 1U
  5801. /*! Slice: mp_y_fifo_full:*/
  5802. /*! FIFO full flag of Y FIFO in main path asserted since last clear */
  5803. #define MRV_MI_MP_Y_FIFO_FULL
  5804. #define MRV_MI_MP_Y_FIFO_FULL_MASK 0x00000001U
  5805. #define MRV_MI_MP_Y_FIFO_FULL_SHIFT 0U
  5806. /*! Register: mi_status_clr: MI Status Clear Register (0x00000110)*/
  5807. /*! Slice: sp_cr_fifo_full:*/
  5808. /*! Clear status of Cr FIFO full flag in self path */
  5809. #define MRV_MI_SP_CR_FIFO_FULL
  5810. #define MRV_MI_SP_CR_FIFO_FULL_MASK 0x00000040U
  5811. #define MRV_MI_SP_CR_FIFO_FULL_SHIFT 6U
  5812. /*! Slice: sp_cb_fifo_full:*/
  5813. /*! Clear status of Cb FIFO full flag in self path */
  5814. #define MRV_MI_SP_CB_FIFO_FULL
  5815. #define MRV_MI_SP_CB_FIFO_FULL_MASK 0x00000020U
  5816. #define MRV_MI_SP_CB_FIFO_FULL_SHIFT 5U
  5817. /*! Slice: sp_y_fifo_full:*/
  5818. /*! Clear status of Y FIFO full flag in self path */
  5819. #define MRV_MI_SP_Y_FIFO_FULL
  5820. #define MRV_MI_SP_Y_FIFO_FULL_MASK 0x00000010U
  5821. #define MRV_MI_SP_Y_FIFO_FULL_SHIFT 4U
  5822. /*! Slice: mp_cr_fifo_full:*/
  5823. /*! Clear status of Cr FIFO full flag in main path */
  5824. #define MRV_MI_MP_CR_FIFO_FULL
  5825. #define MRV_MI_MP_CR_FIFO_FULL_MASK 0x00000004U
  5826. #define MRV_MI_MP_CR_FIFO_FULL_SHIFT 2U
  5827. /*! Slice: mp_cb_fifo_full:*/
  5828. /*! Clear status of Cb FIFO full flag in main path */
  5829. #define MRV_MI_MP_CB_FIFO_FULL
  5830. #define MRV_MI_MP_CB_FIFO_FULL_MASK 0x00000002U
  5831. #define MRV_MI_MP_CB_FIFO_FULL_SHIFT 1U
  5832. /*! Slice: mp_y_fifo_full:*/
  5833. /*! Clear status of Y FIFO full flag in main path */
  5834. #define MRV_MI_MP_Y_FIFO_FULL
  5835. #define MRV_MI_MP_Y_FIFO_FULL_MASK 0x00000001U
  5836. #define MRV_MI_MP_Y_FIFO_FULL_SHIFT 0U
  5837. /*! Register: mi_sp_y_pic_width: Y component image width (0x00000114)*/
  5838. /*! Slice: sp_y_pic_width:*/
  5839. /*! Image width of the self picture Y component or RGB picture in pixel.*/
  5840. /* For YCbCr 4:2:x and RGB 565 the image width must be a multiple of 2. If no line stride is used but flipping required, the image width must be a multiple of 8 for 4:2:x planar or 4 for 4:4:4 planar/4:2:x semi planar. There are no restrictions for RGB 888/666.*/
  5841. /* In planar mode the image width of the Cb and Cr component is assumed according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi planar 4:2:x mode the image width of the Cb component (which includes Cr) is assumed the same size. In interleave mode no Cb/Cr image width is used.*/
  5842. /* Note: Image width always refers to the picture width of the output image. This is particularly important when rotating.*/
  5843. /* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
  5844. #define MRV_MI_SP_Y_PIC_WIDTH
  5845. #define MRV_MI_SP_Y_PIC_WIDTH_MASK 0x00007FFFU
  5846. #define MRV_MI_SP_Y_PIC_WIDTH_SHIFT 0U
  5847. /*! Register: mi_sp_y_pic_height: Y component image height (0x00000118)*/
  5848. /*! Slice: sp_y_pic_height:*/
  5849. /*! Image height of the y component or RGB picture in pixel.*/
  5850. /* In planar and semi planar mode the image width of the cb and cr component is assumed according to the YCbCr format, i.e. half for 4:2:0 and the same for 4:2:2 and 4:4:4.*/
  5851. /* Note: Image height always refers to the picture height of the output image. This is particularly important when rotating.*/
  5852. /* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
  5853. #define MRV_MI_SP_Y_PIC_HEIGHT
  5854. #define MRV_MI_SP_Y_PIC_HEIGHT_MASK 0x00007FFFU
  5855. #define MRV_MI_SP_Y_PIC_HEIGHT_SHIFT 0U
  5856. /*! Register: mi_sp_y_pic_size: Y component image size (0x0000011c)*/
  5857. /*! Slice: sp_y_pic_size:*/
  5858. /*! Image size of the Y component or RGB picture in pixel which has to be the Y line length multiplied by the Y image height (sp_y_llength * sp_y_pic_height).*/
  5859. /* In planar mode the image size of the Cb and Cr component is assumed according to the YCbCr format, i.e. a quarter for 4:2:0, half for 4:2:2 and the same for 4:4:4. In semi planar mode the image size of the Cb and Cr component is assumed half for 4:2:0 and the same size for 4:2:2.*/
  5860. /* Note: Programmed value becomes effective immediately. So write to the register only if no picture data is sent to the self path.*/
  5861. #define MRV_MI_SP_Y_PIC_SIZE
  5862. #define MRV_MI_SP_Y_PIC_SIZE_MASK 0x01FFFFFFU
  5863. #define MRV_MI_SP_Y_PIC_SIZE_SHIFT 0U
  5864. /*! Register: mi_dma_ctrl: DMA control register (0x00000120)*/
  5865. /*! Slice: dma_rgb_format:*/
  5866. /*! Selects RGB Bayer data of read DMA picture */
  5867. /* 00: no DMA RGB Bayer data */
  5868. /* 01: 8 bit RGB Bayer data */
  5869. /* 10: 16 bit RGB Bayer data (12 bit used)*/
  5870. /* bytes are organized MSB first and 4 lower bits of LSB remain unused:*/
  5871. /* byte_even -> bayer[11:4], byte_odd[7:4] -> bayer[3:0]*/
  5872. /* 11: reserved.*/
  5873. #define MRV_MI_DMA_RGB_FORMAT
  5874. #define MRV_MI_DMA_RGB_FORMAT_MASK 0x00003000U
  5875. #define MRV_MI_DMA_RGB_FORMAT_SHIFT 12U
  5876. /*! Slice: dma_frame_end_disable:*/
  5877. /*! Suppresses v_end so that no frame end can be detected by following instances. Note: The dma_ready interrupt is raised as usual, but the dma_frame_end interrupt will not be generated until v_end has been enabled again.*/
  5878. #define MRV_MI_DMA_FRAME_END_DISABLE
  5879. #define MRV_MI_DMA_FRAME_END_DISABLE_MASK 0x00000400U
  5880. #define MRV_MI_DMA_FRAME_END_DISABLE_SHIFT 10U
  5881. /*! Slice: dma_continuous_en:*/
  5882. /*! Enables continuous mode. If set the same frame is read back over and over. A start pulse on dma_start is needed only for the first time. To stop continuous mode reset this bit (takes effect after the next frame end) or execute a soft reset. This bit is intended to be used in conjunction with the Superimpose feature.*/
  5883. #define MRV_MI_DMA_CONTINUOUS_EN
  5884. #define MRV_MI_DMA_CONTINUOUS_EN_MASK 0x00000200U
  5885. #define MRV_MI_DMA_CONTINUOUS_EN_SHIFT 9U
  5886. /*! Slice: dma_byte_swap:*/
  5887. /*! Enables change of DMA byte order of the 32 bit input word at read port */
  5888. /* 1: byte order is mirrored but the bit order within one byte doesn’t change */
  5889. /* 0: no byte mirroring */
  5890. #define MRV_MI_DMA_BYTE_SWAP
  5891. #define MRV_MI_DMA_BYTE_SWAP_MASK 0x00000100U
  5892. #define MRV_MI_DMA_BYTE_SWAP_SHIFT 8U
  5893. /*! Slice: dma_inout_format:*/
  5894. /*! Selects input/output format of DMA picture.*/
  5895. /* 11: YCbCr 4:4:4 */
  5896. /* 10: YCbCr 4:2:2 */
  5897. /* 01: YCbCr 4:2:0 */
  5898. /* 00: YCbCr 4:0:0 */
  5899. #define MRV_MI_DMA_INOUT_FORMAT
  5900. #define MRV_MI_DMA_INOUT_FORMAT_MASK 0x000000C0U
  5901. #define MRV_MI_DMA_INOUT_FORMAT_SHIFT 6U
  5902. /*! Slice: dma_read_format:*/
  5903. /*! Defines how YCbCr picture data is read from memory.*/
  5904. /* 00: planar */
  5905. /* 01: semi planar, for YCbCr 4:2:x */
  5906. /* 10: interleaved (combined), for YCbCr 4:2:2 and RGB only */
  5907. /* 11: reserved */
  5908. #define MRV_MI_DMA_READ_FORMAT
  5909. #define MRV_MI_DMA_READ_FORMAT_MASK 0x00000030U
  5910. #define MRV_MI_DMA_READ_FORMAT_SHIFT 4U
  5911. /*! Slice: dma_burst_len_chrom:*/
  5912. /*! Burst length for Cb or Cr data affecting DMA read port.*/
  5913. /* 00: 4-beat bursts */
  5914. /* 01: 8-beat bursts */
  5915. /* 10: 16-beat bursts */
  5916. /* 11: reserved */
  5917. /* Ignored if 8- or 16-beat bursts are not supported.*/
  5918. #define MRV_MI_DMA_BURST_LEN_CHROM
  5919. #define MRV_MI_DMA_BURST_LEN_CHROM_MASK 0x0000000CU
  5920. #define MRV_MI_DMA_BURST_LEN_CHROM_SHIFT 2U
  5921. /*! Slice: dma_burst_len_lum:*/
  5922. /*! Burst length for Y data affecting DMA read port.*/
  5923. /* 00: 4-beat bursts */
  5924. /* 01: 8-beat bursts */
  5925. /* 10: 16-beat bursts */
  5926. /* 11: reserved */
  5927. /* Ignored if 8- or 16-beat bursts are not supported.*/
  5928. #define MRV_MI_DMA_BURST_LEN_LUM
  5929. #define MRV_MI_DMA_BURST_LEN_LUM_MASK 0x00000003U
  5930. #define MRV_MI_DMA_BURST_LEN_LUM_SHIFT 0U
  5931. /*! Register: mi_dma_start: DMA start register (0x00000124)*/
  5932. /*! Slice: dma_start:*/
  5933. /*! Enables DMA access. Additionally main or self path has to be enabled separately.*/
  5934. #define MRV_MI_DMA_START
  5935. #define MRV_MI_DMA_START_MASK 0x00000001U
  5936. #define MRV_MI_DMA_START_SHIFT 0U
  5937. /*! Register: mi_dma_status: DMA status register (0x00000128)*/
  5938. /*! Slice: dma_active:*/
  5939. /*! If set DMA access is active.*/
  5940. #define MRV_MI_DMA_ACTIVE
  5941. #define MRV_MI_DMA_ACTIVE_MASK 0x00000001U
  5942. #define MRV_MI_DMA_ACTIVE_SHIFT 0U
  5943. /*! Register: mi_pixel_cnt: Counter value for defect pixel list (0x0000012c)*/
  5944. /*! Slice: pix_cnt:*/
  5945. /*! Counter value specifies the number of pixels of the defect pixel list generated by DPCC of the last transmitted frame. Updated at frame end.*/
  5946. /* A soft reset will set the counter to zero.*/
  5947. #define MRV_MI_PIX_CNT
  5948. #define MRV_MI_PIX_CNT_MASK 0x0FFFFFFFU
  5949. #define MRV_MI_PIX_CNT_SHIFT 0U
  5950. /*! Register: mi_mp_y_base_ad_init2: Base address 2 (ping pong) for main picture Y component, JPEG or raw data (0x00000130)*/
  5951. /*! Slice: mp_y_base_ad_init2:*/
  5952. /*! 2nd ping pong base address of main picture Y component buffer, JPEG buffer or raw data buffer.*/
  5953. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5954. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5955. #define MRV_MI_MP_Y_BASE_AD_INIT2
  5956. #define MRV_MI_MP_Y_BASE_AD_INIT2_MASK 0xFFFFFFF8U
  5957. #define MRV_MI_MP_Y_BASE_AD_INIT2_SHIFT 3U
  5958. /*! Register: mi_mp_cb_base_ad_init2: Base address 2 (pingpong) for main picture Cb component (0x00000134)*/
  5959. /*! Slice: mp_cb_base_ad_init2:*/
  5960. /*! 2nd ping pong base address of main picture Cb component buffer.*/
  5961. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5962. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5963. #define MRV_MI_MP_CB_BASE_AD_INIT2
  5964. #define MRV_MI_MP_CB_BASE_AD_INIT2_MASK 0xFFFFFFF8U
  5965. #define MRV_MI_MP_CB_BASE_AD_INIT2_SHIFT 3U
  5966. /*! Register: mi_mp_cr_base_ad_init2: Base address 2 (pingpong) for main picture Cr component ring buffer (0x00000138)*/
  5967. /*! Slice: mp_cr_base_ad_init2:*/
  5968. /*! 2nd ping pong Base address of main picture Cr component buffer.*/
  5969. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5970. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5971. #define MRV_MI_MP_CR_BASE_AD_INIT2
  5972. #define MRV_MI_MP_CR_BASE_AD_INIT2_MASK 0xFFFFFFF8U
  5973. #define MRV_MI_MP_CR_BASE_AD_INIT2_SHIFT 3U
  5974. /*! Register: mi_sp_y_base_ad_init2: Base address 2 (ping pong) for main picture Y component, JPEG or raw data (0x0000013c)*/
  5975. /*! Slice: sp_y_base_ad_init2:*/
  5976. /*! 2nd ping pong base address of main picture Y component buffer, JPEG buffer or raw data buffer.*/
  5977. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5978. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5979. #define MRV_MI_SP_Y_BASE_AD_INIT2
  5980. #define MRV_MI_SP_Y_BASE_AD_INIT2_MASK 0xFFFFFFF8U
  5981. #define MRV_MI_SP_Y_BASE_AD_INIT2_SHIFT 3U
  5982. /*! Register: mi_sp_cb_base_ad_init2: Base address 2 (pingpong) for main picture Cb component (0x00000140)*/
  5983. /*! Slice: sp_cb_base_ad_init2:*/
  5984. /*! 2nd ping pong base address of main picture Cb component buffer.*/
  5985. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5986. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5987. #define MRV_MI_SP_CB_BASE_AD_INIT2
  5988. #define MRV_MI_SP_CB_BASE_AD_INIT2_MASK 0xFFFFFFF8U
  5989. #define MRV_MI_SP_CB_BASE_AD_INIT2_SHIFT 3U
  5990. /*! Register: mi_sp_cr_base_ad_init2: Base address 2 (pingpong) for main picture Cr component ring buffer (0x00000144)*/
  5991. /*! Slice: sp_cr_base_ad_init2:*/
  5992. /*! 2nd ping pong Base address of main picture Cr component buffer.*/
  5993. /* Programmed value becomes effective (visible in corresponding shadow register) after a soft reset, a forced software update or an automatic config update.*/
  5994. /* Note: Set control bit init_base_en before updating so that a forced or automatic update can take effect.*/
  5995. #define MRV_MI_SP_CR_BASE_AD_INIT2
  5996. #define MRV_MI_SP_CR_BASE_AD_INIT2_MASK 0xFFFFFFF8U
  5997. #define MRV_MI_SP_CR_BASE_AD_INIT2_SHIFT 3U
  5998. #ifdef ISP_MI_HANDSHAKE_NANO
  5999. /*! Nano handshake */
  6000. /*! Register: isp_handshake_ctrl_0: IspNano handshake functions (0x0000014C)*/
  6001. /*! Slice: mp_handshake_en:*/
  6002. /*! Enable mp handshake function for MI MP */
  6003. #define MRV_MI_MP_HANDSHK_EN
  6004. #define MRV_MI_MP_HANDSHK_EN_MASK 0x00000001U
  6005. #define MRV_MI_MP_HANDSHK_EN_SHIFT 0U
  6006. /*! Slice: mp_handshk_storage_format */
  6007. /*! Define how YCbCr picture data is stored in memory */
  6008. /*! 00: Planar */
  6009. /*! 01: Semi planar, for YCbCr4:2:x */
  6010. /*! 10: Interleaved(combiled), for YCbCr 4:2:2 only or RAW format.*/
  6011. /*! 11: not support */
  6012. #define MRV_MI_MP_HANDSHK_STORAGE_FORMAT
  6013. #define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_MASK 0x00000006U
  6014. #define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_SHIFT 1U
  6015. /*! Slice: mp_handshk_data_format */
  6016. /*! Defines the video format */
  6017. /*! 00: RAW format */
  6018. /*! 01: reserved */
  6019. /*! 10: YUV 422 */
  6020. /*! 11: YUV 420 */
  6021. #define MRV_MI_MP_HANDSHK_DATA_FORMAT
  6022. #define MRV_MI_MP_HANDSHK_DATA_FORMAT_MASK 0x00000018U
  6023. #define MRV_MI_MP_HANDSHK_DATA_FORMAT_SHIFT 3U
  6024. /*! Slice: mp_handshk_slice_size */
  6025. /*! Defines the slice size to generate handshake signals, minus 1 is used */
  6026. #define MRV_MI_MP_HANDSHK_SLICE_SIZE
  6027. #define MRV_MI_MP_HANDSHK_SLICE_SIZE_MASK 0x00001FE0U
  6028. #define MRV_MI_MP_HANDSHK_SLICE_SIZE_SHIFT 5U
  6029. /*! Slice: mp_handshk_slice_buf_size */
  6030. /*! Defines the circular buffer size in number of defined slices per buffer, minus 1 is used */
  6031. #define MRV_MI_MP_HANDSHK_SLICE_BUF_SIZE
  6032. #define MRV_MI_MP_HANDSHK_SLICE_BUF_SIZE_MASK 0x001FE000U
  6033. #define MRV_MI_MP_HANDSHK_SLICE_BUF_SIZE_SHIFT 13U
  6034. /*! Slice: mp_handshk_ack_count */
  6035. /*! Defines the acknowledage is not received in the defined cycles, it will generate handshake interrupt.*/
  6036. #define MRV_MI_MP_HANDSHK_ACK_COUNT
  6037. #define MRV_MI_MP_HANDSHK_ACK_COUNT_MASK 0x1FE00000U
  6038. #define MRV_MI_MP_HANDSHK_ACK_COUNT_SHIFT 21U
  6039. /*! Register: isp_handshake_mp_y_llength: IspNano handshake y_llength (0x00000150)*/
  6040. /*! Slice: mp_y_llength, line length of main picture Y component or RGB picture in pixel.*/
  6041. /*! Also knows as line stride, if no line stride is used, the line length must match image width.*/
  6042. #define MRV_MI_MP_HANDSHK_Y_LLENGTH
  6043. #define MRV_MI_MP_HANDSHK_Y_LLENGTH_MASK 0x00007FFFU
  6044. #define MRV_MI_MP_HANDSHK_Y_LLENGTH_SHIFT 0U
  6045. /*! Register: isp_handshake_y_slice_offset: IspNano handshake y slice offset (0x00000154)*/
  6046. /*! Slice: mp_y_slice_offset defines the offset bewteen two successive Y slice input buffers in bytes.*/
  6047. #define MRV_MI_MP_HANDSHK_Y_SLICE_OFFSET
  6048. #define MRV_MI_MP_HANDSHK_Y_SLICE_OFFSET_MASK 0xFFFFFFF8U
  6049. #define MRV_MI_MP_HANDSHK_Y_SLICE_OFFSET_SHIFT 0U
  6050. /*! Register: isp_handshake_c_slice_offset: ISPNano handshake c slice offset (ox00000158)*/
  6051. /*! Slice: mp_c_slice_offset defines the offset between two successive Cb/Cr slice input buffers in bytes.*/
  6052. #define MRV_MI_MP_HANDSHK_C_SLICE_OFFSET
  6053. #define MRV_MI_MP_HANDSHK_C_SLICE_OFFSET_MASK 0xFFFFFFF8U
  6054. #define MRV_MI_MP_HANDSHK_C_SLICE_OFFSET_SHIFT 0U
  6055. #endif
  6056. #ifdef ISP_MI_ALIGN_NANO
  6057. /*! Register mi_output_align_format for isp nano: (0x0000015C)*/
  6058. /*! Slice mp_lsb_alignment:*/
  6059. /*! msb/lsb align for raw 10 and raw 12 formats control */
  6060. /*! 0: MSB aligned for RAW10 and RAW12 formats */
  6061. /*! 1: LSB aligned for RAW10 and RAW12 formats */
  6062. #define MRV_MI_LSB_ALIGNMENT
  6063. #define MRV_MI_LSB_ALIGNMENT_MASK 0x00000001U
  6064. #define MRV_MI_LSB_ALIGNMENT_SHIFT 0U
  6065. #endif
  6066. #ifdef ISP_MI_BYTESWAP
  6067. /*! Slice mp_byte_swap:*/
  6068. /*! swap bytes for ISP Nano */
  6069. /*! bit 0 to swap bytes */
  6070. /*! bit 1 to swap words */
  6071. /*! bit 2 to swap dwords */
  6072. /*! 3'b001: ABCDEFGH => BADCFEHG */
  6073. /*! 3'b000: ABCDEFGH => ABCDEFGH */
  6074. /*! 3'b010: ABCDEFGH => CDABGHEF */
  6075. /*! 3'b011: ABCDEFGH => DCBAHGFE */
  6076. /*! 3'b100: ABCDEFGH => EFGHABCD */
  6077. /*! 3'b101: ABCDEFGH => FEHGBADC */
  6078. /*! 3'b110: ABCDEFGH => GHEFCDAB */
  6079. /*! 3'b111: ABCDEFGH => HGFEDCBA */
  6080. #define MRV_MI_MP_BYTE_SWAP
  6081. #define MRV_MI_MP_BYTE_SWAP_MASK 0x0000000EU
  6082. #define MRV_MI_MP_BYTE_SWAP_SHIFT 1U
  6083. #endif
  6084. #ifdef ISP_MI_FIFO_DEPTH_NANO
  6085. /*! Register mi_mp_output_fifo_size for isp nano: (0x00000160)*/
  6086. /*! Slice output_fifo_depth:*/
  6087. /*! Select output FIFO depth setting */
  6088. /*! 00: FULL(2KBytes)*/
  6089. /*! 01: HALF(1KBytes)*/
  6090. /*! 10: 1/4(512Bytes)*/
  6091. /*! 11: 1/8(256Bytes)*/
  6092. #define MRV_MI_OUTOUT_FIFO_DEPTH
  6093. #define MRV_MI_OUTOUT_FIFO_DEPTH_MASK 0x00000003U
  6094. #define MRV_MI_OUTOUT_FIFO_DEPTH_SHIFT 0U
  6095. #endif
  6096. #ifdef ISP_MI_HANDSHAKE_NANO
  6097. /*! Register mi_mp_y_pic_width: IspNano handshake mp_y_pic_width (0x00000164)*/
  6098. /*! Slice mi_mp_y_pic_width:*/
  6099. /*! Image width of the main picture Y component in pixel.*/
  6100. #define MRV_MI_MP_HANDSHK_Y_PIC_WIDTH
  6101. #define MRV_MI_MP_HANDSHK_Y_PIC_WIDTH_MASK 0xFFFFFFFFU
  6102. #define MRV_MI_MP_HANDSHK_Y_PIC_WIDTH_SHIFT 0U
  6103. /*! Register mi_mp_y_pic_height: IspNano handshake mp_y_pic_height (0x00000168)*/
  6104. /*! Slice mi_mp_y_pic_height:*/
  6105. /*! Image height of the main picture Y component in pixel.*/
  6106. #define MRV_MI_MP_HANDSHK_Y_PIC_HEIGHT
  6107. #define MRV_MI_MP_HANDSHK_Y_PIC_HEIGHT_MASK 0xFFFFFFFFU
  6108. #define MRV_MI_MP_HANDSHK_Y_PIC_HEIGHT_SHIFT 0U
  6109. /*! Register mi_mp_y_pic_size: IspNano handshake mp_y_pic_size (0x0000016C)*/
  6110. /*! Slice mi_mp_y_pic_size */
  6111. /*! Image size of the Y component in pixel which has to be the Y line length multipled by */
  6112. /*! the Y image height(mp_y_llength*mp_y_pic_height)*/
  6113. #define MRV_MI_MP_HANDSHK_Y_PIC_ZISE
  6114. #define MRV_MI_MP_HANDSHK_Y_PIC_ZISE_MASK 0xFFFFFFFFU
  6115. #define MRV_MI_MP_HANDSHK_Y_PIC_ZISE_SHIFT 0U
  6116. #endif
  6117. /*! Register: jpe_gen_header: command to start stream header generation (0x00000000)*/
  6118. /*! Slice: gen_header:*/
  6119. /*! "1" = Start command to generate stream header;*/
  6120. /* auto reset to zero after one clock cycle */
  6121. #define MRV_JPE_GEN_HEADER
  6122. #define MRV_JPE_GEN_HEADER_MASK 0x00000001U
  6123. #define MRV_JPE_GEN_HEADER_SHIFT 0U
  6124. /*! Register: jpe_encode: Start command to start JFIF stream encoding (0x00000004)*/
  6125. /*! Slice: encode:*/
  6126. /*! "1" = Start command to start JFIF stream encoding;*/
  6127. /* auto reset to zero after one clock cycle.*/
  6128. /* This bit is write-only: reading result is always zero!*/
  6129. #define MRV_JPE_ENCODE
  6130. #define MRV_JPE_ENCODE_MASK 0x00000001U
  6131. #define MRV_JPE_ENCODE_SHIFT 0U
  6132. /*! Register: jpe_init: Automatic configuration update (INIT) (0x00000008)*/
  6133. /*! Slice: JP_INIT:*/
  6134. /*! "1" = Immediate start of JPEG encoder.*/
  6135. /* This bit has to be set after "Encode" to start the JPEG encoder. The "Encode" command becomes active either with JP_INIT or with the input signal "CFG_UPD".*/
  6136. /* auto reset to zero after one clock cycle !!!*/
  6137. #define MRV_JPE_JP_INIT
  6138. #define MRV_JPE_JP_INIT_MASK 0x00000001U
  6139. #define MRV_JPE_JP_INIT_SHIFT 0U
  6140. /*! Register: jpe_y_scale_en: Y value scaling control register (0x0000000c)*/
  6141. /*! Slice: y_scale_en:*/
  6142. /*! Y scale flag */
  6143. /* 1: scaling Y input from[16..235] to[0..255]*/
  6144. /* 0: no Y input scaling */
  6145. #define MRV_JPE_Y_SCALE_EN
  6146. #define MRV_JPE_Y_SCALE_EN_MASK 0x00000001U
  6147. #define MRV_JPE_Y_SCALE_EN_SHIFT 0U
  6148. /*! Register: jpe_cbcr_scale_en: Cb/Cr value scaling control register (0x00000010)*/
  6149. /*! Slice: cbcr_scale_en:*/
  6150. /*! Cb/Cr scale flag */
  6151. /* 1: scaling Cb/Cr input from[16..240] to[0..255]*/
  6152. /* 0: no Cb/Cr input scaling */
  6153. #define MRV_JPE_CBCR_SCALE_EN
  6154. #define MRV_JPE_CBCR_SCALE_EN_MASK 0x00000001U
  6155. #define MRV_JPE_CBCR_SCALE_EN_SHIFT 0U
  6156. /*! Register: jpe_table_flush: header generation debug register (0x00000014)*/
  6157. /*! Slice: table_flush:*/
  6158. /*! header generation debug control flag */
  6159. /* (controls transmission of last header bytes if the 64 bit output buffer is not completely filled)*/
  6160. /* 1: immediately transmit last header bytes */
  6161. /* 0: wait for encoded image data to fill output buffer */
  6162. #define MRV_JPE_TABLE_FLUSH
  6163. #define MRV_JPE_TABLE_FLUSH_MASK 0x00000001U
  6164. #define MRV_JPE_TABLE_FLUSH_SHIFT 0U
  6165. /*! Register: jpe_enc_hsize: JPEG codec horizontal image size for encoding (0x00000018)*/
  6166. /*! Slice: enc_hsize:*/
  6167. /*! JPEG codec horizontal image size for R2B and SGEN blocks.*/
  6168. /* Note: If the active camerIC version does not support 64 megapixel only those bits will be used which are required and the respective most significant bits will be ignored. Example: 5MP camerIC uses only bits[12:0] and ignores bits[14:13].*/
  6169. #define MRV_JPE_ENC_HSIZE
  6170. #define MRV_JPE_ENC_HSIZE_MASK 0x00007FFFU
  6171. #define MRV_JPE_ENC_HSIZE_SHIFT 0U
  6172. /*! Register: jpe_enc_vsize: JPEG codec vertical image size for encoding (0x0000001c)*/
  6173. /*! Slice: enc_vsize:*/
  6174. /*! JPEG codec vertical image size for R2B and SGEN blocks */
  6175. #define MRV_JPE_ENC_VSIZE
  6176. #define MRV_JPE_ENC_VSIZE_MASK 0x00003FFFU
  6177. #define MRV_JPE_ENC_VSIZE_SHIFT 0U
  6178. /*! Register: jpe_pic_format: JPEG picture encoding format (0x00000020)*/
  6179. /*! Slice: enc_pic_format:*/
  6180. /*! "0:0:1" = 4:2:2 format */
  6181. /* "1:x:x" = 4:0:0 format */
  6182. #define MRV_JPE_ENC_PIC_FORMAT
  6183. #define MRV_JPE_ENC_PIC_FORMAT_MASK 0x00000007U
  6184. #define MRV_JPE_ENC_PIC_FORMAT_SHIFT 0U
  6185. /*! Register: jpe_restart_interval: restart marker insertion register (0x00000024)*/
  6186. /*! Slice: restart_interval:*/
  6187. /*! No of MCU in reset interval via host */
  6188. #define MRV_JPE_RESTART_INTERVAL
  6189. #define MRV_JPE_RESTART_INTERVAL_MASK 0x0000FFFFU
  6190. #define MRV_JPE_RESTART_INTERVAL_SHIFT 0U
  6191. /*! Register: jpe_tq_y_select: Q- table selector 0, quant. table for Y component (0x00000028)*/
  6192. /*! Slice: tq0_select:*/
  6193. /*! "00" = qtable 0 */
  6194. /* "01" = qtable 1 */
  6195. /* "10" = qtable 2 */
  6196. /* "11" = qtable 3 */
  6197. #define MRV_JPE_TQ0_SELECT
  6198. #define MRV_JPE_TQ0_SELECT_MASK 0x00000003U
  6199. #define MRV_JPE_TQ0_SELECT_SHIFT 0U
  6200. /*! Register: jpe_tq_u_select: Q- table selector 1, quant. table for U component (0x0000002c)*/
  6201. /*! Slice: tq1_select:*/
  6202. /*! "00" = qtable 0 */
  6203. /* "01" = qtable 1 */
  6204. /* "10" = qtable 2 */
  6205. /* "11" = qtable 3 */
  6206. #define MRV_JPE_TQ1_SELECT
  6207. #define MRV_JPE_TQ1_SELECT_MASK 0x00000003U
  6208. #define MRV_JPE_TQ1_SELECT_SHIFT 0U
  6209. /*! Register: jpe_tq_v_select: Q- table selector 2, quant. table for V component (0x00000030)*/
  6210. /*! Slice: tq2_select:*/
  6211. /*! "00" = qtable 0 */
  6212. /* "01" = qtable 1 */
  6213. /* "10" = qtable 2 */
  6214. /* "11" = qtable 3 */
  6215. #define MRV_JPE_TQ2_SELECT
  6216. #define MRV_JPE_TQ2_SELECT_MASK 0x00000003U
  6217. #define MRV_JPE_TQ2_SELECT_SHIFT 0U
  6218. /*! Register: jpe_dc_table_select: Huffman table selector for DC values (0x00000034)*/
  6219. /*! Slice: dc_table_select_v:*/
  6220. /*! "0" = dc table 0; color component 2 (V)*/
  6221. /* "1" = dc table 1; color component 2 (V)*/
  6222. #define MRV_JPE_DC_TABLE_SELECT_V
  6223. #define MRV_JPE_DC_TABLE_SELECT_V_MASK 0x00000004U
  6224. #define MRV_JPE_DC_TABLE_SELECT_V_SHIFT 2U
  6225. /*! Slice: dc_table_select_u:*/
  6226. /*! "0" = dc table 0; color component 1 (U)*/
  6227. /* "1" = dc table 1; color component 1 (U)*/
  6228. #define MRV_JPE_DC_TABLE_SELECT_U
  6229. #define MRV_JPE_DC_TABLE_SELECT_U_MASK 0x00000002U
  6230. #define MRV_JPE_DC_TABLE_SELECT_U_SHIFT 1U
  6231. /*! Slice: dc_table_select_y:*/
  6232. /*! "0" = dc table 0; color component 0 (Y)*/
  6233. /* "1" = dc table 1; color component 0 (Y)*/
  6234. #define MRV_JPE_DC_TABLE_SELECT_Y
  6235. #define MRV_JPE_DC_TABLE_SELECT_Y_MASK 0x00000001U
  6236. #define MRV_JPE_DC_TABLE_SELECT_Y_SHIFT 0U
  6237. /*! Register: jpe_ac_table_select: Huffman table selector for AC values (0x00000038)*/
  6238. /*! Slice: ac_table_select_v:*/
  6239. /*! "0" = ac table 0; component 2 (V)*/
  6240. /* "1" = ac table 1; component 2 (V)*/
  6241. #define MRV_JPE_AC_TABLE_SELECT_V
  6242. #define MRV_JPE_AC_TABLE_SELECT_V_MASK 0x00000004U
  6243. #define MRV_JPE_AC_TABLE_SELECT_V_SHIFT 2U
  6244. /*! Slice: ac_table_select_u:*/
  6245. /*! "0" = ac table 0; component 1 (U)*/
  6246. /* "1" = ac table 1; component 1 (U)*/
  6247. #define MRV_JPE_AC_TABLE_SELECT_U
  6248. #define MRV_JPE_AC_TABLE_SELECT_U_MASK 0x00000002U
  6249. #define MRV_JPE_AC_TABLE_SELECT_U_SHIFT 1U
  6250. /*! Slice: ac_table_select_y:*/
  6251. /*! "0" = ac table 0; component 0 (Y)*/
  6252. /* "1" = ac table 1; component 0 (Y)*/
  6253. #define MRV_JPE_AC_TABLE_SELECT_Y
  6254. #define MRV_JPE_AC_TABLE_SELECT_Y_MASK 0x00000001U
  6255. #define MRV_JPE_AC_TABLE_SELECT_Y_SHIFT 0U
  6256. /*! Register: jpe_table_data: table programming register (0x0000003c)*/
  6257. /*! Slice: table_wdata_h:*/
  6258. /*! Table data MSB */
  6259. #define MRV_JPE_TABLE_WDATA_H
  6260. #define MRV_JPE_TABLE_WDATA_H_MASK 0x0000FF00U
  6261. #define MRV_JPE_TABLE_WDATA_H_SHIFT 8U
  6262. /*! Slice: table_wdata_l:*/
  6263. /*! Table data LSB */
  6264. #define MRV_JPE_TABLE_WDATA_L
  6265. #define MRV_JPE_TABLE_WDATA_L_MASK 0x000000FFU
  6266. #define MRV_JPE_TABLE_WDATA_L_SHIFT 0U
  6267. /*! Register: jpe_table_id: table programming select register (0x00000040)*/
  6268. /*! Slice: table_id:*/
  6269. /*! select table */
  6270. /* "0000" : Q-table 0 */
  6271. /* "0001" : Q-table 1 */
  6272. /* "0010" : Q-table 2 */
  6273. /* "0011" : Q-table 3 */
  6274. /* "0100" : VLC DC-table 0 */
  6275. /* "0101" : VLC AC-table 0 */
  6276. /* "0110" : VLC DC-table 1 */
  6277. /* "0111" : VLC AC-table 1 */
  6278. /* "1xxx" : reserved for debug */
  6279. #define MRV_JPE_TABLE_ID
  6280. #define MRV_JPE_TABLE_ID_MASK 0x0000000FU
  6281. #define MRV_JPE_TABLE_ID_SHIFT 0U
  6282. /*! Register: jpe_tac0_len: Huffman AC table 0 length (0x00000044)*/
  6283. /*! Slice: tac0_len:*/
  6284. /*! Huffman table length for ac0 table */
  6285. #define MRV_JPE_TAC0_LEN
  6286. #define MRV_JPE_TAC0_LEN_MASK 0x000000FFU
  6287. #define MRV_JPE_TAC0_LEN_SHIFT 0U
  6288. /*! Register: jpe_tdc0_len: Huffman DC table 0 length (0x00000048)*/
  6289. /*! Slice: tdc0_len:*/
  6290. /*! Huffman table length for dc0 table */
  6291. #define MRV_JPE_TDC0_LEN
  6292. #define MRV_JPE_TDC0_LEN_MASK 0x000000FFU
  6293. #define MRV_JPE_TDC0_LEN_SHIFT 0U
  6294. /*! Register: jpe_tac1_len: Huffman AC table 1 length (0x0000004c)*/
  6295. /*! Slice: tac1_len:*/
  6296. /*! Huffman table length for ac1 table */
  6297. #define MRV_JPE_TAC1_LEN
  6298. #define MRV_JPE_TAC1_LEN_MASK 0x000000FFU
  6299. #define MRV_JPE_TAC1_LEN_SHIFT 0U
  6300. /*! Register: jpe_tdc1_len: Huffman DC table 1 length (0x00000050)*/
  6301. /*! Slice: tdc1_len:*/
  6302. /*! Huffman table length for dc1 table */
  6303. #define MRV_JPE_TDC1_LEN
  6304. #define MRV_JPE_TDC1_LEN_MASK 0x000000FFU
  6305. #define MRV_JPE_TDC1_LEN_SHIFT 0U
  6306. /*! Register: jpe_encoder_busy: encoder status flag (0x00000058)*/
  6307. /*! Slice: codec_busy:*/
  6308. /*! Bit 0 = "1" : JPEG codec in process */
  6309. #define MRV_JPE_CODEC_BUSY
  6310. #define MRV_JPE_CODEC_BUSY_MASK 0x00000001U
  6311. #define MRV_JPE_CODEC_BUSY_SHIFT 0U
  6312. /*! Register: jpe_header_mode: header mode definition (0x0000005c)*/
  6313. /*! Slice: header_mode:*/
  6314. /*! "00" = no header */
  6315. /* "01" = reserved */
  6316. /* "10" = JFIF 1.02 header */
  6317. /* "11" = reserved */
  6318. #define MRV_JPE_HEADER_MODE
  6319. #define MRV_JPE_HEADER_MODE_MASK 0x00000003U
  6320. #define MRV_JPE_HEADER_MODE_SHIFT 0U
  6321. /*! Register: jpe_encode_mode: encode mode (0x00000060)*/
  6322. /*! Slice: encode_mode:*/
  6323. /*! Always "1", because this is the encoder only edition */
  6324. #define MRV_JPE_ENCODE_MODE
  6325. #define MRV_JPE_ENCODE_MODE_MASK 0x00000001U
  6326. #define MRV_JPE_ENCODE_MODE_SHIFT 0U
  6327. /*! Register: jpe_debug: debug information register (0x00000064)*/
  6328. /*! Slice: deb_bad_table_access:*/
  6329. /*! Debug signal only (set if an access to the TABLE_DATA or to the TABLE_ID register is performed, when the JPEG_ENCODER is busy. In this case a default PVCI Acknowledge is generated. Thus the configuration bus is not blocked)*/
  6330. #define MRV_JPE_DEB_BAD_TABLE_ACCESS
  6331. #define MRV_JPE_DEB_BAD_TABLE_ACCESS_MASK 0x00000100U
  6332. #define MRV_JPE_DEB_BAD_TABLE_ACCESS_SHIFT 8U
  6333. /*! Slice: deb_vlc_table_busy:*/
  6334. /*! Debug signal only (vlc access to huff-tables)*/
  6335. #define MRV_JPE_DEB_VLC_TABLE_BUSY
  6336. #define MRV_JPE_DEB_VLC_TABLE_BUSY_MASK 0x00000020U
  6337. #define MRV_JPE_DEB_VLC_TABLE_BUSY_SHIFT 5U
  6338. /*! Slice: deb_r2b_memory_full:*/
  6339. /*! Debug signal only (line memory status of r2b)*/
  6340. #define MRV_JPE_DEB_R2B_MEMORY_FULL
  6341. #define MRV_JPE_DEB_R2B_MEMORY_FULL_MASK 0x00000010U
  6342. #define MRV_JPE_DEB_R2B_MEMORY_FULL_SHIFT 4U
  6343. /*! Slice: deb_vlc_encode_busy:*/
  6344. /*! Debug signal only (vlc encode processing active)*/
  6345. #define MRV_JPE_DEB_VLC_ENCODE_BUSY
  6346. #define MRV_JPE_DEB_VLC_ENCODE_BUSY_MASK 0x00000008U
  6347. #define MRV_JPE_DEB_VLC_ENCODE_BUSY_SHIFT 3U
  6348. /*! Slice: deb_qiq_table_acc:*/
  6349. /*! Debug signal only (QIQ table access)*/
  6350. #define MRV_JPE_DEB_QIQ_TABLE_ACC
  6351. #define MRV_JPE_DEB_QIQ_TABLE_ACC_MASK 0x00000004U
  6352. #define MRV_JPE_DEB_QIQ_TABLE_ACC_SHIFT 2U
  6353. /*! Register: jpe_error_imr: JPEG error interrupt mask register (0x00000068)*/
  6354. /*! Slice: vlc_table_err:*/
  6355. /*! "1" = interrupt is activated (masked in)*/
  6356. #define MRV_JPE_VLC_TABLE_ERR
  6357. #define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U
  6358. #define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U
  6359. /*! Slice: r2b_IMG_size_err:*/
  6360. /*! "1" = interrupt is activated (masked in)*/
  6361. #define MRV_JPE_R2B_IMG_SIZE_ERR
  6362. #define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U
  6363. #define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U
  6364. /*! Slice: DCT_ERR:*/
  6365. /*! "1" = interrupt is activated (masked in)*/
  6366. #define MRV_JPE_DCT_ERR
  6367. #define MRV_JPE_DCT_ERR_MASK 0x00000080U
  6368. #define MRV_JPE_DCT_ERR_SHIFT 7U
  6369. /*! Slice: vlc_symbol_err:*/
  6370. /*! "1" = interrupt is activated (masked in)*/
  6371. #define MRV_JPE_VLC_SYMBOL_ERR
  6372. #define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U
  6373. #define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U
  6374. /*! Register: jpe_error_ris: JPEG error raw interrupt status register (0x0000006c)*/
  6375. /*! Slice: vlc_table_err:*/
  6376. /*! "1" = illegal table detected */
  6377. #define MRV_JPE_VLC_TABLE_ERR
  6378. #define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U
  6379. #define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U
  6380. /*! Slice: r2b_IMG_size_err:*/
  6381. /*! "1" = mismatch of predefined h_size and v_size values with calculated values (encode mode)*/
  6382. #define MRV_JPE_R2B_IMG_SIZE_ERR
  6383. #define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U
  6384. #define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U
  6385. /*! Slice: DCT_ERR:*/
  6386. /*! "1" = block start mismatch */
  6387. #define MRV_JPE_DCT_ERR
  6388. #define MRV_JPE_DCT_ERR_MASK 0x00000080U
  6389. #define MRV_JPE_DCT_ERR_SHIFT 7U
  6390. /*! Slice: vlc_symbol_err:*/
  6391. /*! "1" = illegal symbol detected (encoding)*/
  6392. #define MRV_JPE_VLC_SYMBOL_ERR
  6393. #define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U
  6394. #define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U
  6395. /*! Register: jpe_error_mis: JPEG error masked interrupt status register (0x00000070)*/
  6396. /*! Slice: vlc_table_err:*/
  6397. /*! "1" = illegal table detected */
  6398. #define MRV_JPE_VLC_TABLE_ERR
  6399. #define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U
  6400. #define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U
  6401. /*! Slice: r2b_IMG_size_err:*/
  6402. /*! "1" = mismatch of predefined h_size and v_size values with calculated values (encode mode)*/
  6403. #define MRV_JPE_R2B_IMG_SIZE_ERR
  6404. #define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U
  6405. #define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U
  6406. /*! Slice: DCT_ERR:*/
  6407. /*! "1" = block start mismatch */
  6408. #define MRV_JPE_DCT_ERR
  6409. #define MRV_JPE_DCT_ERR_MASK 0x00000080U
  6410. #define MRV_JPE_DCT_ERR_SHIFT 7U
  6411. /*! Slice: vlc_symbol_err:*/
  6412. /*! "1" = illegal symbol detected (encoding)*/
  6413. #define MRV_JPE_VLC_SYMBOL_ERR
  6414. #define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U
  6415. #define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U
  6416. /*! Register: jpe_error_icr: JPEG error interrupt set register (0x00000074)*/
  6417. /*! Slice: vlc_table_err:*/
  6418. /*! "1" = set error bit, bit is reset to zero after 1 clk */
  6419. #define MRV_JPE_VLC_TABLE_ERR
  6420. #define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U
  6421. #define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U
  6422. /*! Slice: r2b_IMG_size_err:*/
  6423. /*! "1" = set error bit, bit is reset to zero after 1 clk */
  6424. #define MRV_JPE_R2B_IMG_SIZE_ERR
  6425. #define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U
  6426. #define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U
  6427. /*! Slice: DCT_ERR:*/
  6428. /*! "1" = set error bit, bit is reset to zero after 1 clk */
  6429. #define MRV_JPE_DCT_ERR
  6430. #define MRV_JPE_DCT_ERR_MASK 0x00000080U
  6431. #define MRV_JPE_DCT_ERR_SHIFT 7U
  6432. /*! Slice: vlc_symbol_err:*/
  6433. /*! "1" = set error bit, bit is reset to zero after 1 clk */
  6434. #define MRV_JPE_VLC_SYMBOL_ERR
  6435. #define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U
  6436. #define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U
  6437. /*! Register: jpe_error_isr: JPEG error interrupt clear register (0x00000078)*/
  6438. /*! Slice: vlc_table_err:*/
  6439. /*! "1" = clear status bit, bit is reset to zero after 1 clk */
  6440. #define MRV_JPE_VLC_TABLE_ERR
  6441. #define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400U
  6442. #define MRV_JPE_VLC_TABLE_ERR_SHIFT 10U
  6443. /*! Slice: r2b_IMG_size_err:*/
  6444. /*! "1" = clear status bit, bit is reset to zero after 1 clk */
  6445. #define MRV_JPE_R2B_IMG_SIZE_ERR
  6446. #define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200U
  6447. #define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9U
  6448. /*! Slice: dct_err:*/
  6449. /*! "1" = clear status bit, bit is reset to zero after 1 clk */
  6450. #define MRV_JPE_DCT_ERR
  6451. #define MRV_JPE_DCT_ERR_MASK 0x00000080U
  6452. #define MRV_JPE_DCT_ERR_SHIFT 7U
  6453. /*! Slice: vlc_symbol_err:*/
  6454. /*! "1" = clear status bit, bit is reset to zero after 1 clk */
  6455. #define MRV_JPE_VLC_SYMBOL_ERR
  6456. #define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010U
  6457. #define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4U
  6458. /*! Register: jpe_status_imr: JPEG status interrupt mask register (0x0000007c)*/
  6459. /*! Slice: gen_header_done:*/
  6460. /*! "1" = interrupt is activated (masked in)*/
  6461. #define MRV_JPE_GEN_HEADER_DONE
  6462. #define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U
  6463. #define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U
  6464. /*! Slice: encode_done:*/
  6465. /*! "1" = interrupt is activated (masked in)*/
  6466. #define MRV_JPE_ENCODE_DONE
  6467. #define MRV_JPE_ENCODE_DONE_MASK 0x00000010U
  6468. #define MRV_JPE_ENCODE_DONE_SHIFT 4U
  6469. /*! Register: jpe_status_ris: JPEG status raw interrupt status register (0x00000080)*/
  6470. /*! Slice: gen_header_done:*/
  6471. /*! "1" = Stream header generation finished */
  6472. #define MRV_JPE_GEN_HEADER_DONE
  6473. #define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U
  6474. #define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U
  6475. /*! Slice: encode_done:*/
  6476. /*! "1" = Encode processing finished */
  6477. #define MRV_JPE_ENCODE_DONE
  6478. #define MRV_JPE_ENCODE_DONE_MASK 0x00000010U
  6479. #define MRV_JPE_ENCODE_DONE_SHIFT 4U
  6480. /*! Register: jpe_status_mis: JPEG status masked interrupt status register (0x00000084)*/
  6481. /*! Slice: gen_header_done:*/
  6482. /*! "1" = Stream header generation finished */
  6483. #define MRV_JPE_GEN_HEADER_DONE
  6484. #define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U
  6485. #define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U
  6486. /*! Slice: encode_done:*/
  6487. /*! "1" = Encode processing finished */
  6488. #define MRV_JPE_ENCODE_DONE
  6489. #define MRV_JPE_ENCODE_DONE_MASK 0x00000010U
  6490. #define MRV_JPE_ENCODE_DONE_SHIFT 4U
  6491. /*! Register: jpe_status_icr: JPEG status interrupt clear register (0x00000088)*/
  6492. /*! Slice: gen_header_done:*/
  6493. /*! "1" = clear status bit, bit is reset to zero after 1 clk */
  6494. #define MRV_JPE_GEN_HEADER_DONE
  6495. #define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U
  6496. #define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U
  6497. /*! Slice: encode_done:*/
  6498. /*! "1" = clear status bit, bit is reset to zero after 1 clk */
  6499. #define MRV_JPE_ENCODE_DONE
  6500. #define MRV_JPE_ENCODE_DONE_MASK 0x00000010U
  6501. #define MRV_JPE_ENCODE_DONE_SHIFT 4U
  6502. /*! Register: jpe_status_isr: JPEG status interrupt set register (0x0000008c)*/
  6503. /*! Slice: gen_header_done:*/
  6504. /*! "1" = set error bit, bit is reset to zero after 1 clk */
  6505. #define MRV_JPE_GEN_HEADER_DONE
  6506. #define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020U
  6507. #define MRV_JPE_GEN_HEADER_DONE_SHIFT 5U
  6508. /*! Slice: encode_done:*/
  6509. /*! "1" = set error bit, bit is reset to zero after 1 clk */
  6510. #define MRV_JPE_ENCODE_DONE
  6511. #define MRV_JPE_ENCODE_DONE_MASK 0x00000010U
  6512. #define MRV_JPE_ENCODE_DONE_SHIFT 4U
  6513. /*! Register: jpe_config: JPEG configuration register (0x00000090)*/
  6514. /*! Slice: speedview_en:*/
  6515. /*! 1: speed view enabled */
  6516. /* 0: speed view disabled */
  6517. #define MRV_JPE_SPEEDVIEW_EN
  6518. #define MRV_JPE_SPEEDVIEW_EN_MASK 0x00000010U
  6519. #define MRV_JPE_SPEEDVIEW_EN_SHIFT 4U
  6520. /*! Slice: cont_mode:*/
  6521. /*! Encoder continous mode */
  6522. /* "00": encoder stops at frame end (corresponds to former behavior)*/
  6523. /* "01": encoder starts automatically to encode the next frame */
  6524. /* "10": unused */
  6525. /* "11": encoder first generates next header and then encodes automatically the next frame */
  6526. /* These settings are checked after encoding one frame. They are not auto-reset by hardware.*/
  6527. #define MRV_JPE_CONT_MODE
  6528. #define MRV_JPE_CONT_MODE_MASK 0x00000003U
  6529. #define MRV_JPE_CONT_MODE_SHIFT 0U
  6530. /*! Register: smia_ctrl: global control register (0x00000000)*/
  6531. /*! Slice: DMA_CHANNEL_SEL:*/
  6532. /*! DMA channel selector for image data output */
  6533. #define MRV_SMIA_DMA_CHANNEL_SEL
  6534. #define MRV_SMIA_DMA_CHANNEL_SEL_MASK 0x00000700U
  6535. #define MRV_SMIA_DMA_CHANNEL_SEL_SHIFT 8U
  6536. /*! Slice: SHUTDOWN_LANE:*/
  6537. /*! Shutdown Lane Module. Content of this register is directly connected to the output signal shutdown */
  6538. #define MRV_SMIA_SHUTDOWN_LANE
  6539. #define MRV_SMIA_SHUTDOWN_LANE_MASK 0x00000008U
  6540. #define MRV_SMIA_SHUTDOWN_LANE_SHIFT 3U
  6541. /*! Slice: CFG_UPD_ENA:*/
  6542. /*! enables generation of cfg_upd signal at frame end */
  6543. #define MRV_SMIA_CFG_UPD_ENA
  6544. #define MRV_SMIA_CFG_UPD_ENA_MASK 0x00000004U
  6545. #define MRV_SMIA_CFG_UPD_ENA_SHIFT 2U
  6546. /*! Slice: FLUSH_FIFO:*/
  6547. /*! writing '1' resets the write- and read pointers of the embedded data fifo.*/
  6548. #define MRV_SMIA_FLUSH_FIFO
  6549. #define MRV_SMIA_FLUSH_FIFO_MASK 0x00000002U
  6550. #define MRV_SMIA_FLUSH_FIFO_SHIFT 1U
  6551. /*! Slice: OUTPUT_ENA:*/
  6552. /*! '1': transmission to alomics output interface is enabled */
  6553. /* '0': transmission is disabled */
  6554. #define MRV_SMIA_OUTPUT_ENA
  6555. #define MRV_SMIA_OUTPUT_ENA_MASK 0x00000001U
  6556. #define MRV_SMIA_OUTPUT_ENA_SHIFT 0U
  6557. /*! Register: smia_status: global status register (0x00000004)*/
  6558. /*! Slice: DMA_CHANNEL:*/
  6559. /*! DMA channel of currently received packet */
  6560. #define MRV_SMIA_DMA_CHANNEL
  6561. #define MRV_SMIA_DMA_CHANNEL_MASK 0x00000700U
  6562. #define MRV_SMIA_DMA_CHANNEL_SHIFT 8U
  6563. /*! Slice: EMB_DATA_AVAIL:*/
  6564. /*! 1: embedded data fifo not empty */
  6565. #define MRV_SMIA_EMB_DATA_AVAIL
  6566. #define MRV_SMIA_EMB_DATA_AVAIL_MASK 0x00000001U
  6567. #define MRV_SMIA_EMB_DATA_AVAIL_SHIFT 0U
  6568. /*! Register: smia_imsc: Interrupt mask (0x00000008)*/
  6569. /*! Slice: IMSC_FIFO_FILL_LEVEL:*/
  6570. /*! enable interrupt (1) or mask out (0)*/
  6571. #define MRV_SMIA_IMSC_FIFO_FILL_LEVEL
  6572. #define MRV_SMIA_IMSC_FIFO_FILL_LEVEL_MASK 0x00000020U
  6573. #define MRV_SMIA_IMSC_FIFO_FILL_LEVEL_SHIFT 5U
  6574. /*! Slice: IMSC_SYNC_FIFO_OVFLW:*/
  6575. /*! enable interrupt (1) or mask out (0)*/
  6576. #define MRV_SMIA_IMSC_SYNC_FIFO_OVFLW
  6577. #define MRV_SMIA_IMSC_SYNC_FIFO_OVFLW_MASK 0x00000010U
  6578. #define MRV_SMIA_IMSC_SYNC_FIFO_OVFLW_SHIFT 4U
  6579. /*! Slice: IMSC_ERR_CS:*/
  6580. /*! enable interrupt (1) or mask out (0)*/
  6581. #define MRV_SMIA_IMSC_ERR_CS
  6582. #define MRV_SMIA_IMSC_ERR_CS_MASK 0x00000008U
  6583. #define MRV_SMIA_IMSC_ERR_CS_SHIFT 3U
  6584. /*! Slice: IMSC_ERR_PROTOCOL:*/
  6585. /*! enable interrupt (1) or mask out (0)*/
  6586. #define MRV_SMIA_IMSC_ERR_PROTOCOL
  6587. #define MRV_SMIA_IMSC_ERR_PROTOCOL_MASK 0x00000004U
  6588. #define MRV_SMIA_IMSC_ERR_PROTOCOL_SHIFT 2U
  6589. /*! Slice: IMSC_EMB_DATA_OVFLW:*/
  6590. /*! enable interrupt (1) or mask out (0)*/
  6591. #define MRV_SMIA_IMSC_EMB_DATA_OVFLW
  6592. #define MRV_SMIA_IMSC_EMB_DATA_OVFLW_MASK 0x00000002U
  6593. #define MRV_SMIA_IMSC_EMB_DATA_OVFLW_SHIFT 1U
  6594. /*! Slice: IMSC_FRAME_END:*/
  6595. /*! enable interrupt (1) or mask out (0)*/
  6596. #define MRV_SMIA_IMSC_FRAME_END
  6597. #define MRV_SMIA_IMSC_FRAME_END_MASK 0x00000001U
  6598. #define MRV_SMIA_IMSC_FRAME_END_SHIFT 0U
  6599. /*! Register: smia_ris: Raw interrupt status (0x0000000c)*/
  6600. /*! Slice: RIS_FIFO_FILL_LEVEL:*/
  6601. /*! Programmed fill level was reached; will be raised as long as the fill level is greater the programmed value */
  6602. #define MRV_SMIA_RIS_FIFO_FILL_LEVEL
  6603. #define MRV_SMIA_RIS_FIFO_FILL_LEVEL_MASK 0x00000020U
  6604. #define MRV_SMIA_RIS_FIFO_FILL_LEVEL_SHIFT 5U
  6605. /*! Slice: RIS_SYNC_FIFO_OVFLW:*/
  6606. /*! Sync fifo overflow error */
  6607. #define MRV_SMIA_RIS_SYNC_FIFO_OVFLW
  6608. #define MRV_SMIA_RIS_SYNC_FIFO_OVFLW_MASK 0x00000010U
  6609. #define MRV_SMIA_RIS_SYNC_FIFO_OVFLW_SHIFT 4U
  6610. /*! Slice: RIS_ERR_CS:*/
  6611. /*! Checksum error */
  6612. #define MRV_SMIA_RIS_ERR_CS
  6613. #define MRV_SMIA_RIS_ERR_CS_MASK 0x00000008U
  6614. #define MRV_SMIA_RIS_ERR_CS_SHIFT 3U
  6615. /*! Slice: RIS_ERR_PROTOCOL:*/
  6616. /*! Protocol error */
  6617. #define MRV_SMIA_RIS_ERR_PROTOCOL
  6618. #define MRV_SMIA_RIS_ERR_PROTOCOL_MASK 0x00000004U
  6619. #define MRV_SMIA_RIS_ERR_PROTOCOL_SHIFT 2U
  6620. /*! Slice: RIS_EMB_DATA_OVFLW:*/
  6621. /*! Embedded data fifo overflow error */
  6622. #define MRV_SMIA_RIS_EMB_DATA_OVFLW
  6623. #define MRV_SMIA_RIS_EMB_DATA_OVFLW_MASK 0x00000002U
  6624. #define MRV_SMIA_RIS_EMB_DATA_OVFLW_SHIFT 1U
  6625. /*! Slice: RIS_FRAME_END:*/
  6626. /*! Frame end reached */
  6627. #define MRV_SMIA_RIS_FRAME_END
  6628. #define MRV_SMIA_RIS_FRAME_END_MASK 0x00000001U
  6629. #define MRV_SMIA_RIS_FRAME_END_SHIFT 0U
  6630. /*! Register: smia_mis: Masked interrupt status (0x00000010)*/
  6631. /*! Slice: MIS_FIFO_FILL_LEVEL:*/
  6632. /*! Programmed fill level was reached; will be raised as long as the fill level is greater the programmed value */
  6633. #define MRV_SMIA_MIS_FIFO_FILL_LEVEL
  6634. #define MRV_SMIA_MIS_FIFO_FILL_LEVEL_MASK 0x00000020U
  6635. #define MRV_SMIA_MIS_FIFO_FILL_LEVEL_SHIFT 5U
  6636. /*! Slice: MIS_SYNC_FIFO_OVFLW:*/
  6637. /*! Sync fifo overflow error */
  6638. #define MRV_SMIA_MIS_SYNC_FIFO_OVFLW
  6639. #define MRV_SMIA_MIS_SYNC_FIFO_OVFLW_MASK 0x00000010U
  6640. #define MRV_SMIA_MIS_SYNC_FIFO_OVFLW_SHIFT 4U
  6641. /*! Slice: MIS_ERR_CS:*/
  6642. /*! Checksum error */
  6643. #define MRV_SMIA_MIS_ERR_CS
  6644. #define MRV_SMIA_MIS_ERR_CS_MASK 0x00000008U
  6645. #define MRV_SMIA_MIS_ERR_CS_SHIFT 3U
  6646. /*! Slice: MIS_ERR_PROTOCOL:*/
  6647. /*! Protocol error */
  6648. #define MRV_SMIA_MIS_ERR_PROTOCOL
  6649. #define MRV_SMIA_MIS_ERR_PROTOCOL_MASK 0x00000004U
  6650. #define MRV_SMIA_MIS_ERR_PROTOCOL_SHIFT 2U
  6651. /*! Slice: MIS_EMB_DATA_OVFLW:*/
  6652. /*! Embedded data fifo overflow error */
  6653. #define MRV_SMIA_MIS_EMB_DATA_OVFLW
  6654. #define MRV_SMIA_MIS_EMB_DATA_OVFLW_MASK 0x00000002U
  6655. #define MRV_SMIA_MIS_EMB_DATA_OVFLW_SHIFT 1U
  6656. /*! Slice: MIS_FRAME_END:*/
  6657. /*! Frame end reached */
  6658. #define MRV_SMIA_MIS_FRAME_END
  6659. #define MRV_SMIA_MIS_FRAME_END_MASK 0x00000001U
  6660. #define MRV_SMIA_MIS_FRAME_END_SHIFT 0U
  6661. /*! Register: smia_icr: Interrupt clear register (0x00000014)*/
  6662. /*! Slice: ICR_FIFO_FILL_LEVEL:*/
  6663. /*! Write '1': clear interrupt; Write '0': no effect */
  6664. #define MRV_SMIA_ICR_FIFO_FILL_LEVEL
  6665. #define MRV_SMIA_ICR_FIFO_FILL_LEVEL_MASK 0x00000020U
  6666. #define MRV_SMIA_ICR_FIFO_FILL_LEVEL_SHIFT 5U
  6667. /*! Slice: ICR_SYNC_FIFO_OVFLW:*/
  6668. /*! Write '1': clear interrupt; Write '0': no effect */
  6669. #define MRV_SMIA_ICR_SYNC_FIFO_OVFLW
  6670. #define MRV_SMIA_ICR_SYNC_FIFO_OVFLW_MASK 0x00000010U
  6671. #define MRV_SMIA_ICR_SYNC_FIFO_OVFLW_SHIFT 4U
  6672. /*! Slice: ICR_ERR_CS:*/
  6673. /*! Write '1': clear interrupt; Write '0': no effect */
  6674. #define MRV_SMIA_ICR_ERR_CS
  6675. #define MRV_SMIA_ICR_ERR_CS_MASK 0x00000008U
  6676. #define MRV_SMIA_ICR_ERR_CS_SHIFT 3U
  6677. /*! Slice: ICR_ERR_PROTOCOL:*/
  6678. /*! Write '1': clear interrupt; Write '0': no effect */
  6679. #define MRV_SMIA_ICR_ERR_PROTOCOL
  6680. #define MRV_SMIA_ICR_ERR_PROTOCOL_MASK 0x00000004U
  6681. #define MRV_SMIA_ICR_ERR_PROTOCOL_SHIFT 2U
  6682. /*! Slice: ICR_EMB_DATA_OVFLW:*/
  6683. /*! Write '1': clear interrupt; Write '0': no effect */
  6684. #define MRV_SMIA_ICR_EMB_DATA_OVFLW
  6685. #define MRV_SMIA_ICR_EMB_DATA_OVFLW_MASK 0x00000002U
  6686. #define MRV_SMIA_ICR_EMB_DATA_OVFLW_SHIFT 1U
  6687. /*! Slice: ICR_FRAME_END:*/
  6688. /*! Write '1': clear interrupt; Write '0': no effect */
  6689. #define MRV_SMIA_ICR_FRAME_END
  6690. #define MRV_SMIA_ICR_FRAME_END_MASK 0x00000001U
  6691. #define MRV_SMIA_ICR_FRAME_END_SHIFT 0U
  6692. /*! Register: smia_isr: Interrupt set register (0x00000018)*/
  6693. /*! Slice: ISR_FIFO_FILL_LEVEL:*/
  6694. /*! Write '1': set interrupt; Write '0': no effect */
  6695. #define MRV_SMIA_ISR_FIFO_FILL_LEVEL
  6696. #define MRV_SMIA_ISR_FIFO_FILL_LEVEL_MASK 0x00000020U
  6697. #define MRV_SMIA_ISR_FIFO_FILL_LEVEL_SHIFT 5U
  6698. /*! Slice: ISR_SYNC_FIFO_OVFLW:*/
  6699. /*! Write '1': set interrupt; Write '0': no effect */
  6700. #define MRV_SMIA_ISR_SYNC_FIFO_OVFLW
  6701. #define MRV_SMIA_ISR_SYNC_FIFO_OVFLW_MASK 0x00000010U
  6702. #define MRV_SMIA_ISR_SYNC_FIFO_OVFLW_SHIFT 4U
  6703. /*! Slice: ISR_ERR_CS:*/
  6704. /*! Write '1': set interrupt; Write '0': no effect */
  6705. #define MRV_SMIA_ISR_ERR_CS
  6706. #define MRV_SMIA_ISR_ERR_CS_MASK 0x00000008U
  6707. #define MRV_SMIA_ISR_ERR_CS_SHIFT 3U
  6708. /*! Slice: ISR_ERR_PROTOCOL:*/
  6709. /*! Write '1': set interrupt; Write '0': no effect */
  6710. #define MRV_SMIA_ISR_ERR_PROTOCOL
  6711. #define MRV_SMIA_ISR_ERR_PROTOCOL_MASK 0x00000004U
  6712. #define MRV_SMIA_ISR_ERR_PROTOCOL_SHIFT 2U
  6713. /*! Slice: ISR_EMB_DATA_OVFLW:*/
  6714. /*! Write '1': set interrupt; Write '0': no effect */
  6715. #define MRV_SMIA_ISR_EMB_DATA_OVFLW
  6716. #define MRV_SMIA_ISR_EMB_DATA_OVFLW_MASK 0x00000002U
  6717. #define MRV_SMIA_ISR_EMB_DATA_OVFLW_SHIFT 1U
  6718. /*! Slice: ISR_FRAME_END:*/
  6719. /*! Write '1': set interrupt; Write '0': no effect */
  6720. #define MRV_SMIA_ISR_FRAME_END
  6721. #define MRV_SMIA_ISR_FRAME_END_MASK 0x00000001U
  6722. #define MRV_SMIA_ISR_FRAME_END_SHIFT 0U
  6723. /*! Register: smia_data_format_sel: data format selector register (0x0000001c)*/
  6724. /*! Slice: DATA_FORMAT_SEL:*/
  6725. /*! data format selector:*/
  6726. /* 0x0: YUV 422 */
  6727. /* 0x1: YUV 420 */
  6728. /* 0x4: RGB 444 */
  6729. /* 0x5: RGB 565 */
  6730. /* 0x6: RGB 888 */
  6731. /* 0x8: RAW 6 */
  6732. /* 0x9: RAW 7 */
  6733. /* 0xA: RAW 8 */
  6734. /* 0xB: RAW 10 */
  6735. /* 0xC: RAW 12 */
  6736. /* 0xD: RAW 8-bit to 10-bit decompression */
  6737. /* 0xF: compressed */
  6738. /* 0x2, 0x3, 0x7, 0xE: reserved, no output */
  6739. #define MRV_SMIA_DATA_FORMAT_SEL
  6740. #define MRV_SMIA_DATA_FORMAT_SEL_MASK 0x0000000FU
  6741. #define MRV_SMIA_DATA_FORMAT_SEL_SHIFT 0U
  6742. /*! Register: smia_sof_emb_data_lines: start of frame embedded data lines register (0x00000020)*/
  6743. /*! Slice: SOF_EMB_DATA_LINES:*/
  6744. /*! number of embedded data lines at frame start */
  6745. #define MRV_SMIA_SOF_EMB_DATA_LINES
  6746. #define MRV_SMIA_SOF_EMB_DATA_LINES_MASK 0x00000007U
  6747. #define MRV_SMIA_SOF_EMB_DATA_LINES_SHIFT 0U
  6748. /*! Register: smia_emb_hstart: embedded data hstart register (0x00000024)*/
  6749. /*! Slice: EMB_HSTART:*/
  6750. /*! horizontal start position of captured embedded data.*/
  6751. /* Must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/
  6752. #define MRV_SMIA_EMB_HSTART
  6753. #define MRV_SMIA_EMB_HSTART_MASK 0x00007FFCU
  6754. #define MRV_SMIA_EMB_HSTART_SHIFT 2U
  6755. /*! Register: smia_emb_hsize: embedded data hsize register (0x00000028)*/
  6756. /*! Slice: EMB_HSIZE:*/
  6757. /*! number of captured embedded data dwords per line */
  6758. /* '0' means no capturing of embedded data.*/
  6759. /* Must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/
  6760. #define MRV_SMIA_EMB_HSIZE
  6761. #define MRV_SMIA_EMB_HSIZE_MASK 0x00007FFCU
  6762. #define MRV_SMIA_EMB_HSIZE_SHIFT 2U
  6763. /*! Register: smia_emb_vstart: embedded data vstart register (0x0000002c)*/
  6764. /*! Slice: EMB_VSTART:*/
  6765. /*! start line of embedded data extraction.*/
  6766. /* '0' means no capturing of embedded data */
  6767. #define MRV_SMIA_EMB_VSTART
  6768. #define MRV_SMIA_EMB_VSTART_MASK 0x00003FFFU
  6769. #define MRV_SMIA_EMB_VSTART_SHIFT 0U
  6770. /*! Register: smia_num_lines: image data lines register (0x00000030)*/
  6771. /*! Slice: NUM_LINES:*/
  6772. /*! number of image data lines per frame */
  6773. #define MRV_SMIA_NUM_LINES
  6774. #define MRV_SMIA_NUM_LINES_MASK 0x00003FFFU
  6775. #define MRV_SMIA_NUM_LINES_SHIFT 0U
  6776. /*! Register: smia_emb_data_fifo: Embedded Data Fifo (0x00000034)*/
  6777. /*! Slice: EMB_DATA_FIFO:*/
  6778. /*! lowest 4 bytes in embedded data fifo;*/
  6779. /* reading increments fifo read pointer.*/
  6780. /* First embedded data byte will be written to bits 7:0 of 32-bit data word, second data byte written to 15:8 etc.*/
  6781. #define MRV_SMIA_EMB_DATA_FIFO
  6782. #define MRV_SMIA_EMB_DATA_FIFO_MASK 0xFFFFFFFFU
  6783. #define MRV_SMIA_EMB_DATA_FIFO_SHIFT 0U
  6784. /*! Register: smia_fifo_fill_level: Embedded Data FIFO Fill Level (0x00000038)*/
  6785. /*! Slice: FIFO_FILL_LEVEL:*/
  6786. /*! FIFO level in dwords for triggering the fill level interrupt.*/
  6787. /* Must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/
  6788. #define MRV_SMIA_FIFO_FILL_LEVEL
  6789. #define MRV_SMIA_FIFO_FILL_LEVEL_MASK 0x000003FFU
  6790. #define MRV_SMIA_FIFO_FILL_LEVEL_SHIFT 0U
  6791. /*! Register: mipi_ctrl: global control register (0x00000000)*/
  6792. /*! Slice: S_ENABLE_CLK:*/
  6793. /*! Sensor clock lane enable signal. This register is directly connected to the output port "s_enableclk".*/
  6794. /* '1': enable sensor clock lane (DEFAULT)*/
  6795. /* '0': disable sensor clock lane */
  6796. #define MRV_MIPI_S_ENABLE_CLK
  6797. #define MRV_MIPI_S_ENABLE_CLK_MASK 0x00040000U
  6798. #define MRV_MIPI_S_ENABLE_CLK_SHIFT 18U
  6799. /*! Slice: ERR_SOT_SYNC_HS_SKIP:*/
  6800. /*! 1: data within the current transmission is skipped if ErrSotSyncHS is detected (default)*/
  6801. /* 0: ErrSotSyncHS does not affect transmission */
  6802. #define MRV_MIPI_ERR_SOT_SYNC_HS_SKIP
  6803. #define MRV_MIPI_ERR_SOT_SYNC_HS_SKIP_MASK 0x00020000U
  6804. #define MRV_MIPI_ERR_SOT_SYNC_HS_SKIP_SHIFT 17U
  6805. /*! Slice: ERR_SOT_HS_SKIP:*/
  6806. /*! 1: data within the current transmission is skipped if ErrSotHS is detected */
  6807. /* 0: ErrSotHS does not affect transmission (default)*/
  6808. #define MRV_MIPI_ERR_SOT_HS_SKIP
  6809. #define MRV_MIPI_ERR_SOT_HS_SKIP_MASK 0x00010000U
  6810. #define MRV_MIPI_ERR_SOT_HS_SKIP_SHIFT 16U
  6811. /*! Slice: NUM_LANES:*/
  6812. /*! 00: Lane 1 is used */
  6813. /* 01: Lanes 1 and 2 are used */
  6814. /* 10: Lanes 1, 2 and 3 are used */
  6815. /* 11: Lanes 1, 2, 3 and 4 are used (default)*/
  6816. #define MRV_MIPI_NUM_LANES
  6817. #define MRV_MIPI_NUM_LANES_MASK 0x00003000U
  6818. #define MRV_MIPI_NUM_LANES_SHIFT 12U
  6819. /*! Slice: SHUTDOWN_LANE:*/
  6820. /*! Shutdown Lane Module. Content of this register is directly connected to the output signal shutdown[n-1:0] where n denotes the lane number 1..4 */
  6821. #define MRV_MIPI_SHUTDOWN_LANE
  6822. #define MRV_MIPI_SHUTDOWN_LANE_MASK 0x00000F00U
  6823. #define MRV_MIPI_SHUTDOWN_LANE_SHIFT 8U
  6824. /*! Slice: FLUSH_FIFO:*/
  6825. /*! writing '1' resets the write- and read pointers of the additional data fifo, reading returns the status of the flush_fifo bit. This bit must be reset by software.*/
  6826. #define MRV_MIPI_FLUSH_FIFO
  6827. #define MRV_MIPI_FLUSH_FIFO_MASK 0x00000002U
  6828. #define MRV_MIPI_FLUSH_FIFO_SHIFT 1U
  6829. /*! Slice: OUTPUT_ENA:*/
  6830. /*! 1: output to add data fifo and to output interface is enabled */
  6831. /* 0: output is disabled */
  6832. #define MRV_MIPI_OUTPUT_ENA
  6833. #define MRV_MIPI_OUTPUT_ENA_MASK 0x00000001U
  6834. #define MRV_MIPI_OUTPUT_ENA_SHIFT 0U
  6835. /*! Register: mipi_status: global status register (0x00000004)*/
  6836. /*! Slice: S_ULP_ACTIVE_NOT_CLK:*/
  6837. /*! sensor clock lane is in ULP state. This register is directly connected to the synchronized input signal "s_ulpsactivenotclk"*/
  6838. #define MRV_MIPI_S_ULP_ACTIVE_NOT_CLK
  6839. #define MRV_MIPI_S_ULP_ACTIVE_NOT_CLK_MASK 0x00002000U
  6840. #define MRV_MIPI_S_ULP_ACTIVE_NOT_CLK_SHIFT 13U
  6841. /*! Slice: S_STOPSTATE_CLK:*/
  6842. /*! sensor clock lane is in stopstate. This register is directly connected to the synchronized input signal "s_stopstateclk"*/
  6843. #define MRV_MIPI_S_STOPSTATE_CLK
  6844. #define MRV_MIPI_S_STOPSTATE_CLK_MASK 0x00001000U
  6845. #define MRV_MIPI_S_STOPSTATE_CLK_SHIFT 12U
  6846. /*! Slice: STOPSTATE:*/
  6847. /*! Data Lane is in stopstate. This register is directly connected to the synchronized input signal stopstate[n-1:0] where n denotes the lane number 1..4 */
  6848. #define MRV_MIPI_STOPSTATE
  6849. #define MRV_MIPI_STOPSTATE_MASK 0x00000F00U
  6850. #define MRV_MIPI_STOPSTATE_SHIFT 8U
  6851. /*! Slice: ADD_DATA_AVAIL:*/
  6852. /*! 1: additional data fifo contains data */
  6853. /* 0: additional data fifo is empty */
  6854. #define MRV_MIPI_ADD_DATA_AVAIL
  6855. #define MRV_MIPI_ADD_DATA_AVAIL_MASK 0x00000001U
  6856. #define MRV_MIPI_ADD_DATA_AVAIL_SHIFT 0U
  6857. /*! Register: mipi_imsc: Interrupt mask (0x00000008)*/
  6858. /*! Slice: IMSC_GEN_SHORT_PACK:*/
  6859. /*! enable interrupt (1) or mask out (0)*/
  6860. #define MRV_MIPI_IMSC_GEN_SHORT_PACK
  6861. #define MRV_MIPI_IMSC_GEN_SHORT_PACK_MASK 0x08000000U
  6862. #define MRV_MIPI_IMSC_GEN_SHORT_PACK_SHIFT 27U
  6863. /*! Slice: IMSC_ADD_DATA_FILL_LEVEL:*/
  6864. /*! enable interrupt (1) or mask out (0)*/
  6865. #define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL
  6866. #define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_MASK 0x04000000U
  6867. #define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_SHIFT 26U
  6868. /*! Slice: IMSC_ADD_DATA_OVFLW:*/
  6869. /*! enable interrupt (1) or mask out (0)*/
  6870. #define MRV_MIPI_IMSC_ADD_DATA_OVFLW
  6871. #define MRV_MIPI_IMSC_ADD_DATA_OVFLW_MASK 0x02000000U
  6872. #define MRV_MIPI_IMSC_ADD_DATA_OVFLW_SHIFT 25U
  6873. /*! Slice: IMSC_FRAME_END:*/
  6874. /*! enable interrupt (1) or mask out (0)*/
  6875. #define MRV_MIPI_IMSC_FRAME_END
  6876. #define MRV_MIPI_IMSC_FRAME_END_MASK 0x01000000U
  6877. #define MRV_MIPI_IMSC_FRAME_END_SHIFT 24U
  6878. /*! Slice: IMSC_ERR_CS:*/
  6879. /*! enable interrupt (1) or mask out (0)*/
  6880. #define MRV_MIPI_IMSC_ERR_CS
  6881. #define MRV_MIPI_IMSC_ERR_CS_MASK 0x00800000U
  6882. #define MRV_MIPI_IMSC_ERR_CS_SHIFT 23U
  6883. /*! Slice: IMSC_ERR_ECC1:*/
  6884. /*! enable interrupt (1) or mask out (0)*/
  6885. #define MRV_MIPI_IMSC_ERR_ECC1
  6886. #define MRV_MIPI_IMSC_ERR_ECC1_MASK 0x00400000U
  6887. #define MRV_MIPI_IMSC_ERR_ECC1_SHIFT 22U
  6888. /*! Slice: IMSC_ERR_ECC2:*/
  6889. /*! enable interrupt (1) or mask out (0)*/
  6890. #define MRV_MIPI_IMSC_ERR_ECC2
  6891. #define MRV_MIPI_IMSC_ERR_ECC2_MASK 0x00200000U
  6892. #define MRV_MIPI_IMSC_ERR_ECC2_SHIFT 21U
  6893. /*! Slice: IMSC_ERR_PROTOCOL:*/
  6894. /*! enable interrupt (1) or mask out (0)*/
  6895. #define MRV_MIPI_IMSC_ERR_PROTOCOL
  6896. #define MRV_MIPI_IMSC_ERR_PROTOCOL_MASK 0x00100000U
  6897. #define MRV_MIPI_IMSC_ERR_PROTOCOL_SHIFT 20U
  6898. /*! Slice: IMSC_ERR_CONTROL:*/
  6899. /*! enable interrupt (1) or mask out (0) (one bit for each lane)*/
  6900. #define MRV_MIPI_IMSC_ERR_CONTROL
  6901. #define MRV_MIPI_IMSC_ERR_CONTROL_MASK 0x000F0000U
  6902. #define MRV_MIPI_IMSC_ERR_CONTROL_SHIFT 16U
  6903. /*! Slice: IMSC_ERR_EOT_SYNC:*/
  6904. /*! enable interrupt (1) or mask out (0) (one bit for each lane)*/
  6905. #define MRV_MIPI_IMSC_ERR_EOT_SYNC
  6906. #define MRV_MIPI_IMSC_ERR_EOT_SYNC_MASK 0x0000F000U
  6907. #define MRV_MIPI_IMSC_ERR_EOT_SYNC_SHIFT 12U
  6908. /*! Slice: IMSC_ERR_SOT_SYNC:*/
  6909. /*! enable interrupt (1) or mask out (0) (one bit for each lane)*/
  6910. #define MRV_MIPI_IMSC_ERR_SOT_SYNC
  6911. #define MRV_MIPI_IMSC_ERR_SOT_SYNC_MASK 0x00000F00U
  6912. #define MRV_MIPI_IMSC_ERR_SOT_SYNC_SHIFT 8U
  6913. /*! Slice: IMSC_ERR_SOT:*/
  6914. /*! enable interrupt (1) or mask out (0) (one bit for each lane)*/
  6915. #define MRV_MIPI_IMSC_ERR_SOT
  6916. #define MRV_MIPI_IMSC_ERR_SOT_MASK 0x000000F0U
  6917. #define MRV_MIPI_IMSC_ERR_SOT_SHIFT 4U
  6918. /*! Slice: IMSC_SYNC_FIFO_OVFLW:*/
  6919. /*! enable interrupt (1) or mask out (0) (one bit for each lane)*/
  6920. #define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW
  6921. #define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_MASK 0x0000000FU
  6922. #define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_SHIFT 0U
  6923. /*! Register: mipi_ris: Raw interrupt status (0x0000000c)*/
  6924. /*! Slice: RIS_GEN_SHORT_PACK:*/
  6925. /*! generic short packet was received (only available in version 2 of MIPI interface)*/
  6926. /**/
  6927. /* When this interrupt is cleared, all the bits of the MIPI_GEN_SHORT_DT status register are cleared as well; Setting of this interrupt via MIPI_ISR register will set all the bits of the MIPI_GEN_SHORT_DT register.*/
  6928. #define MRV_MIPI_RIS_GEN_SHORT_PACK
  6929. #define MRV_MIPI_RIS_GEN_SHORT_PACK_MASK 0x08000000U
  6930. #define MRV_MIPI_RIS_GEN_SHORT_PACK_SHIFT 27U
  6931. /*! Slice: RIS_ADD_DATA_FILL_LEVEL:*/
  6932. /*! Programmed fill level was reached; will be raised as long as the fill level is greater than the programmed value */
  6933. #define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL
  6934. #define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_MASK 0x04000000U
  6935. #define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_SHIFT 26U
  6936. /*! Slice: RIS_ADD_DATA_OVFLW:*/
  6937. /*! additional data fifo overflow occurred */
  6938. #define MRV_MIPI_RIS_ADD_DATA_OVFLW
  6939. #define MRV_MIPI_RIS_ADD_DATA_OVFLW_MASK 0x02000000U
  6940. #define MRV_MIPI_RIS_ADD_DATA_OVFLW_SHIFT 25U
  6941. /*! Slice: RIS_FRAME_END:*/
  6942. /*! frame end send to output interface */
  6943. #define MRV_MIPI_RIS_FRAME_END
  6944. #define MRV_MIPI_RIS_FRAME_END_MASK 0x01000000U
  6945. #define MRV_MIPI_RIS_FRAME_END_SHIFT 24U
  6946. /*! Slice: RIS_ERR_CS:*/
  6947. /*! checksum error occurred */
  6948. #define MRV_MIPI_RIS_ERR_CS
  6949. #define MRV_MIPI_RIS_ERR_CS_MASK 0x00800000U
  6950. #define MRV_MIPI_RIS_ERR_CS_SHIFT 23U
  6951. /*! Slice: RIS_ERR_ECC1:*/
  6952. /*! 1-bit ecc error occurred */
  6953. #define MRV_MIPI_RIS_ERR_ECC1
  6954. #define MRV_MIPI_RIS_ERR_ECC1_MASK 0x00400000U
  6955. #define MRV_MIPI_RIS_ERR_ECC1_SHIFT 22U
  6956. /*! Slice: RIS_ERR_ECC2:*/
  6957. /*! 2-bit ecc error occurred */
  6958. #define MRV_MIPI_RIS_ERR_ECC2
  6959. #define MRV_MIPI_RIS_ERR_ECC2_MASK 0x00200000U
  6960. #define MRV_MIPI_RIS_ERR_ECC2_SHIFT 21U
  6961. /*! Slice: RIS_ERR_PROTOCOL:*/
  6962. /*! packet start detected within current packet */
  6963. #define MRV_MIPI_RIS_ERR_PROTOCOL
  6964. #define MRV_MIPI_RIS_ERR_PROTOCOL_MASK 0x00100000U
  6965. #define MRV_MIPI_RIS_ERR_PROTOCOL_SHIFT 20U
  6966. /*! Slice: RIS_ERR_CONTROL:*/
  6967. /*! PPI interface control error occured, one bit for each lane */
  6968. #define MRV_MIPI_RIS_ERR_CONTROL
  6969. #define MRV_MIPI_RIS_ERR_CONTROL_MASK 0x000F0000U
  6970. #define MRV_MIPI_RIS_ERR_CONTROL_SHIFT 16U
  6971. /*! Slice: RIS_ERR_EOT_SYNC:*/
  6972. /*! PPI interface eot sync error occured, one bit for each lane */
  6973. #define MRV_MIPI_RIS_ERR_EOT_SYNC
  6974. #define MRV_MIPI_RIS_ERR_EOT_SYNC_MASK 0x0000F000U
  6975. #define MRV_MIPI_RIS_ERR_EOT_SYNC_SHIFT 12U
  6976. /*! Slice: RIS_ERR_SOT_SYNC:*/
  6977. /*! PPI interface sot sync error occured, one bit for each lane */
  6978. #define MRV_MIPI_RIS_ERR_SOT_SYNC
  6979. #define MRV_MIPI_RIS_ERR_SOT_SYNC_MASK 0x00000F00U
  6980. #define MRV_MIPI_RIS_ERR_SOT_SYNC_SHIFT 8U
  6981. /*! Slice: RIS_ERR_SOT:*/
  6982. /*! PPI interface sot error occured, one bit for each lane */
  6983. #define MRV_MIPI_RIS_ERR_SOT
  6984. #define MRV_MIPI_RIS_ERR_SOT_MASK 0x000000F0U
  6985. #define MRV_MIPI_RIS_ERR_SOT_SHIFT 4U
  6986. /*! Slice: RIS_SYNC_FIFO_OVFLW:*/
  6987. /*! synchronization fifo overflow occurred, one bit for each lane */
  6988. #define MRV_MIPI_RIS_SYNC_FIFO_OVFLW
  6989. #define MRV_MIPI_RIS_SYNC_FIFO_OVFLW_MASK 0x0000000FU
  6990. #define MRV_MIPI_RIS_SYNC_FIFO_OVFLW_SHIFT 0U
  6991. /*! Register: mipi_mis: Masked interrupt status (0x00000010)*/
  6992. /*! Slice: MIS_GEN_SHORT_PACK:*/
  6993. /*! generic short packet was received (only available in version 2 of MIPI interface)*/
  6994. #define MRV_MIPI_MIS_GEN_SHORT_PACK
  6995. #define MRV_MIPI_MIS_GEN_SHORT_PACK_MASK 0x08000000U
  6996. #define MRV_MIPI_MIS_GEN_SHORT_PACK_SHIFT 27U
  6997. /*! Slice: MIS_ADD_DATA_FILL_LEVEL:*/
  6998. /*! Programmed fill level was reached; will be raised as long as the fill level is greater the programmed value */
  6999. #define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL
  7000. #define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_MASK 0x04000000U
  7001. #define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_SHIFT 26U
  7002. /*! Slice: MIS_ADD_DATA_OVFLW:*/
  7003. /*! additional data fifo overflow */
  7004. #define MRV_MIPI_MIS_ADD_DATA_OVFLW
  7005. #define MRV_MIPI_MIS_ADD_DATA_OVFLW_MASK 0x02000000U
  7006. #define MRV_MIPI_MIS_ADD_DATA_OVFLW_SHIFT 25U
  7007. /*! Slice: MIS_FRAME_END:*/
  7008. /*! frame end send to output interface */
  7009. #define MRV_MIPI_MIS_FRAME_END
  7010. #define MRV_MIPI_MIS_FRAME_END_MASK 0x01000000U
  7011. #define MRV_MIPI_MIS_FRAME_END_SHIFT 24U
  7012. /*! Slice: MIS_ERR_CS:*/
  7013. /*! checksum error occurred */
  7014. #define MRV_MIPI_MIS_ERR_CS
  7015. #define MRV_MIPI_MIS_ERR_CS_MASK 0x00800000U
  7016. #define MRV_MIPI_MIS_ERR_CS_SHIFT 23U
  7017. /*! Slice: MIS_ERR_ECC1:*/
  7018. /*! 1-bit ecc error occurred */
  7019. #define MRV_MIPI_MIS_ERR_ECC1
  7020. #define MRV_MIPI_MIS_ERR_ECC1_MASK 0x00400000U
  7021. #define MRV_MIPI_MIS_ERR_ECC1_SHIFT 22U
  7022. /*! Slice: MIS_ERR_ECC2:*/
  7023. /*! 2-bit ecc error occurred */
  7024. #define MRV_MIPI_MIS_ERR_ECC2
  7025. #define MRV_MIPI_MIS_ERR_ECC2_MASK 0x00200000U
  7026. #define MRV_MIPI_MIS_ERR_ECC2_SHIFT 21U
  7027. /*! Slice: MIS_ERR_PROTOCOL:*/
  7028. /*! packet start detected within current packet */
  7029. #define MRV_MIPI_MIS_ERR_PROTOCOL
  7030. #define MRV_MIPI_MIS_ERR_PROTOCOL_MASK 0x00100000U
  7031. #define MRV_MIPI_MIS_ERR_PROTOCOL_SHIFT 20U
  7032. /*! Slice: MIS_ERR_CONTROL:*/
  7033. /*! PPI interface control error occured, one bit for each lane */
  7034. #define MRV_MIPI_MIS_ERR_CONTROL
  7035. #define MRV_MIPI_MIS_ERR_CONTROL_MASK 0x000F0000U
  7036. #define MRV_MIPI_MIS_ERR_CONTROL_SHIFT 16U
  7037. /*! Slice: MIS_ERR_EOT_SYNC:*/
  7038. /*! PPI interface eot sync error occured, one bit for each lane */
  7039. #define MRV_MIPI_MIS_ERR_EOT_SYNC
  7040. #define MRV_MIPI_MIS_ERR_EOT_SYNC_MASK 0x0000F000U
  7041. #define MRV_MIPI_MIS_ERR_EOT_SYNC_SHIFT 12U
  7042. /*! Slice: MIS_ERR_SOT_SYNC:*/
  7043. /*! PPI interface sot sync error occured, one bit for each lane */
  7044. #define MRV_MIPI_MIS_ERR_SOT_SYNC
  7045. #define MRV_MIPI_MIS_ERR_SOT_SYNC_MASK 0x00000F00U
  7046. #define MRV_MIPI_MIS_ERR_SOT_SYNC_SHIFT 8U
  7047. /*! Slice: MIS_ERR_SOT:*/
  7048. /*! PPI interface sot error occured, one bit for each lane */
  7049. #define MRV_MIPI_MIS_ERR_SOT
  7050. #define MRV_MIPI_MIS_ERR_SOT_MASK 0x000000F0U
  7051. #define MRV_MIPI_MIS_ERR_SOT_SHIFT 4U
  7052. /*! Slice: MIS_SYNC_FIFO_OVFLW:*/
  7053. /*! synchronization fifo overflow occurred, one bit for each lane */
  7054. #define MRV_MIPI_MIS_SYNC_FIFO_OVFLW
  7055. #define MRV_MIPI_MIS_SYNC_FIFO_OVFLW_MASK 0x0000000FU
  7056. #define MRV_MIPI_MIS_SYNC_FIFO_OVFLW_SHIFT 0U
  7057. /*! Register: mipi_icr: Interrupt clear register (0x00000014)*/
  7058. /*! Slice: ICR_GEN_SHORT_PACK:*/
  7059. /*! 1: clear register; 0: nothing happens */
  7060. #define MRV_MIPI_ICR_GEN_SHORT_PACK
  7061. #define MRV_MIPI_ICR_GEN_SHORT_PACK_MASK 0x08000000U
  7062. #define MRV_MIPI_ICR_GEN_SHORT_PACK_SHIFT 27U
  7063. /*! Slice: ICR_ADD_DATA_FILL_LEVEL:*/
  7064. /*! 1: clear register; 0: nothing happens */
  7065. #define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL
  7066. #define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_MASK 0x04000000U
  7067. #define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_SHIFT 26U
  7068. /*! Slice: ICR_ADD_DATA_OVFLW:*/
  7069. /*! 1: clear register; 0: nothing happens */
  7070. #define MRV_MIPI_ICR_ADD_DATA_OVFLW
  7071. #define MRV_MIPI_ICR_ADD_DATA_OVFLW_MASK 0x02000000U
  7072. #define MRV_MIPI_ICR_ADD_DATA_OVFLW_SHIFT 25U
  7073. /*! Slice: ICR_FRAME_END:*/
  7074. /*! 1: clear register; 0: nothing happens */
  7075. #define MRV_MIPI_ICR_FRAME_END
  7076. #define MRV_MIPI_ICR_FRAME_END_MASK 0x01000000U
  7077. #define MRV_MIPI_ICR_FRAME_END_SHIFT 24U
  7078. /*! Slice: ICR_ERR_CS:*/
  7079. /*! 1: clear register; 0: nothing happens */
  7080. #define MRV_MIPI_ICR_ERR_CS
  7081. #define MRV_MIPI_ICR_ERR_CS_MASK 0x00800000U
  7082. #define MRV_MIPI_ICR_ERR_CS_SHIFT 23U
  7083. /*! Slice: ICR_ERR_ECC1:*/
  7084. /*! 1: clear register; 0: nothing happens */
  7085. #define MRV_MIPI_ICR_ERR_ECC1
  7086. #define MRV_MIPI_ICR_ERR_ECC1_MASK 0x00400000U
  7087. #define MRV_MIPI_ICR_ERR_ECC1_SHIFT 22U
  7088. /*! Slice: ICR_ERR_ECC2:*/
  7089. /*! 1: clear register; 0: nothing happens */
  7090. #define MRV_MIPI_ICR_ERR_ECC2
  7091. #define MRV_MIPI_ICR_ERR_ECC2_MASK 0x00200000U
  7092. #define MRV_MIPI_ICR_ERR_ECC2_SHIFT 21U
  7093. /*! Slice: ICR_ERR_PROTOCOL:*/
  7094. /*! 1: clear register; 0: nothing happens */
  7095. #define MRV_MIPI_ICR_ERR_PROTOCOL
  7096. #define MRV_MIPI_ICR_ERR_PROTOCOL_MASK 0x00100000U
  7097. #define MRV_MIPI_ICR_ERR_PROTOCOL_SHIFT 20U
  7098. /*! Slice: ICR_ERR_CONTROL:*/
  7099. /*! 1: clear register; 0: nothing happens (one bit for each lane)*/
  7100. #define MRV_MIPI_ICR_ERR_CONTROL
  7101. #define MRV_MIPI_ICR_ERR_CONTROL_MASK 0x000F0000U
  7102. #define MRV_MIPI_ICR_ERR_CONTROL_SHIFT 16U
  7103. /*! Slice: ICR_ERR_EOT_SYNC:*/
  7104. /*! 1: clear register; 0: nothing happens (one bit for each lane)*/
  7105. #define MRV_MIPI_ICR_ERR_EOT_SYNC
  7106. #define MRV_MIPI_ICR_ERR_EOT_SYNC_MASK 0x0000F000U
  7107. #define MRV_MIPI_ICR_ERR_EOT_SYNC_SHIFT 12U
  7108. /*! Slice: ICR_ERR_SOT_SYNC:*/
  7109. /*! 1: clear register; 0: nothing happens (one bit for each lane)*/
  7110. #define MRV_MIPI_ICR_ERR_SOT_SYNC
  7111. #define MRV_MIPI_ICR_ERR_SOT_SYNC_MASK 0x00000F00U
  7112. #define MRV_MIPI_ICR_ERR_SOT_SYNC_SHIFT 8U
  7113. /*! Slice: ICR_ERR_SOT:*/
  7114. /*! 1: clear register; 0: nothing happens (one bit for each lane)*/
  7115. #define MRV_MIPI_ICR_ERR_SOT
  7116. #define MRV_MIPI_ICR_ERR_SOT_MASK 0x000000F0U
  7117. #define MRV_MIPI_ICR_ERR_SOT_SHIFT 4U
  7118. /*! Slice: ICR_SYNC_FIFO_OVFLW:*/
  7119. /*! 1: clear register; 0: nothing happens (one bit for each lane)*/
  7120. #define MRV_MIPI_ICR_SYNC_FIFO_OVFLW
  7121. #define MRV_MIPI_ICR_SYNC_FIFO_OVFLW_MASK 0x0000000FU
  7122. #define MRV_MIPI_ICR_SYNC_FIFO_OVFLW_SHIFT 0U
  7123. /*! Register: mipi_isr: Interrupt set register (0x00000018)*/
  7124. /*! Slice: ISR_GEN_SHORT_PACK:*/
  7125. /*! 1: set register; 0: nothing happens */
  7126. #define MRV_MIPI_ISR_GEN_SHORT_PACK
  7127. #define MRV_MIPI_ISR_GEN_SHORT_PACK_MASK 0x08000000U
  7128. #define MRV_MIPI_ISR_GEN_SHORT_PACK_SHIFT 27U
  7129. /*! Slice: ISR_ADD_DATA_FILL_LEVEL:*/
  7130. /*! 1: set register; 0: nothing happens */
  7131. #define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL
  7132. #define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_MASK 0x04000000U
  7133. #define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_SHIFT 26U
  7134. /*! Slice: ISR_ADD_DATA_OVFLW:*/
  7135. /*! 1: set register; 0: nothing happens */
  7136. #define MRV_MIPI_ISR_ADD_DATA_OVFLW
  7137. #define MRV_MIPI_ISR_ADD_DATA_OVFLW_MASK 0x02000000U
  7138. #define MRV_MIPI_ISR_ADD_DATA_OVFLW_SHIFT 25U
  7139. /*! Slice: ISR_FRAME_END:*/
  7140. /*! 1: set register; 0: nothing happens */
  7141. #define MRV_MIPI_ISR_FRAME_END
  7142. #define MRV_MIPI_ISR_FRAME_END_MASK 0x01000000U
  7143. #define MRV_MIPI_ISR_FRAME_END_SHIFT 24U
  7144. /*! Slice: ISR_ERR_CS:*/
  7145. /*! 1: set register; 0: nothing happens */
  7146. #define MRV_MIPI_ISR_ERR_CS
  7147. #define MRV_MIPI_ISR_ERR_CS_MASK 0x00800000U
  7148. #define MRV_MIPI_ISR_ERR_CS_SHIFT 23U
  7149. /*! Slice: ISR_ERR_ECC1:*/
  7150. /*! 1: set register; 0: nothing happens */
  7151. #define MRV_MIPI_ISR_ERR_ECC1
  7152. #define MRV_MIPI_ISR_ERR_ECC1_MASK 0x00400000U
  7153. #define MRV_MIPI_ISR_ERR_ECC1_SHIFT 22U
  7154. /*! Slice: ISR_ERR_ECC2:*/
  7155. /*! 1: set register; 0: nothing happens */
  7156. #define MRV_MIPI_ISR_ERR_ECC2
  7157. #define MRV_MIPI_ISR_ERR_ECC2_MASK 0x00200000U
  7158. #define MRV_MIPI_ISR_ERR_ECC2_SHIFT 21U
  7159. /*! Slice: ISR_ERR_PROTOCOL:*/
  7160. /*! 1: set register; 0: nothing happens */
  7161. #define MRV_MIPI_ISR_ERR_PROTOCOL
  7162. #define MRV_MIPI_ISR_ERR_PROTOCOL_MASK 0x00100000U
  7163. #define MRV_MIPI_ISR_ERR_PROTOCOL_SHIFT 20U
  7164. /*! Slice: ISR_ERR_CONTROL:*/
  7165. /*! 1: set register; 0: nothing happens (one bit for each lane)*/
  7166. #define MRV_MIPI_ISR_ERR_CONTROL
  7167. #define MRV_MIPI_ISR_ERR_CONTROL_MASK 0x000F0000U
  7168. #define MRV_MIPI_ISR_ERR_CONTROL_SHIFT 16U
  7169. /*! Slice: ISR_ERR_EOT_SYNC:*/
  7170. /*! 1: set register; 0: nothing happens (one bit for each lane)*/
  7171. #define MRV_MIPI_ISR_ERR_EOT_SYNC
  7172. #define MRV_MIPI_ISR_ERR_EOT_SYNC_MASK 0x0000F000U
  7173. #define MRV_MIPI_ISR_ERR_EOT_SYNC_SHIFT 12U
  7174. /*! Slice: ISR_ERR_SOT_SYNC:*/
  7175. /*! 1: set register; 0: nothing happens (one bit for each lane)*/
  7176. #define MRV_MIPI_ISR_ERR_SOT_SYNC
  7177. #define MRV_MIPI_ISR_ERR_SOT_SYNC_MASK 0x00000F00U
  7178. #define MRV_MIPI_ISR_ERR_SOT_SYNC_SHIFT 8U
  7179. /*! Slice: ISR_ERR_SOT:*/
  7180. /*! 1: set register; 0: nothing happens (one bit for each lane)*/
  7181. #define MRV_MIPI_ISR_ERR_SOT
  7182. #define MRV_MIPI_ISR_ERR_SOT_MASK 0x000000F0U
  7183. #define MRV_MIPI_ISR_ERR_SOT_SHIFT 4U
  7184. /*! Slice: ISR_SYNC_FIFO_OVFLW:*/
  7185. /*! 1: set register; 0: nothing happens (one bit for each lane)*/
  7186. #define MRV_MIPI_ISR_SYNC_FIFO_OVFLW
  7187. #define MRV_MIPI_ISR_SYNC_FIFO_OVFLW_MASK 0x0000000FU
  7188. #define MRV_MIPI_ISR_SYNC_FIFO_OVFLW_SHIFT 0U
  7189. /*! Register: mipi_cur_data_id: Current Data Identifier (0x0000001c)*/
  7190. /*! Slice: VIRTUAL_CHANNEL:*/
  7191. /*! virtual channel of currently received packet */
  7192. #define MRV_MIPI_VIRTUAL_CHANNEL
  7193. #define MRV_MIPI_VIRTUAL_CHANNEL_MASK 0x000000C0U
  7194. #define MRV_MIPI_VIRTUAL_CHANNEL_SHIFT 6U
  7195. /*! Slice: DATA_TYPE:*/
  7196. /*! data type of currently received packet */
  7197. #define MRV_MIPI_DATA_TYPE
  7198. #define MRV_MIPI_DATA_TYPE_MASK 0x0000003FU
  7199. #define MRV_MIPI_DATA_TYPE_SHIFT 0U
  7200. /*! Register: mipi_img_data_sel: Image Data Selector (0x00000020)*/
  7201. /*! Slice: VIRTUAL_CHANNEL_SEL:*/
  7202. /*! virtual channel selector for image data output */
  7203. #define MRV_MIPI_VIRTUAL_CHANNEL_SEL
  7204. #define MRV_MIPI_VIRTUAL_CHANNEL_SEL_MASK 0x000000C0U
  7205. #define MRV_MIPI_VIRTUAL_CHANNEL_SEL_SHIFT 6U
  7206. /*! Slice: DATA_TYPE_SEL:*/
  7207. /*! data type selector for image data output:*/
  7208. /* 0x08...0x0F generic short packets */
  7209. /* 0x12 embedded 8-bit data */
  7210. /* 0x18 YUV 420 8-bit */
  7211. /* 0x19 YUV 420 10-bit */
  7212. /* 0x1A Legacy YUV 420 8-bit */
  7213. /* 0x1C YUV 420 8-bit (CSPS)*/
  7214. /* 0x1D YUV 420 10-bit (CSPS)*/
  7215. /* 0x1E YUV 422 8-bit */
  7216. /* 0x1F YUV 422 10-bit */
  7217. /* 0x20 RGB 444 */
  7218. /* 0x21 RGB 555 */
  7219. /* 0x22 RGB 565 */
  7220. /* 0x23 RGB 666 */
  7221. /* 0x24 RGB 888 */
  7222. /* 0x28 RAW 6 */
  7223. /* 0x29 RAW 7 */
  7224. /* 0x2A RAW 8 */
  7225. /* 0x2B RAW 10 */
  7226. /* 0x2C RAW 12 */
  7227. /* 0x30...0x37 User Defined Byte-based data */
  7228. #define MRV_MIPI_DATA_TYPE_SEL
  7229. #define MRV_MIPI_DATA_TYPE_SEL_MASK 0x0000003FU
  7230. #define MRV_MIPI_DATA_TYPE_SEL_SHIFT 0U
  7231. /*! Register: mipi_add_data_sel_1: Additional Data Selector 1 (0x00000024)*/
  7232. /*! Slice: ADD_DATA_VC_1:*/
  7233. /*! virtual channel selector for additional data output */
  7234. #define MRV_MIPI_ADD_DATA_VC_1
  7235. #define MRV_MIPI_ADD_DATA_VC_1_MASK 0x000000C0U
  7236. #define MRV_MIPI_ADD_DATA_VC_1_SHIFT 6U
  7237. /*! Slice: ADD_DATA_TYPE_1:*/
  7238. /*! data type selector for additional data output */
  7239. #define MRV_MIPI_ADD_DATA_TYPE_1
  7240. #define MRV_MIPI_ADD_DATA_TYPE_1_MASK 0x0000003FU
  7241. #define MRV_MIPI_ADD_DATA_TYPE_1_SHIFT 0U
  7242. /*! Register: mipi_add_data_sel_2: Additional Data Selector 2 (0x00000028)*/
  7243. /*! Slice: ADD_DATA_VC_2:*/
  7244. /*! virtual channel selector for additional data output */
  7245. #define MRV_MIPI_ADD_DATA_VC_2
  7246. #define MRV_MIPI_ADD_DATA_VC_2_MASK 0x000000C0U
  7247. #define MRV_MIPI_ADD_DATA_VC_2_SHIFT 6U
  7248. /*! Slice: ADD_DATA_TYPE_2:*/
  7249. /*! data type selector for additional data output */
  7250. #define MRV_MIPI_ADD_DATA_TYPE_2
  7251. #define MRV_MIPI_ADD_DATA_TYPE_2_MASK 0x0000003FU
  7252. #define MRV_MIPI_ADD_DATA_TYPE_2_SHIFT 0U
  7253. /*! Register: mipi_add_data_sel_3: Additional Data Selector 3 (0x0000002c)*/
  7254. /*! Slice: ADD_DATA_VC_3:*/
  7255. /*! virtual channel selector for additional data output */
  7256. #define MRV_MIPI_ADD_DATA_VC_3
  7257. #define MRV_MIPI_ADD_DATA_VC_3_MASK 0x000000C0U
  7258. #define MRV_MIPI_ADD_DATA_VC_3_SHIFT 6U
  7259. /*! Slice: ADD_DATA_TYPE_3:*/
  7260. /*! data type selector for additional data output */
  7261. #define MRV_MIPI_ADD_DATA_TYPE_3
  7262. #define MRV_MIPI_ADD_DATA_TYPE_3_MASK 0x0000003FU
  7263. #define MRV_MIPI_ADD_DATA_TYPE_3_SHIFT 0U
  7264. /*! Register: mipi_add_data_sel_4: Additional Data Selector 4 (0x00000030)*/
  7265. /*! Slice: ADD_DATA_VC_4:*/
  7266. /*! virtual channel selector for additional data output */
  7267. #define MRV_MIPI_ADD_DATA_VC_4
  7268. #define MRV_MIPI_ADD_DATA_VC_4_MASK 0x000000C0U
  7269. #define MRV_MIPI_ADD_DATA_VC_4_SHIFT 6U
  7270. /*! Slice: ADD_DATA_TYPE_4:*/
  7271. /*! data type selector for additional data output */
  7272. #define MRV_MIPI_ADD_DATA_TYPE_4
  7273. #define MRV_MIPI_ADD_DATA_TYPE_4_MASK 0x0000003FU
  7274. #define MRV_MIPI_ADD_DATA_TYPE_4_SHIFT 0U
  7275. /*! Register: mipi_add_data_fifo: Additional Data Fifo (0x00000034)*/
  7276. /*! Slice: ADD_DATA_FIFO:*/
  7277. /*! lowest 4 bytes in additional data fifo;*/
  7278. /* reading increments fifo read pointer.*/
  7279. /* First embedded data byte will be written to bits 7:0 of 32-bit data word, second data byte written to 15:8 etc.*/
  7280. #define MRV_MIPI_ADD_DATA_FIFO
  7281. #define MRV_MIPI_ADD_DATA_FIFO_MASK 0xFFFFFFFFU
  7282. #define MRV_MIPI_ADD_DATA_FIFO_SHIFT 0U
  7283. /*! Register: mipi_add_data_fill_level: Additional Data FIFO Fill Level (0x00000038)*/
  7284. /*! Slice: ADD_DATA_FILL_LEVEL:*/
  7285. /*! FIFO level in dwords for triggering the FILL_LEVEL interrupt,*/
  7286. /* must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/
  7287. #define MRV_MIPI_ADD_DATA_FILL_LEVEL
  7288. #define MRV_MIPI_ADD_DATA_FILL_LEVEL_MASK 0x00001FFFU
  7289. #define MRV_MIPI_ADD_DATA_FILL_LEVEL_SHIFT 0U
  7290. /*! Register: mipi_compressed_mode: controls processing of compressed raw data types (0x0000003c)*/
  7291. /*! Slice: predictor_sel:*/
  7292. /*! predictor to be used:*/
  7293. /* 0: predictor 1 */
  7294. /* 1: predictor 2 */
  7295. #define MRV_MIPI_PREDICTOR_SEL
  7296. #define MRV_MIPI_PREDICTOR_SEL_MASK 0x00000100U
  7297. #define MRV_MIPI_PREDICTOR_SEL_SHIFT 8U
  7298. /*! Slice: comp_scheme:*/
  7299. /*! data compression scheme:*/
  7300. /* 0: 12–8–12 */
  7301. /* 1: 12–7–12 */
  7302. /* 2: 12–6–12 */
  7303. /* 3: 10–8–10 */
  7304. /* 4: 10–7–10 */
  7305. /* 5: 10–6–10 */
  7306. /* 6..7: reserved */
  7307. #define MRV_MIPI_COMP_SCHEME
  7308. #define MRV_MIPI_COMP_SCHEME_MASK 0x00000070U
  7309. #define MRV_MIPI_COMP_SCHEME_SHIFT 4U
  7310. /*! Slice: compress_en:*/
  7311. /*! 1: enable compressed mode processing */
  7312. /* 0: disable compressed mode */
  7313. #define MRV_MIPI_COMPRESS_EN
  7314. #define MRV_MIPI_COMPRESS_EN_MASK 0x00000001U
  7315. #define MRV_MIPI_COMPRESS_EN_SHIFT 0U
  7316. /*! Register: mipi_frame: frame number from frame start and frame end short packets (0x00000040)*/
  7317. /*! Slice: frame_number_fe:*/
  7318. /*! 16 bit frame number from Frame End (FE) short packet */
  7319. #define MRV_MIPI_FRAME_NUMBER_FE
  7320. #define MRV_MIPI_FRAME_NUMBER_FE_MASK 0xFFFF0000U
  7321. #define MRV_MIPI_FRAME_NUMBER_FE_SHIFT 16U
  7322. /*! Slice: frame_number_fs:*/
  7323. /*! 16 bit frame number from Frame Start (FS) short packet */
  7324. #define MRV_MIPI_FRAME_NUMBER_FS
  7325. #define MRV_MIPI_FRAME_NUMBER_FS_MASK 0x0000FFFFU
  7326. #define MRV_MIPI_FRAME_NUMBER_FS_SHIFT 0U
  7327. /*! Register: mipi_gen_short_dt: data type flags for received generic short packets (0x00000044)*/
  7328. /*! Slice: GEN_SHORT_DT_0xF:*/
  7329. /*! 1: generic short packet of data type 0xF received */
  7330. /* 0: data type 0xF not received */
  7331. #define MRV_MIPI_GEN_SHORT_DT_0XF
  7332. #define MRV_MIPI_GEN_SHORT_DT_0XF_MASK 0x00000080U
  7333. #define MRV_MIPI_GEN_SHORT_DT_0XF_SHIFT 7U
  7334. /*! Slice: GEN_SHORT_DT_0xE:*/
  7335. /*! 1: generic short packet of data type 0xE received */
  7336. /* 0: data type 0xE not received */
  7337. #define MRV_MIPI_GEN_SHORT_DT_0XE
  7338. #define MRV_MIPI_GEN_SHORT_DT_0XE_MASK 0x00000040U
  7339. #define MRV_MIPI_GEN_SHORT_DT_0XE_SHIFT 6U
  7340. /*! Slice: GEN_SHORT_DT_0xD:*/
  7341. /*! 1: generic short packet of data type 0xD received */
  7342. /* 0: data type 0xD not received */
  7343. #define MRV_MIPI_GEN_SHORT_DT_0XD
  7344. #define MRV_MIPI_GEN_SHORT_DT_0XD_MASK 0x00000020U
  7345. #define MRV_MIPI_GEN_SHORT_DT_0XD_SHIFT 5U
  7346. /*! Slice: GEN_SHORT_DT_0xC:*/
  7347. /*! 1: generic short packet of data type 0xC received */
  7348. /* 0: data type 0xC not received */
  7349. #define MRV_MIPI_GEN_SHORT_DT_0XC
  7350. #define MRV_MIPI_GEN_SHORT_DT_0XC_MASK 0x00000010U
  7351. #define MRV_MIPI_GEN_SHORT_DT_0XC_SHIFT 4U
  7352. /*! Slice: GEN_SHORT_DT_0xB:*/
  7353. /*! 1: generic short packet of data type 0xB received */
  7354. /* 0: data type 0xB not received */
  7355. #define MRV_MIPI_GEN_SHORT_DT_0XB
  7356. #define MRV_MIPI_GEN_SHORT_DT_0XB_MASK 0x00000008U
  7357. #define MRV_MIPI_GEN_SHORT_DT_0XB_SHIFT 3U
  7358. /*! Slice: GEN_SHORT_DT_0xA:*/
  7359. /*! 1: generic short packet of data type 0xA received */
  7360. /* 0: data type 0xA not received */
  7361. #define MRV_MIPI_GEN_SHORT_DT_0XA
  7362. #define MRV_MIPI_GEN_SHORT_DT_0XA_MASK 0x00000004U
  7363. #define MRV_MIPI_GEN_SHORT_DT_0XA_SHIFT 2U
  7364. /*! Slice: GEN_SHORT_DT_0x9:*/
  7365. /*! 1: generic short packet of data type 0x9 received */
  7366. /* 0: data type 0x9 not received */
  7367. #define MRV_MIPI_GEN_SHORT_DT_0X9
  7368. #define MRV_MIPI_GEN_SHORT_DT_0X9_MASK 0x00000002U
  7369. #define MRV_MIPI_GEN_SHORT_DT_0X9_SHIFT 1U
  7370. /*! Slice: GEN_SHORT_DT_0x8:*/
  7371. /*! 1: generic short packet of data type 0x8 received */
  7372. /* 0: data type 0x8 not received */
  7373. #define MRV_MIPI_GEN_SHORT_DT_0X8
  7374. #define MRV_MIPI_GEN_SHORT_DT_0X8_MASK 0x00000001U
  7375. #define MRV_MIPI_GEN_SHORT_DT_0X8_SHIFT 0U
  7376. /*! Register: mipi_gen_short_8_9: data field for generic short packets of data type 0x8 and 0x9 (0x00000048)*/
  7377. /*! Slice: data_field_9:*/
  7378. /*! 16 bit user defined data field from last generic short packet of data type 0x9 */
  7379. #define MRV_MIPI_DATA_FIELD_9
  7380. #define MRV_MIPI_DATA_FIELD_9_MASK 0xFFFF0000U
  7381. #define MRV_MIPI_DATA_FIELD_9_SHIFT 16U
  7382. /*! Slice: data_field_8:*/
  7383. /*! 16 bit user defined data field from last generic short packet of data type 0x8 */
  7384. #define MRV_MIPI_DATA_FIELD_8
  7385. #define MRV_MIPI_DATA_FIELD_8_MASK 0x0000FFFFU
  7386. #define MRV_MIPI_DATA_FIELD_8_SHIFT 0U
  7387. /*! Register: mipi_gen_short_a_b: data field for generic short packets of data type 0xA and 0xB (0x0000004c)*/
  7388. /*! Slice: data_field_B:*/
  7389. /*! 16 bit user defined data field from last generic short packet of data type 0xB */
  7390. #define MRV_MIPI_DATA_FIELD_B
  7391. #define MRV_MIPI_DATA_FIELD_B_MASK 0xFFFF0000U
  7392. #define MRV_MIPI_DATA_FIELD_B_SHIFT 16U
  7393. /*! Slice: data_field_A:*/
  7394. /*! 16 bit user defined data field from last generic short packet of data type 0xA */
  7395. #define MRV_MIPI_DATA_FIELD_A
  7396. #define MRV_MIPI_DATA_FIELD_A_MASK 0x0000FFFFU
  7397. #define MRV_MIPI_DATA_FIELD_A_SHIFT 0U
  7398. /*! Register: mipi_gen_short_c_d: data field for generic short packets of data type 0xC and 0xD (0x00000050)*/
  7399. /*! Slice: data_field_D:*/
  7400. /*! 16 bit user defined data field from last generic short packet of data type 0xD */
  7401. #define MRV_MIPI_DATA_FIELD_D
  7402. #define MRV_MIPI_DATA_FIELD_D_MASK 0xFFFF0000U
  7403. #define MRV_MIPI_DATA_FIELD_D_SHIFT 16U
  7404. /*! Slice: data_field_C:*/
  7405. /*! 16 bit user defined data field from last generic short packet of data type 0xC */
  7406. #define MRV_MIPI_DATA_FIELD_C
  7407. #define MRV_MIPI_DATA_FIELD_C_MASK 0x0000FFFFU
  7408. #define MRV_MIPI_DATA_FIELD_C_SHIFT 0U
  7409. /*! Register: mipi_gen_short_e_f: data field for generic short packets of data type 0xE and 0xF (0x00000054)*/
  7410. /*! Slice: data_field_F:*/
  7411. /*! 16 bit user defined data field from last generic short packet of data type 0xF */
  7412. #define MRV_MIPI_DATA_FIELD_F
  7413. #define MRV_MIPI_DATA_FIELD_F_MASK 0xFFFF0000U
  7414. #define MRV_MIPI_DATA_FIELD_F_SHIFT 16U
  7415. /*! Slice: data_field_E:*/
  7416. /*! 16 bit user defined data field from last generic short packet of data type 0xE */
  7417. #define MRV_MIPI_DATA_FIELD_E
  7418. #define MRV_MIPI_DATA_FIELD_E_MASK 0x0000FFFFU
  7419. #define MRV_MIPI_DATA_FIELD_E_SHIFT 0U
  7420. /*! Register: isp_afm_ctrl: This is the control register for AF measurement unit (0x00000000)*/
  7421. /*! Slice: afm_en:*/
  7422. /*! AF measurement enable */
  7423. /* 0: AF measurement is disabled */
  7424. /* 1: AF measurement is enabled */
  7425. /* Writing a 1 to this register starts a new measurement and resets the afm_fin (measurement finished) interrupt to 0.*/
  7426. /* As long as the afm_en is 1, the AFM unit calculates new sharpness values for each frame.*/
  7427. #define MRV_AFM_AFM_EN
  7428. #define MRV_AFM_AFM_EN_MASK 0x00000001U
  7429. #define MRV_AFM_AFM_EN_SHIFT 0U
  7430. /*! Register: isp_afm_lt_a: Top Left corner of measure window A (0x00000004)*/
  7431. /*! Slice: a_h_l:*/
  7432. /*! first pixel of window A (horizontal left row), value must be greater or equal 5 */
  7433. #define MRV_AFM_A_H_L
  7434. #define MRV_AFM_A_H_L_MASK 0x1FFF0000U
  7435. #define MRV_AFM_A_H_L_SHIFT 16U
  7436. /*! Slice: a_v_t:*/
  7437. /*! first line of window A (vertical top line), value must be greater or equal 2 */
  7438. #define MRV_AFM_A_V_T
  7439. #define MRV_AFM_A_V_T_MASK 0x00001FFFU
  7440. #define MRV_AFM_A_V_T_SHIFT 0U
  7441. /*! Register: isp_afm_rb_a: Bottom right corner of measure window A (0x00000008)*/
  7442. /*! Slice: a_h_r:*/
  7443. /*! last pixel of window A (horizontal right row)*/
  7444. #define MRV_AFM_A_H_R
  7445. #define MRV_AFM_A_H_R_MASK 0x1FFF0000U
  7446. #define MRV_AFM_A_H_R_SHIFT 16U
  7447. /*! Slice: a_v_b:*/
  7448. /*! last line of window A (vertical bottom line), value must be lower than (number of lines – 2)*/
  7449. #define MRV_AFM_A_V_B
  7450. #define MRV_AFM_A_V_B_MASK 0x00001FFFU
  7451. #define MRV_AFM_A_V_B_SHIFT 0U
  7452. /*! Register: isp_afm_lt_b: Top left corner of measure window B (0x0000000c)*/
  7453. /*! Slice: b_h_l:*/
  7454. /*! first pixel of window B (horizontal left row), value must be greater or equal 5 */
  7455. #define MRV_AFM_B_H_L
  7456. #define MRV_AFM_B_H_L_MASK 0x1FFF0000U
  7457. #define MRV_AFM_B_H_L_SHIFT 16U
  7458. /*! Slice: b_v_t:*/
  7459. /*! first line of window B (vertical top line), value must be greater or equal 2 */
  7460. #define MRV_AFM_B_V_T
  7461. #define MRV_AFM_B_V_T_MASK 0x00001FFFU
  7462. #define MRV_AFM_B_V_T_SHIFT 0U
  7463. /*! Register: isp_afm_rb_b: Bottom right corner of measure window B (0x00000010)*/
  7464. /*! Slice: b_h_r:*/
  7465. /*! last pixel of window B (horizontal right row)*/
  7466. #define MRV_AFM_B_H_R
  7467. #define MRV_AFM_B_H_R_MASK 0x1FFF0000U
  7468. #define MRV_AFM_B_H_R_SHIFT 16U
  7469. /*! Slice: b_v_b:*/
  7470. /*! last line of window B (vertical bottom line), value must be lower than (number of lines – 2)*/
  7471. #define MRV_AFM_B_V_B
  7472. #define MRV_AFM_B_V_B_MASK 0x00001FFFU
  7473. #define MRV_AFM_B_V_B_SHIFT 0U
  7474. /*! Register: isp_afm_lt_c: Top left corner of measure window C (0x00000014)*/
  7475. /*! Slice: c_h_l:*/
  7476. /*! first pixel of window C (horizontal left row), value must be greater or equal 5 */
  7477. #define MRV_AFM_C_H_L
  7478. #define MRV_AFM_C_H_L_MASK 0x1FFF0000U
  7479. #define MRV_AFM_C_H_L_SHIFT 16U
  7480. /*! Slice: c_v_t:*/
  7481. /*! first line of window C (vertical top line), value must be greater or equal 2 */
  7482. #define MRV_AFM_C_V_T
  7483. #define MRV_AFM_C_V_T_MASK 0x00001FFFU
  7484. #define MRV_AFM_C_V_T_SHIFT 0U
  7485. /*! Register: isp_afm_rb_c: Bottom right corner of measure window C (0x00000018)*/
  7486. /*! Slice: c_h_r:*/
  7487. /*! last pixel of window C (horizontal right row)*/
  7488. #define MRV_AFM_C_H_R
  7489. #define MRV_AFM_C_H_R_MASK 0x1FFF0000U
  7490. #define MRV_AFM_C_H_R_SHIFT 16U
  7491. /*! Slice: c_v_b:*/
  7492. /*! last line of window C (vertical bottom line), value must be lower than (number of lines – 2)*/
  7493. #define MRV_AFM_C_V_B
  7494. #define MRV_AFM_C_V_B_MASK 0x00001FFFU
  7495. #define MRV_AFM_C_V_B_SHIFT 0U
  7496. /*! Register: isp_afm_thres: Threshold register (0x0000001c)*/
  7497. /*! Slice: afm_thres:*/
  7498. /*! AF measurement threshold */
  7499. /* This register defines a threshold which can be used for minimizing the influence of noise in the measurement result.*/
  7500. #define MRV_AFM_AFM_THRES
  7501. #define MRV_AFM_AFM_THRES_MASK 0x0000FFFFU
  7502. #define MRV_AFM_AFM_THRES_SHIFT 0U
  7503. /*! Register: isp_afm_var_shift: Variable shift register (0x00000020)*/
  7504. /*! Slice: lum_var_shift:*/
  7505. /*! variable shift for luminance summation */
  7506. /* The lum_var_shift defines the number of bits for the shift operation of the value of the current pixel before summation. The shift operation is used to avoid a luminance sum overflow.*/
  7507. #define MRV_AFM_LUM_VAR_SHIFT
  7508. #define MRV_AFM_LUM_VAR_SHIFT_MASK 0x00070000U
  7509. #define MRV_AFM_LUM_VAR_SHIFT_SHIFT 16U
  7510. /*! Slice: afm_var_shift:*/
  7511. /*! variable shift for AF measurement */
  7512. /* The afm_var_shift defines the number of bits for the shift operation at the end of the calculation chain. The shift operation is used to avoid an AF measurement sum overflow.*/
  7513. #define MRV_AFM_AFM_VAR_SHIFT
  7514. #define MRV_AFM_AFM_VAR_SHIFT_MASK 0x00000007U
  7515. #define MRV_AFM_AFM_VAR_SHIFT_SHIFT 0U
  7516. /*! Register: isp_afm_sum_a: Sharpness Value Status Register of Window A (0x00000024)*/
  7517. /*! Slice: afm_sum_a:*/
  7518. /*! sharpness value of window A */
  7519. #define MRV_AFM_AFM_SUM_A
  7520. #define MRV_AFM_AFM_SUM_A_MASK 0xFFFFFFFFU
  7521. #define MRV_AFM_AFM_SUM_A_SHIFT 0U
  7522. /*! Register: isp_afm_sum_b: Sharpness Value Status Register of Window B (0x00000028)*/
  7523. /*! Slice: afm_sum_b:*/
  7524. /*! sharpness value of window B */
  7525. #define MRV_AFM_AFM_SUM_B
  7526. #define MRV_AFM_AFM_SUM_B_MASK 0xFFFFFFFFU
  7527. #define MRV_AFM_AFM_SUM_B_SHIFT 0U
  7528. /*! Register: isp_afm_sum_c: Sharpness Value Status Register of Window C (0x0000002c)*/
  7529. /*! Slice: afm_sum_c:*/
  7530. /*! sharpness value of window C */
  7531. #define MRV_AFM_AFM_SUM_C
  7532. #define MRV_AFM_AFM_SUM_C_MASK 0xFFFFFFFFU
  7533. #define MRV_AFM_AFM_SUM_C_SHIFT 0U
  7534. /*! Register: isp_afm_lum_a: Luminance Value Status Register of Window A (0x00000030)*/
  7535. /*! Slice: afm_lum_a:*/
  7536. /*! luminance value of window A */
  7537. #define MRV_AFM_AFM_LUM_A
  7538. #define MRV_AFM_AFM_LUM_A_MASK 0x00FFFFFFU
  7539. #define MRV_AFM_AFM_LUM_A_SHIFT 0U
  7540. /*! Register: isp_afm_lum_b: Luminance Value Status Register of Window B (0x00000034)*/
  7541. /*! Slice: afm_lum_b:*/
  7542. /*! luminance value of window B */
  7543. #define MRV_AFM_AFM_LUM_B
  7544. #define MRV_AFM_AFM_LUM_B_MASK 0x00FFFFFFU
  7545. #define MRV_AFM_AFM_LUM_B_SHIFT 0U
  7546. /*! Register: isp_afm_lum_c: Luminance Value Status Register of Window C (0x00000038)*/
  7547. /*! Slice: afm_lum_c:*/
  7548. /*! luminance value of window C */
  7549. #define MRV_AFM_AFM_LUM_C
  7550. #define MRV_AFM_AFM_LUM_C_MASK 0x00FFFFFFU
  7551. #define MRV_AFM_AFM_LUM_C_SHIFT 0U
  7552. /*! Register: isp_lsc_ctrl: Lens shade control (0x00000000)*/
  7553. /*! Slice: lsc_en:*/
  7554. /*! 0: activation request for lens shading correction */
  7555. /* 1: deactivation reqeust for lens shading correction */
  7556. /* Activation/Deactivation is object of a shadowing mechnism. The current status is visible at ISP_LSC_STATUS::lsc_enable_status */
  7557. #define MRV_LSC_LSC_EN
  7558. #define MRV_LSC_LSC_EN_MASK 0x00000001U
  7559. #define MRV_LSC_LSC_EN_SHIFT 0U
  7560. /*! Register: isp_lsc_r_table_addr: Table RAM Address for red component (0x00000004)*/
  7561. /*! Slice: r_ram_addr:*/
  7562. /*! table address in RAM for samples of the R color component.*/
  7563. /* Will be automatically incremented by each read or write access to the table.*/
  7564. /* Valid addresses are in the range 0 to 152.*/
  7565. #define MRV_LSC_R_RAM_ADDR
  7566. #define MRV_LSC_R_RAM_ADDR_MASK 0x000001FFU
  7567. #define MRV_LSC_R_RAM_ADDR_SHIFT 0U
  7568. /*! Register: isp_lsc_gr_table_addr: Table RAM Address for green (red) component (0x00000008)*/
  7569. /*! Slice: gr_ram_addr:*/
  7570. /*! table address in RAM for samples of the G_R color component.*/
  7571. /* Will be automatically incremented by each read or write access to the table.*/
  7572. #define MRV_LSC_GR_RAM_ADDR
  7573. #define MRV_LSC_GR_RAM_ADDR_MASK 0x000001FFU
  7574. #define MRV_LSC_GR_RAM_ADDR_SHIFT 0U
  7575. /*! Register: isp_lsc_b_table_addr: Table RAM Address for blue component (0x0000000c)*/
  7576. /*! Slice: b_ram_addr:*/
  7577. /*! table address in RAM for samples of the B color component.*/
  7578. /* Will be automatically incremented by each read or write access to the table.*/
  7579. #define MRV_LSC_B_RAM_ADDR
  7580. #define MRV_LSC_B_RAM_ADDR_MASK 0x000001FFU
  7581. #define MRV_LSC_B_RAM_ADDR_SHIFT 0U
  7582. /*! Register: isp_lsc_gb_table_addr: Table RAM Address for green (blue) component (0x00000010)*/
  7583. /*! Slice: gb_ram_addr:*/
  7584. /*! table address in RAM for samples of the G_B color component.*/
  7585. /* Will be automatically incremented by each read or write access to the table.*/
  7586. #define MRV_LSC_GB_RAM_ADDR
  7587. #define MRV_LSC_GB_RAM_ADDR_MASK 0x000001FFU
  7588. #define MRV_LSC_GB_RAM_ADDR_SHIFT 0U
  7589. /*! Register: isp_lsc_r_table_data: Sample table red (0x00000014)*/
  7590. /*! Slice: r_sample_1:*/
  7591. /*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/
  7592. #define MRV_LSC_R_SAMPLE_1
  7593. #define MRV_LSC_R_SAMPLE_1_MASK 0x00FFF000U
  7594. #define MRV_LSC_R_SAMPLE_1_SHIFT 12U
  7595. /*! Slice: r_sample_0:*/
  7596. /*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/
  7597. #define MRV_LSC_R_SAMPLE_0
  7598. #define MRV_LSC_R_SAMPLE_0_MASK 0x00000FFFU
  7599. #define MRV_LSC_R_SAMPLE_0_SHIFT 0U
  7600. /*! Register: isp_lsc_gr_table_data: Sample table green (red) (0x00000018)*/
  7601. /*! Slice: gr_sample_1:*/
  7602. /*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/
  7603. #define MRV_LSC_GR_SAMPLE_1
  7604. #define MRV_LSC_GR_SAMPLE_1_MASK 0x00FFF000U
  7605. #define MRV_LSC_GR_SAMPLE_1_SHIFT 12U
  7606. /*! Slice: gr_sample_0:*/
  7607. /*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/
  7608. #define MRV_LSC_GR_SAMPLE_0
  7609. #define MRV_LSC_GR_SAMPLE_0_MASK 0x00000FFFU
  7610. #define MRV_LSC_GR_SAMPLE_0_SHIFT 0U
  7611. /*! Register: isp_lsc_b_table_data: Sample table blue (0x0000001c)*/
  7612. /*! Slice: b_sample_1:*/
  7613. /*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/
  7614. #define MRV_LSC_B_SAMPLE_1
  7615. #define MRV_LSC_B_SAMPLE_1_MASK 0x00FFF000U
  7616. #define MRV_LSC_B_SAMPLE_1_SHIFT 12U
  7617. /*! Slice: b_sample_0:*/
  7618. /*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/
  7619. #define MRV_LSC_B_SAMPLE_0
  7620. #define MRV_LSC_B_SAMPLE_0_MASK 0x00000FFFU
  7621. #define MRV_LSC_B_SAMPLE_0_SHIFT 0U
  7622. /*! Register: isp_lsc_gb_table_data: Sample table green (blue) (0x00000020)*/
  7623. /*! Slice: gb_sample_1:*/
  7624. /*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/
  7625. #define MRV_LSC_GB_SAMPLE_1
  7626. #define MRV_LSC_GB_SAMPLE_1_MASK 0x00FFF000U
  7627. #define MRV_LSC_GB_SAMPLE_1_SHIFT 12U
  7628. /*! Slice: gb_sample_0:*/
  7629. /*! correction factor at sample point (fixed point number: 2 bits integer with 10-bit fractional part, range 1..3.999)*/
  7630. #define MRV_LSC_GB_SAMPLE_0
  7631. #define MRV_LSC_GB_SAMPLE_0_MASK 0x00000FFFU
  7632. #define MRV_LSC_GB_SAMPLE_0_SHIFT 0U
  7633. /*! Register: isp_lsc_xgrad_01: Gradient table x (0x00000024)*/
  7634. /*! Slice: xgrad_1:*/
  7635. /*! factor for x-gradient calculation of sector 1 */
  7636. #define MRV_LSC_XGRAD_1
  7637. #define MRV_LSC_XGRAD_1_MASK 0x0FFF0000U
  7638. #define MRV_LSC_XGRAD_1_SHIFT 16U
  7639. /*! Slice: xgrad_0:*/
  7640. /*! factor for x-gradient calculation of sector 0 */
  7641. #define MRV_LSC_XGRAD_0
  7642. #define MRV_LSC_XGRAD_0_MASK 0x00000FFFU
  7643. #define MRV_LSC_XGRAD_0_SHIFT 0U
  7644. /*! Register: isp_lsc_xgrad_23: Gradient table x (0x00000028)*/
  7645. /*! Slice: xgrad_3:*/
  7646. /*! factor for x-gradient calculation of sector 3 */
  7647. #define MRV_LSC_XGRAD_3
  7648. #define MRV_LSC_XGRAD_3_MASK 0x0FFF0000U
  7649. #define MRV_LSC_XGRAD_3_SHIFT 16U
  7650. /*! Slice: xgrad_2:*/
  7651. /*! factor for x-gradient calculation of sector 2 */
  7652. #define MRV_LSC_XGRAD_2
  7653. #define MRV_LSC_XGRAD_2_MASK 0x00000FFFU
  7654. #define MRV_LSC_XGRAD_2_SHIFT 0U
  7655. /*! Register: isp_lsc_xgrad_45: Gradient table x (0x0000002c)*/
  7656. /*! Slice: xgrad_5:*/
  7657. /*! factor for x-gradient calculation of sector 5 */
  7658. #define MRV_LSC_XGRAD_5
  7659. #define MRV_LSC_XGRAD_5_MASK 0x0FFF0000U
  7660. #define MRV_LSC_XGRAD_5_SHIFT 16U
  7661. /*! Slice: xgrad_4:*/
  7662. /*! factor for x-gradient calculation of sector 4 */
  7663. #define MRV_LSC_XGRAD_4
  7664. #define MRV_LSC_XGRAD_4_MASK 0x00000FFFU
  7665. #define MRV_LSC_XGRAD_4_SHIFT 0U
  7666. /*! Register: isp_lsc_xgrad_67: Gradient table x (0x00000030)*/
  7667. /*! Slice: xgrad_7:*/
  7668. /*! factor for x-gradient calculation of sector 7 */
  7669. #define MRV_LSC_XGRAD_7
  7670. #define MRV_LSC_XGRAD_7_MASK 0x0FFF0000U
  7671. #define MRV_LSC_XGRAD_7_SHIFT 16U
  7672. /*! Slice: xgrad_6:*/
  7673. /*! factor for x-gradient calculation of sector 6 */
  7674. #define MRV_LSC_XGRAD_6
  7675. #define MRV_LSC_XGRAD_6_MASK 0x00000FFFU
  7676. #define MRV_LSC_XGRAD_6_SHIFT 0U
  7677. /*! Register: isp_lsc_ygrad_01: Gradient table y (0x00000034)*/
  7678. /*! Slice: ygrad_1:*/
  7679. /*! factor for y-gradient calculation of sector 1 */
  7680. #define MRV_LSC_YGRAD_1
  7681. #define MRV_LSC_YGRAD_1_MASK 0x0FFF0000U
  7682. #define MRV_LSC_YGRAD_1_SHIFT 16U
  7683. /*! Slice: ygrad_0:*/
  7684. /*! factor for y-gradient calculation of sector 0 */
  7685. #define MRV_LSC_YGRAD_0
  7686. #define MRV_LSC_YGRAD_0_MASK 0x00000FFFU
  7687. #define MRV_LSC_YGRAD_0_SHIFT 0U
  7688. /*! Register: isp_lsc_ygrad_23: Gradient table y (0x00000038)*/
  7689. /*! Slice: ygrad_3:*/
  7690. /*! factor for y-gradient calculation of sector 3 */
  7691. #define MRV_LSC_YGRAD_3
  7692. #define MRV_LSC_YGRAD_3_MASK 0x0FFF0000U
  7693. #define MRV_LSC_YGRAD_3_SHIFT 16U
  7694. /*! Slice: ygrad_2:*/
  7695. /*! factor for y-gradient calculation of sector 2 */
  7696. #define MRV_LSC_YGRAD_2
  7697. #define MRV_LSC_YGRAD_2_MASK 0x00000FFFU
  7698. #define MRV_LSC_YGRAD_2_SHIFT 0U
  7699. /*! Register: isp_lsc_ygrad_45: Gradient table y (0x0000003c)*/
  7700. /*! Slice: ygrad_5:*/
  7701. /*! factor for y-gradient calculation of sector 5 */
  7702. #define MRV_LSC_YGRAD_5
  7703. #define MRV_LSC_YGRAD_5_MASK 0x0FFF0000U
  7704. #define MRV_LSC_YGRAD_5_SHIFT 16U
  7705. /*! Slice: ygrad_4:*/
  7706. /*! factor for y-gradient calculation of sector 4 */
  7707. #define MRV_LSC_YGRAD_4
  7708. #define MRV_LSC_YGRAD_4_MASK 0x00000FFFU
  7709. #define MRV_LSC_YGRAD_4_SHIFT 0U
  7710. /*! Register: isp_lsc_ygrad_67: Gradient table y (0x00000040)*/
  7711. /*! Slice: ygrad_7:*/
  7712. /*! factor for y-gradient calculation of sector 7 */
  7713. #define MRV_LSC_YGRAD_7
  7714. #define MRV_LSC_YGRAD_7_MASK 0x0FFF0000U
  7715. #define MRV_LSC_YGRAD_7_SHIFT 16U
  7716. /*! Slice: ygrad_6:*/
  7717. /*! factor for y-gradient calculation of sector 6 */
  7718. #define MRV_LSC_YGRAD_6
  7719. #define MRV_LSC_YGRAD_6_MASK 0x00000FFFU
  7720. #define MRV_LSC_YGRAD_6_SHIFT 0U
  7721. /*! Register: isp_lsc_xsize_01: Size table (0x00000044)*/
  7722. /*! Slice: x_sect_size_1:*/
  7723. /*! sector size 1 in x-direction */
  7724. #define MRV_LSC_X_SECT_SIZE_1
  7725. #define MRV_LSC_X_SECT_SIZE_1_MASK 0x03FF0000U
  7726. #define MRV_LSC_X_SECT_SIZE_1_SHIFT 16U
  7727. /*! Slice: x_sect_size_0:*/
  7728. /*! sector size 0 in x-direction */
  7729. #define MRV_LSC_X_SECT_SIZE_0
  7730. #define MRV_LSC_X_SECT_SIZE_0_MASK 0x000003FFU
  7731. #define MRV_LSC_X_SECT_SIZE_0_SHIFT 0U
  7732. /*! Register: isp_lsc_xsize_23: Size table (0x00000048)*/
  7733. /*! Slice: x_sect_size_3:*/
  7734. /*! sector size 3 in x-direction */
  7735. #define MRV_LSC_X_SECT_SIZE_3
  7736. #define MRV_LSC_X_SECT_SIZE_3_MASK 0x03FF0000U
  7737. #define MRV_LSC_X_SECT_SIZE_3_SHIFT 16U
  7738. /*! Slice: x_sect_size_2:*/
  7739. /*! sector size 2 in x-direction */
  7740. #define MRV_LSC_X_SECT_SIZE_2
  7741. #define MRV_LSC_X_SECT_SIZE_2_MASK 0x000003FFU
  7742. #define MRV_LSC_X_SECT_SIZE_2_SHIFT 0U
  7743. /*! Register: isp_lsc_xsize_45: Size table (0x0000004c)*/
  7744. /*! Slice: x_sect_size_5:*/
  7745. /*! sector size 5 in x-direction */
  7746. #define MRV_LSC_X_SECT_SIZE_5
  7747. #define MRV_LSC_X_SECT_SIZE_5_MASK 0x03FF0000U
  7748. #define MRV_LSC_X_SECT_SIZE_5_SHIFT 16U
  7749. /*! Slice: x_sect_size_4:*/
  7750. /*! sector size 4in x-direction */
  7751. #define MRV_LSC_X_SECT_SIZE_4
  7752. #define MRV_LSC_X_SECT_SIZE_4_MASK 0x000003FFU
  7753. #define MRV_LSC_X_SECT_SIZE_4_SHIFT 0U
  7754. /*! Register: isp_lsc_xsize_67: Size table (0x00000050)*/
  7755. /*! Slice: x_sect_size_7:*/
  7756. /*! sector size 7 in x-direction */
  7757. #define MRV_LSC_X_SECT_SIZE_7
  7758. #define MRV_LSC_X_SECT_SIZE_7_MASK 0x03FF0000U
  7759. #define MRV_LSC_X_SECT_SIZE_7_SHIFT 16U
  7760. /*! Slice: x_sect_size_6:*/
  7761. /*! sector size 6 in x-direction */
  7762. #define MRV_LSC_X_SECT_SIZE_6
  7763. #define MRV_LSC_X_SECT_SIZE_6_MASK 0x000003FFU
  7764. #define MRV_LSC_X_SECT_SIZE_6_SHIFT 0U
  7765. /*! Register: isp_lsc_ysize_01: Size table (0x00000054)*/
  7766. /*! Slice: y_sect_size_1:*/
  7767. /*! sector size 1 in y-direction */
  7768. #define MRV_LSC_Y_SECT_SIZE_1
  7769. #define MRV_LSC_Y_SECT_SIZE_1_MASK 0x03FF0000U
  7770. #define MRV_LSC_Y_SECT_SIZE_1_SHIFT 16U
  7771. /*! Slice: y_sect_size_0:*/
  7772. /*! sector size 0 in y-direction */
  7773. #define MRV_LSC_Y_SECT_SIZE_0
  7774. #define MRV_LSC_Y_SECT_SIZE_0_MASK 0x000003FFU
  7775. #define MRV_LSC_Y_SECT_SIZE_0_SHIFT 0U
  7776. /*! Register: isp_lsc_ysize_23: Size table (0x00000058)*/
  7777. /*! Slice: y_sect_size_3:*/
  7778. /*! sector size 3 in y-direction */
  7779. #define MRV_LSC_Y_SECT_SIZE_3
  7780. #define MRV_LSC_Y_SECT_SIZE_3_MASK 0x03FF0000U
  7781. #define MRV_LSC_Y_SECT_SIZE_3_SHIFT 16U
  7782. /*! Slice: y_sect_size_2:*/
  7783. /*! sector size 2 in y-direction */
  7784. #define MRV_LSC_Y_SECT_SIZE_2
  7785. #define MRV_LSC_Y_SECT_SIZE_2_MASK 0x000003FFU
  7786. #define MRV_LSC_Y_SECT_SIZE_2_SHIFT 0U
  7787. /*! Register: isp_lsc_ysize_45: Size table (0x0000005c)*/
  7788. /*! Slice: y_sect_size_5:*/
  7789. /*! sector size 5 in y-direction */
  7790. #define MRV_LSC_Y_SECT_SIZE_5
  7791. #define MRV_LSC_Y_SECT_SIZE_5_MASK 0x03FF0000U
  7792. #define MRV_LSC_Y_SECT_SIZE_5_SHIFT 16U
  7793. /*! Slice: y_sect_size_4:*/
  7794. /*! sector size 4 in y-direction */
  7795. #define MRV_LSC_Y_SECT_SIZE_4
  7796. #define MRV_LSC_Y_SECT_SIZE_4_MASK 0x000003FFU
  7797. #define MRV_LSC_Y_SECT_SIZE_4_SHIFT 0U
  7798. /*! Register: isp_lsc_ysize_67: Size table (0x00000060)*/
  7799. /*! Slice: y_sect_size_7:*/
  7800. /*! sector size 7 in y-direction */
  7801. #define MRV_LSC_Y_SECT_SIZE_7
  7802. #define MRV_LSC_Y_SECT_SIZE_7_MASK 0x03FF0000U
  7803. #define MRV_LSC_Y_SECT_SIZE_7_SHIFT 16U
  7804. /*! Slice: y_sect_size_6:*/
  7805. /*! sector size 6 in y-direction */
  7806. #define MRV_LSC_Y_SECT_SIZE_6
  7807. #define MRV_LSC_Y_SECT_SIZE_6_MASK 0x000003FFU
  7808. #define MRV_LSC_Y_SECT_SIZE_6_SHIFT 0U
  7809. /*! Register: isp_lsc_table_sel: Lens shade table set selection (0x00000064)*/
  7810. /*! Slice: table_sel:*/
  7811. /*! 0: next active tables set is table set 0.*/
  7812. /* 1: next active tables set is table set 1.*/
  7813. /* Table selection is object of a shadowing mechnism. The current status is visible at ISP_LSC_STATUS::active_table.*/
  7814. #define MRV_LSC_TABLE_SEL
  7815. #define MRV_LSC_TABLE_SEL_MASK 0x00000001U
  7816. #define MRV_LSC_TABLE_SEL_SHIFT 0U
  7817. /*! Register: isp_lsc_status: Lens shade status (0x00000068)*/
  7818. /*! Slice: active_table:*/
  7819. /*! 0: currently active tables set is table set 0 */
  7820. /* 1: currently active tables set is table set 1 */
  7821. #define MRV_LSC_ACTIVE_TABLE
  7822. #define MRV_LSC_ACTIVE_TABLE_MASK 0x00000002U
  7823. #define MRV_LSC_ACTIVE_TABLE_SHIFT 1U
  7824. /*! Slice: lsc_en_status:*/
  7825. /*! 0: lens shading correction is currently off */
  7826. /* 1: lens shading correction is currently on */
  7827. #define MRV_LSC_LSC_EN_STATUS
  7828. #define MRV_LSC_LSC_EN_STATUS_MASK 0x00000001U
  7829. #define MRV_LSC_LSC_EN_STATUS_SHIFT 0U
  7830. /*! Register: isp_is_ctrl: Image Stabilization Control Register (0x00000000)*/
  7831. /*! Slice: is_en:*/
  7832. /*! 1: image stabilization switched on */
  7833. /* 0: image stabilization switched off */
  7834. #define MRV_IS_IS_EN
  7835. #define MRV_IS_IS_EN_MASK 0x00000001U
  7836. #define MRV_IS_IS_EN_SHIFT 0U
  7837. /*! Register: isp_is_recenter: Recenter register (0x00000004)*/
  7838. /*! Slice: is_recenter:*/
  7839. /*! 000: recenter feature switched off */
  7840. /* 1..7: recentering by (cur_h/v_offs-H/V_OFFS)/2^RECENTER */
  7841. #define MRV_IS_IS_RECENTER
  7842. #define MRV_IS_IS_RECENTER_MASK 0x00000007U
  7843. #define MRV_IS_IS_RECENTER_SHIFT 0U
  7844. /*! Register: isp_is_h_offs: Horizontal offset of output window (0x00000008)*/
  7845. /*! Slice: is_h_offs:*/
  7846. /*! horizontal picture offset in pixel */
  7847. #define MRV_IS_IS_H_OFFS
  7848. #define MRV_IS_IS_H_OFFS_MASK 0x00003FFFU
  7849. #define MRV_IS_IS_H_OFFS_SHIFT 0U
  7850. /*! Register: isp_is_v_offs: Vertical offset of output window (0x0000000c)*/
  7851. /*! Slice: is_v_offs:*/
  7852. /*! vertical picture offset in lines */
  7853. #define MRV_IS_IS_V_OFFS
  7854. #define MRV_IS_IS_V_OFFS_MASK 0x00003FFFU
  7855. #define MRV_IS_IS_V_OFFS_SHIFT 0U
  7856. /*! Register: isp_is_h_size: Output horizontal picture size (0x00000010)*/
  7857. /*! Slice: is_h_size:*/
  7858. /*! horizontal picture size in pixel */
  7859. /* if ISP_MODE is set to */
  7860. /* 001-(ITU-R BT.656 YUV),*/
  7861. /* 010-( ITU-R BT.601 YUV),*/
  7862. /* 011-( ITU-R BT.601 Bayer RGB),*/
  7863. /* 101-( ITU-R BT.656 Bayer RGB)*/
  7864. /* only even numbers are accepted, because complete quadruples of YUYV(YCbYCr) are needed for the following modules. If an odd size is programmed the value will be truncated to even size.*/
  7865. #define MRV_IS_IS_H_SIZE
  7866. #define MRV_IS_IS_H_SIZE_MASK 0x00003FFFU
  7867. #define MRV_IS_IS_H_SIZE_SHIFT 0U
  7868. /*! Register: isp_is_v_size: Output vertical picture size (0x00000014)*/
  7869. /*! Slice: is_v_size:*/
  7870. /*! vertical picture size in lines */
  7871. #define MRV_IS_IS_V_SIZE
  7872. #define MRV_IS_IS_V_SIZE_MASK 0x00003FFFU
  7873. #define MRV_IS_IS_V_SIZE_SHIFT 0U
  7874. /*! Register: isp_is_max_dx: Maximum Horizontal Displacement (0x00000018)*/
  7875. /*! Slice: is_max_dx:*/
  7876. /*! maximum allowed accumulated horizontal displacement in pixels */
  7877. #define MRV_IS_IS_MAX_DX
  7878. #define MRV_IS_IS_MAX_DX_MASK 0x00001FFFU
  7879. #define MRV_IS_IS_MAX_DX_SHIFT 0U
  7880. /*! Register: isp_is_max_dy: Maximum Vertical Displacement (0x0000001c)*/
  7881. /*! Slice: is_max_dy:*/
  7882. /*! maximum allowed accumulated vertical displacement in lines */
  7883. #define MRV_IS_IS_MAX_DY
  7884. #define MRV_IS_IS_MAX_DY_MASK 0x00001FFFU
  7885. #define MRV_IS_IS_MAX_DY_SHIFT 0U
  7886. /*! Register: isp_is_displace: Camera displacement (0x00000020)*/
  7887. /*! Slice: dy:*/
  7888. /*! ISP_IS will compensate for vertical camera displacement of DY lines in the next frame */
  7889. #define MRV_IS_DY
  7890. #define MRV_IS_DY_MASK 0x1FFF0000U
  7891. #define MRV_IS_DY_SHIFT 16U
  7892. /*! Slice: dx:*/
  7893. /*! ISP_IS will compensate for horizontal camera displacement of DX pixels in the next frame */
  7894. #define MRV_IS_DX
  7895. #define MRV_IS_DX_MASK 0x00001FFFU
  7896. #define MRV_IS_DX_SHIFT 0U
  7897. /*! Register: isp_is_h_offs_shd: current horizontal offset of output window (shadow register) (0x00000024)*/
  7898. /*! Slice: is_h_offs_shd:*/
  7899. /*! current horizonatl picture offset in lines */
  7900. #define MRV_IS_IS_H_OFFS_SHD
  7901. #define MRV_IS_IS_H_OFFS_SHD_MASK 0x00003FFFU
  7902. #define MRV_IS_IS_H_OFFS_SHD_SHIFT 0U
  7903. /*! Register: isp_is_v_offs_shd: current vertical offset of output window (shadow register) (0x00000028)*/
  7904. /*! Slice: is_v_offs_shd:*/
  7905. /*! current vertical picture offset in lines */
  7906. #define MRV_IS_IS_V_OFFS_SHD
  7907. #define MRV_IS_IS_V_OFFS_SHD_MASK 0x00003FFFU
  7908. #define MRV_IS_IS_V_OFFS_SHD_SHIFT 0U
  7909. /*! Register: isp_is_h_size_shd: current output horizontal picture size (shadow register) (0x0000002c)*/
  7910. /*! Slice: isp_h_size_shd:*/
  7911. /*! current horizontal picture size in pixel */
  7912. #define MRV_IS_ISP_H_SIZE_SHD
  7913. #define MRV_IS_ISP_H_SIZE_SHD_MASK 0x00003FFFU
  7914. #define MRV_IS_ISP_H_SIZE_SHD_SHIFT 0U
  7915. /*! Register: isp_is_v_size_shd: current output vertical picture size (shadow register) (0x00000030)*/
  7916. /*! Slice: isp_v_size_shd:*/
  7917. /*! vertical picture size in lines */
  7918. #define MRV_IS_ISP_V_SIZE_SHD
  7919. #define MRV_IS_ISP_V_SIZE_SHD_MASK 0x00003FFFU
  7920. #define MRV_IS_ISP_V_SIZE_SHD_SHIFT 0U
  7921. /*! Register: isp_hist_prop: Histogram properties (0x00000000)*/
  7922. /*! Slice: stepsize:*/
  7923. /*! histogram predivider, process every (stepsize)th pixel, all other pixels are skipped */
  7924. /* 0,1,2: not allowed */
  7925. /* 3: process every third input pixel */
  7926. /* 4: process every fourth input pixel */
  7927. /* ...*/
  7928. /* 7FH: process every 127th pixel */
  7929. #define MRV_HIST_STEPSIZE
  7930. #define MRV_HIST_STEPSIZE_MASK 0x000003F8U
  7931. #define MRV_HIST_STEPSIZE_SHIFT 3U
  7932. /*! Slice: hist_mode:*/
  7933. /*! histogram mode, luminance is taken at ISP output before output formatter, RGB is taken at xtalk output */
  7934. /* 7, 6: must not be used */
  7935. /* 5: Y (luminance) histogram */
  7936. /* 4: B histogram */
  7937. /* 3: G histogram */
  7938. /* 2: R histogram */
  7939. /* 1: RGB combined histogram */
  7940. /* 0: disable, no measurements */
  7941. #define MRV_HIST_MODE
  7942. #define MRV_HIST_MODE_MASK 0x00000007U
  7943. #define MRV_HIST_MODE_SHIFT 0U
  7944. /*! Register: isp_hist_h_offs: Histogram window horizontal offset for first window of 25 sub-windows (0x00000004)*/
  7945. /*! Slice: hist_h_offset:*/
  7946. /*! Horizontal offset of first window in pixels.*/
  7947. #define MRV_HIST_H_OFFSET
  7948. #define MRV_HIST_H_OFFSET_MASK 0x00001FFFU
  7949. #define MRV_HIST_H_OFFSET_SHIFT 0U
  7950. /*! Register: isp_hist_v_offs: Histogram window vertical offset for first window of 25 sub-windows (0x00000008)*/
  7951. /*! Slice: hist_v_offset:*/
  7952. /*! Vertical offset of first window in pixels.*/
  7953. #define MRV_HIST_V_OFFSET
  7954. #define MRV_HIST_V_OFFSET_MASK 0x00001FFFU
  7955. #define MRV_HIST_V_OFFSET_SHIFT 0U
  7956. /*! Register: isp_hist_h_size: Horizontal (sub-)window size (0x0000000c)*/
  7957. /*! Slice: hist_h_size:*/
  7958. /*! Horizontal size in pixels of one sub-window, if histogram version 3 is implemented.*/
  7959. #define MRV_HIST_H_SIZE
  7960. #define MRV_HIST_H_SIZE_MASK 0x000007FFU
  7961. #define MRV_HIST_H_SIZE_SHIFT 0U
  7962. /*! Register: isp_hist_v_size: Vertical (sub-)window size (0x00000010)*/
  7963. /*! Slice: hist_v_size:*/
  7964. /*! Vertical size in lines of one sub-window, if histogram version 3 is implemented.*/
  7965. #define MRV_HIST_V_SIZE
  7966. #define MRV_HIST_V_SIZE_MASK 0x000007FFU
  7967. #define MRV_HIST_V_SIZE_SHIFT 0U
  7968. #ifndef ISP_HIST256
  7969. /*! Register array: isp_hist_bin: histogram measurement result bin (0x028 + n*0x4 (n=0..15))*/
  7970. /*! Slice: hist_bin_n:*/
  7971. /* measured bin count as 16-bit unsigned integer value plus 4 bit fractional part */
  7972. #define MRV_HIST_BIN_N
  7973. #define MRV_HIST_BIN_N_MASK 0x000FFFFFU
  7974. #define MRV_HIST_BIN_N_SHIFT 0U
  7975. #else
  7976. /*! Register array: isp_hist_bin: histogram measurement result bin (0x028 + n*0x4 (n=0..15))*/
  7977. /*! Slice: hist_bin_n:*/
  7978. /* measured bin count as 26-bit unsigned integer value plus 4 bit fractional part */
  7979. #define MRV_HIST_BIN_N
  7980. #define MRV_HIST_BIN_N_MASK 0x3FFFFFFFU
  7981. #define MRV_HIST_BIN_N_SHIFT 0U
  7982. #endif
  7983. /*! Register: isp_hist_weight_00to30: Weighting factor for sub-windows (0x00000054)*/
  7984. /*! Slice: hist_weight_30:*/
  7985. /*! weighting factor for sub-window 30 */
  7986. #define MRV_HIST_WEIGHT_30
  7987. #define MRV_HIST_WEIGHT_30_MASK 0x1F000000U
  7988. #define MRV_HIST_WEIGHT_30_SHIFT 24U
  7989. /*! Slice: hist_weight_20:*/
  7990. /*! weighting factor for sub-window 20 */
  7991. #define MRV_HIST_WEIGHT_20
  7992. #define MRV_HIST_WEIGHT_20_MASK 0x001F0000U
  7993. #define MRV_HIST_WEIGHT_20_SHIFT 16U
  7994. /*! Slice: hist_weight_10:*/
  7995. /*! weighting factor for sub-window 10 */
  7996. #define MRV_HIST_WEIGHT_10
  7997. #define MRV_HIST_WEIGHT_10_MASK 0x00001F00U
  7998. #define MRV_HIST_WEIGHT_10_SHIFT 8U
  7999. /*! Slice: hist_weight_00:*/
  8000. /*! weighting factor for sub-window 00 */
  8001. #define MRV_HIST_WEIGHT_00
  8002. #define MRV_HIST_WEIGHT_00_MASK 0x0000001FU
  8003. #define MRV_HIST_WEIGHT_00_SHIFT 0U
  8004. /*! Register: isp_hist_weight_40to21: Weighting factor for sub-windows (0x00000058)*/
  8005. /*! Slice: hist_weight_21:*/
  8006. /*! weighting factor for sub-window 21 */
  8007. #define MRV_HIST_WEIGHT_21
  8008. #define MRV_HIST_WEIGHT_21_MASK 0x1F000000U
  8009. #define MRV_HIST_WEIGHT_21_SHIFT 24U
  8010. /*! Slice: hist_weight_11:*/
  8011. /*! weighting factor for sub-window 11 */
  8012. #define MRV_HIST_WEIGHT_11
  8013. #define MRV_HIST_WEIGHT_11_MASK 0x001F0000U
  8014. #define MRV_HIST_WEIGHT_11_SHIFT 16U
  8015. /*! Slice: hist_weight_01:*/
  8016. /*! weighting factor for sub-window 01 */
  8017. #define MRV_HIST_WEIGHT_01
  8018. #define MRV_HIST_WEIGHT_01_MASK 0x00001F00U
  8019. #define MRV_HIST_WEIGHT_01_SHIFT 8U
  8020. /*! Slice: hist_weight_40:*/
  8021. /*! weighting factor for sub-window 40 */
  8022. #define MRV_HIST_WEIGHT_40
  8023. #define MRV_HIST_WEIGHT_40_MASK 0x0000001FU
  8024. #define MRV_HIST_WEIGHT_40_SHIFT 0U
  8025. /*! Register: isp_hist_weight_31to12: Weighting factor for sub-windows (0x0000005c)*/
  8026. /*! Slice: hist_weight_12:*/
  8027. /*! weighting factor for sub-window 12 */
  8028. #define MRV_HIST_WEIGHT_12
  8029. #define MRV_HIST_WEIGHT_12_MASK 0x1F000000U
  8030. #define MRV_HIST_WEIGHT_12_SHIFT 24U
  8031. /*! Slice: hist_weight_02:*/
  8032. /*! weighting factor for sub-window 02 */
  8033. #define MRV_HIST_WEIGHT_02
  8034. #define MRV_HIST_WEIGHT_02_MASK 0x001F0000U
  8035. #define MRV_HIST_WEIGHT_02_SHIFT 16U
  8036. /*! Slice: hist_weight_41:*/
  8037. /*! weighting factor for sub-window 41 */
  8038. #define MRV_HIST_WEIGHT_41
  8039. #define MRV_HIST_WEIGHT_41_MASK 0x00001F00U
  8040. #define MRV_HIST_WEIGHT_41_SHIFT 8U
  8041. /*! Slice: hist_weight_31:*/
  8042. /*! weighting factor for sub-window 31 */
  8043. #define MRV_HIST_WEIGHT_31
  8044. #define MRV_HIST_WEIGHT_31_MASK 0x0000001FU
  8045. #define MRV_HIST_WEIGHT_31_SHIFT 0U
  8046. /*! Register: isp_hist_weight_22to03: Weighting factor for sub-windows (0x00000060)*/
  8047. /*! Slice: hist_weight_03:*/
  8048. /*! weighting factor for sub-window 03 */
  8049. #define MRV_HIST_WEIGHT_03
  8050. #define MRV_HIST_WEIGHT_03_MASK 0x1F000000U
  8051. #define MRV_HIST_WEIGHT_03_SHIFT 24U
  8052. /*! Slice: hist_weight_42:*/
  8053. /*! weighting factor for sub-window 42 */
  8054. #define MRV_HIST_WEIGHT_42
  8055. #define MRV_HIST_WEIGHT_42_MASK 0x001F0000U
  8056. #define MRV_HIST_WEIGHT_42_SHIFT 16U
  8057. /*! Slice: hist_weight_32:*/
  8058. /*! weighting factor for sub-window 32 */
  8059. #define MRV_HIST_WEIGHT_32
  8060. #define MRV_HIST_WEIGHT_32_MASK 0x00001F00U
  8061. #define MRV_HIST_WEIGHT_32_SHIFT 8U
  8062. /*! Slice: hist_weight_22:*/
  8063. /*! weighting factor for sub-window 22 */
  8064. #define MRV_HIST_WEIGHT_22
  8065. #define MRV_HIST_WEIGHT_22_MASK 0x0000001FU
  8066. #define MRV_HIST_WEIGHT_22_SHIFT 0U
  8067. /*! Register: isp_hist_weight_13to43: Weighting factor for sub-windows (0x00000064)*/
  8068. /*! Slice: hist_weight_43:*/
  8069. /*! weighting factor for sub-window 43 */
  8070. #define MRV_HIST_WEIGHT_43
  8071. #define MRV_HIST_WEIGHT_43_MASK 0x1F000000U
  8072. #define MRV_HIST_WEIGHT_43_SHIFT 24U
  8073. /*! Slice: hist_weight_33:*/
  8074. /*! weighting factor for sub-window 33 */
  8075. #define MRV_HIST_WEIGHT_33
  8076. #define MRV_HIST_WEIGHT_33_MASK 0x001F0000U
  8077. #define MRV_HIST_WEIGHT_33_SHIFT 16U
  8078. /*! Slice: hist_weight_23:*/
  8079. /*! weighting factor for sub-window 23 */
  8080. #define MRV_HIST_WEIGHT_23
  8081. #define MRV_HIST_WEIGHT_23_MASK 0x00001F00U
  8082. #define MRV_HIST_WEIGHT_23_SHIFT 8U
  8083. /*! Slice: hist_weight_13:*/
  8084. /*! weighting factor for sub-window 13 */
  8085. #define MRV_HIST_WEIGHT_13
  8086. #define MRV_HIST_WEIGHT_13_MASK 0x0000001FU
  8087. #define MRV_HIST_WEIGHT_13_SHIFT 0U
  8088. /*! Register: isp_hist_weight_04to34: Weighting factor for sub-windows (0x00000068)*/
  8089. /*! Slice: hist_weight_34:*/
  8090. /*! weighting factor for sub-window 34 */
  8091. #define MRV_HIST_WEIGHT_34
  8092. #define MRV_HIST_WEIGHT_34_MASK 0x1F000000U
  8093. #define MRV_HIST_WEIGHT_34_SHIFT 24U
  8094. /*! Slice: hist_weight_24:*/
  8095. /*! weighting factor for sub-window 24 */
  8096. #define MRV_HIST_WEIGHT_24
  8097. #define MRV_HIST_WEIGHT_24_MASK 0x001F0000U
  8098. #define MRV_HIST_WEIGHT_24_SHIFT 16U
  8099. /*! Slice: hist_weight_14:*/
  8100. /*! weighting factor for sub-window 14 */
  8101. #define MRV_HIST_WEIGHT_14
  8102. #define MRV_HIST_WEIGHT_14_MASK 0x00001F00U
  8103. #define MRV_HIST_WEIGHT_14_SHIFT 8U
  8104. /*! Slice: hist_weight_04:*/
  8105. /*! weighting factor for sub-window 04 */
  8106. #define MRV_HIST_WEIGHT_04
  8107. #define MRV_HIST_WEIGHT_04_MASK 0x0000001FU
  8108. #define MRV_HIST_WEIGHT_04_SHIFT 0U
  8109. /*! Register: isp_hist_weight_44: Weighting factor for sub-windows (0x0000006c)*/
  8110. /*! Slice: hist_weight_44:*/
  8111. /*! weighting factor for sub-window 44 */
  8112. #define MRV_HIST_WEIGHT_44
  8113. #define MRV_HIST_WEIGHT_44_MASK 0x0000001FU
  8114. #define MRV_HIST_WEIGHT_44_SHIFT 0U
  8115. /*! Register: isp_filt_mode: mode control register for the filter block (0x00000000)*/
  8116. /*! Slice: stage1_select:*/
  8117. /*! Green filter stage 1 select (range 0x0...0x8)*/
  8118. /* 0x0 maximum blurring */
  8119. /* 0x4 Default */
  8120. /* 0x7 minimum blurring */
  8121. /* 0x8 filter stage1 bypass */
  8122. /* For a detailed description refer to chapter "ISP Filter Programming" of user manual */
  8123. #define MRV_FILT_STAGE1_SELECT
  8124. #define MRV_FILT_STAGE1_SELECT_MASK 0x00000F00U
  8125. #define MRV_FILT_STAGE1_SELECT_SHIFT 8U
  8126. /*! Slice: filt_chr_h_mode:*/
  8127. /*! Chroma filter horizontal mode */
  8128. /* 00 horizontal chroma filter bypass */
  8129. /* 01 horizontal chroma filter 1 static mask =[10 12 10]*/
  8130. /* 10 horizontal chroma filter 2 (dynamic blur1)*/
  8131. /* 11 horizontal chroma filter 3 (dynamic blur2) Default */
  8132. #define MRV_FILT_FILT_CHR_H_MODE
  8133. #define MRV_FILT_FILT_CHR_H_MODE_MASK 0x000000C0U
  8134. #define MRV_FILT_FILT_CHR_H_MODE_SHIFT 6U
  8135. /*! Slice: filt_chr_v_mode:*/
  8136. /*! Chroma filter vertical mode */
  8137. /* 00 vertical chroma filter bypass */
  8138. /* 01 vertical chroma filter 1 static[8 16 8]*/
  8139. /* 10 vertical chroma filter 2 static[10 12 10]*/
  8140. /* 11 vertical chroma filter 3 static[12 8 12] Default */
  8141. #define MRV_FILT_FILT_CHR_V_MODE
  8142. #define MRV_FILT_FILT_CHR_V_MODE_MASK 0x00000030U
  8143. #define MRV_FILT_FILT_CHR_V_MODE_SHIFT 4U
  8144. /*! Slice: filt_mode:*/
  8145. /*! 0 green filter static mode (active filter factor = FILT_FAC_MID)*/
  8146. /* 1 dynamic noise reduction/sharpen Default */
  8147. #define MRV_FILT_FILT_MODE
  8148. #define MRV_FILT_FILT_MODE_MASK 0x00000002U
  8149. #define MRV_FILT_FILT_MODE_SHIFT 1U
  8150. /*! Slice: filt_enable:*/
  8151. /*! 1 enable filter */
  8152. /* 0 bypass filter Default */
  8153. #define MRV_FILT_FILT_ENABLE
  8154. #define MRV_FILT_FILT_ENABLE_MASK 0x00000001U
  8155. #define MRV_FILT_FILT_ENABLE_SHIFT 0U
  8156. /*! Register: isp_filt_thresh_bl0: Blurring threshold 0 (0x00000028)*/
  8157. /*! Slice: filt_thresh_bl0:*/
  8158. /*! If filt_thresh_bl1 < sum_grad < filt_thresh_bl0 then filt_fac_bl0 is selected */
  8159. #define MRV_FILT_FILT_THRESH_BL0
  8160. #define MRV_FILT_FILT_THRESH_BL0_MASK 0x000003FFU
  8161. #define MRV_FILT_FILT_THRESH_BL0_SHIFT 0U
  8162. /*! Register: isp_filt_thresh_bl1: Blurring threshold 1 (0x0000002c)*/
  8163. /*! Slice: filt_thresh_bl1:*/
  8164. /*! If sum_grad < filt_thresh_bl1 then filt_fac_bl1 is selected */
  8165. #define MRV_FILT_FILT_THRESH_BL1
  8166. #define MRV_FILT_FILT_THRESH_BL1_MASK 0x000003FFU
  8167. #define MRV_FILT_FILT_THRESH_BL1_SHIFT 0U
  8168. /*! Register: isp_filt_thresh_sh0: Sharpening threshold 0 (0x00000030)*/
  8169. /*! Slice: filt_thresh_sh0:*/
  8170. /*! If filt_thresh_sh0 < sum_grad < filt_thresh_sh1 then filt_thresh_sh0 is selected */
  8171. #define MRV_FILT_FILT_THRESH_SH0
  8172. #define MRV_FILT_FILT_THRESH_SH0_MASK 0x000003FFU
  8173. #define MRV_FILT_FILT_THRESH_SH0_SHIFT 0U
  8174. /*! Register: isp_filt_thresh_sh1: Sharpening threshold 1 (0x00000034)*/
  8175. /*! Slice: filt_thresh_sh1:*/
  8176. /*! If filt_thresh_sh1 < sum_grad then filt_thresh_sh1 is selected */
  8177. #define MRV_FILT_FILT_THRESH_SH1
  8178. #define MRV_FILT_FILT_THRESH_SH1_MASK 0x000003FFU
  8179. #define MRV_FILT_FILT_THRESH_SH1_SHIFT 0U
  8180. /*! Register: isp_filt_lum_weight: Parameters for luminance weight function (0x00000038)*/
  8181. /*! Slice: lum_weight_gain:*/
  8182. /*! Gain select of luminance weight function */
  8183. #define MRV_FILT_LUM_WEIGHT_GAIN
  8184. #define MRV_FILT_LUM_WEIGHT_GAIN_MASK 0x00070000U
  8185. #define MRV_FILT_LUM_WEIGHT_GAIN_SHIFT 16U
  8186. /*! Slice: lum_weight_kink:*/
  8187. /*! Kink position of luminance weight function */
  8188. #define MRV_FILT_LUM_WEIGHT_KINK
  8189. #define MRV_FILT_LUM_WEIGHT_KINK_MASK 0x0000FF00U
  8190. #define MRV_FILT_LUM_WEIGHT_KINK_SHIFT 8U
  8191. /*! Slice: lum_weight_min:*/
  8192. /*! Minimum value of luminance weight function */
  8193. #define MRV_FILT_LUM_WEIGHT_MIN
  8194. #define MRV_FILT_LUM_WEIGHT_MIN_MASK 0x000000FFU
  8195. #define MRV_FILT_LUM_WEIGHT_MIN_SHIFT 0U
  8196. /*! Register: isp_filt_fac_sh1: filter factor sharp1 (0x0000003c)*/
  8197. /*! Slice: filt_fac_sh1:*/
  8198. /*! Filter factor for sharp1 level */
  8199. #define MRV_FILT_FILT_FAC_SH1
  8200. #define MRV_FILT_FILT_FAC_SH1_MASK 0x0000003FU
  8201. #define MRV_FILT_FILT_FAC_SH1_SHIFT 0U
  8202. /*! Register: isp_filt_fac_sh0: filter factor sharp0 (0x00000040)*/
  8203. /*! Slice: filt_fac_sh0:*/
  8204. /*! Filter factor for sharp0 level */
  8205. #define MRV_FILT_FILT_FAC_SH0
  8206. #define MRV_FILT_FILT_FAC_SH0_MASK 0x0000003FU
  8207. #define MRV_FILT_FILT_FAC_SH0_SHIFT 0U
  8208. /*! Register: isp_filt_fac_mid: filter factor middle (0x00000044)*/
  8209. /*! Slice: filt_fac_mid:*/
  8210. /*! Filter factor for mid level and for static filter mode */
  8211. #define MRV_FILT_FILT_FAC_MID
  8212. #define MRV_FILT_FILT_FAC_MID_MASK 0x0000003FU
  8213. #define MRV_FILT_FILT_FAC_MID_SHIFT 0U
  8214. /*! Register: isp_filt_fac_bl0: Parameter for blur 0 filter (0x00000048)*/
  8215. /*! Slice: filt_fac_bl0:*/
  8216. /*! Filter factor for blur 0 level */
  8217. #define MRV_FILT_FILT_FAC_BL0
  8218. #define MRV_FILT_FILT_FAC_BL0_MASK 0x0000003FU
  8219. #define MRV_FILT_FILT_FAC_BL0_SHIFT 0U
  8220. /*! Register: isp_filt_fac_bl1: Parameter for blur 1 filter (0x0000004c)*/
  8221. /*! Slice: filt_fac_bl1:*/
  8222. /*! Filter factor for blur 1 level (max blur)*/
  8223. #define MRV_FILT_FILT_FAC_BL1
  8224. #define MRV_FILT_FILT_FAC_BL1_MASK 0x0000003FU
  8225. #define MRV_FILT_FILT_FAC_BL1_SHIFT 0U
  8226. /*! Register: isp_cac_ctrl: Control register for chromatic aberration correction (0x00000000)*/
  8227. /*! Slice: h_clip_mode:*/
  8228. /*! Defines the maximum red/blue pixel shift in horizontal direction At pixel positions, that require a larger displacement, the maximum shift value is used instead (vector clipping)*/
  8229. /* 0: Set horizontal vector clipping to +/-4 pixel displacement (Default)*/
  8230. /* 1: Set horizontal vector clipping to +/-4 or +/-5 pixel displacement depending on pixel position inside the Bayer raster (dynamic switching between +/-4 and +/-5)*/
  8231. #define MRV_CAC_H_CLIP_MODE
  8232. #define MRV_CAC_H_CLIP_MODE_MASK 0x00000008U
  8233. #define MRV_CAC_H_CLIP_MODE_SHIFT 3U
  8234. /*! Slice: v_clip_mode:*/
  8235. /*! Defines the maximum red/blue pixel shift in vertical direction */
  8236. /* 00: Set vertical vector clipping to +/-2 pixel ; fix filter_enable (Default)*/
  8237. /* 01: Set vertical vector clipping to +/-3 pixel; dynamic filter_enable for chroma low pass filter */
  8238. /* 10: Set vertical vector clipping +/-3 or +/-4 pixel displacement depending on pixel position inside the Bayer raster (dynamic switching between +/-3 and +/-4)*/
  8239. /* 11: reserved */
  8240. #define MRV_CAC_V_CLIP_MODE
  8241. #define MRV_CAC_V_CLIP_MODE_MASK 0x00000006U
  8242. #define MRV_CAC_V_CLIP_MODE_SHIFT 1U
  8243. /*! Slice: cac_en:*/
  8244. /*! 0: chromatic aberration correction off */
  8245. /* 1: chromatic aberration correction on */
  8246. #define MRV_CAC_CAC_EN
  8247. #define MRV_CAC_CAC_EN_MASK 0x00000001U
  8248. #define MRV_CAC_CAC_EN_SHIFT 0U
  8249. /*! Register: isp_cac_count_start: Preload values for CAC pixel and line counter (0x00000004)*/
  8250. /*! Slice: v_count_start:*/
  8251. /*! 13 bit v_count preload value (range 8191 ... 1) of the vertical CAC line counter. Before frame start v_count has to be preloaded with (v_size/2 + v_center_offset), with */
  8252. /* v_size the image height and */
  8253. /* v_center_offset the vertical distance between image center and optical center.*/
  8254. /**/
  8255. /* After frame start the v_count decrements with every line until a value of zero is reached for the line in the optical center. Than the v_sign bit toggles and the v_counter decrements with every line until end of frame.*/
  8256. #define MRV_CAC_V_COUNT_START
  8257. #define MRV_CAC_V_COUNT_START_MASK 0x1FFF0000U
  8258. #define MRV_CAC_V_COUNT_START_SHIFT 16U
  8259. /*! Slice: h_count_start:*/
  8260. /*! 13 bit h_count preload value (range 8191 .. 1) of the horizontal CAC pixel counter. Before line start h_count has to be preloaded with (h_size/2 + h_center_offset), with */
  8261. /* h_size the image width and */
  8262. /* h_center_offset the horizontal distance between image center and optical center.*/
  8263. /**/
  8264. /* After line start the h_count decrements with every pixel until a value of zero is reached for the column in the optical center. Than the h_sign bit toggles and the h_counter increments with every pixel until end of line.*/
  8265. #define MRV_CAC_H_COUNT_START
  8266. #define MRV_CAC_H_COUNT_START_MASK 0x00001FFFU
  8267. #define MRV_CAC_H_COUNT_START_SHIFT 0U
  8268. /*! Register: isp_cac_a: Linear Parameters for radial shift calculation (0x00000008)*/
  8269. /*! Slice: A_Blue:*/
  8270. /*! Parameter A_Blue for radial blue shift calculation, according to */
  8271. /*(A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/
  8272. /* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/
  8273. #define MRV_CAC_A_BLUE
  8274. #define MRV_CAC_A_BLUE_MASK 0x01FF0000U
  8275. #define MRV_CAC_A_BLUE_SHIFT 16U
  8276. /*! Slice: A_Red:*/
  8277. /*! Parameter A_Red for radial red shift calculation, according to */
  8278. /*(A_Red * r + B_Red * r^2 + C_Red * r^3).*/
  8279. /* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/
  8280. #define MRV_CAC_A_RED
  8281. #define MRV_CAC_A_RED_MASK 0x000001FFU
  8282. #define MRV_CAC_A_RED_SHIFT 0U
  8283. /*! Register: isp_cac_b: Square Parameters for radial shift calculation (0x0000000c)*/
  8284. /*! Slice: B_Blue:*/
  8285. /*! Parameter B_Blue for radial blue shift calculation, according to */
  8286. /*(A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/
  8287. /* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/
  8288. #define MRV_CAC_B_BLUE
  8289. #define MRV_CAC_B_BLUE_MASK 0x01FF0000U
  8290. #define MRV_CAC_B_BLUE_SHIFT 16U
  8291. /*! Slice: B_Red:*/
  8292. /*! Parameter B_Red for radial red shift calculation, according to */
  8293. /*(A_Red * r + B_Red * r^2 + C_Red * r^3).*/
  8294. /* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/
  8295. #define MRV_CAC_B_RED
  8296. #define MRV_CAC_B_RED_MASK 0x000001FFU
  8297. #define MRV_CAC_B_RED_SHIFT 0U
  8298. /*! Register: isp_cac_c: Cubical Parameters for radial shift calculation (0x00000010)*/
  8299. /*! Slice: C_Blue:*/
  8300. /*! Parameter C_Blue for radial blue shift calculation, according to */
  8301. /*(A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/
  8302. /* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/
  8303. #define MRV_CAC_C_BLUE
  8304. #define MRV_CAC_C_BLUE_MASK 0x01FF0000U
  8305. #define MRV_CAC_C_BLUE_SHIFT 16U
  8306. /*! Slice: C_Red:*/
  8307. /*! Parameter C_Red for radial red shift calculation, according to */
  8308. /*(A_Red * r + B_Red * r^2 + C_Red * r^3).*/
  8309. /* It is a 9 bit twos complement integer with 4 fractional digits value and value range from -16 up to 15.9375.*/
  8310. #define MRV_CAC_C_RED
  8311. #define MRV_CAC_C_RED_MASK 0x000001FFU
  8312. #define MRV_CAC_C_RED_SHIFT 0U
  8313. /*! Register: isp_cac_x_norm: Normalization parameters for calculation of image coordinate x_d relative to optical center (0x00000014)*/
  8314. /*! Slice: x_ns:*/
  8315. /*! Horizontal normalization shift parameter x_ns (4 bit unsigned integer) in equation */
  8316. /* x_d[7:0] = (((h_count <% 4) %> x_ns) * x_nf) >> 5 */
  8317. #define MRV_CAC_X_NS
  8318. #define MRV_CAC_X_NS_MASK 0x000F0000U
  8319. #define MRV_CAC_X_NS_SHIFT 16U
  8320. /*! Slice: x_nf:*/
  8321. /*! Horizontal scaling or normalization factor x_nf (5 bit unsigned integer) range 0 .. 31 in equation */
  8322. /* x_d[7:0] = (((h_count <% 4) %> x_ns) * x_nf) >> 5 */
  8323. #define MRV_CAC_X_NF
  8324. #define MRV_CAC_X_NF_MASK 0x0000001FU
  8325. #define MRV_CAC_X_NF_SHIFT 0U
  8326. /*! Register: isp_cac_y_norm: Normalization parameters for calculation of image coordinate y_d relative to optical center (0x00000018)*/
  8327. /*! Slice: y_ns:*/
  8328. /*! Vertical normalization shift parameter y_ns (4 bit unsigned integer) in equation */
  8329. /* y_d[7:0] = (((v_count <% 4) %> y_ns) * y_nf) >> 5 */
  8330. #define MRV_CAC_Y_NS
  8331. #define MRV_CAC_Y_NS_MASK 0x000F0000U
  8332. #define MRV_CAC_Y_NS_SHIFT 16U
  8333. /*! Slice: y_nf:*/
  8334. /*! Vertical scaling or normalization factor y_nf (5 bit unsigned integer) range 0 .. 31 in equation */
  8335. /* y_d[7:0] = (((v_count <% 4) %> y_ns) * y_nf) >> 5 */
  8336. #define MRV_CAC_Y_NF
  8337. #define MRV_CAC_Y_NF_MASK 0x0000001FU
  8338. #define MRV_CAC_Y_NF_SHIFT 0U
  8339. /*! Register: isp_exp_ctrl: Exposure control (0x00000000)*/
  8340. /*! Slice: exp_meas_mode:*/
  8341. /*! '1' luminance calculation according to */
  8342. /* Y=(R+G+B) x 0.332 (85/256)*/
  8343. /* '0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B */
  8344. #define MRV_AE_EXP_MEAS_MODE
  8345. #define MRV_AE_EXP_MEAS_MODE_MASK 0x80000000U
  8346. #define MRV_AE_EXP_MEAS_MODE_SHIFT 31U
  8347. /*! Slice: autostop:*/
  8348. /*! '1' stop measuring after a complete frame */
  8349. /* '0' continous measurement */
  8350. #define MRV_AE_AUTOSTOP
  8351. #define MRV_AE_AUTOSTOP_MASK 0x00000002U
  8352. #define MRV_AE_AUTOSTOP_SHIFT 1U
  8353. /*! Slice: exp_start:*/
  8354. /*! '1' start measuring a frame. The exp block will reset this bit and halt after completing one frame, if bit "autostop" is set to '1'.*/
  8355. #define MRV_AE_EXP_START
  8356. #define MRV_AE_EXP_START_MASK 0x00000001U
  8357. #define MRV_AE_EXP_START_SHIFT 0U
  8358. /*! Register: isp_exp_h_offset: Horizontal offset for first block (0x00000004)*/
  8359. /*! Slice: isp_exp_h_offset:*/
  8360. /*! Horizontal offset of first block in pixels.*/
  8361. /* 0 <= value <= 2424 */
  8362. #define MRV_AE_ISP_EXP_H_OFFSET
  8363. #define MRV_AE_ISP_EXP_H_OFFSET_MASK 0x00001FFFU
  8364. #define MRV_AE_ISP_EXP_H_OFFSET_SHIFT 0U
  8365. /*! Register: isp_exp_v_offset: Vertical offset for first block (0x00000008)*/
  8366. /*! Slice: isp_exp_v_offset:*/
  8367. /*! Vertical offset of first block in pixels.*/
  8368. /* 0 <= value <= 1806 */
  8369. #define MRV_AE_ISP_EXP_V_OFFSET
  8370. #define MRV_AE_ISP_EXP_V_OFFSET_MASK 0x00001FFFU
  8371. #define MRV_AE_ISP_EXP_V_OFFSET_SHIFT 0U
  8372. /*! Register: isp_exp_h_size: Horizontal size of one block (0x0000000c)*/
  8373. /*! Slice: isp_exp_h_size:*/
  8374. /*! Horizontal size in pixels of one block.*/
  8375. /* 35 <= value <= 516 */
  8376. #define MRV_AE_ISP_EXP_H_SIZE
  8377. #define MRV_AE_ISP_EXP_H_SIZE_MASK 0x000007FFU
  8378. #define MRV_AE_ISP_EXP_H_SIZE_SHIFT 0U
  8379. /*! Register: isp_exp_v_size: Vertical size of one block (0x00000010)*/
  8380. /*! Slice: isp_exp_v_size:*/
  8381. /*! Vertical size in pixels of one block.*/
  8382. /* 28 <= value <= 390 */
  8383. #define MRV_AE_ISP_EXP_V_SIZE
  8384. #define MRV_AE_ISP_EXP_V_SIZE_MASK 0x000007FEU
  8385. #define MRV_AE_ISP_EXP_V_SIZE_SHIFT 0U
  8386. /*! Register: isp_exp_mean_00: Mean luminance value of block 00 (0x00000014)*/
  8387. /*! Slice: isp_exp_mean_00:*/
  8388. /*! Mean luminance value of block 00 (x,y)*/
  8389. #define MRV_AE_ISP_EXP_MEAN_00
  8390. #define MRV_AE_ISP_EXP_MEAN_00_MASK 0x000000FFU
  8391. #define MRV_AE_ISP_EXP_MEAN_00_SHIFT 0U
  8392. /*! Register: isp_exp_mean_10: Mean luminance value of block 10 (0x00000018)*/
  8393. /*! Slice: isp_exp_mean_10:*/
  8394. /*! Mean luminance value of block 10 (x,y)*/
  8395. #define MRV_AE_ISP_EXP_MEAN_10
  8396. #define MRV_AE_ISP_EXP_MEAN_10_MASK 0x000000FFU
  8397. #define MRV_AE_ISP_EXP_MEAN_10_SHIFT 0U
  8398. /*! Register: isp_exp_mean_20: Mean luminance value of block 20 (0x0000001c)*/
  8399. /*! Slice: isp_exp_mean_20:*/
  8400. /*! Mean luminance value of block 20 (x,y)*/
  8401. #define MRV_AE_ISP_EXP_MEAN_20
  8402. #define MRV_AE_ISP_EXP_MEAN_20_MASK 0x000000FFU
  8403. #define MRV_AE_ISP_EXP_MEAN_20_SHIFT 0U
  8404. /*! Register: isp_exp_mean_30: Mean luminance value of block 30 (0x00000020)*/
  8405. /*! Slice: isp_exp_mean_30:*/
  8406. /*! Mean luminance value of block 30 (x,y)*/
  8407. #define MRV_AE_ISP_EXP_MEAN_30
  8408. #define MRV_AE_ISP_EXP_MEAN_30_MASK 0x000000FFU
  8409. #define MRV_AE_ISP_EXP_MEAN_30_SHIFT 0U
  8410. /*! Register: isp_exp_mean_40: Mean luminance value of block 40 (0x00000024)*/
  8411. /*! Slice: isp_exp_mean_40:*/
  8412. /*! Mean luminance value of block 40 (x,y)*/
  8413. #define MRV_AE_ISP_EXP_MEAN_40
  8414. #define MRV_AE_ISP_EXP_MEAN_40_MASK 0x000000FFU
  8415. #define MRV_AE_ISP_EXP_MEAN_40_SHIFT 0U
  8416. /*! Register: isp_exp_mean_01: Mean luminance value of block 01 (0x00000028)*/
  8417. /*! Slice: isp_exp_mean_01:*/
  8418. /*! Mean luminance value of block 01 (x,y)*/
  8419. #define MRV_AE_ISP_EXP_MEAN_01
  8420. #define MRV_AE_ISP_EXP_MEAN_01_MASK 0x000000FFU
  8421. #define MRV_AE_ISP_EXP_MEAN_01_SHIFT 0U
  8422. /*! Register: isp_exp_mean_11: Mean luminance value of block 11 (0x0000002c)*/
  8423. /*! Slice: isp_exp_mean_11:*/
  8424. /*! Mean luminance value of block 11 (x,y)*/
  8425. #define MRV_AE_ISP_EXP_MEAN_11
  8426. #define MRV_AE_ISP_EXP_MEAN_11_MASK 0x000000FFU
  8427. #define MRV_AE_ISP_EXP_MEAN_11_SHIFT 0U
  8428. /*! Register: isp_exp_mean_21: Mean luminance value of block 21 (0x00000030)*/
  8429. /*! Slice: isp_exp_mean_21:*/
  8430. /*! Mean luminance value of block 21 (x,y)*/
  8431. #define MRV_AE_ISP_EXP_MEAN_21
  8432. #define MRV_AE_ISP_EXP_MEAN_21_MASK 0x000000FFU
  8433. #define MRV_AE_ISP_EXP_MEAN_21_SHIFT 0U
  8434. /*! Register: isp_exp_mean_31: Mean luminance value of block 31 (0x00000034)*/
  8435. /*! Slice: isp_exp_mean_31:*/
  8436. /*! Mean luminance value of block 31 (x,y)*/
  8437. #define MRV_AE_ISP_EXP_MEAN_31
  8438. #define MRV_AE_ISP_EXP_MEAN_31_MASK 0x000000FFU
  8439. #define MRV_AE_ISP_EXP_MEAN_31_SHIFT 0U
  8440. /*! Register: isp_exp_mean_41: Mean luminance value of block 41 (0x00000038)*/
  8441. /*! Slice: isp_exp_mean_41:*/
  8442. /*! Mean luminance value of block 41 (x,y)*/
  8443. #define MRV_AE_ISP_EXP_MEAN_41
  8444. #define MRV_AE_ISP_EXP_MEAN_41_MASK 0x000000FFU
  8445. #define MRV_AE_ISP_EXP_MEAN_41_SHIFT 0U
  8446. /*! Register: isp_exp_mean_02: Mean luminance value of block 02 (0x0000003c)*/
  8447. /*! Slice: isp_exp_mean_02:*/
  8448. /*! Mean luminance value of block 02 (x,y)*/
  8449. #define MRV_AE_ISP_EXP_MEAN_02
  8450. #define MRV_AE_ISP_EXP_MEAN_02_MASK 0x000000FFU
  8451. #define MRV_AE_ISP_EXP_MEAN_02_SHIFT 0U
  8452. /*! Register: isp_exp_mean_12: Mean luminance value of block 12 (0x00000040)*/
  8453. /*! Slice: isp_exp_mean_12:*/
  8454. /*! Mean luminance value of block 12 (x,y)*/
  8455. #define MRV_AE_ISP_EXP_MEAN_12
  8456. #define MRV_AE_ISP_EXP_MEAN_12_MASK 0x000000FFU
  8457. #define MRV_AE_ISP_EXP_MEAN_12_SHIFT 0U
  8458. /*! Register: isp_exp_mean_22: Mean luminance value of block 22 (0x00000044)*/
  8459. /*! Slice: isp_exp_mean_22:*/
  8460. /*! Mean luminance value of block 22 (x,y)*/
  8461. #define MRV_AE_ISP_EXP_MEAN_22
  8462. #define MRV_AE_ISP_EXP_MEAN_22_MASK 0x000000FFU
  8463. #define MRV_AE_ISP_EXP_MEAN_22_SHIFT 0U
  8464. /*! Register: isp_exp_mean_32: Mean luminance value of block 32 (0x00000048)*/
  8465. /*! Slice: isp_exp_mean_32:*/
  8466. /*! Mean luminance value of block 32 (x,y)*/
  8467. #define MRV_AE_ISP_EXP_MEAN_32
  8468. #define MRV_AE_ISP_EXP_MEAN_32_MASK 0x000000FFU
  8469. #define MRV_AE_ISP_EXP_MEAN_32_SHIFT 0U
  8470. /*! Register: isp_exp_mean_42: Mean luminance value of block 42 (0x0000004c)*/
  8471. /*! Slice: isp_exp_mean_42:*/
  8472. /*! Mean luminance value of block 42 (x,y)*/
  8473. #define MRV_AE_ISP_EXP_MEAN_42
  8474. #define MRV_AE_ISP_EXP_MEAN_42_MASK 0x000000FFU
  8475. #define MRV_AE_ISP_EXP_MEAN_42_SHIFT 0U
  8476. /*! Register: isp_exp_mean_03: Mean luminance value of block 03 (0x00000050)*/
  8477. /*! Slice: isp_exp_mean_03:*/
  8478. /*! Mean luminance value of block 03 (x,y)*/
  8479. #define MRV_AE_ISP_EXP_MEAN_03
  8480. #define MRV_AE_ISP_EXP_MEAN_03_MASK 0x000000FFU
  8481. #define MRV_AE_ISP_EXP_MEAN_03_SHIFT 0U
  8482. /*! Register: isp_exp_mean_13: Mean luminance value of block 13 (0x00000054)*/
  8483. /*! Slice: isp_exp_mean_13:*/
  8484. /*! Mean luminance value of block 13 (x,y)*/
  8485. #define MRV_AE_ISP_EXP_MEAN_13
  8486. #define MRV_AE_ISP_EXP_MEAN_13_MASK 0x000000FFU
  8487. #define MRV_AE_ISP_EXP_MEAN_13_SHIFT 0U
  8488. /*! Register: isp_exp_mean_23: Mean luminance value of block 23 (0x00000058)*/
  8489. /*! Slice: isp_exp_mean_23:*/
  8490. /*! Mean luminance value of block 23 (x,y)*/
  8491. #define MRV_AE_ISP_EXP_MEAN_23
  8492. #define MRV_AE_ISP_EXP_MEAN_23_MASK 0x000000FFU
  8493. #define MRV_AE_ISP_EXP_MEAN_23_SHIFT 0U
  8494. /*! Register: isp_exp_mean_33: Mean luminance value of block 33 (0x0000005c)*/
  8495. /*! Slice: isp_exp_mean_33:*/
  8496. /*! Mean luminance value of block 33 (x,y)*/
  8497. #define MRV_AE_ISP_EXP_MEAN_33
  8498. #define MRV_AE_ISP_EXP_MEAN_33_MASK 0x000000FFU
  8499. #define MRV_AE_ISP_EXP_MEAN_33_SHIFT 0U
  8500. /*! Register: isp_exp_mean_43: Mean luminance value of block 43 (0x00000060)*/
  8501. /*! Slice: isp_exp_mean_43:*/
  8502. /*! Mean luminance value of block 43 (x,y)*/
  8503. #define MRV_AE_ISP_EXP_MEAN_43
  8504. #define MRV_AE_ISP_EXP_MEAN_43_MASK 0x000000FFU
  8505. #define MRV_AE_ISP_EXP_MEAN_43_SHIFT 0U
  8506. /*! Register: isp_exp_mean_04: Mean luminance value of block 04 (0x00000064)*/
  8507. /*! Slice: isp_exp_mean_04:*/
  8508. /*! Mean luminance value of block 04 (x,y)*/
  8509. #define MRV_AE_ISP_EXP_MEAN_04
  8510. #define MRV_AE_ISP_EXP_MEAN_04_MASK 0x000000FFU
  8511. #define MRV_AE_ISP_EXP_MEAN_04_SHIFT 0U
  8512. /*! Register: isp_exp_mean_14: Mean luminance value of block 14 (0x00000068)*/
  8513. /*! Slice: isp_exp_mean_14:*/
  8514. /*! Mean luminance value of block 14 (x,y)*/
  8515. #define MRV_AE_ISP_EXP_MEAN_14
  8516. #define MRV_AE_ISP_EXP_MEAN_14_MASK 0x000000FFU
  8517. #define MRV_AE_ISP_EXP_MEAN_14_SHIFT 0U
  8518. /*! Register: isp_exp_mean_24: Mean luminance value of block 24 (0x0000006c)*/
  8519. /*! Slice: isp_exp_mean_24:*/
  8520. /*! Mean luminance value of block 24 (x,y)*/
  8521. #define MRV_AE_ISP_EXP_MEAN_24
  8522. #define MRV_AE_ISP_EXP_MEAN_24_MASK 0x000000FFU
  8523. #define MRV_AE_ISP_EXP_MEAN_24_SHIFT 0U
  8524. /*! Register: isp_exp_mean_34: Mean luminance value of block 34 (0x00000070)*/
  8525. /*! Slice: isp_exp_mean_34:*/
  8526. /*! Mean luminance value of block 34 (x,y)*/
  8527. #define MRV_AE_ISP_EXP_MEAN_34
  8528. #define MRV_AE_ISP_EXP_MEAN_34_MASK 0x000000FFU
  8529. #define MRV_AE_ISP_EXP_MEAN_34_SHIFT 0U
  8530. /*! Register: isp_exp_mean_44: Mean luminance value of block 44 (0x00000074)*/
  8531. /*! Slice: isp_exp_mean_44:*/
  8532. /*! Mean luminance value of block 44 (x,y)*/
  8533. #define MRV_AE_ISP_EXP_MEAN_44
  8534. #define MRV_AE_ISP_EXP_MEAN_44_MASK 0x000000FFU
  8535. #define MRV_AE_ISP_EXP_MEAN_44_SHIFT 0U
  8536. /*! Register: isp_expv2_ctrl: (0x00002680)*/
  8537. /*! Slice: isp_expv2_ctrl:*/
  8538. #define MRV_AE_ISP_EXPV2_INPUT_SELECT
  8539. #define MRV_AE_ISP_EXPV2_INPUT_SELECT_MASK 0x0000000CU
  8540. #define MRV_AE_ISP_EXPV2_INPUT_SELECT_SHIFT 2U
  8541. #define MRV_AE_ISP_EXPV2_AUTO_STOP
  8542. #define MRV_AE_ISP_EXPV2_AUTO_STOP_MASK 0x00000002U
  8543. #define MRV_AE_ISP_EXPV2_AUTO_STOP_SHIFT 1U
  8544. #define MRV_AE_ISP_EXPV2_ENABLE
  8545. #define MRV_AE_ISP_EXPV2_ENABLE_MASK 0x00000001U
  8546. #define MRV_AE_ISP_EXPV2_ENABLE_SHIFT 0U
  8547. /*! Register: isp_expv2_offset: (0x00002684)*/
  8548. /*! Slice: isp_expv2_offset:*/
  8549. #define MRV_AE_ISP_EXPV2_OFFSET_V
  8550. #define MRV_AE_ISP_EXPV2_OFFSET_V_MASK 0x1FFF0000U
  8551. #define MRV_AE_ISP_EXPV2_OFFSET_V_SHIFT 16U
  8552. #define MRV_AE_ISP_EXPV2_OFFSET_H
  8553. #define MRV_AE_ISP_EXPV2_OFFSET_H_MASK 0x00001FFFU
  8554. #define MRV_AE_ISP_EXPV2_OFFSET_H_SHIFT 0
  8555. /*! Register: isp_expv2_size: (0x00002688)*/
  8556. /*! Slice: isp_expv2_size:*/
  8557. #define MRV_AE_ISP_EXPV2_SIZE_V
  8558. #define MRV_AE_ISP_EXPV2_SIZE_V_MASK 0x01FF0000U
  8559. #define MRV_AE_ISP_EXPV2_SIZE_V_SHIFT 16U
  8560. #define MRV_AE_ISP_EXPV2_SIZE_H
  8561. #define MRV_AE_ISP_EXPV2_SIZE_H_MASK 0x000001FFU
  8562. #define MRV_AE_ISP_EXPV2_SIZE_H_SHIFT 0U
  8563. /*! Register: isp_expv2_size_invert: (0x0000268c)*/
  8564. /*! Slice: isp_expv2_size_invert:*/
  8565. #define MRV_AE_ISP_EXPV2_SIZE_INVERT_V
  8566. #define MRV_AE_ISP_EXPV2_SIZE_INVERT_V_MASK 0xFFFF0000U
  8567. #define MRV_AE_ISP_EXPV2_SIZE_INVERT_V_SHIFT 16U
  8568. #define MRV_AE_ISP_EXPV2_SIZE_INVERT_H
  8569. #define MRV_AE_ISP_EXPV2_SIZE_INVERT_H_MASK 0x0000FFFFU
  8570. #define MRV_AE_ISP_EXPV2_SIZE_INVERT_H_SHIFT 0U
  8571. /*! Register: isp_expv2_pixel_weight: (0x00002690)*/
  8572. /*! Slice: isp_expv2_pixel_weight:*/
  8573. #define MRV_AE_ISP_EXPV2_PIX_WEIGHT_R
  8574. #define MRV_AE_ISP_EXPV2_PIX_WEIGHT_R_MASK 0x3F000000U
  8575. #define MRV_AE_ISP_EXPV2_PIX_WEIGHT_R_SHIFT 24U
  8576. #define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR
  8577. #define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR_MASK 0x003F0000U
  8578. #define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR_SHIFT 16
  8579. #define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB
  8580. #define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB_MASK 0x00003F00U
  8581. #define MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB_SHIFT 8U
  8582. #define MRV_AE_ISP_EXPV2_PIX_WEIGHT_B
  8583. #define MRV_AE_ISP_EXPV2_PIX_WEIGHT_B_MASK 0x0000003FU
  8584. #define MRV_AE_ISP_EXPV2_PIX_WEIGHT_B_SHIFT 0U
  8585. /*! Register: isp_bls_ctrl: global control register (0x00000000)*/
  8586. /*! Slice: WINDOW_ENABLE:*/
  8587. /*! 0: no measuring is performed */
  8588. /* 1: only window 1 is measured */
  8589. /* 2: only window 2 is measured */
  8590. /* 3: both windows are measured */
  8591. #define MRV_BLS_WINDOW_ENABLE
  8592. #define MRV_BLS_WINDOW_ENABLE_MASK 0x0000000CU
  8593. #define MRV_BLS_WINDOW_ENABLE_SHIFT 2U
  8594. /*! Slice: BLS_MODE:*/
  8595. /*! 1: subtract measured values */
  8596. /* 0: subtract fixed values */
  8597. #define MRV_BLS_BLS_MODE
  8598. #define MRV_BLS_BLS_MODE_MASK 0x00000002U
  8599. #define MRV_BLS_BLS_MODE_SHIFT 1U
  8600. /*! Slice: BLS_ENABLE:*/
  8601. /*! 1: black level subtraction is enabled */
  8602. /* 0: bypass the black level processing */
  8603. #define MRV_BLS_BLS_ENABLE
  8604. #define MRV_BLS_BLS_ENABLE_MASK 0x00000001U
  8605. #define MRV_BLS_BLS_ENABLE_SHIFT 0U
  8606. /*! Register: isp_bls_samples: samples register (0x00000004)*/
  8607. /*! Slice: BLS_SAMPLES:*/
  8608. /*! This number to the power of two gives the number of measure samples for each Bayer position. Range 0x00: 2^0=1 to 0x12: 2^18=262144. This number is also the divider for the accumulator for each Bayer position.*/
  8609. /* The accumulation will be stopped, if the number of measured pixels for the current Bayer position is equal to the number of samples.*/
  8610. /* The measure windows must be positioned that way that the number of included pixels of each Bayer position included by both windows is equal or greater than the number of measure samples calculated by 2^BLS_SAMPLES !*/
  8611. /* NOTE: The number of pixels of one Bayer position is 1/4 of the number of all Pixels included by the measure windows.*/
  8612. #define MRV_BLS_BLS_SAMPLES
  8613. #define MRV_BLS_BLS_SAMPLES_MASK 0x0000001FU
  8614. #define MRV_BLS_BLS_SAMPLES_SHIFT 0U
  8615. /*! Register: isp_bls_h1_start: window 1 horizontal start (0x00000008)*/
  8616. /*! Slice: BLS_H1_START:*/
  8617. /*! Black pixel window 1 horizontal start position */
  8618. #define MRV_BLS_BLS_H1_START
  8619. #define MRV_BLS_BLS_H1_START_MASK 0x00003FFFU
  8620. #define MRV_BLS_BLS_H1_START_SHIFT 0U
  8621. /*! Register: isp_bls_h1_stop: window 1 horizontal stop (0x0000000c)*/
  8622. /*! Slice: BLS_H1_STOP:*/
  8623. /*! Black pixel window 1 horizontal stop position */
  8624. #define MRV_BLS_BLS_H1_STOP
  8625. #define MRV_BLS_BLS_H1_STOP_MASK 0x00003FFFU
  8626. #define MRV_BLS_BLS_H1_STOP_SHIFT 0U
  8627. /*! Register: isp_bls_v1_start: window 1 vertical start (0x00000010)*/
  8628. /*! Slice: BLS_V1_START:*/
  8629. /*! Black pixel window 1 vertical start position */
  8630. #define MRV_BLS_BLS_V1_START
  8631. #define MRV_BLS_BLS_V1_START_MASK 0x00003FFFU
  8632. #define MRV_BLS_BLS_V1_START_SHIFT 0U
  8633. /*! Register: isp_bls_v1_stop: window 1 vertical stop (0x00000014)*/
  8634. /*! Slice: BLS_V1_STOP:*/
  8635. /*! Black pixel window 1 vertical stop position */
  8636. #define MRV_BLS_BLS_V1_STOP
  8637. #define MRV_BLS_BLS_V1_STOP_MASK 0x00003FFFU
  8638. #define MRV_BLS_BLS_V1_STOP_SHIFT 0U
  8639. /*! Register: isp_bls_h2_start: window 2 horizontal start (0x00000018)*/
  8640. /*! Slice: BLS_H2_START:*/
  8641. /*! Black pixel window 2 horizontal start position */
  8642. #define MRV_BLS_BLS_H2_START
  8643. #define MRV_BLS_BLS_H2_START_MASK 0x00003FFFU
  8644. #define MRV_BLS_BLS_H2_START_SHIFT 0U
  8645. /*! Register: isp_bls_h2_stop: window 2 horizontal stop (0x0000001c)*/
  8646. /*! Slice: BLS_H2_STOP:*/
  8647. /*! Black pixel window 2 horizontal stop position */
  8648. #define MRV_BLS_BLS_H2_STOP
  8649. #define MRV_BLS_BLS_H2_STOP_MASK 0x00003FFFU
  8650. #define MRV_BLS_BLS_H2_STOP_SHIFT 0U
  8651. /*! Register: isp_bls_v2_start: window 2 vertical start (0x00000020)*/
  8652. /*! Slice: BLS_V2_START:*/
  8653. /*! Black pixel window 2 vertical start position */
  8654. #define MRV_BLS_BLS_V2_START
  8655. #define MRV_BLS_BLS_V2_START_MASK 0x00003FFFU
  8656. #define MRV_BLS_BLS_V2_START_SHIFT 0U
  8657. /*! Register: isp_bls_v2_stop: window 2 vertical stop (0x00000024)*/
  8658. /*! Slice: BLS_V2_STOP:*/
  8659. /*! Black pixel window 2 vertical stop position */
  8660. #define MRV_BLS_BLS_V2_STOP
  8661. #define MRV_BLS_BLS_V2_STOP_MASK 0x00003FFFU
  8662. #define MRV_BLS_BLS_V2_STOP_SHIFT 0U
  8663. /*! Register: isp_bls_a_fixed: fixed black level A (0x00000028)*/
  8664. /*! Slice: BLS_A_FIXED:*/
  8665. /*! Fixed black level for A pixels – signed */
  8666. /* two's complement, value range from -4096 to +4095,*/
  8667. /* a positive value will be subtracted from the pixel values */
  8668. #define MRV_BLS_BLS_A_FIXED
  8669. #define MRV_BLS_BLS_A_FIXED_MASK 0x00001FFFU
  8670. #define MRV_BLS_BLS_A_FIXED_SHIFT 0U
  8671. /*! Register: isp_bls_b_fixed: fixed black level B (0x0000002c)*/
  8672. /*! Slice: BLS_B_FIXED:*/
  8673. /*! Fixed black level for B pixels – signed */
  8674. /* two's complement, value range from -4096 to +4095 */
  8675. #define MRV_BLS_BLS_B_FIXED
  8676. #define MRV_BLS_BLS_B_FIXED_MASK 0x00001FFFU
  8677. #define MRV_BLS_BLS_B_FIXED_SHIFT 0U
  8678. /*! Register: isp_bls_c_fixed: fixed black level C (0x00000030)*/
  8679. /*! Slice: BLS_C_FIXED:*/
  8680. /*! Fixed black level for C pixels – signed */
  8681. /* two's complement, value range from -4096 to +4095 */
  8682. #define MRV_BLS_BLS_C_FIXED
  8683. #define MRV_BLS_BLS_C_FIXED_MASK 0x00001FFFU
  8684. #define MRV_BLS_BLS_C_FIXED_SHIFT 0U
  8685. /*! Register: isp_bls_d_fixed: fixed black level D (0x00000034)*/
  8686. /*! Slice: BLS_D_FIXED:*/
  8687. /*! Fixed black level for D pixels - signed */
  8688. /* two's complement, value range from -4096 to +4095 */
  8689. #define MRV_BLS_BLS_D_FIXED
  8690. #define MRV_BLS_BLS_D_FIXED_MASK 0x00001FFFU
  8691. #define MRV_BLS_BLS_D_FIXED_SHIFT 0U
  8692. /*! Register: isp_bls_a_measured: measured black level A (0x00000038)*/
  8693. /*! Slice: BLS_A_MEASURED:*/
  8694. /*! Measured black level for A pixels */
  8695. #define MRV_BLS_BLS_A_MEASURED
  8696. #define MRV_BLS_BLS_A_MEASURED_MASK 0x00000FFFU
  8697. #define MRV_BLS_BLS_A_MEASURED_SHIFT 0U
  8698. /*! Register: isp_bls_b_measured: measured black level B (0x0000003c)*/
  8699. /*! Slice: BLS_B_MEASURED:*/
  8700. /*! Measured black level for B pixels */
  8701. #define MRV_BLS_BLS_B_MEASURED
  8702. #define MRV_BLS_BLS_B_MEASURED_MASK 0x00000FFFU
  8703. #define MRV_BLS_BLS_B_MEASURED_SHIFT 0U
  8704. /*! Register: isp_bls_c_measured: measured black level C (0x00000040)*/
  8705. /*! Slice: BLS_C_MEASURED:*/
  8706. /*! Measured black level for C pixels */
  8707. #define MRV_BLS_BLS_C_MEASURED
  8708. #define MRV_BLS_BLS_C_MEASURED_MASK 0x00000FFFU
  8709. #define MRV_BLS_BLS_C_MEASURED_SHIFT 0U
  8710. /*! Register: isp_bls_d_measured: measured black level D (0x00000044)*/
  8711. /*! Slice: BLS_D_MEASURED:*/
  8712. /*! Measured black level for D pixels */
  8713. #define MRV_BLS_BLS_D_MEASURED
  8714. #define MRV_BLS_BLS_D_MEASURED_MASK 0x00000FFFU
  8715. #define MRV_BLS_BLS_D_MEASURED_SHIFT 0U
  8716. /*! Register: isp_dpf_mode: Mode control for Denoising Pre-Filter block (0x00000000)*/
  8717. /*! Slice: USE_NF_GAIN:*/
  8718. /*! 1: DPF_NF_GAINs will be used.*/
  8719. /* 0: DPF_NF_GAINs will not be used. *Default**/
  8720. #define MRV_DPF_USE_NF_GAIN
  8721. #define MRV_DPF_USE_NF_GAIN_MASK 0x00000200U
  8722. #define MRV_DPF_USE_NF_GAIN_SHIFT 9U
  8723. /*! Slice: LSC_GAIN_COMP:*/
  8724. /*! 1: LSC gain will be processed */
  8725. /* 0: LSC gain will not be processed. Use LSC gain factor of 1. *Default**/
  8726. #define MRV_DPF_LSC_GAIN_COMP
  8727. #define MRV_DPF_LSC_GAIN_COMP_MASK 0x00000100U
  8728. #define MRV_DPF_LSC_GAIN_COMP_SHIFT 8U
  8729. /*! Slice: AWB_GAIN_COMP:*/
  8730. /*! Only relevant when use_nf_gain == 0 && ISP_CTRL::ISP_AWB_ENABLE ==1 */
  8731. /* 1: ISP_AWB gains will be processed */
  8732. /* 0: ISP_AWB gains will not be processed. Use AWB gain factor of 1. *Default**/
  8733. #define MRV_DPF_AWB_GAIN_COMP
  8734. #define MRV_DPF_AWB_GAIN_COMP_MASK 0x00000080U
  8735. #define MRV_DPF_AWB_GAIN_COMP_SHIFT 7U
  8736. /*! Slice: NLL_SEGMENTATION:*/
  8737. /*! 1: optimized logarithmic like segmentation for Noise Level Lookup (NLL)*/
  8738. /* 0: equidistant segmentation for NLL *Default**/
  8739. #define MRV_DPF_NLL_SEGMENTATION
  8740. #define MRV_DPF_NLL_SEGMENTATION_MASK 0x00000040U
  8741. #define MRV_DPF_NLL_SEGMENTATION_SHIFT 6U
  8742. /*! Slice: RB_FILTER_SIZE:*/
  8743. /*! 1: Red and Blue filter kernel size of 9x9 (5x5 active) pixels */
  8744. /* 0: Wide Red and Blue filter kernel size of 13x9 (7x5 active) pixels *Default**/
  8745. #define MRV_DPF_RB_FILTER_SIZE
  8746. #define MRV_DPF_RB_FILTER_SIZE_MASK 0x00000020U
  8747. #define MRV_DPF_RB_FILTER_SIZE_SHIFT 5U
  8748. /*! Slice: R_FILTER_OFF:*/
  8749. /*! 1: disable filter processing for red pixels (R)*/
  8750. /* 0: filter R pixels *Default**/
  8751. #define MRV_DPF_R_FILTER_OFF
  8752. #define MRV_DPF_R_FILTER_OFF_MASK 0x00000010U
  8753. #define MRV_DPF_R_FILTER_OFF_SHIFT 4U
  8754. /*! Slice: GR_FILTER_OFF:*/
  8755. /*! 1: disable filter processing for green pixels in green/red lines (GR)*/
  8756. /* 0: filter GR pixels *Default**/
  8757. #define MRV_DPF_GR_FILTER_OFF
  8758. #define MRV_DPF_GR_FILTER_OFF_MASK 0x00000008U
  8759. #define MRV_DPF_GR_FILTER_OFF_SHIFT 3U
  8760. /*! Slice: GB_FILTER_OFF:*/
  8761. /*! 1: disable filter processing for green pixels in green/blue lines (GB)*/
  8762. /* 0: filter GB pixels *Default**/
  8763. #define MRV_DPF_GB_FILTER_OFF
  8764. #define MRV_DPF_GB_FILTER_OFF_MASK 0x00000004U
  8765. #define MRV_DPF_GB_FILTER_OFF_SHIFT 2U
  8766. /*! Slice: B_FILTER_OFF:*/
  8767. /*! 1: disable filter processing for blue pixels (B)*/
  8768. /* 0: filter B pixels *Default**/
  8769. #define MRV_DPF_B_FILTER_OFF
  8770. #define MRV_DPF_B_FILTER_OFF_MASK 0x00000002U
  8771. #define MRV_DPF_B_FILTER_OFF_SHIFT 1U
  8772. /*! Slice: DPF_ENABLE:*/
  8773. /*! 1: enable dpf */
  8774. /* 0: bypass dpf *Default**/
  8775. #define MRV_DPF_DPF_ENABLE
  8776. #define MRV_DPF_DPF_ENABLE_MASK 0x00000001U
  8777. #define MRV_DPF_DPF_ENABLE_SHIFT 0U
  8778. /*! Register: isp_dpf_strength_r: filter strength of the RED filter (0x00000004)*/
  8779. /*! Slice: INV_WEIGHT_R:*/
  8780. /*! Filter strength of the filter is determined by weight. Default is a weight of 1. A higher weight increases the filter strength. In this register the unsigned 8 bit value 64/weight is stored.*/
  8781. /**/
  8782. /* The following values show examples:*/
  8783. /* weight=0.251 -> 255, weight=0.5 -> 128,*/
  8784. /* weight=1 -> 64 *default**/
  8785. /* weight=1.25 -> 51, weight=1.5 -> 42,*/
  8786. /* weight=1.75 -> 37, weight=2 -> 32 */
  8787. #define MRV_DPF_INV_WEIGHT_R
  8788. #define MRV_DPF_INV_WEIGHT_R_MASK 0x000000FFU
  8789. #define MRV_DPF_INV_WEIGHT_R_SHIFT 0U
  8790. /*! Register: isp_dpf_strength_g: filter strength of the GREEN filter (0x00000008)*/
  8791. /*! Slice: INV_WEIGHT_G:*/
  8792. /*! Filter strength of the filter is determined by weight. Default is a weight of 1. A higher weight increases the filter strength. In this register the unsigned 8 bit value 64/weight is stored.*/
  8793. /**/
  8794. /* The following values show examples:*/
  8795. /* weight=0.251 -> 255, weight=0.5 -> 128,*/
  8796. /* weight=1 -> 64 *default**/
  8797. /* weight=1.25 -> 51, weight=1.5 -> 42,*/
  8798. /* weight=1.75 -> 37, weight=2 -> 32 */
  8799. #define MRV_DPF_INV_WEIGHT_G
  8800. #define MRV_DPF_INV_WEIGHT_G_MASK 0x000000FFU
  8801. #define MRV_DPF_INV_WEIGHT_G_SHIFT 0U
  8802. /*! Register: isp_dpf_strength_b: filter strength of the BLUE filter (0x0000000c)*/
  8803. /*! Slice: INV_WEIGHT_B:*/
  8804. /*! Filter strength of the filter is determined by weight. Default is a weight of 1. A higher weight increases the filter strength. In this register the unsigned 8 bit value 64/weight is stored.*/
  8805. /**/
  8806. /* The following values show examples:*/
  8807. /* weight=0.251 -> 255, weight=0.5 -> 128,*/
  8808. /* weight=1 -> 64 *default**/
  8809. /* weight=1.25 -> 51, weight=1.5 -> 42,*/
  8810. /* weight=1.75 -> 37, weight=2 -> 32 */
  8811. #define MRV_DPF_INV_WEIGHT_B
  8812. #define MRV_DPF_INV_WEIGHT_B_MASK 0x000000FFU
  8813. #define MRV_DPF_INV_WEIGHT_B_SHIFT 0U
  8814. /*! Register: isp_dpf_s_weight_g_1_4: Spatial Weights green channel 1 2 3 4 (0x00000010)*/
  8815. /*! Slice: S_WEIGHT_G4:*/
  8816. /*! Filter Coefficient green channel S_WEIGHT_G4 */
  8817. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8818. /* Default value is 16/16 (*Default*)*/
  8819. #define MRV_DPF_S_WEIGHT_G4
  8820. #define MRV_DPF_S_WEIGHT_G4_MASK 0x1F000000U
  8821. #define MRV_DPF_S_WEIGHT_G4_SHIFT 24U
  8822. /*! Slice: S_WEIGHT_G3:*/
  8823. /*! Filter Coefficient green channel S_WEIGHT_G3 */
  8824. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8825. /* Default value is 16/16 (*Default*)*/
  8826. #define MRV_DPF_S_WEIGHT_G3
  8827. #define MRV_DPF_S_WEIGHT_G3_MASK 0x001F0000U
  8828. #define MRV_DPF_S_WEIGHT_G3_SHIFT 16U
  8829. /*! Slice: S_WEIGHT_G2:*/
  8830. /*! Filter Coefficient green channel S_WEIGHT_G2 */
  8831. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8832. /* Default value is 16/16 (*Default*)*/
  8833. #define MRV_DPF_S_WEIGHT_G2
  8834. #define MRV_DPF_S_WEIGHT_G2_MASK 0x00001F00U
  8835. #define MRV_DPF_S_WEIGHT_G2_SHIFT 8U
  8836. /*! Slice: S_WEIGHT_G1:*/
  8837. /*! Filter Coefficient green channel S_WEIGHT_G1 */
  8838. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8839. /* Default value is 16/16 (*Default*)*/
  8840. #define MRV_DPF_S_WEIGHT_G1
  8841. #define MRV_DPF_S_WEIGHT_G1_MASK 0x0000001FU
  8842. #define MRV_DPF_S_WEIGHT_G1_SHIFT 0U
  8843. /*! Register: isp_dpf_s_weight_g_5_6: Spatial Weights green channel 5 6 (0x00000014)*/
  8844. /*! Slice: S_WEIGHT_G6:*/
  8845. /*! Filter Coefficient green channel S_WEIGHT_G6 */
  8846. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8847. /* Default value is 16/16 (*Default*)*/
  8848. #define MRV_DPF_S_WEIGHT_G6
  8849. #define MRV_DPF_S_WEIGHT_G6_MASK 0x00001F00U
  8850. #define MRV_DPF_S_WEIGHT_G6_SHIFT 8U
  8851. /*! Slice: S_WEIGHT_G5:*/
  8852. /*! Filter Coefficient green channel S_WEIGHT_G5 */
  8853. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8854. /* Default value is 16/16 (*Default*)*/
  8855. #define MRV_DPF_S_WEIGHT_G5
  8856. #define MRV_DPF_S_WEIGHT_G5_MASK 0x0000001FU
  8857. #define MRV_DPF_S_WEIGHT_G5_SHIFT 0U
  8858. /*! Register: isp_dpf_s_weight_rb_1_4: Spatial Weights red/blue channels 1 2 3 4 (0x00000018)*/
  8859. /*! Slice: S_WEIGHT_RB4:*/
  8860. /*! Filter Coefficient red/blue channels S_WEIGHT_RB4 */
  8861. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8862. /* Default value is 16/16 (*Default*)*/
  8863. #define MRV_DPF_S_WEIGHT_RB4
  8864. #define MRV_DPF_S_WEIGHT_RB4_MASK 0x1F000000U
  8865. #define MRV_DPF_S_WEIGHT_RB4_SHIFT 24U
  8866. /*! Slice: S_WEIGHT_RB3:*/
  8867. /*! Filter Coefficient red/blue channels S_WEIGHT_RB3 */
  8868. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8869. /* Default value is 16/16 (*Default*)*/
  8870. #define MRV_DPF_S_WEIGHT_RB3
  8871. #define MRV_DPF_S_WEIGHT_RB3_MASK 0x001F0000U
  8872. #define MRV_DPF_S_WEIGHT_RB3_SHIFT 16U
  8873. /*! Slice: S_WEIGHT_RB2:*/
  8874. /*! Filter Coefficient red/blue channels S_WEIGHT_RB2 */
  8875. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8876. /* Default value is 16/16 (*Default*)*/
  8877. #define MRV_DPF_S_WEIGHT_RB2
  8878. #define MRV_DPF_S_WEIGHT_RB2_MASK 0x00001F00U
  8879. #define MRV_DPF_S_WEIGHT_RB2_SHIFT 8U
  8880. /*! Slice: S_WEIGHT_RB1:*/
  8881. /*! Filter Coefficient red/blue channels S_WEIGHT_RB1 */
  8882. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8883. /* Default value is 16/16 (*Default*)*/
  8884. #define MRV_DPF_S_WEIGHT_RB1
  8885. #define MRV_DPF_S_WEIGHT_RB1_MASK 0x0000001FU
  8886. #define MRV_DPF_S_WEIGHT_RB1_SHIFT 0U
  8887. /*! Register: isp_dpf_s_weight_rb_5_6: Spatial Weights red/blue channels 5 6 (0x0000001c)*/
  8888. /*! Slice: S_WEIGHT_RB6:*/
  8889. /*! Filter Coefficient red/blue channels S_WEIGHT_RB6 */
  8890. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8891. /* Default value is 16/16 (*Default*)*/
  8892. #define MRV_DPF_S_WEIGHT_RB6
  8893. #define MRV_DPF_S_WEIGHT_RB6_MASK 0x00001F00U
  8894. #define MRV_DPF_S_WEIGHT_RB6_SHIFT 8U
  8895. /*! Slice: S_WEIGHT_RB5:*/
  8896. /*! Filter Coefficient red/blue channels S_WEIGHT_RB5 */
  8897. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8898. /* Default value is 16/16 (*Default*)*/
  8899. #define MRV_DPF_S_WEIGHT_RB5
  8900. #define MRV_DPF_S_WEIGHT_RB5_MASK 0x0000001FU
  8901. #define MRV_DPF_S_WEIGHT_RB5_SHIFT 0U
  8902. /*! Register array: isp_dpf_nll_coeff: Noise Level Lookup Coefficient (0x0040 + n*0x4 (n=0..16))*/
  8903. /*! Slice: nll_coeff_n:*/
  8904. /* Noise Level Lookup Table Coefficient nll_coeff_n */
  8905. /* 10 bit unsigned, value range 1/1024 to 1023/1024 (*Default*)*/
  8906. #define MRV_DPF_NLL_COEFF_N
  8907. #define MRV_DPF_NLL_COEFF_N_MASK 0x000003FFU
  8908. #define MRV_DPF_NLL_COEFF_N_SHIFT 0U
  8909. /*! Register: isp_dpf_nf_gain_r: noise function gain for red pixels (0x00000064)*/
  8910. /*! Slice: DPF_NF_GAIN_R:*/
  8911. /*! Noise Function (NF) Gain that replaces the AWB gain for red pixels.*/
  8912. /* 12 bit unsigned integer format: gain=1 -> 0x100 */
  8913. #define MRV_DPF_DPF_NF_GAIN_R
  8914. #define MRV_DPF_DPF_NF_GAIN_R_MASK 0x00000FFFU
  8915. #define MRV_DPF_DPF_NF_GAIN_R_SHIFT 0U
  8916. /*! Register: isp_dpf_nf_gain_gr: noise function gain for green in red pixels (0x00000068)*/
  8917. /*! Slice: DPF_NF_GAIN_GR:*/
  8918. /*! Noise Function (NF) Gain that replaces the AWB gain for green pixels in a red line.*/
  8919. /* 12 bit unsigned integer format: gain=1 -> 0x100 */
  8920. #define MRV_DPF_DPF_NF_GAIN_GR
  8921. #define MRV_DPF_DPF_NF_GAIN_GR_MASK 0x00000FFFU
  8922. #define MRV_DPF_DPF_NF_GAIN_GR_SHIFT 0U
  8923. /*! Register: isp_dpf_nf_gain_gb: noise function gain for green in blue pixels (0x0000006c)*/
  8924. /*! Slice: DPF_NF_GAIN_GB:*/
  8925. /*! Noise Function (NF) Gain that replaces the AWB gain for green pixels in a blue line.*/
  8926. /* 12 bit unsigned integer format: gain=1 -> 0x100 */
  8927. #define MRV_DPF_DPF_NF_GAIN_GB
  8928. #define MRV_DPF_DPF_NF_GAIN_GB_MASK 0x00000FFFU
  8929. #define MRV_DPF_DPF_NF_GAIN_GB_SHIFT 0U
  8930. /*! Register: isp_dpf_nf_gain_b: noise function gain for blue pixels (0x00000070)*/
  8931. /*! Slice: DPF_NF_GAIN_B:*/
  8932. /*! Noise Function (NF) Gain that replaces the AWB gain for blue pixels.*/
  8933. /* 12 bit unsigned integer format: gain=1 -> 0x100 */
  8934. #define MRV_DPF_DPF_NF_GAIN_B
  8935. #define MRV_DPF_DPF_NF_GAIN_B_MASK 0x00000FFFU
  8936. #define MRV_DPF_DPF_NF_GAIN_B_SHIFT 0U
  8937. /*! Register: isp_dpcc_mode: Mode control for DPCC detection unit (0x00000000)*/
  8938. /*! Slice: STAGE1_ENABLE:*/
  8939. /*! 1: enable stage1 *Default**/
  8940. /* 0: bypass stage1 */
  8941. #define MRV_DPCC_STAGE1_ENABLE
  8942. #define MRV_DPCC_STAGE1_ENABLE_MASK 0x00000004U
  8943. #define MRV_DPCC_STAGE1_ENABLE_SHIFT 2U
  8944. /*! Slice: GRAYSCALE_MODE:*/
  8945. /*! 1: enable gray scale data input from black and white sensors (without color filter array)*/
  8946. /* 0: BAYER DATA INPUT *Default**/
  8947. #define MRV_DPCC_GRAYSCALE_MODE
  8948. #define MRV_DPCC_GRAYSCALE_MODE_MASK 0x00000002U
  8949. #define MRV_DPCC_GRAYSCALE_MODE_SHIFT 1U
  8950. /*! Slice: ISP_DPCC_enable:*/
  8951. /*! 1: enable DPCC */
  8952. /* 0: bypass DPCC *Default**/
  8953. #define MRV_DPCC_ISP_DPCC_ENABLE
  8954. #define MRV_DPCC_ISP_DPCC_ENABLE_MASK 0x00000001U
  8955. #define MRV_DPCC_ISP_DPCC_ENABLE_SHIFT 0U
  8956. /*! Register: isp_dpcc_output_mode: Interpolation mode for correction unit (0x00000004)*/
  8957. /*! Slice: STAGE1_RB_3x3:*/
  8958. /*! 1: stage1 red/blue 9 pixel (3x3) output median */
  8959. /* 0: stage1 red/blue 4 or 5 pixel output median *Default**/
  8960. #define MRV_DPCC_STAGE1_RB_3X3
  8961. #define MRV_DPCC_STAGE1_RB_3X3_MASK 0x00000008U
  8962. #define MRV_DPCC_STAGE1_RB_3X3_SHIFT 3U
  8963. /*! Slice: STAGE1_G_3x3:*/
  8964. /*! 1: stage1 green 9 pixel (3x3) output median */
  8965. /* 0: stage1 green 4 or 5 pixel output median *Default**/
  8966. #define MRV_DPCC_STAGE1_G_3X3
  8967. #define MRV_DPCC_STAGE1_G_3X3_MASK 0x00000004U
  8968. #define MRV_DPCC_STAGE1_G_3X3_SHIFT 2U
  8969. /*! Slice: STAGE1_INCL_RB_CENTER:*/
  8970. /*! 1: stage1 include center pixel for red/blue output median 2x2+1 */
  8971. /* *Default* 0: stage1 do not include center pixel for red/blue output median 2x2 */
  8972. #define MRV_DPCC_STAGE1_INCL_RB_CENTER
  8973. #define MRV_DPCC_STAGE1_INCL_RB_CENTER_MASK 0x00000002U
  8974. #define MRV_DPCC_STAGE1_INCL_RB_CENTER_SHIFT 1U
  8975. /*! Slice: STAGE1_INCL_GREEN_CENTER:*/
  8976. /*! 1: stage1 include center pixel for green output median 2x2+1 *Default**/
  8977. /* 0: stage1 do not include center pixel for green output median 2x2 */
  8978. #define MRV_DPCC_STAGE1_INCL_GREEN_CENTER
  8979. #define MRV_DPCC_STAGE1_INCL_GREEN_CENTER_MASK 0x00000001U
  8980. #define MRV_DPCC_STAGE1_INCL_GREEN_CENTER_SHIFT 0U
  8981. /*! Register: isp_dpcc_set_use: DPCC methods set usage for detection (0x00000008)*/
  8982. /*! Slice: STAGE1_USE_FIX_SET:*/
  8983. /*! 1: stage1 use hard coded methods set *Default**/
  8984. /* 0: stage1 do not use hard coded methods set */
  8985. #define MRV_DPCC_STAGE1_USE_FIX_SET
  8986. #define MRV_DPCC_STAGE1_USE_FIX_SET_MASK 0x00000008U
  8987. #define MRV_DPCC_STAGE1_USE_FIX_SET_SHIFT 3U
  8988. /*! Slice: STAGE1_USE_SET_3:*/
  8989. /*! 1: stage1 use methods set 3 */
  8990. /* 0: stage1 do not use methods set 3 *Default**/
  8991. #define MRV_DPCC_STAGE1_USE_SET_3
  8992. #define MRV_DPCC_STAGE1_USE_SET_3_MASK 0x00000004U
  8993. #define MRV_DPCC_STAGE1_USE_SET_3_SHIFT 2U
  8994. /*! Slice: STAGE1_USE_SET_2:*/
  8995. /*! 1: stage1 use methods set 2 */
  8996. /* 0: stage1 do not use methods set 2 *Default**/
  8997. #define MRV_DPCC_STAGE1_USE_SET_2
  8998. #define MRV_DPCC_STAGE1_USE_SET_2_MASK 0x00000002U
  8999. #define MRV_DPCC_STAGE1_USE_SET_2_SHIFT 1U
  9000. /*! Slice: STAGE1_USE_SET_1:*/
  9001. /*! 1: stage1 use methods set 1 *Default**/
  9002. /* 0: stage1 do not use methods set 1 */
  9003. #define MRV_DPCC_STAGE1_USE_SET_1
  9004. #define MRV_DPCC_STAGE1_USE_SET_1_MASK 0x00000001U
  9005. #define MRV_DPCC_STAGE1_USE_SET_1_SHIFT 0U
  9006. /*! Register: isp_dpcc_methods_set_1: Methods enable bits for SET_1 (0x0000000c)*/
  9007. /*! Slice: RG_RED_BLUE1_ENABLE:*/
  9008. /*! 1: enable Rank Gradient check for red_blue *Default**/
  9009. /* 0: bypass Rank Gradient check for red_blue */
  9010. #define MRV_DPCC_RG_RED_BLUE1_ENABLE
  9011. #define MRV_DPCC_RG_RED_BLUE1_ENABLE_MASK 0x00001000U
  9012. #define MRV_DPCC_RG_RED_BLUE1_ENABLE_SHIFT 12U
  9013. /*! Slice: RND_RED_BLUE1_ENABLE:*/
  9014. /*! 1: enable Rank Neighbor Difference check for red_blue *Default**/
  9015. /* 0: bypass Rank Neighbor Difference check for red_blue */
  9016. #define MRV_DPCC_RND_RED_BLUE1_ENABLE
  9017. #define MRV_DPCC_RND_RED_BLUE1_ENABLE_MASK 0x00000800U
  9018. #define MRV_DPCC_RND_RED_BLUE1_ENABLE_SHIFT 11U
  9019. /*! Slice: RO_RED_BLUE1_ENABLE:*/
  9020. /*! 1: enable Rank Order check for red_blue *Default**/
  9021. /* 0: bypass Rank Order check for red_blue */
  9022. #define MRV_DPCC_RO_RED_BLUE1_ENABLE
  9023. #define MRV_DPCC_RO_RED_BLUE1_ENABLE_MASK 0x00000400U
  9024. #define MRV_DPCC_RO_RED_BLUE1_ENABLE_SHIFT 10U
  9025. /*! Slice: LC_RED_BLUE1_ENABLE:*/
  9026. /*! 1: enable Line check for red_blue *Default**/
  9027. /* 0: bypass Line check for red_blue */
  9028. #define MRV_DPCC_LC_RED_BLUE1_ENABLE
  9029. #define MRV_DPCC_LC_RED_BLUE1_ENABLE_MASK 0x00000200U
  9030. #define MRV_DPCC_LC_RED_BLUE1_ENABLE_SHIFT 9U
  9031. /*! Slice: PG_RED_BLUE1_ENABLE:*/
  9032. /*! 1: enable Peak Gradient check for red_blue *Default**/
  9033. /* 0: bypass Peak Gradient check for red_blue */
  9034. #define MRV_DPCC_PG_RED_BLUE1_ENABLE
  9035. #define MRV_DPCC_PG_RED_BLUE1_ENABLE_MASK 0x00000100U
  9036. #define MRV_DPCC_PG_RED_BLUE1_ENABLE_SHIFT 8U
  9037. /*! Slice: RG_GREEN1_ENABLE:*/
  9038. /*! 1: enable Rank Gradient check for green *Default**/
  9039. /* 0: bypass Rank Gradient check for green */
  9040. #define MRV_DPCC_RG_GREEN1_ENABLE
  9041. #define MRV_DPCC_RG_GREEN1_ENABLE_MASK 0x00000010U
  9042. #define MRV_DPCC_RG_GREEN1_ENABLE_SHIFT 4U
  9043. /*! Slice: RND_GREEN1_ENABLE:*/
  9044. /*! 1: enable Rank Neighbor Difference check for green *Default**/
  9045. /* 0: bypass Rank Neighbor Difference check for green */
  9046. #define MRV_DPCC_RND_GREEN1_ENABLE
  9047. #define MRV_DPCC_RND_GREEN1_ENABLE_MASK 0x00000008U
  9048. #define MRV_DPCC_RND_GREEN1_ENABLE_SHIFT 3U
  9049. /*! Slice: RO_GREEN1_ENABLE:*/
  9050. /*! 1: enable Rank Order check for green *Default**/
  9051. /* 0: bypass Rank Order check for green */
  9052. #define MRV_DPCC_RO_GREEN1_ENABLE
  9053. #define MRV_DPCC_RO_GREEN1_ENABLE_MASK 0x00000004U
  9054. #define MRV_DPCC_RO_GREEN1_ENABLE_SHIFT 2U
  9055. /*! Slice: LC_GREEN1_ENABLE:*/
  9056. /*! 1: enable Line check for green *Default**/
  9057. /* 0: bypass Line check for green */
  9058. #define MRV_DPCC_LC_GREEN1_ENABLE
  9059. #define MRV_DPCC_LC_GREEN1_ENABLE_MASK 0x00000002U
  9060. #define MRV_DPCC_LC_GREEN1_ENABLE_SHIFT 1U
  9061. /*! Slice: PG_GREEN1_ENABLE:*/
  9062. /*! 1: enable Peak Gradient check for green *Default**/
  9063. /* 0: bypass Peak Gradient check for green */
  9064. #define MRV_DPCC_PG_GREEN1_ENABLE
  9065. #define MRV_DPCC_PG_GREEN1_ENABLE_MASK 0x00000001U
  9066. #define MRV_DPCC_PG_GREEN1_ENABLE_SHIFT 0U
  9067. /*! Register: isp_dpcc_methods_set_2: Methods enable bits for SET_2 (0x00000010)*/
  9068. /*! Slice: RG_RED_BLUE2_ENABLE:*/
  9069. /*! 1: enable Rank Gradient check for red_blue *Default**/
  9070. /* 0: bypass Rank Gradient check for red_blue */
  9071. #define MRV_DPCC_RG_RED_BLUE2_ENABLE
  9072. #define MRV_DPCC_RG_RED_BLUE2_ENABLE_MASK 0x00001000U
  9073. #define MRV_DPCC_RG_RED_BLUE2_ENABLE_SHIFT 12U
  9074. /*! Slice: RND_RED_BLUE2_ENABLE:*/
  9075. /*! 1: enable Rank Neighbor Difference check for red_blue *Default**/
  9076. /* 0: bypass Rank Neighbor Difference check for red_blue */
  9077. #define MRV_DPCC_RND_RED_BLUE2_ENABLE
  9078. #define MRV_DPCC_RND_RED_BLUE2_ENABLE_MASK 0x00000800U
  9079. #define MRV_DPCC_RND_RED_BLUE2_ENABLE_SHIFT 11U
  9080. /*! Slice: RO_RED_BLUE2_ENABLE:*/
  9081. /*! 1: enable Rank Order check for red_blue *Default**/
  9082. /* 0: bypass Rank Order check for red_blue */
  9083. #define MRV_DPCC_RO_RED_BLUE2_ENABLE
  9084. #define MRV_DPCC_RO_RED_BLUE2_ENABLE_MASK 0x00000400U
  9085. #define MRV_DPCC_RO_RED_BLUE2_ENABLE_SHIFT 10U
  9086. /*! Slice: LC_RED_BLUE2_ENABLE:*/
  9087. /*! 1: enable Line check for red_blue */
  9088. /* 0: bypass Line check for red_blue *Default**/
  9089. #define MRV_DPCC_LC_RED_BLUE2_ENABLE
  9090. #define MRV_DPCC_LC_RED_BLUE2_ENABLE_MASK 0x00000200U
  9091. #define MRV_DPCC_LC_RED_BLUE2_ENABLE_SHIFT 9U
  9092. /*! Slice: PG_RED_BLUE2_ENABLE:*/
  9093. /*! 1: enable Peak Gradient check for red_blue *Default**/
  9094. /* 0: bypass Peak Gradient check for red_blue */
  9095. #define MRV_DPCC_PG_RED_BLUE2_ENABLE
  9096. #define MRV_DPCC_PG_RED_BLUE2_ENABLE_MASK 0x00000100U
  9097. #define MRV_DPCC_PG_RED_BLUE2_ENABLE_SHIFT 8U
  9098. /*! Slice: RG_GREEN2_ENABLE:*/
  9099. /*! 1: enable Rank Gradient check for green *Default**/
  9100. /* 0: bypass Rank Gradient check for green */
  9101. #define MRV_DPCC_RG_GREEN2_ENABLE
  9102. #define MRV_DPCC_RG_GREEN2_ENABLE_MASK 0x00000010U
  9103. #define MRV_DPCC_RG_GREEN2_ENABLE_SHIFT 4U
  9104. /*! Slice: RND_GREEN2_ENABLE:*/
  9105. /*! 1: enable Rank Neighbor Difference check for green *Default**/
  9106. /* 0: bypass Rank Neighbor Difference check for green */
  9107. #define MRV_DPCC_RND_GREEN2_ENABLE
  9108. #define MRV_DPCC_RND_GREEN2_ENABLE_MASK 0x00000008U
  9109. #define MRV_DPCC_RND_GREEN2_ENABLE_SHIFT 3U
  9110. /*! Slice: RO_GREEN2_ENABLE:*/
  9111. /*! 1: enable Rank Order check for green *Default**/
  9112. /* 0: bypass Rank Order check for green */
  9113. #define MRV_DPCC_RO_GREEN2_ENABLE
  9114. #define MRV_DPCC_RO_GREEN2_ENABLE_MASK 0x00000004U
  9115. #define MRV_DPCC_RO_GREEN2_ENABLE_SHIFT 2U
  9116. /*! Slice: LC_GREEN2_ENABLE:*/
  9117. /*! 1: enable Line check for green */
  9118. /* 0: bypass Line check for green *Default**/
  9119. #define MRV_DPCC_LC_GREEN2_ENABLE
  9120. #define MRV_DPCC_LC_GREEN2_ENABLE_MASK 0x00000002U
  9121. #define MRV_DPCC_LC_GREEN2_ENABLE_SHIFT 1U
  9122. /*! Slice: PG_GREEN2_ENABLE:*/
  9123. /*! 1: enable Peak Gradient check for green *Default**/
  9124. /* 0: bypass Peak Gradient check for green */
  9125. #define MRV_DPCC_PG_GREEN2_ENABLE
  9126. #define MRV_DPCC_PG_GREEN2_ENABLE_MASK 0x00000001U
  9127. #define MRV_DPCC_PG_GREEN2_ENABLE_SHIFT 0U
  9128. /*! Register: isp_dpcc_methods_set_3: Methods enable bits for SET_3 (0x00000014)*/
  9129. /*! Slice: RG_RED_BLUE3_ENABLE:*/
  9130. /*! 1: enable Rank Gradient check for red_blue */
  9131. /* 0: bypass Rank Gradient check for red_blue *Default**/
  9132. #define MRV_DPCC_RG_RED_BLUE3_ENABLE
  9133. #define MRV_DPCC_RG_RED_BLUE3_ENABLE_MASK 0x00001000U
  9134. #define MRV_DPCC_RG_RED_BLUE3_ENABLE_SHIFT 12U
  9135. /*! Slice: RND_RED_BLUE3_ENABLE:*/
  9136. /*! 1: enable Rank Neighbor Difference check for red_blue */
  9137. /* 0: bypass Rank Neighbor Difference check for red_blue *Default**/
  9138. #define MRV_DPCC_RND_RED_BLUE3_ENABLE
  9139. #define MRV_DPCC_RND_RED_BLUE3_ENABLE_MASK 0x00000800U
  9140. #define MRV_DPCC_RND_RED_BLUE3_ENABLE_SHIFT 11U
  9141. /*! Slice: RO_RED_BLUE3_ENABLE:*/
  9142. /*! 1: enable Rank Order check for red_blue *Default**/
  9143. /* 0: bypass Rank Order check for red_blue */
  9144. #define MRV_DPCC_RO_RED_BLUE3_ENABLE
  9145. #define MRV_DPCC_RO_RED_BLUE3_ENABLE_MASK 0x00000400U
  9146. #define MRV_DPCC_RO_RED_BLUE3_ENABLE_SHIFT 10U
  9147. /*! Slice: LC_RED_BLUE3_ENABLE:*/
  9148. /*! 1: enable Line check for red_blue *Default**/
  9149. /* 0: bypass Line check for red_blue */
  9150. #define MRV_DPCC_LC_RED_BLUE3_ENABLE
  9151. #define MRV_DPCC_LC_RED_BLUE3_ENABLE_MASK 0x00000200U
  9152. #define MRV_DPCC_LC_RED_BLUE3_ENABLE_SHIFT 9U
  9153. /*! Slice: PG_RED_BLUE3_ENABLE:*/
  9154. /*! 1: enable Peak Gradient check for red_blue *Default**/
  9155. /* 0: bypass Peak Gradient check for red_blue */
  9156. #define MRV_DPCC_PG_RED_BLUE3_ENABLE
  9157. #define MRV_DPCC_PG_RED_BLUE3_ENABLE_MASK 0x00000100U
  9158. #define MRV_DPCC_PG_RED_BLUE3_ENABLE_SHIFT 8U
  9159. /*! Slice: RG_GREEN3_ENABLE:*/
  9160. /*! 1: enable Rank Gradient check for green */
  9161. /* 0: bypass Rank Gradient check for green *Default**/
  9162. #define MRV_DPCC_RG_GREEN3_ENABLE
  9163. #define MRV_DPCC_RG_GREEN3_ENABLE_MASK 0x00000010U
  9164. #define MRV_DPCC_RG_GREEN3_ENABLE_SHIFT 4U
  9165. /*! Slice: RND_GREEN3_ENABLE:*/
  9166. /*! 1: enable Rank Neighbor Difference check for green */
  9167. /* 0: bypass Rank Neighbor Difference check for green *Default**/
  9168. #define MRV_DPCC_RND_GREEN3_ENABLE
  9169. #define MRV_DPCC_RND_GREEN3_ENABLE_MASK 0x00000008U
  9170. #define MRV_DPCC_RND_GREEN3_ENABLE_SHIFT 3U
  9171. /*! Slice: RO_GREEN3_ENABLE:*/
  9172. /*! 1: enable Rank Order check for green *Default**/
  9173. /* 0: bypass Rank Order check for green */
  9174. #define MRV_DPCC_RO_GREEN3_ENABLE
  9175. #define MRV_DPCC_RO_GREEN3_ENABLE_MASK 0x00000004U
  9176. #define MRV_DPCC_RO_GREEN3_ENABLE_SHIFT 2U
  9177. /*! Slice: LC_GREEN3_ENABLE:*/
  9178. /*! 1: enable Line check for green *Default**/
  9179. /* 0: bypass Line check for green */
  9180. #define MRV_DPCC_LC_GREEN3_ENABLE
  9181. #define MRV_DPCC_LC_GREEN3_ENABLE_MASK 0x00000002U
  9182. #define MRV_DPCC_LC_GREEN3_ENABLE_SHIFT 1U
  9183. /*! Slice: PG_GREEN3_ENABLE:*/
  9184. /*! 1: enable Peak Gradient check for green *Default**/
  9185. /* 0: bypass Peak Gradient check for green */
  9186. #define MRV_DPCC_PG_GREEN3_ENABLE
  9187. #define MRV_DPCC_PG_GREEN3_ENABLE_MASK 0x00000001U
  9188. #define MRV_DPCC_PG_GREEN3_ENABLE_SHIFT 0U
  9189. /*! Register: isp_dpcc_line_thresh_1: Line threshold SET_1 (0x00000018)*/
  9190. /*! Slice: LINE_THR_1_RB:*/
  9191. /*! line threshold for set 1 red/blue */
  9192. #define MRV_DPCC_LINE_THR_1_RB
  9193. #define MRV_DPCC_LINE_THR_1_RB_MASK 0x0000FF00U
  9194. #define MRV_DPCC_LINE_THR_1_RB_SHIFT 8U
  9195. /*! Slice: LINE_THR_1_G:*/
  9196. /*! line threshold for set 1 green */
  9197. #define MRV_DPCC_LINE_THR_1_G
  9198. #define MRV_DPCC_LINE_THR_1_G_MASK 0x000000FFU
  9199. #define MRV_DPCC_LINE_THR_1_G_SHIFT 0U
  9200. /*! Register: isp_dpcc_line_mad_fac_1: Mean Absolute Difference (MAD) factor for Line check set 1 (0x0000001c)*/
  9201. /*! Slice: LINE_MAD_FAC_1_RB:*/
  9202. /*! line MAD factor for set 1 red/blue */
  9203. #define MRV_DPCC_LINE_MAD_FAC_1_RB
  9204. #define MRV_DPCC_LINE_MAD_FAC_1_RB_MASK 0x00003F00U
  9205. #define MRV_DPCC_LINE_MAD_FAC_1_RB_SHIFT 8U
  9206. /*! Slice: LINE_MAD_FAC_1_G:*/
  9207. /*! line MAD factor for set 1 green */
  9208. #define MRV_DPCC_LINE_MAD_FAC_1_G
  9209. #define MRV_DPCC_LINE_MAD_FAC_1_G_MASK 0x0000003FU
  9210. #define MRV_DPCC_LINE_MAD_FAC_1_G_SHIFT 0U
  9211. /*! Register: isp_dpcc_pg_fac_1: Peak gradient factor for set 1 (0x00000020)*/
  9212. /*! Slice: PG_FAC_1_RB:*/
  9213. /*! Peak gradient factor for set 1 red/blue */
  9214. #define MRV_DPCC_PG_FAC_1_RB
  9215. #define MRV_DPCC_PG_FAC_1_RB_MASK 0x00003F00U
  9216. #define MRV_DPCC_PG_FAC_1_RB_SHIFT 8U
  9217. /*! Slice: PG_FAC_1_G:*/
  9218. /*! Peak gradient factor for set 1 green */
  9219. #define MRV_DPCC_PG_FAC_1_G
  9220. #define MRV_DPCC_PG_FAC_1_G_MASK 0x0000003FU
  9221. #define MRV_DPCC_PG_FAC_1_G_SHIFT 0U
  9222. /*! Register: isp_dpcc_rnd_thresh_1: Rank Neighbor Difference threshold for set 1 (0x00000024)*/
  9223. /*! Slice: RND_THR_1_RB:*/
  9224. /*! Rank Neighbor Difference threshold for set 1 red/blue */
  9225. #define MRV_DPCC_RND_THR_1_RB
  9226. #define MRV_DPCC_RND_THR_1_RB_MASK 0x0000FF00U
  9227. #define MRV_DPCC_RND_THR_1_RB_SHIFT 8U
  9228. /*! Slice: RND_THR_1_G:*/
  9229. /*! Rank Neighbor Difference threshold for set 1 green */
  9230. #define MRV_DPCC_RND_THR_1_G
  9231. #define MRV_DPCC_RND_THR_1_G_MASK 0x000000FFU
  9232. #define MRV_DPCC_RND_THR_1_G_SHIFT 0U
  9233. /*! Register: isp_dpcc_rg_fac_1: Rank gradient factor for set 1 (0x00000028)*/
  9234. /*! Slice: RG_FAC_1_RB:*/
  9235. /*! Rank gradient factor for set 1 red/blue */
  9236. #define MRV_DPCC_RG_FAC_1_RB
  9237. #define MRV_DPCC_RG_FAC_1_RB_MASK 0x00003F00U
  9238. #define MRV_DPCC_RG_FAC_1_RB_SHIFT 8U
  9239. /*! Slice: RG_FAC_1_G:*/
  9240. /*! Rank gradient factor for set 1 green */
  9241. #define MRV_DPCC_RG_FAC_1_G
  9242. #define MRV_DPCC_RG_FAC_1_G_MASK 0x0000003FU
  9243. #define MRV_DPCC_RG_FAC_1_G_SHIFT 0U
  9244. /*! Register: isp_dpcc_line_thresh_2: Line threshold set 2 (0x0000002c)*/
  9245. /*! Slice: LINE_THR_2_RB:*/
  9246. /*! line threshold for set 2 red/blue */
  9247. #define MRV_DPCC_LINE_THR_2_RB
  9248. #define MRV_DPCC_LINE_THR_2_RB_MASK 0x0000FF00U
  9249. #define MRV_DPCC_LINE_THR_2_RB_SHIFT 8U
  9250. /*! Slice: LINE_THR_2_G:*/
  9251. /*! line threshold for set 2 green */
  9252. #define MRV_DPCC_LINE_THR_2_G
  9253. #define MRV_DPCC_LINE_THR_2_G_MASK 0x000000FFU
  9254. #define MRV_DPCC_LINE_THR_2_G_SHIFT 0U
  9255. /*! Register: isp_dpcc_line_mad_fac_2: Mean Absolute Difference (MAD) factor for Line check set 2 (0x00000030)*/
  9256. /*! Slice: LINE_MAD_FAC_2_RB:*/
  9257. /*! line MAD factor for set 2 red/blue */
  9258. #define MRV_DPCC_LINE_MAD_FAC_2_RB
  9259. #define MRV_DPCC_LINE_MAD_FAC_2_RB_MASK 0x00003F00U
  9260. #define MRV_DPCC_LINE_MAD_FAC_2_RB_SHIFT 8U
  9261. /*! Slice: LINE_MAD_FAC_2_G:*/
  9262. /*! line MAD factor for set 2 green */
  9263. #define MRV_DPCC_LINE_MAD_FAC_2_G
  9264. #define MRV_DPCC_LINE_MAD_FAC_2_G_MASK 0x0000003FU
  9265. #define MRV_DPCC_LINE_MAD_FAC_2_G_SHIFT 0U
  9266. /*! Register: isp_dpcc_pg_fac_2: Peak gradient factor for set 2 (0x00000034)*/
  9267. /*! Slice: PG_FAC_2_RB:*/
  9268. /*! Peak gradient factor for set 2 red/blue */
  9269. #define MRV_DPCC_PG_FAC_2_RB
  9270. #define MRV_DPCC_PG_FAC_2_RB_MASK 0x00003F00U
  9271. #define MRV_DPCC_PG_FAC_2_RB_SHIFT 8U
  9272. /*! Slice: PG_FAC_2_G:*/
  9273. /*! Peak gradient factor for set 2 green */
  9274. #define MRV_DPCC_PG_FAC_2_G
  9275. #define MRV_DPCC_PG_FAC_2_G_MASK 0x0000003FU
  9276. #define MRV_DPCC_PG_FAC_2_G_SHIFT 0U
  9277. /*! Register: isp_dpcc_rnd_thresh_2: Rank Neighbor Difference threshold for set 2 (0x00000038)*/
  9278. /*! Slice: RND_THR_2_RB:*/
  9279. /*! Rank Neighbor Difference threshold for set 2 red/blue */
  9280. #define MRV_DPCC_RND_THR_2_RB
  9281. #define MRV_DPCC_RND_THR_2_RB_MASK 0x0000FF00U
  9282. #define MRV_DPCC_RND_THR_2_RB_SHIFT 8U
  9283. /*! Slice: RND_THR_2_G:*/
  9284. /*! Rank Neighbor Difference threshold for set 2 green */
  9285. #define MRV_DPCC_RND_THR_2_G
  9286. #define MRV_DPCC_RND_THR_2_G_MASK 0x000000FFU
  9287. #define MRV_DPCC_RND_THR_2_G_SHIFT 0U
  9288. /*! Register: isp_dpcc_rg_fac_2: Rank gradient factor for set 2 (0x0000003c)*/
  9289. /*! Slice: RG_FAC_2_RB:*/
  9290. /*! Rank gradient factor for set 2 red/blue */
  9291. #define MRV_DPCC_RG_FAC_2_RB
  9292. #define MRV_DPCC_RG_FAC_2_RB_MASK 0x00003F00U
  9293. #define MRV_DPCC_RG_FAC_2_RB_SHIFT 8U
  9294. /*! Slice: RG_FAC_2_G:*/
  9295. /*! Rank gradient factor for set 2 green */
  9296. #define MRV_DPCC_RG_FAC_2_G
  9297. #define MRV_DPCC_RG_FAC_2_G_MASK 0x0000003FU
  9298. #define MRV_DPCC_RG_FAC_2_G_SHIFT 0U
  9299. /*! Register: isp_dpcc_line_thresh_3: Line threshold set 3 (0x00000040)*/
  9300. /*! Slice: LINE_THR_3_RB:*/
  9301. /*! line threshold for set 3 red/blue */
  9302. #define MRV_DPCC_LINE_THR_3_RB
  9303. #define MRV_DPCC_LINE_THR_3_RB_MASK 0x0000FF00U
  9304. #define MRV_DPCC_LINE_THR_3_RB_SHIFT 8U
  9305. /*! Slice: LINE_THR_3_G:*/
  9306. /*! line threshold for set 3 green */
  9307. #define MRV_DPCC_LINE_THR_3_G
  9308. #define MRV_DPCC_LINE_THR_3_G_MASK 0x000000FFU
  9309. #define MRV_DPCC_LINE_THR_3_G_SHIFT 0U
  9310. /*! Register: isp_dpcc_line_mad_fac_3: Mean Absolute Difference (MAD) factor for Line check set 3 (0x00000044)*/
  9311. /*! Slice: LINE_MAD_FAC_3_RB:*/
  9312. /*! line MAD factor for set 3 red/blue */
  9313. #define MRV_DPCC_LINE_MAD_FAC_3_RB
  9314. #define MRV_DPCC_LINE_MAD_FAC_3_RB_MASK 0x00003F00U
  9315. #define MRV_DPCC_LINE_MAD_FAC_3_RB_SHIFT 8U
  9316. /*! Slice: LINE_MAD_FAC_3_G:*/
  9317. /*! line MAD factor for set 3 green */
  9318. #define MRV_DPCC_LINE_MAD_FAC_3_G
  9319. #define MRV_DPCC_LINE_MAD_FAC_3_G_MASK 0x0000003FU
  9320. #define MRV_DPCC_LINE_MAD_FAC_3_G_SHIFT 0U
  9321. /*! Register: isp_dpcc_pg_fac_3: Peak gradient factor for set 3 (0x00000048)*/
  9322. /*! Slice: PG_FAC_3_RB:*/
  9323. /*! Peak gradient factor for set 3 red/blue */
  9324. #define MRV_DPCC_PG_FAC_3_RB
  9325. #define MRV_DPCC_PG_FAC_3_RB_MASK 0x00003F00U
  9326. #define MRV_DPCC_PG_FAC_3_RB_SHIFT 8U
  9327. /*! Slice: PG_FAC_3_G:*/
  9328. /*! Peak gradient factor for set 3 green */
  9329. #define MRV_DPCC_PG_FAC_3_G
  9330. #define MRV_DPCC_PG_FAC_3_G_MASK 0x0000003FU
  9331. #define MRV_DPCC_PG_FAC_3_G_SHIFT 0U
  9332. /*! Register: isp_dpcc_rnd_thresh_3: Rank Neighbor Difference threshold for set 3 (0x0000004c)*/
  9333. /*! Slice: RND_THR_3_RB:*/
  9334. /*! Rank Neighbor Difference threshold for set 3 red/blue */
  9335. #define MRV_DPCC_RND_THR_3_RB
  9336. #define MRV_DPCC_RND_THR_3_RB_MASK 0x0000FF00U
  9337. #define MRV_DPCC_RND_THR_3_RB_SHIFT 8U
  9338. /*! Slice: RND_THR_3_G:*/
  9339. /*! Rank Neighbor Difference threshold for set 3 green */
  9340. #define MRV_DPCC_RND_THR_3_G
  9341. #define MRV_DPCC_RND_THR_3_G_MASK 0x000000FFU
  9342. #define MRV_DPCC_RND_THR_3_G_SHIFT 0U
  9343. /*! Register: isp_dpcc_rg_fac_3: Rank gradient factor for set 3 (0x00000050)*/
  9344. /*! Slice: RG_FAC_3_RB:*/
  9345. /*! Rank gradient factor for set 3 red/blue */
  9346. #define MRV_DPCC_RG_FAC_3_RB
  9347. #define MRV_DPCC_RG_FAC_3_RB_MASK 0x00003F00U
  9348. #define MRV_DPCC_RG_FAC_3_RB_SHIFT 8U
  9349. /*! Slice: RG_FAC_3_G:*/
  9350. /*! Rank gradient factor for set 3 green */
  9351. #define MRV_DPCC_RG_FAC_3_G
  9352. #define MRV_DPCC_RG_FAC_3_G_MASK 0x0000003FU
  9353. #define MRV_DPCC_RG_FAC_3_G_SHIFT 0U
  9354. /*! Register: isp_dpcc_ro_limits: Rank Order Limits (0x00000054)*/
  9355. /*! Slice: RO_LIM_3_RB:*/
  9356. /*! Rank order limit for set 3 red/blue */
  9357. #define MRV_DPCC_RO_LIM_3_RB
  9358. #define MRV_DPCC_RO_LIM_3_RB_MASK 0x00000C00U
  9359. #define MRV_DPCC_RO_LIM_3_RB_SHIFT 10U
  9360. /*! Slice: RO_LIM_3_G:*/
  9361. /*! Rank order limit for set 3 green */
  9362. #define MRV_DPCC_RO_LIM_3_G
  9363. #define MRV_DPCC_RO_LIM_3_G_MASK 0x00000300U
  9364. #define MRV_DPCC_RO_LIM_3_G_SHIFT 8U
  9365. /*! Slice: RO_LIM_2_RB:*/
  9366. /*! Rank order limit for set 2 red/blue */
  9367. #define MRV_DPCC_RO_LIM_2_RB
  9368. #define MRV_DPCC_RO_LIM_2_RB_MASK 0x000000C0U
  9369. #define MRV_DPCC_RO_LIM_2_RB_SHIFT 6U
  9370. /*! Slice: RO_LIM_2_G:*/
  9371. /*! Rank order limit for set 2 green */
  9372. #define MRV_DPCC_RO_LIM_2_G
  9373. #define MRV_DPCC_RO_LIM_2_G_MASK 0x00000030U
  9374. #define MRV_DPCC_RO_LIM_2_G_SHIFT 4U
  9375. /*! Slice: RO_LIM_1_RB:*/
  9376. /*! Rank order limit for set 1 red/blue */
  9377. #define MRV_DPCC_RO_LIM_1_RB
  9378. #define MRV_DPCC_RO_LIM_1_RB_MASK 0x0000000CU
  9379. #define MRV_DPCC_RO_LIM_1_RB_SHIFT 2U
  9380. /*! Slice: RO_LIM_1_G:*/
  9381. /*! Rank order limit for set 1 green */
  9382. #define MRV_DPCC_RO_LIM_1_G
  9383. #define MRV_DPCC_RO_LIM_1_G_MASK 0x00000003U
  9384. #define MRV_DPCC_RO_LIM_1_G_SHIFT 0U
  9385. /*! Register: isp_dpcc_rnd_offs: Differential Rank Offsets for Rank Neighbor Difference (0x00000058)*/
  9386. /*! Slice: RND_OFFS_3_RB:*/
  9387. /*! Rank Offset to Neighbor for set 3 red/blue */
  9388. #define MRV_DPCC_RND_OFFS_3_RB
  9389. #define MRV_DPCC_RND_OFFS_3_RB_MASK 0x00000C00U
  9390. #define MRV_DPCC_RND_OFFS_3_RB_SHIFT 10U
  9391. /*! Slice: RND_OFFS_3_G:*/
  9392. /*! Rank Offset to Neighbor for set 3 green */
  9393. #define MRV_DPCC_RND_OFFS_3_G
  9394. #define MRV_DPCC_RND_OFFS_3_G_MASK 0x00000300U
  9395. #define MRV_DPCC_RND_OFFS_3_G_SHIFT 8U
  9396. /*! Slice: RND_OFFS_2_RB:*/
  9397. /*! Rank Offset to Neighbor for set 2 red/blue */
  9398. #define MRV_DPCC_RND_OFFS_2_RB
  9399. #define MRV_DPCC_RND_OFFS_2_RB_MASK 0x000000C0U
  9400. #define MRV_DPCC_RND_OFFS_2_RB_SHIFT 6U
  9401. /*! Slice: RND_OFFS_2_G:*/
  9402. /*! Rank Offset to Neighbor for set 2 green */
  9403. #define MRV_DPCC_RND_OFFS_2_G
  9404. #define MRV_DPCC_RND_OFFS_2_G_MASK 0x00000030U
  9405. #define MRV_DPCC_RND_OFFS_2_G_SHIFT 4U
  9406. /*! Slice: RND_OFFS_1_RB:*/
  9407. /*! Rank Offset to Neighbor for set 1 red/blue */
  9408. #define MRV_DPCC_RND_OFFS_1_RB
  9409. #define MRV_DPCC_RND_OFFS_1_RB_MASK 0x0000000CU
  9410. #define MRV_DPCC_RND_OFFS_1_RB_SHIFT 2U
  9411. /*! Slice: RND_OFFS_1_G:*/
  9412. /*! Rank Offset to Neighbor for set 1 green */
  9413. #define MRV_DPCC_RND_OFFS_1_G
  9414. #define MRV_DPCC_RND_OFFS_1_G_MASK 0x00000003U
  9415. #define MRV_DPCC_RND_OFFS_1_G_SHIFT 0U
  9416. /*! Register: isp_dpcc_bpt_ctrl: bad pixel table settings (0x0000005c)*/
  9417. /*! Slice: BPT_RB_3x3:*/
  9418. /*! 1: if BPT active red/blue 9 pixel (3x3) output median */
  9419. /* 0: if BPT active red/blue 4 or 5 pixel output median *Default**/
  9420. #define MRV_DPCC_BPT_RB_3X3
  9421. #define MRV_DPCC_BPT_RB_3X3_MASK 0x00000800U
  9422. #define MRV_DPCC_BPT_RB_3X3_SHIFT 11U
  9423. /*! Slice: BPT_G_3x3:*/
  9424. /*! 1: if BPT active green 9 pixel (3x3) output median */
  9425. /* 0: if BPT active green 4 or 5 pixel output median *Default**/
  9426. #define MRV_DPCC_BPT_G_3X3
  9427. #define MRV_DPCC_BPT_G_3X3_MASK 0x00000400U
  9428. #define MRV_DPCC_BPT_G_3X3_SHIFT 10U
  9429. /*! Slice: BPT_INCL_RB_CENTER:*/
  9430. /*! 1: if BPT active include center pixel for red/blue output median 2x2+1 */
  9431. /* 0: if BPT active do not include center pixel for red/blue output median 2x2 *Default**/
  9432. #define MRV_DPCC_BPT_INCL_RB_CENTER
  9433. #define MRV_DPCC_BPT_INCL_RB_CENTER_MASK 0x00000200U
  9434. #define MRV_DPCC_BPT_INCL_RB_CENTER_SHIFT 9U
  9435. /*! Slice: BPT_INCL_GREEN_CENTER:*/
  9436. /*! 1: if BPT active include center pixel for green output median 2x2+1 */
  9437. /* 0: if BPT active do not include center pixel for green output median 2x2 *Default**/
  9438. #define MRV_DPCC_BPT_INCL_GREEN_CENTER
  9439. #define MRV_DPCC_BPT_INCL_GREEN_CENTER_MASK 0x00000100U
  9440. #define MRV_DPCC_BPT_INCL_GREEN_CENTER_SHIFT 8U
  9441. /*! Slice: BPT_USE_FIX_SET:*/
  9442. /*! 1: for BPT write use hard coded methods set */
  9443. /* 0: for BPT write do not use hard coded methods set *Default**/
  9444. #define MRV_DPCC_BPT_USE_FIX_SET
  9445. #define MRV_DPCC_BPT_USE_FIX_SET_MASK 0x00000080U
  9446. #define MRV_DPCC_BPT_USE_FIX_SET_SHIFT 7U
  9447. /*! Slice: BPT_USE_SET_3:*/
  9448. /*! 1: for BPT write use methods set 3 */
  9449. /* 0: for BPT write do not use methods set 3 *Default**/
  9450. #define MRV_DPCC_BPT_USE_SET_3
  9451. #define MRV_DPCC_BPT_USE_SET_3_MASK 0x00000040U
  9452. #define MRV_DPCC_BPT_USE_SET_3_SHIFT 6U
  9453. /*! Slice: BPT_USE_SET_2:*/
  9454. /*! 1: for BPT write use methods set 2 */
  9455. /* 0: for BPT write do not use methods set 2 *Default**/
  9456. #define MRV_DPCC_BPT_USE_SET_2
  9457. #define MRV_DPCC_BPT_USE_SET_2_MASK 0x00000020U
  9458. #define MRV_DPCC_BPT_USE_SET_2_SHIFT 5U
  9459. /*! Slice: BPT_USE_SET_1:*/
  9460. /*! 1: for BPT write use methods set 1 */
  9461. /* 0: for BPT write do not use methods set 1 *Default**/
  9462. #define MRV_DPCC_BPT_USE_SET_1
  9463. #define MRV_DPCC_BPT_USE_SET_1_MASK 0x00000010U
  9464. #define MRV_DPCC_BPT_USE_SET_1_SHIFT 4U
  9465. /*! Slice: bpt_cor_en:*/
  9466. /*! table based correction enable */
  9467. /* 1: table based correction is enabled */
  9468. /* 0: table based correction is disabled */
  9469. #define MRV_DPCC_BPT_COR_EN
  9470. #define MRV_DPCC_BPT_COR_EN_MASK 0x00000002U
  9471. #define MRV_DPCC_BPT_COR_EN_SHIFT 1U
  9472. /*! Slice: bpt_det_en:*/
  9473. /*! Bad pixel detection write enable */
  9474. /* 1: bad pixel detection write to memory is enabled */
  9475. /* 0: bad pixel detection write to memory is disabled */
  9476. #define MRV_DPCC_BPT_DET_EN
  9477. #define MRV_DPCC_BPT_DET_EN_MASK 0x00000001U
  9478. #define MRV_DPCC_BPT_DET_EN_SHIFT 0U
  9479. /*! Register: isp_dpcc_bpt_number: Number of entries for bad pixel table (table based correction) (0x00000060)*/
  9480. /*! Slice: bp_number:*/
  9481. /*! Number of current Bad Pixel entries in bad pixel table (BPT)*/
  9482. #define MRV_DPCC_BP_NUMBER
  9483. #define MRV_DPCC_BP_NUMBER_MASK 0x00000FFFU
  9484. #define MRV_DPCC_BP_NUMBER_SHIFT 0U
  9485. /*! Register: isp_dpcc_bpt_addr: TABLE Start Address for table-based correction algorithm (0x00000064)*/
  9486. /*! Slice: bp_table_addr:*/
  9487. /*! Table RAM start address for read or write operations. The address counter is incremented at each read or write access to the data register (auto-increment mechanism).*/
  9488. #define MRV_DPCC_BP_TABLE_ADDR
  9489. #define MRV_DPCC_BP_TABLE_ADDR_MASK 0x000007FFU
  9490. #define MRV_DPCC_BP_TABLE_ADDR_SHIFT 0U
  9491. /*! Register: isp_dpcc_bpt_data: TABLE DATA register for read and write access of table RAM (0x00000068)*/
  9492. /*! Slice: bpt_v_addr:*/
  9493. /*! Bad Pixel vertical address (pixel position)*/
  9494. #define MRV_DPCC_BPT_V_ADDR
  9495. #define MRV_DPCC_BPT_V_ADDR_MASK 0x0FFF0000U
  9496. #define MRV_DPCC_BPT_V_ADDR_SHIFT 16U
  9497. /*! Slice: bpt_h_addr:*/
  9498. /*! Bad Pixel horizontal address (pixel position)*/
  9499. #define MRV_DPCC_BPT_H_ADDR
  9500. #define MRV_DPCC_BPT_H_ADDR_MASK 0x00001FFFU
  9501. #define MRV_DPCC_BPT_H_ADDR_SHIFT 0U
  9502. /*! Register: isp_wdr_ctrl: Control Bits for Wide Dynamic Range Unit (0x00000000)*/
  9503. /*! Slice: WDR_RGB_FACTOR:*/
  9504. /*! rgb_factor defines how much influence the RGBmax approach has in comparison to Y. The illumination reference Iref is calculated according to the following formula:*/
  9505. /* Iref = (WDR_RGB_FACTOR * RGBYmax_tr + (8 - WDR_RGB_FACTOR) * Y) / 8 */
  9506. /* So, rgb_factor = 0 means that the standard approach is used. Use of this factor requires that Iref has been selected, see WDR_USE_IREF.*/
  9507. /* Value range of rgb_factor: 0...8 */
  9508. #define MRV_WDR_RGB_FACTOR
  9509. #define MRV_WDR_RGB_FACTOR_MASK 0x00000F00U
  9510. #define MRV_WDR_RGB_FACTOR_SHIFT 8U
  9511. /*! Slice: WDR_DISABLE_TRANSIENT:*/
  9512. /*! 1: disable transient between Y and RGBY_max */
  9513. /* 0: calculate transient between Y and RGBY_max (for noise reduction) *Default**/
  9514. /* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/
  9515. #define MRV_WDR_DISABLE_TRANSIENT
  9516. #define MRV_WDR_DISABLE_TRANSIENT_MASK 0x00000040U
  9517. #define MRV_WDR_DISABLE_TRANSIENT_SHIFT 6U
  9518. /*! Slice: WDR_USE_RGB7_8:*/
  9519. /*! 1: decrease RGBmax by 7/8 (for noise reduction)*/
  9520. /* 0: do not modify RGBmax *Default**/
  9521. /* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/
  9522. #define MRV_WDR_USE_RGB7_8
  9523. #define MRV_WDR_USE_RGB7_8_MASK 0x00000020U
  9524. #define MRV_WDR_USE_RGB7_8_SHIFT 5U
  9525. /*! Slice: WDR_USE_Y9_8:*/
  9526. /*! 1: use R G B and Y*9/8 for maximum value calculation (for noise reduction)*/
  9527. /* 0: only use R G B for maximum value calculation (RGBYmax approach) *Default**/
  9528. /* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/
  9529. #define MRV_WDR_USE_Y9_8
  9530. #define MRV_WDR_USE_Y9_8_MASK 0x00000010U
  9531. #define MRV_WDR_USE_Y9_8_SHIFT 4U
  9532. /*! Slice: WDR_USE_IREF:*/
  9533. /*! 1: use Iref (Illumination reference) instead of Y for ToneMapping and Gain calculation */
  9534. /* 0: use Y for ToneMapping and Gain calculation *Default**/
  9535. /* Iref is calculated according to the following formula:*/
  9536. /* Iref = (WDR_RGB_FACTOR * RGBmax_tr + (8 - WDR_RGB_FACTOR) * Y) / 8 */
  9537. #define MRV_WDR_USE_IREF
  9538. #define MRV_WDR_USE_IREF_MASK 0x00000008U
  9539. #define MRV_WDR_USE_IREF_SHIFT 3U
  9540. /*! Slice: WDR_CR_MAPPING_DISABLE:*/
  9541. /*! 1: disable (bypass) Chrominance Mapping */
  9542. /* 0: enable Chrominance Mapping *Default**/
  9543. /* requires that Luminance/chrominance color space has been selected */
  9544. #define MRV_WDR_CR_MAPPING_DISABLE
  9545. #define MRV_WDR_CR_MAPPING_DISABLE_MASK 0x00000004U
  9546. #define MRV_WDR_CR_MAPPING_DISABLE_SHIFT 2U
  9547. /*! Slice: WDR_COLOR_SPACE_SELECT:*/
  9548. /*! 1: R, G, B color space */
  9549. /* 0: Luminance/Chrominance color space *Default**/
  9550. #define MRV_WDR_COLOR_SPACE_SELECT
  9551. #define MRV_WDR_COLOR_SPACE_SELECT_MASK 0x00000002U
  9552. #define MRV_WDR_COLOR_SPACE_SELECT_SHIFT 1U
  9553. /*! Slice: WDR_ENABLE:*/
  9554. /*! 1: enable WDR */
  9555. /* 0: bypass WDR *Default**/
  9556. #define MRV_WDR_ENABLE
  9557. #define MRV_WDR_ENABLE_MASK 0x00000001U
  9558. #define MRV_WDR_ENABLE_SHIFT 0U
  9559. /*! Register: isp_wdr_tonecurve_1: Tone Curve sample points dYn definition (part 1) (0x00000004)*/
  9560. /*! Slice: WDR_dY8:*/
  9561. /*! Tone curve sample point definition dY8 on the horizontal axis (input)*/
  9562. #define MRV_WDR_DY8
  9563. #define MRV_WDR_DY8_MASK 0x70000000U
  9564. #define MRV_WDR_DY8_SHIFT 28U
  9565. /*! Slice: WDR_dY7:*/
  9566. /*! Tone curve sample point definition dY7 on the horizontal axis (input)*/
  9567. #define MRV_WDR_DY7
  9568. #define MRV_WDR_DY7_MASK 0x07000000U
  9569. #define MRV_WDR_DY7_SHIFT 24U
  9570. /*! Slice: WDR_dY6:*/
  9571. /*! Tone curve sample point definition dY6 on the horizontal axis (input)*/
  9572. #define MRV_WDR_DY6
  9573. #define MRV_WDR_DY6_MASK 0x00700000U
  9574. #define MRV_WDR_DY6_SHIFT 20U
  9575. /*! Slice: WDR_dY5:*/
  9576. /*! Tone curve sample point definition dY5 on the horizontal axis (input)*/
  9577. #define MRV_WDR_DY5
  9578. #define MRV_WDR_DY5_MASK 0x00070000U
  9579. #define MRV_WDR_DY5_SHIFT 16U
  9580. /*! Slice: WDR_dY4:*/
  9581. /*! Tone curve sample point definition dY4 on the horizontal axis (input)*/
  9582. #define MRV_WDR_DY4
  9583. #define MRV_WDR_DY4_MASK 0x00007000U
  9584. #define MRV_WDR_DY4_SHIFT 12U
  9585. /*! Slice: WDR_dY3:*/
  9586. /*! Tone curve sample point definition dY3 on the horizontal axis (input)*/
  9587. #define MRV_WDR_DY3
  9588. #define MRV_WDR_DY3_MASK 0x00000700U
  9589. #define MRV_WDR_DY3_SHIFT 8U
  9590. /*! Slice: WDR_dY2:*/
  9591. /*! Tone curve sample point definition dY2 on the horizontal axis (input)*/
  9592. #define MRV_WDR_DY2
  9593. #define MRV_WDR_DY2_MASK 0x00000070U
  9594. #define MRV_WDR_DY2_SHIFT 4U
  9595. /*! Slice: WDR_dY1:*/
  9596. /*! Tone curve sample point definition dY1 on the horizontal axis (input)*/
  9597. #define MRV_WDR_DY1
  9598. #define MRV_WDR_DY1_MASK 0x00000007U
  9599. #define MRV_WDR_DY1_SHIFT 0U
  9600. /*! Register: isp_wdr_tonecurve_2: Tone Curve sample points dYn definition (part 2) (0x00000008)*/
  9601. /*! Slice: WDR_dY16:*/
  9602. /*! Tone curve sample point definition dY16 on the horizontal axis (input)*/
  9603. #define MRV_WDR_DY16
  9604. #define MRV_WDR_DY16_MASK 0x70000000U
  9605. #define MRV_WDR_DY16_SHIFT 28U
  9606. /*! Slice: WDR_dY15:*/
  9607. /*! Tone curve sample point definition dY15 on the horizontal axis (input)*/
  9608. #define MRV_WDR_DY15
  9609. #define MRV_WDR_DY15_MASK 0x07000000U
  9610. #define MRV_WDR_DY15_SHIFT 24U
  9611. /*! Slice: WDR_dY14:*/
  9612. /*! Tone curve sample point definition dY14 on the horizontal axis (input)*/
  9613. #define MRV_WDR_DY14
  9614. #define MRV_WDR_DY14_MASK 0x00700000U
  9615. #define MRV_WDR_DY14_SHIFT 20U
  9616. /*! Slice: WDR_dY13:*/
  9617. /*! Tone curve sample point definition dY13 on the horizontal axis (input)*/
  9618. #define MRV_WDR_DY13
  9619. #define MRV_WDR_DY13_MASK 0x00070000U
  9620. #define MRV_WDR_DY13_SHIFT 16U
  9621. /*! Slice: WDR_dY12:*/
  9622. /*! Tone curve sample point definition dY12 on the horizontal axis (input)*/
  9623. #define MRV_WDR_DY12
  9624. #define MRV_WDR_DY12_MASK 0x00007000U
  9625. #define MRV_WDR_DY12_SHIFT 12U
  9626. /*! Slice: WDR_dY11:*/
  9627. /*! Tone curve sample point definition dY11 on the horizontal axis (input)*/
  9628. #define MRV_WDR_DY11
  9629. #define MRV_WDR_DY11_MASK 0x00000700U
  9630. #define MRV_WDR_DY11_SHIFT 8U
  9631. /*! Slice: WDR_dY10:*/
  9632. /*! Tone curve sample point definition dY10 on the horizontal axis (input)*/
  9633. #define MRV_WDR_DY10
  9634. #define MRV_WDR_DY10_MASK 0x00000070U
  9635. #define MRV_WDR_DY10_SHIFT 4U
  9636. /*! Slice: WDR_dY9:*/
  9637. /*! Tone curve sample point definition dY9 on the horizontal axis (input)*/
  9638. #define MRV_WDR_DY9
  9639. #define MRV_WDR_DY9_MASK 0x00000007U
  9640. #define MRV_WDR_DY9_SHIFT 0U
  9641. /*! Register: isp_wdr_tonecurve_3: Tone Curve sample points dYn definition (part 3) (0x0000000c)*/
  9642. /*! Slice: WDR_dY24:*/
  9643. /*! Tone curve sample point definition dY24 on the horizontal axis (input)*/
  9644. #define MRV_WDR_DY24
  9645. #define MRV_WDR_DY24_MASK 0x70000000U
  9646. #define MRV_WDR_DY24_SHIFT 28U
  9647. /*! Slice: WDR_dY23:*/
  9648. /*! Tone curve sample point definition dY23 on the horizontal axis (input)*/
  9649. #define MRV_WDR_DY23
  9650. #define MRV_WDR_DY23_MASK 0x07000000U
  9651. #define MRV_WDR_DY23_SHIFT 24U
  9652. /*! Slice: WDR_dY22:*/
  9653. /*! Tone curve sample point definition dY22 on the horizontal axis (input)*/
  9654. #define MRV_WDR_DY22
  9655. #define MRV_WDR_DY22_MASK 0x00700000U
  9656. #define MRV_WDR_DY22_SHIFT 20U
  9657. /*! Slice: WDR_dY21:*/
  9658. /*! Tone curve sample point definition dY21 on the horizontal axis (input)*/
  9659. #define MRV_WDR_DY21
  9660. #define MRV_WDR_DY21_MASK 0x00070000U
  9661. #define MRV_WDR_DY21_SHIFT 16U
  9662. /*! Slice: WDR_dY20:*/
  9663. /*! Tone curve sample point definition dY20 on the horizontal axis (input)*/
  9664. #define MRV_WDR_DY20
  9665. #define MRV_WDR_DY20_MASK 0x00007000U
  9666. #define MRV_WDR_DY20_SHIFT 12U
  9667. /*! Slice: WDR_dY19:*/
  9668. /*! Tone curve sample point definition dY19 on the horizontal axis (input)*/
  9669. #define MRV_WDR_DY19
  9670. #define MRV_WDR_DY19_MASK 0x00000700U
  9671. #define MRV_WDR_DY19_SHIFT 8U
  9672. /*! Slice: WDR_dY18:*/
  9673. /*! Tone curve sample point definition dY18 on the horizontal axis (input)*/
  9674. #define MRV_WDR_DY18
  9675. #define MRV_WDR_DY18_MASK 0x00000070U
  9676. #define MRV_WDR_DY18_SHIFT 4U
  9677. /*! Slice: WDR_dY17:*/
  9678. /*! Tone curve sample point definition dY17 on the horizontal axis (input)*/
  9679. #define MRV_WDR_DY17
  9680. #define MRV_WDR_DY17_MASK 0x00000007U
  9681. #define MRV_WDR_DY17_SHIFT 0U
  9682. /*! Register: isp_wdr_tonecurve_4: Tone Curve sample points dYn definition (part 4) (0x00000010)*/
  9683. /*! Slice: WDR_dY32:*/
  9684. /*! Tone curve sample point definition dY32 on the horizontal axis (input)*/
  9685. #define MRV_WDR_DY32
  9686. #define MRV_WDR_DY32_MASK 0x70000000U
  9687. #define MRV_WDR_DY32_SHIFT 28U
  9688. /*! Slice: WDR_dY31:*/
  9689. /*! Tone curve sample point definition dY31 on the horizontal axis (input)*/
  9690. #define MRV_WDR_DY31
  9691. #define MRV_WDR_DY31_MASK 0x07000000U
  9692. #define MRV_WDR_DY31_SHIFT 24U
  9693. /*! Slice: WDR_dY30:*/
  9694. /*! Tone curve sample point definition dY30 on the horizontal axis (input)*/
  9695. #define MRV_WDR_DY30
  9696. #define MRV_WDR_DY30_MASK 0x00700000U
  9697. #define MRV_WDR_DY30_SHIFT 20U
  9698. /*! Slice: WDR_dY29:*/
  9699. /*! Tone curve sample point definition dY29 on the horizontal axis (input)*/
  9700. #define MRV_WDR_DY29
  9701. #define MRV_WDR_DY29_MASK 0x00070000U
  9702. #define MRV_WDR_DY29_SHIFT 16U
  9703. /*! Slice: WDR_dY28:*/
  9704. /*! Tone curve sample point definition dY28 on the horizontal axis (input)*/
  9705. #define MRV_WDR_DY28
  9706. #define MRV_WDR_DY28_MASK 0x00007000U
  9707. #define MRV_WDR_DY28_SHIFT 12U
  9708. /*! Slice: WDR_dY27:*/
  9709. /*! Tone curve sample point definition dY27 on the horizontal axis (input)*/
  9710. #define MRV_WDR_DY27
  9711. #define MRV_WDR_DY27_MASK 0x00000700U
  9712. #define MRV_WDR_DY27_SHIFT 8U
  9713. /*! Slice: WDR_dY26:*/
  9714. /*! Tone curve sample point definition dY26 on the horizontal axis (input)*/
  9715. #define MRV_WDR_DY26
  9716. #define MRV_WDR_DY26_MASK 0x00000070U
  9717. #define MRV_WDR_DY26_SHIFT 4U
  9718. /*! Slice: WDR_dY25:*/
  9719. /*! Tone curve sample point definition dY25 on the horizontal axis (input)*/
  9720. #define MRV_WDR_DY25
  9721. #define MRV_WDR_DY25_MASK 0x00000007U
  9722. #define MRV_WDR_DY25_SHIFT 0U
  9723. /*! Register array: isp_wdr_tonecurve_ym: Tonemapping curve coefficient Ym_ (0x0028 + n*0x4 (n=0..32))*/
  9724. /*! Slice: tonecurve_ym_n:*/
  9725. /* Tone curve value definition y-axis (output) of WDR unit */
  9726. #define MRV_WDR_TONECURVE_YM_N
  9727. #define MRV_WDR_TONECURVE_YM_N_MASK 0x00001FFFU
  9728. #define MRV_WDR_TONECURVE_YM_N_SHIFT 0U
  9729. /*! Register: isp_wdr_offset: Offset values for RGB path (0x00000098)*/
  9730. /*! Slice: LUM_OFFSET:*/
  9731. /*! Luminance Offset value (a) for RGB operation mode */
  9732. /* unsigned 12 bit value */
  9733. #define MRV_WDR_LUM_OFFSET
  9734. #define MRV_WDR_LUM_OFFSET_MASK 0x0FFF0000U
  9735. #define MRV_WDR_LUM_OFFSET_SHIFT 16U
  9736. /*! Slice: RGB_OFFSET:*/
  9737. /*! RGB Offset value (b) for RGB operation mode */
  9738. /* unsigned 12 bit value */
  9739. #define MRV_WDR_RGB_OFFSET
  9740. #define MRV_WDR_RGB_OFFSET_MASK 0x00000FFFU
  9741. #define MRV_WDR_RGB_OFFSET_SHIFT 0U
  9742. /*! Register: isp_wdr_deltamin: DeltaMin Threshold and Strength factor (0x0000009c)*/
  9743. /*! Slice: DMIN_STRENGTH:*/
  9744. /*! strength factor for DMIN */
  9745. /* unsigned 5 bit value, range 0x00...0x10 */
  9746. #define MRV_WDR_DMIN_STRENGTH
  9747. #define MRV_WDR_DMIN_STRENGTH_MASK 0x001F0000U
  9748. #define MRV_WDR_DMIN_STRENGTH_SHIFT 16U
  9749. /*! Slice: DMIN_THRESH:*/
  9750. /*! Lower threshold for deltaMin value */
  9751. /* unsigned 12 bit value */
  9752. #define MRV_WDR_DMIN_THRESH
  9753. #define MRV_WDR_DMIN_THRESH_MASK 0x00000FFFU
  9754. #define MRV_WDR_DMIN_THRESH_SHIFT 0U
  9755. /*! Register: isp_wdr_tonecurve_1_shd: Tone Curve sample points dYn definition shadow register (part 1) (0x000000a0)*/
  9756. /*! Slice: WDR_dY8:*/
  9757. /*! Tone curve sample point definition dY8 on the horizontal axis (input)*/
  9758. #define MRV_WDR_DY8
  9759. #define MRV_WDR_DY8_MASK 0x70000000U
  9760. #define MRV_WDR_DY8_SHIFT 28U
  9761. /*! Slice: WDR_dY7:*/
  9762. /*! Tone curve sample point definition dY7 on the horizontal axis (input)*/
  9763. #define MRV_WDR_DY7
  9764. #define MRV_WDR_DY7_MASK 0x07000000U
  9765. #define MRV_WDR_DY7_SHIFT 24U
  9766. /*! Slice: WDR_dY6:*/
  9767. /*! Tone curve sample point definition dY6 on the horizontal axis (input)*/
  9768. #define MRV_WDR_DY6
  9769. #define MRV_WDR_DY6_MASK 0x00700000U
  9770. #define MRV_WDR_DY6_SHIFT 20U
  9771. /*! Slice: WDR_dY5:*/
  9772. /*! Tone curve sample point definition dY5 on the horizontal axis (input)*/
  9773. #define MRV_WDR_DY5
  9774. #define MRV_WDR_DY5_MASK 0x00070000U
  9775. #define MRV_WDR_DY5_SHIFT 16U
  9776. /*! Slice: WDR_dY4:*/
  9777. /*! Tone curve sample point definition dY4 on the horizontal axis (input)*/
  9778. #define MRV_WDR_DY4
  9779. #define MRV_WDR_DY4_MASK 0x00007000U
  9780. #define MRV_WDR_DY4_SHIFT 12U
  9781. /*! Slice: WDR_dY3:*/
  9782. /*! Tone curve sample point definition dY3 on the horizontal axis (input)*/
  9783. #define MRV_WDR_DY3
  9784. #define MRV_WDR_DY3_MASK 0x00000700U
  9785. #define MRV_WDR_DY3_SHIFT 8U
  9786. /*! Slice: WDR_dY2:*/
  9787. /*! Tone curve sample point definition dY2 on the horizontal axis (input)*/
  9788. #define MRV_WDR_DY2
  9789. #define MRV_WDR_DY2_MASK 0x00000070U
  9790. #define MRV_WDR_DY2_SHIFT 4U
  9791. /*! Slice: WDR_dY1:*/
  9792. /*! Tone curve sample point definition dY1 on the horizontal axis (input)*/
  9793. #define MRV_WDR_DY1
  9794. #define MRV_WDR_DY1_MASK 0x00000007U
  9795. #define MRV_WDR_DY1_SHIFT 0U
  9796. /*! Register: isp_wdr_tonecurve_2_shd: Tone Curve sample points dYn definition shadow register (part 2) (0x000000a4)*/
  9797. /*! Slice: WDR_dY16:*/
  9798. /*! Tone curve sample point definition dY16 on the horizontal axis (input)*/
  9799. #define MRV_WDR_DY16
  9800. #define MRV_WDR_DY16_MASK 0x70000000U
  9801. #define MRV_WDR_DY16_SHIFT 28U
  9802. /*! Slice: WDR_dY15:*/
  9803. /*! Tone curve sample point definition dY15 on the horizontal axis (input)*/
  9804. #define MRV_WDR_DY15
  9805. #define MRV_WDR_DY15_MASK 0x07000000U
  9806. #define MRV_WDR_DY15_SHIFT 24U
  9807. /*! Slice: WDR_dY14:*/
  9808. /*! Tone curve sample point definition dY14 on the horizontal axis (input)*/
  9809. #define MRV_WDR_DY14
  9810. #define MRV_WDR_DY14_MASK 0x00700000U
  9811. #define MRV_WDR_DY14_SHIFT 20U
  9812. /*! Slice: WDR_dY13:*/
  9813. /*! Tone curve sample point definition dY13 on the horizontal axis (input)*/
  9814. #define MRV_WDR_DY13
  9815. #define MRV_WDR_DY13_MASK 0x00070000U
  9816. #define MRV_WDR_DY13_SHIFT 16U
  9817. /*! Slice: WDR_dY12:*/
  9818. /*! Tone curve sample point definition dY12 on the horizontal axis (input)*/
  9819. #define MRV_WDR_DY12
  9820. #define MRV_WDR_DY12_MASK 0x00007000U
  9821. #define MRV_WDR_DY12_SHIFT 12U
  9822. /*! Slice: WDR_dY11:*/
  9823. /*! Tone curve sample point definition dY11 on the horizontal axis (input)*/
  9824. #define MRV_WDR_DY11
  9825. #define MRV_WDR_DY11_MASK 0x00000700U
  9826. #define MRV_WDR_DY11_SHIFT 8U
  9827. /*! Slice: WDR_dY10:*/
  9828. /*! Tone curve sample point definition dY10 on the horizontal axis (input)*/
  9829. #define MRV_WDR_DY10
  9830. #define MRV_WDR_DY10_MASK 0x00000070U
  9831. #define MRV_WDR_DY10_SHIFT 4U
  9832. /*! Slice: WDR_dY9:*/
  9833. /*! Tone curve sample point definition dY9 on the horizontal axis (input)*/
  9834. #define MRV_WDR_DY9
  9835. #define MRV_WDR_DY9_MASK 0x00000007U
  9836. #define MRV_WDR_DY9_SHIFT 0U
  9837. /*! Register: isp_wdr_tonecurve_3_shd: Tone Curve sample points dYn definition shadow register (part 3) (0x000000a8)*/
  9838. /*! Slice: WDR_dY24:*/
  9839. /*! Tone curve sample point definition dY24 on the horizontal axis (input)*/
  9840. #define MRV_WDR_DY24
  9841. #define MRV_WDR_DY24_MASK 0x70000000U
  9842. #define MRV_WDR_DY24_SHIFT 28U
  9843. /*! Slice: WDR_dY23:*/
  9844. /*! Tone curve sample point definition dY23 on the horizontal axis (input)*/
  9845. #define MRV_WDR_DY23
  9846. #define MRV_WDR_DY23_MASK 0x07000000U
  9847. #define MRV_WDR_DY23_SHIFT 24U
  9848. /*! Slice: WDR_dY22:*/
  9849. /*! Tone curve sample point definition dY22 on the horizontal axis (input)*/
  9850. #define MRV_WDR_DY22
  9851. #define MRV_WDR_DY22_MASK 0x00700000U
  9852. #define MRV_WDR_DY22_SHIFT 20U
  9853. /*! Slice: WDR_dY21:*/
  9854. /*! Tone curve sample point definition dY21 on the horizontal axis (input)*/
  9855. #define MRV_WDR_DY21
  9856. #define MRV_WDR_DY21_MASK 0x00070000U
  9857. #define MRV_WDR_DY21_SHIFT 16U
  9858. /*! Slice: WDR_dY20:*/
  9859. /*! Tone curve sample point definition dY20 on the horizontal axis (input)*/
  9860. #define MRV_WDR_DY20
  9861. #define MRV_WDR_DY20_MASK 0x00007000U
  9862. #define MRV_WDR_DY20_SHIFT 12U
  9863. /*! Slice: WDR_dY19:*/
  9864. /*! Tone curve sample point definition dY19 on the horizontal axis (input)*/
  9865. #define MRV_WDR_DY19
  9866. #define MRV_WDR_DY19_MASK 0x00000700U
  9867. #define MRV_WDR_DY19_SHIFT 8U
  9868. /*! Slice: WDR_dY18:*/
  9869. /*! Tone curve sample point definition dY18 on the horizontal axis (input)*/
  9870. #define MRV_WDR_DY18
  9871. #define MRV_WDR_DY18_MASK 0x00000070U
  9872. #define MRV_WDR_DY18_SHIFT 4U
  9873. /*! Slice: WDR_dY17:*/
  9874. /*! Tone curve sample point definition dY17 on the horizontal axis (input)*/
  9875. #define MRV_WDR_DY17
  9876. #define MRV_WDR_DY17_MASK 0x00000007U
  9877. #define MRV_WDR_DY17_SHIFT 0U
  9878. /*! Register: isp_wdr_tonecurve_4_shd: Tone Curve sample points dYn definition shadow register(part 4) (0x000000ac)*/
  9879. /*! Slice: WDR_dY32:*/
  9880. /*! Tone curve sample point definition dY32 on the horizontal axis (input)*/
  9881. #define MRV_WDR_DY32
  9882. #define MRV_WDR_DY32_MASK 0x70000000U
  9883. #define MRV_WDR_DY32_SHIFT 28U
  9884. /*! Slice: WDR_dY31:*/
  9885. /*! Tone curve sample point definition dY31 on the horizontal axis (input)*/
  9886. #define MRV_WDR_DY31
  9887. #define MRV_WDR_DY31_MASK 0x07000000U
  9888. #define MRV_WDR_DY31_SHIFT 24U
  9889. /*! Slice: WDR_dY30:*/
  9890. /*! Tone curve sample point definition dY30 on the horizontal axis (input)*/
  9891. #define MRV_WDR_DY30
  9892. #define MRV_WDR_DY30_MASK 0x00700000U
  9893. #define MRV_WDR_DY30_SHIFT 20U
  9894. /*! Slice: WDR_dY29:*/
  9895. /*! Tone curve sample point definition dY29 on the horizontal axis (input)*/
  9896. #define MRV_WDR_DY29
  9897. #define MRV_WDR_DY29_MASK 0x00070000U
  9898. #define MRV_WDR_DY29_SHIFT 16U
  9899. /*! Slice: WDR_dY28:*/
  9900. /*! Tone curve sample point definition dY28 on the horizontal axis (input)*/
  9901. #define MRV_WDR_DY28
  9902. #define MRV_WDR_DY28_MASK 0x00007000U
  9903. #define MRV_WDR_DY28_SHIFT 12U
  9904. /*! Slice: WDR_dY27:*/
  9905. /*! Tone curve sample point definition dY27 on the horizontal axis (input)*/
  9906. #define MRV_WDR_DY27
  9907. #define MRV_WDR_DY27_MASK 0x00000700U
  9908. #define MRV_WDR_DY27_SHIFT 8U
  9909. /*! Slice: WDR_dY26:*/
  9910. /*! Tone curve sample point definition dY26 on the horizontal axis (input)*/
  9911. #define MRV_WDR_DY26
  9912. #define MRV_WDR_DY26_MASK 0x00000070U
  9913. #define MRV_WDR_DY26_SHIFT 4U
  9914. /*! Slice: WDR_dY25:*/
  9915. /*! Tone curve sample point definition dY25 on the horizontal axis (input)*/
  9916. #define MRV_WDR_DY25
  9917. #define MRV_WDR_DY25_MASK 0x00000007U
  9918. #define MRV_WDR_DY25_SHIFT 0U
  9919. /*! Register array: isp_wdr_tonecurve_ym_shd: Tonemapping curve coefficient shadow register (0x0160 + n*0x4 (n=0..32))*/
  9920. /*! Slice: tonecurve_ym_n_shd:*/
  9921. /* Tone curve value definition y-axis (output) of WDR unit */
  9922. /* shadow register.*/
  9923. #define MRV_WDR_TONECURVE_YM_N_SHD
  9924. #define MRV_WDR_TONECURVE_YM_N_SHD_MASK 0x00001FFFU
  9925. #define MRV_WDR_TONECURVE_YM_N_SHD_SHIFT 0U
  9926. /*! Register: awb_meas_mode: AWB Measure Mode (0x00000000)*/
  9927. /*! Slice: AWB_union_e5_and_e8:*/
  9928. /*! unite ellipse 5 with ellipse 8. Accu and count for ellipse 8.*/
  9929. #define ISP_AWB_UNION_E5_AND_E8
  9930. #define ISP_AWB_UNION_E5_AND_E8_MASK 0x00000200U
  9931. #define ISP_AWB_UNION_E5_AND_E8_SHIFT 9U
  9932. /*! Slice: AWB_union_e5_and_e7:*/
  9933. /*! unite ellipse 5 with ellipse 7. Accu and count for ellipse 7.*/
  9934. #define ISP_AWB_UNION_E5_AND_E7
  9935. #define ISP_AWB_UNION_E5_AND_E7_MASK 0x00000100U
  9936. #define ISP_AWB_UNION_E5_AND_E7_SHIFT 8U
  9937. /*! Slice: AWB_union_e5_and_e6:*/
  9938. /*! unite ellipse 5 with ellipse 6. Accu and count for ellipse 6.*/
  9939. #define ISP_AWB_UNION_E5_AND_E6
  9940. #define ISP_AWB_UNION_E5_AND_E6_MASK 0x00000080U
  9941. #define ISP_AWB_UNION_E5_AND_E6_SHIFT 7U
  9942. /*! Slice: AWB_union_e1_and_e4:*/
  9943. /*! unite ellipse 1 with ellipse 4. Accu and count for ellipse 4.*/
  9944. #define ISP_AWB_UNION_E1_AND_E4
  9945. #define ISP_AWB_UNION_E1_AND_E4_MASK 0x00000040U
  9946. #define ISP_AWB_UNION_E1_AND_E4_SHIFT 6U
  9947. /*! Slice: AWB_union_e1_and_e3:*/
  9948. /*! unite ellipse 1 with ellipse 3. Accu and count for ellipse 3.*/
  9949. #define ISP_AWB_UNION_E1_AND_E3
  9950. #define ISP_AWB_UNION_E1_AND_E3_MASK 0x00000020U
  9951. #define ISP_AWB_UNION_E1_AND_E3_SHIFT 5U
  9952. /*! Slice: AWB_union_e1_and_e2:*/
  9953. /*! unite ellipse 1 with ellipse 2. Accu and count for ellipse 2.*/
  9954. #define ISP_AWB_UNION_E1_AND_E2
  9955. #define ISP_AWB_UNION_E1_AND_E2_MASK 0x00000010U
  9956. #define ISP_AWB_UNION_E1_AND_E2_SHIFT 4U
  9957. /*! Slice: AWB_meas_chrom_switch:*/
  9958. /*! Accumulates Q1 and Q2 chromaticies instead of R, G, B color signals. Results are written on AWB_ACCU registers as well.*/
  9959. #define ISP_AWB_MEAS_CHROM_SWITCH
  9960. #define ISP_AWB_MEAS_CHROM_SWITCH_MASK 0x00000008U
  9961. #define ISP_AWB_MEAS_CHROM_SWITCH_SHIFT 3U
  9962. /*! Slice: AWB_meas_irq_enable:*/
  9963. /*! AWB measure done IRQ enable.*/
  9964. #define ISP_AWB_MEAS_IRQ_ENABLE
  9965. #define ISP_AWB_MEAS_IRQ_ENABLE_MASK 0x00000004U
  9966. #define ISP_AWB_MEAS_IRQ_ENABLE_SHIFT 2U
  9967. /*! Slice: AWB_pre_filt_en:*/
  9968. /*! median pre filter enable.*/
  9969. #define ISP_AWB_PRE_FILT_EN
  9970. #define ISP_AWB_PRE_FILT_EN_MASK 0x00000002U
  9971. #define ISP_AWB_PRE_FILT_EN_SHIFT 1U
  9972. /*! Slice: AWB_meas_en:*/
  9973. /*! enable measure.*/
  9974. #define ISP_AWB_MEAS_EN
  9975. #define ISP_AWB_MEAS_EN_MASK 0x00000001U
  9976. #define ISP_AWB_MEAS_EN_SHIFT 0U
  9977. /*! Register: awb_meas_h_offs: AWB window horizontal offset (0x00000004)*/
  9978. /*! Slice: AWB_h_offset:*/
  9979. /*! Horizontal offset in pixels.*/
  9980. #define ISP_AWB_H_OFFSET
  9981. #define ISP_AWB_H_OFFSET_MASK 0x00001FFFU
  9982. #define ISP_AWB_H_OFFSET_SHIFT 0U
  9983. /*! Register: awb_meas_v_offs: AWB window vertical offset (0x00000008)*/
  9984. /*! Slice: AWB_v_offset:*/
  9985. /*! Vertical offset in pixels.*/
  9986. #define ISP_AWB_V_OFFSET
  9987. #define ISP_AWB_V_OFFSET_MASK 0x00001FFFU
  9988. #define ISP_AWB_V_OFFSET_SHIFT 0U
  9989. /*! Register: awb_meas_h_size: Horizontal window size (0x0000000c)*/
  9990. /*! Slice: AWB_h_size:*/
  9991. /*! Horizontal size in pixels.*/
  9992. #define ISP_AWB_H_SIZE
  9993. #define ISP_AWB_H_SIZE_MASK 0x00003FFFU
  9994. #define ISP_AWB_H_SIZE_SHIFT 0U
  9995. /*! Register: awb_meas_v_size: Vertical window size (0x00000010)*/
  9996. /*! Slice: AWB_v_size:*/
  9997. /*! Vertical size.*/
  9998. #define ISP_AWB_V_SIZE
  9999. #define ISP_AWB_V_SIZE_MASK 0x00003FFFU
  10000. #define ISP_AWB_V_SIZE_SHIFT 0U
  10001. /*! Register: awb_meas_r_min_max: Min Max Compare Red (0x00000014)*/
  10002. /*! Slice: r_max:*/
  10003. /*! max red value */
  10004. #define ISP_AWB_R_MAX
  10005. #define ISP_AWB_R_MAX_MASK 0x0000FF00U
  10006. #define ISP_AWB_R_MAX_SHIFT 8U
  10007. /*! Slice: r_min:*/
  10008. /*! min red value */
  10009. #define ISP_AWB_R_MIN
  10010. #define ISP_AWB_R_MIN_MASK 0x000000FFU
  10011. #define ISP_AWB_R_MIN_SHIFT 0U
  10012. /*! Register: awb_meas_g_min_max: Min Max Compare Green (0x00000018)*/
  10013. /*! Slice: g_max:*/
  10014. /*! max green value */
  10015. #define ISP_AWB_G_MAX
  10016. #define ISP_AWB_G_MAX_MASK 0x0000FF00U
  10017. #define ISP_AWB_G_MAX_SHIFT 8U
  10018. /*! Slice: g_min:*/
  10019. /*! min green value */
  10020. #define ISP_AWB_G_MIN
  10021. #define ISP_AWB_G_MIN_MASK 0x000000FFU
  10022. #define ISP_AWB_G_MIN_SHIFT 0U
  10023. /*! Register: awb_meas_b_min_max: Min Max Compare Blue (0x0000001c)*/
  10024. /*! Slice: b_max:*/
  10025. /*! max blue value */
  10026. #define ISP_AWB_B_MAX
  10027. #define ISP_AWB_B_MAX_MASK 0x0000FF00U
  10028. #define ISP_AWB_B_MAX_SHIFT 8U
  10029. /*! Slice: b_min:*/
  10030. /*! min blue value */
  10031. #define ISP_AWB_B_MIN
  10032. #define ISP_AWB_B_MIN_MASK 0x000000FFU
  10033. #define ISP_AWB_B_MIN_SHIFT 0U
  10034. /*! Register: awb_meas_divider_min: Min Compare Divider (0x00000020)*/
  10035. /*! Slice: div_min:*/
  10036. /*! min divider value unsigned integer with 10 fractional Bits range 0 to 0.999 */
  10037. #define ISP_AWB_DIV_MIN
  10038. #define ISP_AWB_DIV_MIN_MASK 0x000003FFU
  10039. #define ISP_AWB_DIV_MIN_SHIFT 0U
  10040. /*! Register: awb_meas_csc_coeff_0: Color conversion coefficient 0 (0x00000024)*/
  10041. /*! Slice: cc_coeff_0:*/
  10042. /*! coefficient 0 for color space conversion */
  10043. #define ISP_AWB_CC_COEFF_0
  10044. #define ISP_AWB_CC_COEFF_0_MASK 0x000007FFU
  10045. #define ISP_AWB_CC_COEFF_0_SHIFT 0U
  10046. /*! Register: awb_meas_ellip1_cen_x: Ellipse 1 Center X (0x00000048)*/
  10047. /*! Slice: ellip1_cen_x:*/
  10048. /*! Ellipse 1 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
  10049. #define ISP_AWB_ELLIP1_CEN_X
  10050. #define ISP_AWB_ELLIP1_CEN_X_MASK 0x000003FFU
  10051. #define ISP_AWB_ELLIP1_CEN_X_SHIFT 0U
  10052. /*! Register: awb_meas_ellip1_cen_y: Ellipse 1 Center Y (0x0000004c)*/
  10053. /*! Slice: ellip1_cen_y:*/
  10054. /*! Ellipse 1 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
  10055. #define ISP_AWB_ELLIP1_CEN_Y
  10056. #define ISP_AWB_ELLIP1_CEN_Y_MASK 0x000003FFU
  10057. #define ISP_AWB_ELLIP1_CEN_Y_SHIFT 0U
  10058. /*! Register: awb_meas_ellip1_a1: Ellipse 1 coefficient a1 (0x00000088)*/
  10059. /*! Slice: ellip1_a1:*/
  10060. /*! Ellipse 1 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  10061. #define ISP_AWB_ELLIP1_A1
  10062. #define ISP_AWB_ELLIP1_A1_MASK 0x00000FFFU
  10063. #define ISP_AWB_ELLIP1_A1_SHIFT 0U
  10064. /*! Register: awb_meas_ellip1_a2: Ellipse 1 coefficient a2 (0x0000008c)*/
  10065. /*! Slice: ellip1_a2:*/
  10066. /*! Ellipse 1 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  10067. #define ISP_AWB_ELLIP1_A2
  10068. #define ISP_AWB_ELLIP1_A2_MASK 0x000001FFU
  10069. #define ISP_AWB_ELLIP1_A2_SHIFT 0U
  10070. /*! Register: awb_meas_ellip1_a3: Ellipse 1 coefficient a3 (0x00000090)*/
  10071. /*! Slice: ellip1_a3:*/
  10072. /*! Ellipse 1 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  10073. #define ISP_AWB_ELLIP1_A3
  10074. #define ISP_AWB_ELLIP1_A3_MASK 0x00000FFFU
  10075. #define ISP_AWB_ELLIP1_A3_SHIFT 0U
  10076. /*! Register: awb_meas_ellip1_a4: Ellipse 1 coefficient a4 (0x00000094)*/
  10077. /*! Slice: ellip1_a4:*/
  10078. /*! Ellipse 1 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  10079. #define ISP_AWB_ELLIP1_A4
  10080. #define ISP_AWB_ELLIP1_A4_MASK 0x000001FFU
  10081. #define ISP_AWB_ELLIP1_A4_SHIFT 0U
  10082. /*! Register: awb_meas_ellip1_rmax: Ellipse 1 r_max (0x00000108)*/
  10083. /*! Slice: ellip1_rmax:*/
  10084. /*! Ellipse 1 max radius square compare value */
  10085. #define ISP_AWB_ELLIP1_RMAX
  10086. #define ISP_AWB_ELLIP1_RMAX_MASK 0x00FFFFFFU
  10087. #define ISP_AWB_ELLIP1_RMAX_SHIFT 0U
  10088. /*! Register: awb_meas_counter_1: AWB Counter 1 (0x00000128)*/
  10089. /*! Slice: count_1:*/
  10090. /*! counted Pixels of Ellipse 1 */
  10091. #define ISP_AWB_COUNT_1
  10092. #define ISP_AWB_COUNT_1_MASK 0x00FFFFFFU
  10093. #define ISP_AWB_COUNT_1_SHIFT 0U
  10094. /*! Register array: awb_meas_accu: AWB Accu Read (0x290 + n*0x4 (n=0..23))*/
  10095. /*! Slice: read_accu:*/
  10096. /* measured sum[34:3] of RGB values.*/
  10097. #define ISP_AWB_READ_ACCU
  10098. #define ISP_AWB_READ_ACCU_MASK 0xFFFFFFFFU
  10099. #define ISP_AWB_READ_ACCU_SHIFT 0U
  10100. /*! Register: isp64_hist_ctrl: Histogram control (0x00000000)*/
  10101. /*! Slice: hist_update_enable:*/
  10102. /*! 0: automatic register update at end of measuement ot frame denied */
  10103. /* 1: automatic register update at end of measuement ot frame enabled.*/
  10104. #define MRV_HIST_UPDATE_ENABLE
  10105. #define MRV_HIST_UPDATE_ENABLE_MASK 0x00000001U
  10106. #define MRV_HIST_UPDATE_ENABLE_SHIFT 0U
  10107. /*! Register: isp64_hist_prop: Histogram properties (0x00000004)*/
  10108. /*! Slice: channel_select:*/
  10109. /*! select 1 out of max. 8 input channels */
  10110. /* 7: channel 7 */
  10111. /* 6: channel 6 */
  10112. /* 5: channel 5 */
  10113. /* 4: channel 4 */
  10114. /* 3: channel 3 */
  10115. /* 2: channel 2 */
  10116. /* 1: channel 1 */
  10117. /* 0: channel 0 */
  10118. /* The channels might be RGB or Bayer channels. Each channel provides 3 subchannels for tranfer the RGB component data. However if the channel operates in bayer mode only subchannel 0 is used transferring the interleaved bayer pattern data. Check with top level specification to discover the channel type.*/
  10119. #define MRV_HIST_CHANNEL_SELECT
  10120. #define MRV_HIST_CHANNEL_SELECT_MASK 0x00000038U
  10121. #define MRV_HIST_CHANNEL_SELECT_SHIFT 3U
  10122. /*! Slice: hist_mode:*/
  10123. /*! histogram mode (RGB/Bayer)*/
  10124. /* 7, 6: reserved */
  10125. /* 5: bayer Gb histogram */
  10126. /* 4: bayer B histogram */
  10127. /* 3: bayer Gr histogram */
  10128. /* 2: bayer R histogram */
  10129. /* 1: Y/R/G/B histogram controlled via coefficients coeff_r/g/b */
  10130. /* 0: disable, no measurements */
  10131. /* With histogram mode 1 all three subchannels are used. Modes 2...5 use only th subchannel 0 which transfers the bayer pattern data. Check with top level specification to discover the channel type.*/
  10132. #define MRV_HIST_MODE
  10133. #define MRV_HIST_MODE_MASK 0x00000007U
  10134. #define MRV_HIST_MODE_SHIFT 0U
  10135. /*! Register: isp64_hist_subsampling: Subsampling properties (0x00000008)*/
  10136. /*! Slice: v_stepsize:*/
  10137. /*! histogram veritcal predivider, process every (stepsize)th line, all other lines are skipped */
  10138. /* RGB mode:*/
  10139. /* 0: not allowed */
  10140. /* 1: process every input line */
  10141. /* 2: process every second line */
  10142. /* 3: process every third input line */
  10143. /* 4: process every fourth input line */
  10144. /* ...*/
  10145. /* 7FH: process every 127th line */
  10146. /* Bayer mode:*/
  10147. /* 0: not allowed */
  10148. /* 1: process every second input line */
  10149. /* 2: process every fourth line */
  10150. /* 3: process every sixth input line */
  10151. /* 4: process every eighth input line */
  10152. /* ...*/
  10153. /* 7FH: process every 254th line */
  10154. /* In bayer mode vertical subsampling will start at the 1st input line which contain the bayer component selected in ISP64_HIST_PROP::hist_mode.*/
  10155. #define MRV_HIST_V_STEPSIZE
  10156. #define MRV_HIST_V_STEPSIZE_MASK 0x7F000000U
  10157. #define MRV_HIST_V_STEPSIZE_SHIFT 24U
  10158. /*! Slice: h_step_inc:*/
  10159. /*! horizontal subsampling step counter increment.*/
  10160. /* In RGB mode the subsampling counter cnt is incremented by h_step_inc with every input pixel (cnt %= cnt + h_step_inc). A valid subsampling position is reached when cnt would result in a value %= 2^16. In this case the new counter value is cnt = cnt + h_step_inc - 2^16. For example if every incoming pixel shall be selected configure h_step_inc = 2^16.*/
  10161. /* In Bayer mode the behaviour is similar but for the fact that cnt is only incremented for pixels which belong to the bayer component selected in ISP64_HIST_PROP::hist_mode.*/
  10162. #define MRV_HIST_H_STEP_INC
  10163. #define MRV_HIST_H_STEP_INC_MASK 0x0001FFFFU
  10164. #define MRV_HIST_H_STEP_INC_SHIFT 0U
  10165. /*! Register: isp64_hist_coeff_r: Color conversion coefficient for red (0x0000000c)*/
  10166. /*! Slice: coeff_r:*/
  10167. /*! coefficient for red for weighted component sum: out_sample = coeff_r * red + coeff_g*green + coeff_b * blue.*/
  10168. #define MRV_HIST_COEFF_R
  10169. #define MRV_HIST_COEFF_R_MASK 0x000000FFU
  10170. #define MRV_HIST_COEFF_R_SHIFT 0U
  10171. /*! Register: isp64_hist_coeff_g: Color conversion coefficient for green (0x00000010)*/
  10172. /*! Slice: coeff_g:*/
  10173. /*! coefficient for green for weighted component sum: out_sample = coeff_r * red + coeff_g*green + coeff_b * blue.*/
  10174. #define MRV_HIST_COEFF_G
  10175. #define MRV_HIST_COEFF_G_MASK 0x000000FFU
  10176. #define MRV_HIST_COEFF_G_SHIFT 0U
  10177. /*! Register: isp64_hist_coeff_b: Color conversion coefficient for blue (0x00000014)*/
  10178. /*! Slice: coeff_b:*/
  10179. /*! coefficient for blue for weighted component sum: out_sample = coeff_r * red + coeff_g*green + coeff_b * blue.*/
  10180. #define MRV_HIST_COEFF_B
  10181. #define MRV_HIST_COEFF_B_MASK 0x000000FFU
  10182. #define MRV_HIST_COEFF_B_SHIFT 0U
  10183. /*! Register: isp64_hist_h_offs: Histogram window horizontal offset for first window of 25 sub-windows (0x00000018)*/
  10184. /*! Slice: hist_h_offset:*/
  10185. /*! Horizontal offset of first window in pixels.*/
  10186. #define MRV_HIST_H_OFFSET
  10187. #define MRV_HIST_H_OFFSET_MASK 0x00001FFFU
  10188. #define MRV_HIST_H_OFFSET_SHIFT 0U
  10189. /*! Register: isp64_hist_v_offs: Histogram window vertical offset for first window of 25 sub-windows (0x0000001c)*/
  10190. /*! Slice: hist_v_offset:*/
  10191. /*! Vertical offset of first window in pixels.*/
  10192. #define MRV_HIST_V_OFFSET
  10193. #define MRV_HIST_V_OFFSET_MASK 0x00001FFFU
  10194. #define MRV_HIST_V_OFFSET_SHIFT 0U
  10195. /*! Register: isp64_hist_h_size: Horizontal (sub-)window size (0x00000020)*/
  10196. /*! Slice: hist_h_size:*/
  10197. /*! Horizontal size in pixels of one sub-window.*/
  10198. #define MRV_HIST_H_SIZE
  10199. #define MRV_HIST_H_SIZE_MASK 0x000007FFU
  10200. #define MRV_HIST_H_SIZE_SHIFT 0U
  10201. /*! Register: isp64_hist_v_size: Vertical (sub-)window size (0x00000024)*/
  10202. /*! Slice: hist_v_size:*/
  10203. /*! Vertical size in lines of one sub-window.*/
  10204. #define MRV_HIST_V_SIZE
  10205. #define MRV_HIST_V_SIZE_MASK 0x000007FFU
  10206. #define MRV_HIST_V_SIZE_SHIFT 0U
  10207. /*! Register: isp64_hist_sample_range: Weighting factor for sub-windows (0x00000028)*/
  10208. /*! Slice: sample_shift:*/
  10209. /*! sample (left) shift will be executed after offset subtraction and prior to histogram evaluation */
  10210. #define MRV_HIST_SAMPLE_SHIFT
  10211. #define MRV_HIST_SAMPLE_SHIFT_MASK 0x00070000U
  10212. #define MRV_HIST_SAMPLE_SHIFT_SHIFT 16U
  10213. /*! Slice: sample_offset:*/
  10214. /*! sample offset will be subtracted from input sample prior to shift and histogram evaluation */
  10215. #define MRV_HIST_SAMPLE_OFFSET
  10216. #define MRV_HIST_SAMPLE_OFFSET_MASK 0x00000FFFU
  10217. #define MRV_HIST_SAMPLE_OFFSET_SHIFT 0U
  10218. /*! Register: isp64_hist_weight_00to30: Weighting factor for sub-windows (0x0000002c)*/
  10219. /*! Slice: hist_weight_30:*/
  10220. /*! weighting factor for sub-window 30 */
  10221. #define MRV_HIST_WEIGHT_30
  10222. #define MRV_HIST_WEIGHT_30_MASK 0x1F000000U
  10223. #define MRV_HIST_WEIGHT_30_SHIFT 24U
  10224. /*! Slice: hist_weight_20:*/
  10225. /*! weighting factor for sub-window 20 */
  10226. #define MRV_HIST_WEIGHT_20
  10227. #define MRV_HIST_WEIGHT_20_MASK 0x001F0000U
  10228. #define MRV_HIST_WEIGHT_20_SHIFT 16U
  10229. /*! Slice: hist_weight_10:*/
  10230. /*! weighting factor for sub-window 10 */
  10231. #define MRV_HIST_WEIGHT_10
  10232. #define MRV_HIST_WEIGHT_10_MASK 0x00001F00U
  10233. #define MRV_HIST_WEIGHT_10_SHIFT 8U
  10234. /*! Slice: hist_weight_00:*/
  10235. /*! weighting factor for sub-window 00 */
  10236. #define MRV_HIST_WEIGHT_00
  10237. #define MRV_HIST_WEIGHT_00_MASK 0x0000001FU
  10238. #define MRV_HIST_WEIGHT_00_SHIFT 0U
  10239. /*! Register: isp64_hist_weight_40to21: Weighting factor for sub-windows (0x00000030)*/
  10240. /*! Slice: hist_weight_21:*/
  10241. /*! weighting factor for sub-window 21 */
  10242. #define MRV_HIST_WEIGHT_21
  10243. #define MRV_HIST_WEIGHT_21_MASK 0x1F000000U
  10244. #define MRV_HIST_WEIGHT_21_SHIFT 24U
  10245. /*! Slice: hist_weight_11:*/
  10246. /*! weighting factor for sub-window 11 */
  10247. #define MRV_HIST_WEIGHT_11
  10248. #define MRV_HIST_WEIGHT_11_MASK 0x001F0000U
  10249. #define MRV_HIST_WEIGHT_11_SHIFT 16U
  10250. /*! Slice: hist_weight_01:*/
  10251. /*! weighting factor for sub-window 01 */
  10252. #define MRV_HIST_WEIGHT_01
  10253. #define MRV_HIST_WEIGHT_01_MASK 0x00001F00U
  10254. #define MRV_HIST_WEIGHT_01_SHIFT 8U
  10255. /*! Slice: hist_weight_40:*/
  10256. /*! weighting factor for sub-window 40 */
  10257. #define MRV_HIST_WEIGHT_40
  10258. #define MRV_HIST_WEIGHT_40_MASK 0x0000001FU
  10259. #define MRV_HIST_WEIGHT_40_SHIFT 0U
  10260. /*! Register: isp64_hist_weight_31to12: Weighting factor for sub-windows (0x00000034)*/
  10261. /*! Slice: hist_weight_12:*/
  10262. /*! weighting factor for sub-window 12 */
  10263. #define MRV_HIST_WEIGHT_12
  10264. #define MRV_HIST_WEIGHT_12_MASK 0x1F000000U
  10265. #define MRV_HIST_WEIGHT_12_SHIFT 24U
  10266. /*! Slice: hist_weight_02:*/
  10267. /*! weighting factor for sub-window 02 */
  10268. #define MRV_HIST_WEIGHT_02
  10269. #define MRV_HIST_WEIGHT_02_MASK 0x001F0000U
  10270. #define MRV_HIST_WEIGHT_02_SHIFT 16U
  10271. /*! Slice: hist_weight_41:*/
  10272. /*! weighting factor for sub-window 41 */
  10273. #define MRV_HIST_WEIGHT_41
  10274. #define MRV_HIST_WEIGHT_41_MASK 0x00001F00U
  10275. #define MRV_HIST_WEIGHT_41_SHIFT 8U
  10276. /*! Slice: hist_weight_31:*/
  10277. /*! weighting factor for sub-window 31 */
  10278. #define MRV_HIST_WEIGHT_31
  10279. #define MRV_HIST_WEIGHT_31_MASK 0x0000001FU
  10280. #define MRV_HIST_WEIGHT_31_SHIFT 0U
  10281. /*! Register: isp64_hist_weight_22to03: Weighting factor for sub-windows (0x00000038)*/
  10282. /*! Slice: hist_weight_03:*/
  10283. /*! weighting factor for sub-window 03 */
  10284. #define MRV_HIST_WEIGHT_03
  10285. #define MRV_HIST_WEIGHT_03_MASK 0x1F000000U
  10286. #define MRV_HIST_WEIGHT_03_SHIFT 24U
  10287. /*! Slice: hist_weight_42:*/
  10288. /*! weighting factor for sub-window 42 */
  10289. #define MRV_HIST_WEIGHT_42
  10290. #define MRV_HIST_WEIGHT_42_MASK 0x001F0000U
  10291. #define MRV_HIST_WEIGHT_42_SHIFT 16U
  10292. /*! Slice: hist_weight_32:*/
  10293. /*! weighting factor for sub-window 32 */
  10294. #define MRV_HIST_WEIGHT_32
  10295. #define MRV_HIST_WEIGHT_32_MASK 0x00001F00U
  10296. #define MRV_HIST_WEIGHT_32_SHIFT 8U
  10297. /*! Slice: hist_weight_22:*/
  10298. /*! weighting factor for sub-window 22 */
  10299. #define MRV_HIST_WEIGHT_22
  10300. #define MRV_HIST_WEIGHT_22_MASK 0x0000001FU
  10301. #define MRV_HIST_WEIGHT_22_SHIFT 0U
  10302. /*! Register: isp64_hist_weight_13to43: Weighting factor for sub-windows (0x0000003c)*/
  10303. /*! Slice: hist_weight_43:*/
  10304. /*! weighting factor for sub-window 43 */
  10305. #define MRV_HIST_WEIGHT_43
  10306. #define MRV_HIST_WEIGHT_43_MASK 0x1F000000U
  10307. #define MRV_HIST_WEIGHT_43_SHIFT 24U
  10308. /*! Slice: hist_weight_33:*/
  10309. /*! weighting factor for sub-window 33 */
  10310. #define MRV_HIST_WEIGHT_33
  10311. #define MRV_HIST_WEIGHT_33_MASK 0x001F0000U
  10312. #define MRV_HIST_WEIGHT_33_SHIFT 16U
  10313. /*! Slice: hist_weight_23:*/
  10314. /*! weighting factor for sub-window 23 */
  10315. #define MRV_HIST_WEIGHT_23
  10316. #define MRV_HIST_WEIGHT_23_MASK 0x00001F00U
  10317. #define MRV_HIST_WEIGHT_23_SHIFT 8U
  10318. /*! Slice: hist_weight_13:*/
  10319. /*! weighting factor for sub-window 13 */
  10320. #define MRV_HIST_WEIGHT_13
  10321. #define MRV_HIST_WEIGHT_13_MASK 0x0000001FU
  10322. #define MRV_HIST_WEIGHT_13_SHIFT 0U
  10323. /*! Register: isp64_hist_weight_04to34: Weighting factor for sub-windows (0x00000040)*/
  10324. /*! Slice: hist_weight_34:*/
  10325. /*! weighting factor for sub-window 34 */
  10326. #define MRV_HIST_WEIGHT_34
  10327. #define MRV_HIST_WEIGHT_34_MASK 0x1F000000U
  10328. #define MRV_HIST_WEIGHT_34_SHIFT 24U
  10329. /*! Slice: hist_weight_24:*/
  10330. /*! weighting factor for sub-window 24 */
  10331. #define MRV_HIST_WEIGHT_24
  10332. #define MRV_HIST_WEIGHT_24_MASK 0x001F0000U
  10333. #define MRV_HIST_WEIGHT_24_SHIFT 16U
  10334. /*! Slice: hist_weight_14:*/
  10335. /*! weighting factor for sub-window 14 */
  10336. #define MRV_HIST_WEIGHT_14
  10337. #define MRV_HIST_WEIGHT_14_MASK 0x00001F00U
  10338. #define MRV_HIST_WEIGHT_14_SHIFT 8U
  10339. /*! Slice: hist_weight_04:*/
  10340. /*! weighting factor for sub-window 04 */
  10341. #define MRV_HIST_WEIGHT_04
  10342. #define MRV_HIST_WEIGHT_04_MASK 0x0000001FU
  10343. #define MRV_HIST_WEIGHT_04_SHIFT 0U
  10344. /*! Register: isp64_hist_weight_44: Weighting factor for sub-windows (0x00000044)*/
  10345. /*! Slice: hist_weight_44:*/
  10346. /*! weighting factor for sub-window 44 */
  10347. #define MRV_HIST_WEIGHT_44
  10348. #define MRV_HIST_WEIGHT_44_MASK 0x0000001FU
  10349. #define MRV_HIST_WEIGHT_44_SHIFT 0U
  10350. /*! Register: isp64_hist_forced_upd_start_line: Forced update start line limit (0x00000048)*/
  10351. /*! Slice: forced_upd_start_line:*/
  10352. /*! start line for histogram calculation in case of forced update. histogram is started as soon as current line < forced_upd_start_line. Used start line will be given in ISP64_HIST_VSTART_STATUS.*/
  10353. #define MRV_HIST_FORCED_UPD_START_LINE
  10354. #define MRV_HIST_FORCED_UPD_START_LINE_MASK 0x00001FFFU
  10355. #define MRV_HIST_FORCED_UPD_START_LINE_SHIFT 0U
  10356. /*! Register: isp64_hist_forced_update: Histogram forced update (0x0000004c)*/
  10357. /*! Slice: forced_upd:*/
  10358. /*! 0: no effect */
  10359. /* 1: forcing register update.*/
  10360. #define MRV_HIST_FORCED_UPD
  10361. #define MRV_HIST_FORCED_UPD_MASK 0x00000001U
  10362. #define MRV_HIST_FORCED_UPD_SHIFT 0U
  10363. /*! Register: isp64_hist_vstart_status: Forced update start line status (0x00000050)*/
  10364. /*! Slice: hist_vstart_status:*/
  10365. /*! start line for histogram. Important in case of backward switching because 1st histogram after switch might not cover the complete image.*/
  10366. #define MRV_HIST_VSTART_STATUS
  10367. #define MRV_HIST_VSTART_STATUS_MASK 0x00001FFFU
  10368. #define MRV_HIST_VSTART_STATUS_SHIFT 0U
  10369. /*! Register array: isp64_hist_bin: histogram measurement result bin (0x0A8 + n*0x4 (n=0..31))*/
  10370. /*! Slice: hist_bin:*/
  10371. /* measured bin count as 16-bit unsigned integer value plus 4 bit fractional part */
  10372. #define MRV_HIST_BIN
  10373. #define MRV_HIST_BIN_MASK 0x000FFFFFU
  10374. #define MRV_HIST_BIN_SHIFT 0U
  10375. /*! Register: isp_vsm_mode: VS Measure Mode (0x00000000)*/
  10376. /*! Slice: vsm_meas_irq_enable:*/
  10377. /*! 1: VS measure done IRQ enable.*/
  10378. #define ISP_VSM_MEAS_IRQ_ENABLE
  10379. #define ISP_VSM_MEAS_IRQ_ENABLE_MASK 0x00000002U
  10380. #define ISP_VSM_MEAS_IRQ_ENABLE_SHIFT 1U
  10381. /*! Slice: vsm_meas_en:*/
  10382. /*! 1: enable measure.*/
  10383. #define ISP_VSM_MEAS_EN
  10384. #define ISP_VSM_MEAS_EN_MASK 0x00000001U
  10385. #define ISP_VSM_MEAS_EN_SHIFT 0U
  10386. /*! Register: isp_vsm_h_offs: VSM window horizontal offset (0x00000004)*/
  10387. /*! Slice: vsm_h_offset:*/
  10388. /*! Horizontal offset in pixels.*/
  10389. #define ISP_VSM_H_OFFSET
  10390. #define ISP_VSM_H_OFFSET_MASK 0x00001FFFU
  10391. #define ISP_VSM_H_OFFSET_SHIFT 0U
  10392. /*! Register: isp_vsm_v_offs: VSM window vertical offset (0x00000008)*/
  10393. /*! Slice: vsm_v_offset:*/
  10394. /*! Vertical offset in pixels.*/
  10395. #define ISP_VSM_V_OFFSET
  10396. #define ISP_VSM_V_OFFSET_MASK 0x00001FFFU
  10397. #define ISP_VSM_V_OFFSET_SHIFT 0U
  10398. /*! Register: isp_vsm_h_size: Horizontal measure window size (0x0000000c)*/
  10399. /*! Slice: vsm_h_size:*/
  10400. /*! Horizontal size in pixels. Range 64..1920 */
  10401. #define ISP_VSM_H_SIZE
  10402. #define ISP_VSM_H_SIZE_MASK 0x00000780U
  10403. #define ISP_VSM_H_SIZE_SHIFT 1U
  10404. /*! Register: isp_vsm_v_size: Vertical measure window size (0x00000010)*/
  10405. /*! Slice: vsm_v_size:*/
  10406. /*! Vertical size. Range 64..1088 */
  10407. #define ISP_VSM_V_SIZE
  10408. #define ISP_VSM_V_SIZE_MASK 0x00000440U
  10409. #define ISP_VSM_V_SIZE_SHIFT 1U
  10410. /*! Register: isp_vsm_h_segments: Iteration 1 horizontal segments (0x00000014)*/
  10411. /*! Slice: vsm_h_segments:*/
  10412. /*! number of 16 point wide segments enclosed by the first iteration sample points in horizontal direction. Range: 1 ... 128 */
  10413. #define ISP_VSM_H_SEGMENTS
  10414. #define ISP_VSM_H_SEGMENTS_MASK 0x000000FFU
  10415. #define ISP_VSM_H_SEGMENTS_SHIFT 0U
  10416. /*! Register: isp_vsm_v_segments: Iteration 1 vertical segments (0x00000018)*/
  10417. /*! Slice: vsm_v_segments:*/
  10418. /*! number of 16 point wide segments enclosed by the first iteration sample points in vertical direction. Range: 1 ... 128 */
  10419. #define ISP_VSM_V_SEGMENTS
  10420. #define ISP_VSM_V_SEGMENTS_MASK 0x000000FFU
  10421. #define ISP_VSM_V_SEGMENTS_SHIFT 0U
  10422. /*! Register: isp_vsm_delta_h: estimated horizontal displacement (0x0000001c)*/
  10423. /*! Slice: delta_h:*/
  10424. /*! estimated horizontal displacement 12Bit two's complement. positive values indicate a displacement of the image from right to left (camera turns right)*/
  10425. #define ISP_VSM_DELTA_H
  10426. #define ISP_VSM_DELTA_H_MASK 0x00000FFFU
  10427. #define ISP_VSM_DELTA_H_SHIFT 0U
  10428. /*! Register: isp_vsm_delta_v: estimated vertical displacement (0x00000020)*/
  10429. /*! Slice: delta_v:*/
  10430. /*! estimated vertical displacement 12Bit two's complement. positive values indicate a displacement of the image from bottom to top (camera turns down)*/
  10431. #define ISP_VSM_DELTA_V
  10432. #define ISP_VSM_DELTA_V_MASK 0x00000FFFU
  10433. #define ISP_VSM_DELTA_V_SHIFT 0U
  10434. #ifdef ISP_RGBGC
  10435. /*! Register: isp_ctrl:isp control register (0x00000400)*/
  10436. /*! Slice: rgb_gc_enable */
  10437. /*! Control of rgb gamma correction */
  10438. /*! 1'b0: disable rgb GC bypass mode */
  10439. /*! 1'b1: enable rgb GC mode */
  10440. #define ISP_RGBGC_ENABLE
  10441. #define ISP_RGBGC_ENABLE_MASK 0x00000800U
  10442. #define ISP_RGBGC_ENABLE_SHIFT 11U
  10443. #endif
  10444. #ifdef ISP_GCMONO
  10445. /*! Register: isp_ctrl:isp control register (0x00000400)*/
  10446. /*! Slice: mono_gc_enable */
  10447. /*! Control of gamma correction for mono sensor RAW data */
  10448. /*! 1'b0: disable GC bypass mode */
  10449. /*! 1'b1: enable GC mode */
  10450. #define ISP_GCMONO_ENABLE
  10451. #define ISP_GCMONO_ENABLE_MASK 0x00080000U
  10452. #define ISP_GCMONO_ENABLE_SHIFT 19U
  10453. /*! Register: isp_ctrl:isp control register (0x00000400)*/
  10454. /*! Slice: mono_gc_mode */
  10455. /*! Control of gamma correction for mono sensor RAW data mode */
  10456. /*! 1'b0: 0: 10->8 */
  10457. /*! 1'b1: 12->10 */
  10458. #define ISP_GCMONO_MODE
  10459. #define ISP_GCMONO_MODE_MASK 0x00100000U
  10460. #define ISP_GCMONO_MODE_SHIFT 20
  10461. /*! Register: isp_gcmono_ctrl: GC Mono control register (0x00000000)*/
  10462. /*! Slice: mono_gc_enable */
  10463. /*! Control of gamma correction for mono sensor RAW data */
  10464. /*! 1'b0: disable GC bypass mode */
  10465. /*! 1'b1: enable GC mode */
  10466. #define ISP_GCMONO_SWITCH
  10467. #define ISP_GCMONO_SWITCH_MASK 0x00000001U
  10468. #define ISP_GCMONO_SWITCH_SHIFT 0U
  10469. /*! Slice: mono_gc_cfg_done */
  10470. /*! To notify the ISP HW the LUT configuration is done, ready to use, active high.*/
  10471. /*! Writing ZERO reset teh internal read/write pointer and also indicates that the LUT can be configured or read from CPU.*/
  10472. #define ISP_GCMONO_CFG_DONE
  10473. #define ISP_GCMONO_CFG_DONE_MASK 0x00000002U
  10474. #define ISP_GCMONO_CFG_DONE_SHIFT 1U
  10475. /*! Register: isp_gcmono_para_base: GC Mono Gamma LUT for mono sensor (0x00000004)*/
  10476. /*! Slice: Base address of Gamma LUT for mono sensor, when AHB slave writes/reads this register address continuously, it means it will start to */
  10477. /*! write or read the LUT.*/
  10478. #define ISP_GCMONO_PARA_BASE
  10479. #define ISP_GCMONO_PARA_BASE_MASK 0xFFFFFFFFU
  10480. #define ISP_GCMONO_PARA_BASE_SHIFT 0U
  10481. #endif
  10482. /*! Register: isp_wdr2_ctrl (0x00003100)*/
  10483. /*! Slice: wdr2_soft_reset_flag:*/
  10484. #define WDR2_SOFT_RESET_FLAG
  10485. #define WDR2_SOFT_RESET_FLAG_MASK 0x00000004U
  10486. #define WDR2_SOFT_RESET_FLAG_SHIFT 2U
  10487. /*! Slice: wdr2_mono_input:*/
  10488. #define WDR2_MONO_INPUT
  10489. #define WDR2_MONO_INPUT_MASK 0x00000002U
  10490. #define WDR2_MONO_INPUT_SHIFT 1U
  10491. /*! Slice: wdr2_enable:*/
  10492. #define WDR2_ENABLE
  10493. #define WDR2_ENABLE_MASK 0x00000001U
  10494. #define WDR2_ENABLE_SHIFT 0U
  10495. /*! Register: isp_wdr2_blk_siz (0x00003104)*/
  10496. /*! Slice: hist_block_width:*/
  10497. #define HIST_BLOCK_WIDTH
  10498. #define HIST_BLOCK_WIDTH_MASK 0x000FFC00U
  10499. #define HIST_BLOCK_WIDTH_SHIFT 10U
  10500. /*! Slice: hist_block_height:*/
  10501. #define HIST_BLOCK_HEIGHT
  10502. #define HIST_BLOCK_HEIGHT_MASK 0x000003FFU
  10503. #define HIST_BLOCK_HEIGHT_SHIFT 0U
  10504. /*! Register: isp_wdr2_color_weight (0x00003108)*/
  10505. /*! Slice: wdr2_color_weight_2:*/
  10506. #define WDR2_COLOR_WEIGHT_2
  10507. #define WDR2_COLOR_WEIGHT_2_MASK 0x00FF0000U
  10508. #define WDR2_COLOR_WEIGHT_2_SHIFT 16U
  10509. /*! Slice: wdr2_color_weight_1:*/
  10510. #define WDR2_COLOR_WEIGHT_1
  10511. #define WDR2_COLOR_WEIGHT_1_MASK 0x0000FF00U
  10512. #define WDR2_COLOR_WEIGHT_1_SHIFT 8U
  10513. /*! Slice: wdr2_color_weight_0:*/
  10514. #define WDR2_COLOR_WEIGHT_0
  10515. #define WDR2_COLOR_WEIGHT_0_MASK 0x000000FFU
  10516. #define WDR2_COLOR_WEIGHT_0_SHIFT 0U
  10517. /*! Register: isp_wdr2_blt_sigma (0x0000310C)*/
  10518. /*! Slice: wdr2_blt_range_sigma:*/
  10519. #define WDR2_BLT_RANGE_SIGMA
  10520. #define WDR2_BLT_RANGE_SIGMA_MASK 0x000FFC00U
  10521. #define WDR2_BLT_RANGE_SIGMA_SHIFT 10U
  10522. /*! Slice: wdr2_blt_spatial_sigma:*/
  10523. #define WDR2_BLT_SPATIAL_SIGMA
  10524. #define WDR2_BLT_SPATIAL_SIGMA_MASK 0x000003FFU
  10525. #define WDR2_BLT_SPATIAL_SIGMA_SHIFT 0U
  10526. /*! Register: isp_wdr2_blt_kernel_0 (0x00003110)*/
  10527. /*! Slice: wdr2_blt_kernel_c:*/
  10528. #define WDR2_BLT_KERNEL_C
  10529. #define WDR2_BLT_KERNEL_C_MASK 0x00FF0000U
  10530. #define WDR2_BLT_KERNEL_C_SHIFT 16U
  10531. /*! Slice: wdr2_blt_kernel_b:*/
  10532. #define WDR2_BLT_KERNEL_B
  10533. #define WDR2_BLT_KERNEL_B_MASK 0x0000FF00U
  10534. #define WDR2_BLT_KERNEL_B_SHIFT 8U
  10535. /*! Slice: wdr2_blt_kernel_a:*/
  10536. #define WDR2_BLT_KERNEL_A
  10537. #define WDR2_BLT_KERNEL_A_MASK 0x000000FFU
  10538. #define WDR2_BLT_KERNEL_A_SHIFT 0U
  10539. /*! Register: isp_wdr2_blt_kernel_1 (0x00003114)*/
  10540. /*! Slice: wdr2_blt_kernel_f:*/
  10541. #define WDR2_BLT_KERNEL_F
  10542. #define WDR2_BLT_KERNEL_F_MASK 0x00FF0000U
  10543. #define WDR2_BLT_KERNEL_F_SHIFT 16U
  10544. /*! Slice: wdr2_blt_kernel_e:*/
  10545. #define WDR2_BLT_KERNEL_E
  10546. #define WDR2_BLT_KERNEL_E_MASK 0x0000FF00U
  10547. #define WDR2_BLT_KERNEL_E_SHIFT 8U
  10548. /*! Slice: wdr2_blt_kernel_d:*/
  10549. #define WDR2_BLT_KERNEL_D
  10550. #define WDR2_BLT_KERNEL_D_MASK 0x000000FFU
  10551. #define WDR2_BLT_KERNEL_D_SHIFT 0U
  10552. /*! Register: isp_wdr2_vol_shift_bit (0x00003118)*/
  10553. /*! Slice: wdr2_vol_shift_bit:*/
  10554. #define WDR2_VOL_SHIFT_BIT
  10555. #define WDR2_VOL_SHIFT_BIT_MASK 0x0000001FU
  10556. #define WDR2_VOL_SHIFT_BIT_SHIFT 0U
  10557. /*! Register: isp_wdr2_bin_dist_0 (0x0000311C)*/
  10558. /*! Slice: wdr2_bin_dist_1:*/
  10559. #define WDR2_BIN_DIST_1
  10560. #define WDR2_BIN_DIST_1_MASK 0x0FFF0000U
  10561. #define WDR2_BIN_DIST_1_SHIFT 16U
  10562. /*! Slice: wdr2_bin_dist_0:*/
  10563. #define WDR2_BIN_DIST_0
  10564. #define WDR2_BIN_DIST_0_MASK 0x00000FFFU
  10565. #define WDR2_BIN_DIST_0_SHIFT 0U
  10566. /*! Register: isp_wdr2_bin_dist_1 (0x00003120)*/
  10567. /*! Slice: wdr2_bin_dist_3:*/
  10568. #define WDR2_BIN_DIST_3
  10569. #define WDR2_BIN_DIST_3_MASK 0x0FFF0000U
  10570. #define WDR2_BIN_DIST_3_SHIFT 16U
  10571. /*! Slice: wdr2_bin_dist_2:*/
  10572. #define WDR2_BIN_DIST_2
  10573. #define WDR2_BIN_DIST_2_MASK 0x00000FFFU
  10574. #define WDR2_BIN_DIST_2_SHIFT 0U
  10575. /*! Register: isp_wdr2_bin_dist_2 (0x00003124)*/
  10576. /*! Slice: wdr2_bin_dist_5:*/
  10577. #define WDR2_BIN_DIST_5
  10578. #define WDR2_BIN_DIST_5_MASK 0x0FFF0000U
  10579. #define WDR2_BIN_DIST_5_SHIFT 16U
  10580. /*! Slice: wdr2_bin_dist_4:*/
  10581. #define WDR2_BIN_DIST_4
  10582. #define WDR2_BIN_DIST_4_MASK 0x00000FFFU
  10583. #define WDR2_BIN_DIST_4_SHIFT 0U
  10584. /*! Register: isp_wdr2_bin_dist_3 (0x00003128)*/
  10585. /*! Slice: wdr2_bin_dist_7:*/
  10586. #define WDR2_BIN_DIST_7
  10587. #define WDR2_BIN_DIST_7_MASK 0x0FFF0000U
  10588. #define WDR2_BIN_DIST_7_SHIFT 16U
  10589. /*! Slice: wdr2_bin_dist_6:*/
  10590. #define WDR2_BIN_DIST_6
  10591. #define WDR2_BIN_DIST_6_MASK 0x00000FFFU
  10592. #define WDR2_BIN_DIST_6_SHIFT 0U
  10593. /*! Register: isp_wdr2_hist_norm_fac (0x0000312C)*/
  10594. /*! Slice: wdr2_hist_norm_shift_bit:*/
  10595. #define WDR2_HIST_NORM_SHIFT_BIT
  10596. #define WDR2_HIST_NORM_SHIFT_BIT_MASK 0x0FFF0000U
  10597. #define WDR2_HIST_NORM_SHIFT_BIT_SHIFT 16U
  10598. /*! Slice: wdr2_hist_norm_mul:*/
  10599. #define WDR2_HIST_NORM_MUL
  10600. #define WDR2_HIST_NORM_MUL_MASK 0x00000FFFU
  10601. #define WDR2_HIST_NORM_MUL_SHIFT 0U
  10602. /*! Register: isp_wdr2_pre_gamma_lut (0x00003138)*/
  10603. /*! Slice: wdr2_pre_gamma_lut:*/
  10604. #define WDR2_PRE_GAMMA_LUT
  10605. #define WDR2_PRE_GAMMA_LUT_MASK 0xFFFFFFFFU
  10606. #define WDR2_PRE_GAMMA_LUT_SHIFT 0U
  10607. /*! Register: isp_wdr2_pre_gamma_write_data (0x0000313C)*/
  10608. /*! Slice: wdr2_pre_gamma_write_data:*/
  10609. #define WDR2_PRE_GAMMA_WRITE_DATA
  10610. #define WDR2_PRE_GAMMA_WRITE_DATA_MASK 0x00000FFFU
  10611. #define WDR2_PRE_GAMMA_WRITE_DATA_SHIFT 0U
  10612. /*! Register: isp_wdr2_tone_curve_lut (0x00003140)*/
  10613. /*! Slice: wdr2_tone_curve_lut:*/
  10614. #define WDR2_TONE_CURVE_LUT
  10615. #define WDR2_TONE_CURVE_LUT_MASK 0xFFFFFFFFU
  10616. #define WDR2_TONE_CURVE_LUT_SHIFT 0U
  10617. /*! Register: isp_wdr2_tone_curve_write_data (0x00003144)*/
  10618. /*! Slice: wdr2_tone_curve_write_data:*/
  10619. #define WDR2_TONE_CURVE_WRITE_DATA
  10620. #define WDR2_TONE_CURVE_WRITE_DATA_MASK 0x00000FFFU
  10621. #define WDR2_TONE_CURVE_WRITE_DATA_SHIFT 0U
  10622. /*! Register: isp_wdr2_merge_coeff_lut (0x00003148)*/
  10623. /*! Slice: wdr2_merge_coeff_lut:*/
  10624. #define WDR2_MERGE_COEFF_LUT
  10625. #define WDR2_MERGE_COEFF_LUT_MASK 0xFFFFFFFFU
  10626. #define WDR2_MERGE_COEFF_LUT_SHIFT 0U
  10627. /*! Register: isp_wdr2_merge_coeff_write_data (0x0000314C)*/
  10628. /*! Slice: wdr2_merge_coeff_write_data:*/
  10629. #define WDR2_MERGE_COEFF_WRITE_DATA
  10630. #define WDR2_MERGE_COEFF_WRITE_DATA_MASK 0x000000FFU
  10631. #define WDR2_MERGE_COEFF_WRITE_DATA_SHIFT 0U
  10632. /*! Register: isp_wdr2_pre_gamma_cx_0 (0x00003150)*/
  10633. /*! Slice: wdr2_pre_gamma_cx_5:*/
  10634. #define WDR2_PRE_GAMMA_CX_5
  10635. #define WDR2_PRE_GAMMA_CX_5_MASK 0x3E000000U
  10636. #define WDR2_PRE_GAMMA_CX_5_SHIFT 25U
  10637. /*! Slice: wdr2_pre_gamma_cx_4:*/
  10638. #define WDR2_PRE_GAMMA_CX_4
  10639. #define WDR2_PRE_GAMMA_CX_4_MASK 0x01F00000U
  10640. #define WDR2_PRE_GAMMA_CX_4_SHIFT 20U
  10641. /*! Slice: wdr2_pre_gamma_cx_3:*/
  10642. #define WDR2_PRE_GAMMA_CX_3
  10643. #define WDR2_PRE_GAMMA_CX_3_MASK 0x000F8000U
  10644. #define WDR2_PRE_GAMMA_CX_3_SHIFT 15U
  10645. /*! Slice: wdr2_pre_gamma_cx_2:*/
  10646. #define WDR2_PRE_GAMMA_CX_2
  10647. #define WDR2_PRE_GAMMA_CX_2_MASK 0x00007C00U
  10648. #define WDR2_PRE_GAMMA_CX_2_SHIFT 10U
  10649. /*! Slice: wdr2_pre_gamma_cx_1:*/
  10650. #define WDR2_PRE_GAMMA_CX_1
  10651. #define WDR2_PRE_GAMMA_CX_1_MASK 0x000003E0U
  10652. #define WDR2_PRE_GAMMA_CX_1_SHIFT 5U
  10653. /*! Slice: wdr2_pre_gamma_cx_0:*/
  10654. #define WDR2_PRE_GAMMA_CX_0
  10655. #define WDR2_PRE_GAMMA_CX_0_MASK 0x0000001FU
  10656. #define WDR2_PRE_GAMMA_CX_0_SHIFT 0U
  10657. /*! Register: isp_wdr2_pre_gamma_cx_1 (0x00003154)*/
  10658. /*! Slice: wdr2_pre_gamma_cx_11:*/
  10659. #define WDR2_PRE_GAMMA_CX_11
  10660. #define WDR2_PRE_GAMMA_CX_11_MASK 0x3E000000U
  10661. #define WDR2_PRE_GAMMA_CX_11_SHIFT 25U
  10662. /*! Slice: wdr2_pre_gamma_cx_10:*/
  10663. #define WDR2_PRE_GAMMA_CX_10
  10664. #define WDR2_PRE_GAMMA_CX_10_MASK 0x01F00000U
  10665. #define WDR2_PRE_GAMMA_CX_10_SHIFT 20U
  10666. /*! Slice: wdr2_pre_gamma_cx_9:*/
  10667. #define WDR2_PRE_GAMMA_CX_9
  10668. #define WDR2_PRE_GAMMA_CX_9_MASK 0x000F8000U
  10669. #define WDR2_PRE_GAMMA_CX_9_SHIFT 15U
  10670. /*! Slice: wdr2_pre_gamma_cx_8:*/
  10671. #define WDR2_PRE_GAMMA_CX_8
  10672. #define WDR2_PRE_GAMMA_CX_8_MASK 0x00007C00U
  10673. #define WDR2_PRE_GAMMA_CX_8_SHIFT 10U
  10674. /*! Slice: wdr2_pre_gamma_cx_7:*/
  10675. #define WDR2_PRE_GAMMA_CX_7
  10676. #define WDR2_PRE_GAMMA_CX_7_MASK 0x000003E0U
  10677. #define WDR2_PRE_GAMMA_CX_7_SHIFT 5U
  10678. /*! Slice: wdr2_pre_gamma_cx_6:*/
  10679. #define WDR2_PRE_GAMMA_CX_6
  10680. #define WDR2_PRE_GAMMA_CX_6_MASK 0x0000001FU
  10681. #define WDR2_PRE_GAMMA_CX_6_SHIFT 0U
  10682. /*! Register: isp_wdr2_pre_gamma_cx_2 (0x00003158)*/
  10683. /*! Slice: wdr2_pre_gamma_cx_17:*/
  10684. #define WDR2_PRE_GAMMA_CX_17
  10685. #define WDR2_PRE_GAMMA_CX_17_MASK 0x3E000000U
  10686. #define WDR2_PRE_GAMMA_CX_17_SHIFT 25U
  10687. /*! Slice: wdr2_pre_gamma_cx_16:*/
  10688. #define WDR2_PRE_GAMMA_CX_16
  10689. #define WDR2_PRE_GAMMA_CX_16_MASK 0x01F00000U
  10690. #define WDR2_PRE_GAMMA_CX_16_SHIFT 20U
  10691. /*! Slice: wdr2_pre_gamma_cx_15:*/
  10692. #define WDR2_PRE_GAMMA_CX_15
  10693. #define WDR2_PRE_GAMMA_CX_15_MASK 0x000F8000U
  10694. #define WDR2_PRE_GAMMA_CX_15_SHIFT 15U
  10695. /*! Slice: wdr2_pre_gamma_cx_14:*/
  10696. #define WDR2_PRE_GAMMA_CX_14
  10697. #define WDR2_PRE_GAMMA_CX_14_MASK 0x00007C00U
  10698. #define WDR2_PRE_GAMMA_CX_14_SHIFT 10U
  10699. /*! Slice: wdr2_pre_gamma_cx_13:*/
  10700. #define WDR2_PRE_GAMMA_CX_13
  10701. #define WDR2_PRE_GAMMA_CX_13_MASK 0x000003E0U
  10702. #define WDR2_PRE_GAMMA_CX_13_SHIFT 5U
  10703. /*! Slice: wdr2_pre_gamma_cx_12:*/
  10704. #define WDR2_PRE_GAMMA_CX_12
  10705. #define WDR2_PRE_GAMMA_CX_12_MASK 0x0000001FU
  10706. #define WDR2_PRE_GAMMA_CX_12_SHIFT 0U
  10707. /*! Register: isp_wdr2_pre_gamma_cx_3 (0x0000315C)*/
  10708. /*! Slice: wdr2_pre_gamma_cx_23:*/
  10709. #define WDR2_PRE_GAMMA_CX_23
  10710. #define WDR2_PRE_GAMMA_CX_23_MASK 0x3E000000U
  10711. #define WDR2_PRE_GAMMA_CX_23_SHIFT 25U
  10712. /*! Slice: wdr2_pre_gamma_cx_22:*/
  10713. #define WDR2_PRE_GAMMA_CX_22
  10714. #define WDR2_PRE_GAMMA_CX_22_MASK 0x01F00000U
  10715. #define WDR2_PRE_GAMMA_CX_22_SHIFT 20U
  10716. /*! Slice: wdr2_pre_gamma_cx_21:*/
  10717. #define WDR2_PRE_GAMMA_CX_21
  10718. #define WDR2_PRE_GAMMA_CX_21_MASK 0x000F8000U
  10719. #define WDR2_PRE_GAMMA_CX_21_SHIFT 15U
  10720. /*! Slice: wdr2_pre_gamma_cx_20:*/
  10721. #define WDR2_PRE_GAMMA_CX_20
  10722. #define WDR2_PRE_GAMMA_CX_20_MASK 0x00007C00U
  10723. #define WDR2_PRE_GAMMA_CX_20_SHIFT 10U
  10724. /*! Slice: wdr2_pre_gamma_cx_19:*/
  10725. #define WDR2_PRE_GAMMA_CX_19
  10726. #define WDR2_PRE_GAMMA_CX_19_MASK 0x000003E0U
  10727. #define WDR2_PRE_GAMMA_CX_19_SHIFT 5U
  10728. /*! Slice: wdr2_pre_gamma_cx_18:*/
  10729. #define WDR2_PRE_GAMMA_CX_18
  10730. #define WDR2_PRE_GAMMA_CX_18_MASK 0x0000001FU
  10731. #define WDR2_PRE_GAMMA_CX_18_SHIFT 0U
  10732. /*! Register: isp_wdr2_pre_gamma_cx_4 (0x00003160)*/
  10733. /*! Slice: wdr2_pre_gamma_cx_29:*/
  10734. #define WDR2_PRE_GAMMA_CX_29
  10735. #define WDR2_PRE_GAMMA_CX_29_MASK 0x3E000000U
  10736. #define WDR2_PRE_GAMMA_CX_29_SHIFT 25U
  10737. /*! Slice: wdr2_pre_gamma_cx_28:*/
  10738. #define WDR2_PRE_GAMMA_CX_28
  10739. #define WDR2_PRE_GAMMA_CX_28_MASK 0x01F00000U
  10740. #define WDR2_PRE_GAMMA_CX_28_SHIFT 20U
  10741. /*! Slice: wdr2_pre_gamma_cx_27:*/
  10742. #define WDR2_PRE_GAMMA_CX_27
  10743. #define WDR2_PRE_GAMMA_CX_27_MASK 0x000F8000U
  10744. #define WDR2_PRE_GAMMA_CX_27_SHIFT 15U
  10745. /*! Slice: wdr2_pre_gamma_cx_26:*/
  10746. #define WDR2_PRE_GAMMA_CX_26
  10747. #define WDR2_PRE_GAMMA_CX_26_MASK 0x00007C00U
  10748. #define WDR2_PRE_GAMMA_CX_26_SHIFT 10U
  10749. /*! Slice: wdr2_pre_gamma_cx_25:*/
  10750. #define WDR2_PRE_GAMMA_CX_25
  10751. #define WDR2_PRE_GAMMA_CX_25_MASK 0x000003E0U
  10752. #define WDR2_PRE_GAMMA_CX_25_SHIFT 5U
  10753. /*! Slice: wdr2_pre_gamma_cx_24:*/
  10754. #define WDR2_PRE_GAMMA_CX_24
  10755. #define WDR2_PRE_GAMMA_CX_24_MASK 0x0000001FU
  10756. #define WDR2_PRE_GAMMA_CX_24_SHIFT 0U
  10757. /*! Register: isp_wdr2_pre_gamma_cx_5 (0x00003164)*/
  10758. /*! Slice: wdr2_pre_gamma_cx_35:*/
  10759. #define WDR2_PRE_GAMMA_CX_35
  10760. #define WDR2_PRE_GAMMA_CX_35_MASK 0x3E000000U
  10761. #define WDR2_PRE_GAMMA_CX_35_SHIFT 25U
  10762. /*! Slice: wdr2_pre_gamma_cx_34:*/
  10763. #define WDR2_PRE_GAMMA_CX_34
  10764. #define WDR2_PRE_GAMMA_CX_34_MASK 0x01F00000U
  10765. #define WDR2_PRE_GAMMA_CX_34_SHIFT 20U
  10766. /*! Slice: wdr2_pre_gamma_cx_33:*/
  10767. #define WDR2_PRE_GAMMA_CX_33
  10768. #define WDR2_PRE_GAMMA_CX_33_MASK 0x000F8000U
  10769. #define WDR2_PRE_GAMMA_CX_33_SHIFT 15U
  10770. /*! Slice: wdr2_pre_gamma_cx_32:*/
  10771. #define WDR2_PRE_GAMMA_CX_32
  10772. #define WDR2_PRE_GAMMA_CX_32_MASK 0x00007C00U
  10773. #define WDR2_PRE_GAMMA_CX_32_SHIFT 10U
  10774. /*! Slice: wdr2_pre_gamma_cx_31:*/
  10775. #define WDR2_PRE_GAMMA_CX_31
  10776. #define WDR2_PRE_GAMMA_CX_31_MASK 0x000003E0U
  10777. #define WDR2_PRE_GAMMA_CX_31_SHIFT 5U
  10778. /*! Slice: wdr2_pre_gamma_cx_30:*/
  10779. #define WDR2_PRE_GAMMA_CX_30
  10780. #define WDR2_PRE_GAMMA_CX_30_MASK 0x0000001FU
  10781. #define WDR2_PRE_GAMMA_CX_30_SHIFT 0U
  10782. /*! Register: isp_wdr2_pre_gamma_cx_6 (0x00003168)*/
  10783. /*! Slice: wdr2_pre_gamma_cx_41:*/
  10784. #define WDR2_PRE_GAMMA_CX_41
  10785. #define WDR2_PRE_GAMMA_CX_41_MASK 0x3E000000U
  10786. #define WDR2_PRE_GAMMA_CX_41_SHIFT 25U
  10787. /*! Slice: wdr2_pre_gamma_cx_40:*/
  10788. #define WDR2_PRE_GAMMA_CX_40
  10789. #define WDR2_PRE_GAMMA_CX_40_MASK 0x01F00000U
  10790. #define WDR2_PRE_GAMMA_CX_40_SHIFT 20U
  10791. /*! Slice: wdr2_pre_gamma_cx_39:*/
  10792. #define WDR2_PRE_GAMMA_CX_39
  10793. #define WDR2_PRE_GAMMA_CX_39_MASK 0x000F8000U
  10794. #define WDR2_PRE_GAMMA_CX_39_SHIFT 15U
  10795. /*! Slice: wdr2_pre_gamma_cx_38:*/
  10796. #define WDR2_PRE_GAMMA_CX_38
  10797. #define WDR2_PRE_GAMMA_CX_38_MASK 0x00007C00U
  10798. #define WDR2_PRE_GAMMA_CX_38_SHIFT 10U
  10799. /*! Slice: wdr2_pre_gamma_cx_37:*/
  10800. #define WDR2_PRE_GAMMA_CX_37
  10801. #define WDR2_PRE_GAMMA_CX_37_MASK 0x000003E0U
  10802. #define WDR2_PRE_GAMMA_CX_37_SHIFT 5U
  10803. /*! Slice: wdr2_pre_gamma_cx_36:*/
  10804. #define WDR2_PRE_GAMMA_CX_36
  10805. #define WDR2_PRE_GAMMA_CX_36_MASK 0x0000001FU
  10806. #define WDR2_PRE_GAMMA_CX_36_SHIFT 0U
  10807. /*! Register: isp_wdr2_pre_gamma_cx_7 (0x0000316C)*/
  10808. /*! Slice: wdr2_pre_gamma_cx_47:*/
  10809. #define WDR2_PRE_GAMMA_CX_47
  10810. #define WDR2_PRE_GAMMA_CX_47_MASK 0x3E000000U
  10811. #define WDR2_PRE_GAMMA_CX_47_SHIFT 25U
  10812. /*! Slice: wdr2_pre_gamma_cx_46:*/
  10813. #define WDR2_PRE_GAMMA_CX_46
  10814. #define WDR2_PRE_GAMMA_CX_46_MASK 0x01F00000U
  10815. #define WDR2_PRE_GAMMA_CX_46_SHIFT 20U
  10816. /*! Slice: wdr2_pre_gamma_cx_45:*/
  10817. #define WDR2_PRE_GAMMA_CX_45
  10818. #define WDR2_PRE_GAMMA_CX_45_MASK 0x000F8000U
  10819. #define WDR2_PRE_GAMMA_CX_45_SHIFT 15U
  10820. /*! Slice: wdr2_pre_gamma_cx_44:*/
  10821. #define WDR2_PRE_GAMMA_CX_44
  10822. #define WDR2_PRE_GAMMA_CX_44_MASK 0x00007C00U
  10823. #define WDR2_PRE_GAMMA_CX_44_SHIFT 10U
  10824. /*! Slice: wdr2_pre_gamma_cx_43:*/
  10825. #define WDR2_PRE_GAMMA_CX_43
  10826. #define WDR2_PRE_GAMMA_CX_43_MASK 0x000003E0U
  10827. #define WDR2_PRE_GAMMA_CX_43_SHIFT 5U
  10828. /*! Slice: wdr2_pre_gamma_cx_42:*/
  10829. #define WDR2_PRE_GAMMA_CX_42
  10830. #define WDR2_PRE_GAMMA_CX_42_MASK 0x0000001FU
  10831. #define WDR2_PRE_GAMMA_CX_42_SHIFT 0U
  10832. /*! Register: isp_wdr2_pre_gamma_cx_8 (0x00003170)*/
  10833. /*! Slice: wdr2_pre_gamma_cx_53:*/
  10834. #define WDR2_PRE_GAMMA_CX_53
  10835. #define WDR2_PRE_GAMMA_CX_53_MASK 0x3E000000U
  10836. #define WDR2_PRE_GAMMA_CX_53_SHIFT 25U
  10837. /*! Slice: wdr2_pre_gamma_cx_52:*/
  10838. #define WDR2_PRE_GAMMA_CX_52
  10839. #define WDR2_PRE_GAMMA_CX_52_MASK 0x01F00000U
  10840. #define WDR2_PRE_GAMMA_CX_52_SHIFT 20U
  10841. /*! Slice: wdr2_pre_gamma_cx_51:*/
  10842. #define WDR2_PRE_GAMMA_CX_51
  10843. #define WDR2_PRE_GAMMA_CX_51_MASK 0x000F8000U
  10844. #define WDR2_PRE_GAMMA_CX_51_SHIFT 15U
  10845. /*! Slice: wdr2_pre_gamma_cx_50:*/
  10846. #define WDR2_PRE_GAMMA_CX_50
  10847. #define WDR2_PRE_GAMMA_CX_50_MASK 0x00007C00U
  10848. #define WDR2_PRE_GAMMA_CX_50_SHIFT 10U
  10849. /*! Slice: wdr2_pre_gamma_cx_49:*/
  10850. #define WDR2_PRE_GAMMA_CX_49
  10851. #define WDR2_PRE_GAMMA_CX_49_MASK 0x000003E0U
  10852. #define WDR2_PRE_GAMMA_CX_49_SHIFT 5U
  10853. /*! Slice: wdr2_pre_gamma_cx_48:*/
  10854. #define WDR2_PRE_GAMMA_CX_48
  10855. #define WDR2_PRE_GAMMA_CX_48_MASK 0x0000001FU
  10856. #define WDR2_PRE_GAMMA_CX_48_SHIFT 0U
  10857. /*! Register: isp_wdr2_pre_gamma_cx_9 (0x00003174)*/
  10858. /*! Slice: wdr2_pre_gamma_cx_59:*/
  10859. #define WDR2_PRE_GAMMA_CX_59
  10860. #define WDR2_PRE_GAMMA_CX_59_MASK 0x3E000000U
  10861. #define WDR2_PRE_GAMMA_CX_59_SHIFT 25U
  10862. /*! Slice: wdr2_pre_gamma_cx_58:*/
  10863. #define WDR2_PRE_GAMMA_CX_58
  10864. #define WDR2_PRE_GAMMA_CX_58_MASK 0x01F00000U
  10865. #define WDR2_PRE_GAMMA_CX_58_SHIFT 20U
  10866. /*! Slice: wdr2_pre_gamma_cx_57:*/
  10867. #define WDR2_PRE_GAMMA_CX_57
  10868. #define WDR2_PRE_GAMMA_CX_57_MASK 0x000F8000U
  10869. #define WDR2_PRE_GAMMA_CX_57_SHIFT 15U
  10870. /*! Slice: wdr2_pre_gamma_cx_56:*/
  10871. #define WDR2_PRE_GAMMA_CX_56
  10872. #define WDR2_PRE_GAMMA_CX_56_MASK 0x00007C00U
  10873. #define WDR2_PRE_GAMMA_CX_56_SHIFT 10U
  10874. /*! Slice: wdr2_pre_gamma_cx_55:*/
  10875. #define WDR2_PRE_GAMMA_CX_55
  10876. #define WDR2_PRE_GAMMA_CX_55_MASK 0x000003E0U
  10877. #define WDR2_PRE_GAMMA_CX_55_SHIFT 5U
  10878. /*! Slice: wdr2_pre_gamma_cx_54:*/
  10879. #define WDR2_PRE_GAMMA_CX_54
  10880. #define WDR2_PRE_GAMMA_CX_54_MASK 0x0000001FU
  10881. #define WDR2_PRE_GAMMA_CX_54_SHIFT 0U
  10882. /*! Register: isp_wdr2_pre_gamma_cx_10 (0x00003178)*/
  10883. /*! Slice: wdr2_pre_gamma_cx_63:*/
  10884. #define WDR2_PRE_GAMMA_CX_63
  10885. #define WDR2_PRE_GAMMA_CX_63_MASK 0x000F8000U
  10886. #define WDR2_PRE_GAMMA_CX_63_SHIFT 15U
  10887. /*! Slice: wdr2_pre_gamma_cx_62:*/
  10888. #define WDR2_PRE_GAMMA_CX_62
  10889. #define WDR2_PRE_GAMMA_CX_62_MASK 0x00007C00U
  10890. #define WDR2_PRE_GAMMA_CX_62_SHIFT 10U
  10891. /*! Slice: wdr2_pre_gamma_cx_61:*/
  10892. #define WDR2_PRE_GAMMA_CX_61
  10893. #define WDR2_PRE_GAMMA_CX_61_MASK 0x000003E0U
  10894. #define WDR2_PRE_GAMMA_CX_61_SHIFT 5U
  10895. /*! Slice: wdr2_pre_gamma_cx_60:*/
  10896. #define WDR2_PRE_GAMMA_CX_60
  10897. #define WDR2_PRE_GAMMA_CX_60_MASK 0x0000001FU
  10898. #define WDR2_PRE_GAMMA_CX_60_SHIFT 0U
  10899. /*! Register: isp_wdr2_tone_curve_cx_0 (0x0000317C)*/
  10900. /*! Slice: wdr2_tone_curve_cx_7:*/
  10901. #define WDR2_TONE_CURVE_CX_7
  10902. #define WDR2_TONE_CURVE_CX_7_MASK 0xF0000000U
  10903. #define WDR2_TONE_CURVE_CX_7_SHIFT 28U
  10904. /*! Slice: wdr2_tone_curve_cx_6:*/
  10905. #define WDR2_TONE_CURVE_CX_6
  10906. #define WDR2_TONE_CURVE_CX_6_MASK 0x0F000000U
  10907. #define WDR2_TONE_CURVE_CX_6_SHIFT 24U
  10908. /*! Slice: wdr2_tone_curve_cx_5:*/
  10909. #define WDR2_TONE_CURVE_CX_5
  10910. #define WDR2_TONE_CURVE_CX_5_MASK 0x00F00000U
  10911. #define WDR2_TONE_CURVE_CX_5_SHIFT 20U
  10912. /*! Slice: wdr2_tone_curve_cx_4:*/
  10913. #define WDR2_TONE_CURVE_CX_4
  10914. #define WDR2_TONE_CURVE_CX_4_MASK 0x000F0000U
  10915. #define WDR2_TONE_CURVE_CX_4_SHIFT 16U
  10916. /*! Slice: wdr2_tone_curve_cx_3:*/
  10917. #define WDR2_TONE_CURVE_CX_3
  10918. #define WDR2_TONE_CURVE_CX_3_MASK 0x0000F000U
  10919. #define WDR2_TONE_CURVE_CX_3_SHIFT 12U
  10920. /*! Slice: wdr2_tone_curve_cx_2:*/
  10921. #define WDR2_TONE_CURVE_CX_2
  10922. #define WDR2_TONE_CURVE_CX_2_MASK 0x00000F00U
  10923. #define WDR2_TONE_CURVE_CX_2_SHIFT 8U
  10924. /*! Slice: wdr2_tone_curve_cx_1:*/
  10925. #define WDR2_TONE_CURVE_CX_1
  10926. #define WDR2_TONE_CURVE_CX_1_MASK 0x000000F0U
  10927. #define WDR2_TONE_CURVE_CX_1_SHIFT 4U
  10928. /*! Slice: wdr2_tone_curve_cx_0:*/
  10929. #define WDR2_TONE_CURVE_CX_0
  10930. #define WDR2_TONE_CURVE_CX_0_MASK 0x0000000FU
  10931. #define WDR2_TONE_CURVE_CX_0_SHIFT 0U
  10932. /*! Register: isp_wdr2_tone_curve_cx_1 (0x00003180)*/
  10933. /*! Slice: wdr2_tone_curve_cx_15:*/
  10934. #define WDR2_TONE_CURVE_CX_15
  10935. #define WDR2_TONE_CURVE_CX_15_MASK 0xF0000000U
  10936. #define WDR2_TONE_CURVE_CX_15_SHIFT 28U
  10937. /*! Slice: wdr2_tone_curve_cx_14:*/
  10938. #define WDR2_TONE_CURVE_CX_14
  10939. #define WDR2_TONE_CURVE_CX_14_MASK 0x0F000000U
  10940. #define WDR2_TONE_CURVE_CX_14_SHIFT 24U
  10941. /*! Slice: wdr2_tone_curve_cx_13:*/
  10942. #define WDR2_TONE_CURVE_CX_13
  10943. #define WDR2_TONE_CURVE_CX_13_MASK 0x00F00000U
  10944. #define WDR2_TONE_CURVE_CX_13_SHIFT 20U
  10945. /*! Slice: wdr2_tone_curve_cx_12:*/
  10946. #define WDR2_TONE_CURVE_CX_12
  10947. #define WDR2_TONE_CURVE_CX_12_MASK 0x000F0000U
  10948. #define WDR2_TONE_CURVE_CX_12_SHIFT 16U
  10949. /*! Slice: wdr2_tone_curve_cx_11:*/
  10950. #define WDR2_TONE_CURVE_CX_11
  10951. #define WDR2_TONE_CURVE_CX_11_MASK 0x0000F000U
  10952. #define WDR2_TONE_CURVE_CX_11_SHIFT 12U
  10953. /*! Slice: wdr2_tone_curve_cx_10:*/
  10954. #define WDR2_TONE_CURVE_CX_10
  10955. #define WDR2_TONE_CURVE_CX_10_MASK 0x00000F00U
  10956. #define WDR2_TONE_CURVE_CX_10_SHIFT 8U
  10957. /*! Slice: wdr2_tone_curve_cx_9:*/
  10958. #define WDR2_TONE_CURVE_CX_9
  10959. #define WDR2_TONE_CURVE_CX_9_MASK 0x000000F0U
  10960. #define WDR2_TONE_CURVE_CX_9_SHIFT 4U
  10961. /*! Slice: wdr2_tone_curve_cx_8:*/
  10962. #define WDR2_TONE_CURVE_CX_8
  10963. #define WDR2_TONE_CURVE_CX_8_MASK 0x0000000FU
  10964. #define WDR2_TONE_CURVE_CX_8_SHIFT 0U
  10965. /*! Register: isp_wdr2_tone_curve_cx_2 (0x00003184)*/
  10966. /*! Slice: wdr2_tone_curve_cx_23:*/
  10967. #define WDR2_TONE_CURVE_CX_23
  10968. #define WDR2_TONE_CURVE_CX_23_MASK 0xF0000000U
  10969. #define WDR2_TONE_CURVE_CX_23_SHIFT 28U
  10970. /*! Slice: wdr2_tone_curve_cx_22:*/
  10971. #define WDR2_TONE_CURVE_CX_22
  10972. #define WDR2_TONE_CURVE_CX_22_MASK 0x0F000000U
  10973. #define WDR2_TONE_CURVE_CX_22_SHIFT 24U
  10974. /*! Slice: wdr2_tone_curve_cx_21:*/
  10975. #define WDR2_TONE_CURVE_CX_21
  10976. #define WDR2_TONE_CURVE_CX_21_MASK 0x00F00000U
  10977. #define WDR2_TONE_CURVE_CX_21_SHIFT 20U
  10978. /*! Slice: wdr2_tone_curve_cx_20:*/
  10979. #define WDR2_TONE_CURVE_CX_20
  10980. #define WDR2_TONE_CURVE_CX_20_MASK 0x000F0000U
  10981. #define WDR2_TONE_CURVE_CX_20_SHIFT 16U
  10982. /*! Slice: wdr2_tone_curve_cx_19:*/
  10983. #define WDR2_TONE_CURVE_CX_19
  10984. #define WDR2_TONE_CURVE_CX_19_MASK 0x0000F000U
  10985. #define WDR2_TONE_CURVE_CX_19_SHIFT 12U
  10986. /*! Slice: wdr2_tone_curve_cx_18:*/
  10987. #define WDR2_TONE_CURVE_CX_18
  10988. #define WDR2_TONE_CURVE_CX_18_MASK 0x00000F00U
  10989. #define WDR2_TONE_CURVE_CX_18_SHIFT 8U
  10990. /*! Slice: wdr2_tone_curve_cx_17:*/
  10991. #define WDR2_TONE_CURVE_CX_17
  10992. #define WDR2_TONE_CURVE_CX_17_MASK 0x000000F0U
  10993. #define WDR2_TONE_CURVE_CX_17_SHIFT 4U
  10994. /*! Slice: wdr2_tone_curve_cx_16:*/
  10995. #define WDR2_TONE_CURVE_CX_16
  10996. #define WDR2_TONE_CURVE_CX_16_MASK 0x0000000FU
  10997. #define WDR2_TONE_CURVE_CX_16_SHIFT 0U
  10998. /*! Register: isp_wdr2_tone_curve_cx_3 (0x00003188)*/
  10999. /*! Slice: wdr2_tone_curve_cx_31:*/
  11000. #define WDR2_TONE_CURVE_CX_31
  11001. #define WDR2_TONE_CURVE_CX_31_MASK 0xF0000000U
  11002. #define WDR2_TONE_CURVE_CX_31_SHIFT 28U
  11003. /*! Slice: wdr2_tone_curve_cx_30:*/
  11004. #define WDR2_TONE_CURVE_CX_30
  11005. #define WDR2_TONE_CURVE_CX_30_MASK 0x0F000000U
  11006. #define WDR2_TONE_CURVE_CX_30_SHIFT 24U
  11007. /*! Slice: wdr2_tone_curve_cx_29:*/
  11008. #define WDR2_TONE_CURVE_CX_29
  11009. #define WDR2_TONE_CURVE_CX_29_MASK 0x00F00000U
  11010. #define WDR2_TONE_CURVE_CX_29_SHIFT 20U
  11011. /*! Slice: wdr2_tone_curve_cx_28:*/
  11012. #define WDR2_TONE_CURVE_CX_28
  11013. #define WDR2_TONE_CURVE_CX_28_MASK 0x000F0000U
  11014. #define WDR2_TONE_CURVE_CX_28_SHIFT 16U
  11015. /*! Slice: wdr2_tone_curve_cx_27:*/
  11016. #define WDR2_TONE_CURVE_CX_27
  11017. #define WDR2_TONE_CURVE_CX_27_MASK 0x0000F000U
  11018. #define WDR2_TONE_CURVE_CX_27_SHIFT 12U
  11019. /*! Slice: wdr2_tone_curve_cx_26:*/
  11020. #define WDR2_TONE_CURVE_CX_26
  11021. #define WDR2_TONE_CURVE_CX_26_MASK 0x00000F00U
  11022. #define WDR2_TONE_CURVE_CX_26_SHIFT 8U
  11023. /*! Slice: wdr2_tone_curve_cx_25:*/
  11024. #define WDR2_TONE_CURVE_CX_25
  11025. #define WDR2_TONE_CURVE_CX_25_MASK 0x000000F0U
  11026. #define WDR2_TONE_CURVE_CX_25_SHIFT 4U
  11027. /*! Slice: wdr2_tone_curve_cx_24:*/
  11028. #define WDR2_TONE_CURVE_CX_24
  11029. #define WDR2_TONE_CURVE_CX_24_MASK 0x0000000FU
  11030. #define WDR2_TONE_CURVE_CX_24_SHIFT 0U
  11031. /*! Register: isp_wdr2_merge_coeff_cx_0 (0x0000318C)*/
  11032. /*! Slice: wdr2_merge_coeff_cx_7:*/
  11033. #define WDR2_MERGE_COEFF_CX_7
  11034. #define WDR2_MERGE_COEFF_CX_7_MASK 0xF0000000U
  11035. #define WDR2_MERGE_COEFF_CX_7_SHIFT 28U
  11036. /*! Slice: wdr2_merge_coeff_cx_6:*/
  11037. #define WDR2_MERGE_COEFF_CX_6
  11038. #define WDR2_MERGE_COEFF_CX_6_MASK 0x0F000000U
  11039. #define WDR2_MERGE_COEFF_CX_6_SHIFT 24U
  11040. /*! Slice: wdr2_merge_coeff_cx_5:*/
  11041. #define WDR2_MERGE_COEFF_CX_5
  11042. #define WDR2_MERGE_COEFF_CX_5_MASK 0x00F00000U
  11043. #define WDR2_MERGE_COEFF_CX_5_SHIFT 20U
  11044. /*! Slice: wdr2_merge_coeff_cx_4:*/
  11045. #define WDR2_MERGE_COEFF_CX_4
  11046. #define WDR2_MERGE_COEFF_CX_4_MASK 0x000F0000U
  11047. #define WDR2_MERGE_COEFF_CX_4_SHIFT 16U
  11048. /*! Slice: wdr2_merge_coeff_cx_3:*/
  11049. #define WDR2_MERGE_COEFF_CX_3
  11050. #define WDR2_MERGE_COEFF_CX_3_MASK 0x0000F000U
  11051. #define WDR2_MERGE_COEFF_CX_3_SHIFT 12U
  11052. /*! Slice: wdr2_merge_coeff_cx_2:*/
  11053. #define WDR2_MERGE_COEFF_CX_2
  11054. #define WDR2_MERGE_COEFF_CX_2_MASK 0x00000F00U
  11055. #define WDR2_MERGE_COEFF_CX_2_SHIFT 8U
  11056. /*! Slice: wdr2_merge_coeff_cx_1:*/
  11057. #define WDR2_MERGE_COEFF_CX_1
  11058. #define WDR2_MERGE_COEFF_CX_1_MASK 0x000000F0U
  11059. #define WDR2_MERGE_COEFF_CX_1_SHIFT 4U
  11060. /*! Slice: wdr2_merge_coeff_cx_0:*/
  11061. #define WDR2_MERGE_COEFF_CX_0
  11062. #define WDR2_MERGE_COEFF_CX_0_MASK 0x0000000FU
  11063. #define WDR2_MERGE_COEFF_CX_0_SHIFT 0U
  11064. /*! Register: isp_wdr2_merge_coeff_cx_1 (0x00003190)*/
  11065. /*! Slice: wdr2_merge_coeff_cx_15:*/
  11066. #define WDR2_MERGE_COEFF_CX_15
  11067. #define WDR2_MERGE_COEFF_CX_15_MASK 0xF0000000U
  11068. #define WDR2_MERGE_COEFF_CX_15_SHIFT 28U
  11069. /*! Slice: wdr2_merge_coeff_cx_14:*/
  11070. #define WDR2_MERGE_COEFF_CX_14
  11071. #define WDR2_MERGE_COEFF_CX_14_MASK 0x0F000000U
  11072. #define WDR2_MERGE_COEFF_CX_14_SHIFT 24U
  11073. /*! Slice: wdr2_merge_coeff_cx_13:*/
  11074. #define WDR2_MERGE_COEFF_CX_13
  11075. #define WDR2_MERGE_COEFF_CX_13_MASK 0x00F00000U
  11076. #define WDR2_MERGE_COEFF_CX_13_SHIFT 20U
  11077. /*! Slice: wdr2_merge_coeff_cx_12:*/
  11078. #define WDR2_MERGE_COEFF_CX_12
  11079. #define WDR2_MERGE_COEFF_CX_12_MASK 0x000F0000U
  11080. #define WDR2_MERGE_COEFF_CX_12_SHIFT 16U
  11081. /*! Slice: wdr2_merge_coeff_cx_11:*/
  11082. #define WDR2_MERGE_COEFF_CX_11
  11083. #define WDR2_MERGE_COEFF_CX_11_MASK 0x0000F000U
  11084. #define WDR2_MERGE_COEFF_CX_11_SHIFT 12U
  11085. /*! Slice: wdr2_merge_coeff_cx_10:*/
  11086. #define WDR2_MERGE_COEFF_CX_10
  11087. #define WDR2_MERGE_COEFF_CX_10_MASK 0x00000F00U
  11088. #define WDR2_MERGE_COEFF_CX_10_SHIFT 8U
  11089. /*! Slice: wdr2_merge_coeff_cx_9:*/
  11090. #define WDR2_MERGE_COEFF_CX_9
  11091. #define WDR2_MERGE_COEFF_CX_9_MASK 0x000000F0U
  11092. #define WDR2_MERGE_COEFF_CX_9_SHIFT 4U
  11093. /*! Slice: wdr2_merge_coeff_cx_8:*/
  11094. #define WDR2_MERGE_COEFF_CX_8
  11095. #define WDR2_MERGE_COEFF_CX_8_MASK 0x0000000FU
  11096. #define WDR2_MERGE_COEFF_CX_8_SHIFT 0U
  11097. /*! Register: isp_wdr2_max_gain_cx (0x000031A8)*/
  11098. /*! Slice: wdr2_max_gain_cx_4:*/
  11099. #define WDR2_MAX_GAIN_CX_4
  11100. #define WDR2_MAX_GAIN_CX_4_MASK 0xFF000000U
  11101. #define WDR2_MAX_GAIN_CX_4_SHIFT 24U
  11102. /*! Slice: wdr2_max_gain_cx_3:*/
  11103. #define WDR2_MAX_GAIN_CX_3
  11104. #define WDR2_MAX_GAIN_CX_3_MASK 0x00FF0000U
  11105. #define WDR2_MAX_GAIN_CX_3_SHIFT 16U
  11106. /*! Slice: wdr2_max_gain_cx_2:*/
  11107. #define WDR2_MAX_GAIN_CX_2
  11108. #define WDR2_MAX_GAIN_CX_2_MASK 0x0000FF00U
  11109. #define WDR2_MAX_GAIN_CX_2_SHIFT 8U
  11110. /*! Slice: wdr2_max_gain_cx_1:*/
  11111. #define WDR2_MAX_GAIN_CX_1
  11112. #define WDR2_MAX_GAIN_CX_1_MASK 0x000000FFU
  11113. #define WDR2_MAX_GAIN_CX_1_SHIFT 0U
  11114. /*! Register: isp_wdr2_max_gain_slope_0 (0x000031AC)*/
  11115. /*! Slice: wdr2_max_gain_slope_1:*/
  11116. #define WDR2_MAX_GAIN_SLOPE_1
  11117. #define WDR2_MAX_GAIN_SLOPE_1_MASK 0x0FFF0000U
  11118. #define WDR2_MAX_GAIN_SLOPE_1_SHIFT 16U
  11119. /*! Slice: wdr2_max_gain_slope_0:*/
  11120. #define WDR2_MAX_GAIN_SLOPE_0
  11121. #define WDR2_MAX_GAIN_SLOPE_0_MASK 0x00000FFFU
  11122. #define WDR2_MAX_GAIN_SLOPE_0_SHIFT 0U
  11123. /*! Register: isp_wdr2_max_gain_slope_1 (0x000031B0)*/
  11124. /*! Slice: wdr2_max_gain_slope_3:*/
  11125. #define WDR2_MAX_GAIN_SLOPE_3
  11126. #define WDR2_MAX_GAIN_SLOPE_3_MASK 0x0FFF0000U
  11127. #define WDR2_MAX_GAIN_SLOPE_3_SHIFT 16U
  11128. /*! Slice: wdr2_max_gain_slope_2:*/
  11129. #define WDR2_MAX_GAIN_SLOPE_2
  11130. #define WDR2_MAX_GAIN_SLOPE_2_MASK 0x00000FFFU
  11131. #define WDR2_MAX_GAIN_SLOPE_2_SHIFT 0U
  11132. /*! Register: isp_wdr2_max_gain_slope_2 (0x000031B4)*/
  11133. /*! Slice: wdr2_max_gain_slope_4:*/
  11134. #define WDR2_MAX_GAIN_SLOPE_4
  11135. #define WDR2_MAX_GAIN_SLOPE_4_MASK 0x00000FFFU
  11136. #define WDR2_MAX_GAIN_SLOPE_4_SHIFT 0U
  11137. /*! Register: isp_wdr2_max_gain_cy_0 (0x000031B8)*/
  11138. /*! Slice: wdr2_max_gain_cy_1:*/
  11139. #define WDR2_MAX_GAIN_CY_1
  11140. #define WDR2_MAX_GAIN_CY_1_MASK 0x0FFF0000U
  11141. #define WDR2_MAX_GAIN_CY_1_SHIFT 16U
  11142. /*! Slice: wdr2_max_gain_cy_0:*/
  11143. #define WDR2_MAX_GAIN_CY_0
  11144. #define WDR2_MAX_GAIN_CY_0_MASK 0x00000FFFU
  11145. #define WDR2_MAX_GAIN_CY_0_SHIFT 0U
  11146. /*! Register: isp_wdr2_max_gain_cy_1 (0x000031BC)*/
  11147. /*! Slice: wdr2_max_gain_cy_3:*/
  11148. #define WDR2_MAX_GAIN_CY_3
  11149. #define WDR2_MAX_GAIN_CY_3_MASK 0x0FFF0000U
  11150. #define WDR2_MAX_GAIN_CY_3_SHIFT 16U
  11151. /*! Slice: wdr2_max_gain_cy_2:*/
  11152. #define WDR2_MAX_GAIN_CY_2
  11153. #define WDR2_MAX_GAIN_CY_2_MASK 0x00000FFFU
  11154. #define WDR2_MAX_GAIN_CY_2_SHIFT 0U
  11155. /*! Register: isp_wdr2_max_gain_cy_2 (0x000031C0)*/
  11156. /*! Slice: wdr2_max_gain_cy_5:*/
  11157. #define WDR2_MAX_GAIN_CY_5
  11158. #define WDR2_MAX_GAIN_CY_5_MASK 0x0FFF0000U
  11159. #define WDR2_MAX_GAIN_CY_5_SHIFT 16U
  11160. /*! Slice: wdr2_max_gain_cy_4:*/
  11161. #define WDR2_MAX_GAIN_CY_4
  11162. #define WDR2_MAX_GAIN_CY_4_MASK 0x00000FFFU
  11163. #define WDR2_MAX_GAIN_CY_4_SHIFT 0U
  11164. /*! Register: isp_wdr2_norm_factor_mul_0 (0x000031C4)*/
  11165. /*! Slice: wdr2_norm_factor_mul_3:*/
  11166. #define WDR2_NORM_FACTOR_MUL_3
  11167. #define WDR2_NORM_FACTOR_MUL_3_MASK 0xFF000000U
  11168. #define WDR2_NORM_FACTOR_MUL_3_SHIFT 24U
  11169. /*! Slice: wdr2_norm_factor_mul_2:*/
  11170. #define WDR2_NORM_FACTOR_MUL_2
  11171. #define WDR2_NORM_FACTOR_MUL_2_MASK 0x00FF0000U
  11172. #define WDR2_NORM_FACTOR_MUL_2_SHIFT 16U
  11173. /*! Slice: wdr2_norm_factor_mul_1:*/
  11174. #define WDR2_NORM_FACTOR_MUL_1
  11175. #define WDR2_NORM_FACTOR_MUL_1_MASK 0x0000FF00U
  11176. #define WDR2_NORM_FACTOR_MUL_1_SHIFT 8U
  11177. /*! Slice: wdr2_norm_factor_mul_0:*/
  11178. #define WDR2_NORM_FACTOR_MUL_0
  11179. #define WDR2_NORM_FACTOR_MUL_0_MASK 0x000000FFU
  11180. #define WDR2_NORM_FACTOR_MUL_0_SHIFT 0U
  11181. /*! Register: isp_wdr2_norm_factor_mul_1 (0x000031C8)*/
  11182. /*! Slice: wdr2_norm_factor_mul_7:*/
  11183. #define WDR2_NORM_FACTOR_MUL_7
  11184. #define WDR2_NORM_FACTOR_MUL_7_MASK 0xFF000000U
  11185. #define WDR2_NORM_FACTOR_MUL_7_SHIFT 24U
  11186. /*! Slice: wdr2_norm_factor_mul_6:*/
  11187. #define WDR2_NORM_FACTOR_MUL_6
  11188. #define WDR2_NORM_FACTOR_MUL_6_MASK 0x00FF0000U
  11189. #define WDR2_NORM_FACTOR_MUL_6_SHIFT 16U
  11190. /*! Slice: wdr2_norm_factor_mul_5:*/
  11191. #define WDR2_NORM_FACTOR_MUL_5
  11192. #define WDR2_NORM_FACTOR_MUL_5_MASK 0x0000FF00U
  11193. #define WDR2_NORM_FACTOR_MUL_5_SHIFT 8U
  11194. /*! Slice: wdr2_norm_factor_mul_4:*/
  11195. #define WDR2_NORM_FACTOR_MUL_4
  11196. #define WDR2_NORM_FACTOR_MUL_4_MASK 0x000000FFU
  11197. #define WDR2_NORM_FACTOR_MUL_4_SHIFT 0U
  11198. /*! Register: isp_wdr2_norm_factor_shift_bit_0 (0x000031CC)*/
  11199. /*! Slice: wdr2_norm_factor_shift_bit_3:*/
  11200. #define WDR2_NORM_FACTOR_SHIFT_BIT_3
  11201. #define WDR2_NORM_FACTOR_SHIFT_BIT_3_MASK 0xFF000000U
  11202. #define WDR2_NORM_FACTOR_SHIFT_BIT_3_SHIFT 24U
  11203. /*! Slice: wdr2_norm_factor_shift_bit_2:*/
  11204. #define WDR2_NORM_FACTOR_SHIFT_BIT_2
  11205. #define WDR2_NORM_FACTOR_SHIFT_BIT_2_MASK 0x00FF0000U
  11206. #define WDR2_NORM_FACTOR_SHIFT_BIT_2_SHIFT 16U
  11207. /*! Slice: wdr2_norm_factor_shift_bit_1:*/
  11208. #define WDR2_NORM_FACTOR_SHIFT_BIT_1
  11209. #define WDR2_NORM_FACTOR_SHIFT_BIT_1_MASK 0x0000FF00U
  11210. #define WDR2_NORM_FACTOR_SHIFT_BIT_1_SHIFT 8U
  11211. /*! Slice: wdr2_norm_factor_shift_bit_0:*/
  11212. #define WDR2_NORM_FACTOR_SHIFT_BIT_0
  11213. #define WDR2_NORM_FACTOR_SHIFT_BIT_0_MASK 0x000000FFU
  11214. #define WDR2_NORM_FACTOR_SHIFT_BIT_0_SHIFT 0U
  11215. /*! Register: isp_wdr2_norm_factor_shift_bit_1 (0x000031D0)*/
  11216. /*! Slice: wdr2_norm_factor_shift_bit_7:*/
  11217. #define WDR2_NORM_FACTOR_SHIFT_BIT_7
  11218. #define WDR2_NORM_FACTOR_SHIFT_BIT_7_MASK 0xFF000000U
  11219. #define WDR2_NORM_FACTOR_SHIFT_BIT_7_SHIFT 24U
  11220. /*! Slice: wdr2_norm_factor_shift_bit_6:*/
  11221. #define WDR2_NORM_FACTOR_SHIFT_BIT_6
  11222. #define WDR2_NORM_FACTOR_SHIFT_BIT_6_MASK 0x00FF0000U
  11223. #define WDR2_NORM_FACTOR_SHIFT_BIT_6_SHIFT 16U
  11224. /*! Slice: wdr2_norm_factor_shift_bit_5:*/
  11225. #define WDR2_NORM_FACTOR_SHIFT_BIT_5
  11226. #define WDR2_NORM_FACTOR_SHIFT_BIT_5_MASK 0x0000FF00U
  11227. #define WDR2_NORM_FACTOR_SHIFT_BIT_5_SHIFT 8U
  11228. /*! Slice: wdr2_norm_factor_shift_bit_4:*/
  11229. #define WDR2_NORM_FACTOR_SHIFT_BIT_4
  11230. #define WDR2_NORM_FACTOR_SHIFT_BIT_4_MASK 0x000000FFU
  11231. #define WDR2_NORM_FACTOR_SHIFT_BIT_4_SHIFT 0U
  11232. /*! Register: isp_wdr2_bin_range_0 (0x000031D4)*/
  11233. /*! Slice: wdr2_bin_range_2:*/
  11234. #define WDR2_BIN_RANGE_2
  11235. #define WDR2_BIN_RANGE_2_MASK 0x0FFF0000U
  11236. #define WDR2_BIN_RANGE_2_SHIFT 16U
  11237. /*! Slice: wdr2_bin_range_1:*/
  11238. #define WDR2_BIN_RANGE_1
  11239. #define WDR2_BIN_RANGE_1_MASK 0x00000FFFU
  11240. #define WDR2_BIN_RANGE_1_SHIFT 0U
  11241. /*! Register: isp_wdr2_bin_range_1 (0x000031D8)*/
  11242. /*! Slice: wdr2_bin_range_4:*/
  11243. #define WDR2_BIN_RANGE_4
  11244. #define WDR2_BIN_RANGE_4_MASK 0x0FFF0000U
  11245. #define WDR2_BIN_RANGE_4_SHIFT 16U
  11246. /*! Slice: wdr2_bin_range_3:*/
  11247. #define WDR2_BIN_RANGE_3
  11248. #define WDR2_BIN_RANGE_3_MASK 0x00000FFFU
  11249. #define WDR2_BIN_RANGE_3_SHIFT 0U
  11250. /*! Register: isp_wdr2_bin_range_2 (0x000031DC)*/
  11251. /*! Slice: wdr2_bin_range_6:*/
  11252. #define WDR2_BIN_RANGE_6
  11253. #define WDR2_BIN_RANGE_6_MASK 0x0FFF0000U
  11254. #define WDR2_BIN_RANGE_6_SHIFT 16U
  11255. /*! Slice: wdr2_bin_range_5:*/
  11256. #define WDR2_BIN_RANGE_5
  11257. #define WDR2_BIN_RANGE_5_MASK 0x00000FFFU
  11258. #define WDR2_BIN_RANGE_5_SHIFT 0U
  11259. /*! Register: isp_wdr2_bin_range_3 (0x000031E0)*/
  11260. /*! Slice: wdr2_bin_range_8:*/
  11261. #define WDR2_BIN_RANGE_8
  11262. #define WDR2_BIN_RANGE_8_MASK 0x0FFF0000U
  11263. #define WDR2_BIN_RANGE_8_SHIFT 16U
  11264. /*! Slice: wdr2_bin_range_7:*/
  11265. #define WDR2_BIN_RANGE_7
  11266. #define WDR2_BIN_RANGE_7_MASK 0x00000FFFU
  11267. #define WDR2_BIN_RANGE_7_SHIFT 0U
  11268. /*! Register: isp_wdr2_hist_data_0 (0x000031E4)*/
  11269. /*! Slice: wdr2_hist_data_3:*/
  11270. #define WDR2_HIST_DATA_3
  11271. #define WDR2_HIST_DATA_3_MASK 0xFF000000U
  11272. #define WDR2_HIST_DATA_3_SHIFT 24U
  11273. /*! Slice: wdr2_hist_data_2:*/
  11274. #define WDR2_HIST_DATA_2
  11275. #define WDR2_HIST_DATA_2_MASK 0x00FF0000U
  11276. #define WDR2_HIST_DATA_2_SHIFT 16U
  11277. /*! Slice: wdr2_hist_data_1:*/
  11278. #define WDR2_HIST_DATA_1
  11279. #define WDR2_HIST_DATA_1_MASK 0x0000FF00U
  11280. #define WDR2_HIST_DATA_1_SHIFT 8U
  11281. /*! Slice: wdr2_hist_data_0:*/
  11282. #define WDR2_HIST_DATA_0
  11283. #define WDR2_HIST_DATA_0_MASK 0x000000FFU
  11284. #define WDR2_HIST_DATA_0_SHIFT 0U
  11285. /*! Register: isp_wdr2_hist_data_1 (0x000031E8)*/
  11286. /*! Slice: wdr2_hist_data_7:*/
  11287. #define WDR2_HIST_DATA_7
  11288. #define WDR2_HIST_DATA_7_MASK 0xFF000000U
  11289. #define WDR2_HIST_DATA_7_SHIFT 24U
  11290. /*! Slice: wdr2_hist_data_6:*/
  11291. #define WDR2_HIST_DATA_6
  11292. #define WDR2_HIST_DATA_6_MASK 0x00FF0000U
  11293. #define WDR2_HIST_DATA_6_SHIFT 16U
  11294. /*! Slice: wdr2_hist_data_5:*/
  11295. #define WDR2_HIST_DATA_5
  11296. #define WDR2_HIST_DATA_5_MASK 0x0000FF00U
  11297. #define WDR2_HIST_DATA_5_SHIFT 8U
  11298. /*! Slice: wdr2_hist_data_4:*/
  11299. #define WDR2_HIST_DATA_4
  11300. #define WDR2_HIST_DATA_4_MASK 0x000000FFU
  11301. #define WDR2_HIST_DATA_4_SHIFT 0U
  11302. /*! Register: isp_compand_ctrl (0x00003200)*/
  11303. /*! Slice: compand_ctrl_bls_enable:*/
  11304. #define COMPAND_CTRL_BLS_ENABLE
  11305. #define COMPAND_CTRL_BLS_ENABLE_MASK 0x00000008U
  11306. #define COMPAND_CTRL_BLS_ENABLE_SHIFT 3U
  11307. /*! Slice: compand_ctrl_soft_reset_flag:*/
  11308. #define COMPAND_CTRL_SOFT_RESET_FLAG
  11309. #define COMPAND_CTRL_SOFT_RESET_FLAG_MASK 0x00000004U
  11310. #define COMPAND_CTRL_SOFT_RESET_FLAG_SHIFT 2U
  11311. /*! Slice: compand_ctrl_compress_enable:*/
  11312. #define COMPAND_CTRL_COMPRESS_ENABLE
  11313. #define COMPAND_CTRL_COMPRESS_ENABLE_MASK 0x00000002U
  11314. #define COMPAND_CTRL_COMPRESS_ENABLE_SHIFT 1U
  11315. /*! Slice: compand_ctrl_expand_enable:*/
  11316. #define COMPAND_CTRL_EXPAND_ENABLE
  11317. #define COMPAND_CTRL_EXPAND_ENABLE_MASK 0x00000001U
  11318. #define COMPAND_CTRL_EXPAND_ENABLE_SHIFT 0U
  11319. /*! Register: isp_compand_bls_a_fixed (0x00003204)*/
  11320. /*! Slice: compand_bls_a_fixed:*/
  11321. #define COMPAND_BLS_A_FIXED
  11322. #define COMPAND_BLS_A_FIXED_MASK 0x001FFFFFU
  11323. #define COMPAND_BLS_A_FIXED_SHIFT 0U
  11324. /*! Register: isp_compand_bls_b_fixed (0x00003208)*/
  11325. /*! Slice: compand_bls_b_fixed:*/
  11326. #define COMPAND_BLS_B_FIXED
  11327. #define COMPAND_BLS_B_FIXED_MASK 0x001FFFFFU
  11328. #define COMPAND_BLS_B_FIXED_SHIFT 0U
  11329. /*! Register: isp_compand_bls_c_fixed (0x0000320C)*/
  11330. /*! Slice: compand_bls_c_fixed:*/
  11331. #define COMPAND_BLS_C_FIXED
  11332. #define COMPAND_BLS_C_FIXED_MASK 0x001FFFFFU
  11333. #define COMPAND_BLS_C_FIXED_SHIFT 0U
  11334. /*! Register: isp_compand_bls_d_fixed (0x00003210)*/
  11335. /*! Slice: compand_bls_d_fixed:*/
  11336. #define COMPAND_BLS_D_FIXED
  11337. #define COMPAND_BLS_D_FIXED_MASK 0x001FFFFFU
  11338. #define COMPAND_BLS_D_FIXED_SHIFT 0U
  11339. /*! Register: isp_compand_expand_px_0 (0x00003214)*/
  11340. /*! Slice: compand_expand_px_5:*/
  11341. #define COMPAND_EXPAND_PX_5
  11342. #define COMPAND_EXPAND_PX_5_MASK 0x3E000000U
  11343. #define COMPAND_EXPAND_PX_5_SHIFT 25U
  11344. /*! Slice: compand_expand_px_4:*/
  11345. #define COMPAND_EXPAND_PX_4
  11346. #define COMPAND_EXPAND_PX_4_MASK 0x01F00000U
  11347. #define COMPAND_EXPAND_PX_4_SHIFT 20U
  11348. /*! Slice: compand_expand_px_3:*/
  11349. #define COMPAND_EXPAND_PX_3
  11350. #define COMPAND_EXPAND_PX_3_MASK 0x000F8000U
  11351. #define COMPAND_EXPAND_PX_3_SHIFT 15U
  11352. /*! Slice: compand_expand_px_2:*/
  11353. #define COMPAND_EXPAND_PX_2
  11354. #define COMPAND_EXPAND_PX_2_MASK 0x00007C00U
  11355. #define COMPAND_EXPAND_PX_2_SHIFT 10U
  11356. /*! Slice: compand_expand_px_1:*/
  11357. #define COMPAND_EXPAND_PX_1
  11358. #define COMPAND_EXPAND_PX_1_MASK 0x000003E0U
  11359. #define COMPAND_EXPAND_PX_1_SHIFT 5U
  11360. /*! Slice: compand_expand_px_0:*/
  11361. #define COMPAND_EXPAND_PX_0
  11362. #define COMPAND_EXPAND_PX_0_MASK 0x0000001FU
  11363. #define COMPAND_EXPAND_PX_0_SHIFT 0U
  11364. /*! Register: isp_compand_expand_px_1 (0x00003218)*/
  11365. /*! Slice: compand_expand_px_11:*/
  11366. #define COMPAND_EXPAND_PX_11
  11367. #define COMPAND_EXPAND_PX_11_MASK 0x3E000000U
  11368. #define COMPAND_EXPAND_PX_11_SHIFT 25U
  11369. /*! Slice: compand_expand_px_10:*/
  11370. #define COMPAND_EXPAND_PX_10
  11371. #define COMPAND_EXPAND_PX_10_MASK 0x01F00000U
  11372. #define COMPAND_EXPAND_PX_10_SHIFT 20U
  11373. /*! Slice: compand_expand_px_9:*/
  11374. #define COMPAND_EXPAND_PX_9
  11375. #define COMPAND_EXPAND_PX_9_MASK 0x000F8000U
  11376. #define COMPAND_EXPAND_PX_9_SHIFT 15U
  11377. /*! Slice: compand_expand_px_8:*/
  11378. #define COMPAND_EXPAND_PX_8
  11379. #define COMPAND_EXPAND_PX_8_MASK 0x00007C00U
  11380. #define COMPAND_EXPAND_PX_8_SHIFT 10U
  11381. /*! Slice: compand_expand_px_7:*/
  11382. #define COMPAND_EXPAND_PX_7
  11383. #define COMPAND_EXPAND_PX_7_MASK 0x000003E0U
  11384. #define COMPAND_EXPAND_PX_7_SHIFT 5U
  11385. /*! Slice: compand_expand_px_6:*/
  11386. #define COMPAND_EXPAND_PX_6
  11387. #define COMPAND_EXPAND_PX_6_MASK 0x0000001FU
  11388. #define COMPAND_EXPAND_PX_6_SHIFT 0U
  11389. /*! Register: isp_compand_expand_px_2 (0x0000321C)*/
  11390. /*! Slice: compand_expand_px_17:*/
  11391. #define COMPAND_EXPAND_PX_17
  11392. #define COMPAND_EXPAND_PX_17_MASK 0x3E000000U
  11393. #define COMPAND_EXPAND_PX_17_SHIFT 25U
  11394. /*! Slice: compand_expand_px_16:*/
  11395. #define COMPAND_EXPAND_PX_16
  11396. #define COMPAND_EXPAND_PX_16_MASK 0x01F00000U
  11397. #define COMPAND_EXPAND_PX_16_SHIFT 20U
  11398. /*! Slice: compand_expand_px_15:*/
  11399. #define COMPAND_EXPAND_PX_15
  11400. #define COMPAND_EXPAND_PX_15_MASK 0x000F8000U
  11401. #define COMPAND_EXPAND_PX_15_SHIFT 15U
  11402. /*! Slice: compand_expand_px_14:*/
  11403. #define COMPAND_EXPAND_PX_14
  11404. #define COMPAND_EXPAND_PX_14_MASK 0x00007C00U
  11405. #define COMPAND_EXPAND_PX_14_SHIFT 10U
  11406. /*! Slice: compand_expand_px_13:*/
  11407. #define COMPAND_EXPAND_PX_13
  11408. #define COMPAND_EXPAND_PX_13_MASK 0x000003E0U
  11409. #define COMPAND_EXPAND_PX_13_SHIFT 5U
  11410. /*! Slice: compand_expand_px_12:*/
  11411. #define COMPAND_EXPAND_PX_12
  11412. #define COMPAND_EXPAND_PX_12_MASK 0x0000001FU
  11413. #define COMPAND_EXPAND_PX_12_SHIFT 0U
  11414. /*! Register: isp_compand_expand_px_3 (0x00003220)*/
  11415. /*! Slice: compand_expand_px_23:*/
  11416. #define COMPAND_EXPAND_PX_23
  11417. #define COMPAND_EXPAND_PX_23_MASK 0x3E000000U
  11418. #define COMPAND_EXPAND_PX_23_SHIFT 25U
  11419. /*! Slice: compand_expand_px_22:*/
  11420. #define COMPAND_EXPAND_PX_22
  11421. #define COMPAND_EXPAND_PX_22_MASK 0x01F00000U
  11422. #define COMPAND_EXPAND_PX_22_SHIFT 20U
  11423. /*! Slice: compand_expand_px_21:*/
  11424. #define COMPAND_EXPAND_PX_21
  11425. #define COMPAND_EXPAND_PX_21_MASK 0x000F8000U
  11426. #define COMPAND_EXPAND_PX_21_SHIFT 15U
  11427. /*! Slice: compand_expand_px_20:*/
  11428. #define COMPAND_EXPAND_PX_20
  11429. #define COMPAND_EXPAND_PX_20_MASK 0x00007C00U
  11430. #define COMPAND_EXPAND_PX_20_SHIFT 10U
  11431. /*! Slice: compand_expand_px_19:*/
  11432. #define COMPAND_EXPAND_PX_19
  11433. #define COMPAND_EXPAND_PX_19_MASK 0x000003E0U
  11434. #define COMPAND_EXPAND_PX_19_SHIFT 5U
  11435. /*! Slice: compand_expand_px_18:*/
  11436. #define COMPAND_EXPAND_PX_18
  11437. #define COMPAND_EXPAND_PX_18_MASK 0x0000001FU
  11438. #define COMPAND_EXPAND_PX_18_SHIFT 0U
  11439. /*! Register: isp_compand_expand_px_4 (0x00003224)*/
  11440. /*! Slice: compand_expand_px_29:*/
  11441. #define COMPAND_EXPAND_PX_29
  11442. #define COMPAND_EXPAND_PX_29_MASK 0x3E000000U
  11443. #define COMPAND_EXPAND_PX_29_SHIFT 25U
  11444. /*! Slice: compand_expand_px_28:*/
  11445. #define COMPAND_EXPAND_PX_28
  11446. #define COMPAND_EXPAND_PX_28_MASK 0x01F00000U
  11447. #define COMPAND_EXPAND_PX_28_SHIFT 20U
  11448. /*! Slice: compand_expand_px_27:*/
  11449. #define COMPAND_EXPAND_PX_27
  11450. #define COMPAND_EXPAND_PX_27_MASK 0x000F8000U
  11451. #define COMPAND_EXPAND_PX_27_SHIFT 15U
  11452. /*! Slice: compand_expand_px_26:*/
  11453. #define COMPAND_EXPAND_PX_26
  11454. #define COMPAND_EXPAND_PX_26_MASK 0x00007C00U
  11455. #define COMPAND_EXPAND_PX_26_SHIFT 10U
  11456. /*! Slice: compand_expand_px_25:*/
  11457. #define COMPAND_EXPAND_PX_25
  11458. #define COMPAND_EXPAND_PX_25_MASK 0x000003E0U
  11459. #define COMPAND_EXPAND_PX_25_SHIFT 5U
  11460. /*! Slice: compand_expand_px_24:*/
  11461. #define COMPAND_EXPAND_PX_24
  11462. #define COMPAND_EXPAND_PX_24_MASK 0x0000001FU
  11463. #define COMPAND_EXPAND_PX_24_SHIFT 0U
  11464. /*! Register: isp_compand_expand_px_5 (0x00003228)*/
  11465. /*! Slice: compand_expand_px_35:*/
  11466. #define COMPAND_EXPAND_PX_35
  11467. #define COMPAND_EXPAND_PX_35_MASK 0x3E000000U
  11468. #define COMPAND_EXPAND_PX_35_SHIFT 25U
  11469. /*! Slice: compand_expand_px_34:*/
  11470. #define COMPAND_EXPAND_PX_34
  11471. #define COMPAND_EXPAND_PX_34_MASK 0x01F00000U
  11472. #define COMPAND_EXPAND_PX_34_SHIFT 20U
  11473. /*! Slice: compand_expand_px_33:*/
  11474. #define COMPAND_EXPAND_PX_33
  11475. #define COMPAND_EXPAND_PX_33_MASK 0x000F8000U
  11476. #define COMPAND_EXPAND_PX_33_SHIFT 15U
  11477. /*! Slice: compand_expand_px_32:*/
  11478. #define COMPAND_EXPAND_PX_32
  11479. #define COMPAND_EXPAND_PX_32_MASK 0x00007C00U
  11480. #define COMPAND_EXPAND_PX_32_SHIFT 10U
  11481. /*! Slice: compand_expand_px_31:*/
  11482. #define COMPAND_EXPAND_PX_31
  11483. #define COMPAND_EXPAND_PX_31_MASK 0x000003E0U
  11484. #define COMPAND_EXPAND_PX_31_SHIFT 5U
  11485. /*! Slice: compand_expand_px_30:*/
  11486. #define COMPAND_EXPAND_PX_30
  11487. #define COMPAND_EXPAND_PX_30_MASK 0x0000001FU
  11488. #define COMPAND_EXPAND_PX_30_SHIFT 0U
  11489. /*! Register: isp_compand_expand_px_6 (0x0000322C)*/
  11490. /*! Slice: compand_expand_px_41:*/
  11491. #define COMPAND_EXPAND_PX_41
  11492. #define COMPAND_EXPAND_PX_41_MASK 0x3E000000U
  11493. #define COMPAND_EXPAND_PX_41_SHIFT 25U
  11494. /*! Slice: compand_expand_px_40:*/
  11495. #define COMPAND_EXPAND_PX_40
  11496. #define COMPAND_EXPAND_PX_40_MASK 0x01F00000U
  11497. #define COMPAND_EXPAND_PX_40_SHIFT 20U
  11498. /*! Slice: compand_expand_px_39:*/
  11499. #define COMPAND_EXPAND_PX_39
  11500. #define COMPAND_EXPAND_PX_39_MASK 0x000F8000U
  11501. #define COMPAND_EXPAND_PX_39_SHIFT 15U
  11502. /*! Slice: compand_expand_px_38:*/
  11503. #define COMPAND_EXPAND_PX_38
  11504. #define COMPAND_EXPAND_PX_38_MASK 0x00007C00U
  11505. #define COMPAND_EXPAND_PX_38_SHIFT 10U
  11506. /*! Slice: compand_expand_px_37:*/
  11507. #define COMPAND_EXPAND_PX_37
  11508. #define COMPAND_EXPAND_PX_37_MASK 0x000003E0U
  11509. #define COMPAND_EXPAND_PX_37_SHIFT 5U
  11510. /*! Slice: compand_expand_px_36:*/
  11511. #define COMPAND_EXPAND_PX_36
  11512. #define COMPAND_EXPAND_PX_36_MASK 0x0000001FU
  11513. #define COMPAND_EXPAND_PX_36_SHIFT 0U
  11514. /*! Register: isp_compand_expand_px_7 (0x00003230)*/
  11515. /*! Slice: compand_expand_px_47:*/
  11516. #define COMPAND_EXPAND_PX_47
  11517. #define COMPAND_EXPAND_PX_47_MASK 0x3E000000U
  11518. #define COMPAND_EXPAND_PX_47_SHIFT 25U
  11519. /*! Slice: compand_expand_px_46:*/
  11520. #define COMPAND_EXPAND_PX_46
  11521. #define COMPAND_EXPAND_PX_46_MASK 0x01F00000U
  11522. #define COMPAND_EXPAND_PX_46_SHIFT 20U
  11523. /*! Slice: compand_expand_px_45:*/
  11524. #define COMPAND_EXPAND_PX_45
  11525. #define COMPAND_EXPAND_PX_45_MASK 0x000F8000U
  11526. #define COMPAND_EXPAND_PX_45_SHIFT 15U
  11527. /*! Slice: compand_expand_px_44:*/
  11528. #define COMPAND_EXPAND_PX_44
  11529. #define COMPAND_EXPAND_PX_44_MASK 0x00007C00U
  11530. #define COMPAND_EXPAND_PX_44_SHIFT 10U
  11531. /*! Slice: compand_expand_px_43:*/
  11532. #define COMPAND_EXPAND_PX_43
  11533. #define COMPAND_EXPAND_PX_43_MASK 0x000003E0U
  11534. #define COMPAND_EXPAND_PX_43_SHIFT 5U
  11535. /*! Slice: compand_expand_px_42:*/
  11536. #define COMPAND_EXPAND_PX_42
  11537. #define COMPAND_EXPAND_PX_42_MASK 0x0000001FU
  11538. #define COMPAND_EXPAND_PX_42_SHIFT 0U
  11539. /*! Register: isp_compand_expand_px_8 (0x00003234)*/
  11540. /*! Slice: compand_expand_px_53:*/
  11541. #define COMPAND_EXPAND_PX_53
  11542. #define COMPAND_EXPAND_PX_53_MASK 0x3E000000U
  11543. #define COMPAND_EXPAND_PX_53_SHIFT 25U
  11544. /*! Slice: compand_expand_px_52:*/
  11545. #define COMPAND_EXPAND_PX_52
  11546. #define COMPAND_EXPAND_PX_52_MASK 0x01F00000U
  11547. #define COMPAND_EXPAND_PX_52_SHIFT 20U
  11548. /*! Slice: compand_expand_px_51:*/
  11549. #define COMPAND_EXPAND_PX_51
  11550. #define COMPAND_EXPAND_PX_51_MASK 0x000F8000U
  11551. #define COMPAND_EXPAND_PX_51_SHIFT 15U
  11552. /*! Slice: compand_expand_px_50:*/
  11553. #define COMPAND_EXPAND_PX_50
  11554. #define COMPAND_EXPAND_PX_50_MASK 0x00007C00U
  11555. #define COMPAND_EXPAND_PX_50_SHIFT 10U
  11556. /*! Slice: compand_expand_px_49:*/
  11557. #define COMPAND_EXPAND_PX_49
  11558. #define COMPAND_EXPAND_PX_49_MASK 0x000003E0U
  11559. #define COMPAND_EXPAND_PX_49_SHIFT 5U
  11560. /*! Slice: compand_expand_px_48:*/
  11561. #define COMPAND_EXPAND_PX_48
  11562. #define COMPAND_EXPAND_PX_48_MASK 0x0000001FU
  11563. #define COMPAND_EXPAND_PX_48_SHIFT 0U
  11564. /*! Register: isp_compand_expand_px_9 (0x00003238)*/
  11565. /*! Slice: compand_expand_px_59:*/
  11566. #define COMPAND_EXPAND_PX_59
  11567. #define COMPAND_EXPAND_PX_59_MASK 0x3E000000U
  11568. #define COMPAND_EXPAND_PX_59_SHIFT 25U
  11569. /*! Slice: compand_expand_px_58:*/
  11570. #define COMPAND_EXPAND_PX_58
  11571. #define COMPAND_EXPAND_PX_58_MASK 0x01F00000U
  11572. #define COMPAND_EXPAND_PX_58_SHIFT 20U
  11573. /*! Slice: compand_expand_px_57:*/
  11574. #define COMPAND_EXPAND_PX_57
  11575. #define COMPAND_EXPAND_PX_57_MASK 0x000F8000U
  11576. #define COMPAND_EXPAND_PX_57_SHIFT 15U
  11577. /*! Slice: compand_expand_px_56:*/
  11578. #define COMPAND_EXPAND_PX_56
  11579. #define COMPAND_EXPAND_PX_56_MASK 0x00007C00U
  11580. #define COMPAND_EXPAND_PX_56_SHIFT 10U
  11581. /*! Slice: compand_expand_px_55:*/
  11582. #define COMPAND_EXPAND_PX_55
  11583. #define COMPAND_EXPAND_PX_55_MASK 0x000003E0U
  11584. #define COMPAND_EXPAND_PX_55_SHIFT 5U
  11585. /*! Slice: compand_expand_px_54:*/
  11586. #define COMPAND_EXPAND_PX_54
  11587. #define COMPAND_EXPAND_PX_54_MASK 0x0000001FU
  11588. #define COMPAND_EXPAND_PX_54_SHIFT 0U
  11589. /*! Register: isp_compand_expand_px_10 (0x0000323C)*/
  11590. /*! Slice: compand_expand_px_63:*/
  11591. #define COMPAND_EXPAND_PX_63
  11592. #define COMPAND_EXPAND_PX_63_MASK 0x000F8000U
  11593. #define COMPAND_EXPAND_PX_63_SHIFT 15U
  11594. /*! Slice: compand_expand_px_62:*/
  11595. #define COMPAND_EXPAND_PX_62
  11596. #define COMPAND_EXPAND_PX_62_MASK 0x00007C00U
  11597. #define COMPAND_EXPAND_PX_62_SHIFT 10U
  11598. /*! Slice: compand_expand_px_61:*/
  11599. #define COMPAND_EXPAND_PX_61
  11600. #define COMPAND_EXPAND_PX_61_MASK 0x000003E0U
  11601. #define COMPAND_EXPAND_PX_61_SHIFT 5U
  11602. /*! Slice: compand_expand_px_60:*/
  11603. #define COMPAND_EXPAND_PX_60
  11604. #define COMPAND_EXPAND_PX_60_MASK 0x0000001FU
  11605. #define COMPAND_EXPAND_PX_60_SHIFT 0U
  11606. /*! Register: isp_compand_compress_px_0 (0x00003240)*/
  11607. /*! Slice: compand_compress_px_5:*/
  11608. #define COMPAND_COMPRESS_PX_5
  11609. #define COMPAND_COMPRESS_PX_5_MASK 0x3E000000U
  11610. #define COMPAND_COMPRESS_PX_5_SHIFT 25U
  11611. /*! Slice: compand_compress_px_4:*/
  11612. #define COMPAND_COMPRESS_PX_4
  11613. #define COMPAND_COMPRESS_PX_4_MASK 0x01F00000U
  11614. #define COMPAND_COMPRESS_PX_4_SHIFT 20U
  11615. /*! Slice: compand_compress_px_3:*/
  11616. #define COMPAND_COMPRESS_PX_3
  11617. #define COMPAND_COMPRESS_PX_3_MASK 0x000F8000U
  11618. #define COMPAND_COMPRESS_PX_3_SHIFT 15U
  11619. /*! Slice: compand_compress_px_2:*/
  11620. #define COMPAND_COMPRESS_PX_2
  11621. #define COMPAND_COMPRESS_PX_2_MASK 0x00007C00U
  11622. #define COMPAND_COMPRESS_PX_2_SHIFT 10U
  11623. /*! Slice: compand_compress_px_1:*/
  11624. #define COMPAND_COMPRESS_PX_1
  11625. #define COMPAND_COMPRESS_PX_1_MASK 0x000003E0U
  11626. #define COMPAND_COMPRESS_PX_1_SHIFT 5U
  11627. /*! Slice: compand_compress_px_0:*/
  11628. #define COMPAND_COMPRESS_PX_0
  11629. #define COMPAND_COMPRESS_PX_0_MASK 0x0000001FU
  11630. #define COMPAND_COMPRESS_PX_0_SHIFT 0U
  11631. /*! Register: isp_compand_compress_px_1 (0x00003244)*/
  11632. /*! Slice: compand_compress_px_11:*/
  11633. #define COMPAND_COMPRESS_PX_11
  11634. #define COMPAND_COMPRESS_PX_11_MASK 0x3E000000U
  11635. #define COMPAND_COMPRESS_PX_11_SHIFT 25U
  11636. /*! Slice: compand_compress_px_10:*/
  11637. #define COMPAND_COMPRESS_PX_10
  11638. #define COMPAND_COMPRESS_PX_10_MASK 0x01F00000U
  11639. #define COMPAND_COMPRESS_PX_10_SHIFT 20U
  11640. /*! Slice: compand_compress_px_9:*/
  11641. #define COMPAND_COMPRESS_PX_9
  11642. #define COMPAND_COMPRESS_PX_9_MASK 0x000F8000U
  11643. #define COMPAND_COMPRESS_PX_9_SHIFT 15U
  11644. /*! Slice: compand_compress_px_8:*/
  11645. #define COMPAND_COMPRESS_PX_8
  11646. #define COMPAND_COMPRESS_PX_8_MASK 0x00007C00U
  11647. #define COMPAND_COMPRESS_PX_8_SHIFT 10U
  11648. /*! Slice: compand_compress_px_7:*/
  11649. #define COMPAND_COMPRESS_PX_7
  11650. #define COMPAND_COMPRESS_PX_7_MASK 0x000003E0U
  11651. #define COMPAND_COMPRESS_PX_7_SHIFT 5U
  11652. /*! Slice: compand_compress_px_6:*/
  11653. #define COMPAND_COMPRESS_PX_6
  11654. #define COMPAND_COMPRESS_PX_6_MASK 0x0000001FU
  11655. #define COMPAND_COMPRESS_PX_6_SHIFT 0U
  11656. /*! Register: isp_compand_compress_px_2 (0x00003248)*/
  11657. /*! Slice: compand_compress_px_17:*/
  11658. #define COMPAND_COMPRESS_PX_17
  11659. #define COMPAND_COMPRESS_PX_17_MASK 0x3E000000U
  11660. #define COMPAND_COMPRESS_PX_17_SHIFT 25U
  11661. /*! Slice: compand_compress_px_16:*/
  11662. #define COMPAND_COMPRESS_PX_16
  11663. #define COMPAND_COMPRESS_PX_16_MASK 0x01F00000U
  11664. #define COMPAND_COMPRESS_PX_16_SHIFT 20U
  11665. /*! Slice: compand_compress_px_15:*/
  11666. #define COMPAND_COMPRESS_PX_15
  11667. #define COMPAND_COMPRESS_PX_15_MASK 0x000F8000U
  11668. #define COMPAND_COMPRESS_PX_15_SHIFT 15U
  11669. /*! Slice: compand_compress_px_14:*/
  11670. #define COMPAND_COMPRESS_PX_14
  11671. #define COMPAND_COMPRESS_PX_14_MASK 0x00007C00U
  11672. #define COMPAND_COMPRESS_PX_14_SHIFT 10U
  11673. /*! Slice: compand_compress_px_13:*/
  11674. #define COMPAND_COMPRESS_PX_13
  11675. #define COMPAND_COMPRESS_PX_13_MASK 0x000003E0U
  11676. #define COMPAND_COMPRESS_PX_13_SHIFT 5U
  11677. /*! Slice: compand_compress_px_12:*/
  11678. #define COMPAND_COMPRESS_PX_12
  11679. #define COMPAND_COMPRESS_PX_12_MASK 0x0000001FU
  11680. #define COMPAND_COMPRESS_PX_12_SHIFT 0U
  11681. /*! Register: isp_compand_compress_px_3 (0x0000324C)*/
  11682. /*! Slice: compand_compress_px_23:*/
  11683. #define COMPAND_COMPRESS_PX_23
  11684. #define COMPAND_COMPRESS_PX_23_MASK 0x3E000000U
  11685. #define COMPAND_COMPRESS_PX_23_SHIFT 25U
  11686. /*! Slice: compand_compress_px_22:*/
  11687. #define COMPAND_COMPRESS_PX_22
  11688. #define COMPAND_COMPRESS_PX_22_MASK 0x01F00000U
  11689. #define COMPAND_COMPRESS_PX_22_SHIFT 20U
  11690. /*! Slice: compand_compress_px_21:*/
  11691. #define COMPAND_COMPRESS_PX_21
  11692. #define COMPAND_COMPRESS_PX_21_MASK 0x000F8000U
  11693. #define COMPAND_COMPRESS_PX_21_SHIFT 15U
  11694. /*! Slice: compand_compress_px_20:*/
  11695. #define COMPAND_COMPRESS_PX_20
  11696. #define COMPAND_COMPRESS_PX_20_MASK 0x00007C00U
  11697. #define COMPAND_COMPRESS_PX_20_SHIFT 10U
  11698. /*! Slice: compand_compress_px_19:*/
  11699. #define COMPAND_COMPRESS_PX_19
  11700. #define COMPAND_COMPRESS_PX_19_MASK 0x000003E0U
  11701. #define COMPAND_COMPRESS_PX_19_SHIFT 5U
  11702. /*! Slice: compand_compress_px_18:*/
  11703. #define COMPAND_COMPRESS_PX_18
  11704. #define COMPAND_COMPRESS_PX_18_MASK 0x0000001FU
  11705. #define COMPAND_COMPRESS_PX_18_SHIFT 0U
  11706. /*! Register: isp_compand_compress_px_4 (0x00003250)*/
  11707. /*! Slice: compand_compress_px_29:*/
  11708. #define COMPAND_COMPRESS_PX_29
  11709. #define COMPAND_COMPRESS_PX_29_MASK 0x3E000000U
  11710. #define COMPAND_COMPRESS_PX_29_SHIFT 25U
  11711. /*! Slice: compand_compress_px_28:*/
  11712. #define COMPAND_COMPRESS_PX_28
  11713. #define COMPAND_COMPRESS_PX_28_MASK 0x01F00000U
  11714. #define COMPAND_COMPRESS_PX_28_SHIFT 20U
  11715. /*! Slice: compand_compress_px_27:*/
  11716. #define COMPAND_COMPRESS_PX_27
  11717. #define COMPAND_COMPRESS_PX_27_MASK 0x000F8000U
  11718. #define COMPAND_COMPRESS_PX_27_SHIFT 15U
  11719. /*! Slice: compand_compress_px_26:*/
  11720. #define COMPAND_COMPRESS_PX_26
  11721. #define COMPAND_COMPRESS_PX_26_MASK 0x00007C00U
  11722. #define COMPAND_COMPRESS_PX_26_SHIFT 10U
  11723. /*! Slice: compand_compress_px_25:*/
  11724. #define COMPAND_COMPRESS_PX_25
  11725. #define COMPAND_COMPRESS_PX_25_MASK 0x000003E0U
  11726. #define COMPAND_COMPRESS_PX_25_SHIFT 5U
  11727. /*! Slice: compand_compress_px_24:*/
  11728. #define COMPAND_COMPRESS_PX_24
  11729. #define COMPAND_COMPRESS_PX_24_MASK 0x0000001FU
  11730. #define COMPAND_COMPRESS_PX_24_SHIFT 0U
  11731. /*! Register: isp_compand_compress_px_5 (0x00003254)*/
  11732. /*! Slice: compand_compress_px_35:*/
  11733. #define COMPAND_COMPRESS_PX_35
  11734. #define COMPAND_COMPRESS_PX_35_MASK 0x3E000000U
  11735. #define COMPAND_COMPRESS_PX_35_SHIFT 25U
  11736. /*! Slice: compand_compress_px_34:*/
  11737. #define COMPAND_COMPRESS_PX_34
  11738. #define COMPAND_COMPRESS_PX_34_MASK 0x01F00000U
  11739. #define COMPAND_COMPRESS_PX_34_SHIFT 20U
  11740. /*! Slice: compand_compress_px_33:*/
  11741. #define COMPAND_COMPRESS_PX_33
  11742. #define COMPAND_COMPRESS_PX_33_MASK 0x000F8000U
  11743. #define COMPAND_COMPRESS_PX_33_SHIFT 15U
  11744. /*! Slice: compand_compress_px_32:*/
  11745. #define COMPAND_COMPRESS_PX_32
  11746. #define COMPAND_COMPRESS_PX_32_MASK 0x00007C00U
  11747. #define COMPAND_COMPRESS_PX_32_SHIFT 10U
  11748. /*! Slice: compand_compress_px_31:*/
  11749. #define COMPAND_COMPRESS_PX_31
  11750. #define COMPAND_COMPRESS_PX_31_MASK 0x000003E0U
  11751. #define COMPAND_COMPRESS_PX_31_SHIFT 5U
  11752. /*! Slice: compand_compress_px_30:*/
  11753. #define COMPAND_COMPRESS_PX_30
  11754. #define COMPAND_COMPRESS_PX_30_MASK 0x0000001FU
  11755. #define COMPAND_COMPRESS_PX_30_SHIFT 0U
  11756. /*! Register: isp_compand_compress_px_6 (0x00003258)*/
  11757. /*! Slice: compand_compress_px_41:*/
  11758. #define COMPAND_COMPRESS_PX_41
  11759. #define COMPAND_COMPRESS_PX_41_MASK 0x3E000000U
  11760. #define COMPAND_COMPRESS_PX_41_SHIFT 25U
  11761. /*! Slice: compand_compress_px_40:*/
  11762. #define COMPAND_COMPRESS_PX_40
  11763. #define COMPAND_COMPRESS_PX_40_MASK 0x01F00000U
  11764. #define COMPAND_COMPRESS_PX_40_SHIFT 20U
  11765. /*! Slice: compand_compress_px_39:*/
  11766. #define COMPAND_COMPRESS_PX_39
  11767. #define COMPAND_COMPRESS_PX_39_MASK 0x000F8000U
  11768. #define COMPAND_COMPRESS_PX_39_SHIFT 15U
  11769. /*! Slice: compand_compress_px_38:*/
  11770. #define COMPAND_COMPRESS_PX_38
  11771. #define COMPAND_COMPRESS_PX_38_MASK 0x00007C00U
  11772. #define COMPAND_COMPRESS_PX_38_SHIFT 10U
  11773. /*! Slice: compand_compress_px_37:*/
  11774. #define COMPAND_COMPRESS_PX_37
  11775. #define COMPAND_COMPRESS_PX_37_MASK 0x000003E0U
  11776. #define COMPAND_COMPRESS_PX_37_SHIFT 5U
  11777. /*! Slice: compand_compress_px_36:*/
  11778. #define COMPAND_COMPRESS_PX_36
  11779. #define COMPAND_COMPRESS_PX_36_MASK 0x0000001FU
  11780. #define COMPAND_COMPRESS_PX_36_SHIFT 0U
  11781. /*! Register: isp_compand_compress_px_7 (0x0000325C)*/
  11782. /*! Slice: compand_compress_px_47:*/
  11783. #define COMPAND_COMPRESS_PX_47
  11784. #define COMPAND_COMPRESS_PX_47_MASK 0x3E000000U
  11785. #define COMPAND_COMPRESS_PX_47_SHIFT 25U
  11786. /*! Slice: compand_compress_px_46:*/
  11787. #define COMPAND_COMPRESS_PX_46
  11788. #define COMPAND_COMPRESS_PX_46_MASK 0x01F00000U
  11789. #define COMPAND_COMPRESS_PX_46_SHIFT 20U
  11790. /*! Slice: compand_compress_px_45:*/
  11791. #define COMPAND_COMPRESS_PX_45
  11792. #define COMPAND_COMPRESS_PX_45_MASK 0x000F8000U
  11793. #define COMPAND_COMPRESS_PX_45_SHIFT 15U
  11794. /*! Slice: compand_compress_px_44:*/
  11795. #define COMPAND_COMPRESS_PX_44
  11796. #define COMPAND_COMPRESS_PX_44_MASK 0x00007C00U
  11797. #define COMPAND_COMPRESS_PX_44_SHIFT 10U
  11798. /*! Slice: compand_compress_px_43:*/
  11799. #define COMPAND_COMPRESS_PX_43
  11800. #define COMPAND_COMPRESS_PX_43_MASK 0x000003E0U
  11801. #define COMPAND_COMPRESS_PX_43_SHIFT 5U
  11802. /*! Slice: compand_compress_px_42:*/
  11803. #define COMPAND_COMPRESS_PX_42
  11804. #define COMPAND_COMPRESS_PX_42_MASK 0x0000001FU
  11805. #define COMPAND_COMPRESS_PX_42_SHIFT 0U
  11806. /*! Register: isp_compand_compress_px_8 (0x00003260)*/
  11807. /*! Slice: compand_compress_px_53:*/
  11808. #define COMPAND_COMPRESS_PX_53
  11809. #define COMPAND_COMPRESS_PX_53_MASK 0x3E000000U
  11810. #define COMPAND_COMPRESS_PX_53_SHIFT 25U
  11811. /*! Slice: compand_compress_px_52:*/
  11812. #define COMPAND_COMPRESS_PX_52
  11813. #define COMPAND_COMPRESS_PX_52_MASK 0x01F00000U
  11814. #define COMPAND_COMPRESS_PX_52_SHIFT 20U
  11815. /*! Slice: compand_compress_px_51:*/
  11816. #define COMPAND_COMPRESS_PX_51
  11817. #define COMPAND_COMPRESS_PX_51_MASK 0x000F8000U
  11818. #define COMPAND_COMPRESS_PX_51_SHIFT 15U
  11819. /*! Slice: compand_compress_px_50:*/
  11820. #define COMPAND_COMPRESS_PX_50
  11821. #define COMPAND_COMPRESS_PX_50_MASK 0x00007C00U
  11822. #define COMPAND_COMPRESS_PX_50_SHIFT 10U
  11823. /*! Slice: compand_compress_px_49:*/
  11824. #define COMPAND_COMPRESS_PX_49
  11825. #define COMPAND_COMPRESS_PX_49_MASK 0x000003E0U
  11826. #define COMPAND_COMPRESS_PX_49_SHIFT 5U
  11827. /*! Slice: compand_compress_px_48:*/
  11828. #define COMPAND_COMPRESS_PX_48
  11829. #define COMPAND_COMPRESS_PX_48_MASK 0x0000001FU
  11830. #define COMPAND_COMPRESS_PX_48_SHIFT 0U
  11831. /*! Register: isp_compand_compress_px_9 (0x00003264)*/
  11832. /*! Slice: compand_compress_px_59:*/
  11833. #define COMPAND_COMPRESS_PX_59
  11834. #define COMPAND_COMPRESS_PX_59_MASK 0x3E000000U
  11835. #define COMPAND_COMPRESS_PX_59_SHIFT 25U
  11836. /*! Slice: compand_compress_px_58:*/
  11837. #define COMPAND_COMPRESS_PX_58
  11838. #define COMPAND_COMPRESS_PX_58_MASK 0x01F00000U
  11839. #define COMPAND_COMPRESS_PX_58_SHIFT 20U
  11840. /*! Slice: compand_compress_px_57:*/
  11841. #define COMPAND_COMPRESS_PX_57
  11842. #define COMPAND_COMPRESS_PX_57_MASK 0x000F8000U
  11843. #define COMPAND_COMPRESS_PX_57_SHIFT 15U
  11844. /*! Slice: compand_compress_px_56:*/
  11845. #define COMPAND_COMPRESS_PX_56
  11846. #define COMPAND_COMPRESS_PX_56_MASK 0x00007C00U
  11847. #define COMPAND_COMPRESS_PX_56_SHIFT 10U
  11848. /*! Slice: compand_compress_px_55:*/
  11849. #define COMPAND_COMPRESS_PX_55
  11850. #define COMPAND_COMPRESS_PX_55_MASK 0x000003E0U
  11851. #define COMPAND_COMPRESS_PX_55_SHIFT 5U
  11852. /*! Slice: compand_compress_px_54:*/
  11853. #define COMPAND_COMPRESS_PX_54
  11854. #define COMPAND_COMPRESS_PX_54_MASK 0x0000001FU
  11855. #define COMPAND_COMPRESS_PX_54_SHIFT 0U
  11856. /*! Register: isp_compand_compress_px_10 (0x00003268)*/
  11857. /*! Slice: compand_compress_px_63:*/
  11858. #define COMPAND_COMPRESS_PX_63
  11859. #define COMPAND_COMPRESS_PX_63_MASK 0x000F8000U
  11860. #define COMPAND_COMPRESS_PX_63_SHIFT 15U
  11861. /*! Slice: compand_compress_px_62:*/
  11862. #define COMPAND_COMPRESS_PX_62
  11863. #define COMPAND_COMPRESS_PX_62_MASK 0x00007C00U
  11864. #define COMPAND_COMPRESS_PX_62_SHIFT 10U
  11865. /*! Slice: compand_compress_px_61:*/
  11866. #define COMPAND_COMPRESS_PX_61
  11867. #define COMPAND_COMPRESS_PX_61_MASK 0x000003E0U
  11868. #define COMPAND_COMPRESS_PX_61_SHIFT 5U
  11869. /*! Slice: compand_compress_px_60:*/
  11870. #define COMPAND_COMPRESS_PX_60
  11871. #define COMPAND_COMPRESS_PX_60_MASK 0x0000001FU
  11872. #define COMPAND_COMPRESS_PX_60_SHIFT 0U
  11873. /*! Register: isp_compand_expand_y_addr (0x0000326C)*/
  11874. /*! Slice: compand_expand_y_addr:*/
  11875. #define COMPAND_EXPAND_Y_ADDR
  11876. #define COMPAND_EXPAND_Y_ADDR_MASK 0xFFFFFFFFU
  11877. #define COMPAND_EXPAND_Y_ADDR_SHIFT 0U
  11878. /*! Register: isp_compand_expand_y_write_data (0x00003270)*/
  11879. /*! Slice: compand_expand_y_write_data:*/
  11880. #define COMPAND_EXPAND_Y_WRITE_DATA
  11881. #define COMPAND_EXPAND_Y_WRITE_DATA_MASK 0x000FFFFFU
  11882. #define COMPAND_EXPAND_Y_WRITE_DATA_SHIFT 0U
  11883. /*! Register: isp_compand_compress_y_addr (0x00003274)*/
  11884. /*! Slice: compand_compress_y_addr:*/
  11885. #define COMPAND_COMPRESS_Y_ADDR
  11886. #define COMPAND_COMPRESS_Y_ADDR_MASK 0xFFFFFFFFU
  11887. #define COMPAND_COMPRESS_Y_ADDR_SHIFT 0U
  11888. /*! Register: isp_compand_compress_y_write_data (0x00003278)*/
  11889. /*! Slice: compand_compress_y_write_data:*/
  11890. #define COMPAND_COMPRESS_Y_WRITE_DATA
  11891. #define COMPAND_COMPRESS_Y_WRITE_DATA_MASK 0x0000FFFFU
  11892. #define COMPAND_COMPRESS_Y_WRITE_DATA_SHIFT 0U
  11893. /*! Register: isp_compand_expand_x_addr (0x0000327C)*/
  11894. /*! Slice: compand_expand_x_addr:*/
  11895. #define COMPAND_EXPAND_X_ADDR
  11896. #define COMPAND_EXPAND_X_ADDR_MASK 0xFFFFFFFFU
  11897. #define COMPAND_EXPAND_X_ADDR_SHIFT 0U
  11898. /*! Register: isp_compand_expand_x_write_data (0x00003280)*/
  11899. /*! Slice: compand_expand_x_write_data:*/
  11900. #define COMPAND_EXPAND_X_WRITE_DATA
  11901. #define COMPAND_EXPAND_X_WRITE_DATA_MASK 0x000FFFFFU
  11902. #define COMPAND_EXPAND_X_WRITE_DATA_SHIFT 0U
  11903. /*! Register: isp_compand_compress_x_addr (0x00003284)*/
  11904. /*! Slice: compand_compress_x_addr:*/
  11905. #define COMPAND_COMPRESS_X_ADDR
  11906. #define COMPAND_COMPRESS_X_ADDR_MASK 0xFFFFFFFFU
  11907. #define COMPAND_COMPRESS_X_ADDR_SHIFT 0U
  11908. /*! Register: isp_compand_compress_x_write_data (0x00003288)*/
  11909. /*! Slice: compand_compress_x_write_data:*/
  11910. #define COMPAND_COMPRESS_X_WRITE_DATA
  11911. #define COMPAND_COMPRESS_X_WRITE_DATA_MASK 0x000FFFFFU
  11912. #define COMPAND_COMPRESS_X_WRITE_DATA_SHIFT 0U
  11913. /*! Register: isp_wdr3_ctrl (0x00003500)*/
  11914. /*! Slice: wdr3_dummmy_blk:*/
  11915. #define WDR3_DUMMY_BLK
  11916. #define WDR3_DUMMY_BLK_MASK 0xffff0000U
  11917. #define WDR3_DUMMY_BLK_SHIFT 16U
  11918. /*! Register: isp_wdr3_ctrl (0x00003500)*/
  11919. /*! Slice: wdr3_dummy_blk_en:*/
  11920. #define WDR3_DUMMY_BLK_EN
  11921. #define WDR3_DUMMY_BLK_EN_MASK 0x00008000U
  11922. #define WDR3_DUMMY_BLK_EN_SHIFT 15U
  11923. /*! Register: isp_wdr3_ctrl (0x00003500)*/
  11924. /*! Slice: wdr3_interrupt_en:*/
  11925. #define WDR3_INTERRUPT_EN
  11926. #define WDR3_INTERRUPT_EN_MASK 0x00000200U
  11927. #define WDR3_INTERRUPT_EN_SHIFT 9U
  11928. /*! Slice: wdr3_soft_reset_flag:*/
  11929. #define WDR3_SOFT_RESET_FLAG
  11930. #define WDR3_SOFT_RESET_FLAG_MASK 0x00000002U
  11931. #define WDR3_SOFT_RESET_FLAG_SHIFT 1U
  11932. /*! Slice: wdr3_enable:*/
  11933. #define WDR3_ENABLE
  11934. #define WDR3_ENABLE_MASK 0x00000001U
  11935. #define WDR3_ENABLE_SHIFT 0U
  11936. /*! Register: isp_wdr3_shift (0x00003504)*/
  11937. /*! Slice: wdr3_gain_shift_bit:*/
  11938. #define WDR3_GAIN_SHIFT_BIT
  11939. #define WDR3_GAIN_SHIFT_BIT_MASK 0x00FC0000U
  11940. #define WDR3_GAIN_SHIFT_BIT_SHIFT 18U
  11941. /*! Slice: wdr3_normalize_shift_bit:*/
  11942. #define WDR3_NORMALIZE_SHIFT_BIT
  11943. #define WDR3_NORMALIZE_SHIFT_BIT_MASK 0x0003F000U
  11944. #define WDR3_NORMALIZE_SHIFT_BIT_SHIFT 12U
  11945. /*! Slice: wdr3_output_shift_bit:*/
  11946. #define WDR3_OUTPUT_SHIFT_BIT
  11947. #define WDR3_OUTPUT_SHIFT_BIT_MASK 0x00000FC0U
  11948. #define WDR3_OUTPUT_SHIFT_BIT_SHIFT 6U
  11949. /*! Slice: wdr3_pixel_shift_bit:*/
  11950. #define WDR3_PIXEL_SHIFT_BIT
  11951. #define WDR3_PIXEL_SHIFT_BIT_MASK 0x0000003FU
  11952. #define WDR3_PIXEL_SHIFT_BIT_SHIFT 0U
  11953. /*! Register: isp_wdr3_block_size (0x00003508)*/
  11954. /*! Slice: wdr3_block_height:*/
  11955. #define WDR3_BLOCK_HEIGHT
  11956. #define WDR3_BLOCK_HEIGHT_MASK 0x0003FE00U
  11957. #define WDR3_BLOCK_HEIGHT_SHIFT 9U
  11958. /*! Slice: wdr3_block_width:*/
  11959. #define WDR3_BLOCK_WIDTH
  11960. #define WDR3_BLOCK_WIDTH_MASK 0x000001FFU
  11961. #define WDR3_BLOCK_WIDTH_SHIFT 0U
  11962. /*! Register: isp_wdr3_block_area_factor (0x0000350C)*/
  11963. /*! Slice: wdr3_block_area_inverse:*/
  11964. #define WDR3_BLOCK_AREA_INVERSE
  11965. #define WDR3_BLOCK_AREA_INVERSE_MASK 0x000FFFFFU
  11966. #define WDR3_BLOCK_AREA_INVERSE_SHIFT 0U
  11967. /*! Register: isp_wdr3_value_weight (0x00003510)*/
  11968. /*! Slice: wdr3_value_weight_3:*/
  11969. #define WDR3_VALUE_WEIGHT_3
  11970. #define WDR3_VALUE_WEIGHT_3_MASK 0x000F8000U
  11971. #define WDR3_VALUE_WEIGHT_3_SHIFT 15U
  11972. /*! Slice: wdr3_value_weight_2:*/
  11973. #define WDR3_VALUE_WEIGHT_2
  11974. #define WDR3_VALUE_WEIGHT_2_MASK 0x00007C00U
  11975. #define WDR3_VALUE_WEIGHT_2_SHIFT 10U
  11976. /*! Slice: wdr3_value_weight_1:*/
  11977. #define WDR3_VALUE_WEIGHT_1
  11978. #define WDR3_VALUE_WEIGHT_1_MASK 0x000003E0U
  11979. #define WDR3_VALUE_WEIGHT_1_SHIFT 5U
  11980. /*! Slice: wdr3_value_weight_0:*/
  11981. #define WDR3_VALUE_WEIGHT_0
  11982. #define WDR3_VALUE_WEIGHT_0_MASK 0x0000001FU
  11983. #define WDR3_VALUE_WEIGHT_0_SHIFT 0U
  11984. /*! Register: isp_wdr3_strength (0x00003514)*/
  11985. /*! Slice: wdr3_total_strength:*/
  11986. #define WDR3_TOTAL_STRENGTH
  11987. #define WDR3_TOTAL_STRENGTH_MASK 0xFF000000U
  11988. #define WDR3_TOTAL_STRENGTH_SHIFT 24U
  11989. /*! Slice: wdr3_local_strength:*/
  11990. #define WDR3_LOCAL_STRENGTH
  11991. #define WDR3_LOCAL_STRENGTH_MASK 0x00FF0000U
  11992. #define WDR3_LOCAL_STRENGTH_SHIFT 16U
  11993. /*! Slice: wdr3_global_strength:*/
  11994. #define WDR3_GLOBAL_STRENGTH
  11995. #define WDR3_GLOBAL_STRENGTH_MASK 0x0000FF00U
  11996. #define WDR3_GLOBAL_STRENGTH_SHIFT 8U
  11997. /*! Slice: wdr3_maximum_gain:*/
  11998. #define WDR3_MAXIMUM_GAIN
  11999. #define WDR3_MAXIMUM_GAIN_MASK 0x000000FFU
  12000. #define WDR3_MAXIMUM_GAIN_SHIFT 0U
  12001. /*! Register: isp_wdr3_pixel_slope (0x00003518)*/
  12002. /*! Slice: wdr3_pixel_merge_slope:*/
  12003. #define WDR3_PIXEL_MERGE_SLOPE
  12004. #define WDR3_PIXEL_MERGE_SLOPE_MASK 0xFF000000U
  12005. #define WDR3_PIXEL_MERGE_SLOPE_SHIFT 24U
  12006. /*! Slice: wdr3_pixel_merge_base:*/
  12007. #define WDR3_PIXEL_MERGE_BASE
  12008. #define WDR3_PIXEL_MERGE_BASE_MASK 0x00FF0000U
  12009. #define WDR3_PIXEL_MERGE_BASE_SHIFT 16U
  12010. /*! Slice: wdr3_pixel_adjust_slope:*/
  12011. #define WDR3_PIXEL_ADJUST_SLOPE
  12012. #define WDR3_PIXEL_ADJUST_SLOPE_MASK 0x0000FF00U
  12013. #define WDR3_PIXEL_ADJUST_SLOPE_SHIFT 8U
  12014. /*! Slice: wdr3_pixel_adjust_base:*/
  12015. #define WDR3_PIXEL_ADJUST_BASE
  12016. #define WDR3_PIXEL_ADJUST_BASE_MASK 0x000000FFU
  12017. #define WDR3_PIXEL_ADJUST_BASE_SHIFT 0U
  12018. /*! Register: isp_wdr3_entropy_slope (0x0000351C)*/
  12019. /*! Slice: wdr3_entropy_slope:*/
  12020. #define WDR3_ENTROPY_SLOPE
  12021. #define WDR3_ENTROPY_SLOPE_MASK 0x000FFC00U
  12022. #define WDR3_ENTROPY_SLOPE_SHIFT 10U
  12023. /*! Slice: wdr3_entropy_base:*/
  12024. #define WDR3_ENTROPY_BASE
  12025. #define WDR3_ENTROPY_BASE_MASK 0x000003FFU
  12026. #define WDR3_ENTROPY_BASE_SHIFT 0U
  12027. /*! Register: isp_wdr3_sigma_width (0x00003520)*/
  12028. /*! Slice: wdr3_biliteral_width_sigma:*/
  12029. #define WDR3_BILITERAL_WIDTH_SIGMA
  12030. #define WDR3_BILITERAL_WIDTH_SIGMA_MASK 0x000FFFFFU
  12031. #define WDR3_BILITERAL_WIDTH_SIGMA_SHIFT 0U
  12032. /*! Register: isp_wdr3_sigma_height (0x00003524)*/
  12033. /*! Slice: wdr3_biliteral_height_sigma:*/
  12034. #define WDR3_BILITERAL_HEIGHT_SIGMA
  12035. #define WDR3_BILITERAL_HEIGHT_SIGMA_MASK 0x000FFFFFU
  12036. #define WDR3_BILITERAL_HEIGHT_SIGMA_SHIFT 0U
  12037. /*! Register: isp_wdr3_sigma_value (0x00003528)*/
  12038. /*! Slice: wdr3_biliteral_value_sigma:*/
  12039. #define WDR3_BILITERAL_VALUE_SIGMA
  12040. #define WDR3_BILITERAL_VALUE_SIGMA_MASK 0x000FFFFFU
  12041. #define WDR3_BILITERAL_VALUE_SIGMA_SHIFT 0U
  12042. /*! Register: isp_wdr3_block_flag_width (0x0000352C)*/
  12043. /*! Slice: wdr3_block_col_flag:*/
  12044. #define WDR3_BLOCK_COL_FLAG
  12045. #define WDR3_BLOCK_COL_FLAG_MASK 0xFFFFFFFFU
  12046. #define WDR3_BLOCK_COL_FLAG_SHIFT 0U
  12047. /*! Register: isp_wdr3_block_flag_height (0x00003530)*/
  12048. /*! Slice: wdr3_block_row_flag:*/
  12049. #define WDR3_BLOCK_ROW_FLAG
  12050. #define WDR3_BLOCK_ROW_FLAG_MASK 0xFFFFFFFFU
  12051. #define WDR3_BLOCK_ROW_FLAG_SHIFT 0U
  12052. /*! Register: isp_wdr3_frame_average (0x00003534)*/
  12053. /*! Slice: wdr3_frame_average:*/
  12054. #define WDR3_FRAME_AVERAGE
  12055. #define WDR3_FRAME_AVERAGE_MASK 0xFFFFFFFFU
  12056. #define WDR3_FRAME_AVERAGE_SHIFT 0U
  12057. /*! Register: isp_wdr3_frame_std (0x00003538)*/
  12058. /*! Slice: wdr3_frame_std:*/
  12059. #define WDR3_FRAME_STD
  12060. #define WDR3_FRAME_STD_MASK 0xFFFFFFFFU
  12061. #define WDR3_FRAME_STD_SHIFT 0U
  12062. /*! Register: isp_wdr3_histogram_0 (0x0000353C)*/
  12063. /*! Slice: wdr3_histogram_curve0:*/
  12064. #define WDR3_HISTOGRAM_CURVE0
  12065. #define WDR3_HISTOGRAM_CURVE0_MASK 0x3FF00000U
  12066. #define WDR3_HISTOGRAM_CURVE0_SHIFT 20U
  12067. /*! Slice: wdr3_histogram_curve1:*/
  12068. #define WDR3_HISTOGRAM_CURVE1
  12069. #define WDR3_HISTOGRAM_CURVE1_MASK 0x000FFC00U
  12070. #define WDR3_HISTOGRAM_CURVE1_SHIFT 10U
  12071. /*! Slice: wdr3_histogram_curve2:*/
  12072. #define WDR3_HISTOGRAM_CURVE2
  12073. #define WDR3_HISTOGRAM_CURVE2_MASK 0x000003FFU
  12074. #define WDR3_HISTOGRAM_CURVE2_SHIFT 0U
  12075. /*! Register: isp_wdr3_entropy_0 (0x00003550)*/
  12076. /*! Slice: wdr3_entropy_convert0:*/
  12077. #define WDR3_ENTROPY_CONVERT0
  12078. #define WDR3_ENTROPY_CONVERT0_MASK 0x07FC0000U
  12079. #define WDR3_ENTROPY_CONVERT0_SHIFT 18U
  12080. /*! Slice: wdr3_entropy_convert1:*/
  12081. #define WDR3_ENTROPY_CONVERT1
  12082. #define WDR3_ENTROPY_CONVERT1_MASK 0x0003FE00U
  12083. #define WDR3_ENTROPY_CONVERT1_SHIFT 9U
  12084. /*! Slice: wdr3_entropy_convert2:*/
  12085. #define WDR3_ENTROPY_CONVERT2
  12086. #define WDR3_ENTROPY_CONVERT2_MASK 0x000001FFU
  12087. #define WDR3_ENTROPY_CONVERT2_SHIFT 0U
  12088. /*! Register: isp_wdr3_gamma_pre_0 (0x00003564)*/
  12089. /*! Slice: wdr3_gamma_pre_curve0:*/
  12090. #define WDR3_GAMMA_PRE_CURVE0
  12091. #define WDR3_GAMMA_PRE_CURVE0_MASK 0x3FF00000U
  12092. #define WDR3_GAMMA_PRE_CURVE0_SHIFT 20U
  12093. /*! Slice: wdr3_gamma_pre_curve1:*/
  12094. #define WDR3_GAMMA_PRE_CURVE1
  12095. #define WDR3_GAMMA_PRE_CURVE1_MASK 0x000FFC00U
  12096. #define WDR3_GAMMA_PRE_CURVE1_SHIFT 10U
  12097. /*! Slice: wdr3_gamma_pre_curve2:*/
  12098. #define WDR3_GAMMA_PRE_CURVE2
  12099. #define WDR3_GAMMA_PRE_CURVE2_MASK 0x000003FFU
  12100. #define WDR3_GAMMA_PRE_CURVE2_SHIFT 0U
  12101. /*! Register: isp_wdr3_gamma_up_0 (0x00003578)*/
  12102. /*! Slice: wdr3_gamma_up_curve0:*/
  12103. #define WDR3_GAMMA_UP_CURVE0
  12104. #define WDR3_GAMMA_UP_CURVE0_MASK 0x3FF00000U
  12105. #define WDR3_GAMMA_UP_CURVE0_SHIFT 20U
  12106. /*! Slice: wdr3_gamma_up_curve1:*/
  12107. #define WDR3_GAMMA_UP_CURVE1
  12108. #define WDR3_GAMMA_UP_CURVE1_MASK 0x000FFC00U
  12109. #define WDR3_GAMMA_UP_CURVE1_SHIFT 10U
  12110. /*! Slice: wdr3_gamma_up_curve2:*/
  12111. #define WDR3_GAMMA_UP_CURVE2
  12112. #define WDR3_GAMMA_UP_CURVE2_MASK 0x000003FFU
  12113. #define WDR3_GAMMA_UP_CURVE2_SHIFT 0U
  12114. /*! Register: isp_wdr3_gamma_down_0 (0x0000358C)*/
  12115. /*! Slice: wdr3_gamma_down_curve0:*/
  12116. #define WDR3_GAMMA_DOWN_CURVE0
  12117. #define WDR3_GAMMA_DOWN_CURVE0_MASK 0x3FF00000U
  12118. #define WDR3_GAMMA_DOWN_CURVE0_SHIFT 20U
  12119. /*! Slice: wdr3_gamma_down_curve1:*/
  12120. #define WDR3_GAMMA_DOWN_CURVE1
  12121. #define WDR3_GAMMA_DOWN_CURVE1_MASK 0x000FFC00U
  12122. #define WDR3_GAMMA_DOWN_CURVE1_SHIFT 10U
  12123. /*! Slice: wdr3_gamma_down_curve2:*/
  12124. #define WDR3_GAMMA_DOWN_CURVE2
  12125. #define WDR3_GAMMA_DOWN_CURVE2_MASK 0x000003FFU
  12126. #define WDR3_GAMMA_DOWN_CURVE2_SHIFT 0U
  12127. /*! Register: isp_wdr3_distance_weight_0 (0x000035A0)*/
  12128. /*! Slice: wdr3_distance_weight_curve0:*/
  12129. #define WDR3_DISTANCE_WEIGHT_CURVE0
  12130. #define WDR3_DISTANCE_WEIGHT_CURVE0_MASK 0x001FC000U
  12131. #define WDR3_DISTANCE_WEIGHT_CURVE0_SHIFT 14U
  12132. /*! Slice: wdr3_distance_weight_curve1:*/
  12133. #define WDR3_DISTANCE_WEIGHT_CURVE1
  12134. #define WDR3_DISTANCE_WEIGHT_CURVE1_MASK 0x00003F80U
  12135. #define WDR3_DISTANCE_WEIGHT_CURVE1_SHIFT 7U
  12136. /*! Slice: wdr3_distance_weight_curve2:*/
  12137. #define WDR3_DISTANCE_WEIGHT_CURVE2
  12138. #define WDR3_DISTANCE_WEIGHT_CURVE2_MASK 0x0000007FU
  12139. #define WDR3_DISTANCE_WEIGHT_CURVE2_SHIFT 0U
  12140. /*! Register: isp_wdr3_difference_weight_0 (0x000035B4)*/
  12141. /*! Slice: wdr3_difference_weight_curve0:*/
  12142. #define WDR3_DIFFERENCE_WEIGHT_CURVE0
  12143. #define WDR3_DIFFERENCE_WEIGHT_CURVE0_MASK 0x001FC000U
  12144. #define WDR3_DIFFERENCE_WEIGHT_CURVE0_SHIFT 14U
  12145. /*! Slice: wdr3_difference_weight_curve1:*/
  12146. #define WDR3_DIFFERENCE_WEIGHT_CURVE1
  12147. #define WDR3_DIFFERENCE_WEIGHT_CURVE1_MASK 0x00003F80U
  12148. #define WDR3_DIFFERENCE_WEIGHT_CURVE1_SHIFT 7U
  12149. /*! Slice: wdr3_difference_weight_curve2:*/
  12150. #define WDR3_DIFFERENCE_WEIGHT_CURVE2
  12151. #define WDR3_DIFFERENCE_WEIGHT_CURVE2_MASK 0x0000007FU
  12152. #define WDR3_DIFFERENCE_WEIGHT_CURVE2_SHIFT 0U
  12153. /*! Register: isp_wdr3_invert_curve_0 (0x000035C8)*/
  12154. /*! Slice: wdr3_global_curve_invert0:*/
  12155. #define WDR3_GLOBAL_CURVE_INVERT0
  12156. #define WDR3_GLOBAL_CURVE_INVERT0_MASK 0x00FFF000U
  12157. #define WDR3_GLOBAL_CURVE_INVERT0_SHIFT 12U
  12158. /*! Slice: wdr3_global_curve_invert1:*/
  12159. #define WDR3_GLOBAL_CURVE_INVERT1
  12160. #define WDR3_GLOBAL_CURVE_INVERT1_MASK 0x00000FFFU
  12161. #define WDR3_GLOBAL_CURVE_INVERT1_SHIFT 0U
  12162. /*! Register: isp_wdr3_invert_curve_1 (0x000035CC)*/
  12163. /*! Slice: wdr3_global_curve_invert2:*/
  12164. #define WDR3_GLOBAL_CURVE_INVERT2
  12165. #define WDR3_GLOBAL_CURVE_INVERT2_MASK 0x00FFF000U
  12166. #define WDR3_GLOBAL_CURVE_INVERT2_SHIFT 12U
  12167. /*! Register: isp_wdr3_invert_linear_0 (0x000035E4)*/
  12168. /*! Slice: wdr3_linear_curve_invert0:*/
  12169. #define WDR3_LINEAR_CURVE_INVERT0
  12170. #define WDR3_LINEAR_CURVE_INVERT0_MASK 0x00FFF000U
  12171. #define WDR3_LINEAR_CURVE_INVERT0_SHIFT 12U
  12172. /*! Slice: wdr3_linear_curve_invert1:*/
  12173. #define WDR3_LINEAR_CURVE_INVERT1
  12174. #define WDR3_LINEAR_CURVE_INVERT1_MASK 0x00000FFFU
  12175. #define WDR3_LINEAR_CURVE_INVERT1_SHIFT 0U
  12176. /*! Register: isp_wdr3_invert_linear_1 (0x000035E8)*/
  12177. /*! Slice: wdr3_linear_curve_invert2:*/
  12178. #define WDR3_LINEAR_CURVE_INVERT2
  12179. #define WDR3_LINEAR_CURVE_INVERT2_MASK 0x00FFF000U
  12180. #define WDR3_LINEAR_CURVE_INVERT2_SHIFT 12U
  12181. /*! Register: isp_wdr3_shift_0 (0x00003600)*/
  12182. /*! Slice: wdr3_histogram_shift0:*/
  12183. #define WDR3_HISTOGRAM_SHIFT0
  12184. #define WDR3_HISTOGRAM_SHIFT0_MASK 0xF0000000U
  12185. #define WDR3_HISTOGRAM_SHIFT0_SHIFT 28U
  12186. /*! Slice: wdr3_histogram_shift1:*/
  12187. #define WDR3_HISTOGRAM_SHIFT1
  12188. #define WDR3_HISTOGRAM_SHIFT1_MASK 0x0F000000U
  12189. #define WDR3_HISTOGRAM_SHIFT1_SHIFT 24U
  12190. /*! Slice: wdr3_histogram_shift2:*/
  12191. #define WDR3_HISTOGRAM_SHIFT2
  12192. #define WDR3_HISTOGRAM_SHIFT2_MASK 0x00F00000U
  12193. #define WDR3_HISTOGRAM_SHIFT2_SHIFT 20U
  12194. /*! Slice: wdr3_histogram_shift3:*/
  12195. #define WDR3_HISTOGRAM_SHIFT3
  12196. #define WDR3_HISTOGRAM_SHIFT3_MASK 0x000F0000U
  12197. #define WDR3_HISTOGRAM_SHIFT3_SHIFT 16U
  12198. /*! Slice: wdr3_histogram_shift4:*/
  12199. #define WDR3_HISTOGRAM_SHIFT4
  12200. #define WDR3_HISTOGRAM_SHIFT4_MASK 0x0000F000U
  12201. #define WDR3_HISTOGRAM_SHIFT4_SHIFT 12U
  12202. /*! Slice: wdr3_histogram_shift5:*/
  12203. #define WDR3_HISTOGRAM_SHIFT5
  12204. #define WDR3_HISTOGRAM_SHIFT5_MASK 0x00000F00U
  12205. #define WDR3_HISTOGRAM_SHIFT5_SHIFT 8U
  12206. /*! Slice: wdr3_histogram_shift6:*/
  12207. #define WDR3_HISTOGRAM_SHIFT6
  12208. #define WDR3_HISTOGRAM_SHIFT6_MASK 0x000000F0U
  12209. #define WDR3_HISTOGRAM_SHIFT6_SHIFT 4U
  12210. /*! Slice: wdr3_histogram_shift7:*/
  12211. #define WDR3_HISTOGRAM_SHIFT7
  12212. #define WDR3_HISTOGRAM_SHIFT7_MASK 0x0000000FU
  12213. #define WDR3_HISTOGRAM_SHIFT7_SHIFT 0U
  12214. /*! Register: isp_wdr3_shift_1 (0x00003604)*/
  12215. /*! Slice: wdr3_histogram_shift8:*/
  12216. #define WDR3_HISTOGRAM_SHIFT8
  12217. #define WDR3_HISTOGRAM_SHIFT8_MASK 0x00F00000U
  12218. #define WDR3_HISTOGRAM_SHIFT8_SHIFT 20U
  12219. /*! Slice: wdr3_histogram_shift9:*/
  12220. #define WDR3_HISTOGRAM_SHIFT9
  12221. #define WDR3_HISTOGRAM_SHIFT9_MASK 0x000F0000U
  12222. #define WDR3_HISTOGRAM_SHIFT9_SHIFT 16U
  12223. /*! Slice: wdr3_histogram_shift10:*/
  12224. #define WDR3_HISTOGRAM_SHIFT10
  12225. #define WDR3_HISTOGRAM_SHIFT10_MASK 0x0000F000U
  12226. #define WDR3_HISTOGRAM_SHIFT10_SHIFT 12U
  12227. /*! Slice: wdr3_histogram_shift11:*/
  12228. #define WDR3_HISTOGRAM_SHIFT11
  12229. #define WDR3_HISTOGRAM_SHIFT11_MASK 0x00000F00U
  12230. #define WDR3_HISTOGRAM_SHIFT11_SHIFT 8U
  12231. /*! Slice: wdr3_histogram_shift12:*/
  12232. #define WDR3_HISTOGRAM_SHIFT12
  12233. #define WDR3_HISTOGRAM_SHIFT12_MASK 0x000000F0U
  12234. #define WDR3_HISTOGRAM_SHIFT12_SHIFT 4U
  12235. /*! Slice: wdr3_histogram_shift13:*/
  12236. #define WDR3_HISTOGRAM_SHIFT13
  12237. #define WDR3_HISTOGRAM_SHIFT13_MASK 0x0000000FU
  12238. #define WDR3_HISTOGRAM_SHIFT13_SHIFT 0U
  12239. /*! Register: isp_wdr3_strength_shd (0x00003608)*/
  12240. /*! Slice: wdr3_total_strength_shd:*/
  12241. #define WDR3_TOTAL_STRENGTH_SHD
  12242. #define WDR3_TOTAL_STRENGTH_SHD_MASK 0xFF000000U
  12243. #define WDR3_TOTAL_STRENGTH_SHD_SHIFT 24U
  12244. /*! Slice: wdr3_local_strength_shd:*/
  12245. #define WDR3_LOCAL_STRENGTH_SHD
  12246. #define WDR3_LOCAL_STRENGTH_SHD_MASK 0x00FF0000U
  12247. #define WDR3_LOCAL_STRENGTH_SHD_SHIFT 16U
  12248. /*! Slice: wdr3_global_strength_shd:*/
  12249. #define WDR3_GLOBAL_STRENGTH_SHD
  12250. #define WDR3_GLOBAL_STRENGTH_SHD_MASK 0x0000FF00U
  12251. #define WDR3_GLOBAL_STRENGTH_SHD_SHIFT 8U
  12252. /*! Slice: wdr3_maximum_gain_shd:*/
  12253. #define WDR3_MAXIMUM_GAIN_SHD
  12254. #define WDR3_MAXIMUM_GAIN_SHD_MASK 0x000000FFU
  12255. #define WDR3_MAXIMUM_GAIN_SHD_SHIFT 0U
  12256. /*! Register: isp_wdr3_pixel_slope_shd (0x0000360C)*/
  12257. /*! Slice: wdr3_pixel_merge_slope_shd:*/
  12258. #define WDR3_PIXEL_MERGE_SLOPE_SHD
  12259. #define WDR3_PIXEL_MERGE_SLOPE_SHD_MASK 0xFF000000U
  12260. #define WDR3_PIXEL_MERGE_SLOPE_SHD_SHIFT 24U
  12261. /*! Slice: wdr3_pixel_merge_base_shd:*/
  12262. #define WDR3_PIXEL_MERGE_BASE_SHD
  12263. #define WDR3_PIXEL_MERGE_BASE_SHD_MASK 0x00FF0000U
  12264. #define WDR3_PIXEL_MERGE_BASE_SHD_SHIFT 16U
  12265. /*! Slice: wdr3_pixel_adjust_slope_shd:*/
  12266. #define WDR3_PIXEL_ADJUST_SLOPE_SHD
  12267. #define WDR3_PIXEL_ADJUST_SLOPE_SHD_MASK 0x0000FF00U
  12268. #define WDR3_PIXEL_ADJUST_SLOPE_SHD_SHIFT 8U
  12269. /*! Slice: wdr3_pixel_adjust_base_shd:*/
  12270. #define WDR3_PIXEL_ADJUST_BASE_SHD
  12271. #define WDR3_PIXEL_ADJUST_BASE_SHD_MASK 0x000000FFU
  12272. #define WDR3_PIXEL_ADJUST_BASE_SHD_SHIFT 0U
  12273. /*! Register: isp_wdr3_entropy_slope_shd (0x00003610)*/
  12274. /*! Slice: wdr3_entropy_slope_shd:*/
  12275. #define WDR3_ENTROPY_SLOPE_SHD
  12276. #define WDR3_ENTROPY_SLOPE_SHD_MASK 0x000FFC00U
  12277. #define WDR3_ENTROPY_SLOPE_SHD_SHIFT 10U
  12278. /*! Slice: wdr3_entropy_base_shd:*/
  12279. #define WDR3_ENTROPY_BASE_SHD
  12280. #define WDR3_ENTROPY_BASE_SHD_MASK 0x000003FFU
  12281. #define WDR3_ENTROPY_BASE_SHD_SHIFT 0U
  12282. /* TPG */
  12283. /*! Register: isp_tpg_ctrl (0x00000700)*/
  12284. /*! Slice: tpg_resolution:*/
  12285. #define TPG_RESOLUTION
  12286. #define TPG_RESOLUTION_MASK 0x00000C00U
  12287. #define TPG_RESOLUTION_SHIFT 10U
  12288. /*! Slice: tpg_max_sync:*/
  12289. #define TPG_MAX_SYNC
  12290. #define TPG_MAX_SYNC_MASK 0x00000200U
  12291. #define TPG_MAX_SYNC_SHIFT 9U
  12292. /*! Slice: tpg_def_sync:*/
  12293. #define TPG_DEF_SYNC
  12294. #define TPG_DEF_SYNC_MASK 0x00000100U
  12295. #define TPG_DEF_SYNC_SHIFT 8U
  12296. /*! Slice: tpg_color_depth:*/
  12297. #define TPG_COLOR_DEPTH
  12298. #define TPG_COLOR_DEPTH_MASK 0x000000C0U
  12299. #define TPG_COLOR_DEPTH_SHIFT 6U
  12300. /*! Slice: tpg_cfa_pat:*/
  12301. #define TPG_CFA_PAT
  12302. #define TPG_CFA_PAT_MASK 0x00000030U
  12303. #define TPG_CFA_PAT_SHIFT 4U
  12304. /*! Slice: tpg_img_num:*/
  12305. #define TPG_IMG_NUM
  12306. #define TPG_IMG_NUM_MASK 0x0000000EU
  12307. #define TPG_IMG_NUM_SHIFT 1U
  12308. /*! Slice: tpg_frame_num:*/
  12309. #define TPG_FRAME_NUM
  12310. #define TPG_FRAME_NUM_MASK 0xFFFF0000U
  12311. #define TPG_FRAME_NUM_SHIFT 16U
  12312. /*! Slice: tpg_enable:*/
  12313. #define TPG_ENABLE
  12314. #define TPG_ENABLE_MASK 0x00000001U
  12315. #define TPG_ENABLE_SHIFT 0U
  12316. /*! Register: isp_tpg_total_in (0x00000704)*/
  12317. /*! Slice: tpg_htotal_in:*/
  12318. #define TPG_HTOTAL_IN
  12319. #define TPG_HTOTAL_IN_MASK 0x0FFFC000U
  12320. #define TPG_HTOTAL_IN_SHIFT 14U
  12321. /*! Slice: tpg_vtotal_in:*/
  12322. #define TPG_VTOTAL_IN
  12323. #define TPG_VTOTAL_IN_MASK 0x00003FFFU
  12324. #define TPG_VTOTAL_IN_SHIFT 0U
  12325. /*! Register: isp_tpg_act_in (0x00000708)*/
  12326. /*! Slice: tpg_hact_in:*/
  12327. #define TPG_HACT_IN
  12328. #define TPG_HACT_IN_MASK 0x0FFFC000U
  12329. #define TPG_HACT_IN_SHIFT 14U
  12330. /*! Slice: tpg_vact_in:*/
  12331. #define TPG_VACT_IN
  12332. #define TPG_VACT_IN_MASK 0x00003FFFU
  12333. #define TPG_VACT_IN_SHIFT 0U
  12334. /*! Register: isp_tpg_fp_in (0x0000070C)*/
  12335. /*! Slice: tpg_fp_h_in:*/
  12336. #define TPG_FP_H_IN
  12337. #define TPG_FP_H_IN_MASK 0x0FFFC000U
  12338. #define TPG_FP_H_IN_SHIFT 14U
  12339. /*! Slice: tpg_fp_v_in:*/
  12340. #define TPG_FP_V_IN
  12341. #define TPG_FP_V_IN_MASK 0x00003FFFU
  12342. #define TPG_FP_V_IN_SHIFT 0U
  12343. /*! Register: isp_tpg_bp_in (0x00000710)*/
  12344. /*! Slice: tpg_bp_h_in:*/
  12345. #define TPG_BP_H_IN
  12346. #define TPG_BP_H_IN_MASK 0x0FFFC000U
  12347. #define TPG_BP_H_IN_SHIFT 14U
  12348. /*! Slice: tpg_bp_v_in:*/
  12349. #define TPG_BP_V_IN
  12350. #define TPG_BP_V_IN_MASK 0x00003FFFU
  12351. #define TPG_BP_V_IN_SHIFT 0U
  12352. /*! Register: isp_tpg_w_in (0x00000714)*/
  12353. /*! Slice: tpg_hs_w_in:*/
  12354. #define TPG_HS_W_IN
  12355. #define TPG_HS_W_IN_MASK 0x0FFFC000U
  12356. #define TPG_HS_W_IN_SHIFT 14U
  12357. /*! Slice: tpg_vs_w_in:*/
  12358. #define TPG_VS_W_IN
  12359. #define TPG_VS_W_IN_MASK 0x00003FFFU
  12360. #define TPG_VS_W_IN_SHIFT 0U
  12361. /*! Register: isp_tpg_gap_in (0x00000718)*/
  12362. /*! Slice: tpg_pix_gap_in:*/
  12363. #define TPG_PIX_GAP_IN
  12364. #define TPG_PIX_GAP_IN_MASK 0x0FFFC000U
  12365. #define TPG_PIX_GAP_IN_SHIFT 14U
  12366. /*! Slice: tpg_line_gap_in:*/
  12367. #define TPG_LINE_GAP_IN
  12368. #define TPG_LINE_GAP_IN_MASK 0x00003FFFU
  12369. #define TPG_LINE_GAP_IN_SHIFT 0U
  12370. /*! Register: isp_tpg_gap_std_in (0x0000071C)*/
  12371. /*! Slice: tpg_pix_gap_std_in:*/
  12372. #define TPG_PIX_GAP_STD_IN
  12373. #define TPG_PIX_GAP_STD_IN_MASK 0x00003FFFU
  12374. #define TPG_PIX_GAP_STD_IN_SHIFT 0U
  12375. /*! Register: isp_tpg_random_seed (0x00000720)*/
  12376. /*! Slice: tpg_random_seed:*/
  12377. #define TPG_RANDOM_SEED
  12378. #define TPG_RANDOM_SEED_MASK 0xFFFFFFFFU
  12379. #define TPG_RANDOM_SEED_SHIFT 0U
  12380. /* MCM */
  12381. /*! Register: mcm_ctrl (0x00001200)*/
  12382. /*! Slice: MCM_SENSOR_MEM_BYPASS:*/
  12383. #define MCM_SENSOR_MEM_BYPASS
  12384. #define MCM_SENSOR_MEM_BYPASS_MASK 0x00020000U
  12385. #define MCM_SENSOR_MEM_BYPASS_SHIFT 17U
  12386. /*! Slice: MCM_G2_WR1_FMT:*/
  12387. #define MCM_G2_WR1_FMT
  12388. #define MCM_G2_WR1_FMT_MASK 0x0001C000U
  12389. #define MCM_G2_WR1_FMT_SHIFT 14U
  12390. /*! Slice: MCM_G2_WR0_FMT:*/
  12391. #define MCM_G2_WR0_FMT
  12392. #define MCM_G2_WR0_FMT_MASK 0x00003800U
  12393. #define MCM_G2_WR0_FMT_SHIFT 11U
  12394. /*! Slice: MCM_WR1_FMT:*/
  12395. #define MCM_WR1_FMT
  12396. #define MCM_WR1_FMT_MASK 0x00000700U
  12397. #define MCM_WR1_FMT_SHIFT 8U
  12398. /*! Slice: MCM_WR0_FMT:*/
  12399. #define MCM_WR0_FMT
  12400. #define MCM_WR0_FMT_MASK 0x000000E0U
  12401. #define MCM_WR0_FMT_SHIFT 5U
  12402. /*! Slice: MCM_BYPASS_SWITCH:*/
  12403. #define MCM_BYPASS_SWITCH
  12404. #define MCM_BYPASS_SWITCH_MASK 0x0000001EU
  12405. #define MCM_BYPASS_SWITCH_SHIFT 1U
  12406. /*! Slice: MCM_BYPASS_EN:*/
  12407. #define MCM_BYPASS_EN
  12408. #define MCM_BYPASS_EN_MASK 0x00000001U
  12409. #define MCM_BYPASS_EN_SHIFT 0U
  12410. /*! Register: mcm_size0 (0x00001204)*/
  12411. /*! Slice: MCM_HEIGHT0:*/
  12412. #define MCM_HEIGHT0
  12413. #define MCM_HEIGHT0_MASK 0x3FFF0000U
  12414. #define MCM_HEIGHT0_SHIFT 16U
  12415. /*! Slice: MCM_WIDTH0:*/
  12416. #define MCM_WIDTH0
  12417. #define MCM_WIDTH0_MASK 0x00003FFFU
  12418. #define MCM_WIDTH0_SHIFT 0U
  12419. /*! Register: mcm_size1 (0x00001208)*/
  12420. /*! Slice: MCM_HEIGHT1:*/
  12421. #define MCM_HEIGHT1
  12422. #define MCM_HEIGHT1_MASK 0x3FFF0000U
  12423. #define MCM_HEIGHT1_SHIFT 16U
  12424. /*! Slice: MCM_WIDTH1:*/
  12425. #define MCM_WIDTH1
  12426. #define MCM_WIDTH1_MASK 0x00003FFFU
  12427. #define MCM_WIDTH1_SHIFT 0U
  12428. /*! Register: mcm_rd_cfg (0x00001280)*/
  12429. /*! Slice: MCM_RD_FMT:*/
  12430. #define MCM_RD_FMT
  12431. #define MCM_RD_FMT_MASK 0x00000007U
  12432. #define MCM_RD_FMT_SHIFT 0U
  12433. /*! Register: mcm_retiming0 (0x00001284)*/
  12434. /*! Slice: MCM_VSYNC_BLANK:*/
  12435. #define MCM_VSYNC_BLANK
  12436. #define MCM_VSYNC_BLANK_MASK 0xFFFFFF00U
  12437. #define MCM_VSYNC_BLANK_SHIFT 8U
  12438. /*! Slice: MCM_VSYNC_DURATION:*/
  12439. #define MCM_VSYNC_DURATION
  12440. #define MCM_VSYNC_DURATION_MASK 0x000000FFU
  12441. #define MCM_VSYNC_DURATION_SHIFT 0U
  12442. /*! Register: mcm_retiming1 (0x00001288)*/
  12443. /*! Slice: MCM_HSYNC_BLANK:*/
  12444. #define MCM_HSYNC_BLANK
  12445. #define MCM_HSYNC_BLANK_MASK 0xFFFFFF00U
  12446. #define MCM_HSYNC_BLANK_SHIFT 8U
  12447. /*! Slice: MCM_HSYNC_PREAMPLE:*/
  12448. #define MCM_HSYNC_PREAMPLE
  12449. #define MCM_HSYNC_PREAMPLE_MASK 0x000000FFU
  12450. #define MCM_HSYNC_PREAMPLE_SHIFT 0U
  12451. /*! Register: mcm_hsync_preample_ext (0x0000128c)*/
  12452. /*! Slice: MCM_HSYNC_PREAMPLE_EXT:*/
  12453. #define MCM_HSYNC_PREAMPLE_EXT
  12454. #define MCM_HSYNC_PREAMPLE_EXT_MASK 0x000FFFFFU
  12455. #define MCM_HSYNC_PREAMPLE_EXT_SHIFT 0U
  12456. /*! Register: mcm_wr_retiming0 (0x00001290)*/
  12457. /*! Slice: MCM_WR_VSYNC_BLANK:*/
  12458. #define MCM_WR_VSYNC_BLANK
  12459. #define MCM_WR_VSYNC_BLANK_MASK 0xFFFFFF00U
  12460. #define MCM_WR_VSYNC_BLANK_SHIFT 8U
  12461. /*! Slice: MCM_WR_VSYNC_DURATION:*/
  12462. #define MCM_WR_VSYNC_DURATION
  12463. #define MCM_WR_VSYNC_DURATION_MASK 0x000000FFU
  12464. #define MCM_WR_VSYNC_DURATION_SHIFT 0U
  12465. /*! Register: mcm_wr_retiming1 (0x00001294)*/
  12466. /*! Slice: MCM_WR_HSYNC_BLANK:*/
  12467. #define MCM_WR_HSYNC_BLANK
  12468. #define MCM_WR_HSYNC_BLANK_MASK 0xFFFFFF00U
  12469. #define MCM_WR_HSYNC_BLANK_SHIFT 8U
  12470. /*! Slice: MCM_WR_HSYNC_PREAMPLE:*/
  12471. #define MCM_WR_HSYNC_PREAMPLE
  12472. #define MCM_WR_HSYNC_PREAMPLE_MASK 0x000000FFU
  12473. #define MCM_WR_HSYNC_PREAMPLE_SHIFT 0U
  12474. /*Stitching */
  12475. /*!Register: isp_stitching_ctrl (0x00003300) */
  12476. /*!Register: isp_stitching_ctrl (0x00003300) */
  12477. /*!Slice: regs_inform_en */
  12478. #define STITCHING_REGS_INFORM_EN
  12479. #define STITCHING_REGS_INFORM_EN_MASK 0x00400000U
  12480. #define STITCHING_REGS_INFORM_EN_SHIFT 22U
  12481. /*!Slice: vsync_pol */
  12482. #define STITCHING_VSYNC_POL
  12483. #define STITCHING_VSYNC_POL_MASK 0x00200000U
  12484. #define STITCHING_VSYNC_POL_SHIFT 21U
  12485. /*!Slice: hsync_pol */
  12486. #define STITCHING_HSYNC_POL
  12487. #define STITCHING_HSYNC_POL_MASK 0x00100000U
  12488. #define STITCHING_HSYNC_POL_SHIFT 20U
  12489. /*!Slice: awb_gain_enable */
  12490. #define STITCHING_AWB_GAIN_ENABLE
  12491. #define STITCHING_AWB_GAIN_ENABLE_MASK 0x00080000U
  12492. #define STITCHING_AWB_GAIN_ENABLE_SHIFT 19U
  12493. /*!Slice: cfg_upd */
  12494. #define STITCHING_CFG_UPD
  12495. #define STITCHING_CFG_UPD_MASK 0x00040000U
  12496. #define STITCHING_CFG_UPD_SHIFT 18U
  12497. /*!Slice: gen_cfg_upd */
  12498. #define STITCHING_GEN_CFG_UPD
  12499. #define STITCHING_GEN_CFG_UPD_MASK 0x00020000U
  12500. #define STITCHING_GEN_CFG_UPD_SHIFT 17U
  12501. /*!Slice: gen_cfg_upd_fix */
  12502. #define STITCHING_GEN_CFG_UPD_FIX
  12503. #define STITCHING_GEN_CFG_UPD_FIX_MASK 0x00010000U
  12504. #define STITCHING_GEN_CFG_UPD_FIX_SHIFT 16U
  12505. /*!Slice: bypass_select */
  12506. #define STITCHING_BYPASS_SELECT
  12507. #define STITCHING_BYPASS_SELECT_MASK 0x00006000U
  12508. #define STITCHING_BYPASS_SELECT_SHIFT 13U
  12509. /*!Slice: linear_combine_enable */
  12510. #define STITCHING_LINEAR_COMBINE_ENABLE
  12511. #define STITCHING_LINEAR_COMBINE_ENABLE_MASK 0x00001000U
  12512. #define STITCHING_LINEAR_COMBINE_ENABLE_SHIFT 12U
  12513. /*!Slice: base_frame_selection */
  12514. #define STITCHING_BASE_FRAME_SELECTION
  12515. #define STITCHING_BASE_FRAME_SELECTION_MASK 0x00000800U
  12516. #define STITCHING_BASE_FRAME_SELECTION_SHIFT 11U
  12517. /*!Slice: combination_mode */
  12518. #define STITCHING_COMBINATION_MODE
  12519. #define STITCHING_COMBINATION_MODE_MASK 0x00000600U
  12520. #define STITCHING_COMBINATION_MODE_SHIFT 9U
  12521. /*!Slice: channel_config_bit */
  12522. #define STITCHING_CHANNEL_CONFIG_BIT
  12523. #define STITCHING_CHANNEL_CONFIG_BIT_MASK 0x00000100U
  12524. #define STITCHING_CHANNEL_CONFIG_BIT_SHIFT 8U
  12525. /*!Slice: B10_enable_bit */
  12526. #define STITCHING_B10_ENABLE_BIT
  12527. #define STITCHING_B10_ENABLE_BIT_MASK 0x00000080U
  12528. #define STITCHING_B10_ENABLE_BIT_SHIFT 7U
  12529. /*!Slice: lin_enable_bit */
  12530. #define STITCHING_LIN_ENABLE_BIT
  12531. #define STITCHING_LIN_ENABLE_BIT_MASK 0x00000040U
  12532. #define STITCHING_LIN_ENABLE_BIT_SHIFT 6U
  12533. /*!Slice: VS_enable_bit */
  12534. #define STITCHING_VS_ENABLE_BIT
  12535. #define STITCHING_VS_ENABLE_BIT_MASK 0x00000020U
  12536. #define STITCHING_VS_ENABLE_BIT_SHIFT 5U
  12537. /*!Slice: bayer_pattern */
  12538. #define STITCHING_BAYER_PATTERN
  12539. #define STITCHING_BAYER_PATTERN_MASK 0x00000018U
  12540. #define STITCHING_BAYER_PATTERN_SHIFT 3U
  12541. /*!Slice: soft_reset_flag */
  12542. #define STITCHING_SOFT_RESET_FLAG
  12543. #define STITCHING_SOFT_RESET_FLAG_MASK 0x00000004U
  12544. #define STITCHING_SOFT_RESET_FLAG_SHIFT 2U
  12545. /*!Slice: mono_input_flag */
  12546. #define STITCHING_MONO_INPUT_FLAG
  12547. #define STITCHING_MONO_INPUT_FLAG_MASK 0x00000002U
  12548. #define STITCHING_MONO_INPUT_FLAG_SHIFT 1U
  12549. /*!Slice: combine_enable_bit */
  12550. #define STITCHING_COMBINE_ENABLE_BIT
  12551. #define STITCHING_COMBINE_ENABLE_BIT_MASK 0x00000001U
  12552. #define STITCHING_COMBINE_ENABLE_BIT_SHIFT 0U
  12553. /*!Slice: regs_inform_en */
  12554. #define STITCHING_REGS_INFORM_EN
  12555. #define STITCHING_REGS_INFORM_EN_MASK 0x00400000U
  12556. #define STITCHING_REGS_INFORM_EN_SHIFT 22U
  12557. /*!Slice: vsync_pol */
  12558. #define STITCHING_VSYNC_POL
  12559. #define STITCHING_VSYNC_POL_MASK 0x00200000U
  12560. #define STITCHING_VSYNC_POL_SHIFT 21U
  12561. /*!Slice: hsync_pol */
  12562. #define STITCHING_HSYNC_POL
  12563. #define STITCHING_HSYNC_POL_MASK 0x00100000U
  12564. #define STITCHING_HSYNC_POL_SHIFT 20U
  12565. /*!Slice: awb_gain_enable */
  12566. #define STITCHING_AWB_GAIN_ENABLE
  12567. #define STITCHING_AWB_GAIN_ENABLE_MASK 0x00080000U
  12568. #define STITCHING_AWB_GAIN_ENABLE_SHIFT 19U
  12569. /*!Slice: cfg_upd */
  12570. #define STITCHING_CFG_UPD
  12571. #define STITCHING_CFG_UPD_MASK 0x00040000U
  12572. #define STITCHING_CFG_UPD_SHIFT 18U
  12573. /*!Slice: gen_cfg_upd */
  12574. #define STITCHING_GEN_CFG_UPD
  12575. #define STITCHING_GEN_CFG_UPD_MASK 0x00020000U
  12576. #define STITCHING_GEN_CFG_UPD_SHIFT 17U
  12577. /*!Slice: gen_cfg_upd_fix */
  12578. #define STITCHING_GEN_CFG_UPD_FIX
  12579. #define STITCHING_GEN_CFG_UPD_FIX_MASK 0x00010000U
  12580. #define STITCHING_GEN_CFG_UPD_FIX_SHIFT 16U
  12581. /*!Slice: bypass_select */
  12582. #define STITCHING_BYPASS_SELECT
  12583. #define STITCHING_BYPASS_SELECT_MASK 0x00006000U
  12584. #define STITCHING_BYPASS_SELECT_SHIFT 13U
  12585. /*!Slice: linear_combine_enable */
  12586. #define STITCHING_LINEAR_COMBINE_ENABLE
  12587. #define STITCHING_LINEAR_COMBINE_ENABLE_MASK 0x00001000U
  12588. #define STITCHING_LINEAR_COMBINE_ENABLE_SHIFT 12U
  12589. /*!Slice: base_frame_selection */
  12590. #define STITCHING_BASE_FRAME_SELECTION
  12591. #define STITCHING_BASE_FRAME_SELECTION_MASK 0x00000800U
  12592. #define STITCHING_BASE_FRAME_SELECTION_SHIFT 11U
  12593. /*!Slice: combination_mode */
  12594. #define STITCHING_COMBINATION_MODE
  12595. #define STITCHING_COMBINATION_MODE_MASK 0x00000600U
  12596. #define STITCHING_COMBINATION_MODE_SHIFT 9U
  12597. /*!Slice: channel_config_bit */
  12598. #define STITCHING_CHANNEL_CONFIG_BIT
  12599. #define STITCHING_CHANNEL_CONFIG_BIT_MASK 0x00000100U
  12600. #define STITCHING_CHANNEL_CONFIG_BIT_SHIFT 8U
  12601. /*!Slice: B10_enable_bit */
  12602. #define STITCHING_B10_ENABLE_BIT
  12603. #define STITCHING_B10_ENABLE_BIT_MASK 0x00000080U
  12604. #define STITCHING_B10_ENABLE_BIT_SHIFT 7U
  12605. /*!Slice: lin_enable_bit */
  12606. #define STITCHING_LIN_ENABLE_BIT
  12607. #define STITCHING_LIN_ENABLE_BIT_MASK 0x00000040U
  12608. #define STITCHING_LIN_ENABLE_BIT_SHIFT 6U
  12609. /*!Slice: VS_enable_bit */
  12610. #define STITCHING_VS_ENABLE_BIT
  12611. #define STITCHING_VS_ENABLE_BIT_MASK 0x00000020U
  12612. #define STITCHING_VS_ENABLE_BIT_SHIFT 5U
  12613. /*!Slice: bayer_pattern */
  12614. #define STITCHING_BAYER_PATTERN
  12615. #define STITCHING_BAYER_PATTERN_MASK 0x00000018U
  12616. #define STITCHING_BAYER_PATTERN_SHIFT 3U
  12617. /*!Slice: soft_reset_flag */
  12618. #define STITCHING_SOFT_RESET_FLAG
  12619. #define STITCHING_SOFT_RESET_FLAG_MASK 0x00000004U
  12620. #define STITCHING_SOFT_RESET_FLAG_SHIFT 2U
  12621. /*!Slice: mono_input_flag */
  12622. #define STITCHING_MONO_INPUT_FLAG
  12623. #define STITCHING_MONO_INPUT_FLAG_MASK 0x00000002U
  12624. #define STITCHING_MONO_INPUT_FLAG_SHIFT 1U
  12625. /*!Slice: combine_enable_bit */
  12626. #define STITCHING_COMBINE_ENABLE_BIT
  12627. #define STITCHING_COMBINE_ENABLE_BIT_MASK 0x00000001U
  12628. #define STITCHING_COMBINE_ENABLE_BIT_SHIFT 0U
  12629. /*!Register: isp_stitching_frame_width (0x00003304) */
  12630. /*!Slice: stitching_frame_width */
  12631. #define STITCHING_FRAME_WIDTH
  12632. #define STITCHING_FRAME_WIDTH_MASK 0x00003FFFU
  12633. #define STITCHING_FRAME_WIDTH_SHIFT 0U
  12634. /*!Register: isp_stitching_ctrl (0x00003300)*/
  12635. /*!Slice: digital_gain_en_2 */
  12636. #define STITCHING_DIGITAL_GAIN_EN2
  12637. #define STITCHING_DIGITAL_GAIN_EN2_MASK 0x02000000U
  12638. #define STITCHING_DIGITAL_GAIN_EN2_SHIFT 25U
  12639. /*!Register: isp_stitching_ctrl (0x00003300)*/
  12640. /*!Slice: digital_gain_en_1 */
  12641. #define STITCHING_DIGITAL_GAIN_EN1
  12642. #define STITCHING_DIGITAL_GAIN_EN1_MASK 0x01000000U
  12643. #define STITCHING_DIGITAL_GAIN_EN1_SHIFT 24U
  12644. /*!Register: isp_stitching_ctrl (0x00003300)*/
  12645. /*!Slice: digital_gain_en_0 */
  12646. #define STITCHING_DIGITAL_GAIN_EN0
  12647. #define STITCHING_DIGITAL_GAIN_EN0_MASK 0x00800000U
  12648. #define STITCHING_DIGITAL_GAIN_EN0_SHIFT 23U
  12649. /*!Register: isp_stitching_ctrl (0x00003300)*/
  12650. /*!Slice: digital_gain_en */
  12651. #define STITCHING_DIGITAL_GAIN_EN
  12652. #define STITCHING_DIGITAL_GAIN_EN_MASK 0x00400000U
  12653. #define STITCHING_DIGITAL_GAIN_EN_SHIFT 22U
  12654. /*!Register: isp_stitching_frame_height (0x00003308) */
  12655. /*!Slice: stitching_frame_height */
  12656. #define STITCHING_FRAME_HEIGHT
  12657. #define STITCHING_FRAME_HEIGHT_MASK 0x00003FFFU
  12658. #define STITCHING_FRAME_HEIGHT_SHIFT 0U
  12659. /*Register: isp_stitching_exposure_bit (0x0000330C) */
  12660. /*!Slice: stitching_l_bit_depth */
  12661. #define STITCHING_L_BIT_DEPTH
  12662. #define STITCHING_L_BIT_DEPTH_MASK 0xFF000000U
  12663. #define STITCHING_L_BIT_DEPTH_SHIFT 24U
  12664. /*!Slice: stitching_s_bit_depth */
  12665. #define STITCHING_S_BIT_DEPTH
  12666. #define STITCHING_S_BIT_DEPTH_MASK 0x00FF0000U
  12667. #define STITCHING_S_BIT_DEPTH_SHIFT 16U
  12668. /*!Slice: stitching_vs_bit_depth */
  12669. #define STITCHING_VS_BIT_DEPTH
  12670. #define STITCHING_VS_BIT_DEPTH_MASK 0x0000FF00U
  12671. #define STITCHING_VS_BIT_DEPTH_SHIFT 8U
  12672. /*!Slice: stitching_ls_bit_depth */
  12673. #define STITCHING_LS_BIT_DEPTH
  12674. #define STITCHING_LS_BIT_DEPTH_MASK 0x000000FFU
  12675. #define STITCHING_LS_BIT_DEPTH_SHIFT 0U
  12676. /*!Register: isp_stitching_color_weight */
  12677. /*!Slice: stitching_color_weight_2 */
  12678. #define STITCHING_COLOR_WEIGHT_2
  12679. #define STITCHING_COLOR_WEIGHT_2_MASK 0x00FF0000U
  12680. #define STITCHING_COLOR_WEIGHT_2_SHIFT 16U
  12681. /*!Slice: stitching_color_weight_1 */
  12682. #define STITCHING_COLOR_WEIGHT_1
  12683. #define STITCHING_COLOR_WEIGHT_1_MASK 0x0000FF00U
  12684. #define STITCHING_COLOR_WEIGHT_1_SHIFT 8U
  12685. /*!Slice: stitching_color_weight_0 */
  12686. #define STITCHING_COLOR_WEIGHT_0
  12687. #define STITCHING_COLOR_WEIGHT_0_MASK 0x000000FFU
  12688. #define STITCHING_COLOR_WEIGHT_0_SHIFT 0U
  12689. /*!Register: isp_stitching_bls_exp_0_a (0x00003314)*/
  12690. /*!Slice: stitching_digital_gain_exp_0_r */
  12691. #define STITCHING_DIGITAL_GAIN_EXP_0_R
  12692. #define STITCHING_DIGITAL_GAIN_EXP_0_R_MASK 0XFFFFF0000U
  12693. #define STITCHING_DIGITAL_GAIN_EXP_0_R_SHIFT 16U
  12694. /*!Register: isp_stitching_bls_exp_0_a (0x00003314)*/
  12695. /*!Slice: stitching_bls_exp_0_a */
  12696. #define STITCHING_BLS_EXP_0_A
  12697. #define STITCHING_BLS_EXP_0_A_MASK 0x000000FFFU
  12698. #define STITCHING_BLS_EXP_0_A_SHIFT 0U
  12699. /*!Register: isp_stitching_bls_exp_0_b (0x00003318)*/
  12700. /*!Slice: stitching_digital_gain_exp_0_g */
  12701. #define STITCHING_DIGITAL_GAIN_EXP_0_G
  12702. #define STITCHING_DIGITAL_GAIN_EXP_0_G_MASK 0XFFFFF0000U
  12703. #define STITCHING_DIGITAL_GAIN_EXP_0_G_SHIFT 16U
  12704. /*!Register: isp_stitching_bls_exp_0_b (0x00003318)*/
  12705. /*!Slice: stitching_bls_exp_0_b */
  12706. #define STITCHING_BLS_EXP_0_B
  12707. #define STITCHING_BLS_EXP_0_B_MASK 0x000000FFFU
  12708. #define STITCHING_BLS_EXP_0_B_SHIFT 0U
  12709. /*!Register: isp_stitching_bls_exp_0_c (0x0000331c)*/
  12710. /*!Slice: stitching_digital_gain_exp_0_gr */
  12711. #define STITCHING_DIGITAL_GAIN_EXP_0_GR
  12712. #define STITCHING_DIGITAL_GAIN_EXP_0_GR_MASK 0XFFFFF0000U
  12713. #define STITCHING_DIGITAL_GAIN_EXP_0_GR_SHIFT 16U
  12714. /*!Register: isp_stitching_bls_exp_0_c (0x0000331C)*/
  12715. /*!Slice: stitching_bls_exp_0_c */
  12716. #define STITCHING_BLS_EXP_0_C
  12717. #define STITCHING_BLS_EXP_0_C_MASK 0x000000FFFU
  12718. #define STITCHING_BLS_EXP_0_C_SHIFT 0U
  12719. /*!Register: isp_stitching_bls_exp_0_d (0x00003320)*/
  12720. /*!Slice: stitching_digital_gain_exp_0_gb */
  12721. #define STITCHING_DIGITAL_GAIN_EXP_0_GB
  12722. #define STITCHING_DIGITAL_GAIN_EXP_0_GB_MASK 0XFFFFF0000U
  12723. #define STITCHING_DIGITAL_GAIN_EXP_0_GB_SHIFT 16U
  12724. /*!Register: isp_stitching_bls_exp_0_d (0x00003320)*/
  12725. /*!Slice: stitching_bls_exp_0_d */
  12726. #define STITCHING_BLS_EXP_0_D
  12727. #define STITCHING_BLS_EXP_0_D_MASK 0x0000FFFU
  12728. #define STITCHING_BLS_EXP_0_D_SHIFT 0U
  12729. /*!Register: isp_stitching_bls_exp_1_a (0x00003324)*/
  12730. /*!Slice: stitching_digital_gain_exp_1_r */
  12731. #define STITCHING_DIGITAL_GAIN_EXP_1_R
  12732. #define STITCHING_DIGITAL_GAIN_EXP_1_R_MASK 0XFFFFF0000U
  12733. #define STITCHING_DIGITAL_GAIN_EXP_1_R_SHIFT 16U
  12734. /*!Register: isp_stitching_bls_exp_1_a (0x00003324)*/
  12735. /*!Slice: stitching_bls_exp_1_a */
  12736. #define STITCHING_BLS_EXP_1_A
  12737. #define STITCHING_BLS_EXP_1_A_MASK 0x0000FFFU
  12738. #define STITCHING_BLS_EXP_1_A_SHIFT 0U
  12739. /*!Register: isp_stitching_bls_exp_1_b (0x00003328)*/
  12740. /*!Slice: stitching_digital_gain_exp_1_g */
  12741. #define STITCHING_DIGITAL_GAIN_EXP_1_G
  12742. #define STITCHING_DIGITAL_GAIN_EXP_1_G_MASK 0XFFFFF0000U
  12743. #define STITCHING_DIGITAL_GAIN_EXP_1_G_SHIFT 16U
  12744. /*!Register: isp_stitching_bls_exp_1_b (0x00003328)*/
  12745. /*!Slice: stitching_bls_exp_1_b */
  12746. #define STITCHING_BLS_EXP_1_B
  12747. #define STITCHING_BLS_EXP_1_B_MASK 0x0000FFFU
  12748. #define STITCHING_BLS_EXP_1_B_SHIFT 0U
  12749. /*!Register: isp_stitching_bls_exp_1_c (0x0000332c)*/
  12750. /*!Slice: stitching_digital_gain_exp_1_gr */
  12751. #define STITCHING_DIGITAL_GAIN_EXP_1_GR
  12752. #define STITCHING_DIGITAL_GAIN_EXP_1_GR_MASK 0XFFFFF0000U
  12753. #define STITCHING_DIGITAL_GAIN_EXP_1_GR_SHIFT 16U
  12754. /*!Register: isp_stitching_bls_exp_1_c (0x0000332C)*/
  12755. /*!Slice: stitching_bls_exp_1_c */
  12756. #define STITCHING_BLS_EXP_1_C
  12757. #define STITCHING_BLS_EXP_1_C_MASK 0x0000FFFU
  12758. #define STITCHING_BLS_EXP_1_C_SHIFT 0U
  12759. /*!Register: isp_stitching_bls_exp_1_d (0x00003330)*/
  12760. /*!Slice: stitching_digital_gain_exp_1_gb */
  12761. #define STITCHING_DIGITAL_GAIN_EXP_1_GB
  12762. #define STITCHING_DIGITAL_GAIN_EXP_1_GB_MASK 0XFFFFF0000U
  12763. #define STITCHING_DIGITAL_GAIN_EXP_1_GB_SHIFT 16U
  12764. /*!Register: isp_stitching_bls_exp_1_d (0x00003330)*/
  12765. /*!Slice: stitching_bls_exp_1_d */
  12766. #define STITCHING_BLS_EXP_1_D
  12767. #define STITCHING_BLS_EXP_1_D_MASK 0x0000FFFU
  12768. #define STITCHING_BLS_EXP_1_D_SHIFT 0U
  12769. /*!Register: isp_stitching_bls_exp_2_a (0x00003334)*/
  12770. /*!Slice: stitching_digital_gain_exp_2_r */
  12771. #define STITCHING_DIGITAL_GAIN_EXP_2_R
  12772. #define STITCHING_DIGITAL_GAIN_EXP_2_R_MASK 0XFFFFF0000U
  12773. #define STITCHING_DIGITAL_GAIN_EXP_2_R_SHIFT 16U
  12774. /*!Register: isp_stitching_bls_exp_2_a (0x00003334)*/
  12775. /*!Slice: stitching_bls_exp_2_a */
  12776. #define STITCHING_BLS_EXP_2_A
  12777. #define STITCHING_BLS_EXP_2_A_MASK 0x0000FFFU
  12778. #define STITCHING_BLS_EXP_2_A_SHIFT 0U
  12779. /*!Register: isp_stitching_bls_exp_2_b (0x00003338)*/
  12780. /*!Slice: stitching_digital_gain_exp_2_g */
  12781. #define STITCHING_DIGITAL_GAIN_EXP_2_G
  12782. #define STITCHING_DIGITAL_GAIN_EXP_2_G_MASK 0XFFFFF0000U
  12783. #define STITCHING_DIGITAL_GAIN_EXP_2_G_SHIFT 16U
  12784. /*!Register: isp_stitching_bls_exp_2_b (0x00003338)*/
  12785. /*!Slice: stitching_bls_exp_2_b */
  12786. #define STITCHING_BLS_EXP_2_B
  12787. #define STITCHING_BLS_EXP_2_B_MASK 0x0000FFFU
  12788. #define STITCHING_BLS_EXP_2_B_SHIFT 0U
  12789. /*!Register: isp_stitching_bls_exp_2_c (0x0000333c)*/
  12790. /*!Slice: stitching_digital_gain_exp_2_gr */
  12791. #define STITCHING_DIGITAL_GAIN_EXP_2_GR
  12792. #define STITCHING_DIGITAL_GAIN_EXP_2_GR_MASK 0XFFFFF0000U
  12793. #define STITCHING_DIGITAL_GAIN_EXP_2_GR_SHIFT 16U
  12794. /*!Register: isp_stitching_bls_exp_2_c (0x0000333C)*/
  12795. /*!Slice: stitching_bls_exp_2_c */
  12796. #define STITCHING_BLS_EXP_2_C
  12797. #define STITCHING_BLS_EXP_2_C_MASK 0x0000FFFU
  12798. #define STITCHING_BLS_EXP_2_C_SHIFT 0U
  12799. /*!Register: isp_stitching_bls_exp_2_d (0x00003340)*/
  12800. /*!Slice: stitching_digital_gain_exp_2_gb */
  12801. #define STITCHING_DIGITAL_GAIN_EXP_2_GB
  12802. #define STITCHING_DIGITAL_GAIN_EXP_2_GB_MASK 0XFFFFF0000U
  12803. #define STITCHING_DIGITAL_GAIN_EXP_2_GB_SHIFT 16U
  12804. /*!Register: isp_stitching_bls_exp_2_d (0x00003340)*/
  12805. /*!Slice: stitching_bls_exp_2_d */
  12806. #define STITCHING_BLS_EXP_2_D
  12807. #define STITCHING_BLS_EXP_2_D_MASK 0x000000FFFU
  12808. #define STITCHING_BLS_EXP_2_D_SHIFT 0U
  12809. /*!Reister: isp_stitching_ratio_ls (0x00003344)*/
  12810. /*!Slice: stitching_ratio_long_short_1 */
  12811. #define STITCHING_RATIO_LONG_SHORT_1
  12812. #define STITCHING_RATIO_LONG_SHORT_1_MASK 0x00FFF000U
  12813. #define STITCHING_RATIO_LONG_SHORT_1_SHIFT 12U
  12814. /*!Slice: stitching_ratio_long_short_0 */
  12815. #define STITCHING_RATIO_LONG_SHORT_0
  12816. #define STITCHING_RATIO_LONG_SHORT_0_MASK 0x00000FFFU
  12817. #define STITCHING_RATIO_LONG_SHORT_0_SHIFT 0U
  12818. /*!Reister: isp_stitching_ratio_vs (0x00003348) */
  12819. /*!Slice: stitching_ratio_veryshort_short_1 */
  12820. #define STITCHING_RATIO_VERYSHORT_SHORT_1
  12821. #define STITCHING_RATIO_VERYSHORT_SHORT_1_MASK 0x00FFF000U
  12822. #define STITCHING_RATIO_VERYSHORT_SHORT_1_SHIFT 12U
  12823. /*!Slice: stitching_ratio_veryshort_short_0 */
  12824. #define STITCHING_RATIO_VERYSHORT_SHORT_0
  12825. #define STITCHING_RATIO_VERYSHORT_SHORT_0_MASK 0x00000FFFU
  12826. #define STITCHING_RATIO_VERYSHORT_SHORT_0_SHIFT 0U
  12827. /*!Reister: isp_stitching_ratio_ls_shd (0x0000334C) */
  12828. /*!Slice: stitching_ratio_long_short_shd_1 */
  12829. #define STITCHING_RATIO_LONG_SHORT_SHD_1
  12830. #define STITCHING_RATIO_LONG_SHORT_SHD_1_MASK 0x00FFF000U
  12831. #define STITCHING_RATIO_LONG_SHORT_SHD_1_SHIFT 12U
  12832. /*!Slice: stitching_ratio_long_short_shd_0 */
  12833. #define STITCHING_RATIO_LONG_SHORT_SHD_0
  12834. #define STITCHING_RATIO_LONG_SHORT_SHD_0_MASK 0x00000FFFU
  12835. #define STITCHING_RATIO_LONG_SHORT_SHD_0_SHIFT 0U
  12836. /*!Reister: isp_stitching_ratio_vs_shd (0x00003350) */
  12837. /*!Slice: stitching_ratio_veryshort_short_shd_1 */
  12838. #define STITCHING_RATIO_VERYSHORT_SHORT_SHD_1
  12839. #define STITCHING_RATIO_VERYSHORT_SHORT_SHD_1_MASK 0x00FFF000U
  12840. #define STITCHING_RATIO_VERYSHORT_SHORT_SHD_1_SHIFT 12U
  12841. /*!Slice: stitching_ratio_veryshort_short_shd_0 */
  12842. #define STITCHING_RATIO_VERYSHORT_SHORT_SHD_0
  12843. #define STITCHING_RATIO_VERYSHORT_SHORT_SHD_0_MASK 0x00000FFFU
  12844. #define STITCHING_RATIO_VERYSHORT_SHORT_SHD_0_SHIFT 0U
  12845. /*!Register: isp_sitching_trans_range_linear (0x00003354) */
  12846. /*!Slice: stitching_trans_range_start_linear */
  12847. #define STITCHING_TRANS_RANGE_START_LINEAR
  12848. #define STITCHING_TRANS_RANGE_START_LINEAR_MASK 0xFFFF0000U
  12849. #define STITCHING_TRANS_RANGE_START_LINEAR_SHIFT 16U
  12850. /*!Slice:stitching_trans_range_norm_factor_mul_linear */
  12851. #define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_LINEAR
  12852. #define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_LINEAR_MASK 0x0000FFFFU
  12853. #define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_LINEAR_SHIFT 0U
  12854. /*!Register: isp_sitching_trans_range_nonlinear (0x00003358) */
  12855. /*!Slice: stitching_trans_range_start_nonlinear */
  12856. #define STITCHING_TRANS_RANGE_START_NONLINEAR
  12857. #define STITCHING_TRANS_RANGE_START_NONLINEAR_MASK 0xFFFF0000U
  12858. #define STITCHING_TRANS_RANGE_START_NONLINEAR_SHIFT 16U
  12859. /*!Slice:stitching_trans_range_norm_factor_mul_nonlinear */
  12860. #define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_NONLINEAR
  12861. #define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_NONLINEAR_MASK 0x0000FFFFU
  12862. #define STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_NONLINEAR_SHIFT 0U
  12863. /*!Register: isp_stitching_sat_level (0x0000335C) */
  12864. //Version-11 Stitching only support one type extend bit
  12865. //!Slice: stitching_short_vs_extend_bit
  12866. #define STITCHING_SHORT_EXTEND_BIT
  12867. #define STITCHING_SHORT_EXTEND_BIT_MASK 0xFF000000U
  12868. #define STITCHING_SHORT_EXTEND_BIT_SHIFT 24U
  12869. //Version-12 Stitching support two type extend bit
  12870. //!Slice: stitching_short_ls_extend_bit
  12871. #define STITCHING_SHORT_LS_EXTEND_BIT
  12872. #define STITCHING_SHORT_LS_EXTEND_BIT_MASK 0xF0000000U
  12873. #define STITCHING_SHORT_LS_EXTEND_BIT_SHIFT 28U
  12874. //!Slice: stitching_short_vs_extend_bit
  12875. #define STITCHING_SHORT_VS_EXTEND_BIT
  12876. #define STITCHING_SHORT_VS_EXTEND_BIT_MASK 0x0F000000U
  12877. #define STITCHING_SHORT_VS_EXTEND_BIT_SHIFT 24U
  12878. /*!Slice: stitching_veryshort_valid_thresh */
  12879. #define STITCHING_VERYSHORT_VALID_THRESH
  12880. #define STITCHING_VERYSHORT_VALID_THRESH_MASK 0x00FFF000U
  12881. #define STITCHING_VERYSHORT_VALID_THRESH_SHIFT 12U
  12882. /*!Slice: stitching_veryshort_offset_val */
  12883. #define STITCHING_VERYSHORT_OFFSET_VAL
  12884. #define STITCHING_VERYSHORT_OFFSET_VAL_MASK 0x00000FFFU
  12885. #define STITCHING_VERYSHORT_OFFSET_VAL_SHIFT 0U
  12886. /*!Register: isp_stitching_long_exposure (0x00003360) */
  12887. /*!Slice: stitching_long_exposure_time */
  12888. #define STITCHING_LONG_EXPOSURE_TIME
  12889. #define STITCHING_LONG_EXPOSURE_TIME_MASK 0x00000FFFU
  12890. #define STITCHING_LONG_EXPOSURE_TIME_SHIFT 0U
  12891. /*!Register: isp_stitching_short_exposure (0x00003364) */
  12892. /*!Slice: stitching_short_exposure_time */
  12893. #define STITCHING_SHORT_EXPOSURE_TIME
  12894. #define STITCHING_SHORT_EXPOSURE_TIME_MASK 0x00000FFFU
  12895. #define STITCHING_SHORT_EXPOSURE_TIME_SHIFT 0U
  12896. /*!Register: isp_stitching_very_short_exposure (0x00003368) */
  12897. /*!Slice: stitching_very_short_exposure_time */
  12898. #define STITCHING_VERY_SHORT_EXPOSURE_TIME
  12899. #define STITCHING_VERY_SHORT_EXPOSURE_TIME_MASK 0x00000FFFU
  12900. #define STITCHING_VERY_SHORT_EXPOSURE_TIME_SHIFT 0U
  12901. /*!Register: isp_stitching_hdr_mode (0x0000336C) */
  12902. /*!Slice: stitching_hdr_mode */
  12903. #define STITCHING_HDR_MODE_BIT
  12904. #define STITCHING_HDR_MODE_BIT_MASK 0x0000000FU
  12905. #define STITCHING_HDR_MODE_BIT_SHIFT 0U
  12906. /*!Register: isp_stitching_out_hblank (0x00003370) */
  12907. /*!Slice: stitching_dummy_s_hblank */
  12908. #define STITCHING_DUMMY_S_HBLANK
  12909. #define STITCHING_DUMMY_S_HBLANK_MASK 0xFFFF0000U
  12910. #define STITCHING_DUMMY_S_HBLANK_SHIFT 16U
  12911. /*!Slice: stitching_out_hblank */
  12912. #define STITCHING_OUT_HBLANK
  12913. #define STITCHING_OUT_HBLANK_MASK 0x00003FFFU
  12914. #define STITCHING_OUT_HBLANK_SHIFT 0U
  12915. /*!Register: isp_stitching_out_vblank (0x00003374) */
  12916. /*!Slice: stitching_dummy_vs_hblank */
  12917. #define STITCHING_DUMMY_VS_HBLANK
  12918. #define STITCHING_DUMMY_VS_HBLANK_MASK 0xFFFF0000U
  12919. #define STITCHING_DUMMY_VS_HBLANK_SHIFT 16U
  12920. /*!Slice: stitching_out_vblank */
  12921. #define STITCHING_OUT_VBLANK
  12922. #define STITCHING_OUT_VBLANK_MASK 0x00000FFFU
  12923. #define STITCHING_OUT_VBLANK_SHIFT 0U
  12924. /*!Register:ISP_STITCHING_OUT_HBLANK (0x00003370)*/
  12925. /* Slice:stiching_dummy_hblank */
  12926. #define STITCHING_DUMMY_HBLANK
  12927. #define STITCHING_DUMMY_HBLANK_MASK 0xFFFF0000U
  12928. #define STITCHING_DUMMY_HBLANK_SHIFT 16U
  12929. /*!Register: isp_stitching_interrupt_status (0x00003378) */
  12930. /*!Slice: stitching_interrupt_status */
  12931. #define STITCHING_INTERRUPT_STATUS
  12932. #define STITCHING_INTERRUPT_STATUS_MASK 0x00000007U
  12933. #define STITCHING_INTERRUPT_STATUS_SHIFT 0U
  12934. /*!Register: isp_stitching_compress_x0 (0x0000337C) */
  12935. /*!Slice: stitching_compress_x0 */
  12936. #define STITCHING_COMPRESS_X0
  12937. #define STITCHING_COMPRESS_X0_MASK 0x000003FFU
  12938. #define STITCHING_COMPRESS_X0_SHIFT 0U
  12939. /*!Register: isp_stitching_compress_lut_0 (0x000033A0) */
  12940. /*!Slice: stitching_compress_lut_2 */
  12941. #define STITCHING_COMPRESS_LUT_2
  12942. #define STITCHING_COMPRESS_LUT_2_MASK 0x3FF00000U
  12943. #define STITCHING_COMPRESS_LUT_2_SHIFT 20U
  12944. /*!Slice: stitching_compress_lut_1 */
  12945. #define STITCHING_COMPRESS_LUT_1
  12946. #define STITCHING_COMPRESS_LUT_1_MASK 0x000FFC00U
  12947. #define STITCHING_COMPRESS_LUT_1_SHIFT 10U
  12948. /*!Slice: stitching_compress_lut_0 */
  12949. #define STITCHING_COMPRESS_LUT_0
  12950. #define STITCHING_COMPRESS_LUT_0_MASK 0x000003FFU
  12951. #define STITCHING_COMPRESS_LUT_0_SHIFT 0U
  12952. /*!Register: isp_stitching_compress_lut_1 (0x000033A4) */
  12953. /*!Slice: stitching_compress_lut_5 */
  12954. #define STITCHING_COMPRESS_LUT_5
  12955. #define STITCHING_COMPRESS_LUT_5_MASK 0x3FF00000U
  12956. #define STITCHING_COMPRESS_LUT_5_SHIFT 20U
  12957. /*!Slice: stitching_compress_lut_4 */
  12958. #define STITCHING_COMPRESS_LUT_4
  12959. #define STITCHING_COMPRESS_LUT_4_MASK 0x000FFC00U
  12960. #define STITCHING_COMPRESS_LUT_4_SHIFT 10U
  12961. /*!Slice: stitching_compress_lut_3 */
  12962. #define STITCHING_COMPRESS_LUT_3
  12963. #define STITCHING_COMPRESS_LUT_3_MASK 0x000003FFU
  12964. #define STITCHING_COMPRESS_LUT_3_SHIFT 0U
  12965. /*!Register: isp_stitching_compress_lut_2 (0x000033A8) */
  12966. /*!Slice: stitching_compress_lut_8 */
  12967. #define STITCHING_COMPRESS_LUT_8
  12968. #define STITCHING_COMPRESS_LUT_8_MASK 0x3FF00000U
  12969. #define STITCHING_COMPRESS_LUT_8_SHIFT 20U
  12970. /*!Slice: stitching_compress_lut_7 */
  12971. #define STITCHING_COMPRESS_LUT_7
  12972. #define STITCHING_COMPRESS_LUT_7_MASK 0x000FFC00U
  12973. #define STITCHING_COMPRESS_LUT_7_SHIFT 10U
  12974. /*!Slice: stitching_compress_lut_6 */
  12975. #define STITCHING_COMPRESS_LUT_6
  12976. #define STITCHING_COMPRESS_LUT_6_MASK 0x000003FFU
  12977. #define STITCHING_COMPRESS_LUT_6_SHIFT 0U
  12978. /*!Register: isp_stitching_compress_lut_3 (0x000033AC) */
  12979. /*!Slice: stitching_compress_lut_11 */
  12980. #define STITCHING_COMPRESS_LUT_11
  12981. #define STITCHING_COMPRESS_LUT_11_MASK 0x3FF00000U
  12982. #define STITCHING_COMPRESS_LUT_11_SHIFT 20U
  12983. /*!Slice: stitching_compress_lut_10 */
  12984. #define STITCHING_COMPRESS_LUT_10
  12985. #define STITCHING_COMPRESS_LUT_10_MASK 0x000FFC00U
  12986. #define STITCHING_COMPRESS_LUT_10_SHIFT 10U
  12987. /*!Slice: stitching_compress_lut_9 */
  12988. #define STITCHING_COMPRESS_LUT_9
  12989. #define STITCHING_COMPRESS_LUT_9_MASK 0x000003FFU
  12990. #define STITCHING_COMPRESS_LUT_9_SHIFT 0U
  12991. /*!Register: isp_stitching_compress_lut_4 (0x000033B0) */
  12992. /*!Slice: stitching_compress_lut_14 */
  12993. #define STITCHING_COMPRESS_LUT_14
  12994. #define STITCHING_COMPRESS_LUT_14_MASK 0x3FF00000U
  12995. #define STITCHING_COMPRESS_LUT_14_SHIFT 20U
  12996. /*!Slice: stitching_compress_lut_13 */
  12997. #define STITCHING_COMPRESS_LUT_13
  12998. #define STITCHING_COMPRESS_LUT_13_MASK 0x000FFC00U
  12999. #define STITCHING_COMPRESS_LUT_13_SHIFT 10U
  13000. /*!Slice: stitching_compress_lut_12 */
  13001. #define STITCHING_COMPRESS_LUT_12
  13002. #define STITCHING_COMPRESS_LUT_12_MASK 0x000003FFU
  13003. #define STITCHING_COMPRESS_LUT_12_SHIFT 0U
  13004. /*/*!Register: isp_stitching_compress_lut_shd_0 (0x000033B4) */
  13005. /*!Slice: stitching_compress_lut_shd_2 */
  13006. #define STITCHING_COMPRESS_LUT_SHD_2
  13007. #define STITCHING_COMPRESS_LUT_SHD_2_MASK 0x3FF00000U
  13008. #define STITCHING_COMPRESS_LUT_SHD_2_SHIFT 20U
  13009. /*!Slice: stitching_compress_lut_shd_1 */
  13010. #define STITCHING_COMPRESS_LUT_SHD_1
  13011. #define STITCHING_COMPRESS_LUT_SHD_1_MASK 0x000FFC00U
  13012. #define STITCHING_COMPRESS_LUT_SHD_1_SHIFT 10U
  13013. /*!Slice: stitching_compress_lut_shd_0 */
  13014. #define STITCHING_COMPRESS_LUT_SHD_0
  13015. #define STITCHING_COMPRESS_LUT_SHD_0_MASK 0x000003FFU
  13016. #define STITCHING_COMPRESS_LUT_SHD_0_SHIFT 0U
  13017. /*!Register: isp_stitching_compress_lut_shd_1 (0x000033B8) */
  13018. /*!Slice: stitching_compress_lut_shd_5 */
  13019. #define STITCHING_COMPRESS_LUT_SHD_5
  13020. #define STITCHING_COMPRESS_LUT_SHD_5_MASK 0x3FF00000U
  13021. #define STITCHING_COMPRESS_LUT_SHD_5_SHIFT 20U
  13022. /*!Slice: stitching_compress_lut_shd_4 */
  13023. #define STITCHING_COMPRESS_LUT_SHD_4
  13024. #define STITCHING_COMPRESS_LUT_SHD_4_MASK 0x000FFC00U
  13025. #define STITCHING_COMPRESS_LUT_SHD_4_SHIFT 10U
  13026. /*!Slice: stitching_compress_lut_shd_3 */
  13027. #define STITCHING_COMPRESS_LUT_SHD_3
  13028. #define STITCHING_COMPRESS_LUT_SHD_3_MASK 0x000003FFU
  13029. #define STITCHING_COMPRESS_LUT_SHD_3_SHIFT 0U
  13030. /*!Register: isp_stitching_compress_lut_shd_2 (0x000033BC) */
  13031. /*!Slice: stitching_compress_lut_shd_8 */
  13032. #define STITCHING_COMPRESS_LUT_SHD_8
  13033. #define STITCHING_COMPRESS_LUT_SHD_8_MASK 0x3FF00000U
  13034. #define STITCHING_COMPRESS_LUT_SHD_8_SHIFT 20U
  13035. /*!Slice: stitching_compress_lut_shd_7 */
  13036. #define STITCHING_COMPRESS_LUT_SHD_7
  13037. #define STITCHING_COMPRESS_LUT_SHD_7_MASK 0x000FFC00U
  13038. #define STITCHING_COMPRESS_LUT_SHD_7_SHIFT 10U
  13039. /*!Slice: stitching_compress_lut_shd_6 */
  13040. #define STITCHING_COMPRESS_LUT_SHD_6
  13041. #define STITCHING_COMPRESS_LUT_SHD_6_MASK 0x000003FFU
  13042. #define STITCHING_COMPRESS_LUT_SHD_6_SHIFT 0U
  13043. /*!Register: isp_stitching_compress_lut_shd_3 (0x000033C0) */
  13044. /*!Slice: stitching_compress_lut_shd_11 */
  13045. #define STITCHING_COMPRESS_LUT_SHD_11
  13046. #define STITCHING_COMPRESS_LUT_SHD_11_MASK 0x3FF00000U
  13047. #define STITCHING_COMPRESS_LUT_SHD_11_SHIFT 20U
  13048. /*!Slice: stitching_compress_lut_shd_10 */
  13049. #define STITCHING_COMPRESS_LUT_SHD_10
  13050. #define STITCHING_COMPRESS_LUT_SHD_10_MASK 0x000FFC00U
  13051. #define STITCHING_COMPRESS_LUT_SHD_10_SHIFT 10U
  13052. /*!Slice: stitching_compress_lut_shd_9 */
  13053. #define STITCHING_COMPRESS_LUT_SHD_9
  13054. #define STITCHING_COMPRESS_LUT_SHD_9_MASK 0x000003FFU
  13055. #define STITCHING_COMPRESS_LUT_SHD_9_SHIFT 0U
  13056. /*!Register: isp_stitching_compress_lut_shd_4 (0x000033C4) */
  13057. /*!Slice: stitching_compress_lut_shd_14 */
  13058. #define STITCHING_COMPRESS_LUT_SHD_14
  13059. #define STITCHING_COMPRESS_LUT_SHD_14_MASK 0x3FF00000U
  13060. #define STITCHING_COMPRESS_LUT_SHD_14_SHIFT 20U
  13061. /*!Slice: stitching_compress_lut_shd_13 */
  13062. #define STITCHING_COMPRESS_LUT_SHD_13
  13063. #define STITCHING_COMPRESS_LUT_SHD_13_MASK 0x000FFC00U
  13064. #define STITCHING_COMPRESS_LUT_SHD_13_SHIFT 10U
  13065. /*!Slice: stitching_compress_lut_shd_12 */
  13066. #define STITCHING_COMPRESS_LUT_SHD_12
  13067. #define STITCHING_COMPRESS_LUT_SHD_12_MASK 0x000003FFU
  13068. #define STITCHING_COMPRESS_LUT_SHD_12_SHIFT 0U
  13069. /*!Register:isp_stitching_exp0_awb_gain_g (0x000033C8) */
  13070. /*Slice:stiching_exp0_awb_gain_gr */
  13071. #define STITCHING_EXP0_AWB_GAIN_GR
  13072. #define STITCHING_EXP0_AWB_GAIN_GR_MASK 0x03FF0000U
  13073. #define STITCHING_EXP0_AWB_GAIN_GR_SHIFT 16U
  13074. /*Slice:stiching_exp0_awb_gain_gb */
  13075. #define STITCHING_EXP0_AWB_GAIN_GB
  13076. #define STITCHING_EXP0_AWB_GAIN_GB_MASK 0x000003FFU
  13077. #define STITCHING_EXP0_AWB_GAIN_GB_SHIFT 0U
  13078. /*Slice:stiching_exp0_awb_gain_r */
  13079. #define STITCHING_EXP0_AWB_GAIN_R
  13080. #define STITCHING_EXP0_AWB_GAIN_R_MASK 0x03FF0000U
  13081. #define STITCHING_EXP0_AWB_GAIN_R_SHIFT 16U
  13082. /*Slice:stiching_exp0_awb_gain_b */
  13083. #define STITCHING_EXP0_AWB_GAIN_B
  13084. #define STITCHING_EXP0_AWB_GAIN_B_MASK 0x000003FFU
  13085. #define STITCHING_EXP0_AWB_GAIN_B_SHIFT 0U
  13086. /*Slice:stiching_exp1_awb_gain_gr */
  13087. #define STITCHING_EXP1_AWB_GAIN_GR
  13088. #define STITCHING_EXP1_AWB_GAIN_GR_MASK 0x03FF0000U
  13089. #define STITCHING_EXP1_AWB_GAIN_GR_SHIFT 16U
  13090. /*Slice:stiching_exp1_awb_gain_gb */
  13091. #define STITCHING_EXP1_AWB_GAIN_GB
  13092. #define STITCHING_EXP1_AWB_GAIN_GB_MASK 0x000003FFU
  13093. #define STITCHING_EXP1_AWB_GAIN_GB_SHIFT 0U
  13094. /*Slice:stiching_exp1_awb_gain_r */
  13095. #define STITCHING_EXP1_AWB_GAIN_R
  13096. #define STITCHING_EXP1_AWB_GAIN_R_MASK 0x03FF0000U
  13097. #define STITCHING_EXP1_AWB_GAIN_R_SHIFT 16U
  13098. /*Slice:stiching_exp1_awb_gain_b */
  13099. #define STITCHING_EXP1_AWB_GAIN_B
  13100. #define STITCHING_EXP1_AWB_GAIN_B_MASK 0x000003FFU
  13101. #define STITCHING_EXP1_AWB_GAIN_B_SHIFT 0U
  13102. /*Slice:stiching_exp2_awb_gain_gr */
  13103. #define STITCHING_EXP2_AWB_GAIN_GR
  13104. #define STITCHING_EXP2_AWB_GAIN_GR_MASK 0x03FF0000U
  13105. #define STITCHING_EXP2_AWB_GAIN_GR_SHIFT 16U
  13106. /*Slice:stiching_exp2_awb_gain_gb */
  13107. #define STITCHING_EXP2_AWB_GAIN_GB
  13108. #define STITCHING_EXP2_AWB_GAIN_GB_MASK 0x000003FFU
  13109. #define STITCHING_EXP2_AWB_GAIN_GB_SHIFT 0U
  13110. /*Slice:stiching_exp0_awb_gain_r */
  13111. #define STITCHING_EXP2_AWB_GAIN_R
  13112. #define STITCHING_EXP2_AWB_GAIN_R_MASK 0x03FF0000U
  13113. #define STITCHING_EXP2_AWB_GAIN_R_SHIFT 16U
  13114. /*Slice:stiching_exp0_awb_gain_b */
  13115. #define STITCHING_EXP2_AWB_GAIN_B
  13116. #define STITCHING_EXP2_AWB_GAIN_B_MASK 0x000003FFU
  13117. #define STITCHING_EXP2_AWB_GAIN_B_SHIFT 0U
  13118. /*Register: isp_stitching_long_sat_params */
  13119. /*!Slice: stitching_long_sat_thresh */
  13120. #define STITCHING_LONG_SAT_THRESH
  13121. #define STITCHING_LONG_SAT_THRESH_MASK 0x00FFF000U
  13122. #define STITCHING_LONG_SAT_THRESH_SHIFT 12U
  13123. /*!Slice: stitching_long_sat_combine_weight */
  13124. #define STITCHING_LONG_SAT_COMBINE_WEIGHT
  13125. #define STITCHING_LONG_SAT_COMBINE_WEIGHT_MASK 0x000001FF
  13126. #define STITCHING_LONG_SAT_COMBINE_WEIGHT_SHIFT 0U
  13127. //!Register: isp_stitching_bls_exp_out_0 (0x000033F8)
  13128. //! Slice: stitching_bls_exp_out_a:
  13129. #define STITCHING_BLS_EXP_OUT_A
  13130. #define STITCHING_BLS_EXP_OUT_A_MASK 0x0FFF0000U
  13131. #define STITCHING_BLS_EXP_OUT_A_SHIFT 16U
  13132. //! Slice: stitching_bls_exp_out_b:
  13133. #define STITCHING_BLS_EXP_OUT_B
  13134. #define STITCHING_BLS_EXP_OUT_B_MASK 0x00000FFFU
  13135. #define STITCHING_BLS_EXP_OUT_B_SHIFT 0U
  13136. //!Register: isp_stitching_bls_exp_out_1 (0x000033FC)
  13137. //! Slice: stitching_bls_exp_out_c:
  13138. #define STITCHING_BLS_EXP_OUT_C
  13139. #define STITCHING_BLS_EXP_OUT_C_MASK 0x0FFF0000U
  13140. #define STITCHING_BLS_EXP_OUT_C_SHIFT 16U
  13141. //! Slice: stitching_bls_exp_out_d:
  13142. #define STITCHING_BLS_EXP_OUT_D
  13143. #define STITCHING_BLS_EXP_OUT_D_MASK 0x00000FFFU
  13144. #define STITCHING_BLS_EXP_OUT_D_SHIFT 0U
  13145. /*! Slice: ISP_STITCHING0_EXP_IMSC:*/
  13146. #define STITCHING_MIS_HDR_EXP_COMPLETE_L
  13147. #define STITCHING_MIS_HDR_EXP_COMPLETE_L_MASK 0x00000008U
  13148. #define STITCHING_MIS_HDR_EXP_COMPLETE_L_SHIFT 3U
  13149. #define STITCHING_MIS_HDR_EXP_COMPLETE_S
  13150. #define STITCHING_MIS_HDR_EXP_COMPLETE_S_MASK 0x00000010U
  13151. #define STITCHING_MIS_HDR_EXP_COMPLETE_S_SHIFT 4U
  13152. #define STITCHING_MIS_HDR_EXP_COMPLETE_VS
  13153. #define STITCHING_MIS_HDR_EXP_COMPLETE_VS_MASK 0x00000020U
  13154. #define STITCHING_MIS_HDR_EXP_COMPLETE_VS_SHIFT 5U
  13155. /*! Slice: ISP_STITCHING0_HIST_MIS:*/
  13156. #define STITCHING_MIS_HDR_HIST_COMPLETE_VS
  13157. #define STITCHING_MIS_HDR_HIST_COMPLETE_VS_MASK 0x00000100U
  13158. #define STITCHING_MIS_HDR_HIST_COMPLETE_VS_SHIFT 8U
  13159. #define STITCHING_MIS_HDR_HIST_COMPLETE_S
  13160. #define STITCHING_MIS_HDR_HIST_COMPLETE_S_MASK 0x00000080U
  13161. #define STITCHING_MIS_HDR_HIST_COMPLETE_S_SHIFT 7U
  13162. #define STITCHING_MIS_HDR_HIST_COMPLETE_L
  13163. #define STITCHING_MIS_HDR_HIST_COMPLETE_L_MASK 0x00000040U
  13164. #define STITCHING_MIS_HDR_HIST_COMPLETE_L_SHIFT 6U
  13165. /*!Slice: 2DNR ENABLE */
  13166. #define ISP_2DNR_ENABLE
  13167. #define ISP_2DNR_ENABLE_MASK 0x00000001
  13168. #define ISP_2DNR_ENABLE_SHIFT 0U
  13169. /*!Slice: 2DNR PRGAMMA STRENGTH */
  13170. #define ISP_2DNR_PRGAMMA_STRENGTH
  13171. #define ISP_2DNR_PRGAMMA_STRENGTH_MASK 0x00003F80
  13172. #define ISP_2DNR_PRGAMMA_STRENGTH_SHIFT 7U
  13173. /*!Slice: 2DNR STRENGTH */
  13174. #define ISP_2DNR_STRENGTH
  13175. #define ISP_2DNR_STRENGTH_MASK 0x0000007F
  13176. #define ISP_2DNR_STRENGTH_SHIFT 0U
  13177. /*!Slice: 2DNR SIGMAY0 */
  13178. #define ISP_2DNR_SIGMAY0
  13179. #define ISP_2DNR_SIGMAY0_MASK 0x00000FFF
  13180. #define ISP_2DNR_SIGMAY0_SHIFT 0U
  13181. /*!Slice: 2DNR SIGMAY1 */
  13182. #define ISP_2DNR_SIGMAY1
  13183. #define ISP_2DNR_SIGMAY1_MASK 0x00FFF000
  13184. #define ISP_2DNR_SIGMAY1_SHIFT 12U
  13185. /*!Slice: 2DNR SIGMAY2A */
  13186. #define ISP_2DNR_SIGMAY2A
  13187. #define ISP_2DNR_SIGMAY2A_MASK 0x3F000000
  13188. #define ISP_2DNR_SIGMAY2A_SHIFT 24U
  13189. /*!Slice: 2DNR SIGMAY2B */
  13190. #define ISP_2DNR_SIGMAY2B
  13191. #define ISP_2DNR_SIGMAY2B_MASK 0x3F000000
  13192. #define ISP_2DNR_SIGMAY2B_SHIFT 24U
  13193. /*!Slice: 2DNR SIGMAY3 */
  13194. #define ISP_2DNR_SIGMAY3
  13195. #define ISP_2DNR_SIGMAY3_MASK 0x00000FFF
  13196. #define ISP_2DNR_SIGMAY3_SHIFT 0U
  13197. /*!Slice: 2DNR SIGMAY4 */
  13198. #define ISP_2DNR_SIGMAY4
  13199. #define ISP_2DNR_SIGMAY4_MASK 0x00FFF000
  13200. #define ISP_2DNR_SIGMAY4_SHIFT 12U
  13201. /*!Slice: 2DNR denoise2d_dummy_hblank */
  13202. #define ISP_2DNR_DUMMY_HBLANK
  13203. #define ISP_2DNR_DUMMY_HBLANK_MASK 0x0000FFFF
  13204. #define ISP_2DNR_DUMMY_HBLANK_SHIFT 0U
  13205. /*!Slice: 2DNR ISP_DENOISE3D2_BLENDING */
  13206. #define DENOISE3D_V20_NLM_STRENGTH_OFFSET
  13207. #define DENOISE3D_V20_NLM_STRENGTH_OFFSET_MASK 0X3FF80000
  13208. #define DENOISE3D_V20_NLM_STRENGTH_OFFSET_SHIFT 19U
  13209. /*!Slice: 2DNR ISP_DENOISE3D2_BLENDING */
  13210. #define DENOISE3D_V20_NLM_STRENGTH_MAX
  13211. #define DENOISE3D_V20_NLM_STRENGTH_MAX_MASK 0X0007ff00
  13212. #define DENOISE3D_V20_NLM_STRENGTH_MAX_SHIFT 8U
  13213. /*!Slice: 2DNR ISP_DENOISE3D2_BLENDING */
  13214. #define DENOISE3D_V20_NLM_STRENGTH_SLOPE
  13215. #define DENOISE3D_V20_NLM_STRENGTH_SLOPE_MASK 0X000000ff
  13216. #define DENOISE3D_V20_NLM_STRENGTH_SLOPE_SHIFT 0U
  13217. /* Register: ISP_DENOISE3D_CTRL 0x00003700 */
  13218. /* Slice: 10:10 denoise3d_read_ref_en */
  13219. #define DENOISE3D_READ_REF_EN
  13220. #define DENOISE3D_READ_REF_EN_MASK 0x00000400U
  13221. #define DENOISE3D_READ_REF_EN_SHIFT 10U
  13222. /* Slice: 9:9 denoise3d_raw_decompress_en */
  13223. #define DENOISE3D_RAW_DECOMPRESS_EN
  13224. #define DENOISE3D_RAW_DECOMPRESS_EN_MASK 0x00000200U
  13225. #define DENOISE3D_RAW_DECOMPRESS_EN_SHIFT 9U
  13226. /* Slice: 8:8 denoise3d_rew_compress_en */
  13227. #define DENOISE3D_RAW_COMPRESS_EN
  13228. #define DENOISE3D_RAW_COMPRESS_EN_MASK 0x00000100U
  13229. #define DENOISE3D_RAW_COMPRESS_EN_SHIFT 8U
  13230. /* Slice: 7:7 denoise3d_write_ref_en */
  13231. #define DENOISE3D_WRITE_REF_EN
  13232. #define DENOISE3D_WRITE_REF_EN_MASK 0x00000080U
  13233. #define DENOISE3D_WRITE_REF_EN_SHIFT 7U
  13234. /* Register: ISP_DENOISE3D_CTRL 0x00003700 */
  13235. /* Slice: 5:5 denoise3d_soft_reset */
  13236. #define DENOISE3D_SOFT_RESET
  13237. #define DENOISE3D_SOFT_RESET_MASK 0x00000020U
  13238. #define DENOISE3D_SOFT_RESET_SHIFT 5U
  13239. /* Slice: 4:4 denoise3d_horizontal_en */
  13240. #define DENOISE3D_HORIZONTAL_EN
  13241. #define DENOISE3D_HORIZONTAL_EN_MASK 0x00000010U
  13242. #define DENOISE3D_HORIZONTAL_EN_SHIFT 4U
  13243. /* Slice: 3:3 denoise3d_vertical_en */
  13244. #define DENOISE3D_VERTICAL_EN
  13245. #define DENOISE3D_VERTICAL_EN_MASK 0x00000008U
  13246. #define DENOISE3D_VERTICAL_EN_SHIFT 3U
  13247. /* Slice: 2:2 denoise3d_temperal_en */
  13248. #define DENOISE3D_TEMPERAL_EN
  13249. #define DENOISE3D_TEMPERAL_EN_MASK 0x00000004U
  13250. #define DENOISE3D_TEMPERAL_EN_SHIFT 2U
  13251. /* Slice: 1:1 denoise3d_dilate_en */
  13252. #define DENOISE3D_DILATE_EN
  13253. #define DENOISE3D_DILATE_EN_MASK 0x00000002U
  13254. #define DENOISE3D_DILATE_EN_SHIFT 1U
  13255. /* Slice: 0:0 denoise3d_enable */
  13256. #define DENOISE3D_ENABLE
  13257. #define DENOISE3D_ENABLE_MASK 0x00000001U
  13258. #define DENOISE3D_ENABLE_SHIFT 0U
  13259. /* Register: ISP_DENOISE3D_STRENGTH 0x00003704 */
  13260. /* Slice: 29:19 denoise3d_update_temperal */
  13261. #define DENOISE3D_UPDATE_TEMPERAL
  13262. #define DENOISE3D_UPDATE_TEMPERAL_MASK 0x3FF80000U
  13263. #define DENOISE3D_UPDATE_TEMPERAL_SHIFT 19U
  13264. /* Slice: 18 : 8 denoise3d_update_spacial */
  13265. #define DENOISE3D_UPDATE_SPACIAL
  13266. #define DENOISE3D_UPDATE_SPACIAL_MASK 0x0007FF00U
  13267. #define DENOISE3D_UPDATE_SPACIAL_SHIFT 8U
  13268. /* Slice: 7 : 0 denoise3d_strength */
  13269. #define DENOISE3D_STRENGTH
  13270. #define DENOISE3D_STRENGTH_MASK 0x000000FFU
  13271. #define DENOISE3D_STRENGTH_SHIFT 0U
  13272. /* Register: ISP_DENOISE3D_EDGE_H 0x00003708 */
  13273. /* Slice: 27:20 denoise3d_strength_curve_spacial */
  13274. #define DENOISE3D_STRENGTH_CURVE_SPACIAL
  13275. #define DENOISE3D_STRENGTH_CURVE_SPACIAL_MASK 0x0FF00000U
  13276. #define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHIFT 20U
  13277. /* Slice: 19 : 0 denoise3d_thr_edge_h_inv */
  13278. #define DENOISE3D_THR_EDGE_H_INV
  13279. #define DENOISE3D_THR_EDGE_H_INV_MASK 0x000FFFFFU
  13280. #define DENOISE3D_THR_EDGE_H_INV_SHIFT 0U
  13281. /* Register: ISP_DENOISE3D_EDGE_V 0x0000370C */
  13282. /* Slice: 27:20 denoise3d_strength_curve_temperal */
  13283. #define DENOISE3D_STRENGTH_CURVE_TEMPERAL
  13284. #define DENOISE3D_STRENGTH_CURVE_TEMPERAL_MASK 0x0FF00000U
  13285. #define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHIFT 20U
  13286. /* Slice: 19 : 0 denoise3d_thr_edge_v_inv */
  13287. #define DENOISE3D_THR_EDGE_V_INV
  13288. #define DENOISE3D_THR_EDGE_V_INV_MASK 0x000FFFFFU
  13289. #define DENOISE3D_THR_EDGE_V_INV_SHIFT 0U
  13290. /* Register: ISP_DENOISE3D_RANGE_S 0x00003710 */
  13291. /* Slice: 19:0 denoise3d_range_s_inv */
  13292. #define DENOISE3D_RANGE_S_INV
  13293. #define DENOISE3D_RANGE_S_INV_MASK 0x000FFFFFU
  13294. #define DENOISE3D_RANGE_S_INV_SHIFT 0U
  13295. /* Register: ISP_DENOISE3D_RANGE_T 0x00003714 */
  13296. /* Slice: 29:25 denoise3d_range_t_h */
  13297. #define DENOISE3D_RANGE_T_H
  13298. #define DENOISE3D_RANGE_T_H_MASK 0x3E000000U
  13299. #define DENOISE3D_RANGE_T_H_SHIFT 25U
  13300. /* Slice: 24:20 denoise3d_range_t_v */
  13301. #define DENOISE3D_RANGE_T_V
  13302. #define DENOISE3D_RANGE_T_V_MASK 0x01F00000U
  13303. #define DENOISE3D_RANGE_T_V_SHIFT 20U
  13304. /* Slice: 19 : 0 denoise3d_range_t_inv */
  13305. #define DENOISE3D_RANGE_T_INV
  13306. #define DENOISE3D_RANGE_T_INV_MASK 0x000FFFFFU
  13307. #define DENOISE3D_RANGE_T_INV_SHIFT 0U
  13308. /* Register: ISP_DENOISE3D_MOTION 0x00003718 */
  13309. /* Slice: 24:20 denoise3d_range_d */
  13310. #define DENOISE3D_RANGE_D
  13311. #define DENOISE3D_RANGE_D_MASK 0x01F00000U
  13312. #define DENOISE3D_RANGE_D_SHIFT 20U
  13313. /* Slice: 19 : 0 denoise3d_motion_inv */
  13314. #define DENOISE3D_MOTION_INV
  13315. #define DENOISE3D_MOTION_INV_MASK 0x000FFFFFU
  13316. #define DENOISE3D_MOTION_INV_SHIFT 0U
  13317. /* Register: ISP_DENOISE3D_DELTA_INV 0x0000371C */
  13318. /* Slice: 29:20 denoise3d_delta_h_inv */
  13319. #define DENOISE3D_DELTA_H_INV
  13320. #define DENOISE3D_DELTA_H_INV_MASK 0x3FF00000U
  13321. #define DENOISE3D_DELTA_H_INV_SHIFT 20U
  13322. /* Slice: 19 : 10 denoise3d_delta_v_inv */
  13323. #define DENOISE3D_DELTA_V_INV
  13324. #define DENOISE3D_DELTA_V_INV_MASK 0x000FFC00U
  13325. #define DENOISE3D_DELTA_V_INV_SHIFT 10U
  13326. /* Slice: 9 : 0 denoise3d_delta_t_inv */
  13327. #define DENOISE3D_DELTA_T_INV
  13328. #define DENOISE3D_DELTA_T_INV_MASK 0x000003FFU
  13329. #define DENOISE3D_DELTA_T_INV_SHIFT 0U
  13330. /* Register: ISP_DENOISE3D_CURVE_S_0 0x00003720 */
  13331. /* Slice: 29:20 denoise3d_spacial_curve0 */
  13332. #define DENOISE3D_SPACIAL_CURVE0
  13333. #define DENOISE3D_SPACIAL_CURVE0_MASK 0x3FF00000U
  13334. #define DENOISE3D_SPACIAL_CURVE0_SHIFT 20U
  13335. /* Slice: 19 : 10 denoise3d_spacial_curve1 */
  13336. #define DENOISE3D_SPACIAL_CURVE1
  13337. #define DENOISE3D_SPACIAL_CURVE1_MASK 0x000FFC00U
  13338. #define DENOISE3D_SPACIAL_CURVE1_SHIFT 10U
  13339. /* Slice: 9 : 0 denoise3d_spacial_curve2 */
  13340. #define DENOISE3D_SPACIAL_CURVE2
  13341. #define DENOISE3D_SPACIAL_CURVE2_MASK 0x000003FFU
  13342. #define DENOISE3D_SPACIAL_CURVE2_SHIFT 0U
  13343. /* Register: ISP_DENOISE3D_CURVE_S_1 0x00003724 */
  13344. /* Slice: 29 : 20 denoise3d_spacial_curve3 */
  13345. #define DENOISE3D_SPACIAL_CURVE3
  13346. #define DENOISE3D_SPACIAL_CURVE3_MASK 0x3FF00000U
  13347. #define DENOISE3D_SPACIAL_CURVE3_SHIFT 20U
  13348. /* Slice: 19 : 10 denoise3d_spacial_curve4 */
  13349. #define DENOISE3D_SPACIAL_CURVE4
  13350. #define DENOISE3D_SPACIAL_CURVE4_MASK 0x000FFC00U
  13351. #define DENOISE3D_SPACIAL_CURVE4_SHIFT 10U
  13352. /* Slice: 9 : 0 denoise3d_spacial_curve5 */
  13353. #define DENOISE3D_SPACIAL_CURVE5
  13354. #define DENOISE3D_SPACIAL_CURVE5_MASK 0x000003FFU
  13355. #define DENOISE3D_SPACIAL_CURVE5_SHIFT 0U
  13356. /* Register: ISP_DENOISE3D_CURVE_S_2 0x00003728 */
  13357. /* Slice: 29 : 20 denoise3d_spacial_curve6 */
  13358. #define DENOISE3D_SPACIAL_CURVE6
  13359. #define DENOISE3D_SPACIAL_CURVE6_MASK 0x3FF00000U
  13360. #define DENOISE3D_SPACIAL_CURVE6_SHIFT 20U
  13361. /* Slice: 19 : 10 denoise3d_spacial_curve7 */
  13362. #define DENOISE3D_SPACIAL_CURVE7
  13363. #define DENOISE3D_SPACIAL_CURVE7_MASK 0x000FFC00U
  13364. #define DENOISE3D_SPACIAL_CURVE7_SHIFT 10U
  13365. /* Slice: 9 : 0 denoise3d_spacial_curve8 */
  13366. #define DENOISE3D_SPACIAL_CURVE8
  13367. #define DENOISE3D_SPACIAL_CURVE8_MASK 0x000003FFU
  13368. #define DENOISE3D_SPACIAL_CURVE8_SHIFT 0U
  13369. /* Register: ISP_DENOISE3D_CURVE_S_3 0x0000372C */
  13370. /* Slice: 29 : 20 denoise3d_spacial_curve9 */
  13371. #define DENOISE3D_SPACIAL_CURVE9
  13372. #define DENOISE3D_SPACIAL_CURVE9_MASK 0x3FF00000U
  13373. #define DENOISE3D_SPACIAL_CURVE9_SHIFT 20U
  13374. /* Slice: 19 : 10 denoise3d_spacial_curve10 */
  13375. #define DENOISE3D_SPACIAL_CURVE10
  13376. #define DENOISE3D_SPACIAL_CURVE10_MASK 0x000FFC00U
  13377. #define DENOISE3D_SPACIAL_CURVE10_SHIFT 10U
  13378. /* Slice: 9 : 0 denoise3d_spacial_curve11 */
  13379. #define DENOISE3D_SPACIAL_CURVE11
  13380. #define DENOISE3D_SPACIAL_CURVE11_MASK 0x000003FFU
  13381. #define DENOISE3D_SPACIAL_CURVE11_SHIFT 0U
  13382. /* Register: ISP_DENOISE3D_CURVE_S_4 0x00003730 */
  13383. /* Slice: 29 : 20 denoise3d_spacial_curve12 */
  13384. #define DENOISE3D_SPACIAL_CURVE12
  13385. #define DENOISE3D_SPACIAL_CURVE12_MASK 0x3FF00000U
  13386. #define DENOISE3D_SPACIAL_CURVE12_SHIFT 20U
  13387. /* Slice: 19 : 10 denoise3d_spacial_curve13 */
  13388. #define DENOISE3D_SPACIAL_CURVE13
  13389. #define DENOISE3D_SPACIAL_CURVE13_MASK 0x000FFC00U
  13390. #define DENOISE3D_SPACIAL_CURVE13_SHIFT 10U
  13391. /* Slice: 9 : 0 denoise3d_spacial_curve14 */
  13392. #define DENOISE3D_SPACIAL_CURVE14
  13393. #define DENOISE3D_SPACIAL_CURVE14_MASK 0x000003FFU
  13394. #define DENOISE3D_SPACIAL_CURVE14_SHIFT 0U
  13395. /* Register: ISP_DENOISE3D_CURVE_S_5 0x00003734 */
  13396. /* Slice: 19 : 10 denoise3d_spacial_curve15 */
  13397. #define DENOISE3D_SPACIAL_CURVE15
  13398. #define DENOISE3D_SPACIAL_CURVE15_MASK 0x000FFC00U
  13399. #define DENOISE3D_SPACIAL_CURVE15_SHIFT 10U
  13400. /* Slice: 9 : 0 denoise3d_spacial_curve16 */
  13401. #define DENOISE3D_SPACIAL_CURVE16
  13402. #define DENOISE3D_SPACIAL_CURVE16_MASK 0x000003FFU
  13403. #define DENOISE3D_SPACIAL_CURVE16_SHIFT 0U
  13404. /* Register: ISP_DENOISE3D_CURVE_T_0 0x00003738 */
  13405. /* Slice: 29 : 20 denoise3d_temperal_curve0 */
  13406. #define DENOISE3D_TEMPERAL_CURVE0
  13407. #define DENOISE3D_TEMPERAL_CURVE0_MASK 0x3FF00000U
  13408. #define DENOISE3D_TEMPERAL_CURVE0_SHIFT 20U
  13409. /* Slice: 19 : 10 denoise3d_temperal_curve1 */
  13410. #define DENOISE3D_TEMPERAL_CURVE1
  13411. #define DENOISE3D_TEMPERAL_CURVE1_MASK 0x000FFC00U
  13412. #define DENOISE3D_TEMPERAL_CURVE1_SHIFT 10U
  13413. /* Slice: 9 : 0 denoise3d_temperal_curve2 */
  13414. #define DENOISE3D_TEMPERAL_CURVE2
  13415. #define DENOISE3D_TEMPERAL_CURVE2_MASK 0x000003FFU
  13416. #define DENOISE3D_TEMPERAL_CURVE2_SHIFT 0U
  13417. /* Register: ISP_DENOISE3D_CURVE_T_1 0x0000373C */
  13418. /* Slice: 29 : 20 denoise3d_temperal_curve3 */
  13419. #define DENOISE3D_TEMPERAL_CURVE3
  13420. #define DENOISE3D_TEMPERAL_CURVE3_MASK 0x3FF00000U
  13421. #define DENOISE3D_TEMPERAL_CURVE3_SHIFT 20U
  13422. /* Slice: 19 : 10 denoise3d_temperal_curve4 */
  13423. #define DENOISE3D_TEMPERAL_CURVE4
  13424. #define DENOISE3D_TEMPERAL_CURVE4_MASK 0x000FFC00U
  13425. #define DENOISE3D_TEMPERAL_CURVE4_SHIFT 10U
  13426. /* Slice: 9 : 0 denoise3d_temperal_curve5 */
  13427. #define DENOISE3D_TEMPERAL_CURVE5
  13428. #define DENOISE3D_TEMPERAL_CURVE5_MASK 0x000003FFU
  13429. #define DENOISE3D_TEMPERAL_CURVE5_SHIFT 0U
  13430. /* Register: ISP_DENOISE3D_CURVE_T_2 0x00003740 */
  13431. /* Slice: 29 : 20 denoise3d_temperal_curve6 */
  13432. #define DENOISE3D_TEMPERAL_CURVE6
  13433. #define DENOISE3D_TEMPERAL_CURVE6_MASK 0x3FF00000U
  13434. #define DENOISE3D_TEMPERAL_CURVE6_SHIFT 20U
  13435. /* Slice: 19 : 10 denoise3d_temperal_curve7 */
  13436. #define DENOISE3D_TEMPERAL_CURVE7
  13437. #define DENOISE3D_TEMPERAL_CURVE7_MASK 0x000FFC00U
  13438. #define DENOISE3D_TEMPERAL_CURVE7_SHIFT 10U
  13439. /* Slice: 9 : 0 denoise3d_temperal_curve8 */
  13440. #define DENOISE3D_TEMPERAL_CURVE8
  13441. #define DENOISE3D_TEMPERAL_CURVE8_MASK 0x000003FFU
  13442. #define DENOISE3D_TEMPERAL_CURVE8_SHIFT 0U
  13443. /* Register: ISP_DENOISE3D_CURVE_T_3 0x00003744 */
  13444. /* Slice: 29 : 20 denoise3d_temperal_curve9 */
  13445. #define DENOISE3D_TEMPERAL_CURVE9
  13446. #define DENOISE3D_TEMPERAL_CURVE9_MASK 0x3FF00000U
  13447. #define DENOISE3D_TEMPERAL_CURVE9_SHIFT 20U
  13448. /* Slice: 19 : 10 denoise3d_temperal_curve10 */
  13449. #define DENOISE3D_TEMPERAL_CURVE10
  13450. #define DENOISE3D_TEMPERAL_CURVE10_MASK 0x000FFC00U
  13451. #define DENOISE3D_TEMPERAL_CURVE10_SHIFT 10U
  13452. /* Slice: 9 : 0 denoise3d_temperal_curve11 */
  13453. #define DENOISE3D_TEMPERAL_CURVE11
  13454. #define DENOISE3D_TEMPERAL_CURVE11_MASK 0x000003FFU
  13455. #define DENOISE3D_TEMPERAL_CURVE11_SHIFT 0U
  13456. /* Register: ISP_DENOISE3D_CURVE_T_4 0x00003748 */
  13457. /* Slice: 29 : 20 denoise3d_temperal_curve12 */
  13458. #define DENOISE3D_TEMPERAL_CURVE12
  13459. #define DENOISE3D_TEMPERAL_CURVE12_MASK 0x3FF00000U
  13460. #define DENOISE3D_TEMPERAL_CURVE12_SHIFT 20U
  13461. /* Slice: 19 : 10 denoise3d_temperal_curve13 */
  13462. #define DENOISE3D_TEMPERAL_CURVE13
  13463. #define DENOISE3D_TEMPERAL_CURVE13_MASK 0x000FFC00U
  13464. #define DENOISE3D_TEMPERAL_CURVE13_SHIFT 10U
  13465. /* Slice: 9 : 0 denoise3d_temperal_curve14 */
  13466. #define DENOISE3D_TEMPERAL_CURVE14
  13467. #define DENOISE3D_TEMPERAL_CURVE14_MASK 0x000003FFU
  13468. #define DENOISE3D_TEMPERAL_CURVE14_SHIFT 0U
  13469. /* Register: ISP_DENOISE3D_CURVE_T_5 0x0000374C */
  13470. /* Slice: 19 : 10 denoise3d_temperal_curve15 */
  13471. #define DENOISE3D_TEMPERAL_CURVE15
  13472. #define DENOISE3D_TEMPERAL_CURVE15_MASK 0x000FFC00U
  13473. #define DENOISE3D_TEMPERAL_CURVE15_SHIFT 10U
  13474. /* Slice: 9 : 0 denoise3d_temperal_curve16 */
  13475. #define DENOISE3D_TEMPERAL_CURVE16
  13476. #define DENOISE3D_TEMPERAL_CURVE16_MASK 0x000003FFU
  13477. #define DENOISE3D_TEMPERAL_CURVE16_SHIFT 0U
  13478. /* Register: ISP_DENOISE3D_AVERAGE 0x00003750 */
  13479. /* Slice: 31 : 0 denoise3d_frame_average */
  13480. #define DENOISE3D_FRAME_AVERAGE
  13481. #define DENOISE3D_FRAME_AVERAGE_MASK 0xFFFFFFFFU
  13482. #define DENOISE3D_FRAME_AVERAGE_SHIFT 0U
  13483. /* Register: ISP_DENOISE3D_STRENGTH_SHD 0x00003754 */
  13484. /* Slice: 29 : 19 denoise3d_update_temperal_shd */
  13485. #define DENOISE3D_UPDATE_TEMPERAL_SHD
  13486. #define DENOISE3D_UPDATE_TEMPERAL_SHD_MASK 0x3FF80000U
  13487. #define DENOISE3D_UPDATE_TEMPERAL_SHD_SHIFT 19U
  13488. /* Slice: 18 : 8 denoise3d_update_spacial_shd */
  13489. #define DENOISE3D_UPDATE_SPACIAL_SHD
  13490. #define DENOISE3D_UPDATE_SPACIAL_SHD_MASK 0x0007FF00U
  13491. #define DENOISE3D_UPDATE_SPACIAL_SHD_SHIFT 8U
  13492. /* Slice: 7 : 0 denoise3d_strength_shd */
  13493. #define DENOISE3D_STRENGTH_SHD
  13494. #define DENOISE3D_STRENGTH_SHD_MASK 0x0000000FU
  13495. #define DENOISE3D_STRENGTH_SHD_SHIFT 0U
  13496. /* Register: ISP_DENOISE3D_EDGE_H_SHD 0x00003758 */
  13497. /* Slice: 27 : 20 denoise3d_strength_curve_spacial_shd */
  13498. #define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD
  13499. #define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD_MASK 0x0FF00000U
  13500. #define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD_SHIFT 20U
  13501. /* Slice: 19 : 0 denoise3d_thr_edge_h_inv_shd */
  13502. #define DENOISE3D_THR_EDGE_H_INV_SHD
  13503. #define DENOISE3D_THR_EDGE_H_INV_SHD_MASK 0x000FFFFFU
  13504. #define DENOISE3D_THR_EDGE_H_INV_SHD_SHIFT 0U
  13505. /* Register: ISP_DENOISE3D_EDGE_V_SHD 0x0000375C */
  13506. /* Slice: 27 : 20 denoise3d_strength_curve_temperal_shd */
  13507. #define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD
  13508. #define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD_MASK 0x0FF00000U
  13509. #define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD_SHIFT 20U
  13510. /* Slice: 19 : 0 denoise3d_thr_edge_v_inv_shd */
  13511. #define DENOISE3D_THR_EDGE_V_INV_SHD
  13512. #define DENOISE3D_THR_EDGE_V_INV_SHD_MASK 0x000FFFFFU
  13513. #define DENOISE3D_THR_EDGE_V_INV_SHD_SHIFT 0U
  13514. /* Register: ISP_DENOISE3D_RANGE_S_SHD 0x00003760 */
  13515. /* Slice: 19 : 0 denoise3d_range_s_inv_shd */
  13516. #define DENOISE3D_RANGE_S_INV_SHD
  13517. #define DENOISE3D_RANGE_S_INV_SHD_MASK 0x000FFFFFU
  13518. #define DENOISE3D_RANGE_S_INV_SHD_SHIFT 0U
  13519. /* Register: ISP_DENOISE3D_RANGE_T_SHD 0x00003764 */
  13520. /* Slice: 29 : 25 denoise3d_range_t_h_shd */
  13521. #define DENOISE3D_RANGE_T_H_SHD
  13522. #define DENOISE3D_RANGE_T_H_SHD_MASK 0x3E000000U
  13523. #define DENOISE3D_RANGE_T_H_SHD_SHIFT 25U
  13524. /* Slice: 24 : 20 denoise3d_range_t_v_shd */
  13525. #define DENOISE3D_RANGE_T_V_SHD
  13526. #define DENOISE3D_RANGE_T_V_SHD_MASK 0x01F00000U
  13527. #define DENOISE3D_RANGE_T_V_SHD_SHIFT 20U
  13528. /* Slice: 19 : 0 denoise3d_range_t_inv_shd */
  13529. #define DENOISE3D_RANGE_T_INV_SHD
  13530. #define DENOISE3D_RANGE_T_INV_SHD_MASK 0x000FFFFFU
  13531. #define DENOISE3D_RANGE_T_INV_SHD_SHIFT 0U
  13532. /* Register: ISP_DENOISE3D_MOTION_SHD 0x00003768 */
  13533. /* Slice: 24 : 20 denoise3d_range_d_shd */
  13534. #define DENOISE3D_RANGE_D_SHD
  13535. #define DENOISE3D_RANGE_D_SHD_MASK 0x01F00000U
  13536. #define DENOISE3D_RANGE_D_SHD_SHIFT 20U
  13537. /* Slice: 19 : 0 denoise3d_motion_inv_shd */
  13538. #define DENOISE3D_MOTION_INV_SHD
  13539. #define DENOISE3D_MOTION_INV_SHD_MASK 0x000FFFFFU
  13540. #define DENOISE3D_MOTION_INV_SHD_SHIFT 0U
  13541. /* Register: ISP_DENOISE3D_DELTA_INV_SHD 0x0000376C */
  13542. /* Slice: 29 : 20 denoise3d_delta_h_inv_shd */
  13543. #define DENOISE3D_DELTA_H_INV_SHD
  13544. #define DENOISE3D_DELTA_H_INV_SHD_MASK 0x3FF00000U
  13545. #define DENOISE3D_DELTA_H_INV_SHD_SHIFT 20U
  13546. /* Slice: 19 : 10 denoise3d_delta_v_inv_shd */
  13547. #define DENOISE3D_DELTA_V_INV_SHD
  13548. #define DENOISE3D_DELTA_V_INV_SHD_MASK 0x000FFFFFU
  13549. #define DENOISE3D_DELTA_V_INV_SHD_SHIFT 10U
  13550. /* Slice: 9 : 0 denoise3d_delta_t_inv_shd */
  13551. #define DENOISE3D_DELTA_T_INV_SHD
  13552. #define DENOISE3D_DELTA_T_INV_SHD_MASK 0x000003FFU
  13553. #define DENOISE3D_DELTA_T_INV_SHD_SHIFT 0U
  13554. /* Register: ISP_DENOISE3D_DUMMY_HBLANK 0x00003770 */
  13555. /* Slice: 14 : 0 denoise3d_H_Blank */
  13556. #define DENOISE3D_H_BLANK
  13557. #define DENOISE3D_H_BLANK_MASK 0x0000FFFFU
  13558. #define DENOISE3D_H_BLANK_SHIFT 0U
  13559. /* Register: ISP_DENOISE3D_CTRL 0x00003700 */
  13560. /* Slice: 5:5 denoise3d_soft_reset */
  13561. #define DENOISE3D_SOFT_RESET
  13562. #define DENOISE3D_SOFT_RESET_MASK 0x00000020U
  13563. #define DENOISE3D_SOFT_RESET_SHIFT 5U
  13564. /* Slice: 4:4 denoise3d_horizontal_en */
  13565. #define DENOISE3D_HORIZONTAL_EN
  13566. #define DENOISE3D_HORIZONTAL_EN_MASK 0x00000010U
  13567. #define DENOISE3D_HORIZONTAL_EN_SHIFT 4U
  13568. /* Slice: 3:3 denoise3d_vertical_en */
  13569. #define DENOISE3D_VERTICAL_EN
  13570. #define DENOISE3D_VERTICAL_EN_MASK 0x00000008U
  13571. #define DENOISE3D_VERTICAL_EN_SHIFT 3U
  13572. /* Slice: 2:2 denoise3d_temperal_en */
  13573. #define DENOISE3D_TEMPERAL_EN
  13574. #define DENOISE3D_TEMPERAL_EN_MASK 0x00000004U
  13575. #define DENOISE3D_TEMPERAL_EN_SHIFT 2U
  13576. /* Slice: 1:1 denoise3d_dilate_en */
  13577. #define DENOISE3D_DILATE_EN
  13578. #define DENOISE3D_DILATE_EN_MASK 0x00000002U
  13579. #define DENOISE3D_DILATE_EN_SHIFT 1U
  13580. /* Slice: 0:0 denoise3d_enable */
  13581. #define DENOISE3D_ENABLE
  13582. #define DENOISE3D_ENABLE_MASK 0x00000001U
  13583. #define DENOISE3D_ENABLE_SHIFT 0U
  13584. /* Register: ISP_DENOISE3D_STRENGTH 0x00003704 */
  13585. /* Slice: 29:19 denoise3d_update_temperal */
  13586. #define DENOISE3D_UPDATE_TEMPERAL
  13587. #define DENOISE3D_UPDATE_TEMPERAL_MASK 0x3FF80000U
  13588. #define DENOISE3D_UPDATE_TEMPERAL_SHIFT 19U
  13589. /* Slice: 18 : 8 denoise3d_update_spacial */
  13590. #define DENOISE3D_UPDATE_SPACIAL
  13591. #define DENOISE3D_UPDATE_SPACIAL_MASK 0x0007FF00U
  13592. #define DENOISE3D_UPDATE_SPACIAL_SHIFT 8U
  13593. /* Slice: 7 : 0 denoise3d_strength */
  13594. #define DENOISE3D_STRENGTH
  13595. #define DENOISE3D_STRENGTH_MASK 0x000000FFU
  13596. #define DENOISE3D_STRENGTH_SHIFT 0U
  13597. /* Register: ISP_DENOISE3D_EDGE_H 0x00003708 */
  13598. /* Slice: 27:20 denoise3d_strength_curve_spacial */
  13599. #define DENOISE3D_STRENGTH_CURVE_SPACIAL
  13600. #define DENOISE3D_STRENGTH_CURVE_SPACIAL_MASK 0x0FF00000U
  13601. #define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHIFT 20U
  13602. /* Slice: 19 : 0 denoise3d_thr_edge_h_inv */
  13603. #define DENOISE3D_THR_EDGE_H_INV
  13604. #define DENOISE3D_THR_EDGE_H_INV_MASK 0x000FFFFFU
  13605. #define DENOISE3D_THR_EDGE_H_INV_SHIFT 0U
  13606. /* Register: ISP_DENOISE3D_EDGE_V 0x0000370C */
  13607. /* Slice: 27:20 denoise3d_strength_curve_temperal */
  13608. #define DENOISE3D_STRENGTH_CURVE_TEMPERAL
  13609. #define DENOISE3D_STRENGTH_CURVE_TEMPERAL_MASK 0x0FF00000U
  13610. #define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHIFT 20U
  13611. /* Slice: 19 : 0 denoise3d_thr_edge_v_inv */
  13612. #define DENOISE3D_THR_EDGE_V_INV
  13613. #define DENOISE3D_THR_EDGE_V_INV_MASK 0x000FFFFFU
  13614. #define DENOISE3D_THR_EDGE_V_INV_SHIFT 0U
  13615. /* Register: ISP_DENOISE3D_RANGE_S 0x00003710 */
  13616. /* Slice: 19:0 denoise3d_range_s_inv */
  13617. #define DENOISE3D_RANGE_S_INV
  13618. #define DENOISE3D_RANGE_S_INV_MASK 0x000FFFFFU
  13619. #define DENOISE3D_RANGE_S_INV_SHIFT 0U
  13620. /* Register: ISP_DENOISE3D_RANGE_T 0x00003714 */
  13621. /* Slice: 29:25 denoise3d_range_t_h */
  13622. #define DENOISE3D_RANGE_T_H
  13623. #define DENOISE3D_RANGE_T_H_MASK 0x3E000000U
  13624. #define DENOISE3D_RANGE_T_H_SHIFT 25U
  13625. /* Slice: 24:20 denoise3d_range_t_v */
  13626. #define DENOISE3D_RANGE_T_V
  13627. #define DENOISE3D_RANGE_T_V_MASK 0x01F00000U
  13628. #define DENOISE3D_RANGE_T_V_SHIFT 20U
  13629. /* Slice: 19 : 0 denoise3d_range_t_inv */
  13630. #define DENOISE3D_RANGE_T_INV
  13631. #define DENOISE3D_RANGE_T_INV_MASK 0x000FFFFFU
  13632. #define DENOISE3D_RANGE_T_INV_SHIFT 0U
  13633. /* Register: ISP_DENOISE3D_MOTION 0x00003718 */
  13634. /* Slice: 24:20 denoise3d_range_d */
  13635. #define DENOISE3D_RANGE_D
  13636. #define DENOISE3D_RANGE_D_MASK 0x01F00000U
  13637. #define DENOISE3D_RANGE_D_SHIFT 20U
  13638. /* Slice: 19 : 0 denoise3d_motion_inv */
  13639. #define DENOISE3D_MOTION_INV
  13640. #define DENOISE3D_MOTION_INV_MASK 0x000FFFFFU
  13641. #define DENOISE3D_MOTION_INV_SHIFT 0U
  13642. /* Register: ISP_DENOISE3D_DELTA_INV 0x0000371C */
  13643. /* Slice: 29:20 denoise3d_delta_h_inv */
  13644. #define DENOISE3D_DELTA_H_INV
  13645. #define DENOISE3D_DELTA_H_INV_MASK 0x3FF00000U
  13646. #define DENOISE3D_DELTA_H_INV_SHIFT 20U
  13647. /* Slice: 19 : 10 denoise3d_delta_v_inv */
  13648. #define DENOISE3D_DELTA_V_INV
  13649. #define DENOISE3D_DELTA_V_INV_MASK 0x000FFC00U
  13650. #define DENOISE3D_DELTA_V_INV_SHIFT 10U
  13651. /* Slice: 9 : 0 denoise3d_delta_t_inv */
  13652. #define DENOISE3D_DELTA_T_INV
  13653. #define DENOISE3D_DELTA_T_INV_MASK 0x000003FFU
  13654. #define DENOISE3D_DELTA_T_INV_SHIFT 0U
  13655. /* Register: ISP_DENOISE3D_CURVE_S_0 0x00003720 */
  13656. /* Slice: 29:20 denoise3d_spacial_curve0 */
  13657. #define DENOISE3D_SPACIAL_CURVE0
  13658. #define DENOISE3D_SPACIAL_CURVE0_MASK 0x3FF00000U
  13659. #define DENOISE3D_SPACIAL_CURVE0_SHIFT 20U
  13660. /* Slice: 19 : 10 denoise3d_spacial_curve1 */
  13661. #define DENOISE3D_SPACIAL_CURVE1
  13662. #define DENOISE3D_SPACIAL_CURVE1_MASK 0x000FFC00U
  13663. #define DENOISE3D_SPACIAL_CURVE1_SHIFT 10U
  13664. /* Slice: 9 : 0 denoise3d_spacial_curve2 */
  13665. #define DENOISE3D_SPACIAL_CURVE2
  13666. #define DENOISE3D_SPACIAL_CURVE2_MASK 0x000003FFU
  13667. #define DENOISE3D_SPACIAL_CURVE2_SHIFT 0U
  13668. /* Register: ISP_DENOISE3D_CURVE_T_0 0x00003738 */
  13669. /* Slice: 29 : 20 denoise3d_temperal_curve0 */
  13670. #define DENOISE3D_TEMPERAL_CURVE0
  13671. #define DENOISE3D_TEMPERAL_CURVE0_MASK 0x3FF00000U
  13672. #define DENOISE3D_TEMPERAL_CURVE0_SHIFT 20U
  13673. /* Slice: 19 : 10 denoise3d_temperal_curve1 */
  13674. #define DENOISE3D_TEMPERAL_CURVE1
  13675. #define DENOISE3D_TEMPERAL_CURVE1_MASK 0x000FFC00U
  13676. #define DENOISE3D_TEMPERAL_CURVE1_SHIFT 10U
  13677. /* Slice: 9 : 0 denoise3d_temperal_curve2 */
  13678. #define DENOISE3D_TEMPERAL_CURVE2
  13679. #define DENOISE3D_TEMPERAL_CURVE2_MASK 0x000003FFU
  13680. #define DENOISE3D_TEMPERAL_CURVE2_SHIFT 0U
  13681. /* Register: ISP_DENOISE3D_AVERAGE 0x00003750 */
  13682. /* Slice: 31 : 0 denoise3d_frame_average */
  13683. #define DENOISE3D_FRAME_AVERAGE
  13684. #define DENOISE3D_FRAME_AVERAGE_MASK 0xFFFFFFFFU
  13685. #define DENOISE3D_FRAME_AVERAGE_SHIFT 0U
  13686. /* Register: ISP_DENOISE3D_STRENGTH_SHD 0x00003754 */
  13687. /* Slice: 29 : 19 denoise3d_update_temperal_shd */
  13688. #define DENOISE3D_UPDATE_TEMPERAL_SHD
  13689. #define DENOISE3D_UPDATE_TEMPERAL_SHD_MASK 0x3FF80000U
  13690. #define DENOISE3D_UPDATE_TEMPERAL_SHD_SHIFT 19U
  13691. /* Slice: 18 : 8 denoise3d_update_spacial_shd */
  13692. #define DENOISE3D_UPDATE_SPACIAL_SHD
  13693. #define DENOISE3D_UPDATE_SPACIAL_SHD_MASK 0x0007FF00U
  13694. #define DENOISE3D_UPDATE_SPACIAL_SHD_SHIFT 8U
  13695. /* Slice: 7 : 0 denoise3d_strength_shd */
  13696. #define DENOISE3D_STRENGTH_SHD
  13697. #define DENOISE3D_STRENGTH_SHD_MASK 0x0000000FU
  13698. #define DENOISE3D_STRENGTH_SHD_SHIFT 0U
  13699. /* Register: ISP_DENOISE3D_EDGE_H_SHD 0x00003758 */
  13700. /* Slice: 27 : 20 denoise3d_strength_curve_spacial_shd */
  13701. #define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD
  13702. #define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD_MASK 0x0FF00000U
  13703. #define DENOISE3D_STRENGTH_CURVE_SPACIAL_SHD_SHIFT 20U
  13704. /* Slice: 19 : 0 denoise3d_thr_edge_h_inv_shd */
  13705. #define DENOISE3D_THR_EDGE_H_INV_SHD
  13706. #define DENOISE3D_THR_EDGE_H_INV_SHD_MASK 0x000FFFFFU
  13707. #define DENOISE3D_THR_EDGE_H_INV_SHD_SHIFT 0U
  13708. /* Register: ISP_DENOISE3D_EDGE_V_SHD 0x0000375C */
  13709. /* Slice: 27 : 20 denoise3d_strength_curve_temperal_shd */
  13710. #define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD
  13711. #define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD_MASK 0x0FF00000U
  13712. #define DENOISE3D_STRENGTH_CURVE_TEMPERAL_SHD_SHIFT 20U
  13713. /* Slice: 19 : 0 denoise3d_thr_edge_v_inv_shd */
  13714. #define DENOISE3D_THR_EDGE_V_INV_SHD
  13715. #define DENOISE3D_THR_EDGE_V_INV_SHD_MASK 0x000FFFFFU
  13716. #define DENOISE3D_THR_EDGE_V_INV_SHD_SHIFT 0U
  13717. /* Register: ISP_DENOISE3D_RANGE_S_SHD 0x00003760 */
  13718. /* Slice: 19 : 0 denoise3d_range_s_inv_shd */
  13719. #define DENOISE3D_RANGE_S_INV_SHD
  13720. #define DENOISE3D_RANGE_S_INV_SHD_MASK 0x000FFFFFU
  13721. #define DENOISE3D_RANGE_S_INV_SHD_SHIFT 0U
  13722. /* Register: ISP_DENOISE3D_RANGE_T_SHD 0x00003764 */
  13723. /* Slice: 29 : 25 denoise3d_range_t_h_shd */
  13724. #define DENOISE3D_RANGE_T_H_SHD
  13725. #define DENOISE3D_RANGE_T_H_SHD_MASK 0x3E000000U
  13726. #define DENOISE3D_RANGE_T_H_SHD_SHIFT 25U
  13727. /* Slice: 24 : 20 denoise3d_range_t_v_shd */
  13728. #define DENOISE3D_RANGE_T_V_SHD
  13729. #define DENOISE3D_RANGE_T_V_SHD_MASK 0x01F00000U
  13730. #define DENOISE3D_RANGE_T_V_SHD_SHIFT 20U
  13731. /* Slice: 19 : 0 denoise3d_range_t_inv_shd */
  13732. #define DENOISE3D_RANGE_T_INV_SHD
  13733. #define DENOISE3D_RANGE_T_INV_SHD_MASK 0x000FFFFFU
  13734. #define DENOISE3D_RANGE_T_INV_SHD_SHIFT 0U
  13735. /* Register: ISP_DENOISE3D_MOTION_SHD 0x00003768 */
  13736. /* Slice: 24 : 20 denoise3d_range_d_shd */
  13737. #define DENOISE3D_RANGE_D_SHD
  13738. #define DENOISE3D_RANGE_D_SHD_MASK 0x01F00000U
  13739. #define DENOISE3D_RANGE_D_SHD_SHIFT 20U
  13740. /* Slice: 19 : 0 denoise3d_motion_inv_shd */
  13741. #define DENOISE3D_MOTION_INV_SHD
  13742. #define DENOISE3D_MOTION_INV_SHD_MASK 0x000FFFFFU
  13743. #define DENOISE3D_MOTION_INV_SHD_SHIFT 0U
  13744. /* Register: ISP_DENOISE3D_DELTA_INV_SHD 0x0000376C */
  13745. /* Slice: 29 : 20 denoise3d_delta_h_inv_shd */
  13746. #define DENOISE3D_DELTA_H_INV_SHD
  13747. #define DENOISE3D_DELTA_H_INV_SHD_MASK 0x3FF00000U
  13748. #define DENOISE3D_DELTA_H_INV_SHD_SHIFT 20U
  13749. /* Slice: 19 : 10 denoise3d_delta_v_inv_shd */
  13750. #define DENOISE3D_DELTA_V_INV_SHD
  13751. #define DENOISE3D_DELTA_V_INV_SHD_MASK 0x000FFFFFU
  13752. #define DENOISE3D_DELTA_V_INV_SHD_SHIFT 10U
  13753. /* Slice: 9 : 0 denoise3d_delta_t_inv_shd */
  13754. #define DENOISE3D_DELTA_T_INV_SHD
  13755. #define DENOISE3D_DELTA_T_INV_SHD_MASK 0x000003FFU
  13756. #define DENOISE3D_DELTA_T_INV_SHD_SHIFT 0U
  13757. /* Register: ISP_DENOISE3D_DUMMY_HBLANK 0x00003770 */
  13758. /* Slice: 14 : 0 denoise3d_H_Blank */
  13759. #define DENOISE3D_H_BLANK
  13760. #define DENOISE3D_H_BLANK_MASK 0x0000FFFFU
  13761. #define DENOISE3D_H_BLANK_SHIFT 0U
  13762. /* Register: ISP_DENOISE3D_WEIGHT1 0x00003778 */
  13763. /* Slice: denoise3d_weight_up_y0 */
  13764. #define DENOISE3D_WEIGHT_UP_Y0
  13765. #define DENOISE3D_WEIGHT_UP_Y0_MASK 0x00F00000U
  13766. #define DENOISE3D_WEIGHT_UP_Y0_SHIFT 20U
  13767. #define DENOISE3D_WEIGHT_UP_Y1
  13768. #define DENOISE3D_WEIGHT_UP_Y1_MASK 0x000F0000U
  13769. #define DENOISE3D_WEIGHT_UP_Y1_SHIFT 16U
  13770. #define DENOISE3D_WEIGHT
  13771. #define DENOISE3D_WEIGHT_MASK 0x0000000FU
  13772. #define DENOISE3D_WEIGHT_SHIFT 0U
  13773. /*! for miv2 by shenchao */
  13774. /*! Register: miv2_ctrl (0x00001300)*/
  13775. /*! Slice: sp2_raw2_continous:*/
  13776. #define SP2_RAW2_CONTINUOUS
  13777. #define SP2_RAW2_CONTINUOUS_MASK 0x1 << 24
  13778. #define SP2_RAW2_CONTINUOUS_SHIFT 24U
  13779. #define SP2_RAW2_START
  13780. #define SP2_RAW2_START_MASK 0x1 << 23
  13781. #define SP2_RAW2_START_SHIFT 23U
  13782. #define PP_DMA_CONTINUOUS
  13783. #define PP_DMA_CONTINUOUS_MASK 0x1 << 22
  13784. #define PP_DMA_CONTINUOUS_SHIFT 22U
  13785. #define PP_DMA_START
  13786. #define PP_DMA_START_MASK 0x1 << 21
  13787. #define PP_DMA_START_SHIFT 21U
  13788. #define SP2_RAW2_WRITE_PATH_ENABLE
  13789. #define SP2_RAW2_WRITE_PATH_ENABLE_MASK 0x1 << 20
  13790. #define SP2_RAW2_WRITE_PATH_ENABLE_SHIFT 20U
  13791. #define PP_WRITE_PATH_ENABLE
  13792. #define PP_WRITE_PATH_ENABLE_MASK 0x1 << 19
  13793. #define PP_WRITE_PATH_ENABLE_SHIFT 19U
  13794. #define MCM_G2_RAW1_PATH_ENABLE
  13795. #define MCM_G2_RAW1_PATH_ENABLE_MASK 0x1 << 18
  13796. #define MCM_G2_RAW1_PATH_ENABLE_SHIFT 18U
  13797. #define MCM_G2_RAW0_PATH_ENABLE
  13798. #define MCM_G2_RAW0_PATH_ENABLE_MASK 0x1 << 17
  13799. #define MCM_G2_RAW0_PATH_ENABLE_SHIFT 17U
  13800. //! Register: isp_hdr_exp_conf: Exposure control (0x00000000)
  13801. //! Slice: exp_meas_mode:
  13802. //! '1' luminance calculation according to
  13803. // Y=(R+G+B) x 0.332 (85/256)
  13804. // '0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B
  13805. #define MRV_HDR_EXP_MEAS_MODE
  13806. #define MRV_HDR_EXP_MEAS_MODE_MASK 0x80000000U
  13807. #define MRV_HDR_EXP_MEAS_MODE_SHIFT 31U
  13808. //! Slice: src_select:
  13809. #define MRV_HDR_EXP_SRC_SEL
  13810. #define MRV_HDR_EXP_SRC_SEL_MASK 0x00000004U
  13811. #define MRV_HDR_EXP_SRC_SEL_SHIFT 2U
  13812. //! Slice: autostop:
  13813. //! '1' stop measuring after a complete frame
  13814. // '0' continous measurement
  13815. #define MRV_HDR_EXP_AUTOSTOP
  13816. #define MRV_HDR_EXP_AUTOSTOP_MASK 0x00000002U
  13817. #define MRV_HDR_EXP_AUTOSTOP_SHIFT 1U
  13818. //! Slice: exp_start:
  13819. //! '1' start measuring a frame. The exp block will reset this bit and halt after completing one frame, if bit "autostop" is set to '1'.
  13820. #define MRV_HDR_EXP_START
  13821. #define MRV_HDR_EXP_START_MASK 0x00000001U
  13822. #define MRV_HDR_EXP_START_SHIFT 0U
  13823. //! Register: isp_hdr_exp_h_offset: Horizontal offset for first block (0x00000004)
  13824. #define MRV_ISP_HDR_EXP_H_OFFSET
  13825. #define MRV_ISP_HDR_EXP_H_OFFSET_MASK 0x00001FFFU
  13826. #define MRV_ISP_HDR_EXP_H_OFFSET_SHIFT 0U
  13827. //! Register: isp_hdr_exp_v_offset: Vertical offset for first block (0x00000008)
  13828. #define MRV_ISP_HDR_EXP_V_OFFSET
  13829. #define MRV_ISP_HDR_EXP_V_OFFSET_MASK 0x00001FFFU
  13830. #define MRV_ISP_HDR_EXP_V_OFFSET_SHIFT 0U
  13831. //! Register: isp_exp_h_size: Horizontal size of one block (0x0000000c)
  13832. #define MRV_ISP_HDR_EXP_H_SIZE
  13833. #define MRV_ISP_HDR_EXP_H_SIZE_MASK 0x000007FFU
  13834. #define MRV_ISP_HDR_EXP_H_SIZE_SHIFT 0U
  13835. //! Register: isp_exp_v_size: Vertical size of one block (0x00000010)
  13836. #define MRV_ISP_HDR_EXP_V_SIZE
  13837. #define MRV_ISP_HDR_EXP_V_SIZE_MASK 0x000007FEU
  13838. #define MRV_ISP_HDR_EXP_V_SIZE_SHIFT 0U
  13839. /*! for miv2 by shenchao */
  13840. /*! Register: miv2_ctrl (0x00001300)*/
  13841. /*! Slice: mcm_raw_rdma_start_con:*/
  13842. #define MCM_RAW_RDMA_START_CON
  13843. #define MCM_RAW_RDMA_START_CON_MASK 0x00010000U
  13844. #define MCM_RAW_RDMA_START_CON_SHIFT 16U
  13845. /*! Slice: mcm_raw_rdma_start:*/
  13846. #define MCM_RAW_RDMA_START
  13847. #define MCM_RAW_RDMA_START_MASK 0x00008000U
  13848. #define MCM_RAW_RDMA_START_SHIFT 15U
  13849. /*! Slice: mcm_raw_rdma_path_enable:*/
  13850. #define MCM_RAW_RDMA_PATH_ENABLE
  13851. #define MCM_RAW_RDMA_PATH_ENABLE_MASK 0x00004000U
  13852. #define MCM_RAW_RDMA_PATH_ENABLE_SHIFT 14U
  13853. /*! Slice: sp2_raw2_rdma_start_con:*/
  13854. #define SP2_RAW2_RDMA_START_CON
  13855. #define SP2_RAW2_RDMA_START_CON_MASK 0x01000000U
  13856. #define SP2_RAW2_RDMA_START_CON_SHIFT 24U
  13857. /*! Slice: sp2_raw2_rdma_start:*/
  13858. #define SP2_RAW2_RDMA_START
  13859. #define SP2_RAW2_RDMA_START_MASK 0x00800000U
  13860. #define SP2_RAW2_RDMA_START_SHIFT 23U
  13861. /*! Slice: sp2_raw_rdma_start_con:*/
  13862. #define SP2_RAW_RDMA_START_CON
  13863. #define SP2_RAW_RDMA_START_CON_MASK 0x00002000U
  13864. #define SP2_RAW_RDMA_START_CON_SHIFT 13U
  13865. /*! Slice: sp2_raw_rdma_start:*/
  13866. #define SP2_RAW_RDMA_START
  13867. #define SP2_RAW_RDMA_START_MASK 0x00001000U
  13868. #define SP2_RAW_RDMA_START_SHIFT 12U
  13869. /*! Slice: sp2_raw_rdma_path_enable:*/
  13870. #define SP2_RAW_RDMA_PATH_ENABLE
  13871. #define SP2_RAW_RDMA_PATH_ENABLE_MASK 0x00000800U
  13872. #define SP2_RAW_RDMA_PATH_ENABLE_SHIFT 11U
  13873. /*! Slice: sp2_ycbcr_rdma_start_con:*/
  13874. #define SP2_YCBCR_RDMA_START_CON
  13875. #define SP2_YCBCR_RDMA_START_CON_MASK 0x00000400U
  13876. #define SP2_YCBCR_RDMA_START_CON_SHIFT 10U
  13877. /*! Slice: sp2_ycbcr_rdma_start:*/
  13878. #define SP2_YCBCR_RDMA_START
  13879. #define SP2_YCBCR_RDMA_START_MASK 0x00000200U
  13880. #define SP2_YCBCR_RDMA_START_SHIFT 9U
  13881. /*! Slice: sp2_ycbcr_rdma_path_enable:*/
  13882. #define SP2_YCBCR_RDMA_PATH_ENABLE
  13883. #define SP2_YCBCR_RDMA_PATH_ENABLE_MASK 0x00000100U
  13884. #define SP2_YCBCR_RDMA_PATH_ENABLE_SHIFT 8U
  13885. /*! Slice: mcm_raw1_path_enable:*/
  13886. #define MCM_RAW1_PATH_ENABLE
  13887. #define MCM_RAW1_PATH_ENABLE_MASK 0x00000080U
  13888. #define MCM_RAW1_PATH_ENABLE_SHIFT 7U
  13889. /*! Slice: mcm_raw0_path_enable:*/
  13890. #define MCM_RAW0_PATH_ENABLE
  13891. #define MCM_RAW0_PATH_ENABLE_MASK 0x00000040U
  13892. #define MCM_RAW0_PATH_ENABLE_SHIFT 6U
  13893. /*! Slice: sp2_raw_path_enable:*/
  13894. #define SP2_RAW_PATH_ENABLE
  13895. #define SP2_RAW_PATH_ENABLE_MASK 0x00000020U
  13896. #define SP2_RAW_PATH_ENABLE_SHIFT 5U
  13897. /*! Slice: sp2_ycbcr_path_enable:*/
  13898. #define SP2_YCBCR_PATH_ENABLE
  13899. #define SP2_YCBCR_PATH_ENABLE_MASK 0x00000010U
  13900. #define SP2_YCBCR_PATH_ENABLE_SHIFT 4U
  13901. /*! Slice: sp1_ycbcr_path_enable:*/
  13902. #define SP1_YCBCR_PATH_ENABLE
  13903. #define SP1_YCBCR_PATH_ENABLE_MASK 0x00000008U
  13904. #define SP1_YCBCR_PATH_ENABLE_SHIFT 3U
  13905. /*! Slice: mp_jdp_path_enable:*/
  13906. #define MP_JDP_PATH_ENABLE
  13907. #define MP_JDP_PATH_ENABLE_MASK 0x00000004U
  13908. #define MP_JDP_PATH_ENABLE_SHIFT 2U
  13909. /*! Slice: mp_raw_path_enable:*/
  13910. #define MP_RAW_PATH_ENABLE
  13911. #define MP_RAW_PATH_ENABLE_MASK 0x00000002U
  13912. #define MP_RAW_PATH_ENABLE_SHIFT 1U
  13913. /*! Slice: mp_ycbcr_path_enable:*/
  13914. #define MP_YCBCR_PATH_ENABLE
  13915. #define MP_YCBCR_PATH_ENABLE_MASK 0x00000001U
  13916. #define MP_YCBCR_PATH_ENABLE_SHIFT 0U
  13917. /*! Register: miv2_ctrl_shd (0x00001304)*/
  13918. /*! Slice: mcm_raw_rdma_start_con:*/
  13919. #define MCM_RAW_RDMA_START_CON
  13920. #define MCM_RAW_RDMA_START_CON_MASK 0x00010000U
  13921. #define MCM_RAW_RDMA_START_CON_SHIFT 16U
  13922. /*! Slice: mcm_raw_rdma_start:*/
  13923. #define MCM_RAW_RDMA_START
  13924. #define MCM_RAW_RDMA_START_MASK 0x00008000U
  13925. #define MCM_RAW_RDMA_START_SHIFT 15U
  13926. /*! Slice: mcm_raw_rdma_path_enable:*/
  13927. #define MCM_RAW_RDMA_PATH_ENABLE
  13928. #define MCM_RAW_RDMA_PATH_ENABLE_MASK 0x00004000U
  13929. #define MCM_RAW_RDMA_PATH_ENABLE_SHIFT 14U
  13930. /*! Slice: sp2_raw_rdma_start_con:*/
  13931. #define SP2_RAW_RDMA_START_CON
  13932. #define SP2_RAW_RDMA_START_CON_MASK 0x00002000U
  13933. #define SP2_RAW_RDMA_START_CON_SHIFT 13U
  13934. /*! Slice: sp2_raw_rdma_start:*/
  13935. #define SP2_RAW_RDMA_START
  13936. #define SP2_RAW_RDMA_START_MASK 0x00001000U
  13937. #define SP2_RAW_RDMA_START_SHIFT 12U
  13938. /*! Slice: sp2_raw_rdma_path_enable:*/
  13939. #define SP2_RAW_RDMA_PATH_ENABLE
  13940. #define SP2_RAW_RDMA_PATH_ENABLE_MASK 0x00000800U
  13941. #define SP2_RAW_RDMA_PATH_ENABLE_SHIFT 11U
  13942. /*! Slice: sp2_ycbcr_rdma_start_con:*/
  13943. #define SP2_YCBCR_RDMA_START_CON
  13944. #define SP2_YCBCR_RDMA_START_CON_MASK 0x00000400U
  13945. #define SP2_YCBCR_RDMA_START_CON_SHIFT 10U
  13946. /*! Slice: sp2_ycbcr_rdma_start:*/
  13947. #define SP2_YCBCR_RDMA_START
  13948. #define SP2_YCBCR_RDMA_START_MASK 0x00000200U
  13949. #define SP2_YCBCR_RDMA_START_SHIFT 9U
  13950. /*! Slice: sp2_ycbcr_rdma_path_enable:*/
  13951. #define SP2_YCBCR_RDMA_PATH_ENABLE
  13952. #define SP2_YCBCR_RDMA_PATH_ENABLE_MASK 0x00000100U
  13953. #define SP2_YCBCR_RDMA_PATH_ENABLE_SHIFT 8U
  13954. /*! Slice: mcm_raw1_path_enable:*/
  13955. #define MCM_RAW1_PATH_ENABLE
  13956. #define MCM_RAW1_PATH_ENABLE_MASK 0x00000080U
  13957. #define MCM_RAW1_PATH_ENABLE_SHIFT 7U
  13958. /*! Slice: mcm_raw0_path_enable:*/
  13959. #define MCM_RAW0_PATH_ENABLE
  13960. #define MCM_RAW0_PATH_ENABLE_MASK 0x00000040U
  13961. #define MCM_RAW0_PATH_ENABLE_SHIFT 6U
  13962. /*! Slice: sp2_raw_path_enable:*/
  13963. #define SP2_RAW_PATH_ENABLE
  13964. #define SP2_RAW_PATH_ENABLE_MASK 0x00000020U
  13965. #define SP2_RAW_PATH_ENABLE_SHIFT 5U
  13966. /*! Slice: sp2_ycbcr_path_enable:*/
  13967. #define SP2_YCBCR_PATH_ENABLE
  13968. #define SP2_YCBCR_PATH_ENABLE_MASK 0x00000010U
  13969. #define SP2_YCBCR_PATH_ENABLE_SHIFT 4U
  13970. /*! Slice: sp1_ycbcr_path_enable:*/
  13971. #define SP1_YCBCR_PATH_ENABLE
  13972. #define SP1_YCBCR_PATH_ENABLE_MASK 0x00000008U
  13973. #define SP1_YCBCR_PATH_ENABLE_SHIFT 3U
  13974. /*! Slice: mp_jdp_path_enable:*/
  13975. #define MP_JDP_PATH_ENABLE
  13976. #define MP_JDP_PATH_ENABLE_MASK 0x00000004U
  13977. #define MP_JDP_PATH_ENABLE_SHIFT 2U
  13978. /*! Slice: mp_raw_path_enable:*/
  13979. #define MP_RAW_PATH_ENABLE
  13980. #define MP_RAW_PATH_ENABLE_MASK 0x00000002U
  13981. #define MP_RAW_PATH_ENABLE_SHIFT 1U
  13982. /*! Slice: mp_ycbcr_path_enable:*/
  13983. #define MP_YCBCR_PATH_ENABLE
  13984. #define MP_YCBCR_PATH_ENABLE_MASK 0x00000001U
  13985. #define MP_YCBCR_PATH_ENABLE_SHIFT 0U
  13986. /*! Register: miv2_mp_ctrl (0x00001310)*/
  13987. /*! Slice: mp_init_offset_en:*/
  13988. #define MP_INIT_OFFSET_EN
  13989. #define MP_INIT_OFFSET_EN_MASK 0x00000020U
  13990. #define MP_INIT_OFFSET_EN_SHIFT 5U
  13991. /*! Slice: mp_init_base_en:*/
  13992. #define MP_INIT_BASE_EN
  13993. #define MP_INIT_BASE_EN_MASK 0x00000010U
  13994. #define MP_INIT_BASE_EN_SHIFT 4U
  13995. /*! Slice: mp_miv2_cfg_upd:*/
  13996. #define MP_MI_CFG_UPD
  13997. #define MP_MI_CFG_UPD_MASK 0x00000008U
  13998. #define MP_MI_CFG_UPD_SHIFT 3U
  13999. /*! Slice: mp_miv2_skip:*/
  14000. #define MP_MI_SKIP
  14001. #define MP_MI_SKIP_MASK 0x00000004U
  14002. #define MP_MI_SKIP_SHIFT 2U
  14003. /*! Slice: mp_auto_update:*/
  14004. #define MP_AUTO_UPDATE
  14005. #define MP_AUTO_UPDATE_MASK 0x00000002U
  14006. #define MP_AUTO_UPDATE_SHIFT 1U
  14007. /*! Slice: mp_pingpong_enable:*/
  14008. #define MP_PINGPONG_ENABLE
  14009. #define MP_PINGPONG_ENABLE_MASK 0x00000001U
  14010. #define MP_PINGPONG_ENABLE_SHIFT 0U
  14011. /*! Register: miv2_mp_fmt (0x00001314)*/
  14012. /*! Slice: mp_wr_jdp_dp_bit:*/
  14013. #define MP_WR_JDP_DP_BIT
  14014. #define MP_WR_JDP_DP_BIT_MASK 0x000020000U
  14015. #define MP_WR_JDP_DP_BIT_SHIFT 17U
  14016. /*! Slice: mp_wr_yuv_nvy:*/
  14017. #define MP_WR_YUV_NVY
  14018. #define MP_WR_YUV_NVY_MASK 0x00006000U
  14019. #define MP_WR_YUV_NVY_SHIFT 13U
  14020. /*! Slice: mp_wr_yuv_nv21:*/
  14021. #define MP_WR_YUV_NV21
  14022. #define MP_WR_YUV_NV21_MASK 0x00001000U
  14023. #define MP_WR_YUV_NV21_SHIFT 12U
  14024. /*! Slice: mp_wr_raw_aligned:*/
  14025. #define MP_WR_RAW_ALIGNED
  14026. #define MP_WR_RAW_ALIGNED_MASK 0x00000C00U
  14027. #define MP_WR_RAW_ALIGNED_SHIFT 10U
  14028. /*! Slice: mp_wr_yuv_aligned:*/
  14029. #define MP_WR_YUV_ALIGNED
  14030. #define MP_WR_YUV_ALIGNED_MASK 0x00000200U
  14031. #define MP_WR_YUV_ALIGNED_SHIFT 9U
  14032. /*! Slice: mp_wr_raw_bit:*/
  14033. #define MP_WR_RAW_BIT
  14034. #define MP_WR_RAW_BIT_MASK 0x000001C0U
  14035. #define MP_WR_RAW_BIT_SHIFT 6U
  14036. /*! Slice: mp_wr_yuv_str:*/
  14037. #define MP_WR_YUV_STR
  14038. #define MP_WR_YUV_STR_MASK 0x00000030U
  14039. #define MP_WR_YUV_STR_SHIFT 4U
  14040. /*! Slice: mp_wr_yuv_fmt:*/
  14041. #define MP_WR_YUV_FMT
  14042. #define MP_WR_YUV_FMT_MASK 0x0000000CU
  14043. #define MP_WR_YUV_FMT_SHIFT 2U
  14044. /*! Slice: mp_wr_yuv_bit:*/
  14045. #define MP_WR_YUV_BIT
  14046. #define MP_WR_YUV_BIT_MASK 0x00000002U
  14047. #define MP_WR_YUV_BIT_SHIFT 1U
  14048. /*! Slice: mp_wr_jdp_fmt:*/
  14049. #define MP_WR_JDP_FMT
  14050. #define MP_WR_JDP_FMT_MASK 0x00000001U
  14051. #define MP_WR_JDP_FMT_SHIFT 0U
  14052. /*! Register: miv2_mp_bus_cfg (0x00001318)*/
  14053. /*! Slice: mp_wr_swap_jdp:*/
  14054. #define MP_WR_SWAP_JDP
  14055. #define MP_WR_SWAP_JDP_MASK 0x0F000000U
  14056. #define MP_WR_SWAP_JDP_SHIFT 24U
  14057. /*! Slice: mp_wr_swap_raw:*/
  14058. #define MP_WR_SWAP_RAW
  14059. #define MP_WR_SWAP_RAW_MASK 0x00F00000U
  14060. #define MP_WR_SWAP_RAW_SHIFT 20U
  14061. /*! Slice: mp_wr_swap_v:*/
  14062. #define MP_WR_SWAP_V
  14063. #define MP_WR_SWAP_V_MASK 0x000F0000U
  14064. #define MP_WR_SWAP_V_SHIFT 16U
  14065. /*! Slice: mp_wr_swap_u:*/
  14066. #define MP_WR_SWAP_U
  14067. #define MP_WR_SWAP_U_MASK 0x0000F000U
  14068. #define MP_WR_SWAP_U_SHIFT 12U
  14069. /*! Slice: mp_wr_swap_y:*/
  14070. #define MP_WR_SWAP_Y
  14071. #define MP_WR_SWAP_Y_MASK 0x00000F00U
  14072. #define MP_WR_SWAP_Y_SHIFT 8U
  14073. /*! Slice: mp_rd_issue_cap:*/
  14074. #define MP_RD_ISSUE_CAP
  14075. #define MP_RD_ISSUE_CAP_MASK 0x000000C0U
  14076. #define MP_RD_ISSUE_CAP_SHIFT 6U
  14077. /*! Slice: mp_wr_issue_cap:*/
  14078. #define MP_WR_ISSUE_CAP
  14079. #define MP_WR_ISSUE_CAP_MASK 0x00000030U
  14080. #define MP_WR_ISSUE_CAP_SHIFT 4U
  14081. /*! Slice: mp_rd_burst_len:*/
  14082. #define MP_RD_BURST_LEN
  14083. #define MP_RD_BURST_LEN_MASK 0x0000000CU
  14084. #define MP_RD_BURST_LEN_SHIFT 2U
  14085. /*! Slice: mp_wr_burst_len:*/
  14086. #define MP_WR_BURST_LEN
  14087. #define MP_WR_BURST_LEN_MASK 0x00000003U
  14088. #define MP_WR_BURST_LEN_SHIFT 0U
  14089. /*! Register: miv2_mp_bus_id (0x0000131c)*/
  14090. /*! Slice: mp_bus_sw_en:*/
  14091. #define MP_BUS_SW_EN
  14092. #define MP_BUS_SW_EN_MASK 0x02000000U
  14093. #define MP_BUS_SW_EN_SHIFT 25U
  14094. /*! Slice: mp_rd_id_en:*/
  14095. #define MP_RD_ID_EN
  14096. #define MP_RD_ID_EN_MASK 0x01000000U
  14097. #define MP_RD_ID_EN_SHIFT 24U
  14098. /*! Slice: mp_rd_id_cfg:*/
  14099. #define MP_RD_ID_CFG
  14100. #define MP_RD_ID_CFG_MASK 0x00FF0000U
  14101. #define MP_RD_ID_CFG_SHIFT 16U
  14102. /*! Slice: mp_wr_id_en:*/
  14103. #define MP_WR_ID_EN
  14104. #define MP_WR_ID_EN_MASK 0x00000100U
  14105. #define MP_WR_ID_EN_SHIFT 8U
  14106. /*! Slice: mp_wr_id_cfg:*/
  14107. #define MP_WR_ID_CFG
  14108. #define MP_WR_ID_CFG_MASK 0x000000FFU
  14109. #define MP_WR_ID_CFG_SHIFT 0U
  14110. /*! Register: miv2_mp_bus_timeo (0x00001320)*/
  14111. /*! Slice: mp_bus_timeo_en:*/
  14112. #define MP_BUS_TIMEO_EN
  14113. #define MP_BUS_TIMEO_EN_MASK 0x80000000U
  14114. #define MP_BUS_TIMEO_EN_SHIFT 31U
  14115. /*! Slice: mp_bus_timeo:*/
  14116. #define MP_BUS_TIMEO
  14117. #define MP_BUS_TIMEO_MASK 0x7FFFFFFEU
  14118. #define MP_BUS_TIMEO_SHIFT 1U
  14119. /*! Slice: mp_bus_timeo_interrupt_disable:*/
  14120. /*! 0 enable 1 disable*/
  14121. #define MP_BUS_TIMEO_INTERRUPT_DISABLE
  14122. #define MP_BUS_TIMEO_INTERRUPT_DISABLE_MASK 1U
  14123. #define MP_BUS_TIMEO_INTERRUPT_DISABLE_SHIFT 0U
  14124. /*! Register: miv2_mp_y_base_ad_init (0x00001324)*/
  14125. /*! Slice: mp_y_base_ad_init:*/
  14126. #define MP_Y_BASE_AD_INIT
  14127. #define MP_Y_BASE_AD_INIT_MASK 0xFFFFFFF0U
  14128. #define MP_Y_BASE_AD_INIT_SHIFT 4U
  14129. /*! Register: miv2_mp_y_size_init (0x00001328)*/
  14130. /*! Slice: mp_y_size_init:*/
  14131. #define MP_Y_SIZE_INIT
  14132. #define MP_Y_SIZE_INIT_MASK 0x1FFFFFF0U
  14133. #define MP_Y_SIZE_INIT_SHIFT 4U
  14134. /*! Register: miv2_mp_y_offs_cnt_init (0x0000132c)*/
  14135. /*! Slice: mp_y_offs_cnt_init:*/
  14136. #define MP_Y_OFFS_CNT_INIT
  14137. #define MP_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF0U
  14138. #define MP_Y_OFFS_CNT_INIT_SHIFT 4U
  14139. /*! Register: miv2_mp_y_llength (0x00001330)*/
  14140. /*! Slice: mp_y_llengh:*/
  14141. #define MP_Y_LLENGH
  14142. #define MP_Y_LLENGH_MASK 0x00007FFFU
  14143. #define MP_Y_LLENGH_SHIFT 0U
  14144. /*! Register: miv2_mp_y_pic_width (0x00001334)*/
  14145. /*! Slice: mp_y_pic_width:*/
  14146. #define MP_Y_PIC_WIDTH
  14147. #define MP_Y_PIC_WIDTH_MASK 0xFFFFFFFFU
  14148. #define MP_Y_PIC_WIDTH_SHIFT 0U
  14149. /*! Register: miv2_mp_y_pic_height (0x00001338)*/
  14150. /*! Slice: mp_y_pic_height:*/
  14151. #define MP_Y_PIC_HEIGHT
  14152. #define MP_Y_PIC_HEIGHT_MASK 0xFFFFFFFFU
  14153. #define MP_Y_PIC_HEIGHT_SHIFT 0U
  14154. /*! Register: miv2_mp_y_pic_size (0x0000133c)*/
  14155. /*! Slice: mp_y_pic_size:*/
  14156. #define MP_Y_PIC_SIZE
  14157. #define MP_Y_PIC_SIZE_MASK 0xFFFFFFFFU
  14158. #define MP_Y_PIC_SIZE_SHIFT 0U
  14159. /*! Register: miv2_mp_cb_base_ad_init (0x00001340)*/
  14160. /*! Slice: mp_cb_base_ad_init:*/
  14161. #define MP_CB_BASE_AD_INIT
  14162. #define MP_CB_BASE_AD_INIT_MASK 0xFFFFFFF0U
  14163. #define MP_CB_BASE_AD_INIT_SHIFT 4U
  14164. /*! Register: miv2_mp_cb_size_init (0x00001344)*/
  14165. /*! Slice: mp_cb_size_init:*/
  14166. #define MP_CB_SIZE_INIT
  14167. #define MP_CB_SIZE_INIT_MASK 0x0FFFFFF0U
  14168. #define MP_CB_SIZE_INIT_SHIFT 4U
  14169. /*! Register: miv2_mp_cb_offs_cnt_init (0x00001348)*/
  14170. /*! Slice: mp_cb_offs_cnt_init:*/
  14171. #define MP_CB_OFFS_CNT_INIT
  14172. #define MP_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF0U
  14173. #define MP_CB_OFFS_CNT_INIT_SHIFT 4U
  14174. /*! Register: miv2_mp_cr_base_ad_init (0x0000134c)*/
  14175. /*! Slice: mp_cr_base_ad_init:*/
  14176. #define MP_CR_BASE_AD_INIT
  14177. #define MP_CR_BASE_AD_INIT_MASK 0xFFFFFFF0U
  14178. #define MP_CR_BASE_AD_INIT_SHIFT 4U
  14179. /*! Register: miv2_mp_cr_size_init (0x00001350)*/
  14180. /*! Slice: mp_cr_size_init:*/
  14181. #define MP_CR_SIZE_INIT
  14182. #define MP_CR_SIZE_INIT_MASK 0x0FFFFFF0U
  14183. #define MP_CR_SIZE_INIT_SHIFT 4U
  14184. /*! Register: miv2_mp_cr_offs_cnt_init (0x00001354)*/
  14185. /*! Slice: mp_cr_offs_cnt_init:*/
  14186. #define MP_CR_OFFS_CNT_INIT
  14187. #define MP_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF0U
  14188. #define MP_CR_OFFS_CNT_INIT_SHIFT 4U
  14189. /*! Register: miv2_mp_y_base_ad_init2 (0x00001358)*/
  14190. /*! Slice: mp_y_base_ad_init2:*/
  14191. #define MP_Y_BASE_AD_INIT2
  14192. #define MP_Y_BASE_AD_INIT2_MASK 0xFFFFFFF0U
  14193. #define MP_Y_BASE_AD_INIT2_SHIFT 4U
  14194. /*! Register: miv2_mp_cb_base_ad_init2 (0x0000135c)*/
  14195. /*! Slice: mp_cb_base_ad_init2:*/
  14196. #define MP_CB_BASE_AD_INIT2
  14197. #define MP_CB_BASE_AD_INIT2_MASK 0xFFFFFFF0U
  14198. #define MP_CB_BASE_AD_INIT2_SHIFT 4U
  14199. /*! Register: miv2_mp_cr_base_ad_init2 (0x00001360)*/
  14200. /*! Slice: mp_cr_base_ad_init2:*/
  14201. #define MP_CR_BASE_AD_INIT2
  14202. #define MP_CR_BASE_AD_INIT2_MASK 0xFFFFFFF0U
  14203. #define MP_CR_BASE_AD_INIT2_SHIFT 4U
  14204. /*! Register: miv2_mp_y_offs_cnt_start (0x00001364)*/
  14205. /*! Slice: mp_y_offs_cnt_start:*/
  14206. #define MP_Y_OFFS_CNT_START
  14207. #define MP_Y_OFFS_CNT_START_MASK 0x1FFFFFF0U
  14208. #define MP_Y_OFFS_CNT_START_SHIFT 4U
  14209. /*! Register: miv2_mp_cb_offs_cnt_start (0x00001368)*/
  14210. /*! Slice: mp_cb_offs_cnt_start:*/
  14211. #define MP_CB_OFFS_CNT_START
  14212. #define MP_CB_OFFS_CNT_START_MASK 0x0FFFFFF0U
  14213. #define MP_CB_OFFS_CNT_START_SHIFT 4U
  14214. /*! Register: miv2_mp_cr_offs_cnt_start (0x0000136c)*/
  14215. /*! Slice: mp_cr_offs_cnt_start:*/
  14216. #define MP_CR_OFFS_CNT_START
  14217. #define MP_CR_OFFS_CNT_START_MASK 0x0FFFFFF0U
  14218. #define MP_CR_OFFS_CNT_START_SHIFT 4U
  14219. /*! Register: miv2_mp_y_base_ad_shd (0x00001370)*/
  14220. /*! Slice: mp_y_base_ad:*/
  14221. #define MP_Y_BASE_AD
  14222. #define MP_Y_BASE_AD_MASK 0xFFFFFFF0U
  14223. #define MP_Y_BASE_AD_SHIFT 4U
  14224. /*! Register: miv2_mp_y_size_shd (0x00001374)*/
  14225. /*! Slice: mp_y_size:*/
  14226. #define MP_Y_SIZE
  14227. #define MP_Y_SIZE_MASK 0x1FFFFFF0U
  14228. #define MP_Y_SIZE_SHIFT 4U
  14229. /*! Register: miv2_mp_y_offs_cnt_shd (0x00001378)*/
  14230. /*! Slice: mp_y_offs_cnt:*/
  14231. #define MP_Y_OFFS_CNT
  14232. #define MP_Y_OFFS_CNT_MASK 0x1FFFFFF0U
  14233. #define MP_Y_OFFS_CNT_SHIFT 4U
  14234. /*! Register: miv2_mp_cb_base_ad_shd (0x0000137c)*/
  14235. /*! Slice: mp_cb_base_ad:*/
  14236. #define MP_CB_BASE_AD
  14237. #define MP_CB_BASE_AD_MASK 0xFFFFFFF0U
  14238. #define MP_CB_BASE_AD_SHIFT 4U
  14239. /*! Register: miv2_mp_cb_size_shd (0x00001380)*/
  14240. /*! Slice: mp_cb_size:*/
  14241. #define MP_CB_SIZE
  14242. #define MP_CB_SIZE_MASK 0x0FFFFFF0U
  14243. #define MP_CB_SIZE_SHIFT 4U
  14244. /*! Register: miv2_mp_cb_offs_cnt_shd (0x00001384)*/
  14245. /*! Slice: mp_cb_offs_cnt:*/
  14246. #define MP_CB_OFFS_CNT
  14247. #define MP_CB_OFFS_CNT_MASK 0x0FFFFFF0U
  14248. #define MP_CB_OFFS_CNT_SHIFT 4U
  14249. /*! Register: miv2_mp_cr_base_ad_shd (0x00001388)*/
  14250. /*! Slice: mp_cr_base_ad:*/
  14251. #define MP_CR_BASE_AD
  14252. #define MP_CR_BASE_AD_MASK 0xFFFFFFF0U
  14253. #define MP_CR_BASE_AD_SHIFT 4U
  14254. /*! Register: miv2_mp_cr_size_shd (0x0000138c)*/
  14255. /*! Slice: mp_cr_size:*/
  14256. #define MP_CR_SIZE
  14257. #define MP_CR_SIZE_MASK 0x0FFFFFF0U
  14258. #define MP_CR_SIZE_SHIFT 4U
  14259. /*! Register: miv2_mp_cr_offs_cnt_shd (0x00001390)*/
  14260. /*! Slice: mp_cr_offs_cnt:*/
  14261. #define MP_CR_OFFS_CNT
  14262. #define MP_CR_OFFS_CNT_MASK 0x0FFFFFF0U
  14263. #define MP_CR_OFFS_CNT_SHIFT 4U
  14264. /*! Register: miv2_mp_raw_base_ad_init (0x00001394)*/
  14265. /*! Slice: mp_raw_base_ad_init:*/
  14266. #define MP_RAW_BASE_AD_INIT
  14267. #define MP_RAW_BASE_AD_INIT_MASK 0xFFFFFFF0U
  14268. #define MP_RAW_BASE_AD_INIT_SHIFT 4U
  14269. /*! Register: miv2_mp_raw_size_init (0x00001398)*/
  14270. /*! Slice: mp_raw_size_init:*/
  14271. #define MP_RAW_SIZE_INIT
  14272. #define MP_RAW_SIZE_INIT_MASK 0x1FFFFFF0U
  14273. #define MP_RAW_SIZE_INIT_SHIFT 4U
  14274. /*! Register: miv2_mp_raw_offs_cnt_init (0x0000139c)*/
  14275. /*! Slice: mp_raw_offs_cnt_init:*/
  14276. #define MP_RAW_OFFS_CNT_INIT
  14277. #define MP_RAW_OFFS_CNT_INIT_MASK 0x1FFFFFF0U
  14278. #define MP_RAW_OFFS_CNT_INIT_SHIFT 4U
  14279. /*! Register: miv2_mp_raw_llength (0x000013a0)*/
  14280. /*! Slice: mp_raw_llengh:*/
  14281. #define MP_RAW_LLENGH
  14282. #define MP_RAW_LLENGH_MASK 0x00007FFFU
  14283. #define MP_RAW_LLENGH_SHIFT 0U
  14284. /*! Register: miv2_mp_raw_pic_width (0x000013a4)*/
  14285. /*! Slice: mp_raw_pic_width:*/
  14286. #define MP_RAW_PIC_WIDTH
  14287. #define MP_RAW_PIC_WIDTH_MASK 0xFFFFFFFFU
  14288. #define MP_RAW_PIC_WIDTH_SHIFT 0U
  14289. /*! Register: miv2_mp_raw_pic_height (0x000013a8)*/
  14290. /*! Slice: mp_raw_pic_height:*/
  14291. #define MP_RAW_PIC_HEIGHT
  14292. #define MP_RAW_PIC_HEIGHT_MASK 0xFFFFFFFFU
  14293. #define MP_RAW_PIC_HEIGHT_SHIFT 0U
  14294. /*! Register: miv2_mp_raw_pic_size (0x000013ac)*/
  14295. /*! Slice: mp_raw_pic_size:*/
  14296. #define MP_RAW_PIC_SIZE
  14297. #define MP_RAW_PIC_SIZE_MASK 0xFFFFFFFFU
  14298. #define MP_RAW_PIC_SIZE_SHIFT 0U
  14299. /*! Register: miv2_mp_raw_offs_cnt_start (0x000013b0)*/
  14300. /*! Slice: mp_raw_offs_cnt_start:*/
  14301. #define MP_RAW_OFFS_CNT_START
  14302. #define MP_RAW_OFFS_CNT_START_MASK 0x1FFFFFF0U
  14303. #define MP_RAW_OFFS_CNT_START_SHIFT 4U
  14304. /*! Register: miv2_mp_raw_base_ad_shd (0x000013b4)*/
  14305. /*! Slice: mp_raw_base_ad:*/
  14306. #define MP_RAW_BASE_AD
  14307. #define MP_RAW_BASE_AD_MASK 0xFFFFFFF0U
  14308. #define MP_RAW_BASE_AD_SHIFT 4U
  14309. /*! Register: miv2_mp_raw_size_shd (0x000013b8)*/
  14310. /*! Slice: mp_raw_size:*/
  14311. #define MP_RAW_SIZE
  14312. #define MP_RAW_SIZE_MASK 0x1FFFFFF0U
  14313. #define MP_RAW_SIZE_SHIFT 4U
  14314. /*! Register: miv2_mp_raw_offs_cnt_shd (0x000013bc)*/
  14315. /*! Slice: mp_raw_offs_cnt:*/
  14316. #define MP_RAW_OFFS_CNT
  14317. #define MP_RAW_OFFS_CNT_MASK 0x1FFFFFF0U
  14318. #define MP_RAW_OFFS_CNT_SHIFT 4U
  14319. /*! Register: miv2_mp_jdp_base_ad_init (0x000013c0)*/
  14320. /*! Slice: mp_jdp_base_ad_init:*/
  14321. #define MP_JDP_BASE_AD_INIT
  14322. #define MP_JDP_BASE_AD_INIT_MASK 0xFFFFFFF0U
  14323. #define MP_JDP_BASE_AD_INIT_SHIFT 4U
  14324. /*! Register: miv2_mp_jdp_size_init (0x000013c4)*/
  14325. /*! Slice: mp_jdp_size_init:*/
  14326. #define MP_JDP_SIZE_INIT
  14327. #define MP_JDP_SIZE_INIT_MASK 0x1FFFFFF0U
  14328. #define MP_JDP_SIZE_INIT_SHIFT 4U
  14329. /*! Register: miv2_mp_jdp_offs_cnt_init (0x000013c8)*/
  14330. /*! Slice: mp_jdp_offs_cnt_init:*/
  14331. #define MP_JDP_OFFS_CNT_INIT
  14332. #define MP_JDP_OFFS_CNT_INIT_MASK 0x1FFFFFF0U
  14333. #define MP_JDP_OFFS_CNT_INIT_SHIFT 4U
  14334. /*! Register: miv2_mp_jdp_llength (0x000013cc)*/
  14335. /*! Slice: mp_jdp_llengh:*/
  14336. #define MP_JDP_LLENGH
  14337. #define MP_JDP_LLENGH_MASK 0x00007FFFU
  14338. #define MP_JDP_LLENGH_SHIFT 0U
  14339. /*! Register: miv2_mp_jdp_pic_width (0x000013d0)*/
  14340. /*! Slice: mp_jdp_pic_width:*/
  14341. #define MP_JDP_PIC_WIDTH
  14342. #define MP_JDP_PIC_WIDTH_MASK 0xFFFFFFFFU
  14343. #define MP_JDP_PIC_WIDTH_SHIFT 0U
  14344. /*! Register: miv2_mp_jdp_pic_height (0x000013d4)*/
  14345. /*! Slice: mp_jdp_pic_height:*/
  14346. #define MP_JDP_PIC_HEIGHT
  14347. #define MP_JDP_PIC_HEIGHT_MASK 0xFFFFFFFFU
  14348. #define MP_JDP_PIC_HEIGHT_SHIFT 0U
  14349. /*! Register: miv2_mp_jdp_pic_size (0x000013d8)*/
  14350. /*! Slice: mp_jdp_pic_size:*/
  14351. #define MP_JDP_PIC_SIZE
  14352. #define MP_JDP_PIC_SIZE_MASK 0xFFFFFFFFU
  14353. #define MP_JDP_PIC_SIZE_SHIFT 0U
  14354. /*! Register: miv2_mp_jdp_offs_cnt_start (0x000013dc)*/
  14355. /*! Slice: mp_jdp_offs_cnt_start:*/
  14356. #define MP_JDP_OFFS_CNT_START
  14357. #define MP_JDP_OFFS_CNT_START_MASK 0x1FFFFFF0U
  14358. #define MP_JDP_OFFS_CNT_START_SHIFT 4U
  14359. /*! Register: miv2_mp_jdp_base_ad_shd (0x000013e0)*/
  14360. /*! Slice: mp_jdp_base_ad:*/
  14361. #define MP_JDP_BASE_AD
  14362. #define MP_JDP_BASE_AD_MASK 0xFFFFFFF0U
  14363. #define MP_JDP_BASE_AD_SHIFT 4U
  14364. /*! Register: miv2_mp_jdp_size_shd (0x000013e4)*/
  14365. /*! Slice: mp_jdp_size:*/
  14366. #define MP_JDP_SIZE
  14367. #define MP_JDP_SIZE_MASK 0x1FFFFFF0U
  14368. #define MP_JDP_SIZE_SHIFT 4U
  14369. /*! Register: miv2_mp_jdp_offs_cnt_shd (0x000013e8)*/
  14370. /*! Slice: mp_jdp_offs_cnt:*/
  14371. #define MP_JDP_OFFS_CNT
  14372. #define MP_JDP_OFFS_CNT_MASK 0x1FFFFFF0U
  14373. #define MP_JDP_OFFS_CNT_SHIFT 4U
  14374. /*! Register: miv2_mp_status_clr (0x000013ec) */
  14375. /*! Slice: mp_jdp_fifo_full: */
  14376. #define MP_JDP_FIFO_FULL
  14377. #define MP_JDP_FIFO_FULL_MASK 0x00000010U
  14378. #define MP_JDP_FIFO_FULL_SHIFT 4U
  14379. /*! Slice: mp_raw_fifo_full:*/
  14380. #define MP_RAW_FIFO_FULL
  14381. #define MP_RAW_FIFO_FULL_MASK 0x00000008U
  14382. #define MP_RAW_FIFO_FULL_SHIFT 3U
  14383. /*! Slice: mp_cr_fifo_full:*/
  14384. #define MP_CR_FIFO_FULL
  14385. #define MP_CR_FIFO_FULL_MASK 0x00000004U
  14386. #define MP_CR_FIFO_FULL_SHIFT 2U
  14387. /*! Slice: mp_cb_fifo_full:*/
  14388. #define MP_CB_FIFO_FULL
  14389. #define MP_CB_FIFO_FULL_MASK 0x00000002U
  14390. #define MP_CB_FIFO_FULL_SHIFT 1U
  14391. /*! Slice: mp_y_fifo_full:*/
  14392. #define MP_Y_FIFO_FULL
  14393. #define MP_Y_FIFO_FULL_MASK 0x00000001U
  14394. #define MP_Y_FIFO_FULL_SHIFT 0U
  14395. /*! Register: miv2_mp_ctrl_status (0x000013f0) */
  14396. /*! Slice: mp_jdp_fifo_full: */
  14397. #define MP_JDP_FIFO_FULL
  14398. #define MP_JDP_FIFO_FULL_MASK 0x00000010U
  14399. #define MP_JDP_FIFO_FULL_SHIFT 4U
  14400. /*! Slice: mp_raw_fifo_full: */
  14401. #define MP_RAW_FIFO_FULL
  14402. #define MP_RAW_FIFO_FULL_MASK 0x00000008U
  14403. #define MP_RAW_FIFO_FULL_SHIFT 3U
  14404. /*! Slice: mp_cr_fifo_full: */
  14405. #define MP_CR_FIFO_FULL
  14406. #define MP_CR_FIFO_FULL_MASK 0x00000004U
  14407. #define MP_CR_FIFO_FULL_SHIFT 2U
  14408. /*! Slice: mp_cb_fifo_full: */
  14409. #define MP_CB_FIFO_FULL
  14410. #define MP_CB_FIFO_FULL_MASK 0x00000002U
  14411. #define MP_CB_FIFO_FULL_SHIFT 1U
  14412. /*! Slice: mp_y_fifo_full: */
  14413. #define MP_Y_FIFO_FULL
  14414. #define MP_Y_FIFO_FULL_MASK 0x00000001U
  14415. #define MP_Y_FIFO_FULL_SHIFT 0U
  14416. /*! Register: miv2_mp_axi_status (0x000013f4) */
  14417. /*! Slice: agsw_enc_pic_rdy: */
  14418. #define AGSW_ENC_PIC_RDY
  14419. #define AGSW_ENC_PIC_RDY_MASK 0x00000002U
  14420. #define AGSW_ENC_PIC_RDY_SHIFT 1U
  14421. /*! Slice: agsw_enc_buf_full:*/
  14422. #define AGSW_ENC_BUF_FULL
  14423. #define AGSW_ENC_BUF_FULL_MASK 0x00000001U
  14424. #define AGSW_ENC_BUF_FULL_SHIFT 0U
  14425. /*! Register: miv2_mp_raw_byte_cnt_status (0x000013f8)*/
  14426. /*! Slice: mp_raw_byte_cnt_status:*/
  14427. #define MP_RAW_BYTE_CNT_STATUS
  14428. #define MP_RAW_BYTE_CNT_STATUS_MASK 0x0FFFFFFFU
  14429. #define MP_RAW_BYTE_CNT_STATUS_SHIFT 0U
  14430. /*! Register: miv2_mp_jdp_byte_cnt_status (0x000013fc)*/
  14431. /*! Slice: mp_jdp_byte_cnt_status:*/
  14432. #define MP_JDP_BYTE_CNT_STATUS
  14433. #define MP_JDP_BYTE_CNT_STATUS_MASK 0x0FFFFFFFU
  14434. #define MP_JDP_BYTE_CNT_STATUS_SHIFT 0U
  14435. /*! Register: miv2_mp_dp_byte_cnt_status (0x00001400)*/
  14436. /*! Slice: mp_dp_byte_cnt_status:*/
  14437. #define MP_DP_BYTE_CNT_STATUS
  14438. #define MP_DP_BYTE_CNT_STATUS_MASK 0x0FFFFFFFU
  14439. #define MP_DP_BYTE_CNT_STATUS_SHIFT 0U
  14440. /*! Register: miv2_sp1_ctrl (0x0000142c)*/
  14441. /*! Slice: sp1_init_offset_en:*/
  14442. #define SP1_INIT_OFFSET_EN
  14443. #define SP1_INIT_OFFSET_EN_MASK 0x00000020U
  14444. #define SP1_INIT_OFFSET_EN_SHIFT 5U
  14445. /*! Slice: sp1_init_base_en:*/
  14446. #define SP1_INIT_BASE_EN
  14447. #define SP1_INIT_BASE_EN_MASK 0x00000010U
  14448. #define SP1_INIT_BASE_EN_SHIFT 4U
  14449. /*! Slice: sp1_miv2_cfg_upd:*/
  14450. #define SP1_MI_CFG_UPD
  14451. #define SP1_MI_CFG_UPD_MASK 0x00000008U
  14452. #define SP1_MI_CFG_UPD_SHIFT 3U
  14453. /*! Slice: sp1_miv2_skip:*/
  14454. #define SP1_MI_SKIP
  14455. #define SP1_MI_SKIP_MASK 0x00000004U
  14456. #define SP1_MI_SKIP_SHIFT 2U
  14457. /*! Slice: sp1_auto_update:*/
  14458. #define SP1_AUTO_UPDATE
  14459. #define SP1_AUTO_UPDATE_MASK 0x00000002U
  14460. #define SP1_AUTO_UPDATE_SHIFT 1U
  14461. /*! Slice: sp1_pingpong_enable:*/
  14462. #define SP1_PINGPONG_ENABLE
  14463. #define SP1_PINGPONG_ENABLE_MASK 0x00000001U
  14464. #define SP1_PINGPONG_ENABLE_SHIFT 0U
  14465. /*! Register: miv2_sp1_fmt (0x00001430)*/
  14466. /*! Slice: sp1_wr_yuv_nvy:*/
  14467. #define SP1_WR_YUV_NVY
  14468. #define SP1_WR_YUV_NVY_MASK 0x00000180U
  14469. #define SP1_WR_YUV_NVY_SHIFT 7U
  14470. /*! Slice: sp1_wr_yuv_nv21:*/
  14471. #define SP1_WR_YUV_NV21
  14472. #define SP1_WR_YUV_NV21_MASK 0x00000040U
  14473. #define SP1_WR_YUV_NV21_SHIFT 6U
  14474. /*! Slice: sp1_wr_yuv_aligned:*/
  14475. #define SP1_WR_YUV_ALIGNED
  14476. #define SP1_WR_YUV_ALIGNED_MASK 0x00000020U
  14477. #define SP1_WR_YUV_ALIGNED_SHIFT 5U
  14478. /*! Slice: sp1_wr_yuv_str:*/
  14479. #define SP1_WR_YUV_STR
  14480. #define SP1_WR_YUV_STR_MASK 0x00000018U
  14481. #define SP1_WR_YUV_STR_SHIFT 3U
  14482. /*! Slice: sp1_wr_yuv_fmt:*/
  14483. #define SP1_WR_YUV_FMT
  14484. #define SP1_WR_YUV_FMT_MASK 0x00000006U
  14485. #define SP1_WR_YUV_FMT_SHIFT 1U
  14486. /*! Slice: sp1_wr_yuv_bit:*/
  14487. #define SP1_WR_YUV_BIT
  14488. #define SP1_WR_YUV_BIT_MASK 0x00000001U
  14489. #define SP1_WR_YUV_BIT_SHIFT 0U
  14490. /*! Register: miv2_sp1_bus_cfg (0x00001434)*/
  14491. /*! Slice: sp1_wr_swap_v:*/
  14492. #define SP1_WR_SWAP_V
  14493. #define SP1_WR_SWAP_V_MASK 0x000F0000U
  14494. #define SP1_WR_SWAP_V_SHIFT 16U
  14495. /*! Slice: sp1_wr_swap_u:*/
  14496. #define SP1_WR_SWAP_U
  14497. #define SP1_WR_SWAP_U_MASK 0x0000F000U
  14498. #define SP1_WR_SWAP_U_SHIFT 12U
  14499. /*! Slice: sp1_wr_swap_y:*/
  14500. #define SP1_WR_SWAP_Y
  14501. #define SP1_WR_SWAP_Y_MASK 0x00000F00U
  14502. #define SP1_WR_SWAP_Y_SHIFT 8U
  14503. /*! Slice: sp1_rd_issue_cap:*/
  14504. #define SP1_RD_ISSUE_CAP
  14505. #define SP1_RD_ISSUE_CAP_MASK 0x000000C0U
  14506. #define SP1_RD_ISSUE_CAP_SHIFT 6U
  14507. /*! Slice: sp1_wr_issue_cap:*/
  14508. #define SP1_WR_ISSUE_CAP
  14509. #define SP1_WR_ISSUE_CAP_MASK 0x00000030U
  14510. #define SP1_WR_ISSUE_CAP_SHIFT 4U
  14511. /*! Slice: sp1_rd_burst_len:*/
  14512. #define SP1_RD_BURST_LEN
  14513. #define SP1_RD_BURST_LEN_MASK 0x0000000CU
  14514. #define SP1_RD_BURST_LEN_SHIFT 2U
  14515. /*! Slice: sp1_wr_burst_len:*/
  14516. #define SP1_WR_BURST_LEN
  14517. #define SP1_WR_BURST_LEN_MASK 0x00000003U
  14518. #define SP1_WR_BURST_LEN_SHIFT 0U
  14519. /*! Register: miv2_sp1_bus_id (0x00001438)*/
  14520. /*! Slice: sp1_bus_sw_en:*/
  14521. #define SP1_BUS_SW_EN
  14522. #define SP1_BUS_SW_EN_MASK 0x02000000U
  14523. #define SP1_BUS_SW_EN_SHIFT 25U
  14524. /*! Slice: sp1_rd_id_en:*/
  14525. #define SP1_RD_ID_EN
  14526. #define SP1_RD_ID_EN_MASK 0x01000000U
  14527. #define SP1_RD_ID_EN_SHIFT 24U
  14528. /*! Slice: sp1_rd_id_cfg:*/
  14529. #define SP1_RD_ID_CFG
  14530. #define SP1_RD_ID_CFG_MASK 0x00FF0000U
  14531. #define SP1_RD_ID_CFG_SHIFT 16U
  14532. /*! Slice: sp1_wr_id_en:*/
  14533. #define SP1_WR_ID_EN
  14534. #define SP1_WR_ID_EN_MASK 0x00000100U
  14535. #define SP1_WR_ID_EN_SHIFT 8U
  14536. /*! Slice: sp1_wr_id_cfg:*/
  14537. #define SP1_WR_ID_CFG
  14538. #define SP1_WR_ID_CFG_MASK 0x000000FFU
  14539. #define SP1_WR_ID_CFG_SHIFT 0U
  14540. /*! Register: miv2_sp1_bus_timeo (0x0000143c)*/
  14541. /*! Slice: sp1_bus_timeo_en:*/
  14542. #define SP1_BUS_TIMEO_EN
  14543. #define SP1_BUS_TIMEO_EN_MASK 0x80000000U
  14544. #define SP1_BUS_TIMEO_EN_SHIFT 31U
  14545. /*! Slice: sp1_bus_timeo:*/
  14546. #define SP1_BUS_TIMEO
  14547. #define SP1_BUS_TIMEO_MASK 0x7FFFFFFFU
  14548. #define SP1_BUS_TIMEO_SHIFT 0U
  14549. /*! Register: miv2_sp1_y_base_ad_init (0x00001440)*/
  14550. /*! Slice: sp1_y_base_ad_init:*/
  14551. #define SP1_Y_BASE_AD_INIT
  14552. #define SP1_Y_BASE_AD_INIT_MASK 0xFFFFFFF0U
  14553. #define SP1_Y_BASE_AD_INIT_SHIFT 4U
  14554. /*! Register: miv2_sp1_y_size_init (0x00001444)*/
  14555. /*! Slice: sp1_y_size_init:*/
  14556. #define SP1_Y_SIZE_INIT
  14557. #define SP1_Y_SIZE_INIT_MASK 0x1FFFFFF0U
  14558. #define SP1_Y_SIZE_INIT_SHIFT 4U
  14559. /*! Register: miv2_sp1_y_offs_cnt_init (0x00001448)*/
  14560. /*! Slice: sp1_y_offs_cnt_init:*/
  14561. #define SP1_Y_OFFS_CNT_INIT
  14562. #define SP1_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF0U
  14563. #define SP1_Y_OFFS_CNT_INIT_SHIFT 4U
  14564. /*! Register: miv2_sp1_y_llength (0x0000144c)*/
  14565. /*! Slice: sp1_y_llengh:*/
  14566. #define SP1_Y_LLENGH
  14567. #define SP1_Y_LLENGH_MASK 0x00007FFFU
  14568. #define SP1_Y_LLENGH_SHIFT 0U
  14569. /*! Register: miv2_sp1_y_pic_width (0x00001450)*/
  14570. /*! Slice: sp1_y_pic_width:*/
  14571. #define SP1_Y_PIC_WIDTH
  14572. #define SP1_Y_PIC_WIDTH_MASK 0xFFFFFFFFU
  14573. #define SP1_Y_PIC_WIDTH_SHIFT 0U
  14574. /*! Register: miv2_sp1_y_pic_height (0x00001454)*/
  14575. /*! Slice: sp1_y_pic_height:*/
  14576. #define SP1_Y_PIC_HEIGHT
  14577. #define SP1_Y_PIC_HEIGHT_MASK 0xFFFFFFFFU
  14578. #define SP1_Y_PIC_HEIGHT_SHIFT 0U
  14579. /*! Register: miv2_sp1_y_pic_size (0x00001458)*/
  14580. /*! Slice: sp1_y_pic_size:*/
  14581. #define SP1_Y_PIC_SIZE
  14582. #define SP1_Y_PIC_SIZE_MASK 0xFFFFFFFFU
  14583. #define SP1_Y_PIC_SIZE_SHIFT 0U
  14584. /*! Register: miv2_sp1_cb_base_ad_init (0x0000145c)*/
  14585. /*! Slice: sp1_cb_base_ad_init:*/
  14586. #define SP1_CB_BASE_AD_INIT
  14587. #define SP1_CB_BASE_AD_INIT_MASK 0xFFFFFFF0U
  14588. #define SP1_CB_BASE_AD_INIT_SHIFT 4U
  14589. /*! Register: miv2_sp1_cb_size_init (0x00001460)*/
  14590. /*! Slice: sp1_cb_size_init:*/
  14591. #define SP1_CB_SIZE_INIT
  14592. #define SP1_CB_SIZE_INIT_MASK 0x0FFFFFF0U
  14593. #define SP1_CB_SIZE_INIT_SHIFT 4U
  14594. /*! Register: miv2_sp1_cb_offs_cnt_init (0x00001464)*/
  14595. /*! Slice: sp1_cb_offs_cnt_init:*/
  14596. #define SP1_CB_OFFS_CNT_INIT
  14597. #define SP1_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF0U
  14598. #define SP1_CB_OFFS_CNT_INIT_SHIFT 4U
  14599. /*! Register: miv2_sp1_cr_base_ad_init (0x00001468)*/
  14600. /*! Slice: sp1_cr_base_ad_init:*/
  14601. #define SP1_CR_BASE_AD_INIT
  14602. #define SP1_CR_BASE_AD_INIT_MASK 0xFFFFFFF0U
  14603. #define SP1_CR_BASE_AD_INIT_SHIFT 4U
  14604. /*! Register: miv2_sp1_cr_size_init (0x0000146c)*/
  14605. /*! Slice: sp1_cr_size_init:*/
  14606. #define SP1_CR_SIZE_INIT
  14607. #define SP1_CR_SIZE_INIT_MASK 0x0FFFFFF0U
  14608. #define SP1_CR_SIZE_INIT_SHIFT 4U
  14609. /*! Register: miv2_sp1_cr_offs_cnt_init (0x00001470)*/
  14610. /*! Slice: sp1_cr_offs_cnt_init:*/
  14611. #define SP1_CR_OFFS_CNT_INIT
  14612. #define SP1_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF0U
  14613. #define SP1_CR_OFFS_CNT_INIT_SHIFT 4U
  14614. /*! Register: miv2_sp1_y_base_ad_init2 (0x00001474)*/
  14615. /*! Slice: sp1_y_base_ad_init2:*/
  14616. #define SP1_Y_BASE_AD_INIT2
  14617. #define SP1_Y_BASE_AD_INIT2_MASK 0xFFFFFFF0U
  14618. #define SP1_Y_BASE_AD_INIT2_SHIFT 4U
  14619. /*! Register: miv2_sp1_cb_base_ad_init2 (0x00001478)*/
  14620. /*! Slice: sp1_cb_base_ad_init2:*/
  14621. #define SP1_CB_BASE_AD_INIT2
  14622. #define SP1_CB_BASE_AD_INIT2_MASK 0xFFFFFFF0U
  14623. #define SP1_CB_BASE_AD_INIT2_SHIFT 4U
  14624. /*! Register: miv2_sp1_cr_base_ad_init2 (0x0000147c)*/
  14625. /*! Slice: sp1_cr_base_ad_init2:*/
  14626. #define SP1_CR_BASE_AD_INIT2
  14627. #define SP1_CR_BASE_AD_INIT2_MASK 0xFFFFFFF0U
  14628. #define SP1_CR_BASE_AD_INIT2_SHIFT 4U
  14629. /*! Register: miv2_sp1_y_offs_cnt_start (0x00001480)*/
  14630. /*! Slice: sp1_y_offs_cnt_start:*/
  14631. #define SP1_Y_OFFS_CNT_START
  14632. #define SP1_Y_OFFS_CNT_START_MASK 0x1FFFFFF0U
  14633. #define SP1_Y_OFFS_CNT_START_SHIFT 4U
  14634. /*! Register: miv2_sp1_cb_offs_cnt_start (0x00001484)*/
  14635. /*! Slice: sp1_cb_offs_cnt_start:*/
  14636. #define SP1_CB_OFFS_CNT_START
  14637. #define SP1_CB_OFFS_CNT_START_MASK 0x0FFFFFF0U
  14638. #define SP1_CB_OFFS_CNT_START_SHIFT 4U
  14639. /*! Register: miv2_sp1_cr_offs_cnt_start (0x00001488)*/
  14640. /*! Slice: sp1_cr_offs_cnt_start:*/
  14641. #define SP1_CR_OFFS_CNT_START
  14642. #define SP1_CR_OFFS_CNT_START_MASK 0x0FFFFFF0U
  14643. #define SP1_CR_OFFS_CNT_START_SHIFT 4U
  14644. /*! Register: miv2_sp1_y_base_ad_shd (0x0000148c)*/
  14645. /*! Slice: sp1_y_base_ad:*/
  14646. #define SP1_Y_BASE_AD
  14647. #define SP1_Y_BASE_AD_MASK 0xFFFFFFF0U
  14648. #define SP1_Y_BASE_AD_SHIFT 4U
  14649. /*! Register: miv2_sp1_y_size_shd (0x00001490)*/
  14650. /*! Slice: sp1_y_size:*/
  14651. #define SP1_Y_SIZE
  14652. #define SP1_Y_SIZE_MASK 0x1FFFFFF0U
  14653. #define SP1_Y_SIZE_SHIFT 4U
  14654. /*! Register: miv2_sp1_y_offs_cnt_shd (0x00001494)*/
  14655. /*! Slice: sp1_y_offs_cnt:*/
  14656. #define SP1_Y_OFFS_CNT
  14657. #define SP1_Y_OFFS_CNT_MASK 0x1FFFFFF0U
  14658. #define SP1_Y_OFFS_CNT_SHIFT 4U
  14659. /*! Register: miv2_sp1_cb_base_ad_shd (0x00001498)*/
  14660. /*! Slice: sp1_cb_base_ad:*/
  14661. #define SP1_CB_BASE_AD
  14662. #define SP1_CB_BASE_AD_MASK 0xFFFFFFF0U
  14663. #define SP1_CB_BASE_AD_SHIFT 4U
  14664. /*! Register: miv2_sp1_cb_size_shd (0x0000149c)*/
  14665. /*! Slice: sp1_cb_size:*/
  14666. #define SP1_CB_SIZE
  14667. #define SP1_CB_SIZE_MASK 0x0FFFFFF0U
  14668. #define SP1_CB_SIZE_SHIFT 4U
  14669. /*! Register: miv2_sp1_cb_offs_cnt_shd (0x000014a0)*/
  14670. /*! Slice: sp1_cb_offs_cnt:*/
  14671. #define SP1_CB_OFFS_CNT
  14672. #define SP1_CB_OFFS_CNT_MASK 0x0FFFFFF0U
  14673. #define SP1_CB_OFFS_CNT_SHIFT 4U
  14674. /*! Register: miv2_sp1_cr_base_ad_shd (0x000014a4)*/
  14675. /*! Slice: sp1_cr_base_ad:*/
  14676. #define SP1_CR_BASE_AD
  14677. #define SP1_CR_BASE_AD_MASK 0xFFFFFFF0U
  14678. #define SP1_CR_BASE_AD_SHIFT 4U
  14679. /*! Register: miv2_sp1_cr_size_shd (0x000014a8)*/
  14680. /*! Slice: sp1_cr_size:*/
  14681. #define SP1_CR_SIZE
  14682. #define SP1_CR_SIZE_MASK 0x0FFFFFF0U
  14683. #define SP1_CR_SIZE_SHIFT 4U
  14684. /*! Register: miv2_sp1_cr_offs_cnt_shd (0x000014ac)*/
  14685. /*! Slice: sp1_cr_offs_cnt:*/
  14686. #define SP1_CR_OFFS_CNT
  14687. #define SP1_CR_OFFS_CNT_MASK 0x0FFFFFF0U
  14688. #define SP1_CR_OFFS_CNT_SHIFT 4U
  14689. /*! Register: miv2_sp1_status_clr (0x000014b0)*/
  14690. /*! Slice: sp1_cr_fifo_full:*/
  14691. #define SP1_CR_FIFO_FULL
  14692. #define SP1_CR_FIFO_FULL_MASK 0x00000004U
  14693. #define SP1_CR_FIFO_FULL_SHIFT 2U
  14694. /*! Slice: sp1_cb_fifo_full:*/
  14695. #define SP1_CB_FIFO_FULL
  14696. #define SP1_CB_FIFO_FULL_MASK 0x00000002U
  14697. #define SP1_CB_FIFO_FULL_SHIFT 1U
  14698. /*! Slice: sp1_y_fifo_full:*/
  14699. #define SP1_Y_FIFO_FULL
  14700. #define SP1_Y_FIFO_FULL_MASK 0x00000001U
  14701. #define SP1_Y_FIFO_FULL_SHIFT 0U
  14702. /*! Register: miv2_sp1_ctrl_status (0x000014b4)*/
  14703. /*! Slice: sp1_cr_fifo_full:*/
  14704. #define SP1_CR_FIFO_FULL
  14705. #define SP1_CR_FIFO_FULL_MASK 0x00000004U
  14706. #define SP1_CR_FIFO_FULL_SHIFT 2U
  14707. /*! Slice: sp1_cb_fifo_full:*/
  14708. #define SP1_CB_FIFO_FULL
  14709. #define SP1_CB_FIFO_FULL_MASK 0x00000002U
  14710. #define SP1_CB_FIFO_FULL_SHIFT 1U
  14711. /*! Slice: sp1_y_fifo_full:*/
  14712. #define SP1_Y_FIFO_FULL
  14713. #define SP1_Y_FIFO_FULL_MASK 0x00000001U
  14714. #define SP1_Y_FIFO_FULL_SHIFT 0U
  14715. /*! Register: miv2_sp1_axi_status (0x000014b8)*/
  14716. /*! Slice: agsw_enc_pic_rdy:*/
  14717. #define AGSW_ENC_PIC_RDY
  14718. #define AGSW_ENC_PIC_RDY_MASK 0x00000002U
  14719. #define AGSW_ENC_PIC_RDY_SHIFT 1U
  14720. /*! Slice: agsw_enc_buf_full:*/
  14721. #define AGSW_ENC_BUF_FULL
  14722. #define AGSW_ENC_BUF_FULL_MASK 0x00000001U
  14723. #define AGSW_ENC_BUF_FULL_SHIFT 0U
  14724. /*! Register: miv2_sp2_ctrl (0x000014e4)*/
  14725. /*! Slice: sp2_rd_raw_cfg_update */
  14726. #define SP2_RD_RAW_CFG_UPDATE
  14727. #define SP2_RD_RAW_CFG_UPDATE_MASK 0x00000200U
  14728. #define SP2_RD_RAW_CFG_UPDATE_SHIFT 9U
  14729. /*! Slice: sp2_rd_raw_auto_update */
  14730. #define SP2_RD_RAW_AUTO_UPDATE
  14731. #define SP2_RD_RAW_AUTO_UPDATE_MASK 0x00000100U
  14732. #define SP2_RD_RAW_AUTO_UPDATE_SHIFT 8U
  14733. /*! Slice: sp2_rd_yuv_cfg_update */
  14734. #define SP2_RD_YUV_CFG_UPDATE
  14735. #define SP2_RD_YUV_CFG_UPDATE_MASK 0x00000080U
  14736. #define SP2_RD_YUV_CFG_UPDATE_SHIFT 7U
  14737. /*! Slice: sp2_rd_yuv_auto_update */
  14738. #define SP2_RD_YUV_AUTO_UPDATE
  14739. #define SP2_RD_YUV_AUTO_UPDATE_MASK 0x00000040U
  14740. #define SP2_RD_YUV_AUTO_UPDATE_SHIFT 6U
  14741. /*! Slice: sp2_init_offset_en:*/
  14742. #define SP2_INIT_OFFSET_EN
  14743. #define SP2_INIT_OFFSET_EN_MASK 0x00000020U
  14744. #define SP2_INIT_OFFSET_EN_SHIFT 5U
  14745. /*! Slice: sp2_init_base_en:*/
  14746. #define SP2_INIT_BASE_EN
  14747. #define SP2_INIT_BASE_EN_MASK 0x00000010U
  14748. #define SP2_INIT_BASE_EN_SHIFT 4U
  14749. /*! Slice: sp2_miv2_cfg_upd:*/
  14750. #define SP2_MI_CFG_UPD
  14751. #define SP2_MI_CFG_UPD_MASK 0x00000008U
  14752. #define SP2_MI_CFG_UPD_SHIFT 3U
  14753. /*! Slice: sp2_miv2_skip:*/
  14754. #define SP2_MI_SKIP
  14755. #define SP2_MI_SKIP_MASK 0x00000004U
  14756. #define SP2_MI_SKIP_SHIFT 2U
  14757. /*! Slice: sp2_auto_update:*/
  14758. #define SP2_AUTO_UPDATE
  14759. #define SP2_AUTO_UPDATE_MASK 0x00000002U
  14760. #define SP2_AUTO_UPDATE_SHIFT 1U
  14761. /*! Slice: sp2_pingpong_enable:*/
  14762. #define SP2_PINGPONG_ENABLE
  14763. #define SP2_PINGPONG_ENABLE_MASK 0x00000001U
  14764. #define SP2_PINGPONG_ENABLE_SHIFT 0U
  14765. /*! Register: miv2_sp2_fmt (0x000014e8)*/
  14766. /*! Slice: sp2_rd_yuv_nvy:*/
  14767. #define SP2_RD_YUV_NVY
  14768. #define SP2_RD_YUV_NVY_MASK 0x0C000000U
  14769. #define SP2_RD_YUV_NVY_SHIFT 26U
  14770. /*! Slice: sp2_rd_yuv_nv21:*/
  14771. #define SP2_RD_YUV_NV21
  14772. #define SP2_RD_YUV_NV21_MASK 0x02000000U
  14773. #define SP2_RD_YUV_NV21_SHIFT 25U
  14774. /*! Slice: sp2_rd_raw_aligned:*/
  14775. #define SP2_RD_RAW_ALIGNED
  14776. #define SP2_RD_RAW_ALIGNED_MASK 0x01800000U
  14777. #define SP2_RD_RAW_ALIGNED_SHIFT 23U
  14778. /*! Slice: sp2_rd_yuv_aligned:*/
  14779. #define SP2_RD_YUV_ALIGNED
  14780. #define SP2_RD_YUV_ALIGNED_MASK 0x00400000U
  14781. #define SP2_RD_YUV_ALIGNED_SHIFT 22U
  14782. /*! Slice: sp2_rd_raw_bit:*/
  14783. #define SP2_RD_RAW_BIT
  14784. #define SP2_RD_RAW_BIT_MASK 0x00380000U
  14785. #define SP2_RD_RAW_BIT_SHIFT 19U
  14786. /*! Slice: sp2_rd_yuv_str:*/
  14787. #define SP2_RD_YUV_STR
  14788. #define SP2_RD_YUV_STR_MASK 0x00060000U
  14789. #define SP2_RD_YUV_STR_SHIFT 17U
  14790. /*! Slice: sp2_rd_yuv_fmt:*/
  14791. #define SP2_RD_YUV_FMT
  14792. #define SP2_RD_YUV_FMT_MASK 0x00018000U
  14793. #define SP2_RD_YUV_FMT_SHIFT 15U
  14794. /*! Slice: sp2_rd_yuv_bit:*/
  14795. #define SP2_RD_YUV_BIT
  14796. #define SP2_RD_YUV_BIT_MASK 0x00004000U
  14797. #define SP2_RD_YUV_BIT_SHIFT 14U
  14798. /*! Slice: sp2_wr_yuv_nvy:*/
  14799. #define SP2_WR_YUV_NVY
  14800. #define SP2_WR_YUV_NVY_MASK 0x00003000U
  14801. #define SP2_WR_YUV_NVY_SHIFT 12U
  14802. /*! Slice: sp2_wr_yuv_nv21:*/
  14803. #define SP2_WR_YUV_NV21
  14804. #define SP2_WR_YUV_NV21_MASK 0x00000800U
  14805. #define SP2_WR_YUV_NV21_SHIFT 11U
  14806. /*! Slice: sp2_wr_raw_aligned:*/
  14807. #define SP2_WR_RAW_ALIGNED
  14808. #define SP2_WR_RAW_ALIGNED_MASK 0x00000600U
  14809. #define SP2_WR_RAW_ALIGNED_SHIFT 9U
  14810. /*! Slice: sp2_wr_yuv_aligned:*/
  14811. #define SP2_WR_YUV_ALIGNED
  14812. #define SP2_WR_YUV_ALIGNED_MASK 0x00000100U
  14813. #define SP2_WR_YUV_ALIGNED_SHIFT 8U
  14814. /*! Slice: sp2_wr_raw_bit:*/
  14815. #define SP2_WR_RAW_BIT
  14816. #define SP2_WR_RAW_BIT_MASK 0x000000E0U
  14817. #define SP2_WR_RAW_BIT_SHIFT 5U
  14818. /*! Slice: sp2_wr_yuv_str:*/
  14819. #define SP2_WR_YUV_STR
  14820. #define SP2_WR_YUV_STR_MASK 0x00000018U
  14821. #define SP2_WR_YUV_STR_SHIFT 3U
  14822. /*! Slice: sp2_wr_yuv_fmt:*/
  14823. #define SP2_WR_YUV_FMT
  14824. #define SP2_WR_YUV_FMT_MASK 0x00000006U
  14825. #define SP2_WR_YUV_FMT_SHIFT 1U
  14826. /*! Slice: sp2_wr_yuv_bit:*/
  14827. #define SP2_WR_YUV_BIT
  14828. #define SP2_WR_YUV_BIT_MASK 0x00000001U
  14829. #define SP2_WR_YUV_BIT_SHIFT 0U
  14830. /*! Register: miv2_sp2_bus_cfg (0x000014ec)*/
  14831. /*! Slice: sp2_rd_swap_raw:*/
  14832. #define SP2_RD_SWAP_RAW
  14833. #define SP2_RD_SWAP_RAW_MASK 0xF0000000U
  14834. #define SP2_RD_SWAP_RAW_SHIFT 28U
  14835. /*! Slice: sp2_rd_swap_v:*/
  14836. #define SP2_RD_SWAP_V
  14837. #define SP2_RD_SWAP_V_MASK 0x0F000000U
  14838. #define SP2_RD_SWAP_V_SHIFT 24U
  14839. /*! Slice: sp2_rd_swap_u:*/
  14840. #define SP2_RD_SWAP_U
  14841. #define SP2_RD_SWAP_U_MASK 0x00F00000U
  14842. #define SP2_RD_SWAP_U_SHIFT 20U
  14843. /*! Slice: sp2_rd_swap_y:*/
  14844. #define SP2_RD_SWAP_Y
  14845. #define SP2_RD_SWAP_Y_MASK 0x000F0000U
  14846. #define SP2_RD_SWAP_Y_SHIFT 16U
  14847. /*! Slice: sp2_wr_swap_raw:*/
  14848. #define SP2_WR_SWAP_RAW
  14849. #define SP2_WR_SWAP_RAW_MASK 0x0000F000U
  14850. #define SP2_WR_SWAP_RAW_SHIFT 12U
  14851. /*! Slice: sp2_wr_swap_v:*/
  14852. #define SP2_WR_SWAP_V
  14853. #define SP2_WR_SWAP_V_MASK 0x00000F00U
  14854. #define SP2_WR_SWAP_V_SHIFT 8U
  14855. /*! Slice: sp2_wr_swap_u:*/
  14856. #define SP2_WR_SWAP_U
  14857. #define SP2_WR_SWAP_U_MASK 0x000000F0U
  14858. #define SP2_WR_SWAP_U_SHIFT 4U
  14859. /*! Slice: sp2_wr_swap_y:*/
  14860. #define SP2_WR_SWAP_Y
  14861. #define SP2_WR_SWAP_Y_MASK 0x0000000FU
  14862. #define SP2_WR_SWAP_Y_SHIFT 0U
  14863. /*! Register: miv2_sp2_bus_id (0x000014f0)*/
  14864. /*! Slice: sp2_bus_sw_en:*/
  14865. #define SP2_BUS_SW_EN
  14866. #define SP2_BUS_SW_EN_MASK 0x08000000U
  14867. #define SP2_BUS_SW_EN_SHIFT 27U
  14868. /*! Slice: sp2_rd_issue_cap:*/
  14869. #define SP2_RD_ISSUE_CAP
  14870. #define SP2_RD_ISSUE_CAP_MASK 0x06000000U
  14871. #define SP2_RD_ISSUE_CAP_SHIFT 25U
  14872. /*! Slice: sp2_wr_issue_cap:*/
  14873. #define SP2_WR_ISSUE_CAP
  14874. #define SP2_WR_ISSUE_CAP_MASK 0x01800000U
  14875. #define SP2_WR_ISSUE_CAP_SHIFT 23U
  14876. /*! Slice: sp2_rd_burst_len:*/
  14877. #define SP2_RD_BURST_LEN
  14878. #define SP2_RD_BURST_LEN_MASK 0x00600000U
  14879. #define SP2_RD_BURST_LEN_SHIFT 21U
  14880. /*! Slice: sp2_wr_burst_len:*/
  14881. #define SP2_WR_BURST_LEN
  14882. #define SP2_WR_BURST_LEN_MASK 0x00180000U
  14883. #define SP2_WR_BURST_LEN_SHIFT 19U
  14884. /*! Slice: sp2_rd_id_en:*/
  14885. #define SP2_RD_ID_EN
  14886. #define SP2_RD_ID_EN_MASK 0x00040000U
  14887. #define SP2_RD_ID_EN_SHIFT 18U
  14888. /*! Slice: sp2_rd_id_cfg:*/
  14889. #define SP2_RD_ID_CFG
  14890. #define SP2_RD_ID_CFG_MASK 0x0003FC00U
  14891. #define SP2_RD_ID_CFG_SHIFT 10U
  14892. /*! Slice: sp2_wr_id_en:*/
  14893. #define SP2_WR_ID_EN
  14894. #define SP2_WR_ID_EN_MASK 0x00000100U
  14895. #define SP2_WR_ID_EN_SHIFT 8U
  14896. /*! Slice: sp2_wr_id_cfg:*/
  14897. #define SP2_WR_ID_CFG
  14898. #define SP2_WR_ID_CFG_MASK 0x000000FFU
  14899. #define SP2_WR_ID_CFG_SHIFT 0U
  14900. /*! Register: miv2_sp2_bus_timeo (0x000014f4)*/
  14901. /*! Slice: sp2_bus_timeo_en:*/
  14902. #define SP2_BUS_TIMEO_EN
  14903. #define SP2_BUS_TIMEO_EN_MASK 0x80000000U
  14904. #define SP2_BUS_TIMEO_EN_SHIFT 31U
  14905. /*! Slice: sp2_bus_timeo:*/
  14906. #define SP2_BUS_TIMEO
  14907. #define SP2_BUS_TIMEO_MASK 0x7FFFFFFFU
  14908. #define SP2_BUS_TIMEO_SHIFT 0U
  14909. /*! Register: miv2_sp2_y_base_ad_init (0x000014f8)*/
  14910. /*! Slice: sp2_y_base_ad_init:*/
  14911. #define SP2_Y_BASE_AD_INIT
  14912. #define SP2_Y_BASE_AD_INIT_MASK 0xFFFFFFF0U
  14913. #define SP2_Y_BASE_AD_INIT_SHIFT 4U
  14914. /*! Register: miv2_sp2_y_size_init (0x000014fc)*/
  14915. /*! Slice: sp2_y_size_init:*/
  14916. #define SP2_Y_SIZE_INIT
  14917. #define SP2_Y_SIZE_INIT_MASK 0x1FFFFFF0U
  14918. #define SP2_Y_SIZE_INIT_SHIFT 4U
  14919. /*! Register: miv2_sp2_y_offs_cnt_init (0x00001500)*/
  14920. /*! Slice: sp2_y_offs_cnt_init:*/
  14921. #define SP2_Y_OFFS_CNT_INIT
  14922. #define SP2_Y_OFFS_CNT_INIT_MASK 0x1FFFFFF0U
  14923. #define SP2_Y_OFFS_CNT_INIT_SHIFT 4U
  14924. /*! Register: miv2_sp2_y_llength (0x00001504)*/
  14925. /*! Slice: sp2_y_llengh:*/
  14926. #define SP2_Y_LLENGH
  14927. #define SP2_Y_LLENGH_MASK 0x00007FFFU
  14928. #define SP2_Y_LLENGH_SHIFT 0U
  14929. /*! Register: miv2_sp2_y_pic_width (0x00001508)*/
  14930. /*! Slice: sp2_y_pic_width:*/
  14931. #define SP2_Y_PIC_WIDTH
  14932. #define SP2_Y_PIC_WIDTH_MASK 0xFFFFFFFFU
  14933. #define SP2_Y_PIC_WIDTH_SHIFT 0U
  14934. /*! Register: miv2_sp2_y_pic_height (0x0000150c)*/
  14935. /*! Slice: sp2_y_pic_height:*/
  14936. #define SP2_Y_PIC_HEIGHT
  14937. #define SP2_Y_PIC_HEIGHT_MASK 0xFFFFFFFFU
  14938. #define SP2_Y_PIC_HEIGHT_SHIFT 0U
  14939. /*! Register: miv2_sp2_y_pic_size (0x00001510)*/
  14940. /*! Slice: sp2_y_pic_size:*/
  14941. #define SP2_Y_PIC_SIZE
  14942. #define SP2_Y_PIC_SIZE_MASK 0xFFFFFFFFU
  14943. #define SP2_Y_PIC_SIZE_SHIFT 0U
  14944. /*! Register: miv2_sp2_cb_base_ad_init (0x00001514)*/
  14945. /*! Slice: sp2_cb_base_ad_init:*/
  14946. #define SP2_CB_BASE_AD_INIT
  14947. #define SP2_CB_BASE_AD_INIT_MASK 0xFFFFFFF0U
  14948. #define SP2_CB_BASE_AD_INIT_SHIFT 4U
  14949. /*! Register: miv2_sp2_cb_size_init (0x00001518)*/
  14950. /*! Slice: sp2_cb_size_init:*/
  14951. #define SP2_CB_SIZE_INIT
  14952. #define SP2_CB_SIZE_INIT_MASK 0x0FFFFFF0U
  14953. #define SP2_CB_SIZE_INIT_SHIFT 4U
  14954. /*! Register: miv2_sp2_cb_offs_cnt_init (0x0000151c)*/
  14955. /*! Slice: sp2_cb_offs_cnt_init:*/
  14956. #define SP2_CB_OFFS_CNT_INIT
  14957. #define SP2_CB_OFFS_CNT_INIT_MASK 0x0FFFFFF0U
  14958. #define SP2_CB_OFFS_CNT_INIT_SHIFT 4U
  14959. /*! Register: miv2_sp2_cr_base_ad_init (0x00001520)*/
  14960. /*! Slice: sp2_cr_base_ad_init:*/
  14961. #define SP2_CR_BASE_AD_INIT
  14962. #define SP2_CR_BASE_AD_INIT_MASK 0xFFFFFFF0U
  14963. #define SP2_CR_BASE_AD_INIT_SHIFT 4U
  14964. /*! Register: miv2_sp2_cr_size_init (0x00001524)*/
  14965. /*! Slice: sp2_cr_size_init:*/
  14966. #define SP2_CR_SIZE_INIT
  14967. #define SP2_CR_SIZE_INIT_MASK 0x0FFFFFF0U
  14968. #define SP2_CR_SIZE_INIT_SHIFT 4U
  14969. /*! Register: miv2_sp2_cr_offs_cnt_init (0x00001528)*/
  14970. /*! Slice: sp2_cr_offs_cnt_init:*/
  14971. #define SP2_CR_OFFS_CNT_INIT
  14972. #define SP2_CR_OFFS_CNT_INIT_MASK 0x0FFFFFF0U
  14973. #define SP2_CR_OFFS_CNT_INIT_SHIFT 4U
  14974. /*! Register: miv2_sp2_y_base_ad_init2 (0x0000152c)*/
  14975. /*! Slice: sp2_y_base_ad_init2:*/
  14976. #define SP2_Y_BASE_AD_INIT2
  14977. #define SP2_Y_BASE_AD_INIT2_MASK 0xFFFFFFF0U
  14978. #define SP2_Y_BASE_AD_INIT2_SHIFT 4U
  14979. /*! Register: miv2_sp2_cb_base_ad_init2 (0x00001530)*/
  14980. /*! Slice: sp2_cb_base_ad_init2:*/
  14981. #define SP2_CB_BASE_AD_INIT2
  14982. #define SP2_CB_BASE_AD_INIT2_MASK 0xFFFFFFF0U
  14983. #define SP2_CB_BASE_AD_INIT2_SHIFT 4U
  14984. /*! Register: miv2_sp2_cr_base_ad_init2 (0x00001534)*/
  14985. /*! Slice: sp2_cr_base_ad_init2:*/
  14986. #define SP2_CR_BASE_AD_INIT2
  14987. #define SP2_CR_BASE_AD_INIT2_MASK 0xFFFFFFF0U
  14988. #define SP2_CR_BASE_AD_INIT2_SHIFT 4U
  14989. /*! Register: miv2_sp2_y_offs_cnt_start (0x00001538)*/
  14990. /*! Slice: sp2_y_offs_cnt_start:*/
  14991. #define SP2_Y_OFFS_CNT_START
  14992. #define SP2_Y_OFFS_CNT_START_MASK 0x1FFFFFF0U
  14993. #define SP2_Y_OFFS_CNT_START_SHIFT 4U
  14994. /*! Register: miv2_sp2_cb_offs_cnt_start (0x0000153c)*/
  14995. /*! Slice: sp2_cb_offs_cnt_start:*/
  14996. #define SP2_CB_OFFS_CNT_START
  14997. #define SP2_CB_OFFS_CNT_START_MASK 0x0FFFFFF0U
  14998. #define SP2_CB_OFFS_CNT_START_SHIFT 4U
  14999. /*! Register: miv2_sp2_cr_offs_cnt_start (0x00001540)*/
  15000. /*! Slice: sp2_cr_offs_cnt_start:*/
  15001. #define SP2_CR_OFFS_CNT_START
  15002. #define SP2_CR_OFFS_CNT_START_MASK 0x0FFFFFF0U
  15003. #define SP2_CR_OFFS_CNT_START_SHIFT 4U
  15004. /*! Register: miv2_sp2_y_base_ad_shd (0x00001544)*/
  15005. /*! Slice: sp2_y_base_ad:*/
  15006. #define SP2_Y_BASE_AD
  15007. #define SP2_Y_BASE_AD_MASK 0xFFFFFFF0U
  15008. #define SP2_Y_BASE_AD_SHIFT 4U
  15009. /*! Register: miv2_sp2_y_size_shd (0x00001548)*/
  15010. /*! Slice: sp2_y_size:*/
  15011. #define SP2_Y_SIZE
  15012. #define SP2_Y_SIZE_MASK 0x1FFFFFF0U
  15013. #define SP2_Y_SIZE_SHIFT 4U
  15014. /*! Register: miv2_sp2_y_offs_cnt_shd (0x0000154c)*/
  15015. /*! Slice: sp2_y_offs_cnt:*/
  15016. #define SP2_Y_OFFS_CNT
  15017. #define SP2_Y_OFFS_CNT_MASK 0x1FFFFFF0U
  15018. #define SP2_Y_OFFS_CNT_SHIFT 4U
  15019. /*! Register: miv2_sp2_cb_base_ad_shd (0x00001550)*/
  15020. /*! Slice: sp2_cb_base_ad:*/
  15021. #define SP2_CB_BASE_AD
  15022. #define SP2_CB_BASE_AD_MASK 0xFFFFFFF0U
  15023. #define SP2_CB_BASE_AD_SHIFT 4U
  15024. /*! Register: miv2_sp2_cb_size_shd (0x00001554)*/
  15025. /*! Slice: sp2_cb_size:*/
  15026. #define SP2_CB_SIZE
  15027. #define SP2_CB_SIZE_MASK 0x0FFFFFF0U
  15028. #define SP2_CB_SIZE_SHIFT 4U
  15029. /*! Register: miv2_sp2_cb_offs_cnt_shd (0x00001558)*/
  15030. /*! Slice: sp2_cb_offs_cnt:*/
  15031. #define SP2_CB_OFFS_CNT
  15032. #define SP2_CB_OFFS_CNT_MASK 0x0FFFFFF0U
  15033. #define SP2_CB_OFFS_CNT_SHIFT 4U
  15034. /*! Register: miv2_sp2_cr_base_ad_shd (0x0000155c)*/
  15035. /*! Slice: sp2_cr_base_ad:*/
  15036. #define SP2_CR_BASE_AD
  15037. #define SP2_CR_BASE_AD_MASK 0xFFFFFFF0U
  15038. #define SP2_CR_BASE_AD_SHIFT 4U
  15039. /*! Register: miv2_sp2_cr_size_shd (0x00001560)*/
  15040. /*! Slice: sp2_cr_size:*/
  15041. #define SP2_CR_SIZE
  15042. #define SP2_CR_SIZE_MASK 0x0FFFFFF0U
  15043. #define SP2_CR_SIZE_SHIFT 4U
  15044. /*! Register: miv2_sp2_cr_offs_cnt_shd (0x00001564)*/
  15045. /*! Slice: sp2_cr_offs_cnt:*/
  15046. #define SP2_CR_OFFS_CNT
  15047. #define SP2_CR_OFFS_CNT_MASK 0x0FFFFFF0U
  15048. #define SP2_CR_OFFS_CNT_SHIFT 4U
  15049. /*! Register: miv2_sp2_raw_base_ad_init (0x00001568)*/
  15050. /*! Slice: sp2_raw_base_ad_init:*/
  15051. #define SP2_RAW_BASE_AD_INIT
  15052. #define SP2_RAW_BASE_AD_INIT_MASK 0xFFFFFFF0U
  15053. #define SP2_RAW_BASE_AD_INIT_SHIFT 4U
  15054. /*! Register: miv2_sp2_raw_size_init (0x0000156c)*/
  15055. /*! Slice: sp2_raw_size_init:*/
  15056. #define SP2_RAW_SIZE_INIT
  15057. #define SP2_RAW_SIZE_INIT_MASK 0x1FFFFFF0U
  15058. #define SP2_RAW_SIZE_INIT_SHIFT 4U
  15059. /*! Register: miv2_sp2_raw_offs_cnt_init (0x00001570)*/
  15060. /*! Slice: sp2_raw_offs_cnt_init:*/
  15061. #define SP2_RAW_OFFS_CNT_INIT
  15062. #define SP2_RAW_OFFS_CNT_INIT_MASK 0x1FFFFFF0U
  15063. #define SP2_RAW_OFFS_CNT_INIT_SHIFT 4U
  15064. /*! Register: miv2_sp2_raw_llength (0x00001574)*/
  15065. /*! Slice: sp2_raw_llengh:*/
  15066. #define SP2_RAW_LLENGH
  15067. #define SP2_RAW_LLENGH_MASK 0x00007FFFU
  15068. #define SP2_RAW_LLENGH_SHIFT 0U
  15069. /*! Register: miv2_sp2_raw_pic_width (0x00001578)*/
  15070. /*! Slice: sp2_raw_pic_width:*/
  15071. #define SP2_RAW_PIC_WIDTH
  15072. #define SP2_RAW_PIC_WIDTH_MASK 0xFFFFFFFFU
  15073. #define SP2_RAW_PIC_WIDTH_SHIFT 0U
  15074. /*! Register: miv2_sp2_raw_pic_height (0x0000157c)*/
  15075. /*! Slice: sp2_raw_pic_height:*/
  15076. #define SP2_RAW_PIC_HEIGHT
  15077. #define SP2_RAW_PIC_HEIGHT_MASK 0xFFFFFFFFU
  15078. #define SP2_RAW_PIC_HEIGHT_SHIFT 0U
  15079. /*! Register: miv2_sp2_raw_pic_size (0x00001580)*/
  15080. /*! Slice: sp2_raw_pic_size:*/
  15081. #define SP2_RAW_PIC_SIZE
  15082. #define SP2_RAW_PIC_SIZE_MASK 0xFFFFFFFFU
  15083. #define SP2_RAW_PIC_SIZE_SHIFT 0U
  15084. /*! Register: miv2_sp2_raw_offs_cnt_start (0x00001584)*/
  15085. /*! Slice: sp2_raw_offs_cnt_start:*/
  15086. #define SP2_RAW_OFFS_CNT_START
  15087. #define SP2_RAW_OFFS_CNT_START_MASK 0x1FFFFFF0U
  15088. #define SP2_RAW_OFFS_CNT_START_SHIFT 4U
  15089. /*! Register: miv2_sp2_raw_base_ad_shd (0x0000158c)*/
  15090. /*! Slice: sp2_raw_base_ad:*/
  15091. #define SP2_RAW_BASE_AD
  15092. #define SP2_RAW_BASE_AD_MASK 0xFFFFFFF0U
  15093. #define SP2_RAW_BASE_AD_SHIFT 4U
  15094. /*! Register: miv2_sp2_raw_size_shd (0x00001590)*/
  15095. /*! Slice: sp2_raw_size:*/
  15096. #define SP2_RAW_SIZE
  15097. #define SP2_RAW_SIZE_MASK 0x1FFFFFF0U
  15098. #define SP2_RAW_SIZE_SHIFT 4U
  15099. /*! Register: miv2_sp2_raw_offs_cnt_shd (0x00001594)*/
  15100. /*! Slice: sp2_raw_offs_cnt:*/
  15101. #define SP2_RAW_OFFS_CNT
  15102. #define SP2_RAW_OFFS_CNT_MASK 0x1FFFFFF0U
  15103. #define SP2_RAW_OFFS_CNT_SHIFT 4U
  15104. /*! Register: miv2_sp2_dma_y_pic_start_ad (0x00001598)*/
  15105. /*! Slice: sp2_dma_y_pic_start_ad:*/
  15106. #define SP2_DMA_Y_PIC_START_AD
  15107. #define SP2_DMA_Y_PIC_START_AD_MASK 0xFFFFFFF0U
  15108. #define SP2_DMA_Y_PIC_START_AD_SHIFT 4U
  15109. /*! Register: miv2_sp2_dma_y_pic_width (0x0000159c)*/
  15110. /*! Slice: sp2_dma_y_pic_width:*/
  15111. #define SP2_DMA_Y_PIC_WIDTH
  15112. #define SP2_DMA_Y_PIC_WIDTH_MASK 0x00007FFFU
  15113. #define SP2_DMA_Y_PIC_WIDTH_SHIFT 0U
  15114. /*! Register: miv2_sp2_dma_y_pic_llength (0x000015a0)*/
  15115. /*! Slice: sp2_dma_y_pic_llength:*/
  15116. #define SP2_DMA_Y_PIC_LLENGTH
  15117. #define SP2_DMA_Y_PIC_LLENGTH_MASK 0x00007FFFU
  15118. #define SP2_DMA_Y_PIC_LLENGTH_SHIFT 0U
  15119. /*! Register: miv2_sp2_dma_y_pic_size (0x000015a4)*/
  15120. /*! Slice: sp2_dma_y_pic_size:*/
  15121. #define SP2_DMA_Y_PIC_SIZE
  15122. #define SP2_DMA_Y_PIC_SIZE_MASK 0x0FFFFFFFU
  15123. #define SP2_DMA_Y_PIC_SIZE_SHIFT 0U
  15124. /*! Register: miv2_sp2_dma_cb_pic_start_ad (0x000015a8)*/
  15125. /*! Slice: sp2_dma_cb_pic_start_ad:*/
  15126. #define SP2_DMA_CB_PIC_START_AD
  15127. #define SP2_DMA_CB_PIC_START_AD_MASK 0xFFFFFFF0U
  15128. #define SP2_DMA_CB_PIC_START_AD_SHIFT 4U
  15129. /*! Register: miv2_sp2_dma_cr_pic_start_ad (0x000015ac)*/
  15130. /*! Slice: sp2_dma_cr_pic_start_ad:*/
  15131. #define SP2_DMA_CR_PIC_START_AD
  15132. #define SP2_DMA_CR_PIC_START_AD_MASK 0xFFFFFFF0U
  15133. #define SP2_DMA_CR_PIC_START_AD_SHIFT 4U
  15134. /*! Register: miv2_sp2_dma_y_pic_start_ad_shd (0x000015b0)*/
  15135. /*! Slice: sp2_dma_y_pic_start_ad:*/
  15136. #define SP2_DMA_Y_PIC_START_AD
  15137. #define SP2_DMA_Y_PIC_START_AD_MASK 0xFFFFFFF0U
  15138. #define SP2_DMA_Y_PIC_START_AD_SHIFT 4U
  15139. /*! Register: miv2_sp2_dma_cb_pic_start_ad_shd (0x000015b4)*/
  15140. /*! Slice: sp2_dma_cb_pic_start_ad:*/
  15141. #define SP2_DMA_CB_PIC_START_AD
  15142. #define SP2_DMA_CB_PIC_START_AD_MASK 0xFFFFFFF0U
  15143. #define SP2_DMA_CB_PIC_START_AD_SHIFT 4U
  15144. /*! Register: miv2_sp2_dma_cr_pic_start_ad_shd (0x000015b8)*/
  15145. /*! Slice: sp2_dma_cr_pic_start_ad:*/
  15146. #define SP2_DMA_CR_PIC_START_AD
  15147. #define SP2_DMA_CR_PIC_START_AD_MASK 0xFFFFFFF0U
  15148. #define SP2_DMA_CR_PIC_START_AD_SHIFT 4U
  15149. /*! Register: miv2_sp2_dma_raw_pic_start_ad (0x000015bc)*/
  15150. /*! Slice: sp2_dma_raw_pic_start_ad:*/
  15151. #define SP2_DMA_RAW_PIC_START_AD
  15152. #define SP2_DMA_RAW_PIC_START_AD_MASK 0xFFFFFFF0U
  15153. #define SP2_DMA_RAW_PIC_START_AD_SHIFT 4U
  15154. /*! Register: miv2_sp2_dma_raw_pic_width (0x000015c0)*/
  15155. /*! Slice: sp2_dma_raw_pic_width:*/
  15156. #define SP2_DMA_RAW_PIC_WIDTH
  15157. #define SP2_DMA_RAW_PIC_WIDTH_MASK 0x00007FFFU
  15158. #define SP2_DMA_RAW_PIC_WIDTH_SHIFT 0U
  15159. /*! Register: miv2_sp2_dma_raw_pic_llength (0x000015c4)*/
  15160. /*! Slice: sp2_dma_raw_pic_llength:*/
  15161. #define SP2_DMA_RAW_PIC_LLENGTH
  15162. #define SP2_DMA_RAW_PIC_LLENGTH_MASK 0x00007FFFU
  15163. #define SP2_DMA_RAW_PIC_LLENGTH_SHIFT 0U
  15164. /*! Register: miv2_sp2_dma_raw_pic_size (0x000015c8)*/
  15165. /*! Slice: sp2_dma_raw_pic_size:*/
  15166. #define SP2_DMA_RAW_PIC_SIZE
  15167. #define SP2_DMA_RAW_PIC_SIZE_MASK 0x0FFFFFFFU
  15168. #define SP2_DMA_RAW_PIC_SIZE_SHIFT 0U
  15169. /*! Register: miv2_sp2_dma_raw_pic_start_ad_shd (0x000015cc)*/
  15170. /*! Slice: sp2_dma_raw_pic_start_ad:*/
  15171. #define SP2_DMA_RAW_PIC_START_AD
  15172. #define SP2_DMA_RAW_PIC_START_AD_MASK 0xFFFFFFF0U
  15173. #define SP2_DMA_RAW_PIC_START_AD_SHIFT 4U
  15174. /*! Register: miv2_sp2_status_clr (0x000015d0)*/
  15175. /*! Slice: sp2_jdp_fifo_full:*/
  15176. #define SP2_JDP_FIFO_FULL
  15177. #define SP2_JDP_FIFO_FULL_MASK 0x00000010U
  15178. #define SP2_JDP_FIFO_FULL_SHIFT 4U
  15179. /*! Slice: sp2_raw_fifo_full:*/
  15180. #define SP2_RAW_FIFO_FULL
  15181. #define SP2_RAW_FIFO_FULL_MASK 0x00000008U
  15182. #define SP2_RAW_FIFO_FULL_SHIFT 3U
  15183. /*! Slice: sp2_cr_fifo_full:*/
  15184. #define SP2_CR_FIFO_FULL
  15185. #define SP2_CR_FIFO_FULL_MASK 0x00000004U
  15186. #define SP2_CR_FIFO_FULL_SHIFT 2U
  15187. /*! Slice: sp2_cb_fifo_full:*/
  15188. #define SP2_CB_FIFO_FULL
  15189. #define SP2_CB_FIFO_FULL_MASK 0x00000002U
  15190. #define SP2_CB_FIFO_FULL_SHIFT 1U
  15191. /*! Slice: sp2_y_fifo_full:*/
  15192. #define SP2_Y_FIFO_FULL
  15193. #define SP2_Y_FIFO_FULL_MASK 0x00000001U
  15194. #define SP2_Y_FIFO_FULL_SHIFT 0U
  15195. /*! Register: miv2_sp2_ctrl_status (0x000015d4)*/
  15196. /*! Slice: sp2_jdp_fifo_full:*/
  15197. #define SP2_JDP_FIFO_FULL
  15198. #define SP2_JDP_FIFO_FULL_MASK 0x00000010U
  15199. #define SP2_JDP_FIFO_FULL_SHIFT 4U
  15200. /*! Slice: sp2_raw_fifo_full:*/
  15201. #define SP2_RAW_FIFO_FULL
  15202. #define SP2_RAW_FIFO_FULL_MASK 0x00000008U
  15203. #define SP2_RAW_FIFO_FULL_SHIFT 3U
  15204. /*! Slice: sp2_cr_fifo_full:*/
  15205. #define SP2_CR_FIFO_FULL
  15206. #define SP2_CR_FIFO_FULL_MASK 0x00000004U
  15207. #define SP2_CR_FIFO_FULL_SHIFT 2U
  15208. /*! Slice: sp2_cb_fifo_full:*/
  15209. #define SP2_CB_FIFO_FULL
  15210. #define SP2_CB_FIFO_FULL_MASK 0x00000002U
  15211. #define SP2_CB_FIFO_FULL_SHIFT 1U
  15212. /*! Slice: sp2_y_fifo_full:*/
  15213. #define SP2_Y_FIFO_FULL
  15214. #define SP2_Y_FIFO_FULL_MASK 0x00000001U
  15215. #define SP2_Y_FIFO_FULL_SHIFT 0U
  15216. /*! Register: miv2_sp2_axi_status (0x000015d8)*/
  15217. /*! Slice: agsw_enc_pic_rdy:*/
  15218. #define AGSW_ENC_PIC_RDY
  15219. #define AGSW_ENC_PIC_RDY_MASK 0x00000002U
  15220. #define AGSW_ENC_PIC_RDY_SHIFT 1U
  15221. /*! Slice: agsw_enc_buf_full:*/
  15222. #define AGSW_ENC_BUF_FULL
  15223. #define AGSW_ENC_BUF_FULL_MASK 0x00000001U
  15224. #define AGSW_ENC_BUF_FULL_SHIFT 0U
  15225. /*! Register: miv2_sp2_dma_yuv_status (0x000015dc)*/
  15226. /*! Slice: sp2_dma_yuv_active:*/
  15227. #define SP2_DMA_YUV_ACTIVE
  15228. #define SP2_DMA_YUV_ACTIVE_MASK 0x00000001U
  15229. #define SP2_DMA_YUV_ACTIVE_SHIFT 0U
  15230. /*! Register: miv2_sp2_dma_raw_status (0x000015e0)*/
  15231. /*! Slice: sp2_dma_raw_active:*/
  15232. #define SP2_DMA_RAW_ACTIVE
  15233. #define SP2_DMA_RAW_ACTIVE_MASK 0x00000001U
  15234. #define SP2_DMA_RAW_ACTIVE_SHIFT 0U
  15235. /*! Register: miv2_mcm_ctrl (0x00001600)*/
  15236. /*! Slice: mcm_init_offset_en:*/
  15237. #define MCM_RD_CFG_UPD
  15238. #define MCM_RD_CFG_UPD_MASK 0x00000040U
  15239. #define MCM_RD_CFG_UPD_SHIFT 6U
  15240. /*! Slice: mcm_init_offset_en:*/
  15241. #define MCM_RD_AUTO_UPDATE
  15242. #define MCM_RD_AUTO_UPDATE_MASK 0x00000020U
  15243. #define MCM_RD_AUTO_UPDATE_SHIFT 5U
  15244. #define MCM_INIT_OFFSET_EN
  15245. #define MCM_INIT_OFFSET_EN_MASK 0x00000010U
  15246. #define MCM_INIT_OFFSET_EN_SHIFT 4U
  15247. /*! Slice: mcm_init_base_en:*/
  15248. #define MCM_INIT_BASE_EN
  15249. #define MCM_INIT_BASE_EN_MASK 0x00000008U
  15250. #define MCM_INIT_BASE_EN_SHIFT 3U
  15251. /*! Slice: mcm_miv2_cfg_upd:*/
  15252. #define MCM_WR_CFG_UPD
  15253. #define MCM_WR_CFG_UPD_MASK 0x00000004U
  15254. #define MCM_WR_CFG_UPD_SHIFT 2U
  15255. /*! Slice: mcm_miv2_skip:*/
  15256. #define MCM_MI_SKIP
  15257. #define MCM_MI_SKIP_MASK 0x00000002U
  15258. #define MCM_MI_SKIP_SHIFT 1U
  15259. /*! Slice: mcm_auto_update:*/
  15260. #define MCM_WR_AUTO_UPDATE
  15261. #define MCM_WR_AUTO_UPDATE_MASK 0x00000001U
  15262. #define MCM_WR_AUTO_UPDATE_SHIFT 0U
  15263. /*! Register: miv2_mcm_fmt (0x00001604)*/
  15264. /*! Slice: mcm_wr1_fmt_aligned:*/
  15265. #define MCM_WR1_FMT_ALIGNED
  15266. #define MCM_WR1_FMT_ALIGNED_MASK 0x00030000U
  15267. #define MCM_WR1_FMT_ALIGNED_SHIFT 16U
  15268. /*! Slice: mcm_wr0_fmt_aligned:*/
  15269. #define MCM_WR0_FMT_ALIGNED
  15270. #define MCM_WR0_FMT_ALIGNED_MASK 0x0000C000U
  15271. #define MCM_WR0_FMT_ALIGNED_SHIFT 14U
  15272. /*! Slice: mcm_rd_fmt_aligned:*/
  15273. #define MCM_RD_FMT_ALIGNED
  15274. #define MCM_RD_FMT_ALIGNED_MASK 0x00003000U
  15275. #define MCM_RD_FMT_ALIGNED_SHIFT 12U
  15276. /*! Slice: mcm_wr1_raw_bit:*/
  15277. #define MCM_WR1_RAW_BIT
  15278. #define MCM_WR1_RAW_BIT_MASK 0x00000F00U
  15279. #define MCM_WR1_RAW_BIT_SHIFT 8U
  15280. /*! Slice: mcm_wr0_raw_bit:*/
  15281. #define MCM_WR0_RAW_BIT
  15282. #define MCM_WR0_RAW_BIT_MASK 0x000000F0U
  15283. #define MCM_WR0_RAW_BIT_SHIFT 4U
  15284. /*! Slice: mcm_rd_raw_bit:*/
  15285. #define MCM_RD_RAW_BIT
  15286. #define MCM_RD_RAW_BIT_MASK 0x0000000FU
  15287. #define MCM_RD_RAW_BIT_SHIFT 0U
  15288. /*! Register: miv2_mcm_bus_cfg (0x00001608)*/
  15289. /*! Slice: mcm_rd_swap_raw:*/
  15290. #define MCM_RD_SWAP_RAW
  15291. #define MCM_RD_SWAP_RAW_MASK 0x000F0000U
  15292. #define MCM_RD_SWAP_RAW_SHIFT 16U
  15293. /*! Slice: mcm_wr0_swap_raw:*/
  15294. #define MCM_WR0_SWAP_RAW
  15295. #define MCM_WR0_SWAP_RAW_MASK 0x0000F000U
  15296. #define MCM_WR0_SWAP_RAW_SHIFT 12U
  15297. /*! Slice: mcm_wr1_swap_raw:*/
  15298. #define MCM_WR1_SWAP_RAW
  15299. #define MCM_WR1_SWAP_RAW_MASK 0x00000F00U
  15300. #define MCM_WR1_SWAP_RAW_SHIFT 8U
  15301. /*! Slice: mcm_rd_issue_cap:*/
  15302. #define MCM_RD_ISSUE_CAP
  15303. #define MCM_RD_ISSUE_CAP_MASK 0x000000C0U
  15304. #define MCM_RD_ISSUE_CAP_SHIFT 6U
  15305. /*! Slice: mcm_wr_issue_cap:*/
  15306. #define MCM_WR_ISSUE_CAP
  15307. #define MCM_WR_ISSUE_CAP_MASK 0x00000030U
  15308. #define MCM_WR_ISSUE_CAP_SHIFT 4U
  15309. /*! Slice: mcm_rd_burst_len:*/
  15310. #define MCM_RD_BURST_LEN
  15311. #define MCM_RD_BURST_LEN_MASK 0x0000000CU
  15312. #define MCM_RD_BURST_LEN_SHIFT 2U
  15313. /*! Slice: mcm_wr_burst_len:*/
  15314. #define MCM_WR_BURST_LEN
  15315. #define MCM_WR_BURST_LEN_MASK 0x00000003U
  15316. #define MCM_WR_BURST_LEN_SHIFT 0U
  15317. /*! Register: miv2_mcm_bus_id (0x0000160c)*/
  15318. /*! Slice: mcm_bus_sw_en:*/
  15319. #define MCM_BUS_SW_EN
  15320. #define MCM_BUS_SW_EN_MASK 0x08000000U
  15321. #define MCM_BUS_SW_EN_SHIFT 27U
  15322. /*! Slice: mcm_rd_id_en:*/
  15323. #define MCM_RD_ID_EN
  15324. #define MCM_RD_ID_EN_MASK 0x04000000U
  15325. #define MCM_RD_ID_EN_SHIFT 26U
  15326. /*! Slice: mcm_rd_id_cfg:*/
  15327. #define MCM_RD_ID_CFG
  15328. #define MCM_RD_ID_CFG_MASK 0x03FC0000U
  15329. #define MCM_RD_ID_CFG_SHIFT 18U
  15330. /*! Slice: mcm_wr0_id_en:*/
  15331. #define MCM_WR0_ID_EN
  15332. #define MCM_WR0_ID_EN_MASK 0x00020000U
  15333. #define MCM_WR0_ID_EN_SHIFT 17U
  15334. /*! Slice: mcm_wr0_id_cfg:*/
  15335. #define MCM_WR0_ID_CFG
  15336. #define MCM_WR0_ID_CFG_MASK 0x0001FE00U
  15337. #define MCM_WR0_ID_CFG_SHIFT 9U
  15338. /*! Slice: mcm_wr1_id_en:*/
  15339. #define MCM_WR1_ID_EN
  15340. #define MCM_WR1_ID_EN_MASK 0x00000100U
  15341. #define MCM_WR1_ID_EN_SHIFT 8U
  15342. /*! Slice: mcm_wr1_id_cfg:*/
  15343. #define MCM_WR1_ID_CFG
  15344. #define MCM_WR1_ID_CFG_MASK 0x000000FFU
  15345. #define MCM_WR1_ID_CFG_SHIFT 0U
  15346. /*! Register: miv2_mcm_bus_timeo (0x00001610)*/
  15347. /*! Slice: mcm_bus_timeo_en:*/
  15348. #define MCM_BUS_TIMEO_EN
  15349. #define MCM_BUS_TIMEO_EN_MASK 0x80000000U
  15350. #define MCM_BUS_TIMEO_EN_SHIFT 31U
  15351. /*! Slice: mcm_bus_timeo:*/
  15352. #define MCM_BUS_TIMEO
  15353. #define MCM_BUS_TIMEO_MASK 0x7FFFFFFFU
  15354. #define MCM_BUS_TIMEO_SHIFT 0U
  15355. /*! Register: miv2_mcm_raw0_base_ad_init (0x00001614)*/
  15356. /*! Slice: mcm_raw0_base_ad_init:*/
  15357. #define MCM_RAW0_BASE_AD_INIT
  15358. #define MCM_RAW0_BASE_AD_INIT_MASK 0xFFFFFFF0U
  15359. #define MCM_RAW0_BASE_AD_INIT_SHIFT 4U
  15360. /*! Register: miv2_mcm_raw0_size_init (0x00001618)*/
  15361. /*! Slice: mcm_raw0_size_init:*/
  15362. #define MCM_RAW0_SIZE_INIT
  15363. #define MCM_RAW0_SIZE_INIT_MASK 0x1FFFFFF0U
  15364. #define MCM_RAW0_SIZE_INIT_SHIFT 4U
  15365. /*! Register: miv2_mcm_raw0_offs_cnt_init (0x0000161c)*/
  15366. /*! Slice: mcm_raw0_offs_cnt_init:*/
  15367. #define MCM_RAW0_OFFS_CNT_INIT
  15368. #define MCM_RAW0_OFFS_CNT_INIT_MASK 0x1FFFFFF0U
  15369. #define MCM_RAW0_OFFS_CNT_INIT_SHIFT 4U
  15370. /*! Register: miv2_mcm_raw0_llength (0x00001620)*/
  15371. /*! Slice: mcm_raw0_llengh:*/
  15372. #define MCM_RAW0_LLENGH
  15373. #define MCM_RAW0_LLENGH_MASK 0x00007FFFU
  15374. #define MCM_RAW0_LLENGH_SHIFT 0U
  15375. /*! Register: miv2_mcm_raw0_pic_width (0x00001624)*/
  15376. /*! Slice: mcm_raw0_pic_width:*/
  15377. #define MCM_RAW0_PIC_WIDTH
  15378. #define MCM_RAW0_PIC_WIDTH_MASK 0xFFFFFFFFU
  15379. #define MCM_RAW0_PIC_WIDTH_SHIFT 0U
  15380. /*! Register: miv2_mcm_raw0_pic_height (0x00001628)*/
  15381. /*! Slice: mcm_raw0_pic_height:*/
  15382. #define MCM_RAW0_PIC_HEIGHT
  15383. #define MCM_RAW0_PIC_HEIGHT_MASK 0xFFFFFFFFU
  15384. #define MCM_RAW0_PIC_HEIGHT_SHIFT 0U
  15385. /*! Register: miv2_mcm_raw0_pic_size (0x0000162c)*/
  15386. /*! Slice: mcm_raw0_pic_size:*/
  15387. #define MCM_RAW0_PIC_SIZE
  15388. #define MCM_RAW0_PIC_SIZE_MASK 0xFFFFFFFFU
  15389. #define MCM_RAW0_PIC_SIZE_SHIFT 0U
  15390. /*! Register: miv2_mcm_raw0_offs_cnt_start (0x00001630)*/
  15391. /*! Slice: mcm_raw0_offs_cnt_start:*/
  15392. #define MCM_RAW0_OFFS_CNT_START
  15393. #define MCM_RAW0_OFFS_CNT_START_MASK 0x1FFFFFF0U
  15394. #define MCM_RAW0_OFFS_CNT_START_SHIFT 4U
  15395. /*! Register: miv2_mcm_raw0_base_ad_shd (0x00001634)*/
  15396. /*! Slice: mcm_raw0_base_ad:*/
  15397. #define MCM_RAW0_BASE_AD
  15398. #define MCM_RAW0_BASE_AD_MASK 0xFFFFFFF0U
  15399. #define MCM_RAW0_BASE_AD_SHIFT 4U
  15400. /*! Register: miv2_mcm_raw0_size_shd (0x00001638)*/
  15401. /*! Slice: mcm_raw0_size:*/
  15402. #define MCM_RAW0_SIZE
  15403. #define MCM_RAW0_SIZE_MASK 0x1FFFFFF0U
  15404. #define MCM_RAW0_SIZE_SHIFT 4U
  15405. /*! Register: miv2_mcm_raw0_offs_cnt_shd (0x0000163c)*/
  15406. /*! Slice: mcm_raw0_offs_cnt:*/
  15407. #define MCM_RAW0_OFFS_CNT
  15408. #define MCM_RAW0_OFFS_CNT_MASK 0x1FFFFFF0U
  15409. #define MCM_RAW0_OFFS_CNT_SHIFT 4U
  15410. /*! Register: miv2_mcm_raw1_base_ad_init (0x00001640)*/
  15411. /*! Slice: mcm_raw1_base_ad_init:*/
  15412. #define MCM_RAW1_BASE_AD_INIT
  15413. #define MCM_RAW1_BASE_AD_INIT_MASK 0xFFFFFFF0U
  15414. #define MCM_RAW1_BASE_AD_INIT_SHIFT 4U
  15415. /*! Register: miv2_mcm_raw1_size_init (0x00001644)*/
  15416. /*! Slice: mcm_raw1_size_init:*/
  15417. #define MCM_RAW1_SIZE_INIT
  15418. #define MCM_RAW1_SIZE_INIT_MASK 0x1FFFFFF0U
  15419. #define MCM_RAW1_SIZE_INIT_SHIFT 4U
  15420. /*! Register: miv2_mcm_raw1_offs_cnt_init (0x00001648)*/
  15421. /*! Slice: mcm_raw1_offs_cnt_init:*/
  15422. #define MCM_RAW1_OFFS_CNT_INIT
  15423. #define MCM_RAW1_OFFS_CNT_INIT_MASK 0x1FFFFFF0U
  15424. #define MCM_RAW1_OFFS_CNT_INIT_SHIFT 4U
  15425. /*! Register: miv2_mcm_raw1_llength (0x0000164c)*/
  15426. /*! Slice: mcm_raw1_llengh:*/
  15427. #define MCM_RAW1_LLENGH
  15428. #define MCM_RAW1_LLENGH_MASK 0x00007FFFU
  15429. #define MCM_RAW1_LLENGH_SHIFT 0U
  15430. /*! Register: miv2_mcm_raw1_pic_width (0x00001650)*/
  15431. /*! Slice: mcm_raw1_pic_width:*/
  15432. #define MCM_RAW1_PIC_WIDTH
  15433. #define MCM_RAW1_PIC_WIDTH_MASK 0xFFFFFFFFU
  15434. #define MCM_RAW1_PIC_WIDTH_SHIFT 0U
  15435. /*! Register: miv2_mcm_raw1_pic_height (0x00001654)*/
  15436. /*! Slice: mcm_raw1_pic_height:*/
  15437. #define MCM_RAW1_PIC_HEIGHT
  15438. #define MCM_RAW1_PIC_HEIGHT_MASK 0xFFFFFFFFU
  15439. #define MCM_RAW1_PIC_HEIGHT_SHIFT 0U
  15440. /*! Register: miv2_mcm_raw1_pic_size (0x00001658)*/
  15441. /*! Slice: mcm_raw1_pic_size:*/
  15442. #define MCM_RAW1_PIC_SIZE
  15443. #define MCM_RAW1_PIC_SIZE_MASK 0xFFFFFFFFU
  15444. #define MCM_RAW1_PIC_SIZE_SHIFT 0U
  15445. /*! Register: miv2_mcm_raw1_offs_cnt_start (0x0000165c)*/
  15446. /*! Slice: mcm_raw1_offs_cnt_start:*/
  15447. #define MCM_RAW1_OFFS_CNT_START
  15448. #define MCM_RAW1_OFFS_CNT_START_MASK 0x1FFFFFF0U
  15449. #define MCM_RAW1_OFFS_CNT_START_SHIFT 4U
  15450. /*! Register: miv2_mcm_raw1_base_ad_shd (0x00001660)*/
  15451. /*! Slice: mcm_raw1_base_ad:*/
  15452. #define MCM_RAW1_BASE_AD
  15453. #define MCM_RAW1_BASE_AD_MASK 0xFFFFFFF0U
  15454. #define MCM_RAW1_BASE_AD_SHIFT 4U
  15455. /*! Register: miv2_mcm_raw1_size_shd (0x00001664)*/
  15456. /*! Slice: mcm_raw1_size:*/
  15457. #define MCM_RAW1_SIZE
  15458. #define MCM_RAW1_SIZE_MASK 0x1FFFFFF0U
  15459. #define MCM_RAW1_SIZE_SHIFT 4U
  15460. /*! Register: miv2_mcm_raw1_offs_cnt_shd (0x00001668)*/
  15461. /*! Slice: mcm_raw1_offs_cnt:*/
  15462. #define MCM_RAW1_OFFS_CNT
  15463. #define MCM_RAW1_OFFS_CNT_MASK 0x1FFFFFF0U
  15464. #define MCM_RAW1_OFFS_CNT_SHIFT 4U
  15465. /*! Register: miv2_mcm_dma_raw_pic_start_ad (0x0000166c)*/
  15466. /*! Slice: mcm_dma_raw_pic_start_ad:*/
  15467. #define MCM_DMA_RAW_PIC_START_AD
  15468. #define MCM_DMA_RAW_PIC_START_AD_MASK 0xFFFFFFF0U
  15469. #define MCM_DMA_RAW_PIC_START_AD_SHIFT 4U
  15470. /*! Register: miv2_mcm_dma_raw_pic_width (0x00001670)*/
  15471. /*! Slice: mcm_dma_raw_pic_width:*/
  15472. #define MCM_DMA_RAW_PIC_WIDTH
  15473. #define MCM_DMA_RAW_PIC_WIDTH_MASK 0x00007FFFU
  15474. #define MCM_DMA_RAW_PIC_WIDTH_SHIFT 0U
  15475. /*! Register: miv2_mcm_dma_raw_pic_llength (0x00001674)*/
  15476. /*! Slice: mcm_dma_raw_pic_llength:*/
  15477. #define MCM_DMA_RAW_PIC_LLENGTH
  15478. #define MCM_DMA_RAW_PIC_LLENGTH_MASK 0x00007FFFU
  15479. #define MCM_DMA_RAW_PIC_LLENGTH_SHIFT 0U
  15480. /*! Register: miv2_mcm_dma_raw_pic_size (0x00001678)*/
  15481. /*! Slice: mcm_dma_raw_pic_size:*/
  15482. #define MCM_DMA_RAW_PIC_SIZE
  15483. #define MCM_DMA_RAW_PIC_SIZE_MASK 0x0FFFFFFFU
  15484. #define MCM_DMA_RAW_PIC_SIZE_SHIFT 0U
  15485. /*! Register: miv2_mcm_dma_raw_pic_start_ad_shd (0x0000167c)*/
  15486. /*! Slice: mcm_dma_raw_pic_start_ad:*/
  15487. #define MCM_DMA_RAW_PIC_START_AD
  15488. #define MCM_DMA_RAW_PIC_START_AD_MASK 0xFFFFFFF0U
  15489. #define MCM_DMA_RAW_PIC_START_AD_SHIFT 4U
  15490. /*! Register: miv2_mcm_status_clr (0x00001680)*/
  15491. /*! Slice: mcm_raw1_fifo_full:*/
  15492. #define MCM_RAW1_FIFO_FULL
  15493. #define MCM_RAW1_FIFO_FULL_MASK 0x00000002U
  15494. #define MCM_RAW1_FIFO_FULL_SHIFT 1U
  15495. /*! Slice: mcm_raw0_fifo_full:*/
  15496. #define MCM_RAW0_FIFO_FULL
  15497. #define MCM_RAW0_FIFO_FULL_MASK 0x00000001U
  15498. #define MCM_RAW0_FIFO_FULL_SHIFT 0U
  15499. /*! Register: miv2_mcm_ctrl_status (0x00001684)*/
  15500. /*! Slice: mcm_raw1_fifo_full:*/
  15501. #define MCM_RAW1_FIFO_FULL
  15502. #define MCM_RAW1_FIFO_FULL_MASK 0x00000002U
  15503. #define MCM_RAW1_FIFO_FULL_SHIFT 1U
  15504. /*! Slice: mcm_raw0_fifo_full:*/
  15505. #define MCM_RAW0_FIFO_FULL
  15506. #define MCM_RAW0_FIFO_FULL_MASK 0x00000001U
  15507. #define MCM_RAW0_FIFO_FULL_SHIFT 0U
  15508. /*! Register: miv2_mcm_axi_status (0x00001688)*/
  15509. /*! Slice: agsw_enc_pic_rdy:*/
  15510. #define AGSW_ENC_PIC_RDY
  15511. #define AGSW_ENC_PIC_RDY_MASK 0x00000002U
  15512. #define AGSW_ENC_PIC_RDY_SHIFT 1U
  15513. /*! Slice: agsw_enc_buf_full:*/
  15514. #define AGSW_ENC_BUF_FULL
  15515. #define AGSW_ENC_BUF_FULL_MASK 0x00000001U
  15516. #define AGSW_ENC_BUF_FULL_SHIFT 0U
  15517. /*! Register: miv2_mcm_dma_status (0x0000168c)*/
  15518. /*! Slice: mcm_dma_active:*/
  15519. #define MCM_DMA_ACTIVE
  15520. #define MCM_DMA_ACTIVE_MASK 0x00000001U
  15521. #define MCM_DMA_ACTIVE_SHIFT 0U
  15522. /*! Register: miv2_imsc (0x000016c0)*/
  15523. /*! Slice: fill_mp_y:*/
  15524. #define FILL_MP_Y
  15525. #define FILL_MP_Y_MASK 0x08000000U
  15526. #define FILL_MP_Y_SHIFT 27U
  15527. /*! Slice: mblk_line:*/
  15528. #define MBLK_LINE
  15529. #define MBLK_LINE_MASK 0x04000000U
  15530. #define MBLK_LINE_SHIFT 26U
  15531. /*! Slice: mp_handshk_int:*/
  15532. #define MP_HANDSHK_INT
  15533. #define MP_HANDSHK_INT_MASK 0x02000000U
  15534. #define MP_HANDSHK_INT_SHIFT 25U
  15535. /*! Slice: mcm_dma_raw_ready:*/
  15536. #define MCM_DMA_RAW_READY
  15537. #define MCM_DMA_RAW_READY_MASK 0x01000000U
  15538. #define MCM_DMA_RAW_READY_SHIFT 24U
  15539. /*! Slice: sp2_dma_raw_ready:*/
  15540. #define SP2_DMA_RAW_READY
  15541. #define SP2_DMA_RAW_READY_MASK 0x00800000U
  15542. #define SP2_DMA_RAW_READY_SHIFT 23U
  15543. /*! Slice: sp2_dma_ycbcr_ready:*/
  15544. #define SP2_DMA_YCBCR_READY
  15545. #define SP2_DMA_YCBCR_READY_MASK 0x00400000U
  15546. #define SP2_DMA_YCBCR_READY_SHIFT 22U
  15547. /*! Slice: wrap_mcm_raw1:*/
  15548. #define WRAP_MCM_RAW1
  15549. #define WRAP_MCM_RAW1_MASK 0x00200000U
  15550. #define WRAP_MCM_RAW1_SHIFT 21U
  15551. /*! Slice: wrap_mcm_raw0:*/
  15552. #define WRAP_MCM_RAW0
  15553. #define WRAP_MCM_RAW0_MASK 0x00100000U
  15554. #define WRAP_MCM_RAW0_SHIFT 20U
  15555. /*! Slice: wrap_sp2_cr:*/
  15556. #define WRAP_SP2_CR
  15557. #define WRAP_SP2_CR_MASK 0x00040000U
  15558. #define WRAP_SP2_CR_SHIFT 18U
  15559. /*! Slice: wrap_sp2_cb:*/
  15560. #define WRAP_SP2_CB
  15561. #define WRAP_SP2_CB_MASK 0x00020000U
  15562. #define WRAP_SP2_CB_SHIFT 17U
  15563. /*! Slice: wrap_sp2_y:*/
  15564. #define WRAP_SP2_Y
  15565. #define WRAP_SP2_Y_MASK 0x00010000U
  15566. #define WRAP_SP2_Y_SHIFT 16U
  15567. /*! Slice: wrap_sp1_cr:*/
  15568. #define WRAP_SP1_CR
  15569. #define WRAP_SP1_CR_MASK 0x00008000U
  15570. #define WRAP_SP1_CR_SHIFT 15U
  15571. /*! Slice: wrap_sp1_cb:*/
  15572. #define WRAP_SP1_CB
  15573. #define WRAP_SP1_CB_MASK 0x00004000U
  15574. #define WRAP_SP1_CB_SHIFT 14U
  15575. /*! Slice: wrap_sp1_y:*/
  15576. #define WRAP_SP1_Y
  15577. #define WRAP_SP1_Y_MASK 0x00002000U
  15578. #define WRAP_SP1_Y_SHIFT 13U
  15579. /*! Slice: wrap_mp_jdp:*/
  15580. #define WRAP_MP_JDP
  15581. #define WRAP_MP_JDP_MASK 0x00001000U
  15582. #define WRAP_MP_JDP_SHIFT 12U
  15583. /*! Slice: wrap_mp_raw:*/
  15584. #define WRAP_MP_RAW
  15585. #define WRAP_MP_RAW_MASK 0x00000800U
  15586. #define WRAP_MP_RAW_SHIFT 11U
  15587. /*! Slice: wrap_mp_cr:*/
  15588. #define WRAP_MP_CR
  15589. #define WRAP_MP_CR_MASK 0x00000400U
  15590. #define WRAP_MP_CR_SHIFT 10U
  15591. /*! Slice: wrap_mp_cb:*/
  15592. #define WRAP_MP_CB
  15593. #define WRAP_MP_CB_MASK 0x00000200U
  15594. #define WRAP_MP_CB_SHIFT 9U
  15595. /*! Slice: wrap_mp_y:*/
  15596. #define WRAP_MP_Y
  15597. #define WRAP_MP_Y_MASK 0x00000100U
  15598. #define WRAP_MP_Y_SHIFT 8U
  15599. /*! Slice: mcm_raw1_frame_end:*/
  15600. #define MCM_RAW1_FRAME_END
  15601. #define MCM_RAW1_FRAME_END_MASK 0x00000080U
  15602. #define MCM_RAW1_FRAME_END_SHIFT 7U
  15603. /*! Slice: mcm_raw0_frame_end:*/
  15604. #define MCM_RAW0_FRAME_END
  15605. #define MCM_RAW0_FRAME_END_MASK 0x00000040U
  15606. #define MCM_RAW0_FRAME_END_SHIFT 6U
  15607. /*! Slice: sp2_raw_frame_end:*/
  15608. #define SP2_RAW_FRAME_END
  15609. #define SP2_RAW_FRAME_END_MASK 0x00000020U
  15610. #define SP2_RAW_FRAME_END_SHIFT 5U
  15611. /*! Slice: sp2_ycbcr_frame_end:*/
  15612. #define SP2_YCBCR_FRAME_END
  15613. #define SP2_YCBCR_FRAME_END_MASK 0x00000010U
  15614. #define SP2_YCBCR_FRAME_END_SHIFT 4U
  15615. /*! Slice: sp1_ycbcr_frame_end:*/
  15616. #define SP1_YCBCR_FRAME_END
  15617. #define SP1_YCBCR_FRAME_END_MASK 0x00000008U
  15618. #define SP1_YCBCR_FRAME_END_SHIFT 3U
  15619. /*! Slice: mp_jdp_frame_end:*/
  15620. #define MP_JDP_FRAME_END
  15621. #define MP_JDP_FRAME_END_MASK 0x00000004U
  15622. #define MP_JDP_FRAME_END_SHIFT 2U
  15623. /*! Slice: mp_raw_frame_end:*/
  15624. #define MP_RAW_FRAME_END
  15625. #define MP_RAW_FRAME_END_MASK 0x00000002U
  15626. #define MP_RAW_FRAME_END_SHIFT 1U
  15627. /*! Slice: mp_ycbcr_frame_end:*/
  15628. #define MP_YCBCR_FRAME_END
  15629. #define MP_YCBCR_FRAME_END_MASK 0x00000001U
  15630. #define MP_YCBCR_FRAME_END_SHIFT 0U
  15631. /*! Register: miv2_imsc1 (0x000016c4)*/
  15632. /*! Slice: miv2_mcm_bus_buserr:*/
  15633. #define MI_MCM_BUS_BUSERR
  15634. #define MI_MCM_BUS_BUSERR_MASK 0x00000080U
  15635. #define MI_MCM_BUS_BUSERR_SHIFT 7U
  15636. /*! Slice: miv2_mcm_bus_timeo:*/
  15637. #define MI_MCM_BUS_TIMEO
  15638. #define MI_MCM_BUS_TIMEO_MASK 0x00000040U
  15639. #define MI_MCM_BUS_TIMEO_SHIFT 6U
  15640. /*! Slice: miv2_sp2_bus_buserr:*/
  15641. #define MI_SP2_BUS_BUSERR
  15642. #define MI_SP2_BUS_BUSERR_MASK 0x00000020U
  15643. #define MI_SP2_BUS_BUSERR_SHIFT 5U
  15644. /*! Slice: miv2_sp2_bus_timeo:*/
  15645. #define MI_SP2_BUS_TIMEO
  15646. #define MI_SP2_BUS_TIMEO_MASK 0x00000010U
  15647. #define MI_SP2_BUS_TIMEO_SHIFT 4U
  15648. /*! Slice: miv2_sp1_bus_buserr:*/
  15649. #define MI_SP1_BUS_BUSERR
  15650. #define MI_SP1_BUS_BUSERR_MASK 0x00000008U
  15651. #define MI_SP1_BUS_BUSERR_SHIFT 3U
  15652. /*! Slice: miv2_sp1_bus_timeo:*/
  15653. #define MI_SP1_BUS_TIMEO
  15654. #define MI_SP1_BUS_TIMEO_MASK 0x00000004U
  15655. #define MI_SP1_BUS_TIMEO_SHIFT 2U
  15656. /*! Slice: miv2_mp_bus_buserr:*/
  15657. #define MI_MP_BUS_BUSERR
  15658. #define MI_MP_BUS_BUSERR_MASK 0x00000002U
  15659. #define MI_MP_BUS_BUSERR_SHIFT 1U
  15660. /*! Slice: miv2_mp_bus_timeo:*/
  15661. #define MI_MP_BUS_TIMEO
  15662. #define MI_MP_BUS_TIMEO_MASK 0x00000001U
  15663. #define MI_MP_BUS_TIMEO_SHIFT 0U
  15664. /*! Register: miv2_isr (0x000016c8)*/
  15665. /*! Slice: fill_mp_y:*/
  15666. #define FILL_MP_Y
  15667. #define FILL_MP_Y_MASK 0x08000000U
  15668. #define FILL_MP_Y_SHIFT 27U
  15669. /*! Slice: mblk_line:*/
  15670. #define MBLK_LINE
  15671. #define MBLK_LINE_MASK 0x04000000U
  15672. #define MBLK_LINE_SHIFT 26U
  15673. /*! Slice: mp_handshk_int:*/
  15674. #define MP_HANDSHK_INT
  15675. #define MP_HANDSHK_INT_MASK 0x02000000U
  15676. #define MP_HANDSHK_INT_SHIFT 25U
  15677. /*! Slice: mcm_dma_raw_ready:*/
  15678. #define MCM_DMA_RAW_READY
  15679. #define MCM_DMA_RAW_READY_MASK 0x01000000U
  15680. #define MCM_DMA_RAW_READY_SHIFT 24U
  15681. /*! Slice: sp2_dma_raw_ready:*/
  15682. #define SP2_DMA_RAW_READY
  15683. #define SP2_DMA_RAW_READY_MASK 0x00800000U
  15684. #define SP2_DMA_RAW_READY_SHIFT 23U
  15685. /*! Slice: sp2_dma_ycbcr_ready:*/
  15686. #define SP2_DMA_YCBCR_READY
  15687. #define SP2_DMA_YCBCR_READY_MASK 0x00400000U
  15688. #define SP2_DMA_YCBCR_READY_SHIFT 22U
  15689. /*! Slice: wrap_mcm_raw1:*/
  15690. #define WRAP_MCM_RAW1
  15691. #define WRAP_MCM_RAW1_MASK 0x00200000U
  15692. #define WRAP_MCM_RAW1_SHIFT 21U
  15693. /*! Slice: wrap_mcm_raw0:*/
  15694. #define WRAP_MCM_RAW0
  15695. #define WRAP_MCM_RAW0_MASK 0x00100000U
  15696. #define WRAP_MCM_RAW0_SHIFT 20U
  15697. /*! Slice: wrap_sp2_cr:*/
  15698. #define WRAP_SP2_CR
  15699. #define WRAP_SP2_CR_MASK 0x00040000U
  15700. #define WRAP_SP2_CR_SHIFT 18U
  15701. /*! Slice: wrap_sp2_cb:*/
  15702. #define WRAP_SP2_CB
  15703. #define WRAP_SP2_CB_MASK 0x00020000U
  15704. #define WRAP_SP2_CB_SHIFT 17U
  15705. /*! Slice: wrap_sp2_y:*/
  15706. #define WRAP_SP2_Y
  15707. #define WRAP_SP2_Y_MASK 0x00010000U
  15708. #define WRAP_SP2_Y_SHIFT 16U
  15709. /*! Slice: wrap_sp1_cr:*/
  15710. #define WRAP_SP1_CR
  15711. #define WRAP_SP1_CR_MASK 0x00008000U
  15712. #define WRAP_SP1_CR_SHIFT 15U
  15713. /*! Slice: wrap_sp1_cb:*/
  15714. #define WRAP_SP1_CB
  15715. #define WRAP_SP1_CB_MASK 0x00004000U
  15716. #define WRAP_SP1_CB_SHIFT 14U
  15717. /*! Slice: wrap_sp1_y:*/
  15718. #define WRAP_SP1_Y
  15719. #define WRAP_SP1_Y_MASK 0x00002000U
  15720. #define WRAP_SP1_Y_SHIFT 13U
  15721. /*! Slice: wrap_mp_jdp:*/
  15722. #define WRAP_MP_JDP
  15723. #define WRAP_MP_JDP_MASK 0x00001000U
  15724. #define WRAP_MP_JDP_SHIFT 12U
  15725. /*! Slice: wrap_mp_raw:*/
  15726. #define WRAP_MP_RAW
  15727. #define WRAP_MP_RAW_MASK 0x00000800U
  15728. #define WRAP_MP_RAW_SHIFT 11U
  15729. /*! Slice: wrap_mp_cr:*/
  15730. #define WRAP_MP_CR
  15731. #define WRAP_MP_CR_MASK 0x00000400U
  15732. #define WRAP_MP_CR_SHIFT 10U
  15733. /*! Slice: wrap_mp_cb:*/
  15734. #define WRAP_MP_CB
  15735. #define WRAP_MP_CB_MASK 0x00000200U
  15736. #define WRAP_MP_CB_SHIFT 9U
  15737. /*! Slice: wrap_mp_y:*/
  15738. #define WRAP_MP_Y
  15739. #define WRAP_MP_Y_MASK 0x00000100U
  15740. #define WRAP_MP_Y_SHIFT 8U
  15741. /*! Slice: mcm_raw1_frame_end:*/
  15742. #define MCM_RAW1_FRAME_END
  15743. #define MCM_RAW1_FRAME_END_MASK 0x00000080U
  15744. #define MCM_RAW1_FRAME_END_SHIFT 7U
  15745. /*! Slice: mcm_raw0_frame_end:*/
  15746. #define MCM_RAW0_FRAME_END
  15747. #define MCM_RAW0_FRAME_END_MASK 0x00000040U
  15748. #define MCM_RAW0_FRAME_END_SHIFT 6U
  15749. /*! Slice: sp2_raw_frame_end:*/
  15750. #define SP2_RAW_FRAME_END
  15751. #define SP2_RAW_FRAME_END_MASK 0x00000020U
  15752. #define SP2_RAW_FRAME_END_SHIFT 5U
  15753. /*! Slice: sp2_ycbcr_frame_end:*/
  15754. #define SP2_YCBCR_FRAME_END
  15755. #define SP2_YCBCR_FRAME_END_MASK 0x00000010U
  15756. #define SP2_YCBCR_FRAME_END_SHIFT 4U
  15757. /*! Slice: sp1_ycbcr_frame_end:*/
  15758. #define SP1_YCBCR_FRAME_END
  15759. #define SP1_YCBCR_FRAME_END_MASK 0x00000008U
  15760. #define SP1_YCBCR_FRAME_END_SHIFT 3U
  15761. /*! Slice: mp_jdp_frame_end:*/
  15762. #define MP_JDP_FRAME_END
  15763. #define MP_JDP_FRAME_END_MASK 0x00000004U
  15764. #define MP_JDP_FRAME_END_SHIFT 2U
  15765. /*! Slice: mp_raw_frame_end:*/
  15766. #define MP_RAW_FRAME_END
  15767. #define MP_RAW_FRAME_END_MASK 0x00000002U
  15768. #define MP_RAW_FRAME_END_SHIFT 1U
  15769. /*! Slice: mp_ycbcr_frame_end:*/
  15770. #define MP_YCBCR_FRAME_END
  15771. #define MP_YCBCR_FRAME_END_MASK 0x00000001U
  15772. #define MP_YCBCR_FRAME_END_SHIFT 0U
  15773. /*! Register: miv2_isr1 (0x000016cc)*/
  15774. /*! Slice: miv2_mcm_bus_buserr:*/
  15775. #define MI_MCM_BUS_BUSERR
  15776. #define MI_MCM_BUS_BUSERR_MASK 0x00000080U
  15777. #define MI_MCM_BUS_BUSERR_SHIFT 7U
  15778. /*! Slice: miv2_mcm_bus_timeo:*/
  15779. #define MI_MCM_BUS_TIMEO
  15780. #define MI_MCM_BUS_TIMEO_MASK 0x00000040U
  15781. #define MI_MCM_BUS_TIMEO_SHIFT 6U
  15782. /*! Slice: miv2_sp2_bus_buserr:*/
  15783. #define MI_SP2_BUS_BUSERR
  15784. #define MI_SP2_BUS_BUSERR_MASK 0x00000020U
  15785. #define MI_SP2_BUS_BUSERR_SHIFT 5U
  15786. /*! Slice: miv2_sp2_bus_timeo:*/
  15787. #define MI_SP2_BUS_TIMEO
  15788. #define MI_SP2_BUS_TIMEO_MASK 0x00000010U
  15789. #define MI_SP2_BUS_TIMEO_SHIFT 4U
  15790. /*! Slice: miv2_sp1_bus_buserr:*/
  15791. #define MI_SP1_BUS_BUSERR
  15792. #define MI_SP1_BUS_BUSERR_MASK 0x00000008U
  15793. #define MI_SP1_BUS_BUSERR_SHIFT 3U
  15794. /*! Slice: miv2_sp1_bus_timeo:*/
  15795. #define MI_SP1_BUS_TIMEO
  15796. #define MI_SP1_BUS_TIMEO_MASK 0x00000004U
  15797. #define MI_SP1_BUS_TIMEO_SHIFT 2U
  15798. #define MRV_MI_BP_PATH_ENABLE
  15799. #define MRV_MI_BP_PATH_ENABLE_MASK 0x00000001U
  15800. #define MRV_MI_BP_PATH_ENABLE_SHIFT 0U
  15801. /*! Register: bp_ctrl: Control register */
  15802. /*! Slice: bp_output_format */
  15803. /* 000 raw8
  15804. 001 raw10
  15805. 010 raw12
  15806. */
  15807. #define MRV_MI_BP_WRITE_RAWBIT
  15808. #define MRV_MI_BP_WRITE_RAWBIT_MASK 0x0000001cU
  15809. #define MRV_MI_BP_WRITE_RAWBIT_SHIFT 2U
  15810. #define MRV_MI_BP_WRITE_FORMAT
  15811. #define MRV_MI_BP_WRITE_FORMAT_MASK 0x00000300U
  15812. #define MRV_MI_BP_WRITE_FORMAT_SHIFT 8U
  15813. #define MRV_MI_BP_WRITE_PLANAR_FORMAT 1
  15814. #define MRV_MI_BP_WRITE_INTERLEAVE_FORMAT 2
  15815. /*! Slice: miv2_mp_bus_buserr:*/
  15816. #define MI_MP_BUS_BUSERR
  15817. #define MI_MP_BUS_BUSERR_MASK 0x00000002U
  15818. #define MI_MP_BUS_BUSERR_SHIFT 1U
  15819. /*! Slice: miv2_mp_bus_timeo:*/
  15820. #define MI_MP_BUS_TIMEO
  15821. #define MI_MP_BUS_TIMEO_MASK 0x00000001U
  15822. #define MI_MP_BUS_TIMEO_SHIFT 0U
  15823. /*! Register: miv2_mis (0x000016d0) */
  15824. /*! Slice: fill_mp_y: */
  15825. #define FILL_MP_Y
  15826. #define FILL_MP_Y_MASK 0x08000000U
  15827. #define FILL_MP_Y_SHIFT 27U
  15828. /*! Slice: mblk_line: */
  15829. #define MBLK_LINE
  15830. #define MBLK_LINE_MASK 0x04000000U
  15831. #define MBLK_LINE_SHIFT 26U
  15832. /*! Slice: mp_handshk_int: */
  15833. #define MP_HANDSHK_INT
  15834. #define MP_HANDSHK_INT_MASK 0x02000000U
  15835. #define MP_HANDSHK_INT_SHIFT 25U
  15836. /*! Slice: mcm_dma_raw_ready: */
  15837. #define MCM_DMA_RAW_READY
  15838. #define MCM_DMA_RAW_READY_MASK 0x01000000U
  15839. #define MCM_DMA_RAW_READY_SHIFT 24U
  15840. /*! Slice: sp2_dma_raw_ready: */
  15841. #define SP2_DMA_RAW_READY
  15842. #define SP2_DMA_RAW_READY_MASK 0x00800000U
  15843. #define SP2_DMA_RAW_READY_SHIFT 23U
  15844. /*! Slice: sp2_dma_ycbcr_ready: */
  15845. #define SP2_DMA_YCBCR_READY
  15846. #define SP2_DMA_YCBCR_READY_MASK 0x00400000U
  15847. #define SP2_DMA_YCBCR_READY_SHIFT 22U
  15848. /*! Slice: wrap_mcm_raw1: */
  15849. #define WRAP_MCM_RAW1
  15850. #define WRAP_MCM_RAW1_MASK 0x00200000U
  15851. #define WRAP_MCM_RAW1_SHIFT 21U
  15852. /*! Slice: wrap_mcm_raw0: */
  15853. #define WRAP_MCM_RAW0
  15854. #define WRAP_MCM_RAW0_MASK 0x00100000U
  15855. #define WRAP_MCM_RAW0_SHIFT 20U
  15856. /*! Slice: wrap_sp2_cr: */
  15857. #define WRAP_SP2_CR
  15858. #define WRAP_SP2_CR_MASK 0x00040000U
  15859. #define WRAP_SP2_CR_SHIFT 18U
  15860. /*! Slice: wrap_sp2_cb: */
  15861. #define WRAP_SP2_CB
  15862. #define WRAP_SP2_CB_MASK 0x00020000U
  15863. #define WRAP_SP2_CB_SHIFT 17U
  15864. /*! Slice: wrap_sp2_y: */
  15865. #define WRAP_SP2_Y
  15866. #define WRAP_SP2_Y_MASK 0x00010000U
  15867. #define WRAP_SP2_Y_SHIFT 16U
  15868. /*! Slice: wrap_sp1_cr: */
  15869. #define WRAP_SP1_CR
  15870. #define WRAP_SP1_CR_MASK 0x00008000U
  15871. #define WRAP_SP1_CR_SHIFT 15U
  15872. /*! Slice: wrap_sp1_cb: */
  15873. #define WRAP_SP1_CB
  15874. #define WRAP_SP1_CB_MASK 0x00004000U
  15875. #define WRAP_SP1_CB_SHIFT 14U
  15876. /*! Slice: wrap_sp1_y: */
  15877. #define WRAP_SP1_Y
  15878. #define WRAP_SP1_Y_MASK 0x00002000U
  15879. #define WRAP_SP1_Y_SHIFT 13U
  15880. /*! Slice: wrap_mp_jdp: */
  15881. #define WRAP_MP_JDP
  15882. #define WRAP_MP_JDP_MASK 0x00001000U
  15883. #define WRAP_MP_JDP_SHIFT 12U
  15884. /*! Slice: wrap_mp_raw: */
  15885. #define WRAP_MP_RAW
  15886. #define WRAP_MP_RAW_MASK 0x00000800U
  15887. #define WRAP_MP_RAW_SHIFT 11U
  15888. /*! Slice: wrap_mp_cr: */
  15889. #define WRAP_MP_CR
  15890. #define WRAP_MP_CR_MASK 0x00000400U
  15891. #define WRAP_MP_CR_SHIFT 10U
  15892. /*! Slice: wrap_mp_cb: */
  15893. #define WRAP_MP_CB
  15894. #define WRAP_MP_CB_MASK 0x00000200U
  15895. #define WRAP_MP_CB_SHIFT 9U
  15896. /*! Slice: wrap_mp_y: */
  15897. #define WRAP_MP_Y
  15898. #define WRAP_MP_Y_MASK 0x00000100U
  15899. #define WRAP_MP_Y_SHIFT 8U
  15900. /*! Slice: mcm_raw1_frame_end: */
  15901. #define MCM_RAW1_FRAME_END
  15902. #define MCM_RAW1_FRAME_END_MASK 0x00000080U
  15903. #define MCM_RAW1_FRAME_END_SHIFT 7U
  15904. /*! Slice: mcm_raw0_frame_end: */
  15905. #define MCM_RAW0_FRAME_END
  15906. #define MCM_RAW0_FRAME_END_MASK 0x00000040U
  15907. #define MCM_RAW0_FRAME_END_SHIFT 6U
  15908. /*! Slice: sp2_raw_frame_end: */
  15909. #define SP2_RAW_FRAME_END
  15910. #define SP2_RAW_FRAME_END_MASK 0x00000020U
  15911. #define SP2_RAW_FRAME_END_SHIFT 5U
  15912. /*! Slice: sp2_ycbcr_frame_end: */
  15913. #define SP2_YCBCR_FRAME_END
  15914. #define SP2_YCBCR_FRAME_END_MASK 0x00000010U
  15915. #define SP2_YCBCR_FRAME_END_SHIFT 4U
  15916. /*! Slice: sp1_ycbcr_frame_end: */
  15917. #define SP1_YCBCR_FRAME_END
  15918. #define SP1_YCBCR_FRAME_END_MASK 0x00000008U
  15919. #define SP1_YCBCR_FRAME_END_SHIFT 3U
  15920. /*! Slice: mp_jdp_frame_end: */
  15921. #define MP_JDP_FRAME_END
  15922. #define MP_JDP_FRAME_END_MASK 0x00000004U
  15923. #define MP_JDP_FRAME_END_SHIFT 2U
  15924. /*! Slice: mp_raw_frame_end: */
  15925. #define MP_RAW_FRAME_END
  15926. #define MP_RAW_FRAME_END_MASK 0x00000002U
  15927. #define MP_RAW_FRAME_END_SHIFT 1U
  15928. /*! Slice: mp_ycbcr_frame_end: */
  15929. #define MP_YCBCR_FRAME_END
  15930. #define MP_YCBCR_FRAME_END_MASK 0x00000001U
  15931. #define MP_YCBCR_FRAME_END_SHIFT 0U
  15932. /*! Register: miv2_mis1 (0x000016d4) */
  15933. /*! Slice: miv2_mcm_bus_buserr: */
  15934. #define MI_MCM_BUS_BUSERR
  15935. #define MI_MCM_BUS_BUSERR_MASK 0x00000080U
  15936. #define MI_MCM_BUS_BUSERR_SHIFT 7U
  15937. /*! Slice: miv2_mcm_bus_timeo: */
  15938. #define MI_MCM_BUS_TIMEO
  15939. #define MI_MCM_BUS_TIMEO_MASK 0x00000040U
  15940. #define MI_MCM_BUS_TIMEO_SHIFT 6U
  15941. /*! Slice: miv2_sp2_bus_buserr: */
  15942. #define MI_SP2_BUS_BUSERR
  15943. #define MI_SP2_BUS_BUSERR_MASK 0x00000020U
  15944. #define MI_SP2_BUS_BUSERR_SHIFT 5U
  15945. /*! Slice: miv2_sp2_bus_timeo: */
  15946. #define MI_SP2_BUS_TIMEO
  15947. #define MI_SP2_BUS_TIMEO_MASK 0x00000010U
  15948. #define MI_SP2_BUS_TIMEO_SHIFT 4U
  15949. /*! Slice: miv2_sp1_bus_buserr: */
  15950. #define MI_SP1_BUS_BUSERR
  15951. #define MI_SP1_BUS_BUSERR_MASK 0x00000008U
  15952. #define MI_SP1_BUS_BUSERR_SHIFT 3U
  15953. /*! Slice: miv2_sp1_bus_timeo: */
  15954. #define MI_SP1_BUS_TIMEO
  15955. #define MI_SP1_BUS_TIMEO_MASK 0x00000004U
  15956. #define MI_SP1_BUS_TIMEO_SHIFT 2U
  15957. /*! Slice: miv2_mp_bus_buserr: */
  15958. #define MI_MP_BUS_BUSERR
  15959. #define MI_MP_BUS_BUSERR_MASK 0x00000002U
  15960. #define MI_MP_BUS_BUSERR_SHIFT 1U
  15961. /*! Slice: miv2_mp_bus_timeo: */
  15962. #define MI_MP_BUS_TIMEO
  15963. #define MI_MP_BUS_TIMEO_MASK 0x00000001U
  15964. #define MI_MP_BUS_TIMEO_SHIFT 0U
  15965. /*! Register: miv2_icr (0x000016d8) */
  15966. /*! Slice: fill_mp_y: */
  15967. #define FILL_MP_Y
  15968. #define FILL_MP_Y_MASK 0x08000000U
  15969. #define FILL_MP_Y_SHIFT 27U
  15970. /*! Slice: mblk_line: */
  15971. #define MBLK_LINE
  15972. #define MBLK_LINE_MASK 0x04000000U
  15973. #define MBLK_LINE_SHIFT 26U
  15974. /*! Slice: mp_handshk_int: */
  15975. #define MP_HANDSHK_INT
  15976. #define MP_HANDSHK_INT_MASK 0x02000000U
  15977. #define MP_HANDSHK_INT_SHIFT 25U
  15978. /*! Slice: mcm_dma_raw_ready: */
  15979. #define MCM_DMA_RAW_READY
  15980. #define MCM_DMA_RAW_READY_MASK 0x01000000U
  15981. #define MCM_DMA_RAW_READY_SHIFT 24U
  15982. /*! Slice: sp2_dma_raw_ready: */
  15983. #define SP2_DMA_RAW_READY
  15984. #define SP2_DMA_RAW_READY_MASK 0x00800000U
  15985. #define SP2_DMA_RAW_READY_SHIFT 23U
  15986. /*! Slice: sp2_dma_ycbcr_ready: */
  15987. #define SP2_DMA_YCBCR_READY
  15988. #define SP2_DMA_YCBCR_READY_MASK 0x00400000U
  15989. #define SP2_DMA_YCBCR_READY_SHIFT 22U
  15990. /*! Slice: wrap_mcm_raw1: */
  15991. #define WRAP_MCM_RAW1
  15992. #define WRAP_MCM_RAW1_MASK 0x00200000U
  15993. #define WRAP_MCM_RAW1_SHIFT 21U
  15994. /*! Slice: wrap_mcm_raw0: */
  15995. #define WRAP_MCM_RAW0
  15996. #define WRAP_MCM_RAW0_MASK 0x00100000U
  15997. #define WRAP_MCM_RAW0_SHIFT 20U
  15998. /*! Slice: wrap_sp2_cr: */
  15999. #define WRAP_SP2_CR
  16000. #define WRAP_SP2_CR_MASK 0x00040000U
  16001. #define WRAP_SP2_CR_SHIFT 18U
  16002. /*! Slice: wrap_sp2_cb: */
  16003. #define WRAP_SP2_CB
  16004. #define WRAP_SP2_CB_MASK 0x00020000U
  16005. #define WRAP_SP2_CB_SHIFT 17U
  16006. /*! Slice: wrap_sp2_y: */
  16007. #define WRAP_SP2_Y
  16008. #define WRAP_SP2_Y_MASK 0x00010000U
  16009. #define WRAP_SP2_Y_SHIFT 16U
  16010. /*! Slice: wrap_sp1_cr: */
  16011. #define WRAP_SP1_CR
  16012. #define WRAP_SP1_CR_MASK 0x00008000U
  16013. #define WRAP_SP1_CR_SHIFT 15U
  16014. /*! Slice: wrap_sp1_cb: */
  16015. #define WRAP_SP1_CB
  16016. #define WRAP_SP1_CB_MASK 0x00004000U
  16017. #define WRAP_SP1_CB_SHIFT 14U
  16018. /*! Slice: wrap_sp1_y: */
  16019. #define WRAP_SP1_Y
  16020. #define WRAP_SP1_Y_MASK 0x00002000U
  16021. #define WRAP_SP1_Y_SHIFT 13U
  16022. /*! Slice: wrap_mp_jdp: */
  16023. #define WRAP_MP_JDP
  16024. #define WRAP_MP_JDP_MASK 0x00001000U
  16025. #define WRAP_MP_JDP_SHIFT 12U
  16026. /*! Slice: wrap_mp_raw: */
  16027. #define WRAP_MP_RAW
  16028. #define WRAP_MP_RAW_MASK 0x00000800U
  16029. #define WRAP_MP_RAW_SHIFT 11U
  16030. /*! Slice: wrap_mp_cr: */
  16031. #define WRAP_MP_CR
  16032. #define WRAP_MP_CR_MASK 0x00000400U
  16033. #define WRAP_MP_CR_SHIFT 10U
  16034. /*! Slice: wrap_mp_cb: */
  16035. #define WRAP_MP_CB
  16036. #define WRAP_MP_CB_MASK 0x00000200U
  16037. #define WRAP_MP_CB_SHIFT 9U
  16038. /*! Slice: wrap_mp_y: */
  16039. #define WRAP_MP_Y
  16040. #define WRAP_MP_Y_MASK 0x00000100U
  16041. #define WRAP_MP_Y_SHIFT 8U
  16042. /*! Slice: mcm_raw1_frame_end: */
  16043. #define MCM_RAW1_FRAME_END
  16044. #define MCM_RAW1_FRAME_END_MASK 0x00000080U
  16045. #define MCM_RAW1_FRAME_END_SHIFT 7U
  16046. /*! Slice: mcm_raw0_frame_end: */
  16047. #define MCM_RAW0_FRAME_END
  16048. #define MCM_RAW0_FRAME_END_MASK 0x00000040U
  16049. #define MCM_RAW0_FRAME_END_SHIFT 6U
  16050. /*! Slice: sp2_raw_frame_end: */
  16051. #define SP2_RAW_FRAME_END
  16052. #define SP2_RAW_FRAME_END_MASK 0x00000020U
  16053. #define SP2_RAW_FRAME_END_SHIFT 5U
  16054. /*! Slice: sp2_ycbcr_frame_end: */
  16055. #define SP2_YCBCR_FRAME_END
  16056. #define SP2_YCBCR_FRAME_END_MASK 0x00000010U
  16057. #define SP2_YCBCR_FRAME_END_SHIFT 4U
  16058. /*! Slice: sp1_ycbcr_frame_end: */
  16059. #define SP1_YCBCR_FRAME_END
  16060. #define SP1_YCBCR_FRAME_END_MASK 0x00000008U
  16061. #define SP1_YCBCR_FRAME_END_SHIFT 3U
  16062. /*! Slice: mp_jdp_frame_end: */
  16063. #define MP_JDP_FRAME_END
  16064. #define MP_JDP_FRAME_END_MASK 0x00000004U
  16065. #define MP_JDP_FRAME_END_SHIFT 2U
  16066. /*! Slice: mp_raw_frame_end: */
  16067. #define MP_RAW_FRAME_END
  16068. #define MP_RAW_FRAME_END_MASK 0x00000002U
  16069. #define MP_RAW_FRAME_END_SHIFT 1U
  16070. /*! Slice: mp_ycbcr_frame_end: */
  16071. #define MP_YCBCR_FRAME_END
  16072. #define MP_YCBCR_FRAME_END_MASK 0x00000001U
  16073. #define MP_YCBCR_FRAME_END_SHIFT 0U
  16074. /*! Register: miv2_icr1 (0x000016dc) */
  16075. /*! Slice: miv2_mcm_bus_buserr: */
  16076. #define MI_MCM_BUS_BUSERR
  16077. #define MI_MCM_BUS_BUSERR_MASK 0x00000080U
  16078. #define MI_MCM_BUS_BUSERR_SHIFT 7U
  16079. /*! Slice: miv2_mcm_bus_timeo: */
  16080. #define MI_MCM_BUS_TIMEO
  16081. #define MI_MCM_BUS_TIMEO_MASK 0x00000040U
  16082. #define MI_MCM_BUS_TIMEO_SHIFT 6U
  16083. /*! Slice: miv2_sp2_bus_buserr: */
  16084. #define MI_SP2_BUS_BUSERR
  16085. #define MI_SP2_BUS_BUSERR_MASK 0x00000020U
  16086. #define MI_SP2_BUS_BUSERR_SHIFT 5U
  16087. /*! Slice: miv2_sp2_bus_timeo: */
  16088. #define MI_SP2_BUS_TIMEO
  16089. #define MI_SP2_BUS_TIMEO_MASK 0x00000010U
  16090. #define MI_SP2_BUS_TIMEO_SHIFT 4U
  16091. /*! Slice: miv2_sp1_bus_buserr: */
  16092. #define MI_SP1_BUS_BUSERR
  16093. #define MI_SP1_BUS_BUSERR_MASK 0x00000008U
  16094. #define MI_SP1_BUS_BUSERR_SHIFT 3U
  16095. /*! Slice: miv2_sp1_bus_timeo: */
  16096. #define MI_SP1_BUS_TIMEO
  16097. #define MI_SP1_BUS_TIMEO_MASK 0x00000004U
  16098. #define MI_SP1_BUS_TIMEO_SHIFT 2U
  16099. /*! Slice: miv2_mp_bus_buserr: */
  16100. #define MI_MP_BUS_BUSERR
  16101. #define MI_MP_BUS_BUSERR_MASK 0x00000002U
  16102. #define MI_MP_BUS_BUSERR_SHIFT 1U
  16103. /*! Slice: miv2_mp_bus_timeo: */
  16104. #define MI_MP_BUS_TIMEO
  16105. #define MI_MP_BUS_TIMEO_MASK 0x00000001U
  16106. #define MI_MP_BUS_TIMEO_SHIFT 0U
  16107. /*! Register: miv2_ris (0x000016e0) */
  16108. /*! Slice: fill_mp_y: */
  16109. #define FILL_MP_Y
  16110. #define FILL_MP_Y_MASK 0x08000000U
  16111. #define FILL_MP_Y_SHIFT 27U
  16112. /*! Slice: mblk_line: */
  16113. #define MBLK_LINE
  16114. #define MBLK_LINE_MASK 0x04000000U
  16115. #define MBLK_LINE_SHIFT 26U
  16116. /*! Slice: mp_handshk_int: */
  16117. #define MP_HANDSHK_INT
  16118. #define MP_HANDSHK_INT_MASK 0x02000000U
  16119. #define MP_HANDSHK_INT_SHIFT 25U
  16120. /*! Slice: mcm_dma_raw_ready: */
  16121. #define MCM_DMA_RAW_READY
  16122. #define MCM_DMA_RAW_READY_MASK 0x01000000U
  16123. #define MCM_DMA_RAW_READY_SHIFT 24U
  16124. /*! Slice: sp2_dma_raw_ready: */
  16125. #define SP2_DMA_RAW_READY
  16126. #define SP2_DMA_RAW_READY_MASK 0x00800000U
  16127. #define SP2_DMA_RAW_READY_SHIFT 23U
  16128. /*! Slice: sp2_dma_ycbcr_ready: */
  16129. #define SP2_DMA_YCBCR_READY
  16130. #define SP2_DMA_YCBCR_READY_MASK 0x00400000U
  16131. #define SP2_DMA_YCBCR_READY_SHIFT 22U
  16132. /*! Slice: wrap_mcm_raw1: */
  16133. #define WRAP_MCM_RAW1
  16134. #define WRAP_MCM_RAW1_MASK 0x00200000U
  16135. #define WRAP_MCM_RAW1_SHIFT 21U
  16136. /*! Slice: wrap_mcm_raw0: */
  16137. #define WRAP_MCM_RAW0
  16138. #define WRAP_MCM_RAW0_MASK 0x00100000U
  16139. #define WRAP_MCM_RAW0_SHIFT 20U
  16140. /*! Slice: wrap_sp2_raw: */
  16141. #define WRAP_SP2_RAW
  16142. #define WRAP_SP2_RAW_MASK (0x1 << 16)
  16143. #define WRAP_SP2_RAW_SHIFT 16U
  16144. /*! Slice: wrap_sp2_cr: */
  16145. #define WRAP_SP2_CR
  16146. #define WRAP_SP2_CR_MASK 0x00040000U
  16147. #define WRAP_SP2_CR_SHIFT 18U
  16148. /*! Slice: wrap_sp2_cb: */
  16149. #define WRAP_SP2_CB
  16150. #define WRAP_SP2_CB_MASK 0x00020000U
  16151. #define WRAP_SP2_CB_SHIFT 17U
  16152. /*! Slice: wrap_sp2_y: */
  16153. #define WRAP_SP2_Y
  16154. #define WRAP_SP2_Y_MASK 0x00010000U
  16155. #define WRAP_SP2_Y_SHIFT 16U
  16156. /*! Slice: wrap_sp1_cr: */
  16157. #define WRAP_SP1_CR
  16158. #define WRAP_SP1_CR_MASK 0x00008000U
  16159. #define WRAP_SP1_CR_SHIFT 15U
  16160. /*! Slice: wrap_sp1_cb: */
  16161. #define WRAP_SP1_CB
  16162. #define WRAP_SP1_CB_MASK 0x00004000U
  16163. #define WRAP_SP1_CB_SHIFT 14U
  16164. /*! Slice: wrap_sp1_y: */
  16165. #define WRAP_SP1_Y
  16166. #define WRAP_SP1_Y_MASK 0x00002000U
  16167. #define WRAP_SP1_Y_SHIFT 13U
  16168. /*! Slice: wrap_mp_jdp: */
  16169. #define WRAP_MP_JDP
  16170. #define WRAP_MP_JDP_MASK 0x00001000U
  16171. #define WRAP_MP_JDP_SHIFT 12U
  16172. /*! Slice: wrap_mp_raw: */
  16173. #define WRAP_MP_RAW
  16174. #define WRAP_MP_RAW_MASK 0x00000800U
  16175. #define WRAP_MP_RAW_SHIFT 11U
  16176. /*! Slice: wrap_mp_cr: */
  16177. #define WRAP_MP_CR
  16178. #define WRAP_MP_CR_MASK 0x00000400U
  16179. #define WRAP_MP_CR_SHIFT 10U
  16180. /*! Slice: wrap_mp_cb: */
  16181. #define WRAP_MP_CB
  16182. #define WRAP_MP_CB_MASK 0x00000200U
  16183. #define WRAP_MP_CB_SHIFT 9U
  16184. /*! Slice: wrap_mp_y: */
  16185. #define WRAP_MP_Y
  16186. #define WRAP_MP_Y_MASK 0x00000100U
  16187. #define WRAP_MP_Y_SHIFT 8U
  16188. /*! Slice: mcm_raw1_frame_end: */
  16189. #define MCM_RAW1_FRAME_END
  16190. #define MCM_RAW1_FRAME_END_MASK 0x00000080U
  16191. #define MCM_RAW1_FRAME_END_SHIFT 7U
  16192. /*! Slice: mcm_raw0_frame_end: */
  16193. #define MCM_RAW0_FRAME_END
  16194. #define MCM_RAW0_FRAME_END_MASK 0x00000040U
  16195. #define MCM_RAW0_FRAME_END_SHIFT 6U
  16196. /*! Slice: sp2_raw_frame_end: */
  16197. #define SP2_RAW_FRAME_END
  16198. #define SP2_RAW_FRAME_END_MASK 0x00000020U
  16199. #define SP2_RAW_FRAME_END_SHIFT 5U
  16200. /*! Slice: sp2_ycbcr_frame_end: */
  16201. #define SP2_YCBCR_FRAME_END
  16202. #define SP2_YCBCR_FRAME_END_MASK 0x00000010U
  16203. #define SP2_YCBCR_FRAME_END_SHIFT 4U
  16204. /*! Slice: sp1_ycbcr_frame_end: */
  16205. #define SP1_YCBCR_FRAME_END
  16206. #define SP1_YCBCR_FRAME_END_MASK 0x00000008U
  16207. #define SP1_YCBCR_FRAME_END_SHIFT 3U
  16208. /*! Slice: mp_jdp_frame_end: */
  16209. #define MP_JDP_FRAME_END
  16210. #define MP_JDP_FRAME_END_MASK 0x00000004U
  16211. #define MP_JDP_FRAME_END_SHIFT 2U
  16212. /*! Slice: mp_raw_frame_end: */
  16213. #define MP_RAW_FRAME_END
  16214. #define MP_RAW_FRAME_END_MASK 0x00000002U
  16215. #define MP_RAW_FRAME_END_SHIFT 1U
  16216. /*! Slice: mp_ycbcr_frame_end: */
  16217. #define MP_YCBCR_FRAME_END
  16218. #define MP_YCBCR_FRAME_END_MASK 0x00000001U
  16219. #define MP_YCBCR_FRAME_END_SHIFT 0U
  16220. /*! Register: miv2_ris1 (0x000016e4)*/
  16221. /*! Slice: miv2_mcm_bus_buserr:*/
  16222. #define MI_MCM_BUS_BUSERR
  16223. #define MI_MCM_BUS_BUSERR_MASK 0x00000080U
  16224. #define MI_MCM_BUS_BUSERR_SHIFT 7U
  16225. /*! Slice: miv2_mcm_bus_timeo:*/
  16226. #define MI_MCM_BUS_TIMEO
  16227. #define MI_MCM_BUS_TIMEO_MASK 0x00000040U
  16228. #define MI_MCM_BUS_TIMEO_SHIFT 6U
  16229. /*! Slice: miv2_sp2_bus_buserr:*/
  16230. #define MI_SP2_BUS_BUSERR
  16231. #define MI_SP2_BUS_BUSERR_MASK 0x00000020U
  16232. #define MI_SP2_BUS_BUSERR_SHIFT 5U
  16233. /*! Slice: miv2_sp2_bus_timeo:*/
  16234. #define MI_SP2_BUS_TIMEO
  16235. #define MI_SP2_BUS_TIMEO_MASK 0x00000010U
  16236. #define MI_SP2_BUS_TIMEO_SHIFT 4U
  16237. /*! Slice: miv2_sp1_bus_buserr:*/
  16238. #define MI_SP1_BUS_BUSERR
  16239. #define MI_SP1_BUS_BUSERR_MASK 0x00000008U
  16240. #define MI_SP1_BUS_BUSERR_SHIFT 3U
  16241. /*! Slice: miv2_sp1_bus_timeo:*/
  16242. #define MI_SP1_BUS_TIMEO
  16243. #define MI_SP1_BUS_TIMEO_MASK 0x00000004U
  16244. #define MI_SP1_BUS_TIMEO_SHIFT 2U
  16245. /*! Slice: miv2_mp_bus_buserr:*/
  16246. #define MI_MP_BUS_BUSERR
  16247. #define MI_MP_BUS_BUSERR_MASK 0x00000002U
  16248. #define MI_MP_BUS_BUSERR_SHIFT 1U
  16249. /*! Slice: miv2_mp_bus_timeo:*/
  16250. #define MI_MP_BUS_TIMEO
  16251. #define MI_MP_BUS_TIMEO_MASK 0x00000001U
  16252. #define MI_MP_BUS_TIMEO_SHIFT 0U
  16253. /*! Register: miv2_mp_y_irq_offs_init (0x00001700)*/
  16254. /*! Slice: mp_y_irq_offs_init:*/
  16255. #define MP_Y_IRQ_OFFS_INIT
  16256. #define MP_Y_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
  16257. #define MP_Y_IRQ_OFFS_INIT_SHIFT 3U
  16258. /*! Register: miv2_mp_jdp_irq_offs_init (0x00001704)*/
  16259. /*! Slice: mp_jdp_irq_offs_init:*/
  16260. #define MP_JDP_IRQ_OFFS_INIT
  16261. #define MP_JDP_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
  16262. #define MP_JDP_IRQ_OFFS_INIT_SHIFT 3U
  16263. /*! Register: miv2_mp_raw_irq_offs_init (0x00001708)*/
  16264. /*! Slice: mp_raw_irq_offs_init:*/
  16265. #define MP_RAW_IRQ_OFFS_INIT
  16266. #define MP_RAW_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
  16267. #define MP_RAW_IRQ_OFFS_INIT_SHIFT 3U
  16268. /*! Register: miv2_sp1_y_irq_offs_init (0x0000170c)*/
  16269. /*! Slice: sp1_y_irq_offs_init:*/
  16270. #define SP1_Y_IRQ_OFFS_INIT
  16271. #define SP1_Y_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
  16272. #define SP1_Y_IRQ_OFFS_INIT_SHIFT 3U
  16273. /*! Register: miv2_sp2_y_irq_offs_init (0x00001710)*/
  16274. /*! Slice: sp2_y_irq_offs_init:*/
  16275. #define SP2_Y_IRQ_OFFS_INIT
  16276. #define SP2_Y_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
  16277. #define SP2_Y_IRQ_OFFS_INIT_SHIFT 3U
  16278. /*! Register: miv2_sp2_raw_irq_offs_init (0x00001714)*/
  16279. /*! Slice: sp2_raw_irq_offs_init:*/
  16280. #define SP2_RAW_IRQ_OFFS_INIT
  16281. #define SP2_RAW_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
  16282. #define SP2_RAW_IRQ_OFFS_INIT_SHIFT 3U
  16283. /*! Register: miv2_mcm_raw0_irq_offs_init (0x00001718)*/
  16284. /*! Slice: mcm_raw0_irq_offs_init:*/
  16285. #define MCM_RAW0_IRQ_OFFS_INIT
  16286. #define MCM_RAW0_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
  16287. #define MCM_RAW0_IRQ_OFFS_INIT_SHIFT 3U
  16288. /*! Register: miv2_mcm_raw1_irq_offs_init (0x0000171c)*/
  16289. /*! Slice: mcm_raw1_irq_offs_init:*/
  16290. #define MCM_RAW1_IRQ_OFFS_INIT
  16291. #define MCM_RAW1_IRQ_OFFS_INIT_MASK 0x1FFFFFF8U
  16292. #define MCM_RAW1_IRQ_OFFS_INIT_SHIFT 3U
  16293. /*! Register: miv2_mp_y_irq_offs_shd (0x00001720)*/
  16294. /*! Slice: mp_y_irq_offs:*/
  16295. #define MP_Y_IRQ_OFFS
  16296. #define MP_Y_IRQ_OFFS_MASK 0x1FFFFFF8U
  16297. #define MP_Y_IRQ_OFFS_SHIFT 3U
  16298. /*! Register: miv2_mp_jdp_irq_offs_shd (0x00001724)*/
  16299. /*! Slice: mp_jdp_irq_offs:*/
  16300. #define MP_JDP_IRQ_OFFS
  16301. #define MP_JDP_IRQ_OFFS_MASK 0x1FFFFFF8U
  16302. #define MP_JDP_IRQ_OFFS_SHIFT 3U
  16303. /*! Register: miv2_mp_raw_irq_offs_shd (0x00001728)*/
  16304. /*! Slice: mp_raw_irq_offs:*/
  16305. #define MP_RAW_IRQ_OFFS
  16306. #define MP_RAW_IRQ_OFFS_MASK 0x1FFFFFF8U
  16307. #define MP_RAW_IRQ_OFFS_SHIFT 3U
  16308. /*! Register: miv2_sp1_y_irq_offs_shd (0x0000172c)*/
  16309. /*! Slice: sp1_y_irq_offs:*/
  16310. #define SP1_Y_IRQ_OFFS
  16311. #define SP1_Y_IRQ_OFFS_MASK 0x1FFFFFF8U
  16312. #define SP1_Y_IRQ_OFFS_SHIFT 3U
  16313. /*! Register: miv2_sp2_y_irq_offs_shd (0x00001730)*/
  16314. /*! Slice: sp2_y_irq_offs:*/
  16315. #define SP2_Y_IRQ_OFFS
  16316. #define SP2_Y_IRQ_OFFS_MASK 0x1FFFFFF8U
  16317. #define SP2_Y_IRQ_OFFS_SHIFT 3U
  16318. /*! Register: miv2_sp2_raw_irq_offs_shd (0x00001734)*/
  16319. /*! Slice: sp2_raw_irq_offs:*/
  16320. #define SP2_RAW_IRQ_OFFS
  16321. #define SP2_RAW_IRQ_OFFS_MASK 0x1FFFFFF8U
  16322. #define SP2_RAW_IRQ_OFFS_SHIFT 3U
  16323. /*! Register: miv2_mcm_raw0_irq_offs_shd (0x00001738)*/
  16324. /*! Slice: mcm_raw0_irq_offs:*/
  16325. #define MCM_RAW0_IRQ_OFFS
  16326. #define MCM_RAW0_IRQ_OFFS_MASK 0x1FFFFFF8U
  16327. #define MCM_RAW0_IRQ_OFFS_SHIFT 3U
  16328. /*! Register: miv2_mcm_raw1_irq_offs_shd (0x0000173c)*/
  16329. /*! Slice: mcm_raw1_irq_offs:*/
  16330. #define MCM_RAW1_IRQ_OFFS
  16331. #define MCM_RAW1_IRQ_OFFS_MASK 0x1FFFFFF8U
  16332. #define MCM_RAW1_IRQ_OFFS_SHIFT 3U
  16333. /*! Register: isp_ee_ctrl (0x00003900)*/
  16334. /*! Slice: isp_ee_ctrl enable:*/
  16335. #define EE_CTRL_ENABLE
  16336. #define EE_CTRL_ENABLE_MASK 0x00000001U
  16337. #define EE_CTRL_ENABLE_SHIFT 0U
  16338. /*! Slice: isp_ee_ctrl_input_sel_flag:*/
  16339. #define EE_CTRL_INPUT_SEL
  16340. #define EE_CTRL_INPUT_SEL_MASK 0x00000002U
  16341. #define EE_CTRL_INPUT_SEL_SHIFT 1U
  16342. /*! Slice: isp_ee_ctrl_soft_reset_flag:*/
  16343. #define EE_CTRL_SOFT_RESET_FLAG
  16344. #define EE_CTRL_SOFT_RESET_FLAG_MASK 0x00000004U
  16345. #define EE_CTRL_SOFT_RESET_FLAG_SHIFT 2U
  16346. /*! Slice: isp_ee_ctrl_strength:*/
  16347. #define EE_CTRL_STRENGTH
  16348. #define EE_CTRL_STRENGTH_MASK 0x000007F8U
  16349. #define EE_CTRL_STRENGTH_SHIFT 3U
  16350. /*! Slice: isp_ee_ctrl_source_strength:*/
  16351. #define EE_CTRL_SOURCE_STRENGTH
  16352. #define EE_CTRL_SOURCE_STRENGTH_MASK 0x0007F800U
  16353. #define EE_CTRL_SOURCE_STRENGTH_SHIFT 11U
  16354. /*! Register: isp_ee_y_gain (0x00003904)*/
  16355. /*! Slice: ee_y_down_gain: */
  16356. #define EE_Y_DOWN_GAIN
  16357. #define EE_Y_DOWN_GAIN_MASK 0xFFFF0000U
  16358. #define EE_Y_DOWN_GAIN_SHIFT 16U
  16359. /*! Slice: ee_y_up_gain: */
  16360. #define EE_Y_UP_GAIN
  16361. #define EE_Y_UP_GAIN_MASK 0x0000FFFFU
  16362. #define EE_Y_UP_GAIN_SHIFT 0U
  16363. /*! Slice: ee_y_gain:*/
  16364. #define EE_Y_GAIN
  16365. #define EE_Y_GAIN_MASK 0xFFFFFFFFU
  16366. #define EE_Y_GAIN_SHIFT 0U
  16367. /*! Register: isp_ee_edge_gain (0x00003908)*/
  16368. /*! Slice: isp_ee_edge_gain:*/
  16369. #define EE_EDGE_GAIN
  16370. #define EE_EDGE_GAIN_MASK 0xFFFF0000U
  16371. #define EE_EDGE_GAIN_SHIFT 16U
  16372. /*! Register: isp_ee_uv_gain (0x00003908)*/
  16373. /*! Slice: isp_ee_uv_gain:*/
  16374. #define EE_UV_GAIN
  16375. #define EE_UV_GAIN_MASK 0x0000FFFFU
  16376. #define EE_UV_GAIN_SHIFT 0U
  16377. /*! Register: isp_ee_dummy_hblank (0x00003918)*/
  16378. /*! Slice: isp_ee_dummy_hblank:*/
  16379. #define ISP_EE_DUMMY_HBLANK
  16380. #define ISP_EE_DUMMY_HBLANK_MASK 0x0000FFFFU
  16381. #define ISP_EE_DUMMY_HBLANK_SHIFT 0U
  16382. /*! Register: isp_ee_ctrl_shd (0x0000390c)*/
  16383. /*! Slice: isp_ee_ctrl_shd enable:*/
  16384. #define EE_CTRL_ENABLE_SHD
  16385. #define EE_CTRL_ENABLE_SHD_MASK 0x00000001U
  16386. #define EE_CTRL_ENABLE_SHD_SHIFT 0U
  16387. /*! Slice: isp_ee_ctrl_input_sel_shd:*/
  16388. #define EE_CTRL_INPUT_SEL_SHD
  16389. #define EE_CTRL_INPUT_SEL_SHD_MASK 0x00000002U
  16390. #define EE_CTRL_INPUT_SEL_SHD_SHIFT 1U
  16391. /*! Slice: isp_ee_ctrl_soft_reset_flag_shd:*/
  16392. #define EE_CTRL_SOFT_RESET_FLAG_SHD
  16393. #define EE_CTRL_SOFT_RESET_FLAG_SHD_MASK 0x00000004U
  16394. #define EE_CTRL_SOFT_RESET_FLAG_SHD_SHIFT 2U
  16395. /*! Slice: isp_ee_ctrl_strength_shd:*/
  16396. #define EE_CTRL_STRENGTH_SHD
  16397. #define EE_CTRL_STRENGTH_SHD_MASK 0x000007F8U
  16398. #define EE_CTRL_STRENGTH_SHD_SHIFT 3U
  16399. /*! Slice: isp_ee_ctrl_source_strength_shd:*/
  16400. #define EE_CTRL_SOURCE_STRENGTH_SHD
  16401. #define EE_CTRL_SOURCE_STRENGTH_SHD_MASK 0xFF000000U
  16402. #define EE_CTRL_SOURCE_STRENGTH_SHD_SHIFT 24U
  16403. /*! Register: isp_ee_y_gain_shd (0x00003910)*/
  16404. /*! Slice: isp_ee_y_gain_shd:*/
  16405. #define EE_Y_GAIN_SHD
  16406. #define EE_Y_GAIN_SHD_MASK 0xFFFFFFFFU
  16407. #define EE_Y_GAIN_SHD_SHIFT 0U
  16408. /*! Register: isp_ee_edge_gain_shd (0x00003908)*/
  16409. /*! Slice: isp_ee_edge_gain_shd:*/
  16410. #define EE_EDGE_GAIN_SHD
  16411. #define EE_EDGE_GAIN_SHD_MASK 0xFFFF0000U
  16412. #define EE_EDGE_GAIN_SHD_SHIFT 16U
  16413. /*! Register: isp_ee_uv_gain_shd (0x00003914)*/
  16414. /*! Slice: isp_ee_uv_gain_shd:*/
  16415. #define EE_UV_GAIN_SHD
  16416. #define EE_UV_GAIN_SHD_MASK 0x0000FFFFU
  16417. #define EE_UV_GAIN_SHD_SHIFT 0U
  16418. #define ISP_DEMOSAIC_THR
  16419. #define ISP_DEMOSAIC_THR_MASK 0xff000000U
  16420. #define ISP_DEMOSAIC_THR_SHIFT 24U
  16421. #define ISP_DEMOSAIC_DENOISE_STRENGTH
  16422. #define ISP_DEMOSAIC_DENOISE_STRENGTH_MASK 0x003f0000U
  16423. #define ISP_DEMOSAIC_DENOISE_STRENGTH_SHIFT 16U
  16424. #define ISP_DEMOSAIC_SHARPEN_SIZE
  16425. #define ISP_DEMOSAIC_SHARPEN_SIZE_MASK 0x00001f00U
  16426. #define ISP_DEMOSAIC_SHARPEN_SIZE_SHIFT 8U
  16427. #define ISP_DEMOSAIC_SHARPEN_LINE_ENABLE
  16428. #define ISP_DEMOSAIC_SHARPEN_LINE_ENABLE_MASK 0x00000020U
  16429. #define ISP_DEMOSAIC_SHARPEN_LINE_ENABLE_SHIFT 5U
  16430. #define ISP_DEMOSAIC_SKIN_ENABLE
  16431. #define ISP_DEMOSAIC_SKIN_ENABLE_MASK 0x00000010U
  16432. #define ISP_DEMOSAIC_SKIN_ENABLE_SHIFT 4U
  16433. #define ISP_DEMOSAIC_DEPURPLE_ENABLE
  16434. #define ISP_DEMOSAIC_DEPURPLE_ENABLE_MASK 0x00000008U
  16435. #define ISP_DEMOSAIC_DEPURPLE_ENABLE_SHIFT 3U
  16436. #define ISP_DEMOSAIC_DEMOIRE_ENABLE
  16437. #define ISP_DEMOSAIC_DEMOIRE_ENABLE_MASK 0x00000004U
  16438. #define ISP_DEMOSAIC_DEMOIRE_ENABLE_SHIFT 2U
  16439. #define ISP_DEMOSAIC_SHARPEN_ENBALE
  16440. #define ISP_DEMOSAIC_SHARPEN_ENBALE_MASK 0x00000002U
  16441. #define ISP_DEMOSAIC_SHARPEN_ENBALE_SHIFT 1U
  16442. #define ISP_DEMOSAIC_BYPASS
  16443. #define ISP_DEMOSAIC_BYPASS_MASK 0x00000001U
  16444. #define ISP_DEMOSAIC_BYPASS_SHIFT 0U
  16445. #define ISP_DMSC_INTERPLATION_DIR_THR_MIN
  16446. #define ISP_DMSC_INTERPLATION_DIR_THR_MIN_MASK 0x00fff000U
  16447. #define ISP_DMSC_INTERPLATION_DIR_THR_MIN_SHIFT 12U
  16448. #define ISP_DMSC_INTERPLATION_DIR_THR_MAX
  16449. #define ISP_DMSC_INTERPLATION_DIR_THR_MAX_MASK 0x00000fffU
  16450. #define ISP_DMSC_INTERPLATION_DIR_THR_MAX_SHIFT 0U
  16451. #define ISP_DMSC_DEMOIRE_AREA_THR
  16452. #define ISP_DMSC_DEMOIRE_AREA_THR_MASK 0x00003f00U
  16453. #define ISP_DMSC_DEMOIRE_AREA_THR_SHIFT 8U
  16454. #define ISP_DMSC_DEMOIRE_SAT_SHRINK
  16455. #define ISP_DMSC_DEMOIRE_SAT_SHRINK_MASK 0x0000003fU
  16456. #define ISP_DMSC_DEMOIRE_SAT_SHRINK_SHIFT 0U
  16457. #define ISP_DMSC_DEMOIRE_R2
  16458. #define ISP_DMSC_DEMOIRE_R2_MASK 0x3FE00000U
  16459. #define ISP_DMSC_DEMOIRE_R2_SHIFT 21U
  16460. #define ISP_DMSC_DEMOIRE_R1
  16461. #define ISP_DMSC_DEMOIRE_R1_MASK 0x001ff000U
  16462. #define ISP_DMSC_DEMOIRE_R1_SHIFT 12U
  16463. #define ISP_DMSC_DEMOIRE_T2_SHIFT
  16464. #define ISP_DMSC_DEMOIRE_T2_SHIFT_MASK 0x00000f00U
  16465. #define ISP_DMSC_DEMOIRE_T2_SHIFT_SHIFT 8U
  16466. #define ISP_DMSC_DEMOIRE_T1
  16467. #define ISP_DMSC_DEMOIRE_T1_MASK 0x000000FFU
  16468. #define ISP_DMSC_DEMOIRE_T1_SHIFT 0U
  16469. #define ISP_DMSC_DEMOIRE_EDGE_R2
  16470. #define ISP_DMSC_DEMOIRE_EDGE_R2_MASK 0x7fc00000U
  16471. #define ISP_DMSC_DEMOIRE_EDGE_R2_SHIFT 22U
  16472. #define ISP_DMSC_DEMOIRE_EDGE_R1
  16473. #define ISP_DMSC_DEMOIRE_EDGE_R1_MASK 0x003fe000U
  16474. #define ISP_DMSC_DEMOIRE_EDGE_R1_SHIFT 13U
  16475. #define ISP_DMSC_DEMOIRE_EDGE_T2_SHIFT
  16476. #define ISP_DMSC_DEMOIRE_EDGE_T2_SHIFT_MASK 0x00001e00U
  16477. #define ISP_DMSC_DEMOIRE_EDGE_T2_SHIFT_SHIFT 9U
  16478. #define ISP_DMSC_DEMOIRE_EDGE_T1
  16479. #define ISP_DMSC_DEMOIRE_EDGE_T1_MASK 0x000001ffU
  16480. #define ISP_DMSC_DEMOIRE_EDGE_T1_SHIFT 0U
  16481. #define ISP_DMSC_SHARPEN_FACTOR_BLACK
  16482. #define ISP_DMSC_SHARPEN_FACTOR_BLACK_MASK 0x001ff000U
  16483. #define ISP_DMSC_SHARPEN_FACTOR_BLACK_SHIFT 12U
  16484. #define ISP_DMSC_SHARPEN_FACTOR_WHITE
  16485. #define ISP_DMSC_SHARPEN_FACTOR_WHITE_MASK 0x000001ffU
  16486. #define ISP_DMSC_SHARPEN_FACTOR_WHITE_SHIFT 0U
  16487. #define ISP_DMSC_SHARPEN_CLIP_BLACK
  16488. #define ISP_DMSC_SHARPEN_CLIP_BLACK_MASK 0x007ff000U
  16489. #define ISP_DMSC_SHARPEN_CLIP_BLACK_SHIFT 12U
  16490. #define ISP_DMSC_SHARPEN_CLIP_WHITE
  16491. #define ISP_DMSC_SHARPEN_CLIP_WHITE_MASK 0x000007ffU
  16492. #define ISP_DMSC_SHARPEN_CLIP_WHITE_SHIFT 0U
  16493. #define ISP_DMSC_SHARPEN_T4_SHIFT
  16494. #define ISP_DMSC_SHARPEN_T4_SHIFT_MASK 0xf0000000U
  16495. #define ISP_DMSC_SHARPEN_T4_SHIFT_SHIFT 28U
  16496. #define ISP_DMSC_SHARPEN_T3
  16497. #define ISP_DMSC_SHARPEN_T3_MASK 0x07ff0000U
  16498. #define ISP_DMSC_SHARPEN_T3_SHIFT 16U
  16499. #define ISP_DMSC_SHARPEN_T2_SHIFT
  16500. #define ISP_DMSC_SHARPEN_T2_SHIFT_MASK 0x0000f000U
  16501. #define ISP_DMSC_SHARPEN_T2_SHIFT_SHIFT 12U
  16502. #define ISP_DMSC_SHARPEN_T1
  16503. #define ISP_DMSC_SHARPEN_T1_MASK 0x000003ffU
  16504. #define ISP_DMSC_SHARPEN_T1_SHIFT 0U
  16505. #define ISP_DMSC_SHARPEN_R3
  16506. #define ISP_DMSC_SHARPEN_R3_MASK 0x07fc0000
  16507. #define ISP_DMSC_SHARPEN_R3_SHIFT 18U
  16508. #define ISP_DMSC_SHARPEN_R2
  16509. #define ISP_DMSC_SHARPEN_R2_MASK 0x0003fe00
  16510. #define ISP_DMSC_SHARPEN_R2_SHIFT 9U
  16511. #define ISP_DMSC_SHARPEN_R1
  16512. #define ISP_DMSC_SHARPEN_R1_MASK 0x000001ffU
  16513. #define ISP_DMSC_SHARPEN_R1_SHIFT 0U
  16514. #define ISP_DMSC_SHARPEN_LINE_SHIFT2
  16515. #define ISP_DMSC_SHARPEN_LINE_SHIFT2_MASK 0xf0000000U
  16516. #define ISP_DMSC_SHARPEN_LINE_SHIFT2_SHIFT 28U
  16517. #define ISP_DMSC_SHARPEN_LINE_SHIFT1
  16518. #define ISP_DMSC_SHARPEN_LINE_SHIFT1_MASK 0x0f000000U
  16519. #define ISP_DMSC_SHARPEN_LINE_SHIFT1_SHIFT 24U
  16520. #define ISP_DMSC_SHARPEN_LINE_T1
  16521. #define ISP_DMSC_SHARPEN_LINE_T1_MASK 0x007ff000U
  16522. #define ISP_DMSC_SHARPEN_LINE_T1_SHIFT 12U
  16523. #define ISP_DMSC_SHARPEN_LINE_STRENGTH
  16524. #define ISP_DMSC_SHARPEN_LINE_STRENGTH_MASK 0x00000fffU
  16525. #define ISP_DMSC_SHARPEN_LINE_STRENGTH_SHIFT 0U
  16526. #define ISP_DMSC_SHARPEN_LINE_R2
  16527. #define ISP_DMSC_SHARPEN_LINE_R2_MASK 0x0003fe00
  16528. #define ISP_DMSC_SHARPEN_LINE_R2_SHIFT 9U
  16529. #define ISP_DMSC_SHARPEN_LINE_R1
  16530. #define ISP_DMSC_SHARPEN_LINE_R1_MASK 0x000001ffU
  16531. #define ISP_DMSC_SHARPEN_LINE_R1_SHIFT 0U
  16532. #define ISP_DMSC_HF_FILT_00
  16533. #define ISP_DMSC_HF_FILT_00_MASK 0x3f000000U
  16534. #define ISP_DMSC_HF_FILT_00_SHIFT 24U
  16535. #define ISP_DMSC_HF_FILT_01
  16536. #define ISP_DMSC_HF_FILT_01_MASK 0x00fc0000U
  16537. #define ISP_DMSC_HF_FILT_01_SHIFT 18U
  16538. #define ISP_DMSC_HF_FILT_02
  16539. #define ISP_DMSC_HF_FILT_02_MASK 0x0003f000U
  16540. #define ISP_DMSC_HF_FILT_02_SHIFT 12U
  16541. #define ISP_DMSC_HF_FILT_10
  16542. #define ISP_DMSC_HF_FILT_10_MASK 0x00000fc0U
  16543. #define ISP_DMSC_HF_FILT_10_SHIFT 6U
  16544. #define ISP_DMSC_HF_FILT_11
  16545. #define ISP_DMSC_HF_FILT_11_MASK 0x0000003fU
  16546. #define ISP_DMSC_HF_FILT_11_SHIFT 0U
  16547. #define ISP_DMSC_HF_FILT_12
  16548. #define ISP_DMSC_HF_FILT_12_MASK 0x00fc0000U
  16549. #define ISP_DMSC_HF_FILT_12_SHIFT 18U
  16550. #define ISP_DMSC_HF_FILT_20
  16551. #define ISP_DMSC_HF_FILT_20_MASK 0x0003f000U
  16552. #define ISP_DMSC_HF_FILT_20_SHIFT 12U
  16553. #define ISP_DMSC_HF_FILT_21
  16554. #define ISP_DMSC_HF_FILT_21_MASK 0x00000fc0U
  16555. #define ISP_DMSC_HF_FILT_21_SHIFT 6U
  16556. #define ISP_DMSC_HF_FILT_22
  16557. #define ISP_DMSC_HF_FILT_22_MASK 0x0000003fU
  16558. #define ISP_DMSC_HF_FILT_22_SHIFT 0U
  16559. #define ISP_DMSC_DEPURPLE_RED_SAT
  16560. #define ISP_DMSC_DEPURPLE_RED_SAT_MASK 0x00001000U
  16561. #define ISP_DMSC_DEPURPLE_RED_SAT_SHIFT 12U
  16562. #define ISP_DMSC_DEPURPLE_BLUE_SAT
  16563. #define ISP_DMSC_DEPURPLE_BLUE_SAT_MASK 0x00002000U
  16564. #define ISP_DMSC_DEPURPLE_BLUE_SAT_SHIFT 13U
  16565. #define ISP_DMSC_DEPURPLE_SAT_SHRINK
  16566. #define ISP_DMSC_DEPURPLE_SAT_SHRINK_MASK 0x00000f00U
  16567. #define ISP_DMSC_DEPURPLE_SAT_SHRINK_SHIFT 8U
  16568. #define ISP_DMSC_DEPURPLE_THR
  16569. #define ISP_DMSC_DEPURPLE_THR_MASK 0x000000ffU
  16570. #define ISP_DMSC_DEPURPLE_THR_SHIFT 0U
  16571. #define ISP_DMSC_SKIN_CB_THR_MAX_2047
  16572. #define ISP_DMSC_SKIN_CB_THR_MAX_2047_MASK 0x00FFF000U
  16573. #define ISP_DMSC_SKIN_CB_THR_MAX_2047_SHIFT 12U
  16574. #define ISP_DMSC_SKIN_CB_THR_MIN_2047
  16575. #define ISP_DMSC_SKIN_CB_THR_MIN_2047_MASK 0x00000fffU
  16576. #define ISP_DMSC_SKIN_CB_THR_MIN_2047_SHIFT 0U
  16577. #define ISP_DMSC_SKIN_CR_THR_MAX_2047
  16578. #define ISP_DMSC_SKIN_CR_THR_MAX_2047_MASK 0x00FFF000U
  16579. #define ISP_DMSC_SKIN_CR_THR_MAX_2047_SHIFT 12U
  16580. #define ISP_DMSC_SKIN_CR_THR_MIN_2047
  16581. #define ISP_DMSC_SKIN_CR_THR_MIN_2047_MASK 0x00000fffU
  16582. #define ISP_DMSC_SKIN_CR_THR_MIN_2047_SHIFT 0U
  16583. #define ISP_DMSC_SKIN_Y_THR_MAX
  16584. #define ISP_DMSC_SKIN_Y_THR_MAX_MASK 0x00FFF000U
  16585. #define ISP_DMSC_SKIN_Y_THR_MAX_SHIFT 12U
  16586. #define ISP_DMSC_SKIN_Y_THR_MIN
  16587. #define ISP_DMSC_SKIN_Y_THR_MIN_MASK 0x00000fffU
  16588. #define ISP_DMSC_SKIN_Y_THR_MIN_SHIFT 0U
  16589. #define ISP_DMSC_CAC_ENABLE
  16590. #define ISP_DMSC_CAC_ENABLE_MASK 0x00000001U
  16591. #define ISP_DMSC_CAC_ENABLE_SHIFT 0U
  16592. #define ISP_DMSC_V_COUNT_START
  16593. #define ISP_DMSC_V_COUNT_START_MASK 0xffff0000U
  16594. #define ISP_DMSC_V_COUNT_START_SHIFT 16U
  16595. #define ISP_DMSC_H_COUNT_START
  16596. #define ISP_DMSC_H_COUNT_START_MASK 0x0000ffffU
  16597. #define ISP_DMSC_H_COUNT_START_SHIFT 0U
  16598. #define ISP_DMSC_A_RED
  16599. #define ISP_DMSC_A_RED_MASK 0x01ff0000U
  16600. #define ISP_DMSC_A_RED_SHIFT 16U
  16601. #define ISP_DMSC_A_BLUE
  16602. #define ISP_DMSC_A_BLUE_MASK 0x000001ffU
  16603. #define ISP_DMSC_A_BLUE_SHIFT 0U
  16604. #define ISP_DMSC_B_RED
  16605. #define ISP_DMSC_B_RED_MASK 0x01ff0000U
  16606. #define ISP_DMSC_B_RED_SHIFT 16U
  16607. #define ISP_DMSC_B_BLUE
  16608. #define ISP_DMSC_B_BLUE_MASK 0x000001ffU
  16609. #define ISP_DMSC_B_BLUE_SHIFT 0U
  16610. #define ISP_DMSC_C_RED
  16611. #define ISP_DMSC_C_RED_MASK 0x01ff0000U
  16612. #define ISP_DMSC_C_RED_SHIFT 16U
  16613. #define ISP_DMSC_C_BLUE
  16614. #define ISP_DMSC_C_BLUE_MASK 0x000001ffU
  16615. #define ISP_DMSC_C_BLUE_SHIFT 0U
  16616. #define ISP_DMSC_X_NS
  16617. #define ISP_DMSC_X_NS_MASK 0x000f0000U
  16618. #define ISP_DMSC_X_NS_SHIFT 16U
  16619. #define ISP_DMSC_X_NF
  16620. #define ISP_DMSC_X_NF_MASK 0x0000001f
  16621. #define ISP_DMSC_X_NF_SHIFT 0U
  16622. #define ISP_DMSC_Y_NS
  16623. #define ISP_DMSC_Y_NS_MASK 0x000f0000U
  16624. #define ISP_DMSC_Y_NS_SHIFT 16U
  16625. #define ISP_DMSC_Y_NF
  16626. #define ISP_DMSC_Y_NF_MASK 0x0000001fU
  16627. #define ISP_DMSC_Y_NF_SHIFT 0U
  16628. #define ISP_DMSC_Y_NF
  16629. #define ISP_DMSC_Y_NF_MASK 0x0000001fU
  16630. #define ISP_DMSC_Y_NF_SHIFT 0U
  16631. #define ISP_DMSC_IMAGE_H_SIZE
  16632. #define ISP_DMSC_IMAGE_H_SIZE_MASK 0x0000ffffU
  16633. #define ISP_DMSC_IMAGE_H_SIZE_SHIFT 0U
  16634. #define ISP_DMSC_IMAGE_H_BLANK
  16635. #define ISP_DMSC_IMAGE_H_BLANK_MASK 0xffff0000U
  16636. #define ISP_DMSC_IMAGE_H_BLANK_SHIFT 16U
  16637. #define ISP_DMSC_H_BLANK
  16638. #define ISP_DMSC_H_BLANK_MASK 0xffff0000U
  16639. #define ISP_DMSC_H_BLANK_SHIFT 16U
  16640. #define ISP_GREEN_EQUILIBTATE_TH
  16641. #define ISP_GREEN_EQUILIBTATE_TH_MASK 0x0001fffeU
  16642. #define ISP_GREEN_EQUILIBTATE_TH_SHIFT 1U
  16643. #define ISP_GREEN_EQUILIBTATE_ENABLE
  16644. #define ISP_GREEN_EQUILIBTATE_ENABLE_MASK 0x00000001U
  16645. #define ISP_GREEN_EQUILIBTATE_ENABLE_SHIFT 0U
  16646. #define ISP_GREEN_EQUILIBTATE_HCNT_DUMMY
  16647. #define ISP_GREEN_EQUILIBTATE_HCNT_DUMMY_MASK 0x0000ffffU
  16648. #define ISP_GREEN_EQUILIBTATE_HCNT_DUMMY_SHIFT 0U
  16649. #define ISP_CURVE_MODE
  16650. #define ISP_CURVE_MODE_MASK 0x00000006U
  16651. #define ISP_CURVE_MODE_SHIFT 1U
  16652. #define ISP_CURVE_ENABLE
  16653. #define ISP_CURVE_ENABLE_MASK 0x00000001U
  16654. #define ISP_CURVE_ENABLE_SHIFT 0U
  16655. #define ISP_CURVE_LUT_X_ADDR
  16656. #define ISP_CURVE_LUT_X_ADDR_MASK 0x0000007fU
  16657. #define ISP_CURVE_LUT_X_ADDR_SHIFT 0U
  16658. #define ISP_CURVE_LUT_X_WRITE_DATA
  16659. #define ISP_CURVE_LUT_X_WRITE_DATA_MASK 0x000000fffU
  16660. #define ISP_CURVE_LUT_X_WRITE_DATA_SHIFT 0U
  16661. #define ISP_CURVE_LUT_LUMA_ADDR
  16662. #define ISP_CURVE_LUT_LUMA_ADDR_MASK 0x0000007fU
  16663. #define ISP_CURVE_LUT_LUMA_ADDR_SHIFT 0U
  16664. #define ISP_CURVE_LUT_LUMA_WRITE_DATA
  16665. #define ISP_CURVE_LUT_LUMA_WRITE_DATA_MASK 0x000007ffU
  16666. #define ISP_CURVE_LUT_LUMA_WRITE_DATA_SHIFT 0U
  16667. #define ISP_CURVE_LUT_CHROMA_ADDR
  16668. #define ISP_CURVE_LUT_CHROMA_ADDR_MASK 0x0000007fU
  16669. #define ISP_CURVE_LUT_CHROMA_ADDR_SHIFT 0U
  16670. #define ISP_CURVE_LUT_CHROMA_WRITE_DATA
  16671. #define ISP_CURVE_LUT_CHROMA_WRITE_DATA_MASK 0x00000fffU
  16672. #define ISP_CURVE_LUT_CHROMA_WRITE_DATA_SHIFT 0U
  16673. #define ISP_CURVE_LUT_SHIFT_ADDR
  16674. #define ISP_CURVE_LUT_SHIFT_ADDR_MASK 0x0000007fU
  16675. #define ISP_CURVE_LUT_SHIFT_ADDR_SHIFT 0U
  16676. #define ISP_CURVE_LUT_SHIFT_WRITE_DATA
  16677. #define ISP_CURVE_LUT_SHIFT_WRITE_DATA_MASK 0x0000001fU
  16678. #define ISP_CURVE_LUT_SHIFT_WRITE_DATA_SHIFT 0U
  16679. #define ISP_DIGITAL_GAIN_R
  16680. #define ISP_DIGITAL_GAIN_R_MASK 0xffff0000U
  16681. #define ISP_DIGITAL_GAIN_R_SHIFT 16U
  16682. #define ISP_DIGITAL_GAIN_B
  16683. #define ISP_DIGITAL_GAIN_B_MASK 0x0000ffffU
  16684. #define ISP_DIGITAL_GAIN_B_SHIFT 0U
  16685. #define ISP_DIGITAL_GAIN_GR
  16686. #define ISP_DIGITAL_GAIN_GR_MASK 0xffff0000U
  16687. #define ISP_DIGITAL_GAIN_GR_SHIFT 16U
  16688. #define ISP_DIGITAL_GAIN_GB
  16689. #define ISP_DIGITAL_GAIN_GB_MASK 0x0000ffffU
  16690. #define ISP_DIGITAL_GAIN_GB_SHIFT 0U
  16691. /*! Register: isp_vsync_delay: (0x00000730)*/
  16692. /*! Slice: vsync_delya:*/
  16693. #define ISP_VSYNC_DELAY
  16694. #define ISP_VSYNC_DELAY_MASK 0x01FFFFFFU
  16695. #define ISP_VSYNC_DELAY_SHIFT 0U
  16696. /*! Register: isp_vsync_delay: (0x00000730)*/
  16697. /*! Slice: reg_vsync_sel:*/
  16698. #define ISP_VSYNC_DELAY_SEL
  16699. #define ISP_VSYNC_DELAY_SEL_MASK 0x80000000U
  16700. #define ISP_VSYNC_DELAY_SEL_SHIFT 31U
  16701. #define WDR4_DUMMY_BLK
  16702. #define WDR4_DUMMY_BLK_MASK (0xffff << 16 )
  16703. #define WDR4_DUMMY_BLK_SHIFT 16U
  16704. #define WDR4_DUMMY_BLK_EN
  16705. #define WDR4_DUMMY_BLK_EN_MASK 0x1 << 15
  16706. #define WDR4_DUMMY_BLK_EN_SHIFT 15U
  16707. #define WDR4_SOFT_RESET_FLAG
  16708. #define WDR4_SOFT_RESET_FLAG_MASK 0x1 << 1
  16709. #define WDR4_SOFT_RESET_FLAG_SHIFT 1U
  16710. #define WDR4_ENABLE
  16711. #define WDR4_ENABLE_MASK 0x1 << 0
  16712. #define WDR4_ENABLE_SHIFT 0U
  16713. #define WDR4_OUTPUT_SHIFT_BIT
  16714. #define WDR4_OUTPUT_SHIFT_BIT_MASK (0x3f << 6 )
  16715. #define WDR4_OUTPUT_SHIFT_BIT_SHIFT 6U
  16716. #define WDR4_PIXEL_SHIFT_BIT
  16717. #define WDR4_PIXEL_SHIFT_BIT_MASK (0x3f << 0 )
  16718. #define WDR4_PIXEL_SHIFT_BIT_SHIFT 0U
  16719. #define WDR4_BLOCK_HEIGHT
  16720. #define WDR4_BLOCK_HEIGHT_MASK (0x1ff << 9 )
  16721. #define WDR4_BLOCK_HEIGHT_SHIFT 9U
  16722. #define WDR4_BLOCK_WIDTH
  16723. #define WDR4_BLOCK_WIDTH_MASK (0x1ff << 0 )
  16724. #define WDR4_BLOCK_WIDTH_SHIFT 0U
  16725. #define WDR4_BLOCK_AREA_INVERSE
  16726. #define WDR4_BLOCK_AREA_INVERSE_MASK (0xfffff << 0 )
  16727. #define WDR4_BLOCK_AREA_INVERSE_SHIFT 0U
  16728. #define WDR4_VALUE_WEIGHT_3
  16729. #define WDR4_VALUE_WEIGHT_3_MASK (0x1f << 15 )
  16730. #define WDR4_VALUE_WEIGHT_3_SHIFT 15U
  16731. #define WDR4_VALUE_WEIGHT_2
  16732. #define WDR4_VALUE_WEIGHT_2_MASK (0x1f << 10 )
  16733. #define WDR4_VALUE_WEIGHT_2_SHIFT 10U
  16734. #define WDR4_VALUE_WEIGHT_1
  16735. #define WDR4_VALUE_WEIGHT_1_MASK (0x1f << 5 )
  16736. #define WDR4_VALUE_WEIGHT_1_SHIFT 5U
  16737. #define WDR4_VALUE_WEIGHT_0
  16738. #define WDR4_VALUE_WEIGHT_0_MASK (0x1f << 0 )
  16739. #define WDR4_VALUE_WEIGHT_0_SHIFT 0U
  16740. #define WDR4_TOTAL_STRENGTH
  16741. #define WDR4_TOTAL_STRENGTH_MASK (0xff << 24 )
  16742. #define WDR4_TOTAL_STRENGTH_SHIFT 24U
  16743. #define WDR4_LOCAL_STRENGTH
  16744. #define WDR4_LOCAL_STRENGTH_MASK (0xff << 16 )
  16745. #define WDR4_LOCAL_STRENGTH_SHIFT 16U
  16746. #define WDR4_GLOBAL_STRENGTH
  16747. #define WDR4_GLOBAL_STRENGTH_MASK (0xff << 8 )
  16748. #define WDR4_GLOBAL_STRENGTH_SHIFT 8U
  16749. #define WDR4_LOW_STRENGTH
  16750. #define WDR4_LOW_STRENGTH_MASK (0xff << 0 )
  16751. #define WDR4_LOW_STRENGTH_SHIFT 0U
  16752. #define WDR4_HIGH_STRENGTH
  16753. #define WDR4_HIGH_STRENGTH_MASK (0xff << 16 )
  16754. #define WDR4_HIGH_STRENGTH_SHIFT 16U
  16755. #define WDR4_DRC_BAYER_RATIOLSVS
  16756. #define WDR4_DRC_BAYER_RATIOLSVS_MASK (0xff << 8 )
  16757. #define WDR4_DRC_BAYER_RATIOLSVS_SHIFT 8U
  16758. #define WDR4_DRC_BAYER_RATIO
  16759. #define WDR4_DRC_BAYER_RATIO_MASK (0xff << 0 )
  16760. #define WDR4_DRC_BAYER_RATIO_SHIFT 0U
  16761. #define WDR4_CONTRAST
  16762. #define WDR4_CONTRAST_MASK (0x7ff << 10 )
  16763. #define WDR4_CONTRAST_SHIFT 10U
  16764. #define WDR4_FLAT_STRENGTH
  16765. #define WDR4_FLAT_STRENGTH_MASK (0x1f << 5 )
  16766. #define WDR4_FLAT_STRENGTH_SHIFT 5U
  16767. #define WDR4_FLAT_THR
  16768. #define WDR4_FLAT_THR_MASK (0x1f << 0 )
  16769. #define WDR4_FLAT_THR_SHIFT 0U
  16770. #define WDR4_PIXEL_MERGE_SLOPE
  16771. #define WDR4_PIXEL_MERGE_SLOPE_MASK (0xff << 24 )
  16772. #define WDR4_PIXEL_MERGE_SLOPE_SHIFT 24U
  16773. #define WDR4_PIXEL_MERGE_BASE
  16774. #define WDR4_PIXEL_MERGE_BASE_MASK (0xff << 16 )
  16775. #define WDR4_PIXEL_MERGE_BASE_SHIFT 16U
  16776. #define WDR4_PIXEL_ADJUST_SLOPE
  16777. #define WDR4_PIXEL_ADJUST_SLOPE_MASK (0xff << 8 )
  16778. #define WDR4_PIXEL_ADJUST_SLOPE_SHIFT 8U
  16779. #define WDR4_PIXEL_ADJUST_BASE
  16780. #define WDR4_PIXEL_ADJUST_BASE_MASK (0xff << 0 )
  16781. #define WDR4_PIXEL_ADJUST_BASE_SHIFT 0U
  16782. #define WDR4_ENTROPY_SLOPE
  16783. #define WDR4_ENTROPY_SLOPE_MASK (0x3ff << 10 )
  16784. #define WDR4_ENTROPY_SLOPE_SHIFT 10U
  16785. #define WDR4_ENTROPY_BASE
  16786. #define WDR4_ENTROPY_BASE_MASK (0x3ff << 0 )
  16787. #define WDR4_ENTROPY_BASE_SHIFT 0U
  16788. #define WDR4_BILITERAL_WIDTH_SIGMA
  16789. #define WDR4_BILITERAL_WIDTH_SIGMA_MASK (0xfffff << 0 )
  16790. #define WDR4_BILITERAL_WIDTH_SIGMA_SHIFT 0U
  16791. #define WDR4_BILITERAL_HEIGHT_SIGMA
  16792. #define WDR4_BILITERAL_HEIGHT_SIGMA_MASK (0xfffff << 0 )
  16793. #define WDR4_BILITERAL_HEIGHT_SIGMA_SHIFT 0U
  16794. #define WDR4_BILITERAL_VALUE_SIGMA
  16795. #define WDR4_BILITERAL_VALUE_SIGMA_MASK (0xfffff << 0 )
  16796. #define WDR4_BILITERAL_VALUE_SIGMA_SHIFT 0U
  16797. #define WDR4_BLOCK_COL_FLAG
  16798. #define WDR4_BLOCK_COL_FLAG_MASK (0xffffffff << 0 )
  16799. #define WDR4_BLOCK_COL_FLAG_SHIFT 0U
  16800. #define WDR4_BLOCK_ROW_FLAG
  16801. #define WDR4_BLOCK_ROW_FLAG_MASK (0xffffffff << 0 )
  16802. #define WDR4_BLOCK_ROW_FLAG_SHIFT 0U
  16803. #define WDR4_FRAME_AVERAGE
  16804. #define WDR4_FRAME_AVERAGE_MASK (0xffffffff << 0 )
  16805. #define WDR4_FRAME_AVERAGE_SHIFT 0U
  16806. #define WDR4_FRAME_STD
  16807. #define WDR4_FRAME_STD_MASK (0xffffffff << 0 )
  16808. #define WDR4_FRAME_STD_SHIFT 0U
  16809. #define WDR4_HISTOGRAM_CURVE0_0
  16810. #define WDR4_HISTOGRAM_CURVE0_0_MASK (0x3ff << 20 )
  16811. #define WDR4_HISTOGRAM_CURVE0_0_SHIFT 20U
  16812. #define WDR4_HISTOGRAM_CURVE1
  16813. #define WDR4_HISTOGRAM_CURVE1_MASK (0xfffff << 0 )
  16814. #define WDR4_HISTOGRAM_CURVE1_SHIFT 0U
  16815. #define WDR4_HISTOGRAM_CURVE0_1
  16816. #define WDR4_HISTOGRAM_CURVE0_1_MASK (0x3ff << 20 )
  16817. #define WDR4_HISTOGRAM_CURVE0_1_SHIFT 20U
  16818. #define WDR4_HISTOGRAM_CURVE2
  16819. #define WDR4_HISTOGRAM_CURVE2_MASK (0xfffff << 0 )
  16820. #define WDR4_HISTOGRAM_CURVE2_SHIFT 0U
  16821. #define WDR4_HISTOGRAM_CURVE3_0
  16822. #define WDR4_HISTOGRAM_CURVE3_0_MASK (0x3ff << 20 )
  16823. #define WDR4_HISTOGRAM_CURVE3_0_SHIFT 20U
  16824. #define WDR4_HISTOGRAM_CURVE4
  16825. #define WDR4_HISTOGRAM_CURVE4_MASK (0xfffff << 0 )
  16826. #define WDR4_HISTOGRAM_CURVE4_SHIFT 0U
  16827. #define WDR4_HISTOGRAM_CURVE3_1
  16828. #define WDR4_HISTOGRAM_CURVE3_1_MASK (0x3ff << 20 )
  16829. #define WDR4_HISTOGRAM_CURVE3_1_SHIFT 20U
  16830. #define WDR4_HISTOGRAM_CURVE5
  16831. #define WDR4_HISTOGRAM_CURVE5_MASK (0xfffff << 0 )
  16832. #define WDR4_HISTOGRAM_CURVE5_SHIFT 0U
  16833. #define WDR4_HISTOGRAM_CURVE6_0
  16834. #define WDR4_HISTOGRAM_CURVE6_0_MASK (0x3ff << 20 )
  16835. #define WDR4_HISTOGRAM_CURVE6_0_SHIFT 20U
  16836. #define WDR4_HISTOGRAM_CURVE7
  16837. #define WDR4_HISTOGRAM_CURVE7_MASK (0xfffff << 0 )
  16838. #define WDR4_HISTOGRAM_CURVE7_SHIFT 0U
  16839. #define WDR4_HISTOGRAM_CURVE6_1
  16840. #define WDR4_HISTOGRAM_CURVE6_1_MASK (0x3ff << 20 )
  16841. #define WDR4_HISTOGRAM_CURVE6_1_SHIFT 20U
  16842. #define WDR4_HISTOGRAM_CURVE8
  16843. #define WDR4_HISTOGRAM_CURVE8_MASK (0xfffff << 0 )
  16844. #define WDR4_HISTOGRAM_CURVE8_SHIFT 0U
  16845. #define WDR4_HISTOGRAM_CURVE9_0
  16846. #define WDR4_HISTOGRAM_CURVE9_0_MASK (0x3ff << 20 )
  16847. #define WDR4_HISTOGRAM_CURVE9_0_SHIFT 20U
  16848. #define WDR4_HISTOGRAM_CURVE10
  16849. #define WDR4_HISTOGRAM_CURVE10_MASK (0xfffff << 0 )
  16850. #define WDR4_HISTOGRAM_CURVE10_SHIFT 0U
  16851. #define WDR4_HISTOGRAM_CURVE9_1
  16852. #define WDR4_HISTOGRAM_CURVE9_1_MASK (0x3ff << 20 )
  16853. #define WDR4_HISTOGRAM_CURVE9_1_SHIFT 20U
  16854. #define WDR4_HISTOGRAM_CURVE11
  16855. #define WDR4_HISTOGRAM_CURVE11_MASK (0xfffff << 0 )
  16856. #define WDR4_HISTOGRAM_CURVE11_SHIFT 0U
  16857. #define WDR4_HISTOGRAM_CURVE12_0
  16858. #define WDR4_HISTOGRAM_CURVE12_0_MASK (0x3ff << 20 )
  16859. #define WDR4_HISTOGRAM_CURVE12_0_SHIFT 20U
  16860. #define WDR4_HISTOGRAM_CURVE13
  16861. #define WDR4_HISTOGRAM_CURVE13_MASK (0xfffff << 0 )
  16862. #define WDR4_HISTOGRAM_CURVE13_SHIFT 0U
  16863. #define WDR4_HISTOGRAM_CURVE12_1
  16864. #define WDR4_HISTOGRAM_CURVE12_1_MASK (0x3ff << 20 )
  16865. #define WDR4_HISTOGRAM_CURVE12_1_SHIFT 20U
  16866. #define WDR4_HISTOGRAM_CURVE14
  16867. #define WDR4_HISTOGRAM_CURVE14_MASK (0xfffff << 0 )
  16868. #define WDR4_HISTOGRAM_CURVE14_SHIFT 0U
  16869. #define WDR4_HISTOGRAM_CURVE15_0
  16870. #define WDR4_HISTOGRAM_CURVE15_0_MASK (0x3ff << 20 )
  16871. #define WDR4_HISTOGRAM_CURVE15_0_SHIFT 20U
  16872. #define WDR4_HISTOGRAM_CURVE16
  16873. #define WDR4_HISTOGRAM_CURVE16_MASK (0xfffff << 0 )
  16874. #define WDR4_HISTOGRAM_CURVE16_SHIFT 0U
  16875. #define WDR4_HISTOGRAM_CURVE15_1
  16876. #define WDR4_HISTOGRAM_CURVE15_1_MASK (0x3ff << 20 )
  16877. #define WDR4_HISTOGRAM_CURVE15_1_SHIFT 20U
  16878. #define WDR4_HISTOGRAM_CURVE17
  16879. #define WDR4_HISTOGRAM_CURVE17_MASK (0xfffff << 0 )
  16880. #define WDR4_HISTOGRAM_CURVE17_SHIFT 0U
  16881. #define WDR4_HISTOGRAM_CURVE18_0
  16882. #define WDR4_HISTOGRAM_CURVE18_0_MASK (0x3ff << 20 )
  16883. #define WDR4_HISTOGRAM_CURVE18_0_SHIFT 20U
  16884. #define WDR4_HISTOGRAM_CURVE19
  16885. #define WDR4_HISTOGRAM_CURVE19_MASK (0xfffff << 0 )
  16886. #define WDR4_HISTOGRAM_CURVE19_SHIFT 0U
  16887. #define WDR4_HISTOGRAM_CURVE18_1
  16888. #define WDR4_HISTOGRAM_CURVE18_1_MASK (0x3ff << 20 )
  16889. #define WDR4_HISTOGRAM_CURVE18_1_SHIFT 20U
  16890. #define WDR4_ENTROPY_CONVERT0
  16891. #define WDR4_ENTROPY_CONVERT0_MASK (0x1ff << 18 )
  16892. #define WDR4_ENTROPY_CONVERT0_SHIFT 18U
  16893. #define WDR4_ENTROPY_CONVERT1
  16894. #define WDR4_ENTROPY_CONVERT1_MASK (0x1ff << 9 )
  16895. #define WDR4_ENTROPY_CONVERT1_SHIFT 9U
  16896. #define WDR4_ENTROPY_CONVERT2
  16897. #define WDR4_ENTROPY_CONVERT2_MASK (0x1ff << 0 )
  16898. #define WDR4_ENTROPY_CONVERT2_SHIFT 0U
  16899. #define WDR4_ENTROPY_CONVERT3
  16900. #define WDR4_ENTROPY_CONVERT3_MASK (0x1ff << 18 )
  16901. #define WDR4_ENTROPY_CONVERT3_SHIFT 18U
  16902. #define WDR4_ENTROPY_CONVERT4
  16903. #define WDR4_ENTROPY_CONVERT4_MASK (0x1ff << 9 )
  16904. #define WDR4_ENTROPY_CONVERT4_SHIFT 9U
  16905. #define WDR4_ENTROPY_CONVERT5
  16906. #define WDR4_ENTROPY_CONVERT5_MASK (0x1ff << 0 )
  16907. #define WDR4_ENTROPY_CONVERT5_SHIFT 0U
  16908. #define WDR4_ENTROPY_CONVERT6
  16909. #define WDR4_ENTROPY_CONVERT6_MASK (0x1ff << 18 )
  16910. #define WDR4_ENTROPY_CONVERT6_SHIFT 18U
  16911. #define WDR4_ENTROPY_CONVERT7
  16912. #define WDR4_ENTROPY_CONVERT7_MASK (0x1ff << 9 )
  16913. #define WDR4_ENTROPY_CONVERT7_SHIFT 9U
  16914. #define WDR4_ENTROPY_CONVERT8
  16915. #define WDR4_ENTROPY_CONVERT8_MASK (0x1ff << 0 )
  16916. #define WDR4_ENTROPY_CONVERT8_SHIFT 0U
  16917. #define WDR4_ENTROPY_CONVERT9
  16918. #define WDR4_ENTROPY_CONVERT9_MASK (0x1ff << 18 )
  16919. #define WDR4_ENTROPY_CONVERT9_SHIFT 18U
  16920. #define WDR4_ENTROPY_CONVERT10
  16921. #define WDR4_ENTROPY_CONVERT10_MASK (0x1ff << 9 )
  16922. #define WDR4_ENTROPY_CONVERT10_SHIFT 9U
  16923. #define WDR4_ENTROPY_CONVERT11
  16924. #define WDR4_ENTROPY_CONVERT11_MASK (0x1ff << 0 )
  16925. #define WDR4_ENTROPY_CONVERT11_SHIFT 0U
  16926. #define WDR4_ENTROPY_CONVERT12
  16927. #define WDR4_ENTROPY_CONVERT12_MASK (0x1ff << 18 )
  16928. #define WDR4_ENTROPY_CONVERT12_SHIFT 18U
  16929. #define WDR4_ENTROPY_CONVERT13
  16930. #define WDR4_ENTROPY_CONVERT13_MASK (0x1ff << 9 )
  16931. #define WDR4_ENTROPY_CONVERT13_SHIFT 9U
  16932. #define WDR4_ENTROPY_CONVERT14
  16933. #define WDR4_ENTROPY_CONVERT14_MASK (0x1ff << 0 )
  16934. #define WDR4_ENTROPY_CONVERT14_SHIFT 0U
  16935. #define WDR4_ENTROPY_CONVERT15
  16936. #define WDR4_ENTROPY_CONVERT15_MASK (0x1ff << 18 )
  16937. #define WDR4_ENTROPY_CONVERT15_SHIFT 18U
  16938. #define WDR4_ENTROPY_CONVERT16
  16939. #define WDR4_ENTROPY_CONVERT16_MASK (0x1ff << 9 )
  16940. #define WDR4_ENTROPY_CONVERT16_SHIFT 9U
  16941. #define WDR4_ENTROPY_CONVERT17
  16942. #define WDR4_ENTROPY_CONVERT17_MASK (0x1ff << 0 )
  16943. #define WDR4_ENTROPY_CONVERT17_SHIFT 0U
  16944. #define WDR4_ENTROPY_CONVERT18
  16945. #define WDR4_ENTROPY_CONVERT18_MASK (0x1ff << 9 )
  16946. #define WDR4_ENTROPY_CONVERT18_SHIFT 9U
  16947. #define WDR4_ENTROPY_CONVERT19
  16948. #define WDR4_ENTROPY_CONVERT19_MASK (0x1ff << 0 )
  16949. #define WDR4_ENTROPY_CONVERT19_SHIFT 0U
  16950. #define WDR4_GAMMA_PRE_CURVE0_0
  16951. #define WDR4_GAMMA_PRE_CURVE0_0_MASK (0x3ff << 20 )
  16952. #define WDR4_GAMMA_PRE_CURVE0_0_SHIFT 20U
  16953. #define WDR4_GAMMA_PRE_CURVE1
  16954. #define WDR4_GAMMA_PRE_CURVE1_MASK (0xfffff << 0 )
  16955. #define WDR4_GAMMA_PRE_CURVE1_SHIFT 0U
  16956. #define WDR4_GAMMA_PRE_CURVE0_1
  16957. #define WDR4_GAMMA_PRE_CURVE0_1_MASK (0x3ff << 20 )
  16958. #define WDR4_GAMMA_PRE_CURVE0_1_SHIFT 20U
  16959. #define WDR4_GAMMA_PRE_CURVE2
  16960. #define WDR4_GAMMA_PRE_CURVE2_MASK (0xfffff << 0 )
  16961. #define WDR4_GAMMA_PRE_CURVE2_SHIFT 0U
  16962. #define WDR4_GAMMA_PRE_CURVE3_0
  16963. #define WDR4_GAMMA_PRE_CURVE3_0_MASK (0x3ff << 20 )
  16964. #define WDR4_GAMMA_PRE_CURVE3_0_SHIFT 20U
  16965. #define WDR4_GAMMA_PRE_CURVE4
  16966. #define WDR4_GAMMA_PRE_CURVE4_MASK (0xfffff << 0 )
  16967. #define WDR4_GAMMA_PRE_CURVE4_SHIFT 0U
  16968. #define WDR4_GAMMA_PRE_CURVE3_1
  16969. #define WDR4_GAMMA_PRE_CURVE3_1_MASK (0x3ff << 20 )
  16970. #define WDR4_GAMMA_PRE_CURVE3_1_SHIFT 20U
  16971. #define WDR4_GAMMA_PRE_CURVE5
  16972. #define WDR4_GAMMA_PRE_CURVE5_MASK (0xfffff << 0 )
  16973. #define WDR4_GAMMA_PRE_CURVE5_SHIFT 0U
  16974. #define WDR4_GAMMA_PRE_CURVE6_0
  16975. #define WDR4_GAMMA_PRE_CURVE6_0_MASK (0x3ff << 20 )
  16976. #define WDR4_GAMMA_PRE_CURVE6_0_SHIFT 20U
  16977. #define WDR4_GAMMA_PRE_CURVE7
  16978. #define WDR4_GAMMA_PRE_CURVE7_MASK (0xfffff << 0 )
  16979. #define WDR4_GAMMA_PRE_CURVE7_SHIFT 0U
  16980. #define WDR4_GAMMA_PRE_CURVE6_1
  16981. #define WDR4_GAMMA_PRE_CURVE6_1_MASK (0x3ff << 20 )
  16982. #define WDR4_GAMMA_PRE_CURVE6_1_SHIFT 20U
  16983. #define WDR4_GAMMA_PRE_CURVE8
  16984. #define WDR4_GAMMA_PRE_CURVE8_MASK (0xfffff << 0 )
  16985. #define WDR4_GAMMA_PRE_CURVE8_SHIFT 0U
  16986. #define WDR4_GAMMA_PRE_CURVE9_0
  16987. #define WDR4_GAMMA_PRE_CURVE9_0_MASK (0x3ff << 20 )
  16988. #define WDR4_GAMMA_PRE_CURVE9_0_SHIFT 20U
  16989. #define WDR4_GAMMA_PRE_CURVE10
  16990. #define WDR4_GAMMA_PRE_CURVE10_MASK (0xfffff << 0 )
  16991. #define WDR4_GAMMA_PRE_CURVE10_SHIFT 0U
  16992. #define WDR4_GAMMA_PRE_CURVE9_1
  16993. #define WDR4_GAMMA_PRE_CURVE9_1_MASK (0x3ff << 20 )
  16994. #define WDR4_GAMMA_PRE_CURVE9_1_SHIFT 20U
  16995. #define WDR4_GAMMA_PRE_CURVE11
  16996. #define WDR4_GAMMA_PRE_CURVE11_MASK (0xfffff << 0 )
  16997. #define WDR4_GAMMA_PRE_CURVE11_SHIFT 0U
  16998. #define WDR4_GAMMA_PRE_CURVE12_0
  16999. #define WDR4_GAMMA_PRE_CURVE12_0_MASK (0x3ff << 20 )
  17000. #define WDR4_GAMMA_PRE_CURVE12_0_SHIFT 20U
  17001. #define WDR4_GAMMA_PRE_CURVE13
  17002. #define WDR4_GAMMA_PRE_CURVE13_MASK (0xfffff << 0 )
  17003. #define WDR4_GAMMA_PRE_CURVE13_SHIFT 0U
  17004. #define WDR4_GAMMA_PRE_CURVE12_1
  17005. #define WDR4_GAMMA_PRE_CURVE12_1_MASK (0x3ff << 20 )
  17006. #define WDR4_GAMMA_PRE_CURVE12_1_SHIFT 20U
  17007. #define WDR4_GAMMA_PRE_CURVE14
  17008. #define WDR4_GAMMA_PRE_CURVE14_MASK (0xfffff << 0 )
  17009. #define WDR4_GAMMA_PRE_CURVE14_SHIFT 0U
  17010. #define WDR4_GAMMA_PRE_CURVE15_0
  17011. #define WDR4_GAMMA_PRE_CURVE15_0_MASK (0x3ff << 20 )
  17012. #define WDR4_GAMMA_PRE_CURVE15_0_SHIFT 20U
  17013. #define WDR4_GAMMA_PRE_CURVE16
  17014. #define WDR4_GAMMA_PRE_CURVE16_MASK (0xfffff << 0 )
  17015. #define WDR4_GAMMA_PRE_CURVE16_SHIFT 0U
  17016. #define WDR4_GAMMA_PRE_CURVE15_1
  17017. #define WDR4_GAMMA_PRE_CURVE15_1_MASK (0x3ff << 20 )
  17018. #define WDR4_GAMMA_PRE_CURVE15_1_SHIFT 20U
  17019. #define WDR4_GAMMA_PRE_CURVE17
  17020. #define WDR4_GAMMA_PRE_CURVE17_MASK (0xfffff << 0 )
  17021. #define WDR4_GAMMA_PRE_CURVE17_SHIFT 0U
  17022. #define WDR4_GAMMA_PRE_CURVE18_0
  17023. #define WDR4_GAMMA_PRE_CURVE18_0_MASK (0x3ff << 20 )
  17024. #define WDR4_GAMMA_PRE_CURVE18_0_SHIFT 20U
  17025. #define WDR4_GAMMA_PRE_CURVE19
  17026. #define WDR4_GAMMA_PRE_CURVE19_MASK (0xfffff << 0 )
  17027. #define WDR4_GAMMA_PRE_CURVE19_SHIFT 0U
  17028. #define WDR4_GAMMA_PRE_CURVE18_1
  17029. #define WDR4_GAMMA_PRE_CURVE18_1_MASK (0x3ff << 20 )
  17030. #define WDR4_GAMMA_PRE_CURVE18_1_SHIFT 20U
  17031. #define WDR4_GAMMA_UP_CURVE0_0
  17032. #define WDR4_GAMMA_UP_CURVE0_0_MASK (0x3ff << 20 )
  17033. #define WDR4_GAMMA_UP_CURVE0_0_SHIFT 20U
  17034. #define WDR4_GAMMA_UP_CURVE1
  17035. #define WDR4_GAMMA_UP_CURVE1_MASK (0xfffff << 0 )
  17036. #define WDR4_GAMMA_UP_CURVE1_SHIFT 0U
  17037. #define WDR4_GAMMA_UP_CURVE0_1
  17038. #define WDR4_GAMMA_UP_CURVE0_1_MASK (0x3ff << 20 )
  17039. #define WDR4_GAMMA_UP_CURVE0_1_SHIFT 20U
  17040. #define WDR4_GAMMA_UP_CURVE2
  17041. #define WDR4_GAMMA_UP_CURVE2_MASK (0xfffff << 0 )
  17042. #define WDR4_GAMMA_UP_CURVE2_SHIFT 0U
  17043. #define WDR4_GAMMA_UP_CURVE3_0
  17044. #define WDR4_GAMMA_UP_CURVE3_0_MASK (0x3ff << 20 )
  17045. #define WDR4_GAMMA_UP_CURVE3_0_SHIFT 20U
  17046. #define WDR4_GAMMA_UP_CURVE4
  17047. #define WDR4_GAMMA_UP_CURVE4_MASK (0xfffff << 0 )
  17048. #define WDR4_GAMMA_UP_CURVE4_SHIFT 0U
  17049. #define WDR4_GAMMA_UP_CURVE3_1
  17050. #define WDR4_GAMMA_UP_CURVE3_1_MASK (0x3ff << 20 )
  17051. #define WDR4_GAMMA_UP_CURVE3_1_SHIFT 20U
  17052. #define WDR4_GAMMA_UP_CURVE5
  17053. #define WDR4_GAMMA_UP_CURVE5_MASK (0xfffff << 0 )
  17054. #define WDR4_GAMMA_UP_CURVE5_SHIFT 0U
  17055. #define WDR4_GAMMA_UP_CURVE6_0
  17056. #define WDR4_GAMMA_UP_CURVE6_0_MASK (0x3ff << 20 )
  17057. #define WDR4_GAMMA_UP_CURVE6_0_SHIFT 20U
  17058. #define WDR4_GAMMA_UP_CURVE7
  17059. #define WDR4_GAMMA_UP_CURVE7_MASK (0xfffff << 0 )
  17060. #define WDR4_GAMMA_UP_CURVE7_SHIFT 0U
  17061. #define WDR4_GAMMA_UP_CURVE6_1
  17062. #define WDR4_GAMMA_UP_CURVE6_1_MASK (0x3ff << 20 )
  17063. #define WDR4_GAMMA_UP_CURVE6_1_SHIFT 20U
  17064. #define WDR4_GAMMA_UP_CURVE8
  17065. #define WDR4_GAMMA_UP_CURVE8_MASK (0xfffff << 0 )
  17066. #define WDR4_GAMMA_UP_CURVE8_SHIFT 0U
  17067. #define WDR4_GAMMA_UP_CURVE9_0
  17068. #define WDR4_GAMMA_UP_CURVE9_0_MASK (0x3ff << 20 )
  17069. #define WDR4_GAMMA_UP_CURVE9_0_SHIFT 20U
  17070. #define WDR4_GAMMA_UP_CURVE10
  17071. #define WDR4_GAMMA_UP_CURVE10_MASK (0xfffff << 0 )
  17072. #define WDR4_GAMMA_UP_CURVE10_SHIFT 0U
  17073. #define WDR4_GAMMA_UP_CURVE9_1
  17074. #define WDR4_GAMMA_UP_CURVE9_1_MASK (0x3ff << 20 )
  17075. #define WDR4_GAMMA_UP_CURVE9_1_SHIFT 20U
  17076. #define WDR4_GAMMA_UP_CURVE11
  17077. #define WDR4_GAMMA_UP_CURVE11_MASK (0xfffff << 0 )
  17078. #define WDR4_GAMMA_UP_CURVE11_SHIFT 0U
  17079. #define WDR4_GAMMA_UP_CURVE12_0
  17080. #define WDR4_GAMMA_UP_CURVE12_0_MASK (0x3ff << 20 )
  17081. #define WDR4_GAMMA_UP_CURVE12_0_SHIFT 20U
  17082. #define WDR4_GAMMA_UP_CURVE13
  17083. #define WDR4_GAMMA_UP_CURVE13_MASK (0xfffff << 0 )
  17084. #define WDR4_GAMMA_UP_CURVE13_SHIFT 0U
  17085. #define WDR4_GAMMA_UP_CURVE12_1
  17086. #define WDR4_GAMMA_UP_CURVE12_1_MASK (0x3ff << 20 )
  17087. #define WDR4_GAMMA_UP_CURVE12_1_SHIFT 20U
  17088. #define WDR4_GAMMA_UP_CURVE14
  17089. #define WDR4_GAMMA_UP_CURVE14_MASK (0xfffff << 0 )
  17090. #define WDR4_GAMMA_UP_CURVE14_SHIFT 0U
  17091. #define WDR4_GAMMA_UP_CURVE15_0
  17092. #define WDR4_GAMMA_UP_CURVE15_0_MASK (0x3ff << 20 )
  17093. #define WDR4_GAMMA_UP_CURVE15_0_SHIFT 20U
  17094. #define WDR4_GAMMA_UP_CURVE16
  17095. #define WDR4_GAMMA_UP_CURVE16_MASK (0xfffff << 0 )
  17096. #define WDR4_GAMMA_UP_CURVE16_SHIFT 0U
  17097. #define WDR4_GAMMA_UP_CURVE15_1
  17098. #define WDR4_GAMMA_UP_CURVE15_1_MASK (0x3ff << 20 )
  17099. #define WDR4_GAMMA_UP_CURVE15_1_SHIFT 20U
  17100. #define WDR4_GAMMA_UP_CURVE17
  17101. #define WDR4_GAMMA_UP_CURVE17_MASK (0xfffff << 0 )
  17102. #define WDR4_GAMMA_UP_CURVE17_SHIFT 0U
  17103. #define WDR4_GAMMA_UP_CURVE18_0
  17104. #define WDR4_GAMMA_UP_CURVE18_0_MASK (0x3ff << 20 )
  17105. #define WDR4_GAMMA_UP_CURVE18_0_SHIFT 20U
  17106. #define WDR4_GAMMA_UP_CURVE19
  17107. #define WDR4_GAMMA_UP_CURVE19_MASK (0xfffff << 0 )
  17108. #define WDR4_GAMMA_UP_CURVE19_SHIFT 0U
  17109. #define WDR4_GAMMA_UP_CURVE18_1
  17110. #define WDR4_GAMMA_UP_CURVE18_1_MASK (0x3ff << 20 )
  17111. #define WDR4_GAMMA_UP_CURVE18_1_SHIFT 20U
  17112. #define WDR4_GAMMA_DOWN_CURVE0
  17113. #define WDR4_GAMMA_DOWN_CURVE0_MASK (0x3ff << 20 )
  17114. #define WDR4_GAMMA_DOWN_CURVE0_SHIFT 20U
  17115. #define WDR4_GAMMA_DOWN_CURVE1
  17116. #define WDR4_GAMMA_DOWN_CURVE1_MASK (0x3ff << 10 )
  17117. #define WDR4_GAMMA_DOWN_CURVE1_SHIFT 10U
  17118. #define WDR4_GAMMA_DOWN_CURVE2
  17119. #define WDR4_GAMMA_DOWN_CURVE2_MASK (0x3ff << 0 )
  17120. #define WDR4_GAMMA_DOWN_CURVE2_SHIFT 0U
  17121. #define WDR4_GAMMA_DOWN_CURVE3
  17122. #define WDR4_GAMMA_DOWN_CURVE3_MASK (0x3ff << 20 )
  17123. #define WDR4_GAMMA_DOWN_CURVE3_SHIFT 20U
  17124. #define WDR4_GAMMA_DOWN_CURVE4
  17125. #define WDR4_GAMMA_DOWN_CURVE4_MASK (0x3ff << 10 )
  17126. #define WDR4_GAMMA_DOWN_CURVE4_SHIFT 10U
  17127. #define WDR4_GAMMA_DOWN_CURVE5
  17128. #define WDR4_GAMMA_DOWN_CURVE5_MASK (0x3ff << 0 )
  17129. #define WDR4_GAMMA_DOWN_CURVE5_SHIFT 0U
  17130. #define WDR4_GAMMA_DOWN_CURVE6
  17131. #define WDR4_GAMMA_DOWN_CURVE6_MASK (0x3ff << 20 )
  17132. #define WDR4_GAMMA_DOWN_CURVE6_SHIFT 20U
  17133. #define WDR4_GAMMA_DOWN_CURVE7
  17134. #define WDR4_GAMMA_DOWN_CURVE7_MASK (0x3ff << 10 )
  17135. #define WDR4_GAMMA_DOWN_CURVE7_SHIFT 10U
  17136. #define WDR4_GAMMA_DOWN_CURVE8
  17137. #define WDR4_GAMMA_DOWN_CURVE8_MASK (0x3ff << 0 )
  17138. #define WDR4_GAMMA_DOWN_CURVE8_SHIFT 0U
  17139. #define WDR4_GAMMA_DOWN_CURVE9
  17140. #define WDR4_GAMMA_DOWN_CURVE9_MASK (0x3ff << 20 )
  17141. #define WDR4_GAMMA_DOWN_CURVE9_SHIFT 20U
  17142. #define WDR4_GAMMA_DOWN_CURVE10
  17143. #define WDR4_GAMMA_DOWN_CURVE10_MASK (0x3ff << 10 )
  17144. #define WDR4_GAMMA_DOWN_CURVE10_SHIFT 10U
  17145. #define WDR4_GAMMA_DOWN_CURVE11
  17146. #define WDR4_GAMMA_DOWN_CURVE11_MASK (0x3ff << 0 )
  17147. #define WDR4_GAMMA_DOWN_CURVE11_SHIFT 0U
  17148. #define WDR4_GAMMA_DOWN_CURVE12
  17149. #define WDR4_GAMMA_DOWN_CURVE12_MASK (0x3ff << 20 )
  17150. #define WDR4_GAMMA_DOWN_CURVE12_SHIFT 20U
  17151. #define WDR4_GAMMA_DOWN_CURVE13
  17152. #define WDR4_GAMMA_DOWN_CURVE13_MASK (0x3ff << 10 )
  17153. #define WDR4_GAMMA_DOWN_CURVE13_SHIFT 10U
  17154. #define WDR4_GAMMA_DOWN_CURVE14
  17155. #define WDR4_GAMMA_DOWN_CURVE14_MASK (0x3ff << 0 )
  17156. #define WDR4_GAMMA_DOWN_CURVE14_SHIFT 0U
  17157. #define WDR4_GAMMA_DOWN_CURVE15
  17158. #define WDR4_GAMMA_DOWN_CURVE15_MASK (0x3ff << 20 )
  17159. #define WDR4_GAMMA_DOWN_CURVE15_SHIFT 20U
  17160. #define WDR4_GAMMA_DOWN_CURVE16
  17161. #define WDR4_GAMMA_DOWN_CURVE16_MASK (0x3ff << 10 )
  17162. #define WDR4_GAMMA_DOWN_CURVE16_SHIFT 10U
  17163. #define WDR4_GAMMA_DOWN_CURVE17
  17164. #define WDR4_GAMMA_DOWN_CURVE17_MASK (0x3ff << 0 )
  17165. #define WDR4_GAMMA_DOWN_CURVE17_SHIFT 0U
  17166. #define WDR4_GAMMA_DOWN_CURVE18
  17167. #define WDR4_GAMMA_DOWN_CURVE18_MASK (0x3ff << 10 )
  17168. #define WDR4_GAMMA_DOWN_CURVE18_SHIFT 10U
  17169. #define WDR4_GAMMA_DOWN_CURVE19
  17170. #define WDR4_GAMMA_DOWN_CURVE19_MASK (0x3ff << 0 )
  17171. #define WDR4_GAMMA_DOWN_CURVE19_SHIFT 0U
  17172. #define WDR4_DISTANCE_WEIGHT_CURVE0
  17173. #define WDR4_DISTANCE_WEIGHT_CURVE0_MASK (0x7f << 21 )
  17174. #define WDR4_DISTANCE_WEIGHT_CURVE0_SHIFT 21U
  17175. #define WDR4_DISTANCE_WEIGHT_CURVE1
  17176. #define WDR4_DISTANCE_WEIGHT_CURVE1_MASK (0x7f << 14 )
  17177. #define WDR4_DISTANCE_WEIGHT_CURVE1_SHIFT 14U
  17178. #define WDR4_DISTANCE_WEIGHT_CURVE2
  17179. #define WDR4_DISTANCE_WEIGHT_CURVE2_MASK (0x7f << 7 )
  17180. #define WDR4_DISTANCE_WEIGHT_CURVE2_SHIFT 7U
  17181. #define WDR4_DISTANCE_WEIGHT_CURVE3
  17182. #define WDR4_DISTANCE_WEIGHT_CURVE3_MASK (0x7f << 0 )
  17183. #define WDR4_DISTANCE_WEIGHT_CURVE3_SHIFT 0U
  17184. #define WDR4_DISTANCE_WEIGHT_CURVE4
  17185. #define WDR4_DISTANCE_WEIGHT_CURVE4_MASK (0x7f << 21 )
  17186. #define WDR4_DISTANCE_WEIGHT_CURVE4_SHIFT 21U
  17187. #define WDR4_DISTANCE_WEIGHT_CURVE5
  17188. #define WDR4_DISTANCE_WEIGHT_CURVE5_MASK (0x7f << 14 )
  17189. #define WDR4_DISTANCE_WEIGHT_CURVE5_SHIFT 14U
  17190. #define WDR4_DISTANCE_WEIGHT_CURVE6
  17191. #define WDR4_DISTANCE_WEIGHT_CURVE6_MASK (0x7f << 7 )
  17192. #define WDR4_DISTANCE_WEIGHT_CURVE6_SHIFT 7U
  17193. #define WDR4_DISTANCE_WEIGHT_CURVE7
  17194. #define WDR4_DISTANCE_WEIGHT_CURVE7_MASK (0x7f << 0 )
  17195. #define WDR4_DISTANCE_WEIGHT_CURVE7_SHIFT 0U
  17196. #define WDR4_DISTANCE_WEIGHT_CURVE8
  17197. #define WDR4_DISTANCE_WEIGHT_CURVE8_MASK (0x7f << 21 )
  17198. #define WDR4_DISTANCE_WEIGHT_CURVE8_SHIFT 21U
  17199. #define WDR4_DISTANCE_WEIGHT_CURVE9
  17200. #define WDR4_DISTANCE_WEIGHT_CURVE9_MASK (0x7f << 14 )
  17201. #define WDR4_DISTANCE_WEIGHT_CURVE9_SHIFT 14U
  17202. #define WDR4_DISTANCE_WEIGHT_CURVE10
  17203. #define WDR4_DISTANCE_WEIGHT_CURVE10_MASK (0x7f << 7 )
  17204. #define WDR4_DISTANCE_WEIGHT_CURVE10_SHIFT 7U
  17205. #define WDR4_DISTANCE_WEIGHT_CURVE11
  17206. #define WDR4_DISTANCE_WEIGHT_CURVE11_MASK (0x7f << 0 )
  17207. #define WDR4_DISTANCE_WEIGHT_CURVE11_SHIFT 0U
  17208. #define WDR4_DISTANCE_WEIGHT_CURVE12
  17209. #define WDR4_DISTANCE_WEIGHT_CURVE12_MASK (0x7f << 21 )
  17210. #define WDR4_DISTANCE_WEIGHT_CURVE12_SHIFT 21U
  17211. #define WDR4_DISTANCE_WEIGHT_CURVE13
  17212. #define WDR4_DISTANCE_WEIGHT_CURVE13_MASK (0x7f << 14 )
  17213. #define WDR4_DISTANCE_WEIGHT_CURVE13_SHIFT 14U
  17214. #define WDR4_DISTANCE_WEIGHT_CURVE14
  17215. #define WDR4_DISTANCE_WEIGHT_CURVE14_MASK (0x7f << 7 )
  17216. #define WDR4_DISTANCE_WEIGHT_CURVE14_SHIFT 7U
  17217. #define WDR4_DISTANCE_WEIGHT_CURVE15
  17218. #define WDR4_DISTANCE_WEIGHT_CURVE15_MASK (0x7f << 0 )
  17219. #define WDR4_DISTANCE_WEIGHT_CURVE15_SHIFT 0U
  17220. #define WDR4_DISTANCE_WEIGHT_CURVE16
  17221. #define WDR4_DISTANCE_WEIGHT_CURVE16_MASK (0x7f << 21 )
  17222. #define WDR4_DISTANCE_WEIGHT_CURVE16_SHIFT 21U
  17223. #define WDR4_DISTANCE_WEIGHT_CURVE17
  17224. #define WDR4_DISTANCE_WEIGHT_CURVE17_MASK (0x7f << 14 )
  17225. #define WDR4_DISTANCE_WEIGHT_CURVE17_SHIFT 14U
  17226. #define WDR4_DISTANCE_WEIGHT_CURVE18
  17227. #define WDR4_DISTANCE_WEIGHT_CURVE18_MASK (0x7f << 7 )
  17228. #define WDR4_DISTANCE_WEIGHT_CURVE18_SHIFT 7U
  17229. #define WDR4_DISTANCE_WEIGHT_CURVE19
  17230. #define WDR4_DISTANCE_WEIGHT_CURVE19_MASK (0x7f << 0 )
  17231. #define WDR4_DISTANCE_WEIGHT_CURVE19_SHIFT 0U
  17232. #define WDR4_DIFFERENCE_WEIGHT_CURVE0
  17233. #define WDR4_DIFFERENCE_WEIGHT_CURVE0_MASK (0x7f << 21 )
  17234. #define WDR4_DIFFERENCE_WEIGHT_CURVE0_SHIFT 21U
  17235. #define WDR4_DIFFERENCE_WEIGHT_CURVE1
  17236. #define WDR4_DIFFERENCE_WEIGHT_CURVE1_MASK (0x7f << 14 )
  17237. #define WDR4_DIFFERENCE_WEIGHT_CURVE1_SHIFT 14U
  17238. #define WDR4_DIFFERENCE_WEIGHT_CURVE2
  17239. #define WDR4_DIFFERENCE_WEIGHT_CURVE2_MASK (0x7f << 7 )
  17240. #define WDR4_DIFFERENCE_WEIGHT_CURVE2_SHIFT 7U
  17241. #define WDR4_DIFFERENCE_WEIGHT_CURVE3
  17242. #define WDR4_DIFFERENCE_WEIGHT_CURVE3_MASK (0x7f << 0 )
  17243. #define WDR4_DIFFERENCE_WEIGHT_CURVE3_SHIFT 0U
  17244. #define WDR4_DIFFERENCE_WEIGHT_CURVE4
  17245. #define WDR4_DIFFERENCE_WEIGHT_CURVE4_MASK (0x7f << 21 )
  17246. #define WDR4_DIFFERENCE_WEIGHT_CURVE4_SHIFT 21U
  17247. #define WDR4_DIFFERENCE_WEIGHT_CURVE5
  17248. #define WDR4_DIFFERENCE_WEIGHT_CURVE5_MASK (0x7f << 14 )
  17249. #define WDR4_DIFFERENCE_WEIGHT_CURVE5_SHIFT 14U
  17250. #define WDR4_DIFFERENCE_WEIGHT_CURVE6
  17251. #define WDR4_DIFFERENCE_WEIGHT_CURVE6_MASK (0x7f << 7 )
  17252. #define WDR4_DIFFERENCE_WEIGHT_CURVE6_SHIFT 7U
  17253. #define WDR4_DIFFERENCE_WEIGHT_CURVE7
  17254. #define WDR4_DIFFERENCE_WEIGHT_CURVE7_MASK (0x7f << 0 )
  17255. #define WDR4_DIFFERENCE_WEIGHT_CURVE7_SHIFT 0U
  17256. #define WDR4_DIFFERENCE_WEIGHT_CURVE8
  17257. #define WDR4_DIFFERENCE_WEIGHT_CURVE8_MASK (0x7f << 21 )
  17258. #define WDR4_DIFFERENCE_WEIGHT_CURVE8_SHIFT 21U
  17259. #define WDR4_DIFFERENCE_WEIGHT_CURVE9
  17260. #define WDR4_DIFFERENCE_WEIGHT_CURVE9_MASK (0x7f << 14 )
  17261. #define WDR4_DIFFERENCE_WEIGHT_CURVE9_SHIFT 14U
  17262. #define WDR4_DIFFERENCE_WEIGHT_CURVE10
  17263. #define WDR4_DIFFERENCE_WEIGHT_CURVE10_MASK (0x7f << 7 )
  17264. #define WDR4_DIFFERENCE_WEIGHT_CURVE10_SHIFT 7U
  17265. #define WDR4_DIFFERENCE_WEIGHT_CURVE11
  17266. #define WDR4_DIFFERENCE_WEIGHT_CURVE11_MASK (0x7f << 0 )
  17267. #define WDR4_DIFFERENCE_WEIGHT_CURVE11_SHIFT 0U
  17268. #define WDR4_DIFFERENCE_WEIGHT_CURVE12
  17269. #define WDR4_DIFFERENCE_WEIGHT_CURVE12_MASK (0x7f << 21 )
  17270. #define WDR4_DIFFERENCE_WEIGHT_CURVE12_SHIFT 21U
  17271. #define WDR4_DIFFERENCE_WEIGHT_CURVE13
  17272. #define WDR4_DIFFERENCE_WEIGHT_CURVE13_MASK (0x7f << 14 )
  17273. #define WDR4_DIFFERENCE_WEIGHT_CURVE13_SHIFT 14U
  17274. #define WDR4_DIFFERENCE_WEIGHT_CURVE14
  17275. #define WDR4_DIFFERENCE_WEIGHT_CURVE14_MASK (0x7f << 7 )
  17276. #define WDR4_DIFFERENCE_WEIGHT_CURVE14_SHIFT 7U
  17277. #define WDR4_DIFFERENCE_WEIGHT_CURVE15
  17278. #define WDR4_DIFFERENCE_WEIGHT_CURVE15_MASK (0x7f << 0 )
  17279. #define WDR4_DIFFERENCE_WEIGHT_CURVE15_SHIFT 0U
  17280. #define WDR4_DIFFERENCE_WEIGHT_CURVE16
  17281. #define WDR4_DIFFERENCE_WEIGHT_CURVE16_MASK (0x7f << 21 )
  17282. #define WDR4_DIFFERENCE_WEIGHT_CURVE16_SHIFT 21U
  17283. #define WDR4_DIFFERENCE_WEIGHT_CURVE17
  17284. #define WDR4_DIFFERENCE_WEIGHT_CURVE17_MASK (0x7f << 14 )
  17285. #define WDR4_DIFFERENCE_WEIGHT_CURVE17_SHIFT 14U
  17286. #define WDR4_DIFFERENCE_WEIGHT_CURVE18
  17287. #define WDR4_DIFFERENCE_WEIGHT_CURVE18_MASK (0x7f << 7 )
  17288. #define WDR4_DIFFERENCE_WEIGHT_CURVE18_SHIFT 7U
  17289. #define WDR4_DIFFERENCE_WEIGHT_CURVE19
  17290. #define WDR4_DIFFERENCE_WEIGHT_CURVE19_MASK (0x7f << 0 )
  17291. #define WDR4_DIFFERENCE_WEIGHT_CURVE19_SHIFT 0U
  17292. #define WDR4_GLOBAL_CURVE_INVERT0
  17293. #define WDR4_GLOBAL_CURVE_INVERT0_MASK (0xfff << 12 )
  17294. #define WDR4_GLOBAL_CURVE_INVERT0_SHIFT 12U
  17295. #define WDR4_GLOBAL_CURVE_INVERT1
  17296. #define WDR4_GLOBAL_CURVE_INVERT1_MASK (0xfff << 0 )
  17297. #define WDR4_GLOBAL_CURVE_INVERT1_SHIFT 0U
  17298. #define WDR4_GLOBAL_CURVE_INVERT2
  17299. #define WDR4_GLOBAL_CURVE_INVERT2_MASK (0xfff << 12 )
  17300. #define WDR4_GLOBAL_CURVE_INVERT2_SHIFT 12U
  17301. #define WDR4_GLOBAL_CURVE_INVERT3
  17302. #define WDR4_GLOBAL_CURVE_INVERT3_MASK (0xfff << 0 )
  17303. #define WDR4_GLOBAL_CURVE_INVERT3_SHIFT 0U
  17304. #define WDR4_GLOBAL_CURVE_INVERT4
  17305. #define WDR4_GLOBAL_CURVE_INVERT4_MASK (0xfff << 12 )
  17306. #define WDR4_GLOBAL_CURVE_INVERT4_SHIFT 12U
  17307. #define WDR4_GLOBAL_CURVE_INVERT5
  17308. #define WDR4_GLOBAL_CURVE_INVERT5_MASK (0xfff << 0 )
  17309. #define WDR4_GLOBAL_CURVE_INVERT5_SHIFT 0U
  17310. #define WDR4_GLOBAL_CURVE_INVERT6
  17311. #define WDR4_GLOBAL_CURVE_INVERT6_MASK (0xfff << 12 )
  17312. #define WDR4_GLOBAL_CURVE_INVERT6_SHIFT 12U
  17313. #define WDR4_GLOBAL_CURVE_INVERT7
  17314. #define WDR4_GLOBAL_CURVE_INVERT7_MASK (0xfff << 0 )
  17315. #define WDR4_GLOBAL_CURVE_INVERT7_SHIFT 0U
  17316. #define WDR4_GLOBAL_CURVE_INVERT8
  17317. #define WDR4_GLOBAL_CURVE_INVERT8_MASK (0xfff << 12 )
  17318. #define WDR4_GLOBAL_CURVE_INVERT8_SHIFT 12U
  17319. #define WDR4_GLOBAL_CURVE_INVERT9
  17320. #define WDR4_GLOBAL_CURVE_INVERT9_MASK (0xfff << 0 )
  17321. #define WDR4_GLOBAL_CURVE_INVERT9_SHIFT 0U
  17322. #define WDR4_GLOBAL_CURVE_INVERT10
  17323. #define WDR4_GLOBAL_CURVE_INVERT10_MASK (0xfff << 12 )
  17324. #define WDR4_GLOBAL_CURVE_INVERT10_SHIFT 12U
  17325. #define WDR4_GLOBAL_CURVE_INVERT11
  17326. #define WDR4_GLOBAL_CURVE_INVERT11_MASK (0xfff << 0 )
  17327. #define WDR4_GLOBAL_CURVE_INVERT11_SHIFT 0U
  17328. #define WDR4_GLOBAL_CURVE_INVERT12
  17329. #define WDR4_GLOBAL_CURVE_INVERT12_MASK (0xfff << 12 )
  17330. #define WDR4_GLOBAL_CURVE_INVERT12_SHIFT 12U
  17331. #define WDR4_GLOBAL_CURVE_INVERT13
  17332. #define WDR4_GLOBAL_CURVE_INVERT13_MASK (0xfff << 0 )
  17333. #define WDR4_GLOBAL_CURVE_INVERT13_SHIFT 0U
  17334. #define WDR4_GLOBAL_CURVE_INVERT14
  17335. #define WDR4_GLOBAL_CURVE_INVERT14_MASK (0xfff << 12 )
  17336. #define WDR4_GLOBAL_CURVE_INVERT14_SHIFT 12U
  17337. #define WDR4_GLOBAL_CURVE_INVERT15
  17338. #define WDR4_GLOBAL_CURVE_INVERT15_MASK (0xfff << 0 )
  17339. #define WDR4_GLOBAL_CURVE_INVERT15_SHIFT 0U
  17340. #define WDR4_GLOBAL_CURVE_INVERT16
  17341. #define WDR4_GLOBAL_CURVE_INVERT16_MASK (0xfff << 12 )
  17342. #define WDR4_GLOBAL_CURVE_INVERT16_SHIFT 12U
  17343. #define WDR4_GLOBAL_CURVE_INVERT17
  17344. #define WDR4_GLOBAL_CURVE_INVERT17_MASK (0xfff << 0 )
  17345. #define WDR4_GLOBAL_CURVE_INVERT17_SHIFT 0U
  17346. #define WDR4_GLOBAL_CURVE_INVERT18
  17347. #define WDR4_GLOBAL_CURVE_INVERT18_MASK (0xfff << 12 )
  17348. #define WDR4_GLOBAL_CURVE_INVERT18_SHIFT 12U
  17349. #define WDR4_GLOBAL_CURVE_INVERT19
  17350. #define WDR4_GLOBAL_CURVE_INVERT19_MASK (0xfff << 0 )
  17351. #define WDR4_GLOBAL_CURVE_INVERT19_SHIFT 0U
  17352. #define WDR4_LINEAR_CURVE_INVERT0_0
  17353. #define WDR4_LINEAR_CURVE_INVERT0_0_MASK (0x1ff << 18 )
  17354. #define WDR4_LINEAR_CURVE_INVERT0_0_SHIFT 18U
  17355. #define WDR4_LINEAR_CURVE_INVERT1
  17356. #define WDR4_LINEAR_CURVE_INVERT1_MASK (0x3ffff << 0 )
  17357. #define WDR4_LINEAR_CURVE_INVERT1_SHIFT 0U
  17358. #define WDR4_LINEAR_CURVE_INVERT0_1
  17359. #define WDR4_LINEAR_CURVE_INVERT0_1_MASK (0x1ff << 18 )
  17360. #define WDR4_LINEAR_CURVE_INVERT0_1_SHIFT 18U
  17361. #define WDR4_LINEAR_CURVE_INVERT2
  17362. #define WDR4_LINEAR_CURVE_INVERT2_MASK (0x3ffff << 0 )
  17363. #define WDR4_LINEAR_CURVE_INVERT2_SHIFT 0U
  17364. #define WDR4_LINEAR_CURVE_INVERT3_0
  17365. #define WDR4_LINEAR_CURVE_INVERT3_0_MASK (0x1ff << 18 )
  17366. #define WDR4_LINEAR_CURVE_INVERT3_0_SHIFT 18U
  17367. #define WDR4_LINEAR_CURVE_INVERT4
  17368. #define WDR4_LINEAR_CURVE_INVERT4_MASK (0x3ffff << 0 )
  17369. #define WDR4_LINEAR_CURVE_INVERT4_SHIFT 0U
  17370. #define WDR4_LINEAR_CURVE_INVERT3_1
  17371. #define WDR4_LINEAR_CURVE_INVERT3_1_MASK (0x1ff << 18 )
  17372. #define WDR4_LINEAR_CURVE_INVERT3_1_SHIFT 18U
  17373. #define WDR4_LINEAR_CURVE_INVERT5
  17374. #define WDR4_LINEAR_CURVE_INVERT5_MASK (0x3ffff << 0 )
  17375. #define WDR4_LINEAR_CURVE_INVERT5_SHIFT 0U
  17376. #define WDR4_LINEAR_CURVE_INVERT6_0
  17377. #define WDR4_LINEAR_CURVE_INVERT6_0_MASK (0x1ff << 18 )
  17378. #define WDR4_LINEAR_CURVE_INVERT6_0_SHIFT 18U
  17379. #define WDR4_LINEAR_CURVE_INVERT7
  17380. #define WDR4_LINEAR_CURVE_INVERT7_MASK (0x3ffff << 0 )
  17381. #define WDR4_LINEAR_CURVE_INVERT7_SHIFT 0U
  17382. #define WDR4_LINEAR_CURVE_INVERT6_1
  17383. #define WDR4_LINEAR_CURVE_INVERT6_1_MASK (0x1ff << 18 )
  17384. #define WDR4_LINEAR_CURVE_INVERT6_1_SHIFT 18U
  17385. #define WDR4_LINEAR_CURVE_INVERT8
  17386. #define WDR4_LINEAR_CURVE_INVERT8_MASK (0x3ffff << 0 )
  17387. #define WDR4_LINEAR_CURVE_INVERT8_SHIFT 0U
  17388. #define WDR4_LINEAR_CURVE_INVERT9_0
  17389. #define WDR4_LINEAR_CURVE_INVERT9_0_MASK (0x1ff << 18 )
  17390. #define WDR4_LINEAR_CURVE_INVERT9_0_SHIFT 18U
  17391. #define WDR4_LINEAR_CURVE_INVERT10
  17392. #define WDR4_LINEAR_CURVE_INVERT10_MASK (0x3ffff << 0 )
  17393. #define WDR4_LINEAR_CURVE_INVERT10_SHIFT 0U
  17394. #define WDR4_LINEAR_CURVE_INVERT9_1
  17395. #define WDR4_LINEAR_CURVE_INVERT9_1_MASK (0x1ff << 18 )
  17396. #define WDR4_LINEAR_CURVE_INVERT9_1_SHIFT 18U
  17397. #define WDR4_LINEAR_CURVE_INVERT11
  17398. #define WDR4_LINEAR_CURVE_INVERT11_MASK (0x3ffff << 0 )
  17399. #define WDR4_LINEAR_CURVE_INVERT11_SHIFT 0U
  17400. #define WDR4_LINEAR_CURVE_INVERT12_0
  17401. #define WDR4_LINEAR_CURVE_INVERT12_0_MASK (0x1ff << 18 )
  17402. #define WDR4_LINEAR_CURVE_INVERT12_0_SHIFT 18U
  17403. #define WDR4_LINEAR_CURVE_INVERT13
  17404. #define WDR4_LINEAR_CURVE_INVERT13_MASK (0x3ffff << 0 )
  17405. #define WDR4_LINEAR_CURVE_INVERT13_SHIFT 0U
  17406. #define WDR4_LINEAR_CURVE_INVERT12_1
  17407. #define WDR4_LINEAR_CURVE_INVERT12_1_MASK (0x1ff << 18 )
  17408. #define WDR4_LINEAR_CURVE_INVERT12_1_SHIFT 18U
  17409. #define WDR4_LINEAR_CURVE_INVERT14
  17410. #define WDR4_LINEAR_CURVE_INVERT14_MASK (0x3ffff << 0 )
  17411. #define WDR4_LINEAR_CURVE_INVERT14_SHIFT 0U
  17412. #define WDR4_LINEAR_CURVE_INVERT15_0
  17413. #define WDR4_LINEAR_CURVE_INVERT15_0_MASK (0x1ff << 18 )
  17414. #define WDR4_LINEAR_CURVE_INVERT15_0_SHIFT 18U
  17415. #define WDR4_LINEAR_CURVE_INVERT16
  17416. #define WDR4_LINEAR_CURVE_INVERT16_MASK (0x3ffff << 0 )
  17417. #define WDR4_LINEAR_CURVE_INVERT16_SHIFT 0U
  17418. #define WDR4_LINEAR_CURVE_INVERT15_1
  17419. #define WDR4_LINEAR_CURVE_INVERT15_1_MASK (0x1ff << 18 )
  17420. #define WDR4_LINEAR_CURVE_INVERT15_1_SHIFT 18U
  17421. #define WDR4_LINEAR_CURVE_INVERT17
  17422. #define WDR4_LINEAR_CURVE_INVERT17_MASK (0x3ffff << 0 )
  17423. #define WDR4_LINEAR_CURVE_INVERT17_SHIFT 0U
  17424. #define WDR4_LINEAR_CURVE_INVERT18_0
  17425. #define WDR4_LINEAR_CURVE_INVERT18_0_MASK (0x1ff << 18 )
  17426. #define WDR4_LINEAR_CURVE_INVERT18_0_SHIFT 18U
  17427. #define WDR4_LINEAR_CURVE_INVERT19
  17428. #define WDR4_LINEAR_CURVE_INVERT19_MASK (0x3ffff << 0 )
  17429. #define WDR4_LINEAR_CURVE_INVERT19_SHIFT 0U
  17430. #define WDR4_LINEAR_CURVE_INVERT18_1
  17431. #define WDR4_LINEAR_CURVE_INVERT18_1_MASK (0x1ff << 18 )
  17432. #define WDR4_LINEAR_CURVE_INVERT18_1_SHIFT 18U
  17433. #define WDR4_SMOOTH_INVERT_CURVE0
  17434. #define WDR4_SMOOTH_INVERT_CURVE0_MASK (0xff << 24 )
  17435. #define WDR4_SMOOTH_INVERT_CURVE0_SHIFT 24U
  17436. #define WDR4_SMOOTH_INVERT_CURVE1
  17437. #define WDR4_SMOOTH_INVERT_CURVE1_MASK (0xff << 16 )
  17438. #define WDR4_SMOOTH_INVERT_CURVE1_SHIFT 16U
  17439. #define WDR4_SMOOTH_INVERT_CURVE2
  17440. #define WDR4_SMOOTH_INVERT_CURVE2_MASK (0xff << 8 )
  17441. #define WDR4_SMOOTH_INVERT_CURVE2_SHIFT 8U
  17442. #define WDR4_SMOOTH_INVERT_CURVE3
  17443. #define WDR4_SMOOTH_INVERT_CURVE3_MASK (0xff << 0 )
  17444. #define WDR4_SMOOTH_INVERT_CURVE3_SHIFT 0U
  17445. #define WDR4_SMOOTH_INVERT_CURVE4
  17446. #define WDR4_SMOOTH_INVERT_CURVE4_MASK (0xff << 24 )
  17447. #define WDR4_SMOOTH_INVERT_CURVE4_SHIFT 24U
  17448. #define WDR4_SMOOTH_INVERT_CURVE5
  17449. #define WDR4_SMOOTH_INVERT_CURVE5_MASK (0xff << 16 )
  17450. #define WDR4_SMOOTH_INVERT_CURVE5_SHIFT 16U
  17451. #define WDR4_SMOOTH_INVERT_CURVE6
  17452. #define WDR4_SMOOTH_INVERT_CURVE6_MASK (0xff << 8 )
  17453. #define WDR4_SMOOTH_INVERT_CURVE6_SHIFT 8U
  17454. #define WDR4_SMOOTH_INVERT_CURVE7
  17455. #define WDR4_SMOOTH_INVERT_CURVE7_MASK (0xff << 0 )
  17456. #define WDR4_SMOOTH_INVERT_CURVE7_SHIFT 0U
  17457. #define WDR4_SMOOTH_INVERT_CURVE8
  17458. #define WDR4_SMOOTH_INVERT_CURVE8_MASK (0xff << 24 )
  17459. #define WDR4_SMOOTH_INVERT_CURVE8_SHIFT 24U
  17460. #define WDR4_SMOOTH_INVERT_CURVE9
  17461. #define WDR4_SMOOTH_INVERT_CURVE9_MASK (0xff << 16 )
  17462. #define WDR4_SMOOTH_INVERT_CURVE9_SHIFT 16U
  17463. #define WDR4_SMOOTH_INVERT_CURVE10
  17464. #define WDR4_SMOOTH_INVERT_CURVE10_MASK (0xff << 8 )
  17465. #define WDR4_SMOOTH_INVERT_CURVE10_SHIFT 8U
  17466. #define WDR4_SMOOTH_INVERT_CURVE11
  17467. #define WDR4_SMOOTH_INVERT_CURVE11_MASK (0xff << 0 )
  17468. #define WDR4_SMOOTH_INVERT_CURVE11_SHIFT 0U
  17469. #define WDR4_SMOOTH_INVERT_CURVE12
  17470. #define WDR4_SMOOTH_INVERT_CURVE12_MASK (0xff << 24 )
  17471. #define WDR4_SMOOTH_INVERT_CURVE12_SHIFT 24U
  17472. #define WDR4_SMOOTH_INVERT_CURVE13
  17473. #define WDR4_SMOOTH_INVERT_CURVE13_MASK (0xff << 16 )
  17474. #define WDR4_SMOOTH_INVERT_CURVE13_SHIFT 16U
  17475. #define WDR4_SMOOTH_INVERT_CURVE14
  17476. #define WDR4_SMOOTH_INVERT_CURVE14_MASK (0xff << 8 )
  17477. #define WDR4_SMOOTH_INVERT_CURVE14_SHIFT 8U
  17478. #define WDR4_SMOOTH_INVERT_CURVE15
  17479. #define WDR4_SMOOTH_INVERT_CURVE15_MASK (0xff << 0 )
  17480. #define WDR4_SMOOTH_INVERT_CURVE15_SHIFT 0U
  17481. #define WDR4_SMOOTH_INVERT_CURVE16
  17482. #define WDR4_SMOOTH_INVERT_CURVE16_MASK (0xff << 24 )
  17483. #define WDR4_SMOOTH_INVERT_CURVE16_SHIFT 24U
  17484. #define WDR4_SMOOTH_INVERT_CURVE17
  17485. #define WDR4_SMOOTH_INVERT_CURVE17_MASK (0xff << 16 )
  17486. #define WDR4_SMOOTH_INVERT_CURVE17_SHIFT 16U
  17487. #define WDR4_SMOOTH_INVERT_CURVE18
  17488. #define WDR4_SMOOTH_INVERT_CURVE18_MASK (0xff << 8 )
  17489. #define WDR4_SMOOTH_INVERT_CURVE18_SHIFT 8U
  17490. #define WDR4_SMOOTH_INVERT_CURVE19
  17491. #define WDR4_SMOOTH_INVERT_CURVE19_MASK (0xff << 0 )
  17492. #define WDR4_SMOOTH_INVERT_CURVE19_SHIFT 0U
  17493. #define WDR4_HISTOGRAM_SHIFT0
  17494. #define WDR4_HISTOGRAM_SHIFT0_MASK (0x1f << 25 )
  17495. #define WDR4_HISTOGRAM_SHIFT0_SHIFT 25U
  17496. #define WDR4_HISTOGRAM_SHIFT1
  17497. #define WDR4_HISTOGRAM_SHIFT1_MASK (0x1f << 20 )
  17498. #define WDR4_HISTOGRAM_SHIFT1_SHIFT 20U
  17499. #define WDR4_HISTOGRAM_SHIFT2
  17500. #define WDR4_HISTOGRAM_SHIFT2_MASK (0x1f << 15 )
  17501. #define WDR4_HISTOGRAM_SHIFT2_SHIFT 15U
  17502. #define WDR4_HISTOGRAM_SHIFT3
  17503. #define WDR4_HISTOGRAM_SHIFT3_MASK (0x1f << 10 )
  17504. #define WDR4_HISTOGRAM_SHIFT3_SHIFT 10U
  17505. #define WDR4_HISTOGRAM_SHIFT4
  17506. #define WDR4_HISTOGRAM_SHIFT4_MASK (0x1f << 5 )
  17507. #define WDR4_HISTOGRAM_SHIFT4_SHIFT 5U
  17508. #define WDR4_HISTOGRAM_SHIFT5
  17509. #define WDR4_HISTOGRAM_SHIFT5_MASK (0x1f << 0 )
  17510. #define WDR4_HISTOGRAM_SHIFT5_SHIFT 0U
  17511. #define WDR4_HISTOGRAM_SHIFT6
  17512. #define WDR4_HISTOGRAM_SHIFT6_MASK (0x1f << 25 )
  17513. #define WDR4_HISTOGRAM_SHIFT6_SHIFT 25U
  17514. #define WDR4_HISTOGRAM_SHIFT7
  17515. #define WDR4_HISTOGRAM_SHIFT7_MASK (0x1f << 20 )
  17516. #define WDR4_HISTOGRAM_SHIFT7_SHIFT 20U
  17517. #define WDR4_HISTOGRAM_SHIFT8
  17518. #define WDR4_HISTOGRAM_SHIFT8_MASK (0x1f << 15 )
  17519. #define WDR4_HISTOGRAM_SHIFT8_SHIFT 15U
  17520. #define WDR4_HISTOGRAM_SHIFT9
  17521. #define WDR4_HISTOGRAM_SHIFT9_MASK (0x1f << 10 )
  17522. #define WDR4_HISTOGRAM_SHIFT9_SHIFT 10U
  17523. #define WDR4_HISTOGRAM_SHIFT10
  17524. #define WDR4_HISTOGRAM_SHIFT10_MASK (0x1f << 5 )
  17525. #define WDR4_HISTOGRAM_SHIFT10_SHIFT 5U
  17526. #define WDR4_HISTOGRAM_SHIFT11
  17527. #define WDR4_HISTOGRAM_SHIFT11_MASK (0x1f << 0 )
  17528. #define WDR4_HISTOGRAM_SHIFT11_SHIFT 0U
  17529. #define WDR4_HISTOGRAM_SHIFT12
  17530. #define WDR4_HISTOGRAM_SHIFT12_MASK (0x1f << 25 )
  17531. #define WDR4_HISTOGRAM_SHIFT12_SHIFT 25U
  17532. #define WDR4_HISTOGRAM_SHIFT13
  17533. #define WDR4_HISTOGRAM_SHIFT13_MASK (0x1f << 20 )
  17534. #define WDR4_HISTOGRAM_SHIFT13_SHIFT 20U
  17535. #define WDR4_HISTOGRAM_SHIFT14
  17536. #define WDR4_HISTOGRAM_SHIFT14_MASK (0x1f << 15 )
  17537. #define WDR4_HISTOGRAM_SHIFT14_SHIFT 15U
  17538. #define WDR4_HISTOGRAM_SHIFT15
  17539. #define WDR4_HISTOGRAM_SHIFT15_MASK (0x1f << 10 )
  17540. #define WDR4_HISTOGRAM_SHIFT15_SHIFT 10U
  17541. #define WDR4_HISTOGRAM_SHIFT16
  17542. #define WDR4_HISTOGRAM_SHIFT16_MASK (0x1f << 5 )
  17543. #define WDR4_HISTOGRAM_SHIFT16_SHIFT 5U
  17544. #define WDR4_HISTOGRAM_SHIFT17
  17545. #define WDR4_HISTOGRAM_SHIFT17_MASK (0x1f << 0 )
  17546. #define WDR4_HISTOGRAM_SHIFT17_SHIFT 0U
  17547. #define WDR4_HISTOGRAM_SHIFT18
  17548. #define WDR4_HISTOGRAM_SHIFT18_MASK (0x1f << 5 )
  17549. #define WDR4_HISTOGRAM_SHIFT18_SHIFT 5U
  17550. #define WDR4_HISTOGRAM_SHIFT19
  17551. #define WDR4_HISTOGRAM_SHIFT19_MASK (0x1f << 0 )
  17552. #define WDR4_HISTOGRAM_SHIFT19_SHIFT 0U
  17553. #define WDR4_HISTOGRAM0_SHIFT0
  17554. #define WDR4_HISTOGRAM0_SHIFT0_MASK (0xf << 28 )
  17555. #define WDR4_HISTOGRAM0_SHIFT0_SHIFT 28U
  17556. #define WDR4_HISTOGRAM0_SHIFT1
  17557. #define WDR4_HISTOGRAM0_SHIFT1_MASK (0xf << 24 )
  17558. #define WDR4_HISTOGRAM0_SHIFT1_SHIFT 24U
  17559. #define WDR4_HISTOGRAM0_SHIFT2
  17560. #define WDR4_HISTOGRAM0_SHIFT2_MASK (0xf << 20 )
  17561. #define WDR4_HISTOGRAM0_SHIFT2_SHIFT 20U
  17562. #define WDR4_HISTOGRAM0_SHIFT3
  17563. #define WDR4_HISTOGRAM0_SHIFT3_MASK (0xf << 16 )
  17564. #define WDR4_HISTOGRAM0_SHIFT3_SHIFT 16U
  17565. #define WDR4_HISTOGRAM0_SHIFT4
  17566. #define WDR4_HISTOGRAM0_SHIFT4_MASK (0xf << 12 )
  17567. #define WDR4_HISTOGRAM0_SHIFT4_SHIFT 12U
  17568. #define WDR4_HISTOGRAM0_SHIFT5
  17569. #define WDR4_HISTOGRAM0_SHIFT5_MASK (0xf << 8 )
  17570. #define WDR4_HISTOGRAM0_SHIFT5_SHIFT 8U
  17571. #define WDR4_HISTOGRAM0_SHIFT6
  17572. #define WDR4_HISTOGRAM0_SHIFT6_MASK (0xf << 4 )
  17573. #define WDR4_HISTOGRAM0_SHIFT6_SHIFT 4U
  17574. #define WDR4_HISTOGRAM0_SHIFT7
  17575. #define WDR4_HISTOGRAM0_SHIFT7_MASK (0xf << 0 )
  17576. #define WDR4_HISTOGRAM0_SHIFT7_SHIFT 0U
  17577. #define WDR4_HISTOGRAM0_SHIFT8
  17578. #define WDR4_HISTOGRAM0_SHIFT8_MASK (0xf << 28 )
  17579. #define WDR4_HISTOGRAM0_SHIFT8_SHIFT 28U
  17580. #define WDR4_HISTOGRAM0_SHIFT9
  17581. #define WDR4_HISTOGRAM0_SHIFT9_MASK (0xf << 24 )
  17582. #define WDR4_HISTOGRAM0_SHIFT9_SHIFT 24U
  17583. #define WDR4_HISTOGRAM0_SHIFT10
  17584. #define WDR4_HISTOGRAM0_SHIFT10_MASK (0xf << 20 )
  17585. #define WDR4_HISTOGRAM0_SHIFT10_SHIFT 20U
  17586. #define WDR4_HISTOGRAM0_SHIFT11
  17587. #define WDR4_HISTOGRAM0_SHIFT11_MASK (0xf << 16 )
  17588. #define WDR4_HISTOGRAM0_SHIFT11_SHIFT 16U
  17589. #define WDR4_HISTOGRAM0_SHIFT12
  17590. #define WDR4_HISTOGRAM0_SHIFT12_MASK (0xf << 12 )
  17591. #define WDR4_HISTOGRAM0_SHIFT12_SHIFT 12U
  17592. #define WDR4_HISTOGRAM0_SHIFT13
  17593. #define WDR4_HISTOGRAM0_SHIFT13_MASK (0xf << 8 )
  17594. #define WDR4_HISTOGRAM0_SHIFT13_SHIFT 8U
  17595. #define WDR4_HISTOGRAM0_SHIFT14
  17596. #define WDR4_HISTOGRAM0_SHIFT14_MASK (0xf << 4 )
  17597. #define WDR4_HISTOGRAM0_SHIFT14_SHIFT 4U
  17598. #define WDR4_HISTOGRAM0_SHIFT15
  17599. #define WDR4_HISTOGRAM0_SHIFT15_MASK (0xf << 0 )
  17600. #define WDR4_HISTOGRAM0_SHIFT15_SHIFT 0U
  17601. #define WDR4_HISTOGRAM0_SHIFT16
  17602. #define WDR4_HISTOGRAM0_SHIFT16_MASK (0xf << 12 )
  17603. #define WDR4_HISTOGRAM0_SHIFT16_SHIFT 12U
  17604. #define WDR4_HISTOGRAM0_SHIFT17
  17605. #define WDR4_HISTOGRAM0_SHIFT17_MASK (0xf << 8 )
  17606. #define WDR4_HISTOGRAM0_SHIFT17_SHIFT 8U
  17607. #define WDR4_HISTOGRAM0_SHIFT18
  17608. #define WDR4_HISTOGRAM0_SHIFT18_MASK (0xf << 4 )
  17609. #define WDR4_HISTOGRAM0_SHIFT18_SHIFT 4U
  17610. #define WDR4_HISTOGRAM0_SHIFT19
  17611. #define WDR4_HISTOGRAM0_SHIFT19_MASK (0xf << 0 )
  17612. #define WDR4_HISTOGRAM0_SHIFT19_SHIFT 0U
  17613. #define WDR4_TOTAL_STRENGTH_SHD
  17614. #define WDR4_TOTAL_STRENGTH_SHD_MASK (0xff << 24 )
  17615. #define WDR4_TOTAL_STRENGTH_SHD_SHIFT 24U
  17616. #define WDR4_LOCAL_STRENGTH_SHD
  17617. #define WDR4_LOCAL_STRENGTH_SHD_MASK (0xff << 16 )
  17618. #define WDR4_LOCAL_STRENGTH_SHD_SHIFT 16U
  17619. #define WDR4_GLOBAL_STRENGTH_SHD
  17620. #define WDR4_GLOBAL_STRENGTH_SHD_MASK (0xff << 8 )
  17621. #define WDR4_GLOBAL_STRENGTH_SHD_SHIFT 8U
  17622. #define WDR4_LOW_STRENGTH_SHD
  17623. #define WDR4_LOW_STRENGTH_SHD_MASK (0xff << 0 )
  17624. #define WDR4_LOW_STRENGTH_SHD_SHIFT 0U
  17625. #define WDR4_HIGH_STRENGTH_SHD
  17626. #define WDR4_HIGH_STRENGTH_SHD_MASK (0xff << 16 )
  17627. #define WDR4_HIGH_STRENGTH_SHD_SHIFT 16U
  17628. #define WDR4_DRC_BAYER_RATIOLSVS_SHD
  17629. #define WDR4_DRC_BAYER_RATIOLSVS_SHD_MASK (0xff << 8 )
  17630. #define WDR4_DRC_BAYER_RATIOLSVS_SHD_SHIFT 8U
  17631. #define WDR4_DRC_BAYER_RATIO_SHD
  17632. #define WDR4_DRC_BAYER_RATIO_SHD_MASK (0xff << 0 )
  17633. #define WDR4_DRC_BAYER_RATIO_SHD_SHIFT 0U
  17634. #define WDR4_CONTRAST_SHD
  17635. #define WDR4_CONTRAST_SHD_MASK (0x7ff << 10 )
  17636. #define WDR4_CONTRAST_SHD_SHIFT 10U
  17637. #define WDR4_FLAT_STRENGTH_SHD
  17638. #define WDR4_FLAT_STRENGTH_SHD_MASK (0x1f << 5 )
  17639. #define WDR4_FLAT_STRENGTH_SHD_SHIFT 5U
  17640. #define WDR4_FLAT_THR_SHD
  17641. #define WDR4_FLAT_THR_SHD_MASK (0x1f << 0 )
  17642. #define WDR4_FLAT_THR_SHD_SHIFT 0U
  17643. #define WDR4_PIXEL_MERGE_SLOPE_SHD
  17644. #define WDR4_PIXEL_MERGE_SLOPE_SHD_MASK (0xff << 24 )
  17645. #define WDR4_PIXEL_MERGE_SLOPE_SHD_SHIFT 24U
  17646. #define WDR4_PIXEL_MERGE_BASE_SHD
  17647. #define WDR4_PIXEL_MERGE_BASE_SHD_MASK (0xff << 16 )
  17648. #define WDR4_PIXEL_MERGE_BASE_SHD_SHIFT 16U
  17649. #define WDR4_PIXEL_ADJUST_SLOPE_SHD
  17650. #define WDR4_PIXEL_ADJUST_SLOPE_SHD_MASK (0xff << 8 )
  17651. #define WDR4_PIXEL_ADJUST_SLOPE_SHD_SHIFT 8U
  17652. #define WDR4_PIXEL_ADJUST_BASE_SHD
  17653. #define WDR4_PIXEL_ADJUST_BASE_SHD_MASK (0xff << 0 )
  17654. #define WDR4_PIXEL_ADJUST_BASE_SHD_SHIFT 0U
  17655. #define WDR4_ENABLE_SHD
  17656. #define WDR4_ENABLE_SHD_MASK 0x1 << 20
  17657. #define WDR4_ENABLE_SHD_SHIFT 20U
  17658. #define WDR4_ENTROPY_SLOPE_SHD
  17659. #define WDR4_ENTROPY_SLOPE_SHD_MASK (0x3ff << 10 )
  17660. #define WDR4_ENTROPY_SLOPE_SHD_SHIFT 10U
  17661. #define WDR4_ENTROPY_BASE_SHD
  17662. #define WDR4_ENTROPY_BASE_SHD_MASK (0x3ff << 0 )
  17663. #define WDR4_ENTROPY_BASE_SHD_SHIFT 0U
  17664. #define DENOISE3D_V20_INVGAMMA_EN
  17665. #define DENOISE3D_V20_INVGAMMA_EN_MASK (0x1 << 11)
  17666. #define DENOISE3D_V20_INVGAMMA_EN_SHIFT 11U
  17667. #define DENOISE3D_V20_PREGAMMA_EN
  17668. #define DENOISE3D_V20_PREGAMMA_EN_MASK (0x1 << 10)
  17669. #define DENOISE3D_V20_PREGAMMA_EN_SHIFT 10U
  17670. #define DENOISE3D_V20_ERODE_EN
  17671. #define DENOISE3D_V20_ERODE_EN_MASK (0x1 << 9)
  17672. #define DENOISE3D_V20_ERODE_EN_SHIFT 9U
  17673. #define DENOISE3D_V20_MOTION_CONV_EN
  17674. #define DENOISE3D_V20_MOTION_CONV_EN_MASK (0x1 << 8)
  17675. #define DENOISE3D_V20_MOTION_CONV_EN_SHIFT 8U
  17676. #define DENOISE3D_V20_INV_DGAIN_EN
  17677. #define DENOISE3D_V20_INV_DGAIN_EN_MASK (0x1 << 7)
  17678. #define DENOISE3D_V20_INV_DGAIN_EN_SHIFT 7U
  17679. #define DENOISE3D_V20_INV_AWB_GAIN_EN
  17680. #define DENOISE3D_V20_INV_AWB_GAIN_EN_MASK (0x1 << 6)
  17681. #define DENOISE3D_V20_INV_AWB_GAIN_EN_SHIFT 6U
  17682. #define DENOISE3D_V20_COMP_LUMA_EN
  17683. #define DENOISE3D_V20_COMP_LUMA_EN_MASK (0x1 << 5)
  17684. #define DENOISE3D_V20_COMP_LUMA_EN_SHIFT 5U
  17685. #define DENOISE3D_V20_REF_RESET
  17686. #define DENOISE3D_V20_REF_RESET_MASK (0x1 << 4)
  17687. #define DENOISE3D_V20_REF_RESET_SHIFT 4U
  17688. #define DENOISE3D_V20_MOTION_DILATE_ENABLE
  17689. #define DENOISE3D_V20_MOTION_DILATE_ENABLE_MASK (0x1 << 3)
  17690. #define DENOISE3D_V20_MOTION_DILATE_ENABLE_SHIFT 3U
  17691. #define DENOISE3D_V20_NLM_ENABLE
  17692. #define DENOISE3D_V20_NLM_ENABLE_MASK (0x1 << 2)
  17693. #define DENOISE3D_V20_NLM_ENABLE_SHIFT 2U
  17694. #define DENOISE3D_V20_TNR_ENABLE
  17695. #define DENOISE3D_V20_TNR_ENABLE_MASK (0x1 << 1)
  17696. #define DENOISE3D_V20_TNR_ENABLE_SHIFT 1U
  17697. #define DENOISE3D_V20_ENABLE
  17698. #define DENOISE3D_V20_ENABLE_MASK (0x1 << 0)
  17699. #define DENOISE3D_V20_ENABLE_SHIFT 0U
  17700. #define DENOISE3D_V20_TNR_STRENGTH
  17701. #define DENOISE3D_V20_TNR_STRENGTH_MASK (0xff << 0 )
  17702. #define DENOISE3D_V20_TNR_STRENGTH_SHIFT 0U
  17703. #define DENOISE3D_V20_NOISE_LEVEL
  17704. #define DENOISE3D_V20_NOISE_LEVEL_MASK (0xffff << 16 )
  17705. #define DENOISE3D_V20_NOISE_LEVEL_SHIFT 16U
  17706. #define DENOISE3D_V20_NOISE_MEAN
  17707. #define DENOISE3D_V20_NOISE_MEAN_MASK (0xffff << 0 )
  17708. #define DENOISE3D_V20_NOISE_MEAN_SHIFT 0U
  17709. #define DENOISE3D_V20_NOSIE_THRESH
  17710. #define DENOISE3D_V20_NOSIE_THRESH_MASK (0xffff << 16 )
  17711. #define DENOISE3D_V20_NOSIE_THRESH_SHIFT 16U
  17712. #define DENOISE3D_V20_MOTION_MEAN
  17713. #define DENOISE3D_V20_MOTION_MEAN_MASK (0xffff << 0 )
  17714. #define DENOISE3D_V20_MOTION_MEAN_SHIFT 0U
  17715. #define DENOISE3D_V20_TNR_RANGE_H
  17716. #define DENOISE3D_V20_TNR_RANGE_H_MASK (0xf << 12 )
  17717. #define DENOISE3D_V20_TNR_RANGE_H_SHIFT 12U
  17718. #define DENOISE3D_V20_TNR_RANGE_V
  17719. #define DENOISE3D_V20_TNR_RANGE_V_MASK (0xf << 8 )
  17720. #define DENOISE3D_V20_TNR_RANGE_V_SHIFT 8U
  17721. #define DENOISE3D_V20_TNR_DILATE_RANGE_H
  17722. #define DENOISE3D_V20_TNR_DILATE_RANGE_H_MASK (0xf << 4 )
  17723. #define DENOISE3D_V20_TNR_DILATE_RANGE_H_SHIFT 4U
  17724. #define DENOISE3D_V20_TNR_DILATE_RANGE_V
  17725. #define DENOISE3D_V20_TNR_DILATE_RANGE_V_MASK (0xf << 0 )
  17726. #define DENOISE3D_V20_TNR_DILATE_RANGE_V_SHIFT 0U
  17727. #define DENOISE3D_V20_MOTION_INV
  17728. #define DENOISE3D_V20_MOTION_INV_MASK (0xfffff << 0 )
  17729. #define DENOISE3D_V20_MOTION_INV_SHIFT 0U
  17730. #define DENOISE3D_V20_THR_UPDATE
  17731. #define DENOISE3D_V20_THR_UPDATE_MASK (0x7ff << 16 )
  17732. #define DENOISE3D_V20_THR_UPDATE_SHIFT 16U
  17733. #define DENOISE3D_V20_MOTION_THR_UPDATE
  17734. #define DENOISE3D_V20_MOTION_THR_UPDATE_MASK (0x7ff << 0 )
  17735. #define DENOISE3D_V20_MOTION_THR_UPDATE_SHIFT 0U
  17736. #define DENOISE3D_V20_MOTION_PRE_WEIGHT
  17737. #define DENOISE3D_V20_MOTION_PRE_WEIGHT_MASK (0x3f << 16 )
  17738. #define DENOISE3D_V20_MOTION_PRE_WEIGHT_SHIFT 16U
  17739. #define DENOISE3D_V20_MOTION_SLOPE
  17740. #define DENOISE3D_V20_MOTION_SLOPE_MASK (0x7ff << 0 )
  17741. #define DENOISE3D_V20_MOTION_SLOPE_SHIFT 0U
  17742. #define DENOISE3D_V20_MOTION_CONV_SHIFT
  17743. #define DENOISE3D_V20_MOTION_CONV_SHIFT_MASK (0xf << 28 )
  17744. #define DENOISE3D_V20_MOTION_CONV_SHIFT_SHIFT 28U
  17745. #define DENOISE3D_V20_MOTION_CONV_MAX
  17746. #define DENOISE3D_V20_MOTION_CONV_MAX_MASK (0x7ff << 17 )
  17747. #define DENOISE3D_V20_MOTION_CONV_MAX_SHIFT 17U
  17748. #define DENOISE3D_V20_TNR_VAL_SHIFT_BIT
  17749. #define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_MASK (0x3f << 11 )
  17750. #define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_SHIFT 11U
  17751. #define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT
  17752. #define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_MASK (0x3f << 5 )
  17753. #define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_SHIFT 5U
  17754. #define DENOISE3D_V20_SAD_WEIGHT
  17755. #define DENOISE3D_V20_SAD_WEIGHT_MASK (0x1f << 0 )
  17756. #define DENOISE3D_V20_SAD_WEIGHT_SHIFT 0U
  17757. #define DENOISE3D_V20_PIXEL_VAL_SHIFT
  17758. #define DENOISE3D_V20_PIXEL_VAL_SHIFT_MASK (0x7ff << 20 )
  17759. #define DENOISE3D_V20_PIXEL_VAL_SHIFT_SHIFT 20U
  17760. #define DENOISE3D_V20_PIXEL_SLOP
  17761. #define DENOISE3D_V20_PIXEL_SLOP_MASK (0xff << 12 )
  17762. #define DENOISE3D_V20_PIXEL_SLOP_SHIFT 12U
  17763. #define DENOISE3D_V20_PIXEL_SLOP_SHIFT_BIT
  17764. #define DENOISE3D_V20_PIXEL_SLOP_SHIFT_BIT_MASK (0xf << 8 )
  17765. #define DENOISE3D_V20_PIXEL_SLOP_SHIFT_BIT_SHIFT 8U
  17766. #define DENOISE3D_V20_PIXEL_SLOP_MIN
  17767. #define DENOISE3D_V20_PIXEL_SLOP_MIN_MASK (0xff << 0 )
  17768. #define DENOISE3D_V20_PIXEL_SLOP_MIN_SHIFT 0U
  17769. #define DENOISE3D_V20_INVGAMMA_EN_SHD
  17770. #define DENOISE3D_V20_INVGAMMA_EN_SHD_MASK 0x1 << 11
  17771. #define DENOISE3D_V20_INVGAMMA_EN_SHD_SHIFT 11U
  17772. #define DENOISE3D_V20_PREGAMMA_EN_SHD
  17773. #define DENOISE3D_V20_PREGAMMA_EN_SHD_MASK 0x1 << 10
  17774. #define DENOISE3D_V20_PREGAMMA_EN_SHD_SHIFT 10U
  17775. #define DENOISE3D_V20_ERODE_EN_SHD
  17776. #define DENOISE3D_V20_ERODE_EN_SHD_MASK 0x1 << 9
  17777. #define DENOISE3D_V20_ERODE_EN_SHD_SHIFT 9U
  17778. #define DENOISE3D_V20_MOTION_CONV_EN_SHD
  17779. #define DENOISE3D_V20_MOTION_CONV_EN_SHD_MASK 0x1 << 8
  17780. #define DENOISE3D_V20_MOTION_CONV_EN_SHD_SHIFT 8U
  17781. #define DENOISE3D_V20_INV_DGAIN_EN_SHD
  17782. #define DENOISE3D_V20_INV_DGAIN_EN_SHD_MASK 0x1 << 7
  17783. #define DENOISE3D_V20_INV_DGAIN_EN_SHD_SHIFT 7U
  17784. #define DENOISE3D_V20_INV_AWB_GAIN_EN_SHD
  17785. #define DENOISE3D_V20_INV_AWB_GAIN_EN_SHD_MASK 0x1 << 6
  17786. #define DENOISE3D_V20_INV_AWB_GAIN_EN_SHD_SHIFT 6U
  17787. #define DENOISE3D_V20_COMP_LUMA_EN_SHD
  17788. #define DENOISE3D_V20_COMP_LUMA_EN_SHD_MASK 0x1 << 5
  17789. #define DENOISE3D_V20_COMP_LUMA_EN_SHD_SHIFT 5U
  17790. #define DENOISE3D_V20_REF_RESET_SHD
  17791. #define DENOISE3D_V20_REF_RESET_SHD_MASK 0x1 << 4
  17792. #define DENOISE3D_V20_REF_RESET_SHD_SHIFT 4U
  17793. #define DENOISE3D_V20_MOTION_DILATE_ENABLE_SHD
  17794. #define DENOISE3D_V20_MOTION_DILATE_ENABLE_SHD_MASK 0x1 << 3
  17795. #define DENOISE3D_V20_MOTION_DILATE_ENABLE_SHD_SHIFT 3U
  17796. #define DENOISE3D_V20_NLM_ENABLE_SHD
  17797. #define DENOISE3D_V20_NLM_ENABLE_SHD_MASK 0x1 << 2
  17798. #define DENOISE3D_V20_NLM_ENABLE_SHD_SHIFT 2U
  17799. #define DENOISE3D_V20_TNR_ENABLE_SHD
  17800. #define DENOISE3D_V20_TNR_ENABLE_SHD_MASK 0x1 << 1
  17801. #define DENOISE3D_V20_TNR_ENABLE_SHD_SHIFT 1U
  17802. #define DENOISE3D_V20_ENABLE_SHD
  17803. #define DENOISE3D_V20_ENABLE_SHD_MASK 0x1 << 0
  17804. #define DENOISE3D_V20_ENABLE_SHD_SHIFT 0U
  17805. #define DENOISE3D_V20_TNR_STRENGTH_SHD
  17806. #define DENOISE3D_V20_TNR_STRENGTH_SHD_MASK (0xff << 0 )
  17807. #define DENOISE3D_V20_TNR_STRENGTH_SHD_SHIFT 0U
  17808. #define DENOISE3D_V20_NOISE_LEVEL_SHD
  17809. #define DENOISE3D_V20_NOISE_LEVEL_SHD_MASK (0x3fff << 16 )
  17810. #define DENOISE3D_V20_NOISE_LEVEL_SHD_SHIFT 16U
  17811. #define DENOISE3D_V20_NOISE_MEAN_SHD
  17812. #define DENOISE3D_V20_NOISE_MEAN_SHD_MASK (0x3fff << 0 )
  17813. #define DENOISE3D_V20_NOISE_MEAN_SHD_SHIFT 0U
  17814. #define DENOISE3D_V20_NOSIE_THRESH_SHD
  17815. #define DENOISE3D_V20_NOSIE_THRESH_SHD_MASK (0x3fff << 16 )
  17816. #define DENOISE3D_V20_NOSIE_THRESH_SHD_SHIFT 16U
  17817. #define DENOISE3D_V20_MOTION_MEAN_SHD
  17818. #define DENOISE3D_V20_MOTION_MEAN_SHD_MASK (0x3fff << 0 )
  17819. #define DENOISE3D_V20_MOTION_MEAN_SHD_SHIFT 0U
  17820. #define DENOISE3D_V20_TNR_RANGE_H_SHD
  17821. #define DENOISE3D_V20_TNR_RANGE_H_SHD_MASK (0x3 << 8 )
  17822. #define DENOISE3D_V20_TNR_RANGE_H_SHD_SHIFT 8U
  17823. #define DENOISE3D_V20_TNR_RANGE_V_SHD
  17824. #define DENOISE3D_V20_TNR_RANGE_V_SHD_MASK (0x3 << 6 )
  17825. #define DENOISE3D_V20_TNR_RANGE_V_SHD_SHIFT 6U
  17826. #define DENOISE3D_V20_TNR_DILATE_RANGE_H_SHD
  17827. #define DENOISE3D_V20_TNR_DILATE_RANGE_H_SHD_MASK (0x7 << 3 )
  17828. #define DENOISE3D_V20_TNR_DILATE_RANGE_H_SHD_SHIFT 3U
  17829. #define DENOISE3D_V20_TNR_DILATE_RANGE_V_SHD
  17830. #define DENOISE3D_V20_TNR_DILATE_RANGE_V_SHD_MASK (0x7 << 0 )
  17831. #define DENOISE3D_V20_TNR_DILATE_RANGE_V_SHD_SHIFT 0U
  17832. #define DENOISE3D_V20_MOTION_INV_SHD
  17833. #define DENOISE3D_V20_MOTION_INV_SHD_MASK (0xfffff << 0 )
  17834. #define DENOISE3D_V20_MOTION_INV_SHD_SHIFT 0U
  17835. #define DENOISE3D_V20_THR_UPDATE_SHD
  17836. #define DENOISE3D_V20_THR_UPDATE_SHD_MASK (0x7ff << 16 )
  17837. #define DENOISE3D_V20_THR_UPDATE_SHD_SHIFT 16U
  17838. #define DENOISE3D_V20_MOTION_THR_UPDATE_SHD
  17839. #define DENOISE3D_V20_MOTION_THR_UPDATE_SHD_MASK (0x7ff << 0 )
  17840. #define DENOISE3D_V20_MOTION_THR_UPDATE_SHD_SHIFT 0U
  17841. #define DENOISE3D_V20_MOTION_PRE_WEIGHT_SHD
  17842. #define DENOISE3D_V20_MOTION_PRE_WEIGHT_SHD_MASK (0x7ff << 16 )
  17843. #define DENOISE3D_V20_MOTION_PRE_WEIGHT_SHD_SHIFT 16U
  17844. #define DENOISE3D_V20_MOTION_SLOPE_SHD
  17845. #define DENOISE3D_V20_MOTION_SLOPE_SHD_MASK (0x7ff << 0 )
  17846. #define DENOISE3D_V20_MOTION_SLOPE_SHD_SHIFT 0U
  17847. #define DENOISE3D_V20_MOTION_CONV_SHIFT_SHD
  17848. #define DENOISE3D_V20_MOTION_CONV_SHIFT_SHD_MASK (0xf << 28 )
  17849. #define DENOISE3D_V20_MOTION_CONV_SHIFT_SHD_SHIFT 28U
  17850. #define DENOISE3D_V20_MOTION_CONV_MAX_SHD
  17851. #define DENOISE3D_V20_MOTION_CONV_MAX_SHD_MASK (0x7ff << 17 )
  17852. #define DENOISE3D_V20_MOTION_CONV_MAX_SHD_SHIFT 17U
  17853. #define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_SHD
  17854. #define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_SHD_MASK (0x3f << 11 )
  17855. #define DENOISE3D_V20_TNR_VAL_SHIFT_BIT_SHD_SHIFT 11U
  17856. #define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_SHD
  17857. #define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_SHD_MASK (0x3f << 5 )
  17858. #define DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT_SHD_SHIFT 5U
  17859. #define DENOISE3D_V20_SAD_WEIGHT_SHD
  17860. #define DENOISE3D_V20_SAD_WEIGHT_SHD_MASK (0x1f << 0 )
  17861. #define DENOISE3D_V20_SAD_WEIGHT_SHD_SHIFT 0U
  17862. #define DENOISE3D_V20_PIXEL_VAL_SHIFT_SHD
  17863. #define DENOISE3D_V20_PIXEL_VAL_SHIFT_SHD_MASK (0x7ff << 20 )
  17864. #define DENOISE3D_V20_PIXEL_VAL_SHIFT_SHD_SHIFT 20U
  17865. #define DENOISE3D_V20_PIXEL_SLOP_MIN_SHD
  17866. #define DENOISE3D_V20_PIXEL_SLOP_MIN_SHD_MASK (0xff << 12 )
  17867. #define DENOISE3D_V20_PIXEL_SLOP_MIN_SHD_SHIFT 12U
  17868. #define DENOISE3D_V20_PIXEL_SLOP_SHIFT_SHD
  17869. #define DENOISE3D_V20_PIXEL_SLOP_SHIFT_SHD_MASK (0xf << 8 )
  17870. #define DENOISE3D_V20_PIXEL_SLOP_SHIFT_SHD_SHIFT 8U
  17871. #define DENOISE3D_V20_BG_VAL_SUM
  17872. #define DENOISE3D_V20_BG_VAL_SUM_MASK (0xffffffff << 0 )
  17873. #define DENOISE3D_V20_BG_VAL_SUM_SHIFT 0U
  17874. #define DENOISE3D_V20_MO_VAL_SUM
  17875. #define DENOISE3D_V20_MO_VAL_SUM_MASK (0xffffffff << 0 )
  17876. #define DENOISE3D_V20_MO_VAL_SUM_SHIFT 0U
  17877. #define DENOISE3D_V20_BG_PIX_CNT
  17878. #define DENOISE3D_V20_BG_PIX_CNT_MASK (0xffffffff << 0 )
  17879. #define DENOISE3D_V20_BG_PIX_CNT_SHIFT 0U
  17880. #define DENOISE3D_V20_MO_PIX_CNT
  17881. #define DENOISE3D_V20_MO_PIX_CNT_MASK (0xffffffff << 0 )
  17882. #define DENOISE3D_V20_MO_PIX_CNT_SHIFT 0U
  17883. #define DENOISE3D_V20_FRAME_AVG
  17884. #define DENOISE3D_V20_FRAME_AVG_MASK (0xffffffff << 0 )
  17885. #define DENOISE3D_V20_FRAME_AVG_SHIFT 0U
  17886. #define DENOISE3D_V20_DUMMY_HBLANK
  17887. #define DENOISE3D_V20_DUMMY_HBLANK_MASK (0xffff << 0 )
  17888. #define DENOISE3D_V20_DUMMY_HBLANK_SHIFT 0U
  17889. #define DENOISE3D2_PREGAMMA_Y_2_A
  17890. #define DENOISE3D2_PREGAMMA_Y_2_A_MASK (0x3f << 24 )
  17891. #define DENOISE3D2_PREGAMMA_Y_2_A_SHIFT 24U
  17892. #define DENOISE3D2_PREGAMMA_Y_1
  17893. #define DENOISE3D2_PREGAMMA_Y_1_MASK (0xfff << 12 )
  17894. #define DENOISE3D2_PREGAMMA_Y_1_SHIFT 12U
  17895. #define DENOISE3D2_PREGAMMA_Y_0
  17896. #define DENOISE3D2_PREGAMMA_Y_0_MASK (0xfff << 0 )
  17897. #define DENOISE3D2_PREGAMMA_Y_0_SHIFT 0U
  17898. #define DENOISE3D2_PREGAMMA_Y_2_B
  17899. #define DENOISE3D2_PREGAMMA_Y_2_B_MASK (0x3f << 24 )
  17900. #define DENOISE3D2_PREGAMMA_Y_2_B_SHIFT 24U
  17901. #define DENOISE3D2_PREGAMMA_Y_4
  17902. #define DENOISE3D2_PREGAMMA_Y_4_MASK (0xfff << 12 )
  17903. #define DENOISE3D2_PREGAMMA_Y_4_SHIFT 12U
  17904. #define DENOISE3D2_PREGAMMA_Y_3
  17905. #define DENOISE3D2_PREGAMMA_Y_3_MASK (0xfff << 0 )
  17906. #define DENOISE3D2_PREGAMMA_Y_3_SHIFT 0U
  17907. #define DENOISE3D2_PREGAMMA_Y_7_A
  17908. #define DENOISE3D2_PREGAMMA_Y_7_A_MASK (0x3f << 24 )
  17909. #define DENOISE3D2_PREGAMMA_Y_7_A_SHIFT 24U
  17910. #define DENOISE3D2_PREGAMMA_Y_6
  17911. #define DENOISE3D2_PREGAMMA_Y_6_MASK (0xfff << 12 )
  17912. #define DENOISE3D2_PREGAMMA_Y_6_SHIFT 12U
  17913. #define DENOISE3D2_PREGAMMA_Y_5
  17914. #define DENOISE3D2_PREGAMMA_Y_5_MASK (0xfff << 0 )
  17915. #define DENOISE3D2_PREGAMMA_Y_5_SHIFT 0U
  17916. #define DENOISE3D2_PREGAMMA_Y_7_B
  17917. #define DENOISE3D2_PREGAMMA_Y_7_B_MASK (0x3f << 24 )
  17918. #define DENOISE3D2_PREGAMMA_Y_7_B_SHIFT 24U
  17919. #define DENOISE3D2_PREGAMMA_Y_9
  17920. #define DENOISE3D2_PREGAMMA_Y_9_MASK (0xfff << 12 )
  17921. #define DENOISE3D2_PREGAMMA_Y_9_SHIFT 12U
  17922. #define DENOISE3D2_PREGAMMA_Y_8
  17923. #define DENOISE3D2_PREGAMMA_Y_8_MASK (0xfff << 0 )
  17924. #define DENOISE3D2_PREGAMMA_Y_8_SHIFT 0U
  17925. #define DENOISE3D2_PREGAMMA_Y_12_A
  17926. #define DENOISE3D2_PREGAMMA_Y_12_A_MASK (0x3f << 24 )
  17927. #define DENOISE3D2_PREGAMMA_Y_12_A_SHIFT 24U
  17928. #define DENOISE3D2_PREGAMMA_Y_11
  17929. #define DENOISE3D2_PREGAMMA_Y_11_MASK (0xfff << 12 )
  17930. #define DENOISE3D2_PREGAMMA_Y_11_SHIFT 12U
  17931. #define DENOISE3D2_PREGAMMA_Y_10
  17932. #define DENOISE3D2_PREGAMMA_Y_10_MASK (0xfff << 0 )
  17933. #define DENOISE3D2_PREGAMMA_Y_10_SHIFT 0U
  17934. #define DENOISE3D2_PREGAMMA_Y_12_B
  17935. #define DENOISE3D2_PREGAMMA_Y_12_B_MASK (0x3f << 24 )
  17936. #define DENOISE3D2_PREGAMMA_Y_12_B_SHIFT 24U
  17937. #define DENOISE3D2_PREGAMMA_Y_14
  17938. #define DENOISE3D2_PREGAMMA_Y_14_MASK (0xfff << 12 )
  17939. #define DENOISE3D2_PREGAMMA_Y_14_SHIFT 12U
  17940. #define DENOISE3D2_PREGAMMA_Y_13
  17941. #define DENOISE3D2_PREGAMMA_Y_13_MASK (0xfff << 0 )
  17942. #define DENOISE3D2_PREGAMMA_Y_13_SHIFT 0U
  17943. #define DENOISE3D2_PREGAMMA_Y_17_A
  17944. #define DENOISE3D2_PREGAMMA_Y_17_A_MASK (0x3f << 24 )
  17945. #define DENOISE3D2_PREGAMMA_Y_17_A_SHIFT 24U
  17946. #define DENOISE3D2_PREGAMMA_Y_16
  17947. #define DENOISE3D2_PREGAMMA_Y_16_MASK (0xfff << 12 )
  17948. #define DENOISE3D2_PREGAMMA_Y_16_SHIFT 12U
  17949. #define DENOISE3D2_PREGAMMA_Y_15
  17950. #define DENOISE3D2_PREGAMMA_Y_15_MASK (0xfff << 0 )
  17951. #define DENOISE3D2_PREGAMMA_Y_15_SHIFT 0U
  17952. #define DENOISE3D2_PREGAMMA_Y_17_B
  17953. #define DENOISE3D2_PREGAMMA_Y_17_B_MASK (0x3f << 24 )
  17954. #define DENOISE3D2_PREGAMMA_Y_17_B_SHIFT 24U
  17955. #define DENOISE3D2_PREGAMMA_Y_19
  17956. #define DENOISE3D2_PREGAMMA_Y_19_MASK (0xfff << 12 )
  17957. #define DENOISE3D2_PREGAMMA_Y_19_SHIFT 12U
  17958. #define DENOISE3D2_PREGAMMA_Y_18
  17959. #define DENOISE3D2_PREGAMMA_Y_18_MASK (0xfff << 0 )
  17960. #define DENOISE3D2_PREGAMMA_Y_18_SHIFT 0U
  17961. #define DENOISE3D2_PREGAMMA_Y_22_A
  17962. #define DENOISE3D2_PREGAMMA_Y_22_A_MASK (0x3f << 24 )
  17963. #define DENOISE3D2_PREGAMMA_Y_22_A_SHIFT 24U
  17964. #define DENOISE3D2_PREGAMMA_Y_21
  17965. #define DENOISE3D2_PREGAMMA_Y_21_MASK (0xfff << 12 )
  17966. #define DENOISE3D2_PREGAMMA_Y_21_SHIFT 12U
  17967. #define DENOISE3D2_PREGAMMA_Y_20
  17968. #define DENOISE3D2_PREGAMMA_Y_20_MASK (0xfff << 0 )
  17969. #define DENOISE3D2_PREGAMMA_Y_20_SHIFT 0U
  17970. #define DENOISE3D2_PREGAMMA_Y_22_B
  17971. #define DENOISE3D2_PREGAMMA_Y_22_B_MASK (0x3f << 24 )
  17972. #define DENOISE3D2_PREGAMMA_Y_22_B_SHIFT 24U
  17973. #define DENOISE3D2_PREGAMMA_Y_24
  17974. #define DENOISE3D2_PREGAMMA_Y_24_MASK (0xfff << 12 )
  17975. #define DENOISE3D2_PREGAMMA_Y_24_SHIFT 12U
  17976. #define DENOISE3D2_PREGAMMA_Y_23
  17977. #define DENOISE3D2_PREGAMMA_Y_23_MASK (0xfff << 0 )
  17978. #define DENOISE3D2_PREGAMMA_Y_23_SHIFT 0U
  17979. #define DENOISE3D2_PREGAMMA_Y_27_A
  17980. #define DENOISE3D2_PREGAMMA_Y_27_A_MASK (0x3f << 24 )
  17981. #define DENOISE3D2_PREGAMMA_Y_27_A_SHIFT 24U
  17982. #define DENOISE3D2_PREGAMMA_Y_26
  17983. #define DENOISE3D2_PREGAMMA_Y_26_MASK (0xfff << 12 )
  17984. #define DENOISE3D2_PREGAMMA_Y_26_SHIFT 12U
  17985. #define DENOISE3D2_PREGAMMA_Y_25
  17986. #define DENOISE3D2_PREGAMMA_Y_25_MASK (0xfff << 0 )
  17987. #define DENOISE3D2_PREGAMMA_Y_25_SHIFT 0U
  17988. #define DENOISE3D2_PREGAMMA_Y_27_B
  17989. #define DENOISE3D2_PREGAMMA_Y_27_B_MASK (0x3f << 24 )
  17990. #define DENOISE3D2_PREGAMMA_Y_27_B_SHIFT 24U
  17991. #define DENOISE3D2_PREGAMMA_Y_29
  17992. #define DENOISE3D2_PREGAMMA_Y_29_MASK (0xfff << 12 )
  17993. #define DENOISE3D2_PREGAMMA_Y_29_SHIFT 12U
  17994. #define DENOISE3D2_PREGAMMA_Y_28
  17995. #define DENOISE3D2_PREGAMMA_Y_28_MASK (0xfff << 0 )
  17996. #define DENOISE3D2_PREGAMMA_Y_28_SHIFT 0U
  17997. #define DENOISE3D2_PREGAMMA_Y_32_A
  17998. #define DENOISE3D2_PREGAMMA_Y_32_A_MASK (0x3f << 24 )
  17999. #define DENOISE3D2_PREGAMMA_Y_32_A_SHIFT 24U
  18000. #define DENOISE3D2_PREGAMMA_Y_31
  18001. #define DENOISE3D2_PREGAMMA_Y_31_MASK (0xfff << 12 )
  18002. #define DENOISE3D2_PREGAMMA_Y_31_SHIFT 12U
  18003. #define DENOISE3D2_PREGAMMA_Y_30
  18004. #define DENOISE3D2_PREGAMMA_Y_30_MASK (0xfff << 0 )
  18005. #define DENOISE3D2_PREGAMMA_Y_30_SHIFT 0U
  18006. #define DENOISE3D2_PREGAMMA_Y_32_B
  18007. #define DENOISE3D2_PREGAMMA_Y_32_B_MASK (0x3f << 0 )
  18008. #define DENOISE3D2_PREGAMMA_Y_32_B_SHIFT 0U
  18009. #define DENOISE3D2_PREGAMMA_Y_2_A_SHD
  18010. #define DENOISE3D2_PREGAMMA_Y_2_A_SHD_MASK (0x3f << 24 )
  18011. #define DENOISE3D2_PREGAMMA_Y_2_A_SHD_SHIFT 24U
  18012. #define DENOISE3D2_PREGAMMA_Y_1_SHD
  18013. #define DENOISE3D2_PREGAMMA_Y_1_SHD_MASK (0xfff << 12 )
  18014. #define DENOISE3D2_PREGAMMA_Y_1_SHD_SHIFT 12U
  18015. #define DENOISE3D2_PREGAMMA_Y_0_SHD
  18016. #define DENOISE3D2_PREGAMMA_Y_0_SHD_MASK (0xfff << 0 )
  18017. #define DENOISE3D2_PREGAMMA_Y_0_SHD_SHIFT 0U
  18018. #define DENOISE3D2_PREGAMMA_Y_2_B_SHD
  18019. #define DENOISE3D2_PREGAMMA_Y_2_B_SHD_MASK (0x3f << 24 )
  18020. #define DENOISE3D2_PREGAMMA_Y_2_B_SHD_SHIFT 24U
  18021. #define DENOISE3D2_PREGAMMA_Y_4_SHD
  18022. #define DENOISE3D2_PREGAMMA_Y_4_SHD_MASK (0xfff << 12 )
  18023. #define DENOISE3D2_PREGAMMA_Y_4_SHD_SHIFT 12U
  18024. #define DENOISE3D2_PREGAMMA_Y_3_SHD
  18025. #define DENOISE3D2_PREGAMMA_Y_3_SHD_MASK (0xfff << 0 )
  18026. #define DENOISE3D2_PREGAMMA_Y_3_SHD_SHIFT 0U
  18027. #define DENOISE3D2_PREGAMMA_Y_7_A_SHD
  18028. #define DENOISE3D2_PREGAMMA_Y_7_A_SHD_MASK (0x3f << 24 )
  18029. #define DENOISE3D2_PREGAMMA_Y_7_A_SHD_SHIFT 24U
  18030. #define DENOISE3D2_PREGAMMA_Y_6_SHD
  18031. #define DENOISE3D2_PREGAMMA_Y_6_SHD_MASK (0xfff << 12 )
  18032. #define DENOISE3D2_PREGAMMA_Y_6_SHD_SHIFT 12U
  18033. #define DENOISE3D2_PREGAMMA_Y_5_SHD
  18034. #define DENOISE3D2_PREGAMMA_Y_5_SHD_MASK (0xfff << 0 )
  18035. #define DENOISE3D2_PREGAMMA_Y_5_SHD_SHIFT 0U
  18036. #define DENOISE3D2_PREGAMMA_Y_7_B_SHD
  18037. #define DENOISE3D2_PREGAMMA_Y_7_B_SHD_MASK (0x3f << 24 )
  18038. #define DENOISE3D2_PREGAMMA_Y_7_B_SHD_SHIFT 24U
  18039. #define DENOISE3D2_PREGAMMA_Y_9_SHD
  18040. #define DENOISE3D2_PREGAMMA_Y_9_SHD_MASK (0xfff << 12 )
  18041. #define DENOISE3D2_PREGAMMA_Y_9_SHD_SHIFT 12U
  18042. #define DENOISE3D2_PREGAMMA_Y_8_SHD
  18043. #define DENOISE3D2_PREGAMMA_Y_8_SHD_MASK (0xfff << 0 )
  18044. #define DENOISE3D2_PREGAMMA_Y_8_SHD_SHIFT 0U
  18045. #define DENOISE3D2_PREGAMMA_Y_12_A_SHD
  18046. #define DENOISE3D2_PREGAMMA_Y_12_A_SHD_MASK (0x3f << 24 )
  18047. #define DENOISE3D2_PREGAMMA_Y_12_A_SHD_SHIFT 24U
  18048. #define DENOISE3D2_PREGAMMA_Y_11_SHD
  18049. #define DENOISE3D2_PREGAMMA_Y_11_SHD_MASK (0xfff << 12 )
  18050. #define DENOISE3D2_PREGAMMA_Y_11_SHD_SHIFT 12U
  18051. #define DENOISE3D2_PREGAMMA_Y_10_SHD
  18052. #define DENOISE3D2_PREGAMMA_Y_10_SHD_MASK (0xfff << 0 )
  18053. #define DENOISE3D2_PREGAMMA_Y_10_SHD_SHIFT 0U
  18054. #define DENOISE3D2_PREGAMMA_Y_12_B_SHD
  18055. #define DENOISE3D2_PREGAMMA_Y_12_B_SHD_MASK (0x3f << 24 )
  18056. #define DENOISE3D2_PREGAMMA_Y_12_B_SHD_SHIFT 24U
  18057. #define DENOISE3D2_PREGAMMA_Y_14_SHD
  18058. #define DENOISE3D2_PREGAMMA_Y_14_SHD_MASK (0xfff << 12 )
  18059. #define DENOISE3D2_PREGAMMA_Y_14_SHD_SHIFT 12U
  18060. #define DENOISE3D2_PREGAMMA_Y_13_SHD
  18061. #define DENOISE3D2_PREGAMMA_Y_13_SHD_MASK (0xfff << 0 )
  18062. #define DENOISE3D2_PREGAMMA_Y_13_SHD_SHIFT 0U
  18063. #define DENOISE3D2_PREGAMMA_Y_17_A_SHD
  18064. #define DENOISE3D2_PREGAMMA_Y_17_A_SHD_MASK (0x3f << 24 )
  18065. #define DENOISE3D2_PREGAMMA_Y_17_A_SHD_SHIFT 24U
  18066. #define DENOISE3D2_PREGAMMA_Y_16_SHD
  18067. #define DENOISE3D2_PREGAMMA_Y_16_SHD_MASK (0xfff << 12 )
  18068. #define DENOISE3D2_PREGAMMA_Y_16_SHD_SHIFT 12U
  18069. #define DENOISE3D2_PREGAMMA_Y_15_SHD
  18070. #define DENOISE3D2_PREGAMMA_Y_15_SHD_MASK (0xfff << 0 )
  18071. #define DENOISE3D2_PREGAMMA_Y_15_SHD_SHIFT 0U
  18072. #define DENOISE3D2_PREGAMMA_Y_17_B_SHD
  18073. #define DENOISE3D2_PREGAMMA_Y_17_B_SHD_MASK (0x3f << 24 )
  18074. #define DENOISE3D2_PREGAMMA_Y_17_B_SHD_SHIFT 24U
  18075. #define DENOISE3D2_PREGAMMA_Y_19_SHD
  18076. #define DENOISE3D2_PREGAMMA_Y_19_SHD_MASK (0xfff << 12 )
  18077. #define DENOISE3D2_PREGAMMA_Y_19_SHD_SHIFT 12U
  18078. #define DENOISE3D2_PREGAMMA_Y_18_SHD
  18079. #define DENOISE3D2_PREGAMMA_Y_18_SHD_MASK (0xfff << 0 )
  18080. #define DENOISE3D2_PREGAMMA_Y_18_SHD_SHIFT 0U
  18081. #define DENOISE3D2_PREGAMMA_Y_22_A_SHD
  18082. #define DENOISE3D2_PREGAMMA_Y_22_A_SHD_MASK (0x3f << 24 )
  18083. #define DENOISE3D2_PREGAMMA_Y_22_A_SHD_SHIFT 24U
  18084. #define DENOISE3D2_PREGAMMA_Y_21_SHD
  18085. #define DENOISE3D2_PREGAMMA_Y_21_SHD_MASK (0xfff << 12 )
  18086. #define DENOISE3D2_PREGAMMA_Y_21_SHD_SHIFT 12U
  18087. #define DENOISE3D2_PREGAMMA_Y_20_SHD
  18088. #define DENOISE3D2_PREGAMMA_Y_20_SHD_MASK (0xfff << 0 )
  18089. #define DENOISE3D2_PREGAMMA_Y_20_SHD_SHIFT 0U
  18090. #define DENOISE3D2_PREGAMMA_Y_22_B_SHD
  18091. #define DENOISE3D2_PREGAMMA_Y_22_B_SHD_MASK (0x3f << 24 )
  18092. #define DENOISE3D2_PREGAMMA_Y_22_B_SHD_SHIFT 24U
  18093. #define DENOISE3D2_PREGAMMA_Y_24_SHD
  18094. #define DENOISE3D2_PREGAMMA_Y_24_SHD_MASK (0xfff << 12 )
  18095. #define DENOISE3D2_PREGAMMA_Y_24_SHD_SHIFT 12U
  18096. #define DENOISE3D2_PREGAMMA_Y_23_SHD
  18097. #define DENOISE3D2_PREGAMMA_Y_23_SHD_MASK (0xfff << 0 )
  18098. #define DENOISE3D2_PREGAMMA_Y_23_SHD_SHIFT 0U
  18099. #define DENOISE3D2_PREGAMMA_Y_27_A_SHD
  18100. #define DENOISE3D2_PREGAMMA_Y_27_A_SHD_MASK (0x3f << 24 )
  18101. #define DENOISE3D2_PREGAMMA_Y_27_A_SHD_SHIFT 24U
  18102. #define DENOISE3D2_PREGAMMA_Y_26_SHD
  18103. #define DENOISE3D2_PREGAMMA_Y_26_SHD_MASK (0xfff << 12 )
  18104. #define DENOISE3D2_PREGAMMA_Y_26_SHD_SHIFT 12U
  18105. #define DENOISE3D2_PREGAMMA_Y_25_SHD
  18106. #define DENOISE3D2_PREGAMMA_Y_25_SHD_MASK (0xfff << 0 )
  18107. #define DENOISE3D2_PREGAMMA_Y_25_SHD_SHIFT 0U
  18108. #define DENOISE3D2_PREGAMMA_Y_27_B_SHD
  18109. #define DENOISE3D2_PREGAMMA_Y_27_B_SHD_MASK (0x3f << 24 )
  18110. #define DENOISE3D2_PREGAMMA_Y_27_B_SHD_SHIFT 24U
  18111. #define DENOISE3D2_PREGAMMA_Y_29_SHD
  18112. #define DENOISE3D2_PREGAMMA_Y_29_SHD_MASK (0xfff << 12 )
  18113. #define DENOISE3D2_PREGAMMA_Y_29_SHD_SHIFT 12U
  18114. #define DENOISE3D2_PREGAMMA_Y_28_SHD
  18115. #define DENOISE3D2_PREGAMMA_Y_28_SHD_MASK (0xfff << 0 )
  18116. #define DENOISE3D2_PREGAMMA_Y_28_SHD_SHIFT 0U
  18117. #define DENOISE3D2_PREGAMMA_Y_32_A_SHD
  18118. #define DENOISE3D2_PREGAMMA_Y_32_A_SHD_MASK (0x3f << 24 )
  18119. #define DENOISE3D2_PREGAMMA_Y_32_A_SHD_SHIFT 24U
  18120. #define DENOISE3D2_PREGAMMA_Y_31_SHD
  18121. #define DENOISE3D2_PREGAMMA_Y_31_SHD_MASK (0xfff << 12 )
  18122. #define DENOISE3D2_PREGAMMA_Y_31_SHD_SHIFT 12U
  18123. #define DENOISE3D2_PREGAMMA_Y_30_SHD
  18124. #define DENOISE3D2_PREGAMMA_Y_30_SHD_MASK (0xfff << 0 )
  18125. #define DENOISE3D2_PREGAMMA_Y_30_SHD_SHIFT 0U
  18126. #define DENOISE3D2_PREGAMMA_Y_32_B_SHD
  18127. #define DENOISE3D2_PREGAMMA_Y_32_B_SHD_MASK (0x3f << 0 )
  18128. #define DENOISE3D2_PREGAMMA_Y_32_B_SHD_SHIFT 0U
  18129. #define DENOISE3D2_INVGAMMA_Y_2_A
  18130. #define DENOISE3D2_INVGAMMA_Y_2_A_MASK (0x3f << 24 )
  18131. #define DENOISE3D2_INVGAMMA_Y_2_A_SHIFT 24U
  18132. #define DENOISE3D2_INVGAMMA_Y_1
  18133. #define DENOISE3D2_INVGAMMA_Y_1_MASK (0xfff << 12 )
  18134. #define DENOISE3D2_INVGAMMA_Y_1_SHIFT 12U
  18135. #define DENOISE3D2_INVGAMMA_Y_0
  18136. #define DENOISE3D2_INVGAMMA_Y_0_MASK (0xfff << 0 )
  18137. #define DENOISE3D2_INVGAMMA_Y_0_SHIFT 0U
  18138. #define DENOISE3D2_INVGAMMA_Y_2_B
  18139. #define DENOISE3D2_INVGAMMA_Y_2_B_MASK (0x3f << 24 )
  18140. #define DENOISE3D2_INVGAMMA_Y_2_B_SHIFT 24U
  18141. #define DENOISE3D2_INVGAMMA_Y_4
  18142. #define DENOISE3D2_INVGAMMA_Y_4_MASK (0xfff << 12 )
  18143. #define DENOISE3D2_INVGAMMA_Y_4_SHIFT 12U
  18144. #define DENOISE3D2_INVGAMMA_Y_3
  18145. #define DENOISE3D2_INVGAMMA_Y_3_MASK (0xfff << 0 )
  18146. #define DENOISE3D2_INVGAMMA_Y_3_SHIFT 0U
  18147. #define DENOISE3D2_INVGAMMA_Y_7_A
  18148. #define DENOISE3D2_INVGAMMA_Y_7_A_MASK (0x3f << 24 )
  18149. #define DENOISE3D2_INVGAMMA_Y_7_A_SHIFT 24U
  18150. #define DENOISE3D2_INVGAMMA_Y_6
  18151. #define DENOISE3D2_INVGAMMA_Y_6_MASK (0xfff << 12 )
  18152. #define DENOISE3D2_INVGAMMA_Y_6_SHIFT 12U
  18153. #define DENOISE3D2_INVGAMMA_Y_5
  18154. #define DENOISE3D2_INVGAMMA_Y_5_MASK (0xfff << 0 )
  18155. #define DENOISE3D2_INVGAMMA_Y_5_SHIFT 0U
  18156. #define DENOISE3D2_INVGAMMA_Y_7_B
  18157. #define DENOISE3D2_INVGAMMA_Y_7_B_MASK (0x3f << 24 )
  18158. #define DENOISE3D2_INVGAMMA_Y_7_B_SHIFT 24U
  18159. #define DENOISE3D2_INVGAMMA_Y_9
  18160. #define DENOISE3D2_INVGAMMA_Y_9_MASK (0xfff << 12 )
  18161. #define DENOISE3D2_INVGAMMA_Y_9_SHIFT 12U
  18162. #define DENOISE3D2_INVGAMMA_Y_8
  18163. #define DENOISE3D2_INVGAMMA_Y_8_MASK (0xfff << 0 )
  18164. #define DENOISE3D2_INVGAMMA_Y_8_SHIFT 0U
  18165. #define DENOISE3D2_INVGAMMA_Y_12_A
  18166. #define DENOISE3D2_INVGAMMA_Y_12_A_MASK (0x3f << 24 )
  18167. #define DENOISE3D2_INVGAMMA_Y_12_A_SHIFT 24U
  18168. #define DENOISE3D2_INVGAMMA_Y_11
  18169. #define DENOISE3D2_INVGAMMA_Y_11_MASK (0xfff << 12 )
  18170. #define DENOISE3D2_INVGAMMA_Y_11_SHIFT 12U
  18171. #define DENOISE3D2_INVGAMMA_Y_10
  18172. #define DENOISE3D2_INVGAMMA_Y_10_MASK (0xfff << 0 )
  18173. #define DENOISE3D2_INVGAMMA_Y_10_SHIFT 0U
  18174. #define DENOISE3D2_INVGAMMA_Y_12_B
  18175. #define DENOISE3D2_INVGAMMA_Y_12_B_MASK (0x3f << 24 )
  18176. #define DENOISE3D2_INVGAMMA_Y_12_B_SHIFT 24U
  18177. #define DENOISE3D2_INVGAMMA_Y_14
  18178. #define DENOISE3D2_INVGAMMA_Y_14_MASK (0xfff << 12 )
  18179. #define DENOISE3D2_INVGAMMA_Y_14_SHIFT 12U
  18180. #define DENOISE3D2_INVGAMMA_Y_13
  18181. #define DENOISE3D2_INVGAMMA_Y_13_MASK (0xfff << 0 )
  18182. #define DENOISE3D2_INVGAMMA_Y_13_SHIFT 0U
  18183. #define DENOISE3D2_INVGAMMA_Y_17_A
  18184. #define DENOISE3D2_INVGAMMA_Y_17_A_MASK (0x3f << 24 )
  18185. #define DENOISE3D2_INVGAMMA_Y_17_A_SHIFT 24U
  18186. #define DENOISE3D2_INVGAMMA_Y_16
  18187. #define DENOISE3D2_INVGAMMA_Y_16_MASK (0xfff << 12 )
  18188. #define DENOISE3D2_INVGAMMA_Y_16_SHIFT 12U
  18189. #define DENOISE3D2_INVGAMMA_Y_15
  18190. #define DENOISE3D2_INVGAMMA_Y_15_MASK (0xfff << 0 )
  18191. #define DENOISE3D2_INVGAMMA_Y_15_SHIFT 0U
  18192. #define DENOISE3D2_INVGAMMA_Y_17_B
  18193. #define DENOISE3D2_INVGAMMA_Y_17_B_MASK (0x3f << 24 )
  18194. #define DENOISE3D2_INVGAMMA_Y_17_B_SHIFT 24U
  18195. #define DENOISE3D2_INVGAMMA_Y_19
  18196. #define DENOISE3D2_INVGAMMA_Y_19_MASK (0xfff << 12 )
  18197. #define DENOISE3D2_INVGAMMA_Y_19_SHIFT 12U
  18198. #define DENOISE3D2_INVGAMMA_Y_18
  18199. #define DENOISE3D2_INVGAMMA_Y_18_MASK (0xfff << 0 )
  18200. #define DENOISE3D2_INVGAMMA_Y_18_SHIFT 0U
  18201. #define DENOISE3D2_INVGAMMA_Y_22_A
  18202. #define DENOISE3D2_INVGAMMA_Y_22_A_MASK (0x3f << 24 )
  18203. #define DENOISE3D2_INVGAMMA_Y_22_A_SHIFT 24U
  18204. #define DENOISE3D2_INVGAMMA_Y_21
  18205. #define DENOISE3D2_INVGAMMA_Y_21_MASK (0xfff << 12 )
  18206. #define DENOISE3D2_INVGAMMA_Y_21_SHIFT 12U
  18207. #define DENOISE3D2_INVGAMMA_Y_20
  18208. #define DENOISE3D2_INVGAMMA_Y_20_MASK (0xfff << 0 )
  18209. #define DENOISE3D2_INVGAMMA_Y_20_SHIFT 0U
  18210. #define DENOISE3D2_INVGAMMA_Y_22_B
  18211. #define DENOISE3D2_INVGAMMA_Y_22_B_MASK (0x3f << 24 )
  18212. #define DENOISE3D2_INVGAMMA_Y_22_B_SHIFT 24U
  18213. #define DENOISE3D2_INVGAMMA_Y_24
  18214. #define DENOISE3D2_INVGAMMA_Y_24_MASK (0xfff << 12 )
  18215. #define DENOISE3D2_INVGAMMA_Y_24_SHIFT 12U
  18216. #define DENOISE3D2_INVGAMMA_Y_23
  18217. #define DENOISE3D2_INVGAMMA_Y_23_MASK (0xfff << 0 )
  18218. #define DENOISE3D2_INVGAMMA_Y_23_SHIFT 0U
  18219. #define DENOISE3D2_INVGAMMA_Y_27_A
  18220. #define DENOISE3D2_INVGAMMA_Y_27_A_MASK (0x3f << 24 )
  18221. #define DENOISE3D2_INVGAMMA_Y_27_A_SHIFT 24U
  18222. #define DENOISE3D2_INVGAMMA_Y_26
  18223. #define DENOISE3D2_INVGAMMA_Y_26_MASK (0xfff << 12 )
  18224. #define DENOISE3D2_INVGAMMA_Y_26_SHIFT 12U
  18225. #define DENOISE3D2_INVGAMMA_Y_25
  18226. #define DENOISE3D2_INVGAMMA_Y_25_MASK (0xfff << 0 )
  18227. #define DENOISE3D2_INVGAMMA_Y_25_SHIFT 0U
  18228. #define DENOISE3D2_INVGAMMA_Y_27_B
  18229. #define DENOISE3D2_INVGAMMA_Y_27_B_MASK (0x3f << 24 )
  18230. #define DENOISE3D2_INVGAMMA_Y_27_B_SHIFT 24U
  18231. #define DENOISE3D2_INVGAMMA_Y_29
  18232. #define DENOISE3D2_INVGAMMA_Y_29_MASK (0xfff << 12 )
  18233. #define DENOISE3D2_INVGAMMA_Y_29_SHIFT 12U
  18234. #define DENOISE3D2_INVGAMMA_Y_28
  18235. #define DENOISE3D2_INVGAMMA_Y_28_MASK (0xfff << 0 )
  18236. #define DENOISE3D2_INVGAMMA_Y_28_SHIFT 0U
  18237. #define DENOISE3D2_INVGAMMA_Y_32_A
  18238. #define DENOISE3D2_INVGAMMA_Y_32_A_MASK (0x3f << 24 )
  18239. #define DENOISE3D2_INVGAMMA_Y_32_A_SHIFT 24U
  18240. #define DENOISE3D2_INVGAMMA_Y_31
  18241. #define DENOISE3D2_INVGAMMA_Y_31_MASK (0xfff << 12 )
  18242. #define DENOISE3D2_INVGAMMA_Y_31_SHIFT 12U
  18243. #define DENOISE3D2_INVGAMMA_Y_30
  18244. #define DENOISE3D2_INVGAMMA_Y_30_MASK (0xfff << 0 )
  18245. #define DENOISE3D2_INVGAMMA_Y_30_SHIFT 0U
  18246. #define DENOISE3D2_INVGAMMA_Y_32_B
  18247. #define DENOISE3D2_INVGAMMA_Y_32_B_MASK (0x3f << 0 )
  18248. #define DENOISE3D2_INVGAMMA_Y_32_B_SHIFT 0U
  18249. #define DENOISE3D2_INVGAMMA_Y_2_A_SHD
  18250. #define DENOISE3D2_INVGAMMA_Y_2_A_SHD_MASK (0x3f << 24 )
  18251. #define DENOISE3D2_INVGAMMA_Y_2_A_SHD_SHIFT 24U
  18252. #define DENOISE3D2_INVGAMMA_Y_1_SHD
  18253. #define DENOISE3D2_INVGAMMA_Y_1_SHD_MASK (0xfff << 12 )
  18254. #define DENOISE3D2_INVGAMMA_Y_1_SHD_SHIFT 12U
  18255. #define DENOISE3D2_INVGAMMA_Y_0_SHD
  18256. #define DENOISE3D2_INVGAMMA_Y_0_SHD_MASK (0xfff << 0 )
  18257. #define DENOISE3D2_INVGAMMA_Y_0_SHD_SHIFT 0U
  18258. #define DENOISE3D2_INVGAMMA_Y_2_B_SHD
  18259. #define DENOISE3D2_INVGAMMA_Y_2_B_SHD_MASK (0x3f << 24 )
  18260. #define DENOISE3D2_INVGAMMA_Y_2_B_SHD_SHIFT 24U
  18261. #define DENOISE3D2_INVGAMMA_Y_4_SHD
  18262. #define DENOISE3D2_INVGAMMA_Y_4_SHD_MASK (0xfff << 12 )
  18263. #define DENOISE3D2_INVGAMMA_Y_4_SHD_SHIFT 12U
  18264. #define DENOISE3D2_INVGAMMA_Y_3_SHD
  18265. #define DENOISE3D2_INVGAMMA_Y_3_SHD_MASK (0xfff << 0 )
  18266. #define DENOISE3D2_INVGAMMA_Y_3_SHD_SHIFT 0U
  18267. #define DENOISE3D2_INVGAMMA_Y_7_A_SHD
  18268. #define DENOISE3D2_INVGAMMA_Y_7_A_SHD_MASK (0x3f << 24 )
  18269. #define DENOISE3D2_INVGAMMA_Y_7_A_SHD_SHIFT 24U
  18270. #define DENOISE3D2_INVGAMMA_Y_6_SHD
  18271. #define DENOISE3D2_INVGAMMA_Y_6_SHD_MASK (0xfff << 12 )
  18272. #define DENOISE3D2_INVGAMMA_Y_6_SHD_SHIFT 12U
  18273. #define DENOISE3D2_INVGAMMA_Y_5_SHD
  18274. #define DENOISE3D2_INVGAMMA_Y_5_SHD_MASK (0xfff << 0 )
  18275. #define DENOISE3D2_INVGAMMA_Y_5_SHD_SHIFT 0U
  18276. #define DENOISE3D2_INVGAMMA_Y_7_B_SHD
  18277. #define DENOISE3D2_INVGAMMA_Y_7_B_SHD_MASK (0x3f << 24 )
  18278. #define DENOISE3D2_INVGAMMA_Y_7_B_SHD_SHIFT 24U
  18279. #define DENOISE3D2_INVGAMMA_Y_9_SHD
  18280. #define DENOISE3D2_INVGAMMA_Y_9_SHD_MASK (0xfff << 12 )
  18281. #define DENOISE3D2_INVGAMMA_Y_9_SHD_SHIFT 12U
  18282. #define DENOISE3D2_INVGAMMA_Y_8_SHD
  18283. #define DENOISE3D2_INVGAMMA_Y_8_SHD_MASK (0xfff << 0 )
  18284. #define DENOISE3D2_INVGAMMA_Y_8_SHD_SHIFT 0U
  18285. #define DENOISE3D2_INVGAMMA_Y_12_A_SHD
  18286. #define DENOISE3D2_INVGAMMA_Y_12_A_SHD_MASK (0x3f << 24 )
  18287. #define DENOISE3D2_INVGAMMA_Y_12_A_SHD_SHIFT 24U
  18288. #define DENOISE3D2_INVGAMMA_Y_11_SHD
  18289. #define DENOISE3D2_INVGAMMA_Y_11_SHD_MASK (0xfff << 12 )
  18290. #define DENOISE3D2_INVGAMMA_Y_11_SHD_SHIFT 12U
  18291. #define DENOISE3D2_INVGAMMA_Y_10_SHD
  18292. #define DENOISE3D2_INVGAMMA_Y_10_SHD_MASK (0xfff << 0 )
  18293. #define DENOISE3D2_INVGAMMA_Y_10_SHD_SHIFT 0U
  18294. #define DENOISE3D2_INVGAMMA_Y_12_B_SHD
  18295. #define DENOISE3D2_INVGAMMA_Y_12_B_SHD_MASK (0x3f << 24 )
  18296. #define DENOISE3D2_INVGAMMA_Y_12_B_SHD_SHIFT 24U
  18297. #define DENOISE3D2_INVGAMMA_Y_14_SHD
  18298. #define DENOISE3D2_INVGAMMA_Y_14_SHD_MASK (0xfff << 12 )
  18299. #define DENOISE3D2_INVGAMMA_Y_14_SHD_SHIFT 12U
  18300. #define DENOISE3D2_INVGAMMA_Y_13_SHD
  18301. #define DENOISE3D2_INVGAMMA_Y_13_SHD_MASK (0xfff << 0 )
  18302. #define DENOISE3D2_INVGAMMA_Y_13_SHD_SHIFT 0U
  18303. #define DENOISE3D2_INVGAMMA_Y_17_A_SHD
  18304. #define DENOISE3D2_INVGAMMA_Y_17_A_SHD_MASK (0x3f << 24 )
  18305. #define DENOISE3D2_INVGAMMA_Y_17_A_SHD_SHIFT 24U
  18306. #define DENOISE3D2_INVGAMMA_Y_16_SHD
  18307. #define DENOISE3D2_INVGAMMA_Y_16_SHD_MASK (0xfff << 12 )
  18308. #define DENOISE3D2_INVGAMMA_Y_16_SHD_SHIFT 12U
  18309. #define DENOISE3D2_INVGAMMA_Y_15_SHD
  18310. #define DENOISE3D2_INVGAMMA_Y_15_SHD_MASK (0xfff << 0 )
  18311. #define DENOISE3D2_INVGAMMA_Y_15_SHD_SHIFT 0U
  18312. #define DENOISE3D2_INVGAMMA_Y_17_B_SHD
  18313. #define DENOISE3D2_INVGAMMA_Y_17_B_SHD_MASK (0x3f << 24 )
  18314. #define DENOISE3D2_INVGAMMA_Y_17_B_SHD_SHIFT 24U
  18315. #define DENOISE3D2_INVGAMMA_Y_19_SHD
  18316. #define DENOISE3D2_INVGAMMA_Y_19_SHD_MASK (0xfff << 12 )
  18317. #define DENOISE3D2_INVGAMMA_Y_19_SHD_SHIFT 12U
  18318. #define DENOISE3D2_INVGAMMA_Y_18_SHD
  18319. #define DENOISE3D2_INVGAMMA_Y_18_SHD_MASK (0xfff << 0 )
  18320. #define DENOISE3D2_INVGAMMA_Y_18_SHD_SHIFT 0U
  18321. #define DENOISE3D2_INVGAMMA_Y_22_A_SHD
  18322. #define DENOISE3D2_INVGAMMA_Y_22_A_SHD_MASK (0x3f << 24 )
  18323. #define DENOISE3D2_INVGAMMA_Y_22_A_SHD_SHIFT 24U
  18324. #define DENOISE3D2_INVGAMMA_Y_21_SHD
  18325. #define DENOISE3D2_INVGAMMA_Y_21_SHD_MASK (0xfff << 12 )
  18326. #define DENOISE3D2_INVGAMMA_Y_21_SHD_SHIFT 12U
  18327. #define DENOISE3D2_INVGAMMA_Y_20_SHD
  18328. #define DENOISE3D2_INVGAMMA_Y_20_SHD_MASK (0xfff << 0 )
  18329. #define DENOISE3D2_INVGAMMA_Y_20_SHD_SHIFT 0U
  18330. #define DENOISE3D2_INVGAMMA_Y_22_B_SHD
  18331. #define DENOISE3D2_INVGAMMA_Y_22_B_SHD_MASK (0x3f << 24 )
  18332. #define DENOISE3D2_INVGAMMA_Y_22_B_SHD_SHIFT 24U
  18333. #define DENOISE3D2_INVGAMMA_Y_24_SHD
  18334. #define DENOISE3D2_INVGAMMA_Y_24_SHD_MASK (0xfff << 12 )
  18335. #define DENOISE3D2_INVGAMMA_Y_24_SHD_SHIFT 12U
  18336. #define DENOISE3D2_INVGAMMA_Y_23_SHD
  18337. #define DENOISE3D2_INVGAMMA_Y_23_SHD_MASK (0xfff << 0 )
  18338. #define DENOISE3D2_INVGAMMA_Y_23_SHD_SHIFT 0U
  18339. #define DENOISE3D2_INVGAMMA_Y_27_A_SHD
  18340. #define DENOISE3D2_INVGAMMA_Y_27_A_SHD_MASK (0x3f << 24 )
  18341. #define DENOISE3D2_INVGAMMA_Y_27_A_SHD_SHIFT 24U
  18342. #define DENOISE3D2_INVGAMMA_Y_26_SHD
  18343. #define DENOISE3D2_INVGAMMA_Y_26_SHD_MASK (0xfff << 12 )
  18344. #define DENOISE3D2_INVGAMMA_Y_26_SHD_SHIFT 12U
  18345. #define DENOISE3D2_INVGAMMA_Y_25_SHD
  18346. #define DENOISE3D2_INVGAMMA_Y_25_SHD_MASK (0xfff << 0 )
  18347. #define DENOISE3D2_INVGAMMA_Y_25_SHD_SHIFT 0U
  18348. #define DENOISE3D2_INVGAMMA_Y_27_B_SHD
  18349. #define DENOISE3D2_INVGAMMA_Y_27_B_SHD_MASK (0x3f << 24 )
  18350. #define DENOISE3D2_INVGAMMA_Y_27_B_SHD_SHIFT 24U
  18351. #define DENOISE3D2_INVGAMMA_Y_29_SHD
  18352. #define DENOISE3D2_INVGAMMA_Y_29_SHD_MASK (0xfff << 12 )
  18353. #define DENOISE3D2_INVGAMMA_Y_29_SHD_SHIFT 12U
  18354. #define DENOISE3D2_INVGAMMA_Y_28_SHD
  18355. #define DENOISE3D2_INVGAMMA_Y_28_SHD_MASK (0xfff << 0 )
  18356. #define DENOISE3D2_INVGAMMA_Y_28_SHD_SHIFT 0U
  18357. #define DENOISE3D2_INVGAMMA_Y_32_A_SHD
  18358. #define DENOISE3D2_INVGAMMA_Y_32_A_SHD_MASK (0x3f << 24 )
  18359. #define DENOISE3D2_INVGAMMA_Y_32_A_SHD_SHIFT 24U
  18360. #define DENOISE3D2_INVGAMMA_Y_31_SHD
  18361. #define DENOISE3D2_INVGAMMA_Y_31_SHD_MASK (0xfff << 12 )
  18362. #define DENOISE3D2_INVGAMMA_Y_31_SHD_SHIFT 12U
  18363. #define DENOISE3D2_INVGAMMA_Y_30_SHD
  18364. #define DENOISE3D2_INVGAMMA_Y_30_SHD_MASK (0xfff << 0 )
  18365. #define DENOISE3D2_INVGAMMA_Y_30_SHD_SHIFT 0U
  18366. #define DENOISE3D2_INVGAMMA_Y_32_B_SHD
  18367. #define DENOISE3D2_INVGAMMA_Y_32_B_SHD_MASK (0x3f << 0 )
  18368. #define DENOISE3D2_INVGAMMA_Y_32_B_SHD_SHIFT 0U
  18369. #define DENOISE3D2_NLM_STRENGTH_SLOPE
  18370. #define DENOISE3D2_NLM_STRENGTH_SLOPE_MASK (0xff << 0 )
  18371. #define DENOISE3D2_NLM_STRENGTH_SLOPE_SHIFT 0U
  18372. #define DENOISE3D2_TNR
  18373. #define DENOISE3D2_TNR_MASK (0x7ff << 0 )
  18374. #define DENOISE3D2_TNR_SHIFT 0U
  18375. #define PP_RD_YUV_CFG_UPDATE
  18376. #define PP_RD_YUV_CFG_UPDATE_MASK 0x1 << 7
  18377. #define PP_RD_YUV_CFG_UPDATE_SHIFT 7U
  18378. #define PP_RD_YUV_AUTO_UPDATE
  18379. #define PP_RD_YUV_AUTO_UPDATE_MASK 0x1 << 6
  18380. #define PP_RD_YUV_AUTO_UPDATE_SHIFT 6U
  18381. #define PP_INIT_OFFSET_EN
  18382. #define PP_INIT_OFFSET_EN_MASK 0x1 << 5
  18383. #define PP_INIT_OFFSET_EN_SHIFT 5U
  18384. #define PP_INIT_BASE_EN
  18385. #define PP_INIT_BASE_EN_MASK 0x1 << 4
  18386. #define PP_INIT_BASE_EN_SHIFT 4U
  18387. #define PP_MI_CFG_UPD
  18388. #define PP_MI_CFG_UPD_MASK 0x1 << 3
  18389. #define PP_MI_CFG_UPD_SHIFT 3U
  18390. #define PP_MI_SKIP
  18391. #define PP_MI_SKIP_MASK 0x1 << 2
  18392. #define PP_MI_SKIP_SHIFT 2U
  18393. #define PP_AUTO_UPDATE
  18394. #define PP_AUTO_UPDATE_MASK 0x1 << 1
  18395. #define PP_AUTO_UPDATE_SHIFT 1U
  18396. #define PP_PINGPONG_ENABLE
  18397. #define PP_PINGPONG_ENABLE_MASK 0x1 << 0
  18398. #define PP_PINGPONG_ENABLE_SHIFT 0U
  18399. #define PP_RD_RAW_ENABLE
  18400. #define PP_RD_RAW_ENABLE_MASK 0x1 << 31
  18401. #define PP_RD_RAW_ENABLE_SHIFT 31U
  18402. #define PP_RD_RAW_ALIGNED
  18403. #define PP_RD_RAW_ALIGNED_MASK (0x3 << 29 )
  18404. #define PP_RD_RAW_ALIGNED_SHIFT 29U
  18405. #define PP_RD_RAW_BIT
  18406. #define PP_RD_RAW_BIT_MASK (0x7 << 26 )
  18407. #define PP_RD_RAW_BIT_SHIFT 26U
  18408. #define PP_RD_YUV_NVY
  18409. #define PP_RD_YUV_NVY_MASK (0x3 << 24 )
  18410. #define PP_RD_YUV_NVY_SHIFT 24U
  18411. #define PP_RD_YUV_NV21
  18412. #define PP_RD_YUV_NV21_MASK 0x1 << 23
  18413. #define PP_RD_YUV_NV21_SHIFT 23U
  18414. #define PP_RD_YUV_ALIGNED
  18415. #define PP_RD_YUV_ALIGNED_MASK 0x1 << 22
  18416. #define PP_RD_YUV_ALIGNED_SHIFT 22U
  18417. #define PP_RD_YUV_STR
  18418. #define PP_RD_YUV_STR_MASK (0x3 << 20 )
  18419. #define PP_RD_YUV_STR_SHIFT 20U
  18420. #define PP_RD_YUV_FMT
  18421. #define PP_RD_YUV_FMT_MASK (0x3 << 18 )
  18422. #define PP_RD_YUV_FMT_SHIFT 18U
  18423. #define PP_RD_YUV_BIT
  18424. #define PP_RD_YUV_BIT_MASK 0x1 << 17
  18425. #define PP_RD_YUV_BIT_SHIFT 17U
  18426. #define PP_WR_RAW_SEL
  18427. #define PP_WR_RAW_SEL_MASK 0x1 << 16
  18428. #define PP_WR_RAW_SEL_SHIFT 16U
  18429. #define PP_WR_RAW_ALIGNED
  18430. #define PP_WR_RAW_ALIGNED_MASK (0x3 << 14 )
  18431. #define PP_WR_RAW_ALIGNED_SHIFT 14U
  18432. #define PP_WR_RAW_BIT
  18433. #define PP_WR_RAW_BIT_MASK (0x7 << 11 )
  18434. #define PP_WR_RAW_BIT_SHIFT 11U
  18435. #define PP_WR_YUV_WORD_ALIGNED_MSB_EN
  18436. #define PP_WR_YUV_WORD_ALIGNED_MSB_EN_MASK 0x1 << 10
  18437. #define PP_WR_YUV_WORD_ALIGNED_MSB_EN_SHIFT 10U
  18438. #define PP_WR_YUV_WORD_ALIGNED
  18439. #define PP_WR_YUV_WORD_ALIGNED_MASK 0x1 << 9
  18440. #define PP_WR_YUV_WORD_ALIGNED_SHIFT 9U
  18441. #define PP_WR_YUV_NVY
  18442. #define PP_WR_YUV_NVY_MASK (0x3 << 7 )
  18443. #define PP_WR_YUV_NVY_SHIFT 7U
  18444. #define PP_WR_YUV_NV21
  18445. #define PP_WR_YUV_NV21_MASK 0x1 << 6
  18446. #define PP_WR_YUV_NV21_SHIFT 6U
  18447. #define PP_WR_YUV_ALIGNED
  18448. #define PP_WR_YUV_ALIGNED_MASK 0x1 << 5
  18449. #define PP_WR_YUV_ALIGNED_SHIFT 5U
  18450. #define PP_WR_YUV_STR
  18451. #define PP_WR_YUV_STR_MASK (0x3 << 3 )
  18452. #define PP_WR_YUV_STR_SHIFT 3U
  18453. #define PP_WR_YUV_FMT
  18454. #define PP_WR_YUV_FMT_MASK (0x3 << 1 )
  18455. #define PP_WR_YUV_FMT_SHIFT 1U
  18456. #define PP_WR_YUV_BIT
  18457. #define PP_WR_YUV_BIT_MASK 0x1 << 0
  18458. #define PP_WR_YUV_BIT_SHIFT 0U
  18459. #define PP_RD_SWAP_V
  18460. #define PP_RD_SWAP_V_MASK 0xf << 24
  18461. #define PP_RD_SWAP_V_SHIFT 24U
  18462. #define PP_RD_SWAP_U
  18463. #define PP_RD_SWAP_U_MASK 0xf << 20
  18464. #define PP_RD_SWAP_U_SHIFT 20U
  18465. #define PP_RD_SWAP_Y
  18466. #define PP_RD_SWAP_Y_MASK 0xf << 16
  18467. #define PP_RD_SWAP_Y_SHIFT 16U
  18468. #define PP_WR_SWAP_V
  18469. #define PP_WR_SWAP_V_MASK 0xf << 8
  18470. #define PP_WR_SWAP_V_SHIFT 8U
  18471. #define PP_WR_SWAP_U
  18472. #define PP_WR_SWAP_U_MASK 0xf << 4
  18473. #define PP_WR_SWAP_U_SHIFT 4U
  18474. #define PP_WR_SWAP_Y
  18475. #define PP_WR_SWAP_Y_MASK 0xf << 0
  18476. #define PP_WR_SWAP_Y_SHIFT 0U
  18477. #define PP_Y_BASE_AD_INIT
  18478. #define PP_Y_BASE_AD_INIT_MASK (0xfffffff << 4 )
  18479. #define PP_Y_BASE_AD_INIT_SHIFT 4U
  18480. #define PP_Y_SIZE_INIT
  18481. #define PP_Y_SIZE_INIT_MASK (0x1ffffff << 4 )
  18482. #define PP_Y_SIZE_INIT_SHIFT 4U
  18483. #define PP_Y_OFFS_CNT_INIT
  18484. #define PP_Y_OFFS_CNT_INIT_MASK (0x1ffffff << 4 )
  18485. #define PP_Y_OFFS_CNT_INIT_SHIFT 4U
  18486. #define PP_Y_LLENGH
  18487. #define PP_Y_LLENGH_MASK (0xffffffff << 0 )
  18488. #define PP_Y_LLENGH_SHIFT 0U
  18489. #define PP_Y_PIC_WIDTH
  18490. #define PP_Y_PIC_WIDTH_MASK (0xffffffff << 0 )
  18491. #define PP_Y_PIC_WIDTH_SHIFT 0U
  18492. #define PP_Y_PIC_HEIGHT
  18493. #define PP_Y_PIC_HEIGHT_MASK (0xffffffff << 0 )
  18494. #define PP_Y_PIC_HEIGHT_SHIFT 0U
  18495. #define PP_Y_PIC_SIZE
  18496. #define PP_Y_PIC_SIZE_MASK (0xffffffff << 0 )
  18497. #define PP_Y_PIC_SIZE_SHIFT 0U
  18498. #define PP_CB_BASE_AD_INIT
  18499. #define PP_CB_BASE_AD_INIT_MASK (0xfffffff << 4 )
  18500. #define PP_CB_BASE_AD_INIT_SHIFT 4U
  18501. #define PP_CB_SIZE_INIT
  18502. #define PP_CB_SIZE_INIT_MASK (0xffffff << 4 )
  18503. #define PP_CB_SIZE_INIT_SHIFT 4U
  18504. #define PP_CB_OFFS_CNT_INIT
  18505. #define PP_CB_OFFS_CNT_INIT_MASK (0xffffff << 4 )
  18506. #define PP_CB_OFFS_CNT_INIT_SHIFT 4U
  18507. #define PP_CR_BASE_AD_INIT
  18508. #define PP_CR_BASE_AD_INIT_MASK (0xfffffff << 4 )
  18509. #define PP_CR_BASE_AD_INIT_SHIFT 4U
  18510. #define PP_CR_SIZE_INIT
  18511. #define PP_CR_SIZE_INIT_MASK (0xffffff << 4 )
  18512. #define PP_CR_SIZE_INIT_SHIFT 4U
  18513. #define PP_CR_OFFS_CNT_INIT
  18514. #define PP_CR_OFFS_CNT_INIT_MASK (0xffffff << 4 )
  18515. #define PP_CR_OFFS_CNT_INIT_SHIFT 4U
  18516. #define PP_Y_BASE_AD_INIT2
  18517. #define PP_Y_BASE_AD_INIT2_MASK (0xfffffff << 4 )
  18518. #define PP_Y_BASE_AD_INIT2_SHIFT 4U
  18519. #define PP_CB_BASE_AD_INIT2
  18520. #define PP_CB_BASE_AD_INIT2_MASK (0xfffffff << 4 )
  18521. #define PP_CB_BASE_AD_INIT2_SHIFT 4U
  18522. #define PP_CR_BASE_AD_INIT2
  18523. #define PP_CR_BASE_AD_INIT2_MASK (0xfffffff << 4 )
  18524. #define PP_CR_BASE_AD_INIT2_SHIFT 4U
  18525. #define PP_Y_OFFS_CNT_START
  18526. #define PP_Y_OFFS_CNT_START_MASK (0x1ffffff << 4 )
  18527. #define PP_Y_OFFS_CNT_START_SHIFT 4U
  18528. #define PP_CB_OFFS_CNT_START
  18529. #define PP_CB_OFFS_CNT_START_MASK (0xffffff << 4 )
  18530. #define PP_CB_OFFS_CNT_START_SHIFT 4U
  18531. #define PP_CR_OFFS_CNT_START
  18532. #define PP_CR_OFFS_CNT_START_MASK (0xffffff << 4 )
  18533. #define PP_CR_OFFS_CNT_START_SHIFT 4U
  18534. #define PP_Y_BASE_AD
  18535. #define PP_Y_BASE_AD_MASK (0xfffffff << 4 )
  18536. #define PP_Y_BASE_AD_SHIFT 4U
  18537. #define PP_Y_SIZE
  18538. #define PP_Y_SIZE_MASK (0x1ffffff << 4 )
  18539. #define PP_Y_SIZE_SHIFT 4U
  18540. #define PP_Y_OFFS_CNT
  18541. #define PP_Y_OFFS_CNT_MASK (0x1ffffff << 4 )
  18542. #define PP_Y_OFFS_CNT_SHIFT 4U
  18543. #define PP_CB_BASE_AD
  18544. #define PP_CB_BASE_AD_MASK (0xfffffff << 4 )
  18545. #define PP_CB_BASE_AD_SHIFT 4U
  18546. #define PP_CB_SIZE
  18547. #define PP_CB_SIZE_MASK (0xffffff << 4 )
  18548. #define PP_CB_SIZE_SHIFT 4U
  18549. #define PP_CB_OFFS_CNT
  18550. #define PP_CB_OFFS_CNT_MASK (0xffffff << 4 )
  18551. #define PP_CB_OFFS_CNT_SHIFT 4U
  18552. #define PP_CR_BASE_AD
  18553. #define PP_CR_BASE_AD_MASK (0xfffffff << 4 )
  18554. #define PP_CR_BASE_AD_SHIFT 4U
  18555. #define PP_CR_SIZE
  18556. #define PP_CR_SIZE_MASK (0xffffff << 4 )
  18557. #define PP_CR_SIZE_SHIFT 4U
  18558. #define PP_CR_OFFS_CNT
  18559. #define PP_CR_OFFS_CNT_MASK (0xffffff << 4 )
  18560. #define PP_CR_OFFS_CNT_SHIFT 4U
  18561. #define PP_DMA_Y_PIC_WIDTH
  18562. #define PP_DMA_Y_PIC_WIDTH_MASK (0x7fff << 0 )
  18563. #define PP_DMA_Y_PIC_WIDTH_SHIFT 0U
  18564. #define PP_DMA_Y_PIC_LLENGTH
  18565. #define PP_DMA_Y_PIC_LLENGTH_MASK (0xffffffff << 0 )
  18566. #define PP_DMA_Y_PIC_LLENGTH_SHIFT 0U
  18567. #define PP_DMA_Y_PIC_SIZE
  18568. #define PP_DMA_Y_PIC_SIZE_MASK (0xfffffff << 0 )
  18569. #define PP_DMA_Y_PIC_SIZE_SHIFT 0U
  18570. #define PP_DMA_CB_PIC_START_AD
  18571. #define PP_DMA_CB_PIC_START_AD_MASK (0xfffffff << 4 )
  18572. #define PP_DMA_CB_PIC_START_AD_SHIFT 4U
  18573. #define PP_DMA_CR_PIC_START_AD
  18574. #define PP_DMA_CR_PIC_START_AD_MASK (0xfffffff << 4 )
  18575. #define PP_DMA_CR_PIC_START_AD_SHIFT 4U
  18576. #define PP_DMA_Y_PIC_START_AD
  18577. #define PP_DMA_Y_PIC_START_AD_MASK (0xfffffff << 4 )
  18578. #define PP_DMA_Y_PIC_START_AD_SHIFT 4U
  18579. #define PP_DMA_CB_PIC_START_AD
  18580. #define PP_DMA_CB_PIC_START_AD_MASK (0xfffffff << 4 )
  18581. #define PP_DMA_CB_PIC_START_AD_SHIFT 4U
  18582. #define PP_DMA_CR_PIC_START_AD
  18583. #define PP_DMA_CR_PIC_START_AD_MASK (0xfffffff << 4 )
  18584. #define PP_DMA_CR_PIC_START_AD_SHIFT 4U
  18585. #define PP_DMA_Y_PIC_LVAL
  18586. #define PP_DMA_Y_PIC_LVAL_MASK (0xffff << 0 )
  18587. #define PP_DMA_Y_PIC_LVAL_SHIFT 0U
  18588. #define HDR_DMA_START_CONTINUOUS
  18589. #define HDR_DMA_START_CONTINUOUS_MASK 0x1 << 8
  18590. #define HDR_DMA_START_CONTINUOUS_SHIFT 8U
  18591. #define HDR_DMA_START
  18592. #define HDR_DMA_START_MASK 0x1 << 7
  18593. #define HDR_DMA_START_SHIFT 7U
  18594. #define HDR_WR_ENABLE
  18595. #define HDR_WR_ENABLE_MASK 0x1 << 6
  18596. #define HDR_WR_ENABLE_SHIFT 6U
  18597. #define HDR_RD_RAW_CFG_UPDATE
  18598. #define HDR_RD_RAW_CFG_UPDATE_MASK 0x1 << 5
  18599. #define HDR_RD_RAW_CFG_UPDATE_SHIFT 5U
  18600. #define HDR_RD_RAW_AUTO_UPDATE
  18601. #define HDR_RD_RAW_AUTO_UPDATE_MASK 0x1 << 4
  18602. #define HDR_RD_RAW_AUTO_UPDATE_SHIFT 4U
  18603. #define HDR_INIT_OFFSET_EN
  18604. #define HDR_INIT_OFFSET_EN_MASK 0x1 << 3
  18605. #define HDR_INIT_OFFSET_EN_SHIFT 3U
  18606. #define HDR_INIT_BASE_EN
  18607. #define HDR_INIT_BASE_EN_MASK 0x1 << 2
  18608. #define HDR_INIT_BASE_EN_SHIFT 2U
  18609. #define HDR_MI_CFG_UPD
  18610. #define HDR_MI_CFG_UPD_MASK 0x1 << 1
  18611. #define HDR_MI_CFG_UPD_SHIFT 1U
  18612. #define HDR_AUTO_UPDATE
  18613. #define HDR_AUTO_UPDATE_MASK 0x1 << 0
  18614. #define HDR_AUTO_UPDATE_SHIFT 0U
  18615. #define HDR_RD_RAW_ALIGNED
  18616. #define HDR_RD_RAW_ALIGNED_MASK (0x3 << 24 )
  18617. #define HDR_RD_RAW_ALIGNED_SHIFT 24U
  18618. #define HDR_RD_VS_BIT
  18619. #define HDR_RD_VS_BIT_MASK (0x3 << 22 )
  18620. #define HDR_RD_VS_BIT_SHIFT 22U
  18621. #define HDR_RD_S_BIT
  18622. #define HDR_RD_S_BIT_MASK (0x3 << 20 )
  18623. #define HDR_RD_S_BIT_SHIFT 20U
  18624. #define HDR_RD_L_BIT
  18625. #define HDR_RD_L_BIT_MASK (0x3 << 18 )
  18626. #define HDR_RD_L_BIT_SHIFT 18U
  18627. #define HDR_RD_STR
  18628. #define HDR_RD_STR_MASK (0x3 << 16 )
  18629. #define HDR_RD_STR_SHIFT 16U
  18630. #define HDR_WR_RAW_ALIGNED
  18631. #define HDR_WR_RAW_ALIGNED_MASK (0x3 << 8 )
  18632. #define HDR_WR_RAW_ALIGNED_SHIFT 8U
  18633. #define HDR_WR_VS_BIT
  18634. #define HDR_WR_VS_BIT_MASK (0x3 << 6 )
  18635. #define HDR_WR_VS_BIT_SHIFT 6U
  18636. #define HDR_WR_S_BIT
  18637. #define HDR_WR_S_BIT_MASK (0x3 << 4 )
  18638. #define HDR_WR_S_BIT_SHIFT 4U
  18639. #define HDR_WR_L_BIT
  18640. #define HDR_WR_L_BIT_MASK (0x3 << 2 )
  18641. #define HDR_WR_L_BIT_SHIFT 2U
  18642. #define HDR_WR_STR
  18643. #define HDR_WR_STR_MASK (0x3 << 0 )
  18644. #define HDR_WR_STR_SHIFT 0U
  18645. #define HDR_DMA_START_BY_LINES
  18646. #define HDR_DMA_START_BY_LINES_MASK (0xffff << 0 )
  18647. #define HDR_DMA_START_BY_LINES_SHIFT 0U
  18648. #define HDR_RD_SWAP_RAW
  18649. #define HDR_RD_SWAP_RAW_MASK (0xf << 16 )
  18650. #define HDR_RD_SWAP_RAW_SHIFT 16U
  18651. #define HDR_WR_SWAP_RAW
  18652. #define HDR_WR_SWAP_RAW_MASK (0xf << 0 )
  18653. #define HDR_WR_SWAP_RAW_SHIFT 0U
  18654. #define HDR_BUS_SW_EN
  18655. #define HDR_BUS_SW_EN_MASK 0x1 << 23
  18656. #define HDR_BUS_SW_EN_SHIFT 23U
  18657. #define HDR_RD_BURST_LEN
  18658. #define HDR_RD_BURST_LEN_MASK (0x3 << 21 )
  18659. #define HDR_RD_BURST_LEN_SHIFT 21U
  18660. #define HDR_WR_BURST_LEN
  18661. #define HDR_WR_BURST_LEN_MASK (0x3 << 19 )
  18662. #define HDR_WR_BURST_LEN_SHIFT 19U
  18663. #define HDR_RD_ID_EN
  18664. #define HDR_RD_ID_EN_MASK 0x1 << 18
  18665. #define HDR_RD_ID_EN_SHIFT 18U
  18666. #define HDR_RD_ID_CFG
  18667. #define HDR_RD_ID_CFG_MASK (0xff << 10 )
  18668. #define HDR_RD_ID_CFG_SHIFT 10U
  18669. #define HDR_WR_ID_EN
  18670. #define HDR_WR_ID_EN_MASK 0x1 << 8
  18671. #define HDR_WR_ID_EN_SHIFT 8U
  18672. #define HDR_WR_ID_CFG
  18673. #define HDR_WR_ID_CFG_MASK (0xff << 0 )
  18674. #define HDR_WR_ID_CFG_SHIFT 0U
  18675. #define HDR_BUS_TIMEO_EN
  18676. #define HDR_BUS_TIMEO_EN_MASK 0x1 << 31
  18677. #define HDR_BUS_TIMEO_EN_SHIFT 31U
  18678. #define HDR_BUS_TIMEO
  18679. #define HDR_BUS_TIMEO_MASK (0x7fffffff << 0 )
  18680. #define HDR_BUS_TIMEO_SHIFT 0U
  18681. #define HDR_L_PIC_WIDTH
  18682. #define HDR_L_PIC_WIDTH_MASK (0xffffffff << 0 )
  18683. #define HDR_L_PIC_WIDTH_SHIFT 0U
  18684. #define HDR_L_PIC_HEIGHT
  18685. #define HDR_L_PIC_HEIGHT_MASK (0xffffffff << 0 )
  18686. #define HDR_L_PIC_HEIGHT_SHIFT 0U
  18687. #define HDR_L_BASE_AD_INIT
  18688. #define HDR_L_BASE_AD_INIT_MASK (0xfffffff << 4 )
  18689. #define HDR_L_BASE_AD_INIT_SHIFT 4U
  18690. #define HDR_L_SIZE_INIT
  18691. #define HDR_L_SIZE_INIT_MASK (0x1ffffff << 4 )
  18692. #define HDR_L_SIZE_INIT_SHIFT 4U
  18693. #define HDR_L_OFFS_CNT_INIT
  18694. #define HDR_L_OFFS_CNT_INIT_MASK (0x1ffffff << 4 )
  18695. #define HDR_L_OFFS_CNT_INIT_SHIFT 4U
  18696. #define HDR_L_LLENGTH
  18697. #define HDR_L_LLENGTH_MASK (0xffffffff << 0 )
  18698. #define HDR_L_LLENGTH_SHIFT 0U
  18699. #define HDR_L_PIC_LVAL
  18700. #define HDR_L_PIC_LVAL_MASK (0xffff << 0 )
  18701. #define HDR_L_PIC_LVAL_SHIFT 0U
  18702. #define HDR_L_IRQ_OFFS_INIT
  18703. #define HDR_L_IRQ_OFFS_INIT_MASK (0xffffffff << 0 )
  18704. #define HDR_L_IRQ_OFFS_INIT_SHIFT 0U
  18705. #define HDR_L_OFFS_CNT_START
  18706. #define HDR_L_OFFS_CNT_START_MASK (0x1ffffff << 4 )
  18707. #define HDR_L_OFFS_CNT_START_SHIFT 4U
  18708. #define HDR_L_BASE_AD_SHD
  18709. #define HDR_L_BASE_AD_SHD_MASK (0xfffffff << 4 )
  18710. #define HDR_L_BASE_AD_SHD_SHIFT 4U
  18711. #define HDR_L_SIZE_SHD
  18712. #define HDR_L_SIZE_SHD_MASK (0x1ffffff << 4 )
  18713. #define HDR_L_SIZE_SHD_SHIFT 4U
  18714. #define HDR_L_OFFS_CNT
  18715. #define HDR_L_OFFS_CNT_MASK (0x1ffffff << 4 )
  18716. #define HDR_L_OFFS_CNT_SHIFT 4U
  18717. #define HDR_L_IRQ_OFFS_SHD
  18718. #define HDR_L_IRQ_OFFS_SHD_MASK (0xffffffff << 0 )
  18719. #define HDR_L_IRQ_OFFS_SHD_SHIFT 0U
  18720. #define HDR_S_BASE_AD_INIT
  18721. #define HDR_S_BASE_AD_INIT_MASK (0xfffffff << 4 )
  18722. #define HDR_S_BASE_AD_INIT_SHIFT 4U
  18723. #define HDR_S_SIZE_INIT
  18724. #define HDR_S_SIZE_INIT_MASK (0x1ffffff << 4 )
  18725. #define HDR_S_SIZE_INIT_SHIFT 4U
  18726. #define HDR_S_OFFS_CNT_INIT
  18727. #define HDR_S_OFFS_CNT_INIT_MASK (0x1ffffff << 4 )
  18728. #define HDR_S_OFFS_CNT_INIT_SHIFT 4U
  18729. #define HDR_S_LLENGTH
  18730. #define HDR_S_LLENGTH_MASK (0xffffffff << 0 )
  18731. #define HDR_S_LLENGTH_SHIFT 0U
  18732. #define HDR_S_PIC_LVAL
  18733. #define HDR_S_PIC_LVAL_MASK (0xffff << 0 )
  18734. #define HDR_S_PIC_LVAL_SHIFT 0U
  18735. #define HDR_S_IRQ_OFFS_INIT
  18736. #define HDR_S_IRQ_OFFS_INIT_MASK (0xffffffff << 0 )
  18737. #define HDR_S_IRQ_OFFS_INIT_SHIFT 0U
  18738. #define HDR_S_OFFS_CNT_START
  18739. #define HDR_S_OFFS_CNT_START_MASK (0x1ffffff << 4 )
  18740. #define HDR_S_OFFS_CNT_START_SHIFT 4U
  18741. #define HDR_S_BASE_AD_SHD
  18742. #define HDR_S_BASE_AD_SHD_MASK (0xfffffff << 4 )
  18743. #define HDR_S_BASE_AD_SHD_SHIFT 4U
  18744. #define HDR_S_SIZE_SHD
  18745. #define HDR_S_SIZE_SHD_MASK (0x1ffffff << 4 )
  18746. #define HDR_S_SIZE_SHD_SHIFT 4U
  18747. #define HDR_S_OFFS_CNT
  18748. #define HDR_S_OFFS_CNT_MASK (0x1ffffff << 4 )
  18749. #define HDR_S_OFFS_CNT_SHIFT 4U
  18750. #define HDR_S_IRQ_OFFS_SHD
  18751. #define HDR_S_IRQ_OFFS_SHD_MASK (0xffffffff << 0 )
  18752. #define HDR_S_IRQ_OFFS_SHD_SHIFT 0U
  18753. #define HDR_VS_BASE_AD_INIT
  18754. #define HDR_VS_BASE_AD_INIT_MASK (0xfffffff << 4 )
  18755. #define HDR_VS_BASE_AD_INIT_SHIFT 4U
  18756. #define HDR_VS_SIZE_INIT
  18757. #define HDR_VS_SIZE_INIT_MASK (0x1ffffff << 4 )
  18758. #define HDR_VS_SIZE_INIT_SHIFT 4U
  18759. #define HDR_VS_OFFS_CNT_INIT
  18760. #define HDR_VS_OFFS_CNT_INIT_MASK (0x1ffffff << 4 )
  18761. #define HDR_VS_OFFS_CNT_INIT_SHIFT 4U
  18762. #define HDR_VS_LLENGTH
  18763. #define HDR_VS_LLENGTH_MASK (0xffffffff << 0 )
  18764. #define HDR_VS_LLENGTH_SHIFT 0U
  18765. #define HDR_VS_PIC_LVAL
  18766. #define HDR_VS_PIC_LVAL_MASK (0xffff << 0 )
  18767. #define HDR_VS_PIC_LVAL_SHIFT 0U
  18768. #define HDR_VS_IRQ_OFFS_INIT
  18769. #define HDR_VS_IRQ_OFFS_INIT_MASK (0xffffffff << 0 )
  18770. #define HDR_VS_IRQ_OFFS_INIT_SHIFT 0U
  18771. #define HDR_VS_OFFS_CNT_START
  18772. #define HDR_VS_OFFS_CNT_START_MASK (0x1ffffff << 4 )
  18773. #define HDR_VS_OFFS_CNT_START_SHIFT 4U
  18774. #define HDR_VS_BASE_AD_SHD
  18775. #define HDR_VS_BASE_AD_SHD_MASK (0xfffffff << 4 )
  18776. #define HDR_VS_BASE_AD_SHD_SHIFT 4U
  18777. #define HDR_VS_SIZE_SHD
  18778. #define HDR_VS_SIZE_SHD_MASK (0x1ffffff << 4 )
  18779. #define HDR_VS_SIZE_SHD_SHIFT 4U
  18780. #define HDR_VS_OFFS_CNT
  18781. #define HDR_VS_OFFS_CNT_MASK (0x1ffffff << 4 )
  18782. #define HDR_VS_OFFS_CNT_SHIFT 4U
  18783. #define HDR_VS_IRQ_OFFS_SHD
  18784. #define HDR_VS_IRQ_OFFS_SHD_MASK (0xffffffff << 0 )
  18785. #define HDR_VS_IRQ_OFFS_SHD_SHIFT 0U
  18786. #define HDR_DMA_PIC_WIDTH
  18787. #define HDR_DMA_PIC_WIDTH_MASK (0x7fff << 0 )
  18788. #define HDR_DMA_PIC_WIDTH_SHIFT 0U
  18789. #define HDR_DMA_PIC_HEIGHT
  18790. #define HDR_DMA_PIC_HEIGHT_MASK (0x7fff << 0 )
  18791. #define HDR_DMA_PIC_HEIGHT_SHIFT 0U
  18792. #define HDR_DMA_L_BASE_AD_INIT
  18793. #define HDR_DMA_L_BASE_AD_INIT_MASK (0xfffffff << 4 )
  18794. #define HDR_DMA_L_BASE_AD_INIT_SHIFT 4U
  18795. #define HDR_DMA_L_SIZE_INIT
  18796. #define HDR_DMA_L_SIZE_INIT_MASK (0xfffffff << 4 )
  18797. #define HDR_DMA_L_SIZE_INIT_SHIFT 4U
  18798. #define HDR_DMA_L_PIC_LLENGTH
  18799. #define HDR_DMA_L_PIC_LLENGTH_MASK (0xfffffff << 4 )
  18800. #define HDR_DMA_L_PIC_LLENGTH_SHIFT 4U
  18801. #define HDR_DMA_L_WIDTH_BYTES
  18802. #define HDR_DMA_L_WIDTH_BYTES_MASK (0xffff << 0 )
  18803. #define HDR_DMA_L_WIDTH_BYTES_SHIFT 0U
  18804. #define HDR_DMA_L_BASE_AD_INIT
  18805. #define HDR_DMA_L_BASE_AD_INIT_MASK (0xfffffff << 4 )
  18806. #define HDR_DMA_L_BASE_AD_INIT_SHIFT 4U
  18807. #define HDR_DMA_L_SIZE_INIT
  18808. #define HDR_DMA_L_SIZE_INIT_MASK (0xfffffff << 4 )
  18809. #define HDR_DMA_L_SIZE_INIT_SHIFT 4U
  18810. #define HDR_DMA_S_BASE_AD_INIT
  18811. #define HDR_DMA_S_BASE_AD_INIT_MASK (0xfffffff << 4 )
  18812. #define HDR_DMA_S_BASE_AD_INIT_SHIFT 4U
  18813. #define HDR_DMA_S_SIZE_INIT
  18814. #define HDR_DMA_S_SIZE_INIT_MASK (0xfffffff << 4 )
  18815. #define HDR_DMA_S_SIZE_INIT_SHIFT 4U
  18816. #define HDR_DMA_S_PIC_LLENGTH
  18817. #define HDR_DMA_S_PIC_LLENGTH_MASK (0xfffffff << 4 )
  18818. #define HDR_DMA_S_PIC_LLENGTH_SHIFT 4U
  18819. #define HDR_DMA_S_WIDTH_BYTES
  18820. #define HDR_DMA_S_WIDTH_BYTES_MASK (0xffff << 0 )
  18821. #define HDR_DMA_S_WIDTH_BYTES_SHIFT 0U
  18822. #define HDR_DMA_S_BASE_AD_INIT
  18823. #define HDR_DMA_S_BASE_AD_INIT_MASK (0xfffffff << 4 )
  18824. #define HDR_DMA_S_BASE_AD_INIT_SHIFT 4U
  18825. #define HDR_DMA_S_SIZE_INIT
  18826. #define HDR_DMA_S_SIZE_INIT_MASK (0xfffffff << 4 )
  18827. #define HDR_DMA_S_SIZE_INIT_SHIFT 4U
  18828. #define HDR_DMA_VS_BASE_AD_INIT
  18829. #define HDR_DMA_VS_BASE_AD_INIT_MASK (0xfffffff << 4 )
  18830. #define HDR_DMA_VS_BASE_AD_INIT_SHIFT 4U
  18831. #define HDR_DMA_VS_SIZE_INIT
  18832. #define HDR_DMA_VS_SIZE_INIT_MASK (0xfffffff << 4 )
  18833. #define HDR_DMA_VS_SIZE_INIT_SHIFT 4U
  18834. #define HDR_DMA_VS_PIC_LLENGTH
  18835. #define HDR_DMA_VS_PIC_LLENGTH_MASK (0xfffffff << 4 )
  18836. #define HDR_DMA_VS_PIC_LLENGTH_SHIFT 4U
  18837. #define HDR_DMA_VS_WIDTH_BYTES
  18838. #define HDR_DMA_VS_WIDTH_BYTES_MASK (0xffff << 0 )
  18839. #define HDR_DMA_VS_WIDTH_BYTES_SHIFT 0U
  18840. #define HDR_DMA_VS_BASE_AD_INIT
  18841. #define HDR_DMA_VS_BASE_AD_INIT_MASK (0xfffffff << 4 )
  18842. #define HDR_DMA_VS_BASE_AD_INIT_SHIFT 4U
  18843. #define HDR_DMA_VS_SIZE_INIT
  18844. #define HDR_DMA_VS_SIZE_INIT_MASK (0xfffffff << 4 )
  18845. #define HDR_DMA_VS_SIZE_INIT_SHIFT 4U
  18846. #define HDR_RT_VSYNC_POL
  18847. #define HDR_RT_VSYNC_POL_MASK (0x1 << 8)
  18848. #define HDR_RT_VSYNC_POL_SHIFT 8U
  18849. #define HDR_RT_HSYNC_POL
  18850. #define HDR_RT_HSYNC_POL_MASK (0x1 << 7)
  18851. #define HDR_RT_HSYNC_POL_SHIFT 7U
  18852. #define HDR_RETIMING_ENABLE
  18853. #define HDR_RETIMING_ENABLE_MASK 0x1 << 6
  18854. #define HDR_RETIMING_ENABLE_SHIFT 6U
  18855. #define LONG_USE_DDR_ONLY_EN
  18856. #define LONG_USE_DDR_ONLY_EN_MASK 0x1 << 5
  18857. #define LONG_USE_DDR_ONLY_EN_SHIFT 5U
  18858. #define SHORT_USE_DDR_ONLY_EN
  18859. #define SHORT_USE_DDR_ONLY_EN_MASK 0x1 << 4
  18860. #define SHORT_USE_DDR_ONLY_EN_SHIFT 4U
  18861. #define DUMP_MODE_EN
  18862. #define DUMP_MODE_EN_MASK 0x1 << 3
  18863. #define DUMP_MODE_EN_SHIFT 3U
  18864. #define L_VS_COMBINING_ENABLE
  18865. #define L_VS_COMBINING_ENABLE_MASK 0x1 << 2
  18866. #define L_VS_COMBINING_ENABLE_SHIFT 2U
  18867. #define EXPOSURE_COUNT
  18868. #define EXPOSURE_COUNT_MASK (0x3 << 0 )
  18869. #define EXPOSURE_COUNT_SHIFT 0U
  18870. #define HDR_INTERVAL1
  18871. #define HDR_INTERVAL1_MASK (0xffff << 16 )
  18872. #define HDR_INTERVAL1_SHIFT 16U
  18873. #define HDR_INTERVAL0
  18874. #define HDR_INTERVAL0_MASK (0xffff << 0 )
  18875. #define HDR_INTERVAL0_SHIFT 0U
  18876. #define PART_TWO_ENABLE
  18877. #define PART_TWO_ENABLE_MASK 0x1 << 23
  18878. #define PART_TWO_ENABLE_SHIFT 23U
  18879. #define PART_ONE_ENABLE
  18880. #define PART_ONE_ENABLE_MASK 0x1 << 22
  18881. #define PART_ONE_ENABLE_SHIFT 22U
  18882. #define SOFT_RST_PRE_FILT
  18883. #define SOFT_RST_PRE_FILT_MASK 0x1 << 21
  18884. #define SOFT_RST_PRE_FILT_SHIFT 21U
  18885. #define DEMOSAIC_THRESHOLD
  18886. #define DEMOSAIC_THRESHOLD_MASK (0xff << 13 )
  18887. #define DEMOSAIC_THRESHOLD_SHIFT 13U
  18888. #define STAGE1_SELECT
  18889. #define STAGE1_SELECT_MASK (0xf << 9 )
  18890. #define STAGE1_SELECT_SHIFT 9U
  18891. #define OUT_RGB_BAYER_PATTERN
  18892. #define OUT_RGB_BAYER_PATTERN_MASK (0x3 << 7 )
  18893. #define OUT_RGB_BAYER_PATTERN_SHIFT 7U
  18894. #define RGBIR_BAYER_PATTERN
  18895. #define RGBIR_BAYER_PATTERN_MASK (0xf << 3 )
  18896. #define RGBIR_BAYER_PATTERN_SHIFT 3U
  18897. #define GREEN_FILT_ENABLE
  18898. #define GREEN_FILT_ENABLE_MASK 0x1 << 2
  18899. #define GREEN_FILT_ENABLE_SHIFT 2U
  18900. #define GREEN_FILT_MODE
  18901. #define GREEN_FILT_MODE_MASK 0x1 << 1
  18902. #define GREEN_FILT_MODE_SHIFT 1U
  18903. #define ISP_PRE_FILT_ENABLE
  18904. #define ISP_PRE_FILT_ENABLE_MASK 0x1 << 0
  18905. #define ISP_PRE_FILT_ENABLE_SHIFT 0U
  18906. #define ISP_PRE_FILT_BLS_A
  18907. #define ISP_PRE_FILT_BLS_A_MASK (0xffff << 0 )
  18908. #define ISP_PRE_FILT_BLS_A_SHIFT 0U
  18909. #define ISP_PRE_FILT_BLS_B
  18910. #define ISP_PRE_FILT_BLS_B_MASK (0xffff << 0 )
  18911. #define ISP_PRE_FILT_BLS_B_SHIFT 0U
  18912. #define ISP_PRE_FILT_BLS_C
  18913. #define ISP_PRE_FILT_BLS_C_MASK (0xffff << 0 )
  18914. #define ISP_PRE_FILT_BLS_C_SHIFT 0U
  18915. #define ISP_PRE_FILT_BLS_D
  18916. #define ISP_PRE_FILT_BLS_D_MASK (0xffff << 0 )
  18917. #define ISP_PRE_FILT_BLS_D_SHIFT 0U
  18918. #define ISP_PRE_FILT_GAIN_R
  18919. #define ISP_PRE_FILT_GAIN_R_MASK (0x3ff << 0 )
  18920. #define ISP_PRE_FILT_GAIN_R_SHIFT 0U
  18921. #define ISP_PRE_FILT_GAIN_G
  18922. #define ISP_PRE_FILT_GAIN_G_MASK (0x3ff << 0 )
  18923. #define ISP_PRE_FILT_GAIN_G_SHIFT 0U
  18924. #define ISP_PRE_FILT_GAIN_B
  18925. #define ISP_PRE_FILT_GAIN_B_MASK (0x3ff << 0 )
  18926. #define ISP_PRE_FILT_GAIN_B_SHIFT 0U
  18927. #define ISP_PRE_FILT_DPC_TH_MED_R
  18928. #define ISP_PRE_FILT_DPC_TH_MED_R_MASK (0xffff << 16 )
  18929. #define ISP_PRE_FILT_DPC_TH_MED_R_SHIFT 16U
  18930. #define ISP_PRE_FILT_DPC_TH_AVG_R
  18931. #define ISP_PRE_FILT_DPC_TH_AVG_R_MASK (0xffff << 0 )
  18932. #define ISP_PRE_FILT_DPC_TH_AVG_R_SHIFT 0U
  18933. #define ISP_PRE_FILT_DPC_TH_MED_G
  18934. #define ISP_PRE_FILT_DPC_TH_MED_G_MASK (0xffff << 16 )
  18935. #define ISP_PRE_FILT_DPC_TH_MED_G_SHIFT 16U
  18936. #define ISP_PRE_FILT_DPC_TH_AVG_G
  18937. #define ISP_PRE_FILT_DPC_TH_AVG_G_MASK (0xffff << 0 )
  18938. #define ISP_PRE_FILT_DPC_TH_AVG_G_SHIFT 0U
  18939. #define ISP_PRE_FILT_DPC_TH_MED_B
  18940. #define ISP_PRE_FILT_DPC_TH_MED_B_MASK (0xffff << 16 )
  18941. #define ISP_PRE_FILT_DPC_TH_MED_B_SHIFT 16U
  18942. #define ISP_PRE_FILT_DPC_TH_AVG_B
  18943. #define ISP_PRE_FILT_DPC_TH_AVG_B_MASK (0xffff << 0 )
  18944. #define ISP_PRE_FILT_DPC_TH_AVG_B_SHIFT 0U
  18945. #define ISP_PRE_FILT_DPC_TH_MED_IR
  18946. #define ISP_PRE_FILT_DPC_TH_MED_IR_MASK (0xffff << 16 )
  18947. #define ISP_PRE_FILT_DPC_TH_MED_IR_SHIFT 16U
  18948. #define ISP_PRE_FILT_DPC_TH_AVG_IR
  18949. #define ISP_PRE_FILT_DPC_TH_AVG_IR_MASK (0xffff << 0 )
  18950. #define ISP_PRE_FILT_DPC_TH_AVG_IR_SHIFT 0U
  18951. #define ISP_PRE_FILT_CC_00
  18952. #define ISP_PRE_FILT_CC_00_MASK (0x7ff << 16 )
  18953. #define ISP_PRE_FILT_CC_00_SHIFT 16U
  18954. #define ISP_PRE_FILT_CC_01
  18955. #define ISP_PRE_FILT_CC_01_MASK (0x7ff << 0 )
  18956. #define ISP_PRE_FILT_CC_01_SHIFT 0U
  18957. #define ISP_PRE_FILT_CC_02
  18958. #define ISP_PRE_FILT_CC_02_MASK (0x7ff << 16 )
  18959. #define ISP_PRE_FILT_CC_02_SHIFT 16U
  18960. #define ISP_PRE_FILT_CC_03
  18961. #define ISP_PRE_FILT_CC_03_MASK (0x7ff << 0 )
  18962. #define ISP_PRE_FILT_CC_03_SHIFT 0U
  18963. #define ISP_PRE_FILT_CC_10
  18964. #define ISP_PRE_FILT_CC_10_MASK (0x7ff << 16 )
  18965. #define ISP_PRE_FILT_CC_10_SHIFT 16U
  18966. #define ISP_PRE_FILT_CC_11
  18967. #define ISP_PRE_FILT_CC_11_MASK (0x7ff << 0 )
  18968. #define ISP_PRE_FILT_CC_11_SHIFT 0U
  18969. #define ISP_PRE_FILT_CC_12
  18970. #define ISP_PRE_FILT_CC_12_MASK (0x7ff << 16 )
  18971. #define ISP_PRE_FILT_CC_12_SHIFT 16U
  18972. #define ISP_PRE_FILT_CC_13
  18973. #define ISP_PRE_FILT_CC_13_MASK (0x7ff << 0 )
  18974. #define ISP_PRE_FILT_CC_13_SHIFT 0U
  18975. #define ISP_PRE_FILT_CC_20
  18976. #define ISP_PRE_FILT_CC_20_MASK (0x7ff << 16 )
  18977. #define ISP_PRE_FILT_CC_20_SHIFT 16U
  18978. #define ISP_PRE_FILT_CC_21
  18979. #define ISP_PRE_FILT_CC_21_MASK (0x7ff << 0 )
  18980. #define ISP_PRE_FILT_CC_21_SHIFT 0U
  18981. #define ISP_PRE_FILT_CC_22
  18982. #define ISP_PRE_FILT_CC_22_MASK (0x7ff << 16 )
  18983. #define ISP_PRE_FILT_CC_22_SHIFT 16U
  18984. #define ISP_PRE_FILT_CC_23
  18985. #define ISP_PRE_FILT_CC_23_MASK (0x7ff << 0 )
  18986. #define ISP_PRE_FILT_CC_23_SHIFT 0U
  18987. #define ISP_PRE_FILT_CC_00_SHD
  18988. #define ISP_PRE_FILT_CC_00_SHD_MASK (0x7ff << 16 )
  18989. #define ISP_PRE_FILT_CC_00_SHD_SHIFT 16U
  18990. #define ISP_PRE_FILT_CC_01_SHD
  18991. #define ISP_PRE_FILT_CC_01_SHD_MASK (0x7ff << 0 )
  18992. #define ISP_PRE_FILT_CC_01_SHD_SHIFT 0U
  18993. #define ISP_PRE_FILT_CC_02_SHD
  18994. #define ISP_PRE_FILT_CC_02_SHD_MASK (0x7ff << 16 )
  18995. #define ISP_PRE_FILT_CC_02_SHD_SHIFT 16U
  18996. #define ISP_PRE_FILT_CC_03_SHD
  18997. #define ISP_PRE_FILT_CC_03_SHD_MASK (0x7ff << 0 )
  18998. #define ISP_PRE_FILT_CC_03_SHD_SHIFT 0U
  18999. #define ISP_PRE_FILT_CC_10_SHD
  19000. #define ISP_PRE_FILT_CC_10_SHD_MASK (0x7ff << 16 )
  19001. #define ISP_PRE_FILT_CC_10_SHD_SHIFT 16U
  19002. #define ISP_PRE_FILT_CC_11_SHD
  19003. #define ISP_PRE_FILT_CC_11_SHD_MASK (0x7ff << 0 )
  19004. #define ISP_PRE_FILT_CC_11_SHD_SHIFT 0U
  19005. #define ISP_PRE_FILT_CC_12_SHD
  19006. #define ISP_PRE_FILT_CC_12_SHD_MASK (0x7ff << 16 )
  19007. #define ISP_PRE_FILT_CC_12_SHD_SHIFT 16U
  19008. #define ISP_PRE_FILT_CC_13_SHD
  19009. #define ISP_PRE_FILT_CC_13_SHD_MASK (0x7ff << 0 )
  19010. #define ISP_PRE_FILT_CC_13_SHD_SHIFT 0U
  19011. #define ISP_PRE_FILT_CC_20_SHD
  19012. #define ISP_PRE_FILT_CC_20_SHD_MASK (0x7ff << 16 )
  19013. #define ISP_PRE_FILT_CC_20_SHD_SHIFT 16U
  19014. #define ISP_PRE_FILT_CC_21_SHD
  19015. #define ISP_PRE_FILT_CC_21_SHD_MASK (0x7ff << 0 )
  19016. #define ISP_PRE_FILT_CC_21_SHD_SHIFT 0U
  19017. #define ISP_PRE_FILT_CC_22_SHD
  19018. #define ISP_PRE_FILT_CC_22_SHD_MASK (0x7ff << 16 )
  19019. #define ISP_PRE_FILT_CC_22_SHD_SHIFT 16U
  19020. #define ISP_PRE_FILT_CC_23_SHD
  19021. #define ISP_PRE_FILT_CC_23_SHD_MASK (0x7ff << 0 )
  19022. #define ISP_PRE_FILT_CC_23_SHD_SHIFT 0U
  19023. #define ISP_PRE_FILT_IR_DES_PX1
  19024. #define ISP_PRE_FILT_IR_DES_PX1_MASK (0xffff << 0 )
  19025. #define ISP_PRE_FILT_IR_DES_PX1_SHIFT 0U
  19026. #define ISP_PRE_FILT_IR_DES_PY2
  19027. #define ISP_PRE_FILT_IR_DES_PY2_MASK (0xffff << 16 )
  19028. #define ISP_PRE_FILT_IR_DES_PY2_SHIFT 16U
  19029. #define ISP_PRE_FILT_IR_DES_PY1
  19030. #define ISP_PRE_FILT_IR_DES_PY1_MASK (0xffff << 0 )
  19031. #define ISP_PRE_FILT_IR_DES_PY1_SHIFT 0U
  19032. #define ISP_PRE_FILT_IR_DES_PY4
  19033. #define ISP_PRE_FILT_IR_DES_PY4_MASK (0xffff << 16 )
  19034. #define ISP_PRE_FILT_IR_DES_PY4_SHIFT 16U
  19035. #define ISP_PRE_FILT_IR_DES_PY3
  19036. #define ISP_PRE_FILT_IR_DES_PY3_MASK (0xffff << 0 )
  19037. #define ISP_PRE_FILT_IR_DES_PY3_SHIFT 0U
  19038. #define ISP_PRE_FILT_IR_DES_PY6
  19039. #define ISP_PRE_FILT_IR_DES_PY6_MASK (0xffff << 16 )
  19040. #define ISP_PRE_FILT_IR_DES_PY6_SHIFT 16U
  19041. #define ISP_PRE_FILT_IR_DES_PY5
  19042. #define ISP_PRE_FILT_IR_DES_PY5_MASK (0xffff << 0 )
  19043. #define ISP_PRE_FILT_IR_DES_PY5_SHIFT 0U
  19044. #define ISP_PRE_FILT_IR_DES_PY8
  19045. #define ISP_PRE_FILT_IR_DES_PY8_MASK (0xffff << 16 )
  19046. #define ISP_PRE_FILT_IR_DES_PY8_SHIFT 16U
  19047. #define ISP_PRE_FILT_IR_DES_PY7
  19048. #define ISP_PRE_FILT_IR_DES_PY7_MASK (0xffff << 0 )
  19049. #define ISP_PRE_FILT_IR_DES_PY7_SHIFT 0U
  19050. #define ISP_PRE_FILT_IR_DES_PY10
  19051. #define ISP_PRE_FILT_IR_DES_PY10_MASK (0xffff << 16 )
  19052. #define ISP_PRE_FILT_IR_DES_PY10_SHIFT 16U
  19053. #define ISP_PRE_FILT_IR_DES_PY9
  19054. #define ISP_PRE_FILT_IR_DES_PY9_MASK (0xffff << 0 )
  19055. #define ISP_PRE_FILT_IR_DES_PY9_SHIFT 0U
  19056. #define ISP_PRE_FILT_IR_DES_PY12
  19057. #define ISP_PRE_FILT_IR_DES_PY12_MASK (0xffff << 16 )
  19058. #define ISP_PRE_FILT_IR_DES_PY12_SHIFT 16U
  19059. #define ISP_PRE_FILT_IR_DES_PY11
  19060. #define ISP_PRE_FILT_IR_DES_PY11_MASK (0xffff << 0 )
  19061. #define ISP_PRE_FILT_IR_DES_PY11_SHIFT 0U
  19062. #define ISP_PRE_FILT_IR_DES_PY14
  19063. #define ISP_PRE_FILT_IR_DES_PY14_MASK (0xffff << 16 )
  19064. #define ISP_PRE_FILT_IR_DES_PY14_SHIFT 16U
  19065. #define ISP_PRE_FILT_IR_DES_PY13
  19066. #define ISP_PRE_FILT_IR_DES_PY13_MASK (0xffff << 0 )
  19067. #define ISP_PRE_FILT_IR_DES_PY13_SHIFT 0U
  19068. #define ISP_PRE_FILT_IR_DES_PY16
  19069. #define ISP_PRE_FILT_IR_DES_PY16_MASK (0xffff << 16 )
  19070. #define ISP_PRE_FILT_IR_DES_PY16_SHIFT 16U
  19071. #define ISP_PRE_FILT_IR_DES_PY15
  19072. #define ISP_PRE_FILT_IR_DES_PY15_MASK (0xffff << 0 )
  19073. #define ISP_PRE_FILT_IR_DES_PY15_SHIFT 0U
  19074. #define ISP_PRE_FILT_IR_DES_PD4
  19075. #define ISP_PRE_FILT_IR_DES_PD4_MASK (0xff << 24 )
  19076. #define ISP_PRE_FILT_IR_DES_PD4_SHIFT 24U
  19077. #define ISP_PRE_FILT_IR_DES_PD3
  19078. #define ISP_PRE_FILT_IR_DES_PD3_MASK (0xff << 16 )
  19079. #define ISP_PRE_FILT_IR_DES_PD3_SHIFT 16U
  19080. #define ISP_PRE_FILT_IR_DES_PD2
  19081. #define ISP_PRE_FILT_IR_DES_PD2_MASK (0xff << 8 )
  19082. #define ISP_PRE_FILT_IR_DES_PD2_SHIFT 8U
  19083. #define ISP_PRE_FILT_IR_DES_PD1
  19084. #define ISP_PRE_FILT_IR_DES_PD1_MASK (0xff << 0 )
  19085. #define ISP_PRE_FILT_IR_DES_PD1_SHIFT 0U
  19086. #define ISP_PRE_FILT_IR_DES_PD8
  19087. #define ISP_PRE_FILT_IR_DES_PD8_MASK (0xff << 24 )
  19088. #define ISP_PRE_FILT_IR_DES_PD8_SHIFT 24U
  19089. #define ISP_PRE_FILT_IR_DES_PD7
  19090. #define ISP_PRE_FILT_IR_DES_PD7_MASK (0xff << 16 )
  19091. #define ISP_PRE_FILT_IR_DES_PD7_SHIFT 16U
  19092. #define ISP_PRE_FILT_IR_DES_PD6
  19093. #define ISP_PRE_FILT_IR_DES_PD6_MASK (0xff << 8 )
  19094. #define ISP_PRE_FILT_IR_DES_PD6_SHIFT 8U
  19095. #define ISP_PRE_FILT_IR_DES_PD5
  19096. #define ISP_PRE_FILT_IR_DES_PD5_MASK (0xff << 0 )
  19097. #define ISP_PRE_FILT_IR_DES_PD5_SHIFT 0U
  19098. #define ISP_PRE_FILT_IR_DES_PD12
  19099. #define ISP_PRE_FILT_IR_DES_PD12_MASK (0xff << 24 )
  19100. #define ISP_PRE_FILT_IR_DES_PD12_SHIFT 24U
  19101. #define ISP_PRE_FILT_IR_DES_PD11
  19102. #define ISP_PRE_FILT_IR_DES_PD11_MASK (0xff << 16 )
  19103. #define ISP_PRE_FILT_IR_DES_PD11_SHIFT 16U
  19104. #define ISP_PRE_FILT_IR_DES_PD10
  19105. #define ISP_PRE_FILT_IR_DES_PD10_MASK (0xff << 8 )
  19106. #define ISP_PRE_FILT_IR_DES_PD10_SHIFT 8U
  19107. #define ISP_PRE_FILT_IR_DES_PD9
  19108. #define ISP_PRE_FILT_IR_DES_PD9_MASK (0xff << 0 )
  19109. #define ISP_PRE_FILT_IR_DES_PD9_SHIFT 0U
  19110. #define ISP_PRE_FILT_IR_DES_PD15
  19111. #define ISP_PRE_FILT_IR_DES_PD15_MASK (0xff << 16 )
  19112. #define ISP_PRE_FILT_IR_DES_PD15_SHIFT 16U
  19113. #define ISP_PRE_FILT_IR_DES_PD14
  19114. #define ISP_PRE_FILT_IR_DES_PD14_MASK (0xff << 8 )
  19115. #define ISP_PRE_FILT_IR_DES_PD14_SHIFT 8U
  19116. #define ISP_PRE_FILT_IR_DES_PD13
  19117. #define ISP_PRE_FILT_IR_DES_PD13_MASK (0xff << 0 )
  19118. #define ISP_PRE_FILT_IR_DES_PD13_SHIFT 0U
  19119. #define ISP_PRE_FILT_L_DES_PX1
  19120. #define ISP_PRE_FILT_L_DES_PX1_MASK (0xffff << 0 )
  19121. #define ISP_PRE_FILT_L_DES_PX1_SHIFT 0U
  19122. #define ISP_PRE_FILT_L_DES_PY2
  19123. #define ISP_PRE_FILT_L_DES_PY2_MASK (0xffff << 16 )
  19124. #define ISP_PRE_FILT_L_DES_PY2_SHIFT 16U
  19125. #define ISP_PRE_FILT_L_DES_PY1
  19126. #define ISP_PRE_FILT_L_DES_PY1_MASK (0xffff << 0 )
  19127. #define ISP_PRE_FILT_L_DES_PY1_SHIFT 0U
  19128. #define ISP_PRE_FILT_L_DES_PY4
  19129. #define ISP_PRE_FILT_L_DES_PY4_MASK (0xffff << 16 )
  19130. #define ISP_PRE_FILT_L_DES_PY4_SHIFT 16U
  19131. #define ISP_PRE_FILT_L_DES_PY3
  19132. #define ISP_PRE_FILT_L_DES_PY3_MASK (0xffff << 0 )
  19133. #define ISP_PRE_FILT_L_DES_PY3_SHIFT 0U
  19134. #define ISP_PRE_FILT_L_DES_PY6
  19135. #define ISP_PRE_FILT_L_DES_PY6_MASK (0xffff << 16 )
  19136. #define ISP_PRE_FILT_L_DES_PY6_SHIFT 16U
  19137. #define ISP_PRE_FILT_L_DES_PY5
  19138. #define ISP_PRE_FILT_L_DES_PY5_MASK (0xffff << 0 )
  19139. #define ISP_PRE_FILT_L_DES_PY5_SHIFT 0U
  19140. #define ISP_PRE_FILT_L_DES_PY8
  19141. #define ISP_PRE_FILT_L_DES_PY8_MASK (0xffff << 16 )
  19142. #define ISP_PRE_FILT_L_DES_PY8_SHIFT 16U
  19143. #define ISP_PRE_FILT_L_DES_PY7
  19144. #define ISP_PRE_FILT_L_DES_PY7_MASK (0xffff << 0 )
  19145. #define ISP_PRE_FILT_L_DES_PY7_SHIFT 0U
  19146. #define ISP_PRE_FILT_L_DES_PY10
  19147. #define ISP_PRE_FILT_L_DES_PY10_MASK (0xffff << 16 )
  19148. #define ISP_PRE_FILT_L_DES_PY10_SHIFT 16U
  19149. #define ISP_PRE_FILT_L_DES_PY9
  19150. #define ISP_PRE_FILT_L_DES_PY9_MASK (0xffff << 0 )
  19151. #define ISP_PRE_FILT_L_DES_PY9_SHIFT 0U
  19152. #define ISP_PRE_FILT_L_DES_PY12
  19153. #define ISP_PRE_FILT_L_DES_PY12_MASK (0xffff << 16 )
  19154. #define ISP_PRE_FILT_L_DES_PY12_SHIFT 16U
  19155. #define ISP_PRE_FILT_L_DES_PY11
  19156. #define ISP_PRE_FILT_L_DES_PY11_MASK (0xffff << 0 )
  19157. #define ISP_PRE_FILT_L_DES_PY11_SHIFT 0U
  19158. #define ISP_PRE_FILT_L_DES_PY14
  19159. #define ISP_PRE_FILT_L_DES_PY14_MASK (0xffff << 16 )
  19160. #define ISP_PRE_FILT_L_DES_PY14_SHIFT 16U
  19161. #define ISP_PRE_FILT_L_DES_PY13
  19162. #define ISP_PRE_FILT_L_DES_PY13_MASK (0xffff << 0 )
  19163. #define ISP_PRE_FILT_L_DES_PY13_SHIFT 0U
  19164. #define ISP_PRE_FILT_L_DES_PY16
  19165. #define ISP_PRE_FILT_L_DES_PY16_MASK (0xffff << 16 )
  19166. #define ISP_PRE_FILT_L_DES_PY16_SHIFT 16U
  19167. #define ISP_PRE_FILT_L_DES_PY15
  19168. #define ISP_PRE_FILT_L_DES_PY15_MASK (0xffff << 0 )
  19169. #define ISP_PRE_FILT_L_DES_PY15_SHIFT 0U
  19170. #define ISP_PRE_FILT_L_DES_PD4
  19171. #define ISP_PRE_FILT_L_DES_PD4_MASK (0xff << 24 )
  19172. #define ISP_PRE_FILT_L_DES_PD4_SHIFT 24U
  19173. #define ISP_PRE_FILT_L_DES_PD3
  19174. #define ISP_PRE_FILT_L_DES_PD3_MASK (0xff << 16 )
  19175. #define ISP_PRE_FILT_L_DES_PD3_SHIFT 16U
  19176. #define ISP_PRE_FILT_L_DES_PD2
  19177. #define ISP_PRE_FILT_L_DES_PD2_MASK (0xff << 8 )
  19178. #define ISP_PRE_FILT_L_DES_PD2_SHIFT 8U
  19179. #define ISP_PRE_FILT_L_DES_PD1
  19180. #define ISP_PRE_FILT_L_DES_PD1_MASK (0xff << 0 )
  19181. #define ISP_PRE_FILT_L_DES_PD1_SHIFT 0U
  19182. #define ISP_PRE_FILT_L_DES_PD8
  19183. #define ISP_PRE_FILT_L_DES_PD8_MASK (0xff << 24 )
  19184. #define ISP_PRE_FILT_L_DES_PD8_SHIFT 24U
  19185. #define ISP_PRE_FILT_L_DES_PD7
  19186. #define ISP_PRE_FILT_L_DES_PD7_MASK (0xff << 16 )
  19187. #define ISP_PRE_FILT_L_DES_PD7_SHIFT 16U
  19188. #define ISP_PRE_FILT_L_DES_PD6
  19189. #define ISP_PRE_FILT_L_DES_PD6_MASK (0xff << 8 )
  19190. #define ISP_PRE_FILT_L_DES_PD6_SHIFT 8U
  19191. #define ISP_PRE_FILT_L_DES_PD5
  19192. #define ISP_PRE_FILT_L_DES_PD5_MASK (0xff << 0 )
  19193. #define ISP_PRE_FILT_L_DES_PD5_SHIFT 0U
  19194. #define ISP_PRE_FILT_L_DES_PD12
  19195. #define ISP_PRE_FILT_L_DES_PD12_MASK (0xff << 24 )
  19196. #define ISP_PRE_FILT_L_DES_PD12_SHIFT 24U
  19197. #define ISP_PRE_FILT_L_DES_PD11
  19198. #define ISP_PRE_FILT_L_DES_PD11_MASK (0xff << 16 )
  19199. #define ISP_PRE_FILT_L_DES_PD11_SHIFT 16U
  19200. #define ISP_PRE_FILT_L_DES_PD10
  19201. #define ISP_PRE_FILT_L_DES_PD10_MASK (0xff << 8 )
  19202. #define ISP_PRE_FILT_L_DES_PD10_SHIFT 8U
  19203. #define ISP_PRE_FILT_L_DES_PD9
  19204. #define ISP_PRE_FILT_L_DES_PD9_MASK (0xff << 0 )
  19205. #define ISP_PRE_FILT_L_DES_PD9_SHIFT 0U
  19206. #define ISP_PRE_FILT_L_DES_PD15
  19207. #define ISP_PRE_FILT_L_DES_PD15_MASK (0xff << 16 )
  19208. #define ISP_PRE_FILT_L_DES_PD15_SHIFT 16U
  19209. #define ISP_PRE_FILT_L_DES_PD14
  19210. #define ISP_PRE_FILT_L_DES_PD14_MASK (0xff << 8 )
  19211. #define ISP_PRE_FILT_L_DES_PD14_SHIFT 8U
  19212. #define ISP_PRE_FILT_L_DES_PD13
  19213. #define ISP_PRE_FILT_L_DES_PD13_MASK (0xff << 0 )
  19214. #define ISP_PRE_FILT_L_DES_PD13_SHIFT 0U
  19215. #define PREFILT_THRESH_BL0
  19216. #define PREFILT_THRESH_BL0_MASK (0x3ff << 0 )
  19217. #define PREFILT_THRESH_BL0_SHIFT 0U
  19218. #define PREFILT_THRESH_BL1
  19219. #define PREFILT_THRESH_BL1_MASK (0x3ff << 0 )
  19220. #define PREFILT_THRESH_BL1_SHIFT 0U
  19221. #define PREFILT_THRESH_SH0
  19222. #define PREFILT_THRESH_SH0_MASK (0x3ff << 0 )
  19223. #define PREFILT_THRESH_SH0_SHIFT 0U
  19224. #define PREFILT_THRESH_SH1
  19225. #define PREFILT_THRESH_SH1_MASK (0x3ff << 0 )
  19226. #define PREFILT_THRESH_SH1_SHIFT 0U
  19227. #define LUM_WEIGHT_GAIN
  19228. #define LUM_WEIGHT_GAIN_MASK (0x7 << 16 )
  19229. #define LUM_WEIGHT_GAIN_SHIFT 16U
  19230. #define LUM_WEIGHT_KINK
  19231. #define LUM_WEIGHT_KINK_MASK (0xff << 8 )
  19232. #define LUM_WEIGHT_KINK_SHIFT 8U
  19233. #define LUM_WEIGHT_MIN
  19234. #define LUM_WEIGHT_MIN_MASK (0xff << 0 )
  19235. #define LUM_WEIGHT_MIN_SHIFT 0U
  19236. #define PREFILT_FAC_SH1
  19237. #define PREFILT_FAC_SH1_MASK (0x3f << 0 )
  19238. #define PREFILT_FAC_SH1_SHIFT 0U
  19239. #define PREFILT_FAC_SH0
  19240. #define PREFILT_FAC_SH0_MASK (0x3f << 0 )
  19241. #define PREFILT_FAC_SH0_SHIFT 0U
  19242. #define PREFILT_FAC_MID
  19243. #define PREFILT_FAC_MID_MASK (0x3f << 0 )
  19244. #define PREFILT_FAC_MID_SHIFT 0U
  19245. #define PREFILT_FAC_BL0
  19246. #define PREFILT_FAC_BL0_MASK (0x3f << 0 )
  19247. #define PREFILT_FAC_BL0_SHIFT 0U
  19248. #define PREFILT_FAC_BL1
  19249. #define PREFILT_FAC_BL1_MASK (0x3f << 0 )
  19250. #define PREFILT_FAC_BL1_SHIFT 0U
  19251. #define ISP_PRE_FILT_IR_DENOISE_SW3
  19252. #define ISP_PRE_FILT_IR_DENOISE_SW3_MASK (0xff << 24 )
  19253. #define ISP_PRE_FILT_IR_DENOISE_SW3_SHIFT 24U
  19254. #define ISP_PRE_FILT_IR_DENOISE_SW2
  19255. #define ISP_PRE_FILT_IR_DENOISE_SW2_MASK (0xff << 16 )
  19256. #define ISP_PRE_FILT_IR_DENOISE_SW2_SHIFT 16U
  19257. #define ISP_PRE_FILT_IR_DENOISE_SW1
  19258. #define ISP_PRE_FILT_IR_DENOISE_SW1_MASK (0xff << 8 )
  19259. #define ISP_PRE_FILT_IR_DENOISE_SW1_SHIFT 8U
  19260. #define ISP_PRE_FILT_IR_DENOISE_SW0
  19261. #define ISP_PRE_FILT_IR_DENOISE_SW0_MASK (0xff << 0 )
  19262. #define ISP_PRE_FILT_IR_DENOISE_SW0_SHIFT 0U
  19263. #define ISP_PRE_FILT_IR_DENOISE_SW5
  19264. #define ISP_PRE_FILT_IR_DENOISE_SW5_MASK (0xff << 8 )
  19265. #define ISP_PRE_FILT_IR_DENOISE_SW5_SHIFT 8U
  19266. #define ISP_PRE_FILT_IR_DENOISE_SW4
  19267. #define ISP_PRE_FILT_IR_DENOISE_SW4_MASK (0xff << 0 )
  19268. #define ISP_PRE_FILT_IR_DENOISE_SW4_SHIFT 0U
  19269. #define PRE_FILT_H_SIZE
  19270. #define PRE_FILT_H_SIZE_MASK (0x7fff << 0 )
  19271. #define PRE_FILT_H_SIZE_SHIFT 0U
  19272. #define PRE_FILT_V_SIZE
  19273. #define PRE_FILT_V_SIZE_MASK (0x3fff << 0 )
  19274. #define PRE_FILT_V_SIZE_SHIFT 0U
  19275. #define PRE_FILT_DMY_HB
  19276. #define PRE_FILT_DMY_HB_MASK (0x1fff << 0 )
  19277. #define PRE_FILT_DMY_HB_SHIFT 0U
  19278. #define SP2_DMA_RAW_WIDTH_BYTES
  19279. #define SP2_DMA_RAW_WIDTH_BYTES_MASK (0xffff << 0 )
  19280. #define SP2_DMA_RAW_WIDTH_BYTES_SHIFT 0U
  19281. #define PPW_Y_BUF_FULL
  19282. #define PPW_Y_BUF_FULL_MASK (0x1 << 26)
  19283. #define PPW_Y_BUF_FULL_SHIFT 26U
  19284. #define PPW_U_BUF_FULL
  19285. #define PPW_U_BUF_FULL_MASK (0x1 << 25)
  19286. #define PPW_U_BUF_FULL_SHIFT 25U
  19287. #define PPW_V_BUF_FULL
  19288. #define PPW_V_BUF_FULL_MASK (0x1 << 24)
  19289. #define PPW_V_BUF_FULL_SHIFT 24U
  19290. #define PPR_Y_BUF_FULL
  19291. #define PPR_Y_BUF_FULL_MASK (0x1 << 23)
  19292. #define PPR_Y_BUF_FULL_SHIFT 23U
  19293. #define SP2_RAW2_W_BUF_FULL
  19294. #define SP2_RAW2_W_BUF_FULL_MASK (0x1 << 22)
  19295. #define SP2_RAW2_W_BUF_FULL_SHIFT 22U
  19296. #define SP2_RAW2_R_BUF_FULL
  19297. #define SP2_RAW2_R_BUF_FULL_MASK (0x1 << 21)
  19298. #define SP2_RAW2_R_BUF_FULL_SHIFT 21U
  19299. #define HDR_W_BUF_FULL
  19300. #define HDR_W_BUF_FULL_MASK (0x1 << 20)
  19301. #define HDR_W_BUF_FULL_SHIFT 20U
  19302. #define HDR_R_BUF_FULL
  19303. #define HDR_R_BUF_FULL_MASK (0x1 << 19)
  19304. #define HDR_R_BUF_FULL_SHIFT 19U
  19305. #define SP2_RAW2_DMA_READY
  19306. #define SP2_RAW2_DMA_READY_MASK (0x1 << 18)
  19307. #define SP2_RAW2_DMA_READY_SHIFT 18U
  19308. #define PPR_DMA_READY
  19309. #define PPR_DMA_READY_MASK (0x1 << 17)
  19310. #define PPR_DMA_READY_SHIFT 17U
  19311. #define WRAP_PPW_CR
  19312. #define WRAP_PPW_CR_MASK (0x1 << 15)
  19313. #define WRAP_PPW_CR_SHIFT 15U
  19314. #define WRAP_PPW_CB
  19315. #define WRAP_PPW_CB_MASK (0x1 << 14)
  19316. #define WRAP_PPW_CB_SHIFT 14U
  19317. #define WRAP_PPW_Y
  19318. #define WRAP_PPW_Y_MASK (0x1 << 13)
  19319. #define WRAP_PPW_Y_SHIFT 13U
  19320. #define SP2_RAW2_FRAME_END
  19321. #define SP2_RAW2_FRAME_END_MASK (0x1 << 12)
  19322. #define SP2_RAW2_FRAME_END_SHIFT 12U
  19323. #define PPW_FRAME_END
  19324. #define PPW_FRAME_END_MASK (0x1 << 11)
  19325. #define PPW_FRAME_END_SHIFT 11U
  19326. #define HDR_VS_DMA_READY
  19327. #define HDR_VS_DMA_READY_MASK (0x1 << 10)
  19328. #define HDR_VS_DMA_READY_SHIFT 10U
  19329. #define HDR_S_DMA_READY
  19330. #define HDR_S_DMA_READY_MASK (0x1 << 9)
  19331. #define HDR_S_DMA_READY_SHIFT 9U
  19332. #define HDR_L_DMA_READY
  19333. #define HDR_L_DMA_READY_MASK (0x1 << 8)
  19334. #define HDR_L_DMA_READY_SHIFT 8U
  19335. #define WRAP_HDR_VS
  19336. #define WRAP_HDR_VS_MASK (0x1 << 7)
  19337. #define WRAP_HDR_VS_SHIFT 7U
  19338. #define WRAP_HDR_S
  19339. #define WRAP_HDR_S_MASK (0x1 << 6)
  19340. #define WRAP_HDR_S_SHIFT 6U
  19341. #define WRAP_HDR_L
  19342. #define WRAP_HDR_L_MASK (0x1 << 5)
  19343. #define WRAP_HDR_L_SHIFT 5U
  19344. #define HDR_VS_FRAME_END
  19345. #define HDR_VS_FRAME_END_MASK (0x1 << 4)
  19346. #define HDR_VS_FRAME_END_SHIFT 4U
  19347. #define HDR_S_FRAME_END
  19348. #define HDR_S_FRAME_END_MASK (0x1 << 3)
  19349. #define HDR_S_FRAME_END_SHIFT 3U
  19350. #define HDR_L_FRAME_END
  19351. #define HDR_L_FRAME_END_MASK (0x1 << 2)
  19352. #define HDR_L_FRAME_END_SHIFT 2U
  19353. #define MI_RT_BUS_BUSERR
  19354. #define MI_RT_BUS_BUSERR_MASK (0x1 << 1)
  19355. #define MI_RT_BUS_BUSERR_SHIFT 1U
  19356. #define MI_RT_BUS_TIMEO
  19357. #define MI_RT_BUS_TIMEO_MASK (0x1 << 0)
  19358. #define MI_RT_BUS_TIMEO_SHIFT 0U
  19359. #endif /* _MRV_ALL_REGS_H */