mrv_all_bits.h 449 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright 2010, Dream Chip Technologies GmbH. All rights reserved.
  4. *
  5. ****************************************************************************
  6. *
  7. * The MIT License (MIT)
  8. *
  9. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  10. *
  11. * Permission is hereby granted, free of charge, to any person obtaining a
  12. * copy of this software and associated documentation files (the "Software"),
  13. * to deal in the Software without restriction, including without limitation
  14. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  15. * and/or sell copies of the Software, and to permit persons to whom the
  16. * Software is furnished to do so, subject to the following conditions:
  17. *
  18. * The above copyright notice and this permission notice shall be included in
  19. * all copies or substantial portions of the Software.
  20. *
  21. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  22. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  23. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  24. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  25. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  26. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  27. * DEALINGS IN THE SOFTWARE.
  28. *
  29. *****************************************************************************
  30. *
  31. * The GPL License (GPL)
  32. *
  33. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  34. *
  35. * This program is free software; you can redistribute it and/or
  36. * modify it under the terms of the GNU General Public License
  37. * as published by the Free Software Foundation; either version 2
  38. * of the License, or (at your option) any later version.
  39. *
  40. * This program is distributed in the hope that it will be useful,
  41. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  42. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  43. * GNU General Public License for more details.
  44. *
  45. * You should have received a copy of the GNU General Public License
  46. * along with this program;
  47. *
  48. *****************************************************************************
  49. *
  50. * Note: This software is released under dual MIT and GPL licenses. A
  51. * recipient may use this file under the terms of either the MIT license or
  52. * GPL License. If you wish to use only one license not the other, you can
  53. * indicate your decision by deleting one of the above license notices in your
  54. * version of this file.
  55. *
  56. *****************************************************************************/
  57. #ifndef __MRV_ALL_BITS_H__
  58. #define __MRV_ALL_BITS_H__
  59. /*****************************************************************************/
  60. /* this includes the registermap generated by SIG-flow */
  61. /*****************************************************************************/
  62. #ifndef __KERNEL__
  63. #include <stdint.h>
  64. #else
  65. #include <linux/types.h>
  66. #endif
  67. #include "mrv_all_regs.h"
  68. /*****************************************************************************/
  69. /* this includes the hw version information */
  70. /*****************************************************************************/
  71. #include "isp_version.h"
  72. /*****************************************************************************/
  73. /* Marvin Main Control Registers */
  74. /*****************************************************************************/
  75. #define ALIGN_16BYTE(width) (((width) + (0xF - 1)) & (~(0xF - 1)))
  76. #define ALIGN_32BYTE(width) (((width) + 31) & (~31))
  77. /*****************************************************************************/
  78. /**
  79. * register: vi_ccl: Data path control register (0x0000)
  80. *
  81. *****************************************************************************/
  82. /* Slice: vi_ccl_dis:*/
  83. /* Clock Control Logic disable */
  84. /* 0: processing/cfg-clocks for all marvin sub modules enabled */
  85. /* 1: processing/cfg-clocks for all marvin sub modules disabled w/o access to ID and VI_CCL register */
  86. #ifdef MRV_VI_CCL_DIS
  87. #define MRV_VI_CCL_ENABLE_CLOCKS 0
  88. #define MRV_VI_CCL_DISABLE_CLOCKS 1
  89. #endif /* MRV_VI_CCL_DIS */
  90. /*****************************************************************************/
  91. /**
  92. * register: vi_id: Revision identification register (0x0008)
  93. *
  94. *****************************************************************************/
  95. /* Slice: rev_id:*/
  96. /* MARVIN5 revision IDs */
  97. #ifdef MRV_REV_ID
  98. #endif /* MRV_REV_ID */
  99. /*****************************************************************************/
  100. /**
  101. * register: vi_iccl: Internal clock control register (0x0010)
  102. *
  103. *****************************************************************************/
  104. /* Slice: vi_mipi_clk_enable: */
  105. /* MIPI interface clock enable */
  106. /* 1: processing mode */
  107. /* 0: power safe */
  108. #ifdef MRV_VI_MIPI_CLK_ENABLE
  109. #endif /* MRV_VI_MIPI_CLK_ENABLE */
  110. /* Slice: vi_smia_clk_enable:*/
  111. /* SMIA interface clock enable */
  112. /* 1: processing mode */
  113. /* 0: power safe */
  114. #ifdef MRV_VI_SMIA_CLK_ENABLE
  115. #endif /* MRV_VI_SMIA_CLK_ENABLE */
  116. /* Slice: vi_simp_clk_enable:*/
  117. /* Superimpose clock enable */
  118. /* 1: processing mode */
  119. /* 0: power safe */
  120. #ifdef MRV_VI_SIMP_CLK_ENABLE
  121. #endif /* MRV_VI_SIMP_CLK_ENABLE */
  122. /* Slice: vi_ie_clk_enable:*/
  123. /* Image effect clock enable */
  124. /* 1: processing mode */
  125. /* 0: power safe */
  126. #ifdef MRV_VI_IE_CLK_ENABLE
  127. #endif /* MRV_VI_IE_CLK_ENABLE */
  128. /* Slice: vi_mi_clk_enable:*/
  129. /* memory interface clock enable */
  130. /* 1: processing mode */
  131. /* 0: power safe */
  132. #ifdef MRV_VI_MI_CLK_ENABLE
  133. #endif /* MRV_VI_MI_CLK_ENABLE */
  134. /* Slice: vi_jpeg_clk_enable:*/
  135. /* JPEG encoder clock enable */
  136. /* 1: processing mode */
  137. /* 0: power safe */
  138. #ifdef MRV_VI_JPEG_CLK_ENABLE
  139. #endif /* MRV_VI_JPEG_CLK_ENABLE */
  140. /* Slice: vi_srsz_clk_enable:*/
  141. /* main resize clock enable */
  142. /* 1: processing mode */
  143. /* 0: power safe */
  144. #ifdef MRV_VI_SRSZ_CLK_ENABLE
  145. #endif /* MRV_VI_SRSZ_CLK_ENABLE */
  146. /* Slice: vi_mrsz_clk_enable:*/
  147. /* main resize clock enable */
  148. /* 1: processing mode */
  149. /* 0: power safe */
  150. #ifdef MRV_VI_MRSZ_CLK_ENABLE
  151. #endif /* MRV_VI_MRSZ_CLK_ENABLE */
  152. /* Slice: vi_cp_clk_enable:*/
  153. /* color processing clock enable */
  154. /* 1: processing mode */
  155. /* 0: power safe */
  156. #ifdef MRV_VI_CP_CLK_ENABLE
  157. #endif /* MRV_VI_CP_CLK_ENABLE */
  158. /* Slice: vi_isp_clk_enable:*/
  159. /* isp processing clock enable */
  160. /* 1: processing mode */
  161. /* 0: power safe */
  162. #ifdef MRV_VI_ISP_CLK_ENABLE
  163. #endif /* MRV_VI_ISP_CLK_ENABLE */
  164. /*****************************************************************************/
  165. /**
  166. * register: vi_ircl: Internal reset control register (0x0014)
  167. *
  168. *****************************************************************************/
  169. /* Slice: vi_mipi_soft_rst:*/
  170. /* MIPI Interface software reset */
  171. /* 0: processing mode */
  172. /* 1: reset state */
  173. #ifdef MRV_VI_MIPI_SOFT_RST
  174. #endif /* MRV_VI_MIPI_SOFT_RST */
  175. /* Slice: vi_smia_soft_rst:*/
  176. /* SMIA Interface software reset */
  177. /* 0: processing mode */
  178. /* 1: reset state */
  179. #ifdef MRV_VI_SMIA_SOFT_RST
  180. #endif /* MRV_VI_SMIA_SOFT_RST */
  181. /* Slice: vi_simp_soft_rst:*/
  182. /* Superimpose software reset */
  183. /* 0: processing mode */
  184. /* 1: reset state */
  185. #ifdef MRV_VI_SIMP_SOFT_RST
  186. #endif /* MRV_VI_SIMP_SOFT_RST */
  187. /* Slice: vi_ie_soft_rst:*/
  188. /* Image effect software reset */
  189. /* 0: processing mode */
  190. /* 1: reset state */
  191. #ifdef MRV_VI_IE_SOFT_RST
  192. #endif /* MRV_VI_IE_SOFT_RST */
  193. /* Slice: vi_marvin_rst:*/
  194. /* Soft reset of entire marvin */
  195. /* 0: processing mode */
  196. /* 1: reset state */
  197. #ifdef MRV_VI_MARVIN_RST
  198. #endif /* MRV_VI_MARVIN_RST */
  199. /* Slice: vi_mi_soft_rst:*/
  200. /* memory interface software reset */
  201. /* 0: processing mode */
  202. /* 1: reset state */
  203. #ifdef MRV_VI_MI_SOFT_RST
  204. #endif /* MRV_VI_MI_SOFT_RST */
  205. /* Slice: vi_jpeg_soft_rst:*/
  206. /* JPEG encoder software reset */
  207. /* 0: processing mode */
  208. /* 1: reset state */
  209. #ifdef MRV_VI_JPEG_SOFT_RST
  210. #endif /* MRV_VI_JPEG_SOFT_RST */
  211. /* Slice: vi_srsz_soft_rst:*/
  212. /* Self-picture resize software reset */
  213. /* 0: processing mode */
  214. /* 1: reset state */
  215. #ifdef MRV_VI_SRSZ_SOFT_RST
  216. #endif /* MRV_VI_SRSZ_SOFT_RST */
  217. /* Slice: vi_mrsz_soft_rst:*/
  218. /* Main-picture resize software reset */
  219. /* 0: processing mode */
  220. /* 1: reset state */
  221. #ifdef MRV_VI_MRSZ_SOFT_RST
  222. #endif /* MRV_VI_MRSZ_SOFT_RST */
  223. /* Slice: vi_ycs_soft_rst:*/
  224. /* y/c splitter software reset */
  225. /* 0: processing mode */
  226. /* 1: reset state */
  227. #ifdef MRV_VI_YCS_SOFT_RST
  228. #endif /* MRV_VI_YCS_SOFT_RST */
  229. /* Slice: vi_cp_soft_rst:*/
  230. /* color processing software reset */
  231. /* 0: processing mode */
  232. /* 1: reset state */
  233. #ifdef MRV_VI_CP_SOFT_RST
  234. #endif /* MRV_VI_CP_SOFT_RST */
  235. /* Slice: vi_isp_soft_rst:*/
  236. /* isp software reset */
  237. /* 0: processing mode */
  238. /* 1: reset state */
  239. #ifdef MRV_VI_ISP_SOFT_RST
  240. #endif /* MRV_VI_ISP_SOFT_RST */
  241. /*****************************************************************************/
  242. /**
  243. * register: vi_dpcl: Data path control register (0x0018)
  244. *
  245. *****************************************************************************/
  246. /* Slice: vi_dma_spmux:*/
  247. /* 0: data from camera interface to self resize */
  248. /* 1: data from DMA read port to self resize */
  249. #ifdef MRV_VI_DMA_SPMUX
  250. #define MRV_VI_DMA_SPMUX_CAM 0 /* 0: data from camera interface to self resize */
  251. #define MRV_VI_DMA_SPMUX_DMA 1 /* 1: data from DMA read port to self resize */
  252. #endif /* MRV_VI_DMA_SPMUX */
  253. /* Slice: vi_dma_iemux:*/
  254. /* 0: data from camera interface to image effects */
  255. /* 1: data from DMA read port to image effects */
  256. #ifdef MRV_VI_DMA_IEMUX
  257. #define MRV_VI_DMA_IEMUX_CAM 0 /* 0: data from camera interface to image effects */
  258. #define MRV_VI_DMA_IEMUX_DMA 1 /* 1: data from DMA read port to image effects */
  259. #endif /* MRV_VI_DMA_IEMUX */
  260. /* Slice: if_select:*/
  261. /* selects input interface */
  262. /* 0: parallel interface */
  263. /* 1: SMIA-interface */
  264. /* 2: MIPI-interface */
  265. #ifdef MRV_IF_SELECT
  266. #define MRV_IF_SELECT_PAR 0 /* 0: parallel interface */
  267. #define MRV_IF_SELECT_SMIA 1 /* 1: SMIA-interface */
  268. #define MRV_IF_SELECT_MIPI 2 /* 2: MIPI-interface */
  269. #define MRV_IF_SELECT_HDR 3 /* 2: HDR-interface */
  270. #endif /* MRV_IF_SELECT */
  271. /* Slice: vi_dma_switch:*/
  272. /* DMA read data path selector */
  273. /* 0: path to SPMUX */
  274. /* 1: path to Superimpose */
  275. /* 2: path to Image Effects */
  276. /* 3: reserved (for path to JPEG)*/
  277. /* 4..7: reserved */
  278. #ifdef MRV_VI_DMA_SWITCH
  279. #define MRV_VI_DMA_SWITCH_SELF 0 /* 0: path to SPMUX */
  280. #define MRV_VI_DMA_SWITCH_SIMP 1 /* 1: path to Superimpose */
  281. #define MRV_VI_DMA_SWITCH_IE 2 /* 2: path to Image Effects */
  282. #define MRV_VI_DMA_SWITCH_JPG 3 /* 3: path to JPEG */
  283. #define MRV_VI_DMA_SWITCH_ISP 4 /* 4: path to ISP */
  284. #endif /* MRV_VI_DMA_SWITCH */
  285. /* Slice: vi_chan_mode:*/
  286. /* Y/C splitter channel mode */
  287. /* 0: disabled */
  288. /* 1: main path and raw data mode */
  289. /* 2: self path mode */
  290. /* 3: main and self path mode */
  291. #ifdef MRV_VI_CHAN_MODE
  292. #define MRV_VI_CHAN_MODE_OFF 0x00 /* 0: disabled */
  293. #define MRV_VI_CHAN_MODE_Y 0xFF /* not supported */
  294. #define MRV_VI_CHAN_MODE_MP_RAW 0x01 /* 1: main path and raw data mode */
  295. #define MRV_VI_CHAN_MODE_MP 0x01 /* 1: main path and raw data mode */
  296. #define MRV_VI_CHAN_MODE_SP 0x02 /* 2: self path mode */
  297. #define MRV_VI_CHAN_MODE_MP_SP 0x03 /* 3: main and self path mode */
  298. #define MRV_VI_CHAN_MODE_SP2 0x04 /* 4: self2 path mode */
  299. #define MRV_VI_CHAN_MODE_MP_SP2 0x05 /* 5: main and self2 path mode */
  300. #define MRV_VI_CHAN_MODE_SP_SP2 0x06 /* 6: self and self2 path mode */
  301. #define MRV_VI_CHAN_MODE_MP_SP_SP2 0x07 /* 7: main self and self2 path mode */
  302. #endif /* MRV_VI_CHAN_MODE */
  303. /* Slice: vi_mp_mux:*/
  304. /* data path selector for main path */
  305. /* 00: reserved (future: data from DMA read port to JPEG encoder)*/
  306. /* 01: data from main resize to MI, uncompressed */
  307. /* 10: data from main resize to JPEG encoder */
  308. /* 11: reserved */
  309. #ifdef MRV_VI_MP_MUX
  310. #define MRV_VI_MP_MUX_JPGDIRECT 0x00 /* 00: reserved (future: data from DMA read port to JPEG encoder) */
  311. #define MRV_VI_MP_MUX_MP 0x01 /* 01: data from main resize to MI, uncompressed */
  312. #define MRV_VI_MP_MUX_RAW 0x01 /* (now also used for RAW data bypass) */
  313. #define MRV_VI_MP_MUX_JPEG 0x02 /* 10: data from main resize to JPEG encoder */
  314. #endif /* MRV_VI_MP_MUX */
  315. /*****************************************************************************/
  316. /* Image Effects Registers */
  317. /*****************************************************************************/
  318. /*****************************************************************************/
  319. /**
  320. * register: img_eff_ctrl: Global control register (0x0000)
  321. *
  322. *****************************************************************************/
  323. /* Slice: full_range:*/
  324. /* write 0: pixel value range according to BT.601 */
  325. /* write 1: YCbCr full range 0...255 */
  326. #ifdef MRV_IMGEFF_FULL_RANGE
  327. #define MRV_IMGEFF_FULL_RANGE_FULL 1 /* 1: YCbCr full range 0...255 */
  328. #define MRV_IMGEFF_FULL_RANGE_BT601 0 /* 0: pixel value range according to BT.601 */
  329. #endif /* MRV_IMGEFF_FULL_RANGE */
  330. /* Slice: cfg_upd:*/
  331. /* write 0: nothing happens */
  332. /* write 1: update shadow registers */
  333. /* read: always 0 */
  334. #ifdef MRV_IMGEFF_CFG_UPD
  335. #define MRV_IMGEFF_CFG_UPD_NOTHING 0 /* 0: nothing happens */
  336. #define MRV_IMGEFF_CFG_UPD_UPDATE 1 /* 1: update shadow registers */
  337. #endif /* MRV_IMGEFF_CFG_UPD */
  338. /* Slice: effect_mode:*/
  339. /* effect mode */
  340. /* 000: black & white effect (grayscale)*/
  341. /* 001: negative effect */
  342. /* 010: sepia effect */
  343. /* 011: color selection effect */
  344. /* 100: emboss effect */
  345. /* 101: sketch effect */
  346. /* 110: sharpen effect */
  347. /* 111: reserved */
  348. #ifdef MRV_IMGEFF_EFFECT_MODE
  349. #define MRV_IMGEFF_EFFECT_MODE_GRAY 0 /* 000: black & white effect (grayscale) */
  350. #define MRV_IMGEFF_EFFECT_MODE_NEGATIVE 1 /* 001: negative effect */
  351. #define MRV_IMGEFF_EFFECT_MODE_SEPIA 2 /* 010: sepia effect */
  352. #define MRV_IMGEFF_EFFECT_MODE_COLOR_SEL 3 /* 011: color selection effect */
  353. #define MRV_IMGEFF_EFFECT_MODE_EMBOSS 4 /* 100: emboss effect */
  354. #define MRV_IMGEFF_EFFECT_MODE_SKETCH 5 /* 101: sketch effect */
  355. #define MRV_IMGEFF_EFFECT_MODE_SHARPEN 6 /* 110: sharpen effect */
  356. #endif /* MRV_IMGEFF_EFFECT_MODE */
  357. /* Slice: bypass_mode:*/
  358. /* bypass mode */
  359. /* 1: processing is activated */
  360. /* 0: processing is deactivated, bypass mode is selected */
  361. #ifdef MRV_IMGEFF_BYPASS_MODE
  362. #define MRV_IMGEFF_BYPASS_MODE_PROCESS 1 /* 1: processing is activated */
  363. #define MRV_IMGEFF_BYPASS_MODE_BYPASS 0 /* 0: processing is deactivated, bypass mode is selected */
  364. #endif /* MRV_IMGEFF_BYPASS_MODE */
  365. /*****************************************************************************/
  366. /**
  367. * register: img_eff_color_sel: Color selection register (for
  368. * color selection effect) (0x0004)
  369. *
  370. *****************************************************************************/
  371. /* Slice: color_threshold:*/
  372. /* Threshold value of the RGB colors for the color selection effect.*/
  373. #ifdef MRV_IMGEFF_COLOR_THRESHOLD
  374. #endif /* MRV_IMGEFF_COLOR_THRESHOLD */
  375. /* Slice: color_selection:*/
  376. /* Defining the maintained color:*/
  377. /* 000: red green and blue */
  378. /* 001: blue */
  379. /* 010: green */
  380. /* 011: green and blue */
  381. /* 100: red */
  382. /* 101: red and blue */
  383. /* 110: red and green */
  384. /* 111: red green and blue */
  385. #ifdef MRV_IMGEFF_COLOR_SELECTION
  386. #define MRV_IMGEFF_COLOR_SELECTION_RGB 0 /* 000: red green and blue */
  387. #define MRV_IMGEFF_COLOR_SELECTION_B 1 /* 001: blue */
  388. #define MRV_IMGEFF_COLOR_SELECTION_G 2 /* 010: green */
  389. #define MRV_IMGEFF_COLOR_SELECTION_BG 3 /* 011: green and blue */
  390. #define MRV_IMGEFF_COLOR_SELECTION_R 4 /* 100: red */
  391. #define MRV_IMGEFF_COLOR_SELECTION_RB 5 /* 101: red and blue */
  392. #define MRV_IMGEFF_COLOR_SELECTION_RG 6 /* 110: red and green */
  393. #define MRV_IMGEFF_COLOR_SELECTION_BGR 7 /* 111: red green and blue */
  394. #endif /* MRV_IMGEFF_COLOR_SELECTION */
  395. /* Slice: emb_coef_21_en:*/
  396. /* 0: entry not used (coefficient is zero)*/
  397. /* 1: entry used */
  398. #ifdef MRV_IMGEFF_EMB_COEF_21_EN
  399. #endif /* MRV_IMGEFF_EMB_COEF_21_EN */
  400. /* Slice: emb_coef_21:*/
  401. /* second line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  402. /* coefficients:*/
  403. /* 000 (1), 001(2), 010(4), 011(8)*/
  404. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  405. #ifdef MRV_IMGEFF_EMB_COEF_21
  406. #define MRV_IMGEFF_EMB_COEF_21_ONE 0 /* 000 (1) */
  407. #define MRV_IMGEFF_EMB_COEF_21_TWO 1 /* 001 (2) */
  408. #define MRV_IMGEFF_EMB_COEF_21_FOUR 2 /* 010 (4) */
  409. #define MRV_IMGEFF_EMB_COEF_21_EIGHT 3 /* 011 (8) */
  410. #define MRV_IMGEFF_EMB_COEF_21_MIN_ONE 4 /* 100 (-1) */
  411. #define MRV_IMGEFF_EMB_COEF_21_MIN_TWO 5 /* 101 (-2) */
  412. #define MRV_IMGEFF_EMB_COEF_21_MIN_FOUR 6 /* 110 (-4) */
  413. #define MRV_IMGEFF_EMB_COEF_21_MIN_EIGHT 8 /* 111 (-8) */
  414. #endif /* MRV_IMGEFF_EMB_COEF_21 */
  415. /* combination of value and enable bit */
  416. #define MRV_IMGEFF_EMB_COEF_21_4
  417. #define MRV_IMGEFF_EMB_COEF_21_4_MASK 0x0000F000
  418. #define MRV_IMGEFF_EMB_COEF_21_4_SHIFT 12
  419. /* Slice: emb_coef_13_en:*/
  420. /* 0: entry not used (coefficient is zero)*/
  421. /* 1: entry used */
  422. #ifdef MRV_IMGEFF_EMB_COEF_13_EN
  423. #endif /* MRV_IMGEFF_EMB_COEF_13_EN */
  424. /* Slice: emb_coef_13:*/
  425. /* first line, right entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  426. /* coefficients:*/
  427. /* 000 (1), 001(2), 010(4), 011(8)*/
  428. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  429. #ifdef MRV_IMGEFF_EMB_COEF_13
  430. #define MRV_IMGEFF_EMB_COEF_13_ONE 0 /* 000 (1) */
  431. #define MRV_IMGEFF_EMB_COEF_13_TWO 1 /* 001 (2) */
  432. #define MRV_IMGEFF_EMB_COEF_13_FOUR 2 /* 010 (4) */
  433. #define MRV_IMGEFF_EMB_COEF_13_EIGHT 3 /* 011 (8) */
  434. #define MRV_IMGEFF_EMB_COEF_13_MIN_ONE 4 /* 100 (-1) */
  435. #define MRV_IMGEFF_EMB_COEF_13_MIN_TWO 5 /* 101 (-2) */
  436. #define MRV_IMGEFF_EMB_COEF_13_MIN_FOUR 6 /* 110 (-4) */
  437. #define MRV_IMGEFF_EMB_COEF_13_MIN_EIGHT 8 /* 111 (-8) */
  438. #endif /* MRV_IMGEFF_EMB_COEF_13 */
  439. /* combination of value and enable bit */
  440. #define MRV_IMGEFF_EMB_COEF_13_4
  441. #define MRV_IMGEFF_EMB_COEF_13_4_MASK 0x00000F00
  442. #define MRV_IMGEFF_EMB_COEF_13_4_SHIFT 8
  443. /* Slice: emb_coef_12_en:*/
  444. /* 0: entry not used (coefficient is zero)*/
  445. /* 1: entry used */
  446. #ifdef MRV_IMGEFF_EMB_COEF_12_EN
  447. #endif /* MRV_IMGEFF_EMB_COEF_12_EN */
  448. /* Slice: emb_coef_12:*/
  449. /* first line, middle entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  450. /* coefficients:*/
  451. /* 000 (1), 001(2), 010(4), 011(8)*/
  452. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  453. #ifdef MRV_IMGEFF_EMB_COEF_12
  454. #define MRV_IMGEFF_EMB_COEF_12_ONE 0 /* 000 (1) */
  455. #define MRV_IMGEFF_EMB_COEF_12_TWO 1 /* 001 (2) */
  456. #define MRV_IMGEFF_EMB_COEF_12_FOUR 2 /* 010 (4) */
  457. #define MRV_IMGEFF_EMB_COEF_12_EIGHT 3 /* 011 (8) */
  458. #define MRV_IMGEFF_EMB_COEF_12_MIN_ONE 4 /* 100 (-1) */
  459. #define MRV_IMGEFF_EMB_COEF_12_MIN_TWO 5 /* 101 (-2) */
  460. #define MRV_IMGEFF_EMB_COEF_12_MIN_FOUR 6 /* 110 (-4) */
  461. #define MRV_IMGEFF_EMB_COEF_12_MIN_EIGHT 8 /* 111 (-8) */
  462. #endif /* MRV_IMGEFF_EMB_COEF_12 */
  463. /* combination of value and enable bit */
  464. #define MRV_IMGEFF_EMB_COEF_12_4
  465. #define MRV_IMGEFF_EMB_COEF_12_4_MASK 0x000000F0
  466. #define MRV_IMGEFF_EMB_COEF_12_4_SHIFT 4
  467. /* Slice: emb_coef_11_en:*/
  468. /* 0: entry not used (coefficient is zero)*/
  469. /* 1: entry used */
  470. #ifdef MRV_IMGEFF_EMB_COEF_11_EN
  471. #define MRV_IMGEFF_EMB_COEF_11_EN_ON 1
  472. #define MRV_IMGEFF_EMB_COEF_11_EN_OFF 0
  473. #endif /* MRV_IMGEFF_EMB_COEF_11_EN */
  474. /* Slice: emb_coef_11:*/
  475. /* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  476. /* coefficients:*/
  477. /* 000 (1), 001(2), 010(4), 011(8)*/
  478. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  479. #ifdef MRV_IMGEFF_EMB_COEF_11
  480. #define MRV_IMGEFF_EMB_COEF_11_ONE 0 /* 000 (1) */
  481. #define MRV_IMGEFF_EMB_COEF_11_TWO 1 /* 001 (2) */
  482. #define MRV_IMGEFF_EMB_COEF_11_FOUR 2 /* 010 (4) */
  483. #define MRV_IMGEFF_EMB_COEF_11_EIGHT 3 /* 011 (8) */
  484. #define MRV_IMGEFF_EMB_COEF_11_MIN_ONE 4 /* 100 (-1) */
  485. #define MRV_IMGEFF_EMB_COEF_11_MIN_TWO 5 /* 101 (-2) */
  486. #define MRV_IMGEFF_EMB_COEF_11_MIN_FOUR 6 /* 110 (-4) */
  487. #define MRV_IMGEFF_EMB_COEF_11_MIN_EIGHT 8 /* 111 (-8) */
  488. #endif /* MRV_IMGEFF_EMB_COEF_11 */
  489. /* combination of value and enable bit */
  490. #define MRV_IMGEFF_EMB_COEF_11_4
  491. #define MRV_IMGEFF_EMB_COEF_11_4_MASK 0x0000000F
  492. #define MRV_IMGEFF_EMB_COEF_11_4_SHIFT 0
  493. /* Slice: emb_coef_32_en:*/
  494. /* 0: entry not used (coefficient is zero)*/
  495. /* 1: entry used */
  496. #ifdef MRV_IMGEFF_EMB_COEF_32_EN
  497. #endif /* MRV_IMGEFF_EMB_COEF_32_EN */
  498. /* Slice: emb_coef_32:*/
  499. /* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  500. /* coefficients:*/
  501. /* 000 (1), 001(2), 010(4), 011(8)*/
  502. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  503. #ifdef MRV_IMGEFF_EMB_COEF_32
  504. #define MRV_IMGEFF_EMB_COEF_32_ONE 0 /* 000 (1) */
  505. #define MRV_IMGEFF_EMB_COEF_32_TWO 1 /* 001 (2) */
  506. #define MRV_IMGEFF_EMB_COEF_32_FOUR 2 /* 010 (4) */
  507. #define MRV_IMGEFF_EMB_COEF_32_EIGHT 3 /* 011 (8) */
  508. #define MRV_IMGEFF_EMB_COEF_32_MIN_ONE 4 /* 100 (-1) */
  509. #define MRV_IMGEFF_EMB_COEF_32_MIN_TWO 5 /* 101 (-2) */
  510. #define MRV_IMGEFF_EMB_COEF_32_MIN_FOUR 6 /* 110 (-4) */
  511. #define MRV_IMGEFF_EMB_COEF_32_MIN_EIGHT 8 /* 111 (-8) */
  512. #endif /* MRV_IMGEFF_EMB_COEF_32 */
  513. /* combination of value and enable bit */
  514. #define MRV_IMGEFF_EMB_COEF_32_4
  515. #define MRV_IMGEFF_EMB_COEF_32_4_MASK 0x0000F000
  516. #define MRV_IMGEFF_EMB_COEF_32_4_SHIFT 12
  517. /* Slice: emb_coef_31_en:*/
  518. /* 0: entry not used (coefficient is zero)*/
  519. /* 1: entry used */
  520. #ifdef MRV_IMGEFF_EMB_COEF_31_EN
  521. #endif /* MRV_IMGEFF_EMB_COEF_31_EN */
  522. /* Slice: emb_coef_31:*/
  523. /* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  524. /* coefficients:*/
  525. /* 000 (1), 001(2), 010(4), 011(8)*/
  526. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  527. #ifdef MRV_IMGEFF_EMB_COEF_31
  528. #define MRV_IMGEFF_EMB_COEF_31_ONE 0 /* 000 (1) */
  529. #define MRV_IMGEFF_EMB_COEF_31_TWO 1 /* 001 (2) */
  530. #define MRV_IMGEFF_EMB_COEF_31_FOUR 2 /* 010 (4) */
  531. #define MRV_IMGEFF_EMB_COEF_31_EIGHT 3 /* 011 (8) */
  532. #define MRV_IMGEFF_EMB_COEF_31_MIN_ONE 4 /* 100 (-1) */
  533. #define MRV_IMGEFF_EMB_COEF_31_MIN_TWO 5 /* 101 (-2) */
  534. #define MRV_IMGEFF_EMB_COEF_31_MIN_FOUR 6 /* 110 (-4) */
  535. #define MRV_IMGEFF_EMB_COEF_31_MIN_EIGHT 8 /* 111 (-8) */
  536. #endif /* MRV_IMGEFF_EMB_COEF_31 */
  537. /* combination of value and enable bit */
  538. #define MRV_IMGEFF_EMB_COEF_31_4
  539. #define MRV_IMGEFF_EMB_COEF_31_4_MASK 0x00000F00
  540. #define MRV_IMGEFF_EMB_COEF_31_4_SHIFT 8
  541. /* Slice: emb_coef_23_en:*/
  542. /* 0: entry not used (coefficient is zero)*/
  543. /* 1: entry used */
  544. #ifdef MRV_IMGEFF_EMB_COEF_23_EN
  545. #endif /* MRV_IMGEFF_EMB_COEF_23_EN */
  546. /* Slice: emb_coef_23:*/
  547. /* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  548. /* coefficients:*/
  549. /* 000 (1), 001(2), 010(4), 011(8)*/
  550. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  551. #ifdef MRV_IMGEFF_EMB_COEF_23
  552. #define MRV_IMGEFF_EMB_COEF_23_ONE 0 /* 000 (1) */
  553. #define MRV_IMGEFF_EMB_COEF_23_TWO 1 /* 001 (2) */
  554. #define MRV_IMGEFF_EMB_COEF_23_FOUR 2 /* 010 (4) */
  555. #define MRV_IMGEFF_EMB_COEF_23_EIGHT 3 /* 011 (8) */
  556. #define MRV_IMGEFF_EMB_COEF_23_MIN_ONE 4 /* 100 (-1) */
  557. #define MRV_IMGEFF_EMB_COEF_23_MIN_TWO 5 /* 101 (-2) */
  558. #define MRV_IMGEFF_EMB_COEF_23_MIN_FOUR 6 /* 110 (-4) */
  559. #define MRV_IMGEFF_EMB_COEF_23_MIN_EIGHT 8 /* 111 (-8) */
  560. #endif /* MRV_IMGEFF_EMB_COEF_23 */
  561. /* combination of value and enable bit */
  562. #define MRV_IMGEFF_EMB_COEF_23_4
  563. #define MRV_IMGEFF_EMB_COEF_23_4_MASK 0x000000F0
  564. #define MRV_IMGEFF_EMB_COEF_23_4_SHIFT 4
  565. /* Slice: emb_coef_22_en:*/
  566. /* 0: entry not used (coefficient is zero)*/
  567. /* 1: entry used */
  568. #ifdef MRV_IMGEFF_EMB_COEF_22_EN
  569. #endif /* MRV_IMGEFF_EMB_COEF_22_EN */
  570. /* Slice: emb_coef_22:*/
  571. /* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  572. /* coefficients:*/
  573. /* 000 (1), 001(2), 010(4), 011(8)*/
  574. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  575. #ifdef MRV_IMGEFF_EMB_COEF_22
  576. #define MRV_IMGEFF_EMB_COEF_22_ONE 0 /* 000 (1) */
  577. #define MRV_IMGEFF_EMB_COEF_22_TWO 1 /* 001 (2) */
  578. #define MRV_IMGEFF_EMB_COEF_22_FOUR 2 /* 010 (4) */
  579. #define MRV_IMGEFF_EMB_COEF_22_EIGHT 3 /* 011 (8) */
  580. #define MRV_IMGEFF_EMB_COEF_22_MIN_ONE 4 /* 100 (-1) */
  581. #define MRV_IMGEFF_EMB_COEF_22_MIN_TWO 5 /* 101 (-2) */
  582. #define MRV_IMGEFF_EMB_COEF_22_MIN_FOUR 6 /* 110 (-4) */
  583. #define MRV_IMGEFF_EMB_COEF_22_MIN_EIGHT 8 /* 111 (-8) */
  584. #endif /* MRV_IMGEFF_EMB_COEF_22 */
  585. /* combination of value and enable bit */
  586. #define MRV_IMGEFF_EMB_COEF_22_4
  587. #define MRV_IMGEFF_EMB_COEF_22_4_MASK 0x0000000F
  588. #define MRV_IMGEFF_EMB_COEF_22_4_SHIFT 0
  589. /*****************************************************************************/
  590. /**
  591. * register: img_eff_mat_3: 3x3 matrix coefficients for emboss(3) effect /
  592. * sketch(1) effect (0x0010)
  593. *
  594. *****************************************************************************/
  595. /* Slice: sket_coef_13_en:*/
  596. /* 0: entry not used (coefficient is zero)*/
  597. /* 1: entry used */
  598. #ifdef MRV_IMGEFF_SKET_COEF_13_EN
  599. #endif /* MRV_IMGEFF_SKET_COEF_13_EN */
  600. /* Slice: sket_coef_13:*/
  601. /* first line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  602. /* coefficients:*/
  603. /* 000 (1), 001(2), 010(4), 011(8)*/
  604. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  605. #ifdef MRV_IMGEFF_SKET_COEF_13
  606. #define MRV_IMGEFF_SKET_COEF_13_ONE 0 /* 000 (1) */
  607. #define MRV_IMGEFF_SKET_COEF_13_TWO 1 /* 001 (2) */
  608. #define MRV_IMGEFF_SKET_COEF_13_FOUR 2 /* 010 (4) */
  609. #define MRV_IMGEFF_SKET_COEF_13_EIGHT 3 /* 011 (8) */
  610. #define MRV_IMGEFF_SKET_COEF_13_MIN_ONE 4 /* 100 (-1) */
  611. #define MRV_IMGEFF_SKET_COEF_13_MIN_TWO 5 /* 101 (-2) */
  612. #define MRV_IMGEFF_SKET_COEF_13_MIN_FOUR 6 /* 110 (-4) */
  613. #define MRV_IMGEFF_SKET_COEF_13_MIN_EIGHT 8 /* 111 (-8) */
  614. #endif /* MRV_IMGEFF_SKET_COEF_13 */
  615. /* combination of value and enable bit */
  616. #define MRV_IMGEFF_SKET_COEF_13_4
  617. #define MRV_IMGEFF_SKET_COEF_13_4_MASK 0x0000F000
  618. #define MRV_IMGEFF_SKET_COEF_13_4_SHIFT 12
  619. /* Slice: sket_coef_12_en:*/
  620. /* 0: entry not used (coefficient is zero)*/
  621. /* 1: entry used */
  622. #ifdef MRV_IMGEFF_SKET_COEF_12_EN
  623. #endif /* MRV_IMGEFF_SKET_COEF_13_EN */
  624. /* Slice: sket_coef_12:*/
  625. /* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  626. /* coefficients:*/
  627. /* 000 (1), 001(2), 010(4), 011(8)*/
  628. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  629. #ifdef MRV_IMGEFF_SKET_COEF_12
  630. #define MRV_IMGEFF_SKET_COEF_12_ONE 0 /* 000 (1) */
  631. #define MRV_IMGEFF_SKET_COEF_12_TWO 1 /* 001 (2) */
  632. #define MRV_IMGEFF_SKET_COEF_12_FOUR 2 /* 010 (4) */
  633. #define MRV_IMGEFF_SKET_COEF_12_EIGHT 3 /* 011 (8) */
  634. #define MRV_IMGEFF_SKET_COEF_12_MIN_ONE 4 /* 100 (-1) */
  635. #define MRV_IMGEFF_SKET_COEF_12_MIN_TWO 5 /* 101 (-2) */
  636. #define MRV_IMGEFF_SKET_COEF_12_MIN_FOUR 6 /* 110 (-4) */
  637. #define MRV_IMGEFF_SKET_COEF_12_MIN_EIGHT 8 /* 111 (-8) */
  638. #endif /* MRV_IMGEFF_SKET_COEF_12 */
  639. /* combination of value and enable bit */
  640. #define MRV_IMGEFF_SKET_COEF_12_4
  641. #define MRV_IMGEFF_SKET_COEF_12_4_MASK 0x00000F00
  642. #define MRV_IMGEFF_SKET_COEF_12_4_SHIFT 8
  643. /* Slice: sket_coef_11_en:*/
  644. /* 0: entry not used (coefficient is zero)*/
  645. /* 1: entry used */
  646. #ifdef MRV_IMGEFF_SKET_COEF_11_EN
  647. #endif /* MRV_IMGEFF_SKET_COEF_13_EN */
  648. /* Slice: sket_coef_11:*/
  649. /* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  650. /* coefficients:*/
  651. /* 000 (1), 001(2), 010(4), 011(8)*/
  652. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  653. #ifdef MRV_IMGEFF_SKET_COEF_11
  654. #define MRV_IMGEFF_SKET_COEF_11_ONE 0 /* 000 (1) */
  655. #define MRV_IMGEFF_SKET_COEF_11_TWO 1 /* 001 (2) */
  656. #define MRV_IMGEFF_SKET_COEF_11_FOUR 2 /* 010 (4) */
  657. #define MRV_IMGEFF_SKET_COEF_11_EIGHT 3 /* 011 (8) */
  658. #define MRV_IMGEFF_SKET_COEF_11_MIN_ONE 4 /* 100 (-1) */
  659. #define MRV_IMGEFF_SKET_COEF_11_MIN_TWO 5 /* 101 (-2) */
  660. #define MRV_IMGEFF_SKET_COEF_11_MIN_FOUR 6 /* 110 (-4) */
  661. #define MRV_IMGEFF_SKET_COEF_11_MIN_EIGHT 8 /* 111 (-8) */
  662. #endif /* MRV_IMGEFF_SKET_COEF_11 */
  663. /* combination of value and enable bit */
  664. #define MRV_IMGEFF_SKET_COEF_11_4
  665. #define MRV_IMGEFF_SKET_COEF_11_4_MASK 0x000000F0
  666. #define MRV_IMGEFF_SKET_COEF_11_4_SHIFT 4
  667. /* Slice: emb_coef_33_en:*/
  668. /* 0: entry not used (coefficient is zero)*/
  669. /* 1: entry used */
  670. #ifdef MRV_IMGEFF_EMB_COEF_33_EN
  671. #endif /* MRV_IMGEFF_EMB_COEF_33_EN */
  672. /* Slice: emb_coef_33:*/
  673. /* first line, left entry of 3x3 emboss effect matrix, 2 bit for coefficient, one sign bit.*/
  674. /* coefficients:*/
  675. /* 000 (1), 001(2), 010(4), 011(8)*/
  676. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  677. #ifdef MRV_IMGEFF_EMB_COEF_3
  678. #define MRV_IMGEFF_EMB_COEF_33_ONE 0 /* 000 (1) */
  679. #define MRV_IMGEFF_EMB_COEF_33_TWO 1 /* 001 (2) */
  680. #define MRV_IMGEFF_EMB_COEF_33_FOUR 2 /* 010 (4) */
  681. #define MRV_IMGEFF_EMB_COEF_33_EIGHT 3 /* 011 (8) */
  682. #define MRV_IMGEFF_EMB_COEF_33_MIN_ONE 4 /* 100 (-1) */
  683. #define MRV_IMGEFF_EMB_COEF_33_MIN_TWO 5 /* 101 (-2) */
  684. #define MRV_IMGEFF_EMB_COEF_33_MIN_FOUR 6 /* 110 (-4) */
  685. #define MRV_IMGEFF_EMB_COEF_33_MIN_EIGHT 8 /* 111 (-8) */
  686. #endif /* MRV_IMGEFF_EMB_COEF_33 */
  687. /* combination of value and enable bit */
  688. #define MRV_IMGEFF_EMB_COEF_33_4
  689. #define MRV_IMGEFF_EMB_COEF_33_4_MASK 0x0000000F
  690. #define MRV_IMGEFF_EMB_COEF_33_4_SHIFT 0
  691. /*****************************************************************************/
  692. /**
  693. * register: img_eff_mat_4: 3x3 matrix coefficients for sketch effect (2)
  694. * (0x0014)
  695. *
  696. *****************************************************************************/
  697. /* Slice: sket_coef_31_en:*/
  698. /* 0: entry not used (coefficient is zero)*/
  699. /* 1: entry used */
  700. #ifdef MRV_IMGEFF_SKET_COEF_31_EN
  701. #endif /* MRV_IMGEFF_SKET_COEF_31_EN */
  702. /* Slice: sket_coef_31:*/
  703. /* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  704. /* coefficients:*/
  705. /* 000 (1), 001(2), 010(4), 011(8)*/
  706. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  707. #ifdef MRV_IMGEFF_SKET_COEF_31
  708. #define MRV_IMGEFF_SKET_COEF_31_ONE 0 /* 000 (1) */
  709. #define MRV_IMGEFF_SKET_COEF_31_TWO 1 /* 001 (2) */
  710. #define MRV_IMGEFF_SKET_COEF_31_FOUR 2 /* 010 (4) */
  711. #define MRV_IMGEFF_SKET_COEF_31_EIGHT 3 /* 011 (8) */
  712. #define MRV_IMGEFF_SKET_COEF_31_MIN_ONE 4 /* 100 (-1) */
  713. #define MRV_IMGEFF_SKET_COEF_31_MIN_TWO 5 /* 101 (-2) */
  714. #define MRV_IMGEFF_SKET_COEF_31_MIN_FOUR 6 /* 110 (-4) */
  715. #define MRV_IMGEFF_SKET_COEF_31_MIN_EIGHT 8 /* 111 (-8) */
  716. #endif /* MRV_IMGEFF_SKET_COEF_31 */
  717. /* combination of value and enable bit */
  718. #define MRV_IMGEFF_SKET_COEF_31_4
  719. #define MRV_IMGEFF_SKET_COEF_31_4_MASK 0x0000F000
  720. #define MRV_IMGEFF_SKET_COEF_31_4_SHIFT 12
  721. /* Slice: sket_coef_23_en:*/
  722. /* 0: entry not used (coefficient is zero)*/
  723. /* 1: entry used */
  724. #ifdef MRV_IMGEFF_SKET_COEF_23_EN
  725. #endif /* MRV_IMGEFF_SKET_COEF_23_EN */
  726. /* Slice: sket_coef_23:*/
  727. /* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  728. /* coefficients:*/
  729. /* 000 (1), 001(2), 010(4), 011(8)*/
  730. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  731. #ifdef MRV_IMGEFF_SKET_COEF_23
  732. #define MRV_IMGEFF_SKET_COEF_23_ONE 0 /* 000 (1) */
  733. #define MRV_IMGEFF_SKET_COEF_23_TWO 1 /* 001 (2) */
  734. #define MRV_IMGEFF_SKET_COEF_23_FOUR 2 /* 010 (4) */
  735. #define MRV_IMGEFF_SKET_COEF_23_EIGHT 3 /* 011 (8) */
  736. #define MRV_IMGEFF_SKET_COEF_23_MIN_ONE 4 /* 100 (-1) */
  737. #define MRV_IMGEFF_SKET_COEF_23_MIN_TWO 5 /* 101 (-2) */
  738. #define MRV_IMGEFF_SKET_COEF_23_MIN_FOUR 6 /* 110 (-4) */
  739. #define MRV_IMGEFF_SKET_COEF_23_MIN_EIGHT 8 /* 111 (-8) */
  740. #endif /* MRV_IMGEFF_SKET_COEF_23 */
  741. /* combination of value and enable bit */
  742. #define MRV_IMGEFF_SKET_COEF_23_4
  743. #define MRV_IMGEFF_SKET_COEF_23_4_MASK 0x00000F00
  744. #define MRV_IMGEFF_SKET_COEF_23_4_SHIFT 8
  745. /* Slice: sket_coef_22_en:*/
  746. /* 0: entry not used (coefficient is zero)*/
  747. /* 1: entry used */
  748. #ifdef MRV_IMGEFF_SKET_COEF_22_EN
  749. #endif /* MRV_IMGEFF_SKET_COEF_22_EN */
  750. /* Slice: sket_coef_22:*/
  751. /* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  752. /* coefficients:*/
  753. /* 000 (1), 001(2), 010(4), 011(8)*/
  754. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  755. #ifdef MRV_IMGEFF_SKET_COEF_22
  756. #define MRV_IMGEFF_SKET_COEF_22_ONE 0 /* 000 (1) */
  757. #define MRV_IMGEFF_SKET_COEF_22_TWO 1 /* 001 (2) */
  758. #define MRV_IMGEFF_SKET_COEF_22_FOUR 2 /* 010 (4) */
  759. #define MRV_IMGEFF_SKET_COEF_22_EIGHT 3 /* 011 (8) */
  760. #define MRV_IMGEFF_SKET_COEF_22_MIN_ONE 4 /* 100 (-1) */
  761. #define MRV_IMGEFF_SKET_COEF_22_MIN_TWO 5 /* 101 (-2) */
  762. #define MRV_IMGEFF_SKET_COEF_22_MIN_FOUR 6 /* 110 (-4) */
  763. #define MRV_IMGEFF_SKET_COEF_22_MIN_EIGHT 8 /* 111 (-8) */
  764. #endif /* MRV_IMGEFF_SKET_COEF_22 */
  765. /* combination of value and enable bit */
  766. #define MRV_IMGEFF_SKET_COEF_22_4
  767. #define MRV_IMGEFF_SKET_COEF_22_4_MASK 0x000000F0
  768. #define MRV_IMGEFF_SKET_COEF_22_4_SHIFT 4
  769. /* Slice: sket_coef_21_en:*/
  770. /* 0: entry not used (coefficient is zero)*/
  771. /* 1: entry used */
  772. #ifdef MRV_IMGEFF_SKET_COEF_21_EN
  773. #endif /* MRV_IMGEFF_SKET_COEF_21_EN */
  774. /* Slice: sket_coef_21:*/
  775. /* first line, middle entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  776. /* coefficients:*/
  777. /* 000 (1), 001(2), 010(4), 011(8)*/
  778. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  779. #ifdef MRV_IMGEFF_SKET_COEF_21
  780. #define MRV_IMGEFF_SKET_COEF_21_ONE 0 /* 000 (1) */
  781. #define MRV_IMGEFF_SKET_COEF_21_TWO 1 /* 001 (2) */
  782. #define MRV_IMGEFF_SKET_COEF_21_FOUR 2 /* 010 (4) */
  783. #define MRV_IMGEFF_SKET_COEF_21_EIGHT 3 /* 011 (8) */
  784. #define MRV_IMGEFF_SKET_COEF_21_MIN_ONE 4 /* 100 (-1) */
  785. #define MRV_IMGEFF_SKET_COEF_21_MIN_TWO 5 /* 101 (-2) */
  786. #define MRV_IMGEFF_SKET_COEF_21_MIN_FOUR 6 /* 110 (-4) */
  787. #define MRV_IMGEFF_SKET_COEF_21_MIN_EIGHT 8 /* 111 (-8) */
  788. #endif /* MRV_IMGEFF_SKET_COEF_21 */
  789. /* combination of value and enable bit */
  790. #define MRV_IMGEFF_SKET_COEF_21_4
  791. #define MRV_IMGEFF_SKET_COEF_21_4_MASK 0x0000000F
  792. #define MRV_IMGEFF_SKET_COEF_21_4_SHIFT 0
  793. /*****************************************************************************/
  794. /**
  795. * register: img_eff_mat_5: 3x3 matrix coefficients for sketch effect (3)
  796. * (0x0018)
  797. *
  798. *****************************************************************************/
  799. /* Slice: sket_coef_33_en:*/
  800. /* 0: entry not used (coefficient is zero)*/
  801. /* 1: entry used */
  802. #ifdef MRV_IMGEFF_SKET_COEF_33_EN
  803. #endif /* MRV_IMGEFF_SKET_COEF_33_EN */
  804. /* Slice: sket_coef_33:*/
  805. /* third line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  806. /* coefficients:*/
  807. /* 000 (1), 001(2), 010(4), 011(8)*/
  808. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  809. #ifdef MRV_IMGEFF_SKET_COEF_33
  810. #define MRV_IMGEFF_SKET_COEF_33_ONE 0 /* 000 (1) */
  811. #define MRV_IMGEFF_SKET_COEF_33_TWO 1 /* 001 (2) */
  812. #define MRV_IMGEFF_SKET_COEF_33_FOUR 2 /* 010 (4) */
  813. #define MRV_IMGEFF_SKET_COEF_33_EIGHT 3 /* 011 (8) */
  814. #define MRV_IMGEFF_SKET_COEF_33_MIN_ONE 4 /* 100 (-1) */
  815. #define MRV_IMGEFF_SKET_COEF_33_MIN_TWO 5 /* 101 (-2) */
  816. #define MRV_IMGEFF_SKET_COEF_33_MIN_FOUR 6 /* 110 (-4) */
  817. #define MRV_IMGEFF_SKET_COEF_33_MIN_EIGHT 8 /* 111 (-8) */
  818. #endif /* MRV_IMGEFF_SKET_COEF_33 */
  819. /* combination of value and enable bit */
  820. #define MRV_IMGEFF_SKET_COEF_33_4
  821. #define MRV_IMGEFF_SKET_COEF_33_4_MASK 0x000000F0
  822. #define MRV_IMGEFF_SKET_COEF_33_4_SHIFT 4
  823. /* Slice: sket_coef_32_en:*/
  824. /* 0: entry not used (coefficient is zero)*/
  825. /* 1: entry used */
  826. #ifdef MRV_IMGEFF_SKET_COEF_32_EN
  827. #endif /* MRV_IMGEFF_SKET_COEF_32_EN */
  828. /* Slice: sket_coef_32:*/
  829. /* third line, right entry of 3x3 sketch effect matrix, 2 bit for coefficient, one sign bit.*/
  830. /* coefficients:*/
  831. /* 000 (1), 001(2), 010(4), 011(8)*/
  832. /* 100 (-1), 101(-2), 110(-4), 111(-8)*/
  833. #ifdef MRV_IMGEFF_SKET_COEF_32
  834. #define MRV_IMGEFF_SKET_COEF_32_ONE 0 /* 000 (1) */
  835. #define MRV_IMGEFF_SKET_COEF_32_TWO 1 /* 001 (2) */
  836. #define MRV_IMGEFF_SKET_COEF_32_FOUR 2 /* 010 (4) */
  837. #define MRV_IMGEFF_SKET_COEF_32_EIGHT 3 /* 011 (8) */
  838. #define MRV_IMGEFF_SKET_COEF_32_MIN_ONE 4 /* 100 (-1) */
  839. #define MRV_IMGEFF_SKET_COEF_32_MIN_TWO 5 /* 101 (-2) */
  840. #define MRV_IMGEFF_SKET_COEF_32_MIN_FOUR 6 /* 110 (-4) */
  841. #define MRV_IMGEFF_SKET_COEF_32_MIN_EIGHT 8 /* 111 (-8) */
  842. #endif /* MRV_IMGEFF_SKET_COEF_32 */
  843. /* combination of value and enable bit */
  844. #define MRV_IMGEFF_SKET_COEF_32_4
  845. #define MRV_IMGEFF_SKET_COEF_32_4_MASK 0x0000000F
  846. #define MRV_IMGEFF_SKET_COEF_32_4_SHIFT 0
  847. /* valid for all coeffiecient definitions */
  848. #define MRV_IMGEFF_COEF
  849. #define MRV_IMGEFF_COEF_ONE 0U
  850. #define MRV_IMGEFF_COEF_TWO 1U /* 001: (2) */
  851. #define MRV_IMGEFF_COEF_FOUR 2U /* 010: (4) */
  852. #define MRV_IMGEFF_COEF_EIGHT 3U /* 011: (8) */
  853. #define MRV_IMGEFF_COEF_MIN_ONE 4U /* 100: (-1) */
  854. #define MRV_IMGEFF_COEF_MIN_TWO 5U /* 101: (-2) */
  855. #define MRV_IMGEFF_COEF_MIN_FOUR 6U /* 110: (-4) */
  856. #define MRV_IMGEFF_COEF_MIN_EIGHT 7U /* 111: (-8) */
  857. #define MRV_IMGEFF_COEF_ON 1U /* 1: coefficient enabled */
  858. #define MRV_IMGEFF_COEF_OFF 0U /* 0: coefficient disabled */
  859. #define MRV_IMGEFF_COEF_SHIFT 3U /* shift for enable bit */
  860. /*****************************************************************************/
  861. /**
  862. * register: img_eff_tint: Chrominance increment values of a tint
  863. * (used for sepia effect) (0x001c)
  864. *
  865. *****************************************************************************/
  866. /* Slice: incr_cr:*/
  867. /* Cr increment value of a tint. 7 bits for value, 1 sign bit.*/
  868. /* Default tint is R=162 G=138 B=101, which is used for the sepia effect. See below for the calculation of the entries.*/
  869. #ifdef MRV_IMGEFF_INCR_CR
  870. #endif /* MRV_IMGEFF_INCR_CR */
  871. /* Slice: incr_cb:*/
  872. /* Cb increment value of a tint. 7 bits for value, 1 sign bit.*/
  873. /* Default tint is R=162 G=138 B=101, which is used for the sepia effect. See below for the calculation of the entries.*/
  874. #ifdef MRV_IMGEFF_INCR_CB
  875. #endif /* MRV_IMGEFF_INCR_CB */
  876. /*****************************************************************************/
  877. /**
  878. * register: img_eff_ctrl_shd: Shadow register for control register (0x0020)
  879. *
  880. *****************************************************************************/
  881. /* Slice: effect_mode_shd:*/
  882. /* effect mode */
  883. /* 000: black & white effect (grayscale)*/
  884. /* 001: negative effect */
  885. /* 010: sepia effect */
  886. /* 011: color selection effect */
  887. /* 100: emboss effect */
  888. /* 101: sketch effect */
  889. /* 110-111: not used */
  890. #ifdef MRV_IMGEFF_EFFECT_MODE_SHD
  891. #define MRV_IMGEFF_EFFECT_MODE_SHD_GRAY 0 /* 000: black & white effect (grayscale) */
  892. #define MRV_IMGEFF_EFFECT_MODE_SHD_NEGATIVE 1 /* 001: negative effect */
  893. #define MRV_IMGEFF_EFFECT_MODE_SHD_SEPIA 2 /* 010: sepia effect */
  894. #define MRV_IMGEFF_EFFECT_MODE_SHD_COLOR_SEL 3 /* 011: color selection effect */
  895. #define MRV_IMGEFF_EFFECT_MODE_SHD_EMBOSS 4 /* 100: emboss effect */
  896. #define MRV_IMGEFF_EFFECT_MODE_SHD_SKETCH 5 /* 101: sketch effect */
  897. #define MRV_IMGEFF_EFFECT_MODE_SHD_SHARPEN 6 /* 110: sharpen effect */
  898. #endif /* MRV_IMGEFF_EFFECT_MODE_SHD */
  899. /*****************************************************************************/
  900. /* Super Impose Registers */
  901. /*****************************************************************************/
  902. /*****************************************************************************/
  903. /**
  904. * register: super_imp_ctrl: Global control register (0x0000)
  905. *
  906. *****************************************************************************/
  907. /* Slice: transparency_mode:*/
  908. /* transparency mode */
  909. /* 1: transparency mode disabled */
  910. /* 0: transparency mode enabled */
  911. #ifdef MRV_SI_TRANSPARENCY_MODE
  912. #define MRV_SI_TRANSPARENCY_MODE_DISABLED 1 /* 1: transparency mode disabled */
  913. #define MRV_SI_TRANSPARENCY_MODE_ENABLED 0 /* 0: transparency mode enabled */
  914. #endif /* MRV_SI_TRANSPARENCY_MODE */
  915. /* Slice: ref_image:*/
  916. /* Define the reference image */
  917. /* 1: superimpose bitmap from main memory */
  918. /* 0: image from the Image Effect module */
  919. /* Note: the reference image defines the size of the output image */
  920. #ifdef MRV_SI_REF_IMAGE
  921. #define MRV_SI_REF_IMAGE_MEM 1 /* 1: superimpose bitmap from main memory */
  922. #define MRV_SI_REF_IMAGE_IE 0 /* 0: image from the Image Effect module */
  923. #endif /* MRV_SI_REF_IMAGE */
  924. /* Slice: bypass_mode:*/
  925. /* bypass mode */
  926. /* 1: processing is activated */
  927. /* 0: processing is deactivated, bypass mode is selected */
  928. #ifdef MRV_SI_BYPASS_MODE
  929. #define MRV_SI_BYPASS_MODE_PROCESS 1 /* 1: processing is activated */
  930. #define MRV_SI_BYPASS_MODE_BYPASS 0 /* 0: processing is deactivated, bypass mode is selected */
  931. #endif /* MRV_IMGEFF_BYPASS_MODE */
  932. /*****************************************************************************/
  933. /**
  934. * register: super_imp_offset_x: Offset x register (0x0004)
  935. *
  936. *****************************************************************************/
  937. /* Slice: offset_x:*/
  938. /* Offset X */
  939. /* Note: the bit 0 is don't care (write 1 doesn't have any effect, the read access always gives 0)*/
  940. /* Note: the offset_x is positive and refers to the reference image */
  941. #ifdef MRV_SI_OFFSET_X
  942. #endif /* MRV_SI_OFFSET_X */
  943. /*****************************************************************************/
  944. /**
  945. * register: super_imp_offset_y: Offset y register (0x0008)
  946. *
  947. *****************************************************************************/
  948. /* Slice: offset_y:*/
  949. /* Offset Y */
  950. /* Note: the offset_y is positive and refers to the reference image */
  951. #ifdef MRV_SI_OFFSET_Y
  952. #endif /* MRV_SI_OFFSET_Y */
  953. /*****************************************************************************/
  954. /**
  955. * register: super_imp_color_y: Y component of transparent key color (0x000c)
  956. *
  957. *****************************************************************************/
  958. /* Slice: y_comp:*/
  959. /* Y component of transparent key color */
  960. #ifdef MRV_SI_Y_COMP
  961. #endif /* MRV_SI_Y_COMP */
  962. /*****************************************************************************/
  963. /**
  964. * register: super_imp_color_cb: Cb component of transparent key color (0x0010)
  965. *
  966. *****************************************************************************/
  967. /* Slice: cb_comp:*/
  968. /* Cb component of transparent key color */
  969. #ifdef MRV_SI_CB_COMP
  970. #endif /* MRV_SI_CB_COMP */
  971. /*****************************************************************************/
  972. /**
  973. * register: super_imp_color_cr: Cr component of transparent key color (0x0014)
  974. *
  975. *****************************************************************************/
  976. /* Slice: cr_comp:*/
  977. /* Cr component of transparent key color */
  978. #ifdef MRV_SI_CR_COMP
  979. #endif /* MRV_SI_CR_COMP */
  980. /*****************************************************************************/
  981. /* ISP Registers */
  982. /*****************************************************************************/
  983. /*****************************************************************************/
  984. /**
  985. * register: isp_ctrl: global control register (0x0000)
  986. *
  987. *****************************************************************************/
  988. /* Slice: ISP_DPF_RAW_OUT */
  989. /*! Slice MRV_ISP_DPF_RAW_OUT:*/
  990. /*! 0: DPF RAW OUT is disable */
  991. /*! 1: DPF RAW OUT is enable */
  992. #ifdef ISP_DPF_RAW
  993. #ifdef MRV_ISP_DPF_RAW_OUT
  994. #define MRV_ISP_DPF_RAW_OUT_DISABLE 0 /* 0: DPF raw out is disable */
  995. #define MRV_ISP_DPF_RAW_OUT_ENABLE 1 /* 1: DPF raw out is enable */
  996. #endif
  997. #endif
  998. /* Slice: ISP_CSM_C_RANGE:*/
  999. /* Color Space Matrix chrominance clipping range for ISP output */
  1000. /* 0: CbCr range 64..960 (16..240) according to ITU-R BT.601 standard */
  1001. /* 1: full UV range 0..1023 (0..255)*/
  1002. /* Numbers in brackets are for 8 bit resolution.*/
  1003. #ifdef MRV_ISP_ISP_CSM_C_RANGE
  1004. #define MRV_ISP_ISP_CSM_C_RANGE_BT601 0 /* 0: CbCr range 64..960 (16..240) according to ITU-R BT.601 standard */
  1005. #define MRV_ISP_ISP_CSM_C_RANGE_FULL 1 /* 1: full UV range 0..1023 (0..255) */
  1006. #endif /* MRV_ISP_ISP_CSM_C_RANGE */
  1007. /* Slice: ISP_CSM_Y_RANGE:*/
  1008. /* Color Space Matrix luminance clipping range for ISP output */
  1009. /* 0: Y range 64..940 (16..235) according to ITU-R BT.601 standard */
  1010. /* 1: full Y range 0..1023 (0..255)*/
  1011. /* Numbers in brackets are for 8 bit resolution.*/
  1012. #ifdef MRV_ISP_ISP_CSM_Y_RANGE
  1013. #define MRV_ISP_ISP_CSM_Y_RANGE_BT601 0 /* 0: Y range 64..940 (16..235) according to ITU-R BT.601 standard */
  1014. #define MRV_ISP_ISP_CSM_Y_RANGE_FULL 1 /* 1: full Y range 0..1023 (0..255) */
  1015. #endif /* MRV_ISP_ISP_CSM_Y_RANGE */
  1016. /* Slice: ISP_FLASH_MODE:*/
  1017. /* 0: sensor interface works independently from flash control unit */
  1018. /* 1: one frame is captured when signaled by flash control unit */
  1019. #ifdef MRV_ISP_ISP_FLASH_MODE
  1020. #define MRV_ISP_ISP_FLASH_MODE_INDEP 0 /* 0: sensor interface works independently from flash control unit */
  1021. #define MRV_ISP_ISP_FLASH_MODE_SYNC 1 /* 1: one frame is captured when signaled by flash control unit */
  1022. #endif /* MRV_ISP_ISP_FLASH_MODE */
  1023. /* Slice: ISP_GAMMA_OUT_ENABLE:*/
  1024. /* gamma ON/OFF */
  1025. #ifdef MRV_ISP_ISP_GAMMA_OUT_ENABLE
  1026. #endif /* MRV_ISP_ISP_GAMMA_OUT_ENABLE */
  1027. /* Slice: ISP_GEN_CFG_UPD:*/
  1028. /* generate vsynced config shadow signal at the output, write only */
  1029. #ifdef MRV_ISP_ISP_GEN_CFG_UPD
  1030. #endif /* MRV_ISP_ISP_GEN_CFG_UPD */
  1031. /* Slice: ISP_CFG_UPD:*/
  1032. /* immediate configure internal shadow registers, write only */
  1033. #ifdef MRV_ISP_ISP_CFG_UPD
  1034. #endif /* MRV_ISP_ISP_CFG_UPD */
  1035. /* Slice: ISP_AE_ENABLE:*/
  1036. /* auto exposure ON/OFF */
  1037. #ifdef MRV_ISP_ISP_AE_ENABLE
  1038. #endif /* MRV_ISP_ISP_AE_ENABLE */
  1039. /* Slice: ISP_AWB_ENABLE:*/
  1040. /* auto white balance ON/OFF */
  1041. #ifdef MRV_ISP_ISP_AWB_ENABLE
  1042. #endif /* MRV_ISP_ISP_AWB_ENABLE */
  1043. /* Slice: ISP_GAMMA_IN_ENABLE:*/
  1044. /* Sensor De-gamma ON/OFF */
  1045. #ifdef MRV_ISP_ISP_GAMMA_IN_ENABLE
  1046. #define MRV_ISP_ISP_GAMMA_IN_ENABLE_ON 1U
  1047. #define MRV_ISP_ISP_GAMMA_IN_ENABLE_OFF 0U
  1048. #endif /* MRV_ISP_ISP_GAMMA_IN_ENABLE */
  1049. /* Slice: ISP_INFORM_ENABLE:*/
  1050. /* input block ON/OFF (frame-synced on)*/
  1051. #ifdef MRV_ISP_ISP_INFORM_ENABLE
  1052. #endif /* MRV_ISP_ISP_INFORM_ENABLE */
  1053. /* Slice: ISP_MODE:*/
  1054. /* 000: RAW picture with BT.601 sync (ISP bypass)*/
  1055. /* 001: ITU-R BT.656 (YUV with embedded sync)*/
  1056. /* 010: ITU-R BT.601 (YUV input with H and Vsync signals)*/
  1057. /* 011: Bayer RGB processing with H and Vsync signals */
  1058. /* 100: data mode (ISP bypass, sync signals interpreted as data enable)*/
  1059. /* 101: Bayer RGB processing with BT.656 synchronization */
  1060. /* 110: RAW picture with ITU-R BT.656 synchronization (ISP bypass)*/
  1061. /* 111: reserved */
  1062. /**/
  1063. /* Side effect:*/
  1064. /* If RAW, BT.601, BT.656, or data mode is selected, the clock of the */
  1065. /* ISP SRAMs (ISP line buffer, Lens Shading, Bad Pixel) is switched off.*/
  1066. /* Only in Bayer RGB mode the clock to the SRAMs is enabled. This */
  1067. /* further reduces power consumption.*/
  1068. #ifdef MRV_ISP_ISP_MODE
  1069. #define MRV_ISP_ISP_MODE_RAW 0 /* 000 - RAW picture with BT.601 sync (ISP bypass) */
  1070. #define MRV_ISP_ISP_MODE_656 1 /* 001 - ITU-R BT.656 (YUV with embedded sync) */
  1071. #define MRV_ISP_ISP_MODE_601 2 /* 010 - ITU-R BT.601 (YUV input with H and Vsync signals) */
  1072. #define MRV_ISP_ISP_MODE_RGB 3 /* 011 - Bayer RGB processing with H and Vsync signals */
  1073. #define MRV_ISP_ISP_MODE_DATA 4 /* 100 - data mode (ISP bypass, sync signals interpreted as data enable) */
  1074. #define MRV_ISP_ISP_MODE_RGB656 5 /* 101 - Bayer RGB processing with BT.656 synchronization */
  1075. #define MRV_ISP_ISP_MODE_RAW656 6 /* 110 - RAW picture with ITU-R BT.656 synchronization (ISP bypass) */
  1076. #endif /* MRV_ISP_ISP_MODE */
  1077. /* Slice: ISP_ENABLE:*/
  1078. /* MANUAL ON/OFF (controls output formatter, framesynced)*/
  1079. #ifdef MRV_ISP_ISP_ENABLE
  1080. #endif /* MRV_ISP_ISP_ENABLE */
  1081. /*****************************************************************************/
  1082. /**
  1083. * register: isp_acq_prop: ISP acquisition properties (0x0004)
  1084. *
  1085. *****************************************************************************/
  1086. #ifdef ISP_DVP_PINMAPPING
  1087. /*! Slice: MRV_ISP_DVP_INPUT_PIN_MAPPING */
  1088. /*! Bit Mapping for LSB to MSP for ISPNano.*/
  1089. /*! 3'b000: normal 12-bit external interface */
  1090. /*! 3'b001: mapping low 10 bit to high 10 bits, append 2 zeros as LSBs.*/
  1091. /*! 3'b010: mapping low 8 bit to high 8 bits, append 4 zeros as LSBs.*/
  1092. /*! 3'b011: mapping middle 8 bit to high 8 bits, append 4 zeros as LSBs.*/
  1093. /*! 3'b100..3'b111: rsvd */
  1094. #ifdef MRV_ISP_DVP_INPUT_PIN_MAPPING
  1095. #define MRV_ISP_DVP_INPUT_PIN_MAPPING_12TO12 0
  1096. #define MRV_ISP_DVP_INPUT_PIN_MAPPING_L10TOH10 1
  1097. #define MRV_ISP_DVP_INPUT_PIN_MAPPING_L8TOH8 2
  1098. #define MRV_ISP_DVP_INPUT_PIN_MAPPING_M8TOH8 3
  1099. #endif
  1100. #endif
  1101. /*! Slice: DMA_YUV_SELECTION */
  1102. /*! 0: use align or conversion data for isp_is input */
  1103. /*! 1: use dma yuv read data for isp_is input */
  1104. #ifdef MRV_ISP_DMA_YUV_SELECTION
  1105. #define MRV_ISP_DMA_YUV_SELECTION_ALIGNED_CONV 0
  1106. #define MRV_ISP_DMA_YUV_SELECTION_DMA_YUV 1
  1107. #endif
  1108. /* Slice: LATENCY_FIFO_SELECTION:*/
  1109. /* 0: use input formatter input for latency fifo.*/
  1110. /* 1: use dma rgb read input for latency fifo.*/
  1111. #ifdef MRV_ISP_LATENCY_FIFO_SELECTION
  1112. #define MRV_ISP_LATENCY_FIFO_SELECTION_INPUT_FORMATTER 0
  1113. #define MRV_ISP_LATENCY_FIFO_SELECTION_DMA_READ 1
  1114. #endif /* MRV_ISP_LATENCY_FIFO_SELECTION */
  1115. /* Slice: INPUT_SELECTION:*/
  1116. /* 000: 12Bit external Interface */
  1117. /* 001: 10Bit Interface, append 2 zeroes as LSBs */
  1118. /* 010: 10Bit Interface, append 2 MSBs as LSBs */
  1119. /* 011: 8Bit Interface, append 4 zeroes as LSBs */
  1120. /* 100: 8Bit Interface, append 4 MSBs as LSBs */
  1121. /* 101...111: reserved */
  1122. #ifdef MRV_ISP_INPUT_SELECTION
  1123. #define MRV_ISP_INPUT_SELECTION_12EXT 0 /* 000- 12Bit external Interface */
  1124. #define MRV_ISP_INPUT_SELECTION_10ZERO 1 /* 001- 10Bit Interface, append 2 zeroes as LSBs */
  1125. #define MRV_ISP_INPUT_SELECTION_10MSB 2 /* 010- 10Bit Interface, append 2 MSBs as LSBs */
  1126. #define MRV_ISP_INPUT_SELECTION_8ZERO 3 /* 011- 8Bit Interface, append 4 zeroes as LSBs */
  1127. #define MRV_ISP_INPUT_SELECTION_8MSB 4 /* 100- 8Bit Interface, append 4 MSBs as LSBs */
  1128. #endif /* MRV_ISP_INPUT_SELECTION */
  1129. /* Slice: FIELD_SELECTION:*/
  1130. /* 00: sample all fields (don't care about fields)*/
  1131. /* 01: sample only even fields */
  1132. /* 10: sample only odd fields */
  1133. /* 11: reserved */
  1134. #ifdef MRV_ISP_FIELD_SELECTION
  1135. #define MRV_ISP_FIELD_SELECTION_BOTH 0 /* 00- sample all fields (don't care about fields) */
  1136. #define MRV_ISP_FIELD_SELECTION_EVEN 1 /* 01- sample only even fields */
  1137. #define MRV_ISP_FIELD_SELECTION_ODD 2 /* 10- sample only odd fields */
  1138. #endif /* MRV_ISP_FIELD_SELECTION */
  1139. /* Slice: CCIR_SEQ:*/
  1140. /* 00: YCbYCr */
  1141. /* 01: YCrYCb */
  1142. /* 10: CbYCrY */
  1143. /* 11: CrYCbY */
  1144. #ifdef MRV_ISP_CCIR_SEQ
  1145. #define MRV_ISP_CCIR_SEQ_YCBYCR 0 /* 00 - YCbYCr */
  1146. #define MRV_ISP_CCIR_SEQ_YCRYCB 1 /* 01 - YCrYCb */
  1147. #define MRV_ISP_CCIR_SEQ_CBYCRY 2 /* 10 - CbYCrY */
  1148. #define MRV_ISP_CCIR_SEQ_CRYCBY 3 /* 11 - CrYCbY */
  1149. #endif /* MRV_ISP_CCIR_SEQ */
  1150. /* Slice: CONV_422:*/
  1151. /* 00- co-sited color subsampling Y0Cb0Cr0 - Y1 */
  1152. /* 01- interleaved color subsampling Y0Cb0 - Y1Cr1 (not recommended)*/
  1153. /* 10- non-cosited color subsampling Y0Cb(0+1)/2 - Y1Cr(0+1)/2 */
  1154. /* 11- reserved */
  1155. #ifdef MRV_ISP_CONV_422
  1156. #define MRV_ISP_CONV_422_CO 0 /* 00- co-sited color subsampling Y0Cb0Cr0 - Y1 */
  1157. #define MRV_ISP_CONV_422_INTER 1 /* 01- interleaved color subsampling Y0Cb0 - Y1Cr1 (not recommended) */
  1158. #define MRV_ISP_CONV_422_NONCO 2 /* 10- non-cosited color subsampling Y0Cb(0+1)/2 - Y1Cr(0+1)/2 */
  1159. #endif /* MRV_ISP_CONV_422 */
  1160. /* Slice: BAYER_PAT:*/
  1161. /* color components from sensor, starting with top left position in sampled frame */
  1162. /* (reprogram with ISP_ACQ_H_OFFS, ISP_ACQ_V_OFFS)*/
  1163. /**/
  1164. /* 00: first line: RGRG, second line: GBGB, etc.*/
  1165. /* 01: first line: GRGR, second line: BGBG, etc.*/
  1166. /* 10: first line: GBGB, second line: RGRG, etc.*/
  1167. /* 11: first line: BGBG, second line: GRGR, etc.*/
  1168. /* This configuration applies for the black level area after cropping by the input formatter.*/
  1169. #ifdef MRV_ISP_BAYER_PAT
  1170. #define MRV_ISP_BAYER_PAT_RG 0 /* 00 - first line: RGRG, second line: GBGB, etc. */
  1171. #define MRV_ISP_BAYER_PAT_GR 1 /* 01 - first line: GRGR, second line: BGBG, etc. */
  1172. #define MRV_ISP_BAYER_PAT_GB 2 /* 10 - first line: GBGB, second line: RGRG, etc. */
  1173. #define MRV_ISP_BAYER_PAT_BG 3 /* 11 - first line: BGBG, second line: GRGR, etc. */
  1174. #endif /* MRV_ISP_BAYER_PAT */
  1175. /* Slice: VSYNC_POL:*/
  1176. /* vertical sync polarity */
  1177. /* 0: high active */
  1178. /* 1: low active */
  1179. #ifdef MRV_ISP_VSYNC_POL
  1180. #endif /* MRV_ISP_VSYNC_POL */
  1181. /* Slice: HSYNC_POL:*/
  1182. /* horizontal sync polarity */
  1183. /* 0: high active */
  1184. /* 1: low active */
  1185. #ifdef MRV_ISP_HSYNC_POL
  1186. #endif /* MRV_ISP_HSYNC_POL */
  1187. /* Slice: SAMPLE_EDGE:*/
  1188. /* 0: negative edge sampling */
  1189. /* 1: positive edge sampling */
  1190. #ifdef MRV_ISP_SAMPLE_EDGE
  1191. #endif /* MRV_ISP_SAMPLE_EDGE */
  1192. /*****************************************************************************/
  1193. /**
  1194. * register: isp_acq_h_offs: horizontal input offset (0x0008)
  1195. *
  1196. *****************************************************************************/
  1197. /* Slice: ACQ_H_OFFS:*/
  1198. /* horizontal sample offset in 8-bit samples (yuv: 4 samples=2pix)*/
  1199. #ifdef MRV_ISP_ACQ_H_OFFS
  1200. #endif /* MRV_ISP_ACQ_H_OFFS */
  1201. /*****************************************************************************/
  1202. /**
  1203. * register: isp_acq_v_offs: vertical input offset (0x000c)
  1204. *
  1205. *****************************************************************************/
  1206. /* Slice: ACQ_V_OFFS:*/
  1207. /* vertical sample offset in lines */
  1208. #ifdef MRV_ISP_ACQ_V_OFFS
  1209. #endif /* MRV_ISP_ACQ_V_OFFS */
  1210. /*****************************************************************************/
  1211. /**
  1212. * register: isp_acq_h_size: horizontal input size (0x0010)
  1213. *
  1214. *****************************************************************************/
  1215. /* Slice: ACQ_H_SIZE:*/
  1216. /* horizontal sample size in 12-bit samples */
  1217. /* YUV input: 2 samples = 1 pixel, else 1 sample = 1 pixel; So in YUV mode ACQ_H_SIZE must be twice as large as horizontal image size */
  1218. /* horizontal image size must always be even exept in raw picture mode; if an odd size is programmed the value will be truncated to even size */
  1219. #ifdef MRV_ISP_ACQ_H_SIZE
  1220. #endif /* MRV_ISP_ACQ_H_SIZE */
  1221. /*****************************************************************************/
  1222. /**
  1223. * register: isp_acq_v_size: vertical input size (0x0014)
  1224. *
  1225. *****************************************************************************/
  1226. /* Slice: ACQ_V_SIZE:*/
  1227. /* vertical sample size in lines */
  1228. #ifdef MRV_ISP_ACQ_V_SIZE
  1229. #endif /* MRV_ISP_ACQ_V_SIZE */
  1230. /*****************************************************************************/
  1231. /**
  1232. * register: isp_acq_nr_frames: Number of frames to be captured (0x0018)
  1233. *
  1234. *****************************************************************************/
  1235. /* Slice: ACQ_NR_FRAMES:*/
  1236. /* number of input frames to be sampled (0 = continuous)*/
  1237. #ifdef MRV_ISP_ACQ_NR_FRAMES
  1238. #endif /* MRV_ISP_ACQ_NR_FRAMES */
  1239. /*****************************************************************************/
  1240. /**
  1241. * register: isp_gamma_dx_lo: De-Gamma Curve definition lower x increments
  1242. * (sampling points) (0x001c)
  1243. *
  1244. *****************************************************************************/
  1245. /* Slice: GAMMA_DX_8:*/
  1246. /* gamma curve sample point definition x-axis (input)*/
  1247. #ifdef MRV_ISP_GAMMA_DX_8
  1248. #endif /* MRV_ISP_GAMMA_DX_8 */
  1249. /* Slice: GAMMA_DX_7:*/
  1250. /* gamma curve sample point definition x-axis (input)*/
  1251. #ifdef MRV_ISP_GAMMA_DX_7
  1252. #endif /* MRV_ISP_GAMMA_DX_7 */
  1253. /* Slice: GAMMA_DX_6:*/
  1254. /* gamma curve sample point definition x-axis (input)*/
  1255. #ifdef MRV_ISP_GAMMA_DX_6
  1256. #endif /* MRV_ISP_GAMMA_DX_6 */
  1257. /* Slice: GAMMA_DX_5:*/
  1258. /* gamma curve sample point definition x-axis (input)*/
  1259. #ifdef MRV_ISP_GAMMA_DX_5
  1260. #endif /* MRV_ISP_GAMMA_DX_5 */
  1261. /* Slice: GAMMA_DX_4:*/
  1262. /* gamma curve sample point definition x-axis (input)*/
  1263. #ifdef MRV_ISP_GAMMA_DX_4
  1264. #endif /* MRV_ISP_GAMMA_DX_4 */
  1265. /* Slice: GAMMA_DX_3:*/
  1266. /* gamma curve sample point definition x-axis (input)*/
  1267. #ifdef MRV_ISP_GAMMA_DX_3
  1268. #endif /* MRV_ISP_GAMMA_DX_3 */
  1269. /* Slice: GAMMA_DX_2:*/
  1270. /* gamma curve sample point definition x-axis (input)*/
  1271. #ifdef MRV_ISP_GAMMA_DX_2
  1272. #endif /* MRV_ISP_GAMMA_DX_2 */
  1273. /* Slice: GAMMA_DX_1:*/
  1274. /* gamma curve sample point definition x-axis (input)*/
  1275. #ifdef MRV_ISP_GAMMA_DX_1
  1276. #endif /* MRV_ISP_GAMMA_DX_1 */
  1277. /*****************************************************************************/
  1278. /**
  1279. * register: isp_gamma_dx_hi: De-Gamma Curve definition higher x increments
  1280. * (sampling points) (0x0020)
  1281. *
  1282. *****************************************************************************/
  1283. /* Slice: GAMMA_DX_16:*/
  1284. /* gamma curve sample point definition x-axis (input)*/
  1285. #ifdef MRV_ISP_GAMMA_DX_16
  1286. #endif /* MRV_ISP_GAMMA_DX_16 */
  1287. /* Slice: GAMMA_DX_15:*/
  1288. /* gamma curve sample point definition x-axis (input)*/
  1289. #ifdef MRV_ISP_GAMMA_DX_15
  1290. #endif /* MRV_ISP_GAMMA_DX_15 */
  1291. /* Slice: GAMMA_DX_14:*/
  1292. /* gamma curve sample point definition x-axis (input)*/
  1293. #ifdef MRV_ISP_GAMMA_DX_14
  1294. #endif /* MRV_ISP_GAMMA_DX_14 */
  1295. /* Slice: GAMMA_DX_13:*/
  1296. /* gamma curve sample point definition x-axis (input)*/
  1297. #ifdef MRV_ISP_GAMMA_DX_13
  1298. #endif /* MRV_ISP_GAMMA_DX_13 */
  1299. /* Slice: GAMMA_DX_12:*/
  1300. /* gamma curve sample point definition x-axis (input)*/
  1301. #ifdef MRV_ISP_GAMMA_DX_12
  1302. #endif /* MRV_ISP_GAMMA_DX_12 */
  1303. /* Slice: GAMMA_DX_11:*/
  1304. /* gamma curve sample point definition x-axis (input)*/
  1305. #ifdef MRV_ISP_GAMMA_DX_11
  1306. #endif /* MRV_ISP_GAMMA_DX_11 */
  1307. /* Slice: GAMMA_DX_10:*/
  1308. /* gamma curve sample point definition x-axis (input)*/
  1309. #ifdef MRV_ISP_GAMMA_DX_10
  1310. #endif /* MRV_ISP_GAMMA_DX_10 */
  1311. /* Slice: GAMMA_DX_9:*/
  1312. /* gamma curve sample point definition x-axis (input)*/
  1313. #ifdef MRV_ISP_GAMMA_DX_9
  1314. #endif /* MRV_ISP_GAMMA_DX_9 */
  1315. /*****************************************************************************/
  1316. /**
  1317. * register array: isp_gamma_r_y: De-Gamma Curve definition y red (0x0024+n (n=0..16))
  1318. *
  1319. *****************************************************************************/
  1320. /* Slice: GAMMA_R_Y:*/
  1321. /* gamma curve point definition y-axis (output) for red */
  1322. /* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that dy is 12-bit signed !)*/
  1323. #ifdef MRV_ISP_GAMMA_R_Y
  1324. #endif /* MRV_ISP_GAMMA_R_Y */
  1325. /*****************************************************************************/
  1326. /**
  1327. * register array: isp_gamma_g_y: De-Gamma Curve definition y green (0x0068+n (n=0..16))
  1328. *
  1329. *****************************************************************************/
  1330. /* Slice: GAMMA_G_Y:*/
  1331. /* gamma curve point definition y-axis (output) for green */
  1332. /* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that dy is 12-bit signed !)*/
  1333. #ifdef MRV_ISP_GAMMA_G_Y
  1334. #endif /* MRV_ISP_GAMMA_G_Y */
  1335. /*****************************************************************************/
  1336. /**
  1337. * register array: isp_gamma_b_y: De-Gamma Curve definition y blue (0x00AC+n (n=0..16))
  1338. *
  1339. *****************************************************************************/
  1340. /* Slice: GAMMA_B_Y:*/
  1341. /* gamma curve point definition y-axis (output) for blue */
  1342. /* RESTRICTION: each Y must be in the +2047/-2048 range compared to its predecessor (so that dy is 12-bit signed !)*/
  1343. #ifdef MRV_ISP_GAMMA_B_Y
  1344. #endif /* MRV_ISP_GAMMA_B_Y */
  1345. /*****************************************************************************/
  1346. /* ISP Auto White Balance Registers */
  1347. /*****************************************************************************/
  1348. /*****************************************************************************/
  1349. /**
  1350. * register: isp_awb_prop: Auto white balance properties (0x0110)
  1351. *
  1352. *****************************************************************************/
  1353. /* Slice: AWB_MEAS_MODE:*/
  1354. /* 1: RGB based measurement mode */
  1355. /* 0: near white discrimination mode using YCbCr color space */
  1356. #ifdef MRV_ISP_AWB_MEAS_MODE
  1357. #define MRV_ISP_AWB_MEAS_MODE_RGB 1U /* 1: RGB based measurement mode */
  1358. #define MRV_ISP_AWB_MEAS_MODE_YCBCR 0U /* 0: near white discrimination mode using YCbCr color space */
  1359. #endif /* MRV_ISP_AWB_MEAS_MODE */
  1360. /* Slice: AWB_MAX_EN:*/
  1361. /* 1: enable Y_MAX compare */
  1362. /* 0: disable Y_MAX compare */
  1363. /* ignored if RGB measurement mode is enabled */
  1364. #ifdef MRV_ISP_AWB_MAX_EN
  1365. #define MRV_ISP_AWB_MAX_EN_ENABLE 1U /* 1: enable Y_MAX compare */
  1366. #define MRV_ISP_AWB_MAX_EN_DISABLE 0U /* 0: disable Y_MAX compare */
  1367. #endif /* MRV_ISP_AWB_MAX_EN */
  1368. /* Slice: AWB_MODE:*/
  1369. /* AWB_MODE(1:0):*/
  1370. /* 11: reserved */
  1371. /* 10: white balance measurement of YCbCr means */
  1372. /* 01: reserved */
  1373. /* 00: manual white balance (gain adjust possible), no measurement */
  1374. #ifdef MRV_ISP_AWB_MODE
  1375. #define MRV_ISP_AWB_MODE_MEAS 2U /* 10: white balance measurement of YCbCr or RGB means (dependent on MRV_ISP_AWB_MEAS_MODE) */
  1376. #define MRV_ISP_AWB_MODE_NOMEAS 0U /* 00: manual white balance (gain adjust possible), no measurement */
  1377. #endif /* MRV_ISP_AWB_MODE */
  1378. /*****************************************************************************/
  1379. /**
  1380. * register: isp_awb_h_offs: Auto white balance horizontal offset of measure
  1381. * window (0x0114)
  1382. *
  1383. *****************************************************************************/
  1384. /* Slice: AWB_H_OFFS:*/
  1385. /* horizontal window offset in pixel */
  1386. #ifdef MRV_ISP_AWB_H_OFFS
  1387. #define MRV_ISP_AWB_H_OFFS_MIN 0U
  1388. #define MRV_ISP_AWB_H_OFFS_MAX (MRV_ISP_AWB_H_OFFS_MASK >> MRV_ISP_AWB_H_OFFS_SHIFT)
  1389. #endif /* MRV_ISP_AWB_H_OFFS */
  1390. /*****************************************************************************/
  1391. /**
  1392. * register: isp_awb_v_offs: Auto white balance vertical offset of measure
  1393. * window (0x0118)
  1394. *
  1395. *****************************************************************************/
  1396. /* Slice: AWB_V_OFFS:*/
  1397. /* vertical window offset in lines */
  1398. #ifdef MRV_ISP_AWB_V_OFFS
  1399. #define MRV_ISP_AWB_V_OFFS_MIN 0U
  1400. #define MRV_ISP_AWB_V_OFFS_MAX (MRV_ISP_AWB_V_OFFS_MASK >> MRV_ISP_AWB_V_OFFS_SHIFT)
  1401. #endif /* MRV_ISP_AWB_V_OFFS */
  1402. /*****************************************************************************/
  1403. /**
  1404. * register: isp_awb_h_size: Auto white balance horizontal window size (0x011c)
  1405. *
  1406. *****************************************************************************/
  1407. /* Slice: AWB_H_SIZE:*/
  1408. /* horizontal measurement window size in pixel */
  1409. #ifdef MRV_ISP_AWB_H_SIZE
  1410. #define MRV_ISP_AWB_H_SIZE_MIN 0U
  1411. #define MRV_ISP_AWB_H_SIZE_MAX (MRV_ISP_AWB_H_SIZE_MASK >> MRV_ISP_AWB_H_SIZE_SHIFT)
  1412. #endif /* MRV_ISP_AWB_H_SIZE */
  1413. /*****************************************************************************/
  1414. /**
  1415. * register: isp_awb_v_size: Auto white balance vertical window size (0x0120)
  1416. *
  1417. *****************************************************************************/
  1418. /* Slice: AWB_V_SIZE:*/
  1419. /* vertical measurement window size in lines */
  1420. #ifdef MRV_ISP_AWB_V_SIZE
  1421. #define MRV_ISP_AWB_V_SIZE_MIN 0U
  1422. #define MRV_ISP_AWB_V_SIZE_MAX (MRV_ISP_AWB_V_SIZE_MASK >> MRV_ISP_AWB_V_SIZE_SHIFT)
  1423. #endif /* MRV_ISP_AWB_V_SIZE */
  1424. /*****************************************************************************/
  1425. /**
  1426. * register: isp_awb_frames: Auto white balance mean value over multiple frames (0x0124)
  1427. *
  1428. *****************************************************************************/
  1429. /* Slice: AWB_FRAMES:*/
  1430. /* number of frames-1 used for mean value calculation (value of 0 means 1 frame, value of 7 means 8 frames)*/
  1431. #ifdef MRV_ISP_AWB_FRAMES
  1432. #endif /* MRV_ISP_AWB_FRAMES */
  1433. /*****************************************************************************/
  1434. /**
  1435. * register: isp_awb_ref: Auto white balance reference Cb/Cr values (0x0128)
  1436. * or maximum red/blue values
  1437. *
  1438. *****************************************************************************/
  1439. /* Slice: AWB_REF_CR__MAX_R:*/
  1440. /* - reference Cr value for AWB regulation, target for AWB */
  1441. /* - maximum red value, if RGB measurement mode is selected */
  1442. #ifdef MRV_ISP_AWB_REF_CR__MAX_R
  1443. #endif /* MRV_ISP_AWB_REF_CR__MAX_R */
  1444. /* Slice: AWB_REF_CB__MAX_B:*/
  1445. /* - reference Cb value for AWB regulation, target for AWB */
  1446. /* - maximum blue value, if RGB measurement mode is selected */
  1447. #ifdef MRV_ISP_AWB_REF_CB__MAX_B
  1448. #endif /* MRV_ISP_AWB_REF_CB__MAX_B */
  1449. /*****************************************************************************/
  1450. /**
  1451. * register: isp_awb_thresh: Auto white balance threshold values (0x012c)
  1452. *
  1453. *****************************************************************************/
  1454. /* Slice: AWB_MAX_Y:*/
  1455. /* - Luminance maximum value, only consider pixels with luminance smaller than threshold for the WB measurement (must be enabled by AWB_MODE(2)),*/
  1456. /* - ignored if RGB measurement mode is enabled */
  1457. #ifdef MRV_ISP_AWB_MAX_Y
  1458. #endif /* MRV_ISP_AWB_MAX_Y */
  1459. /* Slice: AWB_MIN_Y__MAX_G:*/
  1460. /* - Luminance minimum value, only consider pixels with luminance greater than threshold for the WB measurement */
  1461. /* - maximum green value, if RGB measurement mode is selected */
  1462. #ifdef MRV_ISP_AWB_MIN_Y__MAX_G
  1463. #endif /* MRV_ISP_AWB_MIN_Y__MAX_G */
  1464. /* Slice: AWB_MAX_CSUM:*/
  1465. /* - Chrominance sum maximum value, only consider pixels with Cb+Cr smaller than threshold for WB measurements */
  1466. /* - ignored if RGB measurement mode is enabled */
  1467. #ifdef MRV_ISP_AWB_MAX_CSUM
  1468. #endif /* MRV_ISP_AWB_MAX_CSUM */
  1469. /* Slice: AWB_MIN_C:*/
  1470. /* - Chrominance minimum value, only consider pixels with Cb/Cr each greater than threshold value for WB measurements */
  1471. /* - ignored if RGB measurement mode is enabled */
  1472. #ifdef MRV_ISP_AWB_MIN_C
  1473. #endif /* MRV_ISP_AWB_MIN_C */
  1474. /*****************************************************************************/
  1475. /**
  1476. * register: isp_awb_gain_g: Auto white balance gain green (0x0138)
  1477. *
  1478. *****************************************************************************/
  1479. /* Slice: AWB_GAIN_GR:*/
  1480. /* gain value for green component in red line 100h = 1 */
  1481. #ifdef MRV_ISP_AWB_GAIN_GR
  1482. #define MRV_ISP_AWB_GAIN_GR_DEFAULT (0x100U)
  1483. #define MRV_ISP_AWB_GAIN_GR_MAX (MRV_ISP_AWB_GAIN_GR_MASK >> MRV_ISP_AWB_GAIN_GR_SHIFT)
  1484. #endif /* MRV_ISP_AWB_GAIN_GR */
  1485. /* Slice: AWB_GAIN_GB:*/
  1486. /* gain value for green component in blue line 100h = 1 */
  1487. #ifdef MRV_ISP_AWB_GAIN_GB
  1488. #define MRV_ISP_AWB_GAIN_GB_DEFAULT (0x100U)
  1489. #define MRV_ISP_AWB_GAIN_GB_MAX (MRV_ISP_AWB_GAIN_GB_MASK >> MRV_ISP_AWB_GAIN_GB_SHIFT)
  1490. #endif /* MRV_ISP_AWB_GAIN_GB */
  1491. /*****************************************************************************/
  1492. /**
  1493. * register: isp_awb_gain_rb: Auto white balance gain red and blue (0x013c)
  1494. *
  1495. *****************************************************************************/
  1496. /* Slice: AWB_GAIN_R:*/
  1497. /* gain value for red component 100h = 1 */
  1498. #ifdef MRV_ISP_AWB_GAIN_R
  1499. #define MRV_ISP_AWB_GAIN_R_DEFAULT (0x100U)
  1500. #define MRV_ISP_AWB_GAIN_R_MAX (MRV_ISP_AWB_GAIN_R_MASK >> MRV_ISP_AWB_GAIN_R_SHIFT)
  1501. #endif /* MRV_ISP_AWB_GAIN_R */
  1502. /* Slice: AWB_GAIN_B:*/
  1503. /* gain value for blue component 100h = 1 */
  1504. #ifdef MRV_ISP_AWB_GAIN_B
  1505. #define MRV_ISP_AWB_GAIN_B_DEFAULT (0x100U)
  1506. #define MRV_ISP_AWB_GAIN_B_MAX (MRV_ISP_AWB_GAIN_B_MASK >> MRV_ISP_AWB_GAIN_B_SHIFT)
  1507. #endif /* MRV_ISP_AWB_GAIN_B */
  1508. /*****************************************************************************/
  1509. /**
  1510. * register: isp_awb_white_cnt: Auto white balance white pixel count (0x0140)
  1511. *
  1512. *****************************************************************************/
  1513. /* Slice: AWB_WHITE_CNT:*/
  1514. /* White pixel count, number of "white pixels" found during last measurement, i.e. pixels included in mean value calculation */
  1515. #ifdef MRV_ISP_AWB_WHITE_CNT
  1516. #endif /* MRV_ISP_AWB_WHITE_CNT */
  1517. /*****************************************************************************/
  1518. /**
  1519. * register: isp_awb_mean: Auto white balance measured mean value (0x0144)
  1520. *
  1521. *****************************************************************************/
  1522. /* Slice: AWB_MEAN_Y_G:*/
  1523. /* - mean value of Y within window and frames */
  1524. /* - mean value of green within window and frames if RGB measurement is enabled */
  1525. #ifdef MRV_ISP_AWB_MEAN_Y__G
  1526. #endif /* MRV_ISP_AWB_MEAN_Y__G */
  1527. /* Slice: AWB_MEAN_CB_B:*/
  1528. /* - mean value of Cb within window and frames */
  1529. /* - mean value of blue within window and frames if RGB measurement is enabled */
  1530. #ifdef MRV_ISP_AWB_MEAN_CB__B
  1531. #endif /* MRV_ISP_AWB_MEAN_CB__B */
  1532. /* Slice: AWB_MEAN_CR_R:*/
  1533. /* - mean value of Cr within window and frames */
  1534. /* - mean value of red within window and frames if RGB measurement is enabled */
  1535. #ifdef MRV_ISP_AWB_MEAN_CR__R
  1536. #endif /* MRV_ISP_AWB_MEAN_CR__R */
  1537. /*****************************************************************************/
  1538. /**
  1539. * register: isp_cc_coeff_0: Color conversion coefficient 0 (0x0170)
  1540. *
  1541. *****************************************************************************/
  1542. /* Slice: cc_coeff_0:*/
  1543. /* coefficient 0 for color space conversion */
  1544. #ifdef MRV_ISP_CC_COEFF_0
  1545. #endif /* MRV_ISP_CC_COEFF_0 */
  1546. /*****************************************************************************/
  1547. /**
  1548. * register: isp_cc_coeff_1: Color conversion coefficient 1 (0x0174)
  1549. *
  1550. *****************************************************************************/
  1551. /* Slice: cc_coeff_1:*/
  1552. /* coefficient 1 for color space conversion */
  1553. #ifdef MRV_ISP_CC_COEFF_1
  1554. #endif /* MRV_ISP_CC_COEFF_1 */
  1555. /*****************************************************************************/
  1556. /**
  1557. * register: isp_cc_coeff_2: Color conversion coefficient 2 (0x0178)
  1558. *
  1559. *****************************************************************************/
  1560. /* Slice: cc_coeff_2:*/
  1561. /* coefficient 2 for color space conversion */
  1562. #ifdef MRV_ISP_CC_COEFF_2
  1563. #endif /* MRV_ISP_CC_COEFF_2 */
  1564. /*****************************************************************************/
  1565. /**
  1566. * register: isp_cc_coeff_3: Color conversion coefficient 3 (0x017c)
  1567. *
  1568. *****************************************************************************/
  1569. /* Slice: cc_coeff_3:*/
  1570. /* coefficient 3 for color space conversion */
  1571. #ifdef MRV_ISP_CC_COEFF_3
  1572. #endif /* MRV_ISP_CC_COEFF_3 */
  1573. /*****************************************************************************/
  1574. /**
  1575. * register: isp_cc_coeff_4: Color conversion coefficient 4 (0x0180)
  1576. *
  1577. *****************************************************************************/
  1578. /* Slice: cc_coeff_4:*/
  1579. /* coefficient 4 for color space conversion */
  1580. #ifdef MRV_ISP_CC_COEFF_4
  1581. #endif /* MRV_ISP_CC_COEFF_4 */
  1582. /*****************************************************************************/
  1583. /**
  1584. * register: isp_cc_coeff_5: Color conversion coefficient 5 (0x0184)
  1585. *
  1586. *****************************************************************************/
  1587. /* Slice: cc_coeff_5:*/
  1588. /* coefficient 5 for color space conversion */
  1589. #ifdef MRV_ISP_CC_COEFF_5
  1590. #endif /* MRV_ISP_CC_COEFF_5 */
  1591. /*****************************************************************************/
  1592. /**
  1593. * register: isp_cc_coeff_6: Color conversion coefficient 6 (0x0188)
  1594. *
  1595. *****************************************************************************/
  1596. /* Slice: cc_coeff_6:*/
  1597. /* coefficient 6 for color space conversion */
  1598. #ifdef MRV_ISP_CC_COEFF_6
  1599. #endif /* MRV_ISP_CC_COEFF_6 */
  1600. /*****************************************************************************/
  1601. /**
  1602. * register: isp_cc_coeff_7: Color conversion coefficient 7 (0x018c)
  1603. *
  1604. *****************************************************************************/
  1605. /* Slice: cc_coeff_7:*/
  1606. /* coefficient 7 for color space conversion */
  1607. #ifdef MRV_ISP_CC_COEFF_7
  1608. #endif /* MRV_ISP_CC_COEFF_7 */
  1609. /*****************************************************************************/
  1610. /**
  1611. * register: isp_cc_coeff_8: Color conversion coefficient 8 (0x0190)
  1612. *
  1613. *****************************************************************************/
  1614. /* Slice: cc_coeff_8:*/
  1615. /* coefficient 8 for color space conversion */
  1616. #ifdef MRV_ISP_CC_COEFF_8
  1617. #endif /* MRV_ISP_CC_COEFF_8 */
  1618. /*****************************************************************************/
  1619. /**
  1620. * register: isp_out_h_offs: Horizontal offset of output window (0x0194)
  1621. *
  1622. *****************************************************************************/
  1623. /* Slice: ISP_OUT_H_OFFS:*/
  1624. /* vertical pic offset in lines */
  1625. #ifdef MRV_ISP_ISP_OUT_H_OFFS
  1626. #endif /* MRV_ISP_ISP_OUT_H_OFFS */
  1627. /*****************************************************************************/
  1628. /**
  1629. * register: isp_out_v_offs: Vertical offset of output window (0x0198)
  1630. *
  1631. *****************************************************************************/
  1632. /* Slice: ISP_OUT_V_OFFS:*/
  1633. /* vertical pic offset in lines */
  1634. #ifdef MRV_ISP_ISP_OUT_V_OFFS
  1635. #endif /* MRV_ISP_ISP_OUT_V_OFFS */
  1636. /*****************************************************************************/
  1637. /**
  1638. * register: isp_out_h_size: Output horizontal picture size (0x019c)
  1639. *
  1640. *****************************************************************************/
  1641. /* Slice: ISP_OUT_H_SIZE:*/
  1642. /* horizontal picture size in pixel */
  1643. /* if ISP_MODE is set to */
  1644. /* 001: (ITU-R BT.656 YUV),*/
  1645. /* 010: (ITU-R BT.601 YUV),*/
  1646. /* 011: (ITU-R BT.601 Bayer RGB),*/
  1647. /* 101: (ITU-R BT.656 Bayer RGB)*/
  1648. /* only even numbers are accepted, because complete quadruples of YUYV(YCbYCr)*/
  1649. /* are needed for the 422 output. (if an odd size is programmed the value will */
  1650. /* be truncated to an even size)*/
  1651. #ifdef MRV_ISP_ISP_OUT_H_SIZE
  1652. #define MRV_ISP_ISP_OUT_H_SIZE_IS_EVEN(x) (!(x & 0x01U)) /* check is even value */
  1653. #define MRV_ISP_ISP_OUT_H_SIZE_IS_ODD(x) (x & 0x01U) /* check is odd value */
  1654. #endif /* MRV_ISP_ISP_OUT_H_SIZE */
  1655. /*****************************************************************************/
  1656. /**
  1657. * register: isp_out_v_size: Output vertical picture size (0x01a0)
  1658. *
  1659. *****************************************************************************/
  1660. /* Slice: ISP_OUT_V_SIZE:*/
  1661. /* vertical pic size in lines */
  1662. #ifdef MRV_ISP_ISP_OUT_V_SIZE
  1663. #endif /* MRV_ISP_ISP_OUT_V_SIZE */
  1664. /*****************************************************************************/
  1665. /**
  1666. * register: isp_demosaic: Demosaic parameters (0x000001a4)
  1667. *
  1668. *****************************************************************************/
  1669. /* Slice: DEMOSAIC_BYPASS:*/
  1670. /* 0: normal operation for RGB Bayer Pattern input */
  1671. /* 1: demosaicing bypass for Black&White input data */
  1672. #ifdef MRV_ISP_DEMOSAIC_BYPASS
  1673. #define MRV_ISP_DEMOSAIC_MODE_STD 0 /* "0": standard */
  1674. #define MRV_ISP_DEMOSAIC_MODE_ENH 1 /* "1": enhanced mode */
  1675. #endif /* MRV_ISP_DEMOSAIC_BYPASS */
  1676. /* Slice: DEMOSAIC_TH:*/
  1677. /* Threshold for Bayer demosaicing texture detection. This value shifted left */
  1678. /* 4bit is compared with the difference of the vertical and horizontal 12Bit */
  1679. /* wide texture indicators, to decide if the vertical or horizontal texture */
  1680. /* flag must be set.*/
  1681. /* 0xFF: no texture detection */
  1682. /* 0x00: maximum edge sensitivity */
  1683. #ifdef MRV_ISP_DEMOSAIC_TH
  1684. #define MRV_ISP_DEMOSAIC_TH_MAX_TEXTURE_DETECTION 0xFFU /* 0xFF: no texture detection */
  1685. #define MRV_ISP_DEMOSAIC_TH_MAX_EDGE_SENSITIVITY 0x00U /* 0x00: maximum edge sensitivity */
  1686. #endif /* MRV_ISP_DEMOSAIC_TH */
  1687. /*****************************************************************************/
  1688. /**
  1689. * register: isp_flags_shd: Flags (current status) of certain signals and
  1690. * Shadow regs for enable signals (0x000001a8)
  1691. *
  1692. *****************************************************************************/
  1693. /* Slice: S_HSYNC:*/
  1694. /* state of ISP input port s_hsync, for test purposes */
  1695. #ifdef MRV_ISP_S_HSYNC
  1696. #endif /* MRV_ISP_S_HSYNC */
  1697. /* Slice: S_VSYNC:*/
  1698. /* state of ISP input port s_vsync, for test purposes */
  1699. #ifdef MRV_ISP_S_VSYNC
  1700. #endif /* MRV_ISP_S_VSYNC */
  1701. /* Slice: S_DATA:*/
  1702. /* state of ISP input port s_data, for test purposes */
  1703. #ifdef MRV_ISP_S_DATA
  1704. #endif /* MRV_ISP_S_DATA */
  1705. /* Slice: INFORM_FIELD:*/
  1706. /* current field information */
  1707. /* 0: odd */
  1708. /* 1: even */
  1709. #ifdef MRV_ISP_INFORM_FIELD
  1710. #define MRV_ISP_INFORM_FIELD_ODD 0 /* 0: odd field is sampled */
  1711. #define MRV_ISP_INFORM_FIELD_EVEN 1 /* 1: even field is sampled */
  1712. #endif /* MRV_ISP_INFORM_FIELD */
  1713. /* Slice: INFORM_EN_SHD:*/
  1714. /* Input formatter enable shadow register */
  1715. #ifdef MRV_ISP_INFORM_EN_SHD
  1716. #endif /* MRV_ISP_INFORM_EN_SHD */
  1717. /* Slice: ISP_ENABLE_SHD:*/
  1718. /* ISP enable shadow register */
  1719. /* shows, if ISP currently outputs data (1) or not (0)*/
  1720. #ifdef MRV_ISP_ISP_ENABLE_SHD
  1721. #endif /* MRV_ISP_ISP_ENABLE_SHD */
  1722. /*****************************************************************************/
  1723. /**
  1724. * register: isp_out_h_offs_shd: current horizontal offset of output window
  1725. * (shadow register) (0x000001ac)
  1726. *
  1727. *****************************************************************************/
  1728. /* Slice: ISP_OUT_H_OFFS_SHD:*/
  1729. /* current vertical pic offset in lines */
  1730. #ifdef MRV_ISP_ISP_OUT_H_OFFS_SHD
  1731. #endif /* MRV_ISP_ISP_OUT_H_OFFS_SHD */
  1732. /*****************************************************************************/
  1733. /**
  1734. * register: isp_out_v_offs_shd: current vertical offset of output window
  1735. * (shadow register) (0x000001b0)
  1736. *
  1737. *****************************************************************************/
  1738. /* Slice: ISP_OUT_V_OFFS_SHD:*/
  1739. /* current vertical pic offset in lines */
  1740. #ifdef MRV_ISP_ISP_OUT_V_OFFS_SHD
  1741. #endif /* MRV_ISP_ISP_OUT_V_OFFS_SHD */
  1742. /*****************************************************************************/
  1743. /**
  1744. * register: isp_out_h_size_shd: current output horizontal picture size
  1745. * (shadow register) (0x000001b4)
  1746. *
  1747. *****************************************************************************/
  1748. /* Slice: ISP_OUT_H_SIZE_SHD:*/
  1749. /* current horizontal pic size in pixel */
  1750. #ifdef MRV_ISP_ISP_OUT_H_SIZE_SHD
  1751. #endif /* MRV_ISP_ISP_OUT_H_SIZE_SHD */
  1752. /*****************************************************************************/
  1753. /**
  1754. * register: isp_out_v_size_shd: current output vertical picture size
  1755. * (shadow register) (0x000001b8)
  1756. *
  1757. *****************************************************************************/
  1758. /* Slice: ISP_OUT_V_SIZE_SHD:*/
  1759. /* vertical pic size in lines */
  1760. #ifdef MRV_ISP_ISP_OUT_V_SIZE_SHD
  1761. #endif /* MRV_ISP_ISP_OUT_V_SIZE_SHD */
  1762. /*****************************************************************************/
  1763. /**
  1764. * register: isp_imsc: Interrupt mask (0x000001bc)
  1765. *
  1766. *****************************************************************************/
  1767. /*! Slice: IMSC_VSM_END:*/
  1768. /*! enable interrupt (1) or mask out (0)*/
  1769. #ifndef MRV_ISP_IMSC_VSM_END
  1770. #define MRV_ISP_IMSC_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1771. #endif /* !MRV_ISP_IMSC_VSM_END */
  1772. /* Slice: IMSC_EXP_END:*/
  1773. /* enable interrupt (1) or mask out (0)*/
  1774. #ifndef MRV_ISP_IMSC_EXP_END
  1775. #define MRV_ISP_IMSC_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1776. #endif /* !MRV_ISP_IMSC_EXP_END */
  1777. /* Slice: IMSC_FLASH_CAP:*/
  1778. /* enable interrupt (1) or mask out (0)*/
  1779. #ifndef MRV_ISP_IMSC_FLASH_CAP
  1780. #define MRV_ISP_IMSC_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1781. #endif /* !MRV_ISP_IMSC_FLASH_CAP */
  1782. /* Slice: IMSC_BP_DET:*/
  1783. /* enable interrupt (1) or mask out (0)*/
  1784. #ifndef MRV_ISP_IMSC_BP_DET
  1785. #define MRV_ISP_IMSC_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1786. #endif /* !MRV_ISP_IMSC_BP_DET */
  1787. /* Slice: IMSC_HIST_MEASURE_RDY:*/
  1788. /* enable interrupt (1) or mask out (0)*/
  1789. #ifndef MRV_ISP_IMSC_HIST_MEASURE_RDY
  1790. #define MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1791. #endif /* !MRV_ISP_IMSC_HIST_MEASURE_RDY */
  1792. /* Slice: IMSC_AFM_FIN:*/
  1793. /* enable interrupt (1) or mask out (0)*/
  1794. #ifndef MRV_ISP_IMSC_AFM_FIN
  1795. #define MRV_ISP_IMSC_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1796. #endif /* !IMSC_AFM_FIN */
  1797. /* Slice: IMSC_AFM_LUM_OF:*/
  1798. /* enable interrupt (1) or mask out (0)*/
  1799. #ifndef MRV_ISP_IMSC_AFM_LUM_OF
  1800. #define MRV_ISP_IMSC_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1801. #endif /* !MRV_ISP_IMSC_AFM_LUM_OF */
  1802. /* Slice: IMSC_AFM_SUM_OF:*/
  1803. /* enable interrupt (1) or mask out (0)*/
  1804. #ifndef MRV_ISP_IMSC_AFM_SUM_OF
  1805. #define MRV_ISP_IMSC_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1806. #endif /* !MRV_ISP_IMSC_AFM_SUM_OF */
  1807. /* Slice: IMSC_SHUTTER_OFF:*/
  1808. /* enable interrupt (1) or mask out (0)*/
  1809. #ifndef MRV_ISP_IMSC_SHUTTER_OFF
  1810. #define MRV_ISP_IMSC_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1811. #endif /* !MRV_ISP_IMSC_SHUTTER_OFF */
  1812. /* Slice: IMSC_SHUTTER_ON:*/
  1813. /* enable interrupt (1) or mask out (0)*/
  1814. #ifndef MRV_ISP_IMSC_SHUTTER_ON
  1815. #define MRV_ISP_IMSC_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1816. #endif /* !MRV_ISP_IMSC_SHUTTER_ON */
  1817. /* Slice: IMSC_FLASH_OFF:*/
  1818. /* enable interrupt (1) or mask out (0)*/
  1819. #ifndef MRV_ISP_IMSC_FLASH_OFF
  1820. #define MRV_ISP_IMSC_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1821. #endif /* !MRV_ISP_IMSC_FLASH_OFF */
  1822. /* Slice: IMSC_FLASH_ON:*/
  1823. /* enable interrupt (1) or mask out (0)*/
  1824. #ifndef MRV_ISP_IMSC_FLASH_ON
  1825. #define MRV_ISP_IMSC_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1826. #endif /* !MRV_ISP_IMSC_FLASH_ON */
  1827. /* Slice: IMSC_H_START:*/
  1828. /* enable interrupt (1) or mask out (0)*/
  1829. #ifndef MRV_ISP_IMSC_H_START
  1830. #define MRV_ISP_IMSC_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1831. #endif /* !MRV_ISP_IMSC_H_START */
  1832. /* Slice: IMSC_V_START:*/
  1833. /* enable interrupt (1) or mask out (0)*/
  1834. #ifndef MRV_ISP_IMSC_V_START
  1835. #define MRV_ISP_IMSC_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1836. #endif /* !MRV_ISP_IMSC_V_START */
  1837. /* Slice: IMSC_FRAME_IN:*/
  1838. /* enable interrupt (1) or mask out (0)*/
  1839. #ifndef MRV_ISP_IMSC_FRAME_IN
  1840. #define MRV_ISP_IMSC_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1841. #endif /* !MRV_ISP_IMSC_FRAME_IN */
  1842. /* Slice: IMSC_AWB_DONE:*/
  1843. /* enable interrupt (1) or mask out (0)*/
  1844. #ifndef MRV_ISP_IMSC_AWB_DONE
  1845. #define MRV_ISP_IMSC_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1846. #endif /* !MRV_ISP_IMSC_AWB_DONE */
  1847. /* Slice: IMSC_PIC_SIZE_ERR:*/
  1848. /* enable interrupt (1) or mask out (0)*/
  1849. #ifndef MRV_ISP_IMSC_PIC_SIZE_ERR
  1850. #define MRV_ISP_IMSC_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1851. #endif /* !MRV_ISP_IMSC_PIC_SIZE_ERR */
  1852. /* Slice: IMSC_DATA_LOSS:*/
  1853. /* enable interrupt (1) or mask out (0)*/
  1854. #ifndef MRV_ISP_IMSC_DATA_LOSS
  1855. #define MRV_ISP_IMSC_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1856. #endif /* !MRV_ISP_IMSC_DATA_LOSS */
  1857. /* Slice: IMSC_FRAME:*/
  1858. /* enable interrupt (1) or mask out (0)*/
  1859. #ifndef MRV_ISP_IMSC_FRAME
  1860. #define MRV_ISP_IMSC_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1861. #endif /* !MRV_ISP_IMSC_FRAME */
  1862. /* Slice: IMSC_ISP_OFF:*/
  1863. /* enable interrupt (1) or mask out (0)*/
  1864. #ifndef MRV_ISP_IMSC_ISP_OFF
  1865. #define MRV_ISP_IMSC_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1866. #endif /* !MRV_ISP_IMSC_ISP_OFF */
  1867. /* combination of all interrupt lines */
  1868. #define MRV_ISP_IMSC_ALL_IRQS
  1869. #define MRV_ISP_IMSC_ALL_IRQS_MASK \
  1870. (0 \
  1871. | MRV_ISP_IMSC_VSM_END_MASK \
  1872. | MRV_ISP_IMSC_EXP_END_MASK \
  1873. | MRV_ISP_IMSC_FLASH_CAP_MASK \
  1874. | MRV_ISP_IMSC_BP_DET_MASK \
  1875. | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK \
  1876. | MRV_ISP_IMSC_AFM_FIN_MASK \
  1877. | MRV_ISP_IMSC_AFM_LUM_OF_MASK \
  1878. | MRV_ISP_IMSC_AFM_SUM_OF_MASK \
  1879. | MRV_ISP_IMSC_SHUTTER_OFF_MASK \
  1880. | MRV_ISP_IMSC_SHUTTER_ON_MASK \
  1881. | MRV_ISP_IMSC_FLASH_OFF_MASK \
  1882. | MRV_ISP_IMSC_FLASH_ON_MASK \
  1883. | MRV_ISP_IMSC_H_START_MASK \
  1884. | MRV_ISP_IMSC_V_START_MASK \
  1885. | MRV_ISP_IMSC_FRAME_IN_MASK \
  1886. | MRV_ISP_IMSC_AWB_DONE_MASK \
  1887. | MRV_ISP_IMSC_PIC_SIZE_ERR_MASK \
  1888. | MRV_ISP_IMSC_DATA_LOSS_MASK \
  1889. | MRV_ISP_IMSC_FRAME_MASK \
  1890. | MRV_ISP_IMSC_ISP_OFF_MASK \
  1891. )
  1892. #define MRV_ISP_IMSC_ALL_IRQS_SHIFT 0U
  1893. /*****************************************************************************/
  1894. /**
  1895. * register: isp_ris: Raw interrupt status (0x000001c0)
  1896. *
  1897. *****************************************************************************/
  1898. /*! Slice: RIS_VSM_END:*/
  1899. /*! VSM measurement complete */
  1900. #ifndef MRV_ISP_RIS_VSM_END
  1901. #define MRV_ISP_RIS_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1902. #endif /* !MRV_ISP_RIS_VSM_END */
  1903. /* Slice: RIS_EXP_END:*/
  1904. /* enable interrupt (1) or mask out (0)*/
  1905. #ifndef MRV_ISP_RIS_EXP_END
  1906. #define MRV_ISP_RIS_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1907. #endif /* !MRV_ISP_RIS_EXP_END */
  1908. /* Slice: RIS_FLASH_CAP:*/
  1909. /* enable interrupt (1) or mask out (0)*/
  1910. #ifndef MRV_ISP_RIS_FLASH_CAP
  1911. #define MRV_ISP_RIS_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1912. #endif /* !MRV_ISP_RIS_FLASH_CAP */
  1913. /* Slice: RIS_BP_DET:*/
  1914. /* enable interrupt (1) or mask out (0)*/
  1915. #ifndef MRV_ISP_RIS_BP_DET
  1916. #define MRV_ISP_RIS_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1917. #endif /* !MRV_ISP_RIS_BP_DET */
  1918. /* Slice: RIS_HIST_MEASURE_RDY:*/
  1919. /* enable interrupt (1) or mask out (0)*/
  1920. #ifndef MRV_ISP_RIS_HIST_MEASURE_RDY
  1921. #define MRV_ISP_RIS_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1922. #endif /* !MRV_ISP_RIS_HIST_MEASURE_RDY */
  1923. /* Slice: RIS_AFM_FIN:*/
  1924. /* enable interrupt (1) or mask out (0)*/
  1925. #ifndef MRV_ISP_RIS_AFM_FIN
  1926. #define MRV_ISP_RIS_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1927. #endif /* !RIS_AFM_FIN */
  1928. /* Slice: RIS_AFM_LUM_OF:*/
  1929. /* enable interrupt (1) or mask out (0)*/
  1930. #ifndef MRV_ISP_RIS_AFM_LUM_OF
  1931. #define MRV_ISP_RIS_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1932. #endif /* !MRV_ISP_RIS_AFM_LUM_OF */
  1933. /* Slice: RIS_AFM_SUM_OF:*/
  1934. /* enable interrupt (1) or mask out (0)*/
  1935. #ifndef MRV_ISP_RIS_AFM_SUM_OF
  1936. #define MRV_ISP_RIS_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1937. #endif /* !MRV_ISP_RIS_AFM_SUM_OF */
  1938. /* Slice: RIS_SHUTTER_OFF:*/
  1939. /* enable interrupt (1) or mask out (0)*/
  1940. #ifndef MRV_ISP_RIS_SHUTTER_OFF
  1941. #define MRV_ISP_RIS_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1942. #endif /* !MRV_ISP_RIS_SHUTTER_OFF */
  1943. /* Slice: RIS_SHUTTER_ON:*/
  1944. /* enable interrupt (1) or mask out (0)*/
  1945. #ifndef MRV_ISP_RIS_SHUTTER_ON
  1946. #define MRV_ISP_RIS_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1947. #endif /* !MRV_ISP_RIS_SHUTTER_ON */
  1948. /* Slice: RIS_FLASH_OFF:*/
  1949. /* enable interrupt (1) or mask out (0)*/
  1950. #ifndef MRV_ISP_RIS_FLASH_OFF
  1951. #define MRV_ISP_RIS_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1952. #endif /* !MRV_ISP_RIS_FLASH_OFF */
  1953. /* Slice: RIS_FLASH_ON:*/
  1954. /* enable interrupt (1) or mask out (0)*/
  1955. #ifndef MRV_ISP_RIS_FLASH_ON
  1956. #define MRV_ISP_RIS_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1957. #endif /* !MRV_ISP_RIS_FLASH_ON */
  1958. /* Slice: RIS_H_START:*/
  1959. /* enable interrupt (1) or mask out (0)*/
  1960. #ifndef MRV_ISP_RIS_H_START
  1961. #define MRV_ISP_RIS_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1962. #endif /* !MRV_ISP_RIS_H_START */
  1963. /* Slice: RIS_V_START:*/
  1964. /* enable interrupt (1) or mask out (0)*/
  1965. #ifndef MRV_ISP_RIS_V_START
  1966. #define MRV_ISP_RIS_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1967. #endif /* !MRV_ISP_RIS_V_START */
  1968. /* Slice: RIS_FRAME_IN:*/
  1969. /* enable interrupt (1) or mask out (0)*/
  1970. #ifndef MRV_ISP_RIS_FRAME_IN
  1971. #define MRV_ISP_RIS_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1972. #endif /* !MRV_ISP_RIS_FRAME_IN */
  1973. /* Slice: RIS_AWB_DONE:*/
  1974. /* enable interrupt (1) or mask out (0)*/
  1975. #ifndef MRV_ISP_RIS_AWB_DONE
  1976. #define MRV_ISP_RIS_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1977. #endif /* !MRV_ISP_RIS_AWB_DONE */
  1978. /* Slice: RIS_PIC_SIZE_ERR:*/
  1979. /* enable interrupt (1) or mask out (0)*/
  1980. #ifndef MRV_ISP_RIS_PIC_SIZE_ERR
  1981. #define MRV_ISP_RIS_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1982. #endif /* !MRV_ISP_RIS_PIC_SIZE_ERR */
  1983. /* Slice: RIS_DATA_LOSS:*/
  1984. /* enable interrupt (1) or mask out (0)*/
  1985. #ifndef MRV_ISP_RIS_DATA_LOSS
  1986. #define MRV_ISP_RIS_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1987. #endif /* !MRV_ISP_RIS_DATA_LOSS */
  1988. /* Slice: RIS_FRAME:*/
  1989. /* enable interrupt (1) or mask out (0)*/
  1990. #ifndef MRV_ISP_RIS_FRAME
  1991. #define MRV_ISP_RIS_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1992. #endif /* !MRV_ISP_RIS_FRAME */
  1993. /* Slice: RIS_ISP_OFF:*/
  1994. /* enable interrupt (1) or mask out (0)*/
  1995. #ifndef MRV_ISP_RIS_ISP_OFF
  1996. #define MRV_ISP_RIS_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  1997. #endif /* !MRV_ISP_RIS_ISP_OFF */
  1998. /* combination of all interrupt lines */
  1999. #define MRV_ISP_RIS_ALL_IRQS
  2000. #define MRV_ISP_RIS_ALL_IRQS_MASK \
  2001. (0 \
  2002. | MRV_ISP_RIS_VSM_END_MASK \
  2003. | MRV_ISP_RIS_EXP_END_MASK \
  2004. | MRV_ISP_RIS_FLASH_CAP_MASK \
  2005. | MRV_ISP_RIS_BP_DET_MASK \
  2006. | MRV_ISP_RIS_HIST_MEASURE_RDY_MASK \
  2007. | MRV_ISP_RIS_AFM_FIN_MASK \
  2008. | MRV_ISP_RIS_AFM_LUM_OF_MASK \
  2009. | MRV_ISP_RIS_AFM_SUM_OF_MASK \
  2010. | MRV_ISP_RIS_SHUTTER_OFF_MASK \
  2011. | MRV_ISP_RIS_SHUTTER_ON_MASK \
  2012. | MRV_ISP_RIS_FLASH_OFF_MASK \
  2013. | MRV_ISP_RIS_FLASH_ON_MASK \
  2014. | MRV_ISP_RIS_H_START_MASK \
  2015. | MRV_ISP_RIS_V_START_MASK \
  2016. | MRV_ISP_RIS_FRAME_IN_MASK \
  2017. | MRV_ISP_RIS_AWB_DONE_MASK \
  2018. | MRV_ISP_RIS_PIC_SIZE_ERR_MASK \
  2019. | MRV_ISP_RIS_DATA_LOSS_MASK \
  2020. | MRV_ISP_RIS_FRAME_MASK \
  2021. | MRV_ISP_RIS_ISP_OFF_MASK \
  2022. )
  2023. #define MRV_ISP_RIS_ALL_IRQS_SHIFT 0U
  2024. /*****************************************************************************/
  2025. /**
  2026. * register: isp_mis: Masked interrupt status (0x000001c4)
  2027. *
  2028. *****************************************************************************/
  2029. /*! Slice: MIS_VSM_END:*/
  2030. /*! VSM measurement complete */
  2031. #ifndef MRV_ISP_MIS_VSM_END
  2032. #define MRV_ISP_MIS_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2033. #endif /* !MRV_ISP_MIS_VSM_END_MASK */
  2034. /* Slice: MIS_EXP_END:*/
  2035. /* enable interrupt (1) or mask out (0)*/
  2036. #ifndef MRV_ISP_MIS_EXP_END
  2037. #define MRV_ISP_MIS_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2038. #endif /* !MRV_ISP_MIS_EXP_END */
  2039. /* Slice: MIS_FLASH_CAP:*/
  2040. /* enable interrupt (1) or mask out (0)*/
  2041. #ifndef MRV_ISP_MIS_FLASH_CAP
  2042. #define MRV_ISP_MIS_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2043. #endif /* !MRV_ISP_MIS_FLASH_CAP */
  2044. /* Slice: MIS_BP_DET:*/
  2045. /* enable interrupt (1) or mask out (0)*/
  2046. #ifndef MRV_ISP_MIS_BP_DET
  2047. #define MRV_ISP_MIS_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2048. #endif /* !MRV_ISP_MIS_BP_DET */
  2049. /* Slice: MIS_HIST_MEASURE_RDY:*/
  2050. /* enable interrupt (1) or mask out (0)*/
  2051. #ifndef MRV_ISP_MIS_HIST_MEASURE_RDY
  2052. #define MRV_ISP_MIS_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2053. #endif /* !MRV_ISP_MIS_HIST_MEASURE_RDY */
  2054. /* Slice: MIS_AFM_FIN:*/
  2055. /* enable interrupt (1) or mask out (0)*/
  2056. #ifndef MRV_ISP_MIS_AFM_FIN
  2057. #define MRV_ISP_MIS_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2058. #endif /* !MIS_AFM_FIN */
  2059. /* Slice: MIS_AFM_LUM_OF:*/
  2060. /* enable interrupt (1) or mask out (0)*/
  2061. #ifndef MRV_ISP_MIS_AFM_LUM_OF
  2062. #define MRV_ISP_MIS_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2063. #endif /* !MRV_ISP_MIS_AFM_LUM_OF */
  2064. /* Slice: MIS_AFM_SUM_OF:*/
  2065. /* enable interrupt (1) or mask out (0)*/
  2066. #ifndef MRV_ISP_MIS_AFM_SUM_OF
  2067. #define MRV_ISP_MIS_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2068. #endif /* !MRV_ISP_MIS_AFM_SUM_OF */
  2069. /* Slice: MIS_SHUTTER_OFF:*/
  2070. /* enable interrupt (1) or mask out (0)*/
  2071. #ifndef MRV_ISP_MIS_SHUTTER_OFF
  2072. #define MRV_ISP_MIS_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2073. #endif /* !MRV_ISP_MIS_SHUTTER_OFF */
  2074. /* Slice: MIS_SHUTTER_ON:*/
  2075. /* enable interrupt (1) or mask out (0)*/
  2076. #ifndef MRV_ISP_MIS_SHUTTER_ON
  2077. #define MRV_ISP_MIS_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2078. #endif /* !MRV_ISP_MIS_SHUTTER_ON */
  2079. /* Slice: MIS_FLASH_OFF:*/
  2080. /* enable interrupt (1) or mask out (0)*/
  2081. #ifndef MRV_ISP_MIS_FLASH_OFF
  2082. #define MRV_ISP_MIS_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2083. #endif /* !MRV_ISP_MIS_FLASH_OFF */
  2084. /* Slice: MIS_FLASH_ON:*/
  2085. /* enable interrupt (1) or mask out (0)*/
  2086. #ifndef MRV_ISP_MIS_FLASH_ON
  2087. #define MRV_ISP_MIS_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2088. #endif /* !MRV_ISP_MIS_FLASH_ON */
  2089. /* Slice: MIS_H_START:*/
  2090. /* enable interrupt (1) or mask out (0)*/
  2091. #ifndef MRV_ISP_MIS_H_START
  2092. #define MRV_ISP_MIS_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2093. #endif /* !MRV_ISP_MIS_H_START */
  2094. /* Slice: MIS_V_START:*/
  2095. /* enable interrupt (1) or mask out (0)*/
  2096. #ifndef MRV_ISP_MIS_V_START
  2097. #define MRV_ISP_MIS_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2098. #endif /* !MRV_ISP_MIS_V_START */
  2099. /* Slice: MIS_FRAME_IN:*/
  2100. /* enable interrupt (1) or mask out (0)*/
  2101. #ifndef MRV_ISP_MIS_FRAME_IN
  2102. #define MRV_ISP_MIS_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2103. #endif /* !MRV_ISP_MIS_FRAME_IN */
  2104. /* Slice: MIS_AWB_DONE:*/
  2105. /* enable interrupt (1) or mask out (0)*/
  2106. #ifndef MRV_ISP_MIS_AWB_DONE
  2107. #define MRV_ISP_MIS_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2108. #endif /* !MRV_ISP_MIS_AWB_DONE */
  2109. /* Slice: MIS_PIC_SIZE_ERR:*/
  2110. /* enable interrupt (1) or mask out (0)*/
  2111. #ifndef MRV_ISP_MIS_PIC_SIZE_ERR
  2112. #define MRV_ISP_MIS_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2113. #endif /* !MRV_ISP_MIS_PIC_SIZE_ERR */
  2114. /* Slice: MIS_DATA_LOSS:*/
  2115. /* enable interrupt (1) or mask out (0)*/
  2116. #ifndef MRV_ISP_MIS_DATA_LOSS
  2117. #define MRV_ISP_MIS_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2118. #endif /* !MRV_ISP_MIS_DATA_LOSS */
  2119. /* Slice: MIS_FRAME:*/
  2120. /* enable interrupt (1) or mask out (0)*/
  2121. #ifndef MRV_ISP_MIS_FRAME
  2122. #define MRV_ISP_MIS_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2123. #endif /* !MRV_ISP_MIS_FRAME */
  2124. /* Slice: MIS_ISP_OFF:*/
  2125. /* enable interrupt (1) or mask out (0)*/
  2126. #ifndef MRV_ISP_MIS_ISP_OFF
  2127. #define MRV_ISP_MIS_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2128. #endif /* !MRV_ISP_MIS_ISP_OFF */
  2129. /* combination of all interrupt lines */
  2130. #define MRV_ISP_MIS_ALL_IRQS
  2131. #define MRV_ISP_MIS_ALL_IRQS_MASK \
  2132. (0 \
  2133. | MRV_ISP_MIS_VSM_END_MASK \
  2134. | MRV_ISP_MIS_EXP_END_MASK \
  2135. | MRV_ISP_MIS_FLASH_CAP_MASK \
  2136. | MRV_ISP_MIS_BP_DET_MASK \
  2137. | MRV_ISP_MIS_HIST_MEASURE_RDY_MASK \
  2138. | MRV_ISP_MIS_AFM_FIN_MASK \
  2139. | MRV_ISP_MIS_AFM_LUM_OF_MASK \
  2140. | MRV_ISP_MIS_AFM_SUM_OF_MASK \
  2141. | MRV_ISP_MIS_SHUTTER_OFF_MASK \
  2142. | MRV_ISP_MIS_SHUTTER_ON_MASK \
  2143. | MRV_ISP_MIS_FLASH_OFF_MASK \
  2144. | MRV_ISP_MIS_FLASH_ON_MASK \
  2145. | MRV_ISP_MIS_H_START_MASK \
  2146. | MRV_ISP_MIS_V_START_MASK \
  2147. | MRV_ISP_MIS_FRAME_IN_MASK \
  2148. | MRV_ISP_MIS_AWB_DONE_MASK \
  2149. | MRV_ISP_MIS_PIC_SIZE_ERR_MASK \
  2150. | MRV_ISP_MIS_DATA_LOSS_MASK \
  2151. | MRV_ISP_MIS_FRAME_MASK \
  2152. | MRV_ISP_MIS_ISP_OFF_MASK \
  2153. )
  2154. #define MRV_ISP_MIS_ALL_IRQS_SHIFT 0U
  2155. /*****************************************************************************/
  2156. /**
  2157. * register: isp_icr: Interrupt clear register (0x000001c8)
  2158. *
  2159. *****************************************************************************/
  2160. /*! Slice: ICR_VSM_END:*/
  2161. /*! clear interrupt */
  2162. #ifndef MRV_ISP_ICR_VSM_END
  2163. #define MRV_ISP_ICR_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2164. #endif /* !MRV_ISP_ICR_VSM_END */
  2165. /* Slice: ICR_EXP_END:*/
  2166. /* enable interrupt (1) or mask out (0)*/
  2167. #ifndef MRV_ISP_ICR_EXP_END
  2168. #define MRV_ISP_ICR_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2169. #endif /* !MRV_ISP_ICR_EXP_END */
  2170. /* Slice: ICR_FLASH_CAP:*/
  2171. /* enable interrupt (1) or mask out (0)*/
  2172. #ifndef MRV_ISP_ICR_FLASH_CAP
  2173. #define MRV_ISP_ICR_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2174. #endif /* !MRV_ISP_ICR_FLASH_CAP */
  2175. /* Slice: ICR_BP_DET:*/
  2176. /* enable interrupt (1) or mask out (0)*/
  2177. #ifndef MRV_ISP_ICR_BP_DET
  2178. #define MRV_ISP_ICR_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2179. #endif /* !MRV_ISP_ICR_BP_DET */
  2180. /* Slice: ICR_HIST_MEASURE_RDY:*/
  2181. /* enable interrupt (1) or mask out (0)*/
  2182. #ifndef MRV_ISP_ICR_HIST_MEASURE_RDY
  2183. #define MRV_ISP_ICR_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2184. #endif /* !MRV_ISP_ICR_HIST_MEASURE_RDY */
  2185. /* Slice: ICR_AFM_FIN:*/
  2186. /* enable interrupt (1) or mask out (0)*/
  2187. #ifndef MRV_ISP_ICR_AFM_FIN
  2188. #define MRV_ISP_ICR_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2189. #endif /* !ICR_AFM_FIN */
  2190. /* Slice: ICR_AFM_LUM_OF:*/
  2191. /* enable interrupt (1) or mask out (0)*/
  2192. #ifndef MRV_ISP_ICR_AFM_LUM_OF
  2193. #define MRV_ISP_ICR_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2194. #endif /* !MRV_ISP_ICR_AFM_LUM_OF */
  2195. /* Slice: ICR_AFM_SUM_OF:*/
  2196. /* enable interrupt (1) or mask out (0)*/
  2197. #ifndef MRV_ISP_ICR_AFM_SUM_OF
  2198. #define MRV_ISP_ICR_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2199. #endif /* !MRV_ISP_ICR_AFM_SUM_OF */
  2200. /* Slice: ICR_SHUTTER_OFF:*/
  2201. /* enable interrupt (1) or mask out (0)*/
  2202. #ifndef MRV_ISP_ICR_SHUTTER_OFF
  2203. #define MRV_ISP_ICR_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2204. #endif /* !MRV_ISP_ICR_SHUTTER_OFF */
  2205. /* Slice: ICR_SHUTTER_ON:*/
  2206. /* enable interrupt (1) or mask out (0)*/
  2207. #ifndef MRV_ISP_ICR_SHUTTER_ON
  2208. #define MRV_ISP_ICR_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2209. #endif /* !MRV_ISP_ICR_SHUTTER_ON */
  2210. /* Slice: ICR_FLASH_OFF:*/
  2211. /* enable interrupt (1) or mask out (0)*/
  2212. #ifndef MRV_ISP_ICR_FLASH_OFF
  2213. #define MRV_ISP_ICR_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2214. #endif /* !MRV_ISP_ICR_FLASH_OFF */
  2215. /* Slice: ICR_FLASH_ON:*/
  2216. /* enable interrupt (1) or mask out (0)*/
  2217. #ifndef MRV_ISP_ICR_FLASH_ON
  2218. #define MRV_ISP_ICR_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2219. #endif /* !MRV_ISP_ICR_FLASH_ON */
  2220. /* Slice: ICR_H_START:*/
  2221. /* enable interrupt (1) or mask out (0)*/
  2222. #ifndef MRV_ISP_ICR_H_START
  2223. #define MRV_ISP_ICR_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2224. #endif /* !MRV_ISP_ICR_H_START */
  2225. /* Slice: ICR_V_START:*/
  2226. /* enable interrupt (1) or mask out (0)*/
  2227. #ifndef MRV_ISP_ICR_V_START
  2228. #define MRV_ISP_ICR_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2229. #endif /* !MRV_ISP_ICR_V_START */
  2230. /* Slice: ICR_FRAME_IN:*/
  2231. /* enable interrupt (1) or mask out (0)*/
  2232. #ifndef MRV_ISP_ICR_FRAME_IN
  2233. #define MRV_ISP_ICR_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2234. #endif /* !MRV_ISP_ICR_FRAME_IN */
  2235. /* Slice: ICR_AWB_DONE:*/
  2236. /* enable interrupt (1) or mask out (0)*/
  2237. #ifndef MRV_ISP_ICR_AWB_DONE
  2238. #define MRV_ISP_ICR_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2239. #endif /* !MRV_ISP_ICR_AWB_DONE */
  2240. /* Slice: ICR_PIC_SIZE_ERR:*/
  2241. /* enable interrupt (1) or mask out (0)*/
  2242. #ifndef MRV_ISP_ICR_PIC_SIZE_ERR
  2243. #define MRV_ISP_ICR_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2244. #endif /* !MRV_ISP_ICR_PIC_SIZE_ERR */
  2245. /* Slice: ICR_DATA_LOSS:*/
  2246. /* enable interrupt (1) or mask out (0)*/
  2247. #ifndef MRV_ISP_ICR_DATA_LOSS
  2248. #define MRV_ISP_ICR_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2249. #endif /* !MRV_ISP_ICR_DATA_LOSS */
  2250. /* Slice: ICR_FRAME:*/
  2251. /* enable interrupt (1) or mask out (0)*/
  2252. #ifndef MRV_ISP_ICR_FRAME
  2253. #define MRV_ISP_ICR_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2254. #endif /* !MRV_ISP_ICR_FRAME */
  2255. /* Slice: ICR_ISP_OFF:*/
  2256. /* enable interrupt (1) or mask out (0)*/
  2257. #ifndef MRV_ISP_ICR_ISP_OFF
  2258. #define MRV_ISP_ICR_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2259. #endif /* !MRV_ISP_ICR_ISP_OFF */
  2260. /* combination of all interrupt lines */
  2261. #define MRV_ISP_ICR_ALL_IRQS
  2262. #define MRV_ISP_ICR_ALL_IRQS_MASK \
  2263. (0 \
  2264. | MRV_ISP_ICR_VSM_END_MASK \
  2265. | MRV_ISP_ICR_EXP_END_MASK \
  2266. | MRV_ISP_ICR_FLASH_CAP_MASK \
  2267. | MRV_ISP_ICR_BP_DET_MASK \
  2268. | MRV_ISP_ICR_HIST_MEASURE_RDY_MASK \
  2269. | MRV_ISP_ICR_AFM_FIN_MASK \
  2270. | MRV_ISP_ICR_AFM_LUM_OF_MASK \
  2271. | MRV_ISP_ICR_AFM_SUM_OF_MASK \
  2272. | MRV_ISP_ICR_SHUTTER_OFF_MASK \
  2273. | MRV_ISP_ICR_SHUTTER_ON_MASK \
  2274. | MRV_ISP_ICR_FLASH_OFF_MASK \
  2275. | MRV_ISP_ICR_FLASH_ON_MASK \
  2276. | MRV_ISP_ICR_H_START_MASK \
  2277. | MRV_ISP_ICR_V_START_MASK \
  2278. | MRV_ISP_ICR_FRAME_IN_MASK \
  2279. | MRV_ISP_ICR_AWB_DONE_MASK \
  2280. | MRV_ISP_ICR_PIC_SIZE_ERR_MASK \
  2281. | MRV_ISP_ICR_DATA_LOSS_MASK \
  2282. | MRV_ISP_ICR_FRAME_MASK \
  2283. | MRV_ISP_ICR_ISP_OFF_MASK \
  2284. )
  2285. #define MRV_ISP_ICR_ALL_IRQS_SHIFT 0U
  2286. /*****************************************************************************/
  2287. /**
  2288. * register: isp_isr: Interrupt set register (0x000001cc)
  2289. *
  2290. *****************************************************************************/
  2291. /*! Register: isp_isr: Interrupt set register (0x000001cc)*/
  2292. /*! Slice: ISR_VSM_END:*/
  2293. /*! set interrupt */
  2294. #ifndef MRV_ISP_ISR_VSM_END
  2295. #define MRV_ISP_ISR_VSM_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2296. #endif /* !MRV_ISP_ISR_VSM_END */
  2297. /* Slice: ISR_EXP_END:*/
  2298. /* enable interrupt (1) or mask out (0)*/
  2299. #ifndef MRV_ISP_ISR_EXP_END
  2300. #define MRV_ISP_ISR_EXP_END_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2301. #endif /* !MRV_ISP_ISR_EXP_END */
  2302. /* Slice: ISR_FLASH_CAP:*/
  2303. /* enable interrupt (1) or mask out (0)*/
  2304. #ifndef MRV_ISP_ISR_FLASH_CAP
  2305. #define MRV_ISP_ISR_FLASH_CAP_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2306. #endif /* !MRV_ISP_ISR_FLASH_CAP */
  2307. /* Slice: ISR_BP_DET:*/
  2308. /* enable interrupt (1) or mask out (0)*/
  2309. #ifndef MRV_ISP_ISR_BP_DET
  2310. #define MRV_ISP_ISR_BP_DET_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2311. #endif /* !MRV_ISP_ISR_BP_DET */
  2312. /* Slice: ISR_HIST_MEASURE_RDY:*/
  2313. /* enable interrupt (1) or mask out (0)*/
  2314. #ifndef MRV_ISP_ISR_HIST_MEASURE_RDY
  2315. #define MRV_ISP_ISR_HIST_MEASURE_RDY_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2316. #endif /* !MRV_ISP_ISR_HIST_MEASURE_RDY */
  2317. /* Slice: ISR_AFM_FIN:*/
  2318. /* enable interrupt (1) or mask out (0)*/
  2319. #ifndef MRV_ISP_ISR_AFM_FIN
  2320. #define MRV_ISP_ISR_AFM_FIN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2321. #endif /* !ISR_AFM_FIN */
  2322. /* Slice: ISR_AFM_LUM_OF:*/
  2323. /* enable interrupt (1) or mask out (0)*/
  2324. #ifndef MRV_ISP_ISR_AFM_LUM_OF
  2325. #define MRV_ISP_ISR_AFM_LUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2326. #endif /* !MRV_ISP_ISR_AFM_LUM_OF */
  2327. /* Slice: ISR_AFM_SUM_OF:*/
  2328. /* enable interrupt (1) or mask out (0)*/
  2329. #ifndef MRV_ISP_ISR_AFM_SUM_OF
  2330. #define MRV_ISP_ISR_AFM_SUM_OF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2331. #endif /* !MRV_ISP_ISR_AFM_SUM_OF */
  2332. /* Slice: ISR_SHUTTER_OFF:*/
  2333. /* enable interrupt (1) or mask out (0)*/
  2334. #ifndef MRV_ISP_ISR_SHUTTER_OFF
  2335. #define MRV_ISP_ISR_SHUTTER_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2336. #endif /* !MRV_ISP_ISR_SHUTTER_OFF */
  2337. /* Slice: ISR_SHUTTER_ON:*/
  2338. /* enable interrupt (1) or mask out (0)*/
  2339. #ifndef MRV_ISP_ISR_SHUTTER_ON
  2340. #define MRV_ISP_ISR_SHUTTER_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2341. #endif /* !MRV_ISP_ISR_SHUTTER_ON */
  2342. /* Slice: ISR_FLASH_OFF:*/
  2343. /* enable interrupt (1) or mask out (0)*/
  2344. #ifndef MRV_ISP_ISR_FLASH_OFF
  2345. #define MRV_ISP_ISR_FLASH_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2346. #endif /* !MRV_ISP_ISR_FLASH_OFF */
  2347. /* Slice: ISR_FLASH_ON:*/
  2348. /* enable interrupt (1) or mask out (0)*/
  2349. #ifndef MRV_ISP_ISR_FLASH_ON
  2350. #define MRV_ISP_ISR_FLASH_ON_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2351. #endif /* !MRV_ISP_ISR_FLASH_ON */
  2352. /* Slice: ISR_H_START:*/
  2353. /* enable interrupt (1) or mask out (0)*/
  2354. #ifndef MRV_ISP_ISR_H_START
  2355. #define MRV_ISP_ISR_H_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2356. #endif /* !MRV_ISP_ISR_H_START */
  2357. /* Slice: ISR_V_START:*/
  2358. /* enable interrupt (1) or mask out (0)*/
  2359. #ifndef MRV_ISP_ISR_V_START
  2360. #define MRV_ISP_ISR_V_START_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2361. #endif /* !MRV_ISP_ISR_V_START */
  2362. /* Slice: ISR_FRAME_IN:*/
  2363. /* enable interrupt (1) or mask out (0)*/
  2364. #ifndef MRV_ISP_ISR_FRAME_IN
  2365. #define MRV_ISP_ISR_FRAME_IN_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2366. #endif /* !MRV_ISP_ISR_FRAME_IN */
  2367. /* Slice: ISR_AWB_DONE:*/
  2368. /* enable interrupt (1) or mask out (0)*/
  2369. #ifndef MRV_ISP_ISR_AWB_DONE
  2370. #define MRV_ISP_ISR_AWB_DONE_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2371. #endif /* !MRV_ISP_ISR_AWB_DONE */
  2372. /* Slice: ISR_PIC_SIZE_ERR:*/
  2373. /* enable interrupt (1) or mask out (0)*/
  2374. #ifndef MRV_ISP_ISR_PIC_SIZE_ERR
  2375. #define MRV_ISP_ISR_PIC_SIZE_ERR_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2376. #endif /* !MRV_ISP_ISR_PIC_SIZE_ERR */
  2377. /* Slice: ISR_DATA_LOSS:*/
  2378. /* enable interrupt (1) or mask out (0)*/
  2379. #ifndef MRV_ISP_ISR_DATA_LOSS
  2380. #define MRV_ISP_ISR_DATA_LOSS_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2381. #endif /* !MRV_ISP_ISR_DATA_LOSS */
  2382. /* Slice: ISR_FRAME:*/
  2383. /* enable interrupt (1) or mask out (0)*/
  2384. #ifndef MRV_ISP_ISR_FRAME
  2385. #define MRV_ISP_ISR_FRAME_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2386. #endif /* !MRV_ISP_ISR_FRAME */
  2387. /* Slice: ISR_ISP_OFF:*/
  2388. /* enable interrupt (1) or mask out (0)*/
  2389. #ifndef MRV_ISP_ISR_ISP_OFF
  2390. #define MRV_ISP_ISR_ISP_OFF_MASK 0U /* make sure, that this mask is defined for the combination mask */
  2391. #endif /* !MRV_ISP_ISR_ISP_OFF */
  2392. /* combination of all interrupt lines */
  2393. #define MRV_ISP_ISR_ALL_IRQS
  2394. #define MRV_ISP_ISR_ALL_IRQS_MASK \
  2395. (0 \
  2396. | MRV_ISP_ISR_VSM_END_MASK \
  2397. | MRV_ISP_ISR_EXP_END_MASK \
  2398. | MRV_ISP_ISR_FLASH_CAP_MASK \
  2399. | MRV_ISP_ISR_BP_DET_MASK \
  2400. | MRV_ISP_ISR_HIST_MEASURE_RDY_MASK \
  2401. | MRV_ISP_ISR_AFM_FIN_MASK \
  2402. | MRV_ISP_ISR_AFM_LUM_OF_MASK \
  2403. | MRV_ISP_ISR_AFM_SUM_OF_MASK \
  2404. | MRV_ISP_ISR_SHUTTER_OFF_MASK \
  2405. | MRV_ISP_ISR_SHUTTER_ON_MASK \
  2406. | MRV_ISP_ISR_FLASH_OFF_MASK \
  2407. | MRV_ISP_ISR_FLASH_ON_MASK \
  2408. | MRV_ISP_ISR_H_START_MASK \
  2409. | MRV_ISP_ISR_V_START_MASK \
  2410. | MRV_ISP_ISR_FRAME_IN_MASK \
  2411. | MRV_ISP_ISR_AWB_DONE_MASK \
  2412. | MRV_ISP_ISR_PIC_SIZE_ERR_MASK \
  2413. | MRV_ISP_ISR_DATA_LOSS_MASK \
  2414. | MRV_ISP_ISR_FRAME_MASK \
  2415. | MRV_ISP_ISR_ISP_OFF_MASK \
  2416. )
  2417. #define MRV_ISP_ISR_ALL_IRQS_SHIFT 0U
  2418. /*****************************************************************************/
  2419. /**
  2420. * register array: isp_ct_coeff: cross-talk configuration register (color
  2421. * correction matrix) (0x03A0 + n*0x4 (n=0..8))
  2422. *
  2423. *****************************************************************************/
  2424. /* Slice: ct_coeff:*/
  2425. /* Coefficient n for cross talk matrix.*/
  2426. /**/
  2427. /* Values are 11-bit signed fixed-point numbers with 4 bit integer and */
  2428. /* 7 bit fractional part, ranging from -8 (0x400) to +7.992 (0x3FF).*/
  2429. /* 0 is reprsented by 0x000 and a coefficient value of 1 as 0x080.*/
  2430. #ifdef MRV_ISP_CT_COEFF
  2431. #define MRV_ISP_CT_COEFF_DEFAULT 0x080U /* default value */
  2432. #endif /* MRV_ISP_CT_COEFF */
  2433. /*****************************************************************************/
  2434. /**
  2435. * register: isp_gamma_out_mode: gamma segmentation mode register for output
  2436. * gamma (0x000001f4)
  2437. *
  2438. *****************************************************************************/
  2439. /* Slice: equ_segm:*/
  2440. /* 0: logarithmic like segmentation of gamma curve (default after reset)*/
  2441. /* segmentation from 0 to 4095: 64 64 64 64 128 128 128 128 256 256 256 512 512 512 512 512 */
  2442. /* 1: equidistant segmentation (all 16 segments are 256)*/
  2443. #ifdef MRV_ISP_EQU_SEGM
  2444. #define MRV_ISP_EQU_SEGM_LOG 0 /* 0: logarithmic like segmentation of gamma curve (default after reset) */
  2445. #define MRV_ISP_EQU_SEGM_EQU 1 /* 1: equidistant segmentation (all 16 segments are 256) */
  2446. #endif /* MRV_ISP_EQU_SEGM */
  2447. /*****************************************************************************/
  2448. /**
  2449. * register array: isp_gamma_out_y: Gamma Out Curve definition y (0x03F0 + n*0x4 (n=0..16))
  2450. *
  2451. *****************************************************************************/
  2452. /* Slice: isp_gamma_out_y:*/
  2453. /* Gamma_out curve point definition y-axis (output) for all color */
  2454. /* components (red, green, blue)*/
  2455. /* RESTRICTION: each Y_n must be in the +511/-512 range compared */
  2456. /* to its predecessor (so that dy is 10-bit signed !)*/
  2457. #ifdef MRV_ISP_ISP_GAMMA_OUT_Y
  2458. #endif /* MRV_ISP_ISP_GAMMA_OUT_Y */
  2459. /*****************************************************************************/
  2460. /**
  2461. * register: isp_err: ISP error register (0x0000023c)
  2462. *
  2463. *****************************************************************************/
  2464. /* Slice: outform_size_err:*/
  2465. /* size error is generated in outmux submodule */
  2466. #ifdef MRV_ISP_OUTFORM_SIZE_ERR
  2467. #endif /* MRV_ISP_OUTFORM_SIZE_ERR */
  2468. /* Slice: is_size_err:*/
  2469. /* size error is generated in image stabilization submodule */
  2470. #ifdef MRV_ISP_IS_SIZE_ERR
  2471. #endif /* MRV_ISP_IS_SIZE_ERR */
  2472. /* Slice: inform_size_err:*/
  2473. /* size error is generated in inform submodule */
  2474. #ifdef MRV_ISP_INFORM_SIZE_ERR
  2475. #endif /* MRV_ISP_INFORM_SIZE_ERR */
  2476. /*****************************************************************************/
  2477. /**
  2478. * register: isp_err_clr: ISP error clear register (0x00000240)
  2479. *
  2480. *****************************************************************************/
  2481. /* Slice: outform_size_err_clr:*/
  2482. /* size error is cleared */
  2483. #ifdef MRV_ISP_OUTFORM_SIZE_ERR_CLR
  2484. #endif /* MRV_ISP_OUTFORM_SIZE_ERR_CLR */
  2485. /* Slice: is_size_err_clr:*/
  2486. /* size error is cleared */
  2487. #ifdef MRV_ISP_IS_SIZE_ERR_CLR
  2488. #endif /* MRV_ISP_IS_SIZE_ERR_CLR */
  2489. /* Slice: inform_size_err_clr:*/
  2490. /* size error is cleared */
  2491. #ifdef MRV_ISP_INFORM_SIZE_ERR_CLR
  2492. #endif /* MRV_ISP_INFORM_SIZE_ERR_CLR */
  2493. /*****************************************************************************/
  2494. /**
  2495. * register: isp_frame_count: Frame counter (0x00000244)
  2496. *
  2497. *****************************************************************************/
  2498. /* Slice: frame_counter:*/
  2499. /* Current frame count of processing */
  2500. #ifdef MRV_ISP_FRAME_COUNTER
  2501. #endif /* MRV_ISP_FRAME_COUNTER */
  2502. /*****************************************************************************/
  2503. /**
  2504. * register: isp_ct_offset_r: cross-talk offset red (0x00000248)
  2505. *
  2506. *****************************************************************************/
  2507. /* Slice: ct_offset_r:*/
  2508. /* Offset red for cross talk matrix. Two's complement integer number ranging */
  2509. /* from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/
  2510. #ifdef MRV_ISP_CT_OFFSET_R
  2511. #define MRV_ISP_CT_OFFSET_R_DEFAULT 0x000U /* default value */
  2512. #endif /* MRV_ISP_CT_OFFSET_R */
  2513. /*****************************************************************************/
  2514. /**
  2515. * register: isp_ct_offset_g: cross-talk offset green (0x0000024c)
  2516. *
  2517. *****************************************************************************/
  2518. /* Slice: ct_offset_g:*/
  2519. /* Offset green for cross talk matrix. Two's complement integer number ranging */
  2520. /* from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/
  2521. #ifdef MRV_ISP_CT_OFFSET_G
  2522. #define MRV_ISP_CT_OFFSET_G_DEFAULT 0x000U /* default value */
  2523. #endif /* MRV_ISP_CT_OFFSET_G */
  2524. /*****************************************************************************/
  2525. /**
  2526. * register: isp_ct_offset_b: cross-talk offset blue (0x00000250)
  2527. *
  2528. *****************************************************************************/
  2529. /* Slice: ct_offset_b:*/
  2530. /* Offset blue for cross talk matrix. Two's complement integer number ranging */
  2531. /* from -2048 (0x800) to 2047 (0x7FF). 0 is represented as 0x000.*/
  2532. #ifdef MRV_ISP_CT_OFFSET_B
  2533. #define MRV_ISP_CT_OFFSET_B_DEFAULT 0x000U /* default value */
  2534. #endif /* MRV_ISP_CT_OFFSET_B */
  2535. /*****************************************************************************/
  2536. /* ISP Flash Module Registers */
  2537. /*****************************************************************************/
  2538. /*****************************************************************************/
  2539. /**
  2540. * register: isp_flash_cmd: Flash command (0x0000)
  2541. *
  2542. *****************************************************************************/
  2543. /* Slice: preflash_on:*/
  2544. /* preflash on */
  2545. /* 0: no effect */
  2546. /* 1: flash delay counter is started at next trigger event */
  2547. /* No capture event is signaled to the sensor interface block.*/
  2548. #ifdef MRV_FLASH_PREFLASH_ON
  2549. #endif /* MRV_FLASH_PREFLASH_ON */
  2550. /* Slice: flash_on:*/
  2551. /* flash on */
  2552. /* 0: no effect */
  2553. /* 1: flash delay counter is started at next trigger event */
  2554. /* A capture event is signaled to the sensor interface block.*/
  2555. #ifdef MRV_FLASH_FLASH_ON
  2556. #endif /* MRV_FLASH_FLASH_ON */
  2557. /* Slice: prelight_on:*/
  2558. /* prelight on */
  2559. /* 0: prelight is switched off at next trigger event */
  2560. /* 1: prelight is switched on at next trigger event */
  2561. #ifdef MRV_FLASH_PRELIGHT_ON
  2562. #endif /* MRV_FLASH_PRELIGHT_ON */
  2563. /*****************************************************************************/
  2564. /**
  2565. * register: isp_flash_config: Flash config (0x0004)
  2566. *
  2567. *****************************************************************************/
  2568. /* Slice: fl_cap_del:*/
  2569. /* capture delay */
  2570. /* frame number (0 to 15) to be captured after trigger event */
  2571. #ifdef MRV_FLASH_FL_CAP_DEL
  2572. #endif /* MRV_FLASH_FL_CAP_DEL */
  2573. /* Slice: fl_trig_src:*/
  2574. /* trigger source for flash and prelight */
  2575. /* 0: use "vds_vsync" for trigger event (with evaluation of vs_in_edge)*/
  2576. /* 1: use "fl_trig" for trigger event (positive edge)*/
  2577. #ifdef MRV_FLASH_FL_TRIG_SRC
  2578. #define MRV_FLASH_FL_TRIG_SRC_VDS 0 /* 0: use "vds_vsync" for trigger event (with evaluation of vs_in_edge) */
  2579. #define MRV_FLASH_FL_TRIG_SRC_FL 1 /* 1: use "fl_trig" for trigger event (positive edge) */
  2580. #endif /* MRV_FLASH_FL_TRIG_SRC */
  2581. /* Slice: fl_pol:*/
  2582. /* polarity of flash related signals */
  2583. /* 0: flash_trig, prelight_trig are high active */
  2584. /* 1: flash_trig, prelight_trig are low active */
  2585. #ifdef MRV_FLASH_FL_POL
  2586. #define MRV_FLASH_FL_POL_HIGH 0 /* 0: flash_trig, prelight_trig are high active */
  2587. #define MRV_FLASH_FL_POL_LOW 1 /* 1: flash_trig, prelight_trig are low active */
  2588. #endif /* MRV_FLASH_FL_POL */
  2589. /* Slice: vs_in_edge:*/
  2590. /* VSYNC edge */
  2591. /* 0: use negative edge of "vds_vsync" if generating a trigger event */
  2592. /* 1: use positive edge of "vds_vsync" if generating a trigger event */
  2593. #ifdef MRV_FLASH_VS_IN_EDGE
  2594. #define MRV_FLASH_VS_IN_EDGE_NEG 0 /* 0: use negative edge of "vds_vsync" if generating a trigger event */
  2595. #define MRV_FLASH_VS_IN_EDGE_POS 1 /* 1: use positive edge of "vds_vsync" if generating a trigger event */
  2596. #endif /* MRV_FLASH_VS_IN_EDGE */
  2597. /* Slice: prelight_mode:*/
  2598. /* prelight mode */
  2599. /* 0: prelight is switched off at begin of flash */
  2600. /* 1: prelight is switched off at end of flash */
  2601. #ifdef MRV_FLASH_PRELIGHT_MODE
  2602. #define MRV_FLASH_PRELIGHT_MODE_OASF 0 /* 0: prelight is switched off at begin of flash */
  2603. #define MRV_FLASH_PRELIGHT_MODE_OAEF 1 /* 1: prelight is switched off at end of flash */
  2604. #endif /* MRV_FLASH_PRELIGHT_MODE */
  2605. /*****************************************************************************/
  2606. /**
  2607. * register: isp_flash_prediv: Flash Counter Pre-Divider (0x00000008)
  2608. *
  2609. *****************************************************************************/
  2610. /* Slice: fl_pre_div:*/
  2611. /* pre-divider for flush/preflash counter */
  2612. #ifdef MRV_FLASH_FL_PRE_DIV
  2613. #endif /* MRV_FLASH_FL_PRE_DIV */
  2614. /*****************************************************************************/
  2615. /**
  2616. * register: isp_flash_delay: Flash Delay (0x000c)
  2617. *
  2618. *****************************************************************************/
  2619. /* Slice: fl_delay:*/
  2620. /* counter value for flash/preflash delay */
  2621. /* open_delay = (fl_delay + 1) * (fl_pre_div+1) / clk_isp */
  2622. /* fl_delay = (open_delay * clk_isp) / (fl_pre_div+1) - 1 */
  2623. #ifdef MRV_FLASH_FL_DELAY
  2624. #endif /* MRV_FLASH_FL_DELAY */
  2625. /*****************************************************************************/
  2626. /**
  2627. * register: isp_flash_time: Flash time (0x00000010)
  2628. *
  2629. *****************************************************************************/
  2630. /* Slice: fl_time:*/
  2631. /* counter value for flash/preflash time */
  2632. /* open_time = (fl_time + 1) * (fl_pre_div+1) / clk_isp */
  2633. /* fl_time = (open_time * clk_isp) / (fl_pre_div+1) - 1 */
  2634. #ifdef MRV_FLASH_FL_TIME
  2635. #endif /* MRV_FLASH_FL_TIME */
  2636. /*****************************************************************************/
  2637. /**
  2638. * register: isp_flash_maxp: Maximum value for flash or preflash (0x00000014)
  2639. *
  2640. *****************************************************************************/
  2641. /* Slice: fl_maxp:*/
  2642. /* maximum period value for flash or preflash */
  2643. /* max. flash/preflash period = 214 * (fl_maxp + 1) / clk_isp */
  2644. /* fl_maxp = (max_period * clk_isp) / 214 - 1 */
  2645. #ifdef MRV_FLASH_FL_MAXP
  2646. #endif /* MRV_FLASH_FL_MAXP */
  2647. /*****************************************************************************/
  2648. /* ISP Shutter Module Registers */
  2649. /*****************************************************************************/
  2650. /*****************************************************************************/
  2651. /**
  2652. * register: isp_sh_ctrl: mechanical shutter control (0x0000)
  2653. *
  2654. *****************************************************************************/
  2655. /* Slice: sh_open_pol:*/
  2656. /* shutter_open polarity */
  2657. /* 0: shutter_open is high active */
  2658. /* 1: shutter_open is low active */
  2659. #ifdef MRV_SHUT_SH_OPEN_POL
  2660. #define MRV_SHUT_SH_OPEN_POL_HIGH 0 /* 0: shutter_open is high active */
  2661. #define MRV_SHUT_SH_OPEN_POL_LOW 1 /* 1: shutter_open is low active */
  2662. #endif /* MRV_SHUT_SH_OPEN_POL */
  2663. /* Slice: sh_trig_en:*/
  2664. /* mechanical shutter trigger edge */
  2665. /* 0: use negative edge of trigger signal */
  2666. /* 1: use positive edge of trigger signal */
  2667. #ifdef MRV_SHUT_SH_TRIG_EN
  2668. #define MRV_SHUT_SH_TRIG_EN_NEG 0 /* 0: use negative edge of trigger signal */
  2669. #define MRV_SHUT_SH_TRIG_EN_POS 1 /* 1: use positive edge of trigger signal */
  2670. #endif /* MRV_SHUT_SH_TRIG_EN */
  2671. /* Slice: sh_trig_src:*/
  2672. /* mechanical shutter trigger source */
  2673. /* 0: use "vds_vsync" for trigger event */
  2674. /* 1: use "shutter_trig" for trigger event */
  2675. #ifdef MRV_SHUT_SH_TRIG_SRC
  2676. #define MRV_SHUT_SH_TRIG_SRC_VDS 0 /* 0: use "vds_vsync" for trigger event */
  2677. #define MRV_SHUT_SH_TRIG_SRC_SHUT 1 /* 1: use "shutter_trig" for trigger event */
  2678. #endif /* MRV_SHUT_SH_TRIG_SRC */
  2679. /* Slice: sh_rep_en:*/
  2680. /* mechanical shutter repetition enable */
  2681. /* 0: shutter is opened only once */
  2682. /* 1: shutter is opened with the repetition rate of the trigger signal */
  2683. #ifdef MRV_SHUT_SH_REP_EN
  2684. #define MRV_SHUT_SH_REP_EN_ONCE 0 /* 0: shutter is opened only once */
  2685. #define MRV_SHUT_SH_REP_EN_REP 1 /* 1: shutter is opened with the repetition rate of the trigger signal */
  2686. #endif /* MRV_SHUT_SH_REP_EN */
  2687. /* Slice: sh_en:*/
  2688. /* mechanical shutter enable */
  2689. /* 0: mechanical shutter function is disabled */
  2690. /* 1: mechanical shutter function is enabled */
  2691. #ifdef MRV_SHUT_SH_EN
  2692. #endif /* MRV_SHUT_SH_EN */
  2693. /*****************************************************************************/
  2694. /**
  2695. * register: isp_sh_prediv: Mech. Shutter Counter Pre-Divider (0x0004)
  2696. *
  2697. *****************************************************************************/
  2698. /* Slice: sh_pre_div:*/
  2699. /* pre-divider for mechanical shutter open_delay and open_time counter */
  2700. #ifdef MRV_SHUT_SH_PRE_DIV
  2701. #endif /* MRV_SHUT_SH_PRE_DIV */
  2702. /*****************************************************************************/
  2703. /**
  2704. * register: isp_sh_delay: Delay register (0x00000008)
  2705. *
  2706. *****************************************************************************/
  2707. /* Slice: sh_delay:*/
  2708. /* counter value for delay */
  2709. /* open_delay = (sh_delay + 1) * (fl_pre_div+1) / clk_isp */
  2710. /* sh_delay = (open_delay * clk_isp) / (sh_pre_div+1) – 1 */
  2711. #ifdef MRV_SHUT_SH_DELAY
  2712. #endif /* MRV_SHUT_SH_DELAY */
  2713. /*****************************************************************************/
  2714. /**
  2715. * register: isp_sh_time: Time register (0x0000000c)
  2716. *
  2717. *****************************************************************************/
  2718. /* Slice: sh_time:*/
  2719. /* counter value for time */
  2720. /* open_time = (sh_time + 1) * (fl_pre_div+1) / clk_isp */
  2721. /* sh_time = (open_time * clk_isp) / (sh_pre_div+1) - 1 */
  2722. #ifndef MRV_SHUT_SH_TIME
  2723. #endif /* MRV_SHUT_SH_TIME */
  2724. /*****************************************************************************/
  2725. /* Color Processing Module Registers */
  2726. /*****************************************************************************/
  2727. /*****************************************************************************/
  2728. /**
  2729. * register: c_proc_ctrl: Global control register (0x0000)
  2730. *
  2731. *****************************************************************************/
  2732. /* Slice: cproc_c_out_range:*/
  2733. /* Color processing chrominance pixel clipping range at output */
  2734. /* 0: CbCr_out clipping range 16..240 according to ITU-R BT.601 standard */
  2735. /* 1: full UV_out clipping range 0..255 */
  2736. #ifdef MRV_CPROC_CPROC_C_OUT_RANGE
  2737. #define MRV_CPROC_CPROC_C_OUT_RANGE_BT601 0 /* 0: CbCr_out clipping range 16..240 according to ITU-R BT.601 standard */
  2738. #define MRV_CPROC_CPROC_C_OUT_RANGE_FULL 1 /* 1: full UV_out clipping range 0..255 */
  2739. #endif /* MRV_CPROC_CPROC_C_OUT_RANGE */
  2740. /* Slice: cproc_y_in_range:*/
  2741. /* Color processing luminance input range (offset processing)*/
  2742. /* 0: Y_in range 64..940 according to ITU-R BT.601 standard;*/
  2743. /* offset of 64 will be subtracted from Y_in */
  2744. /* 1: Y_in full range 0..1023; no offset will be subtracted from Y_in */
  2745. #ifdef MRV_CPROC_CPROC_Y_IN_RANGE
  2746. #define MRV_CPROC_CPROC_Y_IN_RANGE_BT601 0 /* 0: Y_in range 64..940 according to ITU-R BT.601 standard */
  2747. #define MRV_CPROC_CPROC_Y_IN_RANGE_FULL 1 /* 1: Y_in full range 0..1023 */
  2748. #endif /* MRV_CPROC_CPROC_Y_IN_RANGE */
  2749. /* Slice: cproc_y_out_range:*/
  2750. /* Color processing luminance output clipping range */
  2751. /* 0: Y_out clipping range 16..235; offset of 16 is added to Y_out according to ITU-R BT.601 standard */
  2752. /* 1: Y_out clipping range 0..255; no offset is added to Y_out */
  2753. #ifdef MRV_CPROC_CPROC_Y_OUT_RANGE
  2754. #define MRV_CPROC_CPROC_Y_OUT_RANGE_BT601 0 /* 0: Y_out clipping range 16..235; offset of 16 is added to Y_out according to ITU-R BT.601 standard */
  2755. #define MRV_CPROC_CPROC_Y_OUT_RANGE_FULL 1 /* 1: Y_out clipping range 0..255; no offset is added to Y_out */
  2756. #endif /* MRV_CPROC_CPROC_Y_OUT_RANGE */
  2757. /* Slice: cproc_enable:*/
  2758. /* color processing enable */
  2759. /* 0: color processing is bypassed */
  2760. /* 2 * 10 Bit input data are truncated to 2 * 8Bit output data */
  2761. /* 1: color processing is active */
  2762. /* output data are rounded to 2 * 8Bit and clipping is active */
  2763. #ifdef MRV_CPROC_CPROC_ENABLE
  2764. #define MRV_CPROC_CPROC_ENABLE_PROCESS 1 /* 1: processing is activated */
  2765. #define MRV_CPROC_CPROC_ENABLE_BYPASS 0 /* 0: processing is deactivated, bypass mode is selected */
  2766. #endif /* MRV_CPROC_CPROC_ENABLE */
  2767. /*****************************************************************************/
  2768. /**
  2769. * register: c_proc_contrast: Color Processing contrast register (0x0004)
  2770. *
  2771. *****************************************************************************/
  2772. /* Slice: cproc_contrast:*/
  2773. /* contrast adjustment value */
  2774. /* 00H equals x 0.0 */
  2775. /* ...*/
  2776. /* 80H equals x 1.0 */
  2777. /* ...*/
  2778. /* FFH equals x 1.992 */
  2779. #ifdef MRV_CPROC_CPROC_CONTRAST
  2780. #endif /* MRV_CPROC_CPROC_CONTRAST */
  2781. /*****************************************************************************/
  2782. /**
  2783. * register: c_proc_brightness: Color Processing brightness register (0x0008)
  2784. *
  2785. *****************************************************************************/
  2786. /* Slice: cproc_brightness:*/
  2787. /* brightness adjustment value */
  2788. /* 80H equals -128 */
  2789. /* ...*/
  2790. /* 00H equals +0 */
  2791. /* ...*/
  2792. /* 7FH equals +127 */
  2793. #ifdef MRV_CPROC_CPROC_BRIGHTNESS
  2794. #endif /* MRV_CPROC_CPROC_BRIGHTNESS */
  2795. /*****************************************************************************/
  2796. /**
  2797. * register: c_proc_saturation: Color Processing saturation register (0x000c)
  2798. *
  2799. *****************************************************************************/
  2800. /* Slice: cproc_saturation:*/
  2801. /* saturation adjustment value */
  2802. /* 00H equals x 0.0 */
  2803. /* ...*/
  2804. /* 80H equals x 1.0 */
  2805. /* ...*/
  2806. /* FFH equals x 1.992 */
  2807. #ifdef MRV_CPROC_CPROC_SATURATION
  2808. #endif /* MRV_CPROC_CPROC_SATURATION */
  2809. /*****************************************************************************/
  2810. /**
  2811. * register: c_proc_hue: Color Processing hue register (0x0010)
  2812. *
  2813. *****************************************************************************/
  2814. /* Slice: cproc_hue:*/
  2815. /* hue adjustment value */
  2816. /* 80H equals -90 deg */
  2817. /* ...*/
  2818. /* 00H equals 0 deg */
  2819. /* ...*/
  2820. /* 7FH equals +87.188 deg */
  2821. #ifdef MRV_CPROC_CPROC_HUE
  2822. #endif /* MRV_CPROC_CPROC_HUE */
  2823. /*****************************************************************************/
  2824. /* Main Resizer/Scaler Registers */
  2825. /*****************************************************************************/
  2826. /*****************************************************************************/
  2827. /**
  2828. * register: mrsz_ctrl: global control register (0x00000000)
  2829. *
  2830. *****************************************************************************/
  2831. /* Slice: cfg_upd:*/
  2832. /* write 0: nothing happens */
  2833. /* write 1: update shadow registers */
  2834. /* read: always 0 */
  2835. #ifdef MRV_MRSZ_CFG_UPD
  2836. #endif /* MRV_MRSZ_CFG_UPD */
  2837. /* Slice: scale_vc_up:*/
  2838. /* 1: vertical chrominance upscaling selected */
  2839. /* 0: vertical chrominance downscaling selected */
  2840. #ifdef MRV_MRSZ_SCALE_VC_UP
  2841. #define MRV_MRSZ_SCALE_VC_UP_UPSCALE 1 /* 1: vertical chrominance upscaling selected */
  2842. #define MRV_MRSZ_SCALE_VC_UP_DOWNSCALE 0 /* 0: vertical chrominance downscaling selected */
  2843. #endif /* MRV_MRSZ_SCALE_VC_UP */
  2844. /* Slice: scale_vy_up:*/
  2845. /* 1: vertical luminance upscaling selected */
  2846. /* 0: vertical luminance downscaling selected */
  2847. #ifdef MRV_MRSZ_SCALE_VY_UP
  2848. #define MRV_MRSZ_SCALE_VY_UP_UPSCALE 1 /* 1: vertical luminance upscaling selected */
  2849. #define MRV_MRSZ_SCALE_VY_UP_DOWNSCALE 0 /* 0: vertical luminance downscaling selected */
  2850. #endif /* MRV_MRSZ_SCALE_VY_UP */
  2851. /* Slice: scale_hc_up:*/
  2852. /* 1: horizontal chrominance upscaling selected */
  2853. /* 0: horizontal chrominance downscaling selected */
  2854. #ifdef MRV_MRSZ_SCALE_HC_UP
  2855. #define MRV_MRSZ_SCALE_HC_UP_UPSCALE 1 /* 1: horizontal chrominance upscaling selected */
  2856. #define MRV_MRSZ_SCALE_HC_UP_DOWNSCALE 0 /* 0: horizontal chrominance downscaling selected */
  2857. #endif /* MRV_MRSZ_SCALE_HC_UP */
  2858. /* Slice: scale_hy_up:*/
  2859. /* 1: horizontal luminance upscaling selected */
  2860. /* 0: horizontal luminance downscaling selected */
  2861. #ifdef MRV_MRSZ_SCALE_HY_UP
  2862. #define MRV_MRSZ_SCALE_HY_UP_UPSCALE 1 /* 1: horizontal luminance upscaling selected */
  2863. #define MRV_MRSZ_SCALE_HY_UP_DOWNSCALE 0 /* 0: horizontal luminance downscaling selected */
  2864. #endif /* MRV_MRSZ_SCALE_HY_UP */
  2865. /* Slice: scale_vc_enable:*/
  2866. /* 0: bypass vertical chrominance scaling unit */
  2867. /* 1: enable vertical chrominance scaling unit */
  2868. #ifdef MRV_MRSZ_SCALE_VC_ENABLE
  2869. #define MRV_MRSZ_SCALE_VC_ENABLE_PROCESS 1 /* 1: enable vertical chrominance scaling unit */
  2870. #define MRV_MRSZ_SCALE_VC_ENABLE_BYPASS 0 /* 0: bypass vertical chrominance scaling unit */
  2871. #endif /* MRV_MRSZ_SCALE_VC_ENABLE */
  2872. /* Slice: scale_vy_enable:*/
  2873. /* 0: bypass vertical luminance scaling unit */
  2874. /* 1: enable vertical luminance scaling unit */
  2875. #ifdef MRV_MRSZ_SCALE_VY_ENABLE
  2876. #define MRV_MRSZ_SCALE_VY_ENABLE_PROCESS 1 /* 1: enable vertical luminance scaling unit */
  2877. #define MRV_MRSZ_SCALE_VY_ENABLE_BYPASS 0 /* 0: bypass vertical luminance scaling unit */
  2878. #endif /* MRV_MRSZ_SCALE_VY_ENABLE */
  2879. /* Slice: scale_hc_enable:*/
  2880. /* 0: bypass horizontal chrominance scaling unit */
  2881. /* 1: enable horizontal chrominance scaling unit */
  2882. #ifdef MRV_MRSZ_SCALE_HC_ENABLE
  2883. #define MRV_MRSZ_SCALE_HC_ENABLE_PROCESS 1 /* 1: enable horizontal chrominance scaling unit */
  2884. #define MRV_MRSZ_SCALE_HC_ENABLE_BYPASS 0 /* 0: bypass horizontal chrominance scaling unit */
  2885. #endif /* MRV_MRSZ_SCALE_HC_ENABLE */
  2886. /* Slice: scale_hy_enable:*/
  2887. /* 0: bypass horizontal luminance scaling unit */
  2888. /* 1: enable horizontal luminance scaling unit */
  2889. #ifdef MRV_MRSZ_SCALE_HY_ENABLE
  2890. #define MRV_MRSZ_SCALE_HY_ENABLE_PROCESS 1 /* 1: enable horizontal luminance scaling unit */
  2891. #define MRV_MRSZ_SCALE_HY_ENABLE_BYPASS 0 /* 0: bypass horizontal luminance scaling unit */
  2892. #endif /* MRV_MRSZ_SCALE_HY_ENABLE */
  2893. /*****************************************************************************/
  2894. /**
  2895. * register: mrsz_scale_hy: horizontal luminance scale factor register
  2896. * (0x00000004)
  2897. *
  2898. *****************************************************************************/
  2899. /* Slice: scale_hy:*/
  2900. /* This register is set to the horizontal luminance downscale factor or to */
  2901. /* the reciprocal of the horizontal luminance upscale factor */
  2902. #ifdef MRV_MRSZ_SCALE_HY
  2903. #endif /* MRV_MRSZ_SCALE_HY */
  2904. /*****************************************************************************/
  2905. /**
  2906. * register: mrsz_scale_hcb: horizontal Cb scale factor register (0x00000008)
  2907. *
  2908. *****************************************************************************/
  2909. /* Slice: scale_hcb:*/
  2910. /* This register is set to the horizontal Cb downscale factor or to the */
  2911. /* reciprocal of the horizontal Cb upscale factor */
  2912. #ifdef MRV_MRSZ_SCALE_HCB
  2913. #endif /* MRV_MRSZ_SCALE_HCB */
  2914. /*****************************************************************************/
  2915. /**
  2916. * register: mrsz_scale_hcr: horizontal Cr scale factor register (0x0000000c)
  2917. *
  2918. *****************************************************************************/
  2919. /* Slice: scale_hcr:*/
  2920. /* This register is set to the horizontal Cr downscale factor or to the */
  2921. /* reciprocal of the horizontal Cr upscale factor */
  2922. #ifdef MRV_MRSZ_SCALE_HCR
  2923. #endif /* MRV_MRSZ_SCALE_HCR */
  2924. /*****************************************************************************/
  2925. /**
  2926. * register: mrsz_scale_vy: vertical luminance scale factor register (0x00000010)
  2927. *
  2928. *****************************************************************************/
  2929. /* Slice: scale_vy:*/
  2930. /* This register is set to the vertical luminance downscale factor or to the */
  2931. /* reciprocal of the vertical luminance upscale factor */
  2932. #ifdef MRV_MRSZ_SCALE_VY
  2933. #endif /* MRV_MRSZ_SCALE_VY */
  2934. /*****************************************************************************/
  2935. /**
  2936. * register: mrsz_scale_vc: vertical chrominance scale factor register (0x00000014)
  2937. *
  2938. *****************************************************************************/
  2939. /* Slice: scale_vc:*/
  2940. /* This register is set to the vertical chrominance downscale factor or to the */
  2941. /* reciprocal of the vertical chrominance upscale factor */
  2942. #ifdef MRV_MRSZ_SCALE_VC
  2943. #endif /* MRV_MRSZ_SCALE_VC */
  2944. /*****************************************************************************/
  2945. /**
  2946. * register: mrsz_phase_hy: horizontal luminance phase register (0x00000018)
  2947. *
  2948. *****************************************************************************/
  2949. /* Slice: phase_hy:*/
  2950. /* This register is set to the horizontal luminance phase offset */
  2951. #ifdef MRV_MRSZ_PHASE_HY
  2952. #endif /* MRV_MRSZ_PHASE_HY */
  2953. /*****************************************************************************/
  2954. /**
  2955. * register: mrsz_phase_hc: horizontal chrominance phase register (0x0000001c)
  2956. *
  2957. *****************************************************************************/
  2958. /* Slice: phase_hc:*/
  2959. /* This register is set to the horizontal chrominance phase offset */
  2960. #ifdef MRV_MRSZ_PHASE_HC
  2961. #endif /* MRV_MRSZ_PHASE_HC */
  2962. /*****************************************************************************/
  2963. /**
  2964. * register: mrsz_phase_vy: vertical luminance phase register (0x00000020)
  2965. *
  2966. *****************************************************************************/
  2967. /* Slice: phase_vy:*/
  2968. /* This register is set to the vertical luminance phase offset */
  2969. #ifdef MRV_MRSZ_PHASE_VY
  2970. #endif /* MRV_MRSZ_PHASE_VY */
  2971. /*****************************************************************************/
  2972. /**
  2973. * register: mrsz_phase_vc: vertical chrominance phase register (0x00000024)
  2974. *
  2975. *****************************************************************************/
  2976. /* Slice: phase_vc:*/
  2977. /* This register is set to the vertical chrominance phase offset */
  2978. #ifdef MRV_MRSZ_PHASE_VC
  2979. #endif /* MRV_MRSZ_PHASE_VC */
  2980. /*****************************************************************************/
  2981. /**
  2982. * register: mrsz_scale_lut_addr: Address pointer of up-scaling look up table
  2983. * (0x00000028)
  2984. *
  2985. *****************************************************************************/
  2986. /* Slice: scale_lut_addr:*/
  2987. /* Pointer to entry of lookup table */
  2988. #ifdef MRV_MRSZ_SCALE_LUT_ADDR
  2989. #endif /* MRV_MRSZ_SCALE_LUT_ADDR */
  2990. /*****************************************************************************/
  2991. /**
  2992. * register: mrsz_scale_lut: Entry of up-scaling look up table (0x0000002c)
  2993. *
  2994. *****************************************************************************/
  2995. /* Slice: scale_lut:*/
  2996. /* Entry of lookup table at position scale_lut_addr. The lookup table must be */
  2997. /* filled with appropriate values before the up-scaling functionality can be */
  2998. /* used.*/
  2999. #ifdef MRV_MRSZ_SCALE_LUT
  3000. #endif /* MRV_MRSZ_SCALE_LUT */
  3001. /*****************************************************************************/
  3002. /**
  3003. * register: mrsz_ctrl_shd: global control shadow register (0x0030)
  3004. *
  3005. *****************************************************************************/
  3006. /* Slice: scale_vc_up_shd:*/
  3007. /* 1: vertical chrominance upscaling selected */
  3008. /* 0: vertical chrominance downscaling selected */
  3009. #ifdef MRV_MRSZ_SCALE_VC_UP_SHD
  3010. #define MRV_MRSZ_SCALE_VC_UP_SHD_UPSCALE 1 /* 1: vertical chrominance upscaling selected */
  3011. #define MRV_MRSZ_SCALE_VC_UP_SHD_DOWNSCALE 0 /* 0: vertical chrominance downscaling selected */
  3012. #endif /* MRV_MRSZ_SCALE_VC_UP_SHD */
  3013. /* Slice: scale_vy_up_shd:*/
  3014. /* 1: vertical luminance upscaling selected */
  3015. /* 0: vertical luminance downscaling selected */
  3016. #ifdef MRV_MRSZ_SCALE_VY_UP_SHD
  3017. #define MRV_MRSZ_SCALE_VY_UP_SHD_UPSCALE 1 /* 1: vertical luminance upscaling selected */
  3018. #define MRV_MRSZ_SCALE_VY_UP_SHD_DOWNSCALE 0 /* 0: vertical luminance downscaling selected */
  3019. #endif /* MRV_MRSZ_SCALE_VY_UP_SHD */
  3020. /* Slice: scale_hc_up_shd:*/
  3021. /* 1: horizontal chrominance upscaling selected */
  3022. /* 0: horizontal chrominance downscaling selected */
  3023. #ifdef MRV_MRSZ_SCALE_HC_UP_SHD
  3024. #define MRV_MRSZ_SCALE_HC_UP_SHD_UPSCALE 1 /* 1: horizontal chrominance upscaling selected */
  3025. #define MRV_MRSZ_SCALE_HC_UP_SHD_DOWNSCALE 0 /* 0: horizontal chrominance downscaling selected */
  3026. #endif /* MRV_MRSZ_SCALE_HC_UP_SHD */
  3027. /* Slice: scale_hy_up_shd:*/
  3028. /* 1: horizontal luminance upscaling selected */
  3029. /* 0: horizontal luminance downscaling selected */
  3030. #ifdef MRV_MRSZ_SCALE_HY_UP_SHD
  3031. #define MRV_MRSZ_SCALE_HY_UP_SHD_UPSCALE 1 /* 1: horizontal luminance upscaling selected */
  3032. #define MRV_MRSZ_SCALE_HY_UP_SHD_DOWNSCALE 0 /* 0: horizontal luminance downscaling selected */
  3033. #endif /* MRV_MRSZ_SCALE_HY_UP_SHD */
  3034. /* Slice: scale_vc_enable_shd:*/
  3035. /* 0: bypass vertical chrominance scaling unit */
  3036. /* 1: enable vertical chrominance scaling unit */
  3037. #ifdef MRV_MRSZ_SCALE_VC_ENABLE_SHD
  3038. #define MRV_MRSZ_SCALE_VC_ENABLE_SHD_PROCESS 1 /* 1: enable vertical chrominance scaling unit */
  3039. #define MRV_MRSZ_SCALE_VC_ENABLE_SHD_BYPASS 0 /* 0: bypass vertical chrominance scaling unit */
  3040. #endif /* MRV_MRSZ_SCALE_VC_ENABLE_SHD */
  3041. /* Slice: scale_vy_enable_shd:*/
  3042. /* 0: bypass vertical luminance scaling unit */
  3043. /* 1: enable vertical luminance scaling unit */
  3044. #ifdef MRV_MRSZ_SCALE_VY_ENABLE_SHD
  3045. #define MRV_MRSZ_SCALE_VY_ENABLE_SHD_PROCESS 1 /* 1: enable vertical luminance scaling unit */
  3046. #define MRV_MRSZ_SCALE_VY_ENABLE_SHD_BYPASS 0 /* 0: bypass vertical luminance scaling unit */
  3047. #endif /* MRV_MRSZ_SCALE_VY_ENABLE_SHD */
  3048. /* Slice: scale_hc_enable_shd:*/
  3049. /* 0: bypass horizontal chrominance scaling unit */
  3050. /* 1: enable horizontal chrominance scaling unit */
  3051. #ifdef MRV_MRSZ_SCALE_HC_ENABLE_SHD
  3052. #define MRV_MRSZ_SCALE_HC_ENABLE_SHD_PROCESS 1 /* 1: enable horizontal chrominance scaling unit */
  3053. #define MRV_MRSZ_SCALE_HC_ENABLE_SHD_BYPASS 0 /* 0: bypass horizontal chrominance scaling unit */
  3054. #endif /* MRV_MRSZ_SCALE_HC_ENABLE_SHD */
  3055. /* Slice: scale_hy_enable_shd:*/
  3056. /* 0: bypass horizontal luminance scaling unit */
  3057. /* 1: enable horizontal luminance scaling unit */
  3058. #ifdef MRV_MRSZ_SCALE_HY_ENABLE_SHD
  3059. #define MRV_MRSZ_SCALE_HY_ENABLE_SHD_PROCESS 1 /* 1: enable horizontal luminance scaling unit */
  3060. #define MRV_MRSZ_SCALE_HY_ENABLE_SHD_BYPASS 0 /* 0: bypass horizontal luminance scaling unit */
  3061. #endif /* MRV_MRSZ_SCALE_HY_ENABLE_SHD */
  3062. /*****************************************************************************/
  3063. /**
  3064. * register: mrsz_scale_hy_shd: horizontal luminance scale factor shadow
  3065. * register (0x00000034)
  3066. *
  3067. *****************************************************************************/
  3068. /* Slice: scale_hy_shd:*/
  3069. /* This register is set to the horizontal luminance downscale factor or to the */
  3070. /* reciprocal of the horizontal luminance upscale factor */
  3071. #ifdef MRV_MRSZ_SCALE_HY_SHD
  3072. #endif /* MRV_MRSZ_SCALE_HY_SHD */
  3073. /*****************************************************************************/
  3074. /**
  3075. * register: mrsz_scale_hcb_shd: horizontal Cb scale factor shadow register
  3076. * (0x00000038)
  3077. *
  3078. *****************************************************************************/
  3079. /* Slice: scale_hcb_shd:*/
  3080. /* This register is set to the horizontal Cb downscale factor or to the */
  3081. /* reciprocal of the horizontal Cb upscale factor */
  3082. #ifdef MRV_MRSZ_SCALE_HCB_SHD
  3083. #endif /* MRV_MRSZ_SCALE_HCB_SHD */
  3084. /*****************************************************************************/
  3085. /**
  3086. * register: mrsz_scale_hcr_shd: horizontal Cr scale factor shadow register
  3087. * (0x0000003c)
  3088. *
  3089. *****************************************************************************/
  3090. /* Slice: scale_hcr_shd:*/
  3091. /* This register is set to the horizontal Cr downscale factor or to the */
  3092. /* reciprocal of the horizontal Cr upscale factor */
  3093. #ifdef MRV_MRSZ_SCALE_HCR_SHD
  3094. #endif /* MRV_MRSZ_SCALE_HCR_SHD */
  3095. /*****************************************************************************/
  3096. /**
  3097. * register: mrsz_scale_vy_shd: vertical luminance scale factor shadow register
  3098. * (0x00000040)
  3099. *
  3100. *****************************************************************************/
  3101. /* Slice: scale_vy_shd:*/
  3102. /* This register is set to the vertical luminance downscale factor or to the */
  3103. /* reciprocal of the vertical luminance upscale factor */
  3104. #ifdef MRV_MRSZ_SCALE_VY_SHD
  3105. #endif /* MRV_MRSZ_SCALE_VY_SHD */
  3106. /*****************************************************************************/
  3107. /**
  3108. * register: mrsz_scale_vc_shd: vertical chrominance scale factor shadow
  3109. * register (0x00000044)
  3110. *
  3111. *****************************************************************************/
  3112. /* Slice: scale_vc_shd:*/
  3113. /* This register is set to the vertical chrominance downscale factor or to */
  3114. /* the reciprocal of the vertical chrominance upscale factor */
  3115. #ifdef MRV_MRSZ_SCALE_VC_SHD
  3116. #endif /* MRV_MRSZ_SCALE_VC_SHD */
  3117. /*****************************************************************************/
  3118. /**
  3119. * register: mrsz_phase_hy_shd: horizontal luminance phase shadow register
  3120. * (0x00000048)
  3121. *
  3122. *****************************************************************************/
  3123. /* Slice: phase_hy_shd:*/
  3124. /* This register is set to the horizontal luminance phase offset */
  3125. #ifdef MRV_MRSZ_PHASE_HY_SHD
  3126. #endif /* MRV_MRSZ_PHASE_HY_SHD */
  3127. /*****************************************************************************/
  3128. /**
  3129. * register: mrsz_phase_hc_shd: horizontal chrominance phase shadow register
  3130. * (0x0000004c)
  3131. *
  3132. *****************************************************************************/
  3133. /* Slice: phase_hc_shd:*/
  3134. /* This register is set to the horizontal chrominance phase offset */
  3135. #ifdef MRV_MRSZ_PHASE_HC_SHD
  3136. #endif /* MRV_MRSZ_PHASE_HC_SHD */
  3137. /*****************************************************************************/
  3138. /**
  3139. * register: mrsz_phase_vy_shd: vertical luminance phase shadow register
  3140. * (0x00000050)
  3141. *
  3142. *****************************************************************************/
  3143. /* Slice: phase_vy_shd:*/
  3144. /* This register is set to the vertical luminance phase offset */
  3145. #ifdef MRV_MRSZ_PHASE_VY_SHD
  3146. #endif /* MRV_MRSZ_PHASE_VY_SHD */
  3147. /*****************************************************************************/
  3148. /**
  3149. * register: mrsz_phase_vc_shd: vertical chrominance phase shadow register
  3150. * (0x00000054)
  3151. *
  3152. *****************************************************************************/
  3153. /* Slice: phase_vc_shd:*/
  3154. /* This register is set to the vertical chrominance phase offset */
  3155. #ifdef MRV_MRSZ_PHASE_VC_SHD
  3156. #endif /* MRV_MRSZ_PHASE_VC_SHD */
  3157. /*****************************************************************************/
  3158. /* Self Resizer/Scaler Registers */
  3159. /*****************************************************************************/
  3160. /*****************************************************************************/
  3161. /**
  3162. * register: srsz_ctrl: global control register (0x00000000)
  3163. *
  3164. *****************************************************************************/
  3165. /* Slice: cfg_upd:*/
  3166. /* write 0: nothing happens */
  3167. /* write 1: update shadow registers */
  3168. /* read: always 0 */
  3169. #ifdef MRV_SRSZ_CFG_UPD
  3170. #endif /* MRV_SRSZ_CFG_UPD */
  3171. /* Slice: scale_vc_up:*/
  3172. /* 1: vertical chrominance upscaling selected */
  3173. /* 0: vertical chrominance downscaling selected */
  3174. #ifdef MRV_SRSZ_SCALE_VC_UP
  3175. #define MRV_SRSZ_SCALE_VC_UP_UPSCALE 1 /* 1: vertical chrominance upscaling selected */
  3176. #define MRV_SRSZ_SCALE_VC_UP_DOWNSCALE 0 /* 0: vertical chrominance downscaling selected */
  3177. #endif /* MRV_SRSZ_SCALE_VC_UP */
  3178. /* Slice: scale_vy_up:*/
  3179. /* 1: vertical luminance upscaling selected */
  3180. /* 0: vertical luminance downscaling selected */
  3181. #ifdef MRV_SRSZ_SCALE_VY_UP
  3182. #define MRV_SRSZ_SCALE_VY_UP_UPSCALE 1 /* 1: vertical luminance upscaling selected */
  3183. #define MRV_SRSZ_SCALE_VY_UP_DOWNSCALE 0 /* 0: vertical luminance downscaling selected */
  3184. #endif /* MRV_SRSZ_SCALE_VY_UP */
  3185. /* Slice: scale_hc_up:*/
  3186. /* 1: horizontal chrominance upscaling selected */
  3187. /* 0: horizontal chrominance downscaling selected */
  3188. #ifdef MRV_SRSZ_SCALE_HC_UP
  3189. #define MRV_SRSZ_SCALE_HC_UP_UPSCALE 1 /* 1: horizontal chrominance upscaling selected */
  3190. #define MRV_SRSZ_SCALE_HC_UP_DOWNSCALE 0 /* 0: horizontal chrominance downscaling selected */
  3191. #endif /* MRV_SRSZ_SCALE_HC_UP */
  3192. /* Slice: scale_hy_up:*/
  3193. /* 1: horizontal luminance upscaling selected */
  3194. /* 0: horizontal luminance downscaling selected */
  3195. #ifdef MRV_SRSZ_SCALE_HY_UP
  3196. #define MRV_SRSZ_SCALE_HY_UP_UPSCALE 1 /* 1: horizontal luminance upscaling selected */
  3197. #define MRV_SRSZ_SCALE_HY_UP_DOWNSCALE 0 /* 0: horizontal luminance downscaling selected */
  3198. #endif /* MRV_SRSZ_SCALE_HY_UP */
  3199. /* Slice: scale_vc_enable:*/
  3200. /* 0: bypass vertical chrominance scaling unit */
  3201. /* 1: enable vertical chrominance scaling unit */
  3202. #ifdef MRV_SRSZ_SCALE_VC_ENABLE
  3203. #define MRV_SRSZ_SCALE_VC_ENABLE_PROCESS 1 /* 1: enable vertical chrominance scaling unit */
  3204. #define MRV_SRSZ_SCALE_VC_ENABLE_BYPASS 0 /* 0: bypass vertical chrominance scaling unit */
  3205. #endif /* MRV_SRSZ_SCALE_VC_ENABLE */
  3206. /* Slice: scale_vy_enable:*/
  3207. /* 0: bypass vertical luminance scaling unit */
  3208. /* 1: enable vertical luminance scaling unit */
  3209. #ifdef MRV_SRSZ_SCALE_VY_ENABLE
  3210. #define MRV_SRSZ_SCALE_VY_ENABLE_PROCESS 1 /* 1: enable vertical luminance scaling unit */
  3211. #define MRV_SRSZ_SCALE_VY_ENABLE_BYPASS 0 /* 0: bypass vertical luminance scaling unit */
  3212. #endif /* MRV_SRSZ_SCALE_VY_ENABLE */
  3213. /* Slice: scale_hc_enable:*/
  3214. /* 0: bypass horizontal chrominance scaling unit */
  3215. /* 1: enable horizontal chrominance scaling unit */
  3216. #ifdef MRV_SRSZ_SCALE_HC_ENABLE
  3217. #define MRV_SRSZ_SCALE_HC_ENABLE_PROCESS 1 /* 1: enable horizontal chrominance scaling unit */
  3218. #define MRV_SRSZ_SCALE_HC_ENABLE_BYPASS 0 /* 0: bypass horizontal chrominance scaling unit */
  3219. #endif /* MRV_SRSZ_SCALE_HC_ENABLE */
  3220. /* Slice: scale_hy_enable:*/
  3221. /* 0: bypass horizontal luminance scaling unit */
  3222. /* 1: enable horizontal luminance scaling unit */
  3223. #ifdef MRV_SRSZ_SCALE_HY_ENABLE
  3224. #define MRV_SRSZ_SCALE_HY_ENABLE_PROCESS 1 /* 1: enable horizontal luminance scaling unit */
  3225. #define MRV_SRSZ_SCALE_HY_ENABLE_BYPASS 0 /* 0: bypass horizontal luminance scaling unit */
  3226. #endif /* MRV_SRSZ_SCALE_HY_ENABLE */
  3227. /*****************************************************************************/
  3228. /**
  3229. * register: srsz_scale_hy: horizontal luminance scale factor register
  3230. * (0x00000004)
  3231. *
  3232. *****************************************************************************/
  3233. /* Slice: scale_hy:*/
  3234. /* This register is set to the horizontal luminance downscale factor or to */
  3235. /* the reciprocal of the horizontal luminance upscale factor */
  3236. #ifdef MRV_SRSZ_SCALE_HY
  3237. #endif /* MRV_SRSZ_SCALE_HY */
  3238. /*****************************************************************************/
  3239. /**
  3240. * register: srsz_scale_hcb: horizontal Cb scale factor register (0x00000008)
  3241. *
  3242. *****************************************************************************/
  3243. /* Slice: scale_hcb:*/
  3244. /* This register is set to the horizontal Cb downscale factor or to the */
  3245. /* reciprocal of the horizontal Cb upscale factor */
  3246. #ifdef MRV_SRSZ_SCALE_HCB
  3247. #endif /* MRV_SRSZ_SCALE_HCB */
  3248. /*****************************************************************************/
  3249. /**
  3250. * register: srsz_scale_hcr: horizontal Cr scale factor register (0x0000000c)
  3251. *
  3252. *****************************************************************************/
  3253. /* Slice: scale_hcr:*/
  3254. /* This register is set to the horizontal Cr downscale factor or to the */
  3255. /* reciprocal of the horizontal Cr upscale factor */
  3256. #ifdef MRV_SRSZ_SCALE_HCR
  3257. #endif /* MRV_SRSZ_SCALE_HCR */
  3258. /*****************************************************************************/
  3259. /**
  3260. * register: srsz_scale_vy: vertical luminance scale factor register (0x00000010)
  3261. *
  3262. *****************************************************************************/
  3263. /* Slice: scale_vy:*/
  3264. /* This register is set to the vertical luminance downscale factor or to the */
  3265. /* reciprocal of the vertical luminance upscale factor */
  3266. #ifdef MRV_SRSZ_SCALE_VY
  3267. #endif /* MRV_SRSZ_SCALE_VY */
  3268. /*****************************************************************************/
  3269. /**
  3270. * register: srsz_scale_vc: vertical chrominance scale factor register (0x00000014)
  3271. *
  3272. *****************************************************************************/
  3273. /* Slice: scale_vc:*/
  3274. /* This register is set to the vertical chrominance downscale factor or to the */
  3275. /* reciprocal of the vertical chrominance upscale factor */
  3276. #ifdef MRV_SRSZ_SCALE_VC
  3277. #endif /* MRV_SRSZ_SCALE_VC */
  3278. /*****************************************************************************/
  3279. /**
  3280. * register: srsz_phase_hy: horizontal luminance phase register (0x00000018)
  3281. *
  3282. *****************************************************************************/
  3283. /* Slice: phase_hy:*/
  3284. /* This register is set to the horizontal luminance phase offset */
  3285. #ifdef MRV_SRSZ_PHASE_HY
  3286. #endif /* MRV_SRSZ_PHASE_HY */
  3287. /*****************************************************************************/
  3288. /**
  3289. * register: srsz_phase_hc: horizontal chrominance phase register (0x0000001c)
  3290. *
  3291. *****************************************************************************/
  3292. /* Slice: phase_hc:*/
  3293. /* This register is set to the horizontal chrominance phase offset */
  3294. #ifdef MRV_SRSZ_PHASE_HC
  3295. #endif /* MRV_SRSZ_PHASE_HC */
  3296. /*****************************************************************************/
  3297. /**
  3298. * register: srsz_phase_vy: vertical luminance phase register (0x00000020)
  3299. *
  3300. *****************************************************************************/
  3301. /* Slice: phase_vy:*/
  3302. /* This register is set to the vertical luminance phase offset */
  3303. #ifdef MRV_SRSZ_PHASE_VY
  3304. #endif /* MRV_SRSZ_PHASE_VY */
  3305. /*****************************************************************************/
  3306. /**
  3307. * register: srsz_phase_vc: vertical chrominance phase register (0x00000024)
  3308. *
  3309. *****************************************************************************/
  3310. /* Slice: phase_vc:*/
  3311. /* This register is set to the vertical chrominance phase offset */
  3312. #ifdef MRV_SRSZ_PHASE_VC
  3313. #endif /* MRV_SRSZ_PHASE_VC */
  3314. /*****************************************************************************/
  3315. /**
  3316. * register: srsz_scale_lut_addr: Address pointer of up-scaling look up table
  3317. * (0x00000028)
  3318. *
  3319. *****************************************************************************/
  3320. /* Slice: scale_lut_addr:*/
  3321. /* Pointer to entry of lookup table */
  3322. #ifdef MRV_SRSZ_SCALE_LUT_ADDR
  3323. #endif /* MRV_SRSZ_SCALE_LUT_ADDR */
  3324. /*****************************************************************************/
  3325. /**
  3326. * register: srsz_scale_lut: Entry of up-scaling look up table (0x0000002c)
  3327. *
  3328. *****************************************************************************/
  3329. /* Slice: scale_lut:*/
  3330. /* Entry of lookup table at position scale_lut_addr. The lookup table must be */
  3331. /* filled with appropriate values before the up-scaling functionality can be */
  3332. /* used.*/
  3333. #ifdef MRV_SRSZ_SCALE_LUT
  3334. #endif /* MRV_SRSZ_SCALE_LUT */
  3335. /*****************************************************************************/
  3336. /**
  3337. * register: srsz_ctrl_shd: global control shadow register (0x0030)
  3338. *
  3339. *****************************************************************************/
  3340. /* Slice: scale_vc_up_shd:*/
  3341. /* 1: vertical chrominance upscaling selected */
  3342. /* 0: vertical chrominance downscaling selected */
  3343. #ifdef MRV_SRSZ_SCALE_VC_UP_SHD
  3344. #define MRV_SRSZ_SCALE_VC_UP_SHD_UPSCALE 1 /* 1: vertical chrominance upscaling selected */
  3345. #define MRV_SRSZ_SCALE_VC_UP_SHD_DOWNSCALE 0 /* 0: vertical chrominance downscaling selected */
  3346. #endif /* MRV_SRSZ_SCALE_VC_UP_SHD */
  3347. /* Slice: scale_vy_up_shd:*/
  3348. /* 1: vertical luminance upscaling selected */
  3349. /* 0: vertical luminance downscaling selected */
  3350. #ifdef MRV_SRSZ_SCALE_VY_UP_SHD
  3351. #define MRV_SRSZ_SCALE_VY_UP_SHD_UPSCALE 1 /* 1: vertical luminance upscaling selected */
  3352. #define MRV_SRSZ_SCALE_VY_UP_SHD_DOWNSCALE 0 /* 0: vertical luminance downscaling selected */
  3353. #endif /* MRV_SRSZ_SCALE_VY_UP_SHD */
  3354. /* Slice: scale_hc_up_shd:*/
  3355. /* 1: horizontal chrominance upscaling selected */
  3356. /* 0: horizontal chrominance downscaling selected */
  3357. #ifdef MRV_SRSZ_SCALE_HC_UP_SHD
  3358. #define MRV_SRSZ_SCALE_HC_UP_SHD_UPSCALE 1 /* 1: horizontal chrominance upscaling selected */
  3359. #define MRV_SRSZ_SCALE_HC_UP_SHD_DOWNSCALE 0 /* 0: horizontal chrominance downscaling selected */
  3360. #endif /* MRV_SRSZ_SCALE_HC_UP_SHD */
  3361. /* Slice: scale_hy_up_shd:*/
  3362. /* 1: horizontal luminance upscaling selected */
  3363. /* 0: horizontal luminance downscaling selected */
  3364. #ifdef MRV_SRSZ_SCALE_HY_UP_SHD
  3365. #define MRV_SRSZ_SCALE_HY_UP_SHD_UPSCALE 1 /* 1: horizontal luminance upscaling selected */
  3366. #define MRV_SRSZ_SCALE_HY_UP_SHD_DOWNSCALE 0 /* 0: horizontal luminance downscaling selected */
  3367. #endif /* MRV_SRSZ_SCALE_HY_UP_SHD */
  3368. /* Slice: scale_vc_enable_shd:*/
  3369. /* 0: bypass vertical chrominance scaling unit */
  3370. /* 1: enable vertical chrominance scaling unit */
  3371. #ifdef MRV_SRSZ_SCALE_VC_ENABLE_SHD
  3372. #define MRV_SRSZ_SCALE_VC_ENABLE_SHD_PROCESS 1 /* 1: enable vertical chrominance scaling unit */
  3373. #define MRV_SRSZ_SCALE_VC_ENABLE_SHD_BYPASS 0 /* 0: bypass vertical chrominance scaling unit */
  3374. #endif /* MRV_SRSZ_SCALE_VC_ENABLE_SHD */
  3375. /* Slice: scale_vy_enable_shd:*/
  3376. /* 0: bypass vertical luminance scaling unit */
  3377. /* 1: enable vertical luminance scaling unit */
  3378. #ifdef MRV_SRSZ_SCALE_VY_ENABLE_SHD
  3379. #define MRV_SRSZ_SCALE_VY_ENABLE_SHD_PROCESS 1 /* 1: enable vertical luminance scaling unit */
  3380. #define MRV_SRSZ_SCALE_VY_ENABLE_SHD_BYPASS 0 /* 0: bypass vertical luminance scaling unit */
  3381. #endif /* MRV_SRSZ_SCALE_VY_ENABLE_SHD */
  3382. /* Slice: scale_hc_enable_shd:*/
  3383. /* 0: bypass horizontal chrominance scaling unit */
  3384. /* 1: enable horizontal chrominance scaling unit */
  3385. #ifdef MRV_SRSZ_SCALE_HC_ENABLE_SHD
  3386. #define MRV_SRSZ_SCALE_HC_ENABLE_SHD_PROCESS 1 /* 1: enable horizontal chrominance scaling unit */
  3387. #define MRV_SRSZ_SCALE_HC_ENABLE_SHD_BYPASS 0 /* 0: bypass horizontal chrominance scaling unit */
  3388. #endif /* MRV_SRSZ_SCALE_HC_ENABLE_SHD */
  3389. /* Slice: scale_hy_enable_shd:*/
  3390. /* 0: bypass horizontal luminance scaling unit */
  3391. /* 1: enable horizontal luminance scaling unit */
  3392. #ifdef MRV_SRSZ_SCALE_HY_ENABLE_SHD
  3393. #define MRV_SRSZ_SCALE_HY_ENABLE_SHD_PROCESS 1 /* 1: enable horizontal luminance scaling unit */
  3394. #define MRV_SRSZ_SCALE_HY_ENABLE_SHD_BYPASS 0 /* 0: bypass horizontal luminance scaling unit */
  3395. #endif /* MRV_SRSZ_SCALE_HY_ENABLE_SHD */
  3396. /*****************************************************************************/
  3397. /**
  3398. * register: srsz_scale_hy_shd: horizontal luminance scale factor shadow
  3399. * register (0x00000034)
  3400. *
  3401. *****************************************************************************/
  3402. /* Slice: scale_hy_shd:*/
  3403. /* This register is set to the horizontal luminance downscale factor or to the */
  3404. /* reciprocal of the horizontal luminance upscale factor */
  3405. #ifdef MRV_SRSZ_SCALE_HY_SHD
  3406. #endif /* MRV_SRSZ_SCALE_HY_SHD */
  3407. /*****************************************************************************/
  3408. /**
  3409. * register: srsz_scale_hcb_shd: horizontal Cb scale factor shadow register
  3410. * (0x00000038)
  3411. *
  3412. *****************************************************************************/
  3413. /* Slice: scale_hcb_shd:*/
  3414. /* This register is set to the horizontal Cb downscale factor or to the */
  3415. /* reciprocal of the horizontal Cb upscale factor */
  3416. #ifdef MRV_SRSZ_SCALE_HCB_SHD
  3417. #endif /* MRV_SRSZ_SCALE_HCB_SHD */
  3418. /*****************************************************************************/
  3419. /**
  3420. * register: srsz_scale_hcr_shd: horizontal Cr scale factor shadow register
  3421. * (0x0000003c)
  3422. *
  3423. *****************************************************************************/
  3424. /* Slice: scale_hcr_shd:*/
  3425. /* This register is set to the horizontal Cr downscale factor or to the */
  3426. /* reciprocal of the horizontal Cr upscale factor */
  3427. #ifdef MRV_SRSZ_SCALE_HCR_SHD
  3428. #endif /* MRV_SRSZ_SCALE_HCR_SHD */
  3429. /*****************************************************************************/
  3430. /**
  3431. * register: srsz_scale_vy_shd: vertical luminance scale factor shadow register
  3432. * (0x00000040)
  3433. *
  3434. *****************************************************************************/
  3435. /* Slice: scale_vy_shd:*/
  3436. /* This register is set to the vertical luminance downscale factor or to the */
  3437. /* reciprocal of the vertical luminance upscale factor */
  3438. #ifdef MRV_SRSZ_SCALE_VY_SHD
  3439. #endif /* MRV_SRSZ_SCALE_VY_SHD */
  3440. /*****************************************************************************/
  3441. /**
  3442. * register: srsz_scale_vc_shd: vertical chrominance scale factor shadow
  3443. * register (0x00000044)
  3444. *
  3445. *****************************************************************************/
  3446. /* Slice: scale_vc_shd:*/
  3447. /* This register is set to the vertical chrominance downscale factor or to */
  3448. /* the reciprocal of the vertical chrominance upscale factor */
  3449. #ifdef MRV_SRSZ_SCALE_VC_SHD
  3450. #endif /* MRV_SRSZ_SCALE_VC_SHD */
  3451. /*****************************************************************************/
  3452. /**
  3453. * register: srsz_phase_hy_shd: horizontal luminance phase shadow register
  3454. * (0x00000048)
  3455. *
  3456. *****************************************************************************/
  3457. /* Slice: phase_hy_shd:*/
  3458. /* This register is set to the horizontal luminance phase offset */
  3459. #ifdef MRV_SRSZ_PHASE_HY_SHD
  3460. #endif /* MRV_SRSZ_PHASE_HY_SHD */
  3461. /*****************************************************************************/
  3462. /**
  3463. * register: srsz_phase_hc_shd: horizontal chrominance phase shadow register
  3464. * (0x0000004c)
  3465. *
  3466. *****************************************************************************/
  3467. /* Slice: phase_hc_shd:*/
  3468. /* This register is set to the horizontal chrominance phase offset */
  3469. #ifdef MRV_SRSZ_PHASE_HC_SHD
  3470. #endif /* MRV_SRSZ_PHASE_HC_SHD */
  3471. /*****************************************************************************/
  3472. /**
  3473. * register: srsz_phase_vy_shd: vertical luminance phase shadow register
  3474. * (0x00000050)
  3475. *
  3476. *****************************************************************************/
  3477. /* Slice: phase_vy_shd:*/
  3478. /* This register is set to the vertical luminance phase offset */
  3479. #ifdef MRV_SRSZ_PHASE_VY_SHD
  3480. #endif /* MRV_SRSZ_PHASE_VY_SHD */
  3481. /*****************************************************************************/
  3482. /**
  3483. * register: srsz_phase_vc_shd: vertical chrominance phase shadow register
  3484. * (0x00000054)
  3485. *
  3486. *****************************************************************************/
  3487. /* Slice: phase_vc_shd:*/
  3488. /* This register is set to the vertical chrominance phase offset */
  3489. #ifdef MRV_SRSZ_PHASE_VC_SHD
  3490. #endif /* MRV_SRSZ_PHASE_VC_SHD */
  3491. /*****************************************************************************/
  3492. /* Memory Interface Registers */
  3493. /*****************************************************************************/
  3494. /*****************************************************************************/
  3495. /**
  3496. * register: mi_ctrl: Global control register (0x0000)
  3497. *
  3498. *****************************************************************************/
  3499. /* Slice: sp_output_format:*/
  3500. /* Selects output format of self picture. For possible restrictions see sub-*/
  3501. /* chapter "Picture Orientation" in chapter "Self Path Output Programming".*/
  3502. /**/
  3503. /* 111: reserved */
  3504. /* 110: RGB 888 */
  3505. /* 101: RGB 666 */
  3506. /* 100: RGB 565 */
  3507. /**/
  3508. /* 011: YCbCr 4:4:4 */
  3509. /* 010: YCbCr 4:2:2 */
  3510. /* 001: YCbCr 4:2:0 */
  3511. /* 000: YCbCr 4:0:0 */
  3512. /**/
  3513. /* Note:*/
  3514. /* - Programmed value becomes effective immediately. So write to the */
  3515. /* register only if no picture data is sent to the self path.*/
  3516. /* - for RGB output format the SP input format must be YCbCr 4:2:2 */
  3517. #ifdef MRV_MI_SP_OUTPUT_FORMAT
  3518. #define MRV_MI_SP_OUTPUT_FORMAT_RGB888 6 /* 110: RGB 888 */
  3519. #define MRV_MI_SP_OUTPUT_FORMAT_RGB666 5 /* 101: RGB 666 */
  3520. #define MRV_MI_SP_OUTPUT_FORMAT_RGB565 4 /* 100: RGB 565 */
  3521. #define MRV_MI_SP_OUTPUT_FORMAT_YUV444 3 /* 011: YCbCr 4:4:4 */
  3522. #define MRV_MI_SP_OUTPUT_FORMAT_YUV422 2 /* 010: YCbCr 4:2:2 */
  3523. #define MRV_MI_SP_OUTPUT_FORMAT_YUV420 1 /* 001: YCbCr 4:2:0 */
  3524. #define MRV_MI_SP_OUTPUT_FORMAT_YUV400 0 /* 000: YCbCr 4:0:0 */
  3525. #endif /* MRV_MI_SP_OUTPUT_FORMAT */
  3526. /* Slice: sp_input_format:*/
  3527. /* Selects input format of self picture. For possible restrictions see sub-*/
  3528. /* chapter "Picture Orientation" in chapter "Self Path Output Programming".*/
  3529. /**/
  3530. /* 11: YCbCr 4:4:4 */
  3531. /* 10: YCbCr 4:2:2 */
  3532. /* 01: YCbCr 4:2:0 */
  3533. /* 00: YCbCr 4:0:0 */
  3534. /**/
  3535. /* Note:*/
  3536. /* - Programmed value becomes effective immediately. So write to the */
  3537. /* register only if no picture data is sent to the self path.*/
  3538. #ifdef MRV_MI_SP_INPUT_FORMAT
  3539. #define MRV_MI_SP_INPUT_FORMAT_YUV444 3 /* 11: YCbCr 4:4:4 */
  3540. #define MRV_MI_SP_INPUT_FORMAT_YUV422 2 /* 10: YCbCr 4:2:2 */
  3541. #define MRV_MI_SP_INPUT_FORMAT_YUV420 1 /* 01: YCbCr 4:2:0 */
  3542. #define MRV_MI_SP_INPUT_FORMAT_YUV400 0 /* 00: YCbCr 4:0:0 */
  3543. #endif /* MRV_MI_SP_INPUT_FORMAT */
  3544. /* Slice: sp_write_format:*/
  3545. /* Defines how YCbCr self picture data is written to memory. Ignored if */
  3546. /* RGB conversion is chosen. With RGB conversion active the output format */
  3547. /* is always interleaved.*/
  3548. /**/
  3549. /* 00: planar */
  3550. /* 01: semi planar, for YCbCr 4:2:x */
  3551. /* 10: interleaved (combined), for YCbCr 4:2:2 only */
  3552. /* 11: reserved */
  3553. /**/
  3554. /* Note:*/
  3555. /* - Programmed value becomes effective immediately. So write to the */
  3556. /* register only if no picture data is sent to the self path.*/
  3557. #ifdef MRV_MI_SP_WRITE_FORMAT
  3558. #define MRV_MI_SP_WRITE_FORMAT_PLANAR 0 /* 00: planar */
  3559. #define MRV_MI_SP_WRITE_FORMAT_SEMIPLANAR 1 /* 01: semi planar, for YCbCr 4:2:x */
  3560. #define MRV_MI_SP_WRITE_FORMAT_INTERLEAVED 2 /* 10: interleaved (combined), for YCbCr 4:2:2 only */
  3561. #define MRV_MI_SP_WRITE_FORMAT_RGB_INTERLEAVED 0 /* 00: hw expects a 0 in RGB mode */
  3562. #endif /* MRV_MI_SP_WRITE_FORMAT */
  3563. /* Slice: mp_write_format:*/
  3564. /* Defines how YCbCr main picture data is written to memory.*/
  3565. /* Ignored if JPEG data is chosen.*/
  3566. /* In YCbCr mode the following meaning is applicable */
  3567. /* 00: planar */
  3568. /* 01: semi planar, for YCbCr 4:2:x */
  3569. /* 10: interleaved (combined), for YCbCr 4:2:2 only */
  3570. /* 11: reserved */
  3571. /* In RAW data mode the following meaning is applicable */
  3572. /* 00: RAW 8 bit */
  3573. /* 01: reserved */
  3574. /* 10: RAW 12 bit */
  3575. /* 11: reserved */
  3576. /* Note:*/
  3577. /* - Programmed value becomes effective immediately. So write to the */
  3578. /* register only if no picture data is sent to the main path.*/
  3579. #ifdef MRV_MI_MP_WRITE_FORMAT
  3580. #define MRV_MI_MP_WRITE_FORMAT_PLANAR 0 /* 00: planar */
  3581. #define MRV_MI_MP_WRITE_FORMAT_SEMIPLANAR 1 /* 01: semi planar, for YCbCr 4:2:x */
  3582. #define MRV_MI_MP_WRITE_FORMAT_INTERLEAVED 2 /* 10: interleaved (combined), for YCbCr 4:2:2 only */
  3583. #define MRV_MI_MP_WRITE_FORMAT_RAW_8 0 /* 0x: RAW 8 bit */
  3584. #define MRV_MI_MP_WRITE_FORMAT_RAW_12 2 /* 1x: RAW 12 bit */
  3585. #endif /* MRV_MI_MP_WRITE_FORMAT */
  3586. /* Slice: bp_write_format:*/
  3587. /* In RAW data mode the following meaning is applicable */
  3588. /* 00: RAW 8 bit */
  3589. /* 01: RAW 10 bit */
  3590. /* 10: RAW 12 bit */
  3591. /* 11: reserved */
  3592. /* Note:*/
  3593. /* - Programmed value becomes effective immediately. So write to the */
  3594. /* register only if no picture data is sent to the main path.*/
  3595. #ifdef MRV_MI_BP_WRITE_RAWBIT
  3596. #define MRV_MI_BP_WRITE_RAWBIT_RAW_8 0 /* 0x: RAW 8 bit */
  3597. #define MRV_MI_BP_WRITE_RAWBIT_RAW_10 1 /* 01x: RAW 10 bit */
  3598. #define MRV_MI_BP_WRITE_RAWBIT_RAW_12 2 /* 10x: RAW 12 bit */
  3599. #endif /* MRV_MI_BP_WRITE_RAWBIT */
  3600. /* Slice: init_offset_en:*/
  3601. /* Enables updating of the offset counters shadow registers for */
  3602. /* main and self picture to the programmed register init values.*/
  3603. /**/
  3604. /* MI_MP/SP_Y/CB/CR_OFFS_CNT_INIT */
  3605. /* -> MI_MP/SP_Y/CB/CR_OFFS_CNT_SHD */
  3606. /**/
  3607. /* The update will be executed either when a forced software */
  3608. /* update occurs (in register MI_INIT bit cfg_upd = 1) or when */
  3609. /* an automatic config update signal arrives at the MI input port.*/
  3610. /* The latter is split into main and self picture. So only the */
  3611. /* corresponding main/self shadow registers are affected.*/
  3612. /* After a picture skip has been performed init_offset_en selects */
  3613. /* between skip restart and skip init mode (see bit skip in */
  3614. /* register MI_INIT).*/
  3615. #ifdef MRV_MI_INIT_OFFSET_EN
  3616. #endif /* MRV_MI_INIT_OFFSET_EN */
  3617. /* Slice: init_base_en:*/
  3618. /* Enables updating of the base address and buffer size shadow */
  3619. /* registers for main and self picture to the programmed register */
  3620. /* init values.*/
  3621. /**/
  3622. /* MI_MP/SP_Y/CB/CR_BASE_AD_INIT */
  3623. /* -> MI_MP/SP_Y/CB/CR_BASE_AD_SHD */
  3624. /**/
  3625. /* MI_MP/SP_Y/CB/CR_SIZE_INIT */
  3626. /* -> MI_MP/SP_Y/CB/CR_SIZE_SHD */
  3627. /**/
  3628. /* The update will be executed either when a forced software */
  3629. /* update occurs (in register MI_INIT bit cfg_upd = 1) or when */
  3630. /* an automatic config update signal arrives at the MI input port.*/
  3631. /* The latter is split into main and self picture. So only the */
  3632. /* corresponding main/self shadow registers are affected.*/
  3633. #ifdef MRV_MI_INIT_BASE_EN
  3634. #endif /* MRV_MI_INIT_BASE_EN */
  3635. /* Slice: burst_len_chrom:*/
  3636. /* Burst length for Cb or Cr data affecting write port.*/
  3637. /* 00: 4-beat bursts */
  3638. /* 01: 8-beat bursts */
  3639. /* 10: 16-beat bursts */
  3640. /* 11: reserved */
  3641. /* Ignored if 8- or 16-beat bursts are not supported. If rotation */
  3642. /* is active, then only 4-beat bursts will be generated in self path,*/
  3643. /* regardless of the setting here.*/
  3644. /**/
  3645. /* Note:*/
  3646. /* - Programmed value becomes effective immediately. So write to the */
  3647. /* register only if no picture data is sent to the main and self path.*/
  3648. #ifdef MRV_MI_BURST_LEN_CHROM
  3649. #define MRV_MI_BURST_LEN_CHROM_4 0 /* 0: 4-beat bursts */
  3650. #define MRV_MI_BURST_LEN_CHROM_8 1 /* 1: 8-beat bursts */
  3651. #define MRV_MI_BURST_LEN_CHROM_16 2 /* 2: 16-beat bursts */
  3652. #endif /* MRV_MI_BURST_LEN_CHROM */
  3653. /* Slice: burst_len_lum:*/
  3654. /* Burst length for Y, JPEG, or raw data affecting write port.*/
  3655. /* 00: 4-beat bursts */
  3656. /* 01: 8-beat bursts */
  3657. /* 10: 16-beat bursts */
  3658. /* 11: reserved */
  3659. /* Ignored if 8- or 16-beat bursts are not supported.*/
  3660. /**/
  3661. /* Note: Programmed value becomes effective immediately. So write to */
  3662. /* the register only if no picture data is sent to the main and self path.*/
  3663. #ifdef MRV_MI_BURST_LEN_LUM
  3664. #define MRV_MI_BURST_LEN_LUM_4 0 /* 0: 4-beat bursts */
  3665. #define MRV_MI_BURST_LEN_LUM_8 1 /* 1: 8-beat bursts */
  3666. #define MRV_MI_BURST_LEN_LUM_16 2 /* 2: 16-beat bursts */
  3667. #endif /* MRV_MI_BURST_LEN_LUM */
  3668. /* Slice: last_pixel_sig_en:*/
  3669. /* enables the last pixel signalization */
  3670. /* 1: enabled */
  3671. /* 0: disabled */
  3672. #ifdef MRV_MI_LAST_PIXEL_SIG_EN
  3673. #define MRV_MI_LAST_PIXEL_SIG_EN_ENABLE 1 /* 1: enable last pixel signalization */
  3674. #define MRV_MI_LAST_PIXEL_SIG_EN_DISABLE 0 /* 0: disable last pixel signalization */
  3675. #endif /* MRV_MI_LAST_PIXEL_SIG_EN */
  3676. /* Slice: 422noncosited:*/
  3677. /* Enables self path YCbCr422non-co-sited -> YCbCr444 interpolation */
  3678. /* 1: YCbCr422 data are non_co-sited (Cb and Cr samples */
  3679. /* are centered between Y samples) so modified interpolation */
  3680. /* is activated */
  3681. /* 0: YCbCr422 data are co-sited (Y0 Cb0 and Cr0 are */
  3682. /* sampled at the same position)*/
  3683. /**/
  3684. /* Note:*/
  3685. /* - Programmed value becomes effective immediately. So write to the */
  3686. /* register only if no picture data is sent to the self path.*/
  3687. #ifdef MRV_MI_422NONCOSITED
  3688. #endif /* MRV_MI_422NONCOSITED */
  3689. /* Slice: cbcr_full_range:*/
  3690. /* Enables CbCr full range for self path YCbCr -> RGB conversion */
  3691. /* 1: CbCr have full range (0..255)*/
  3692. /* 0: CbCr have compressed range range (16..240)*/
  3693. /**/
  3694. /* Note:*/
  3695. /* - Programmed value becomes effective immediately. So write to the */
  3696. /* register only if no picture data is sent to the self path.*/
  3697. #ifdef MRV_MI_CBCR_FULL_RANGE
  3698. #endif /* MRV_MI_CBCR_FULL_RANGE */
  3699. /* Slice: y_full_range:*/
  3700. /* Enables Y full range for self path YCbCr -> RGB conversion */
  3701. /* 1: Y has full range (0..255)*/
  3702. /* 0: Y has compressed range (16..235)*/
  3703. /**/
  3704. /* Note:*/
  3705. /* - Programmed value becomes effective immediately. So write to the */
  3706. /* register only if no picture data is sent to the self path.*/
  3707. #ifdef MRV_MI_Y_FULL_RANGE
  3708. #endif /* MRV_MI_Y_FULL_RANGE */
  3709. /* Slice: byte_swap:*/
  3710. /* Enables change of byte order of the 32 bit output word at write port */
  3711. /* 1: byte order is mirrored but the bit order within one byte doesn't */
  3712. /* change */
  3713. /* 0: no byte mirroring */
  3714. /**/
  3715. /* Note: Programmed value becomes effective immediately. So write to the */
  3716. /* register only if no picture data is sent to the main and self path.*/
  3717. #ifdef MRV_MI_BYTE_SWAP
  3718. #endif /* MRV_MI_BYTE_SWAP */
  3719. /* Slice: rot:*/
  3720. /* Rotation 90 degree counter clockwise of self picture, only in RGB */
  3721. /* mode. For picture orientation and operation modes see sub-chapter */
  3722. /* "Picture Orientation" in chapter "Self Path Output Programming".*/
  3723. /**/
  3724. /* For RGB 565 format the line length must be a multiple of 2. There */
  3725. /* are no restrictions for RGB 888/666.*/
  3726. /* 1: enabled */
  3727. /* 0: disabled */
  3728. /**/
  3729. /* Note:*/
  3730. /* - Programmed value becomes effective immediately. So write to the */
  3731. /* register only if no picture data is sent to the self path. In */
  3732. /* rotation mode only 4-beat bursts are supported for self-path.*/
  3733. #ifdef MRV_MI_ROT
  3734. #endif /* MRV_MI_ROT */
  3735. /* Slice: v_flip:*/
  3736. /* Vertical flipping of self picture. For picture orientation and */
  3737. /* operation modes see sub-chapter "Picture Orientation" in chapter */
  3738. /* "Self Path Output Programming". For Y component the line length */
  3739. /* in 4:2:x planar mode must be a multiple of 8, for all other component */
  3740. /* modes a multiple of 4 and for RGB 565 a multiple of 2. There are */
  3741. /* no restrictions for RGB 888/666.*/
  3742. /**/
  3743. /* 1: enabled */
  3744. /* 0: disabled */
  3745. /**/
  3746. /* Note:*/
  3747. /* - Programmed value becomes effective immediately. So write to the */
  3748. /* register only if no picture data is sent to the self path.*/
  3749. #ifdef MRV_MI_V_FLIP
  3750. #endif /* MRV_MI_V_FLIP */
  3751. /* Slice: h_flip:*/
  3752. /* Horizontal flipping of self picture. For picture orientation and */
  3753. /* operation modes see sub-chapter "Picture Orientation" in chapter */
  3754. /* "Self Path Output Programming".*/
  3755. /**/
  3756. /* For Y component the line length in 4:2:x planar mode must be a */
  3757. /* multiple of 8, for all other component modes a multiple of 4 and */
  3758. /* for RGB 565 a multiple of 2. There are no restrictions for RGB 888/666.*/
  3759. /**/
  3760. /* 1: enabled */
  3761. /* 0: disabled */
  3762. /**/
  3763. /* Note:*/
  3764. /* - Programmed value becomes effective immediately. So write to the */
  3765. /* register only if no picture data is sent to the self path.*/
  3766. #ifdef MRV_MI_H_FLIP
  3767. #endif /* MRV_MI_H_FLIP */
  3768. /* Programmed value becomes effective (visible in shadow register)*/
  3769. /* after a soft reset, a forced software update or an automatic */
  3770. /* config update. Affects MI_IN and MI_OUT module.*/
  3771. /* Slice: raw_enable:*/
  3772. /* Enables raw data */
  3773. /* Programmed value becomes effective (visible in control shadow register) after a soft reset or a forced software update.*/
  3774. /* Affects MI_IN and MI_OUT module.*/
  3775. #ifndef MRV_MI_RAW_ENABLE
  3776. #define MRV_MI_RAW_ENABLE
  3777. #define MRV_MI_RAW_ENABLE_MASK 0x00000008
  3778. #define MRV_MI_RAW_ENABLE_SHIFT 3
  3779. #endif /* MRV_MI_RAW_ENABLE */
  3780. /* Slice: dpcc_enable:*/
  3781. /* Enables DPCC data */
  3782. /* Programmed value becomes effective (visible in control shadow register) after a soft reset or a forced software.*/
  3783. /* Affects MI_IN and MI_OUT module.*/
  3784. #ifndef MRV_MI_DPCC_ENABLE
  3785. #define MRV_MI_DPCC_ENABLE
  3786. #define MRV_MI_DPCC_ENABLE_MASK 0x0000000C
  3787. #define MRV_MI_DPCC_ENABLE_SHIFT 2
  3788. #endif /* MRV_MI_JPEG_ENABLE */
  3789. /* Slice: jpeg_enable:*/
  3790. /* Enables JPEG data */
  3791. /* Programmed value becomes effective (visible in control shadow register) after a soft reset or a forced software.*/
  3792. /* Affects MI_IN and MI_OUT module.*/
  3793. #ifndef MRV_MI_JPEG_ENABLE
  3794. #define MRV_MI_JPEG_ENABLE
  3795. #define MRV_MI_JPEG_ENABLE_MASK 0x00000004
  3796. #define MRV_MI_JPEG_ENABLE_SHIFT 2
  3797. #endif /* MRV_MI_JPEG_ENABLE */
  3798. /* Slice: sp_enable:*/
  3799. /* Enables self picture data path.*/
  3800. /* Programmed value becomes effective (visible in control shadow register) after a soft reset, a forced software update or an automatic config update.*/
  3801. /* Affects MI_IN and MI_OUT module.*/
  3802. #ifndef MRV_MI_SP_ENABLE
  3803. #define MRV_MI_SP_ENABLE
  3804. #define MRV_MI_SP_ENABLE_MASK 0x00000002
  3805. #define MRV_MI_SP_ENABLE_SHIFT 1
  3806. #endif /* MRV_MI_SP_ENABLE */
  3807. /* Slice: mp_enable:*/
  3808. /* Enables main picture data path */
  3809. /* Programmed value becomes effective (visible in control shadow register) after a soft reset, a forced software update or an automatic config update.*/
  3810. /* Affects MI_IN and MI_OUT module.*/
  3811. #ifndef MRV_MI_MP_ENABLE
  3812. #define MRV_MI_MP_ENABLE
  3813. #define MRV_MI_MP_ENABLE_MASK 0x00000001
  3814. #define MRV_MI_MP_ENABLE_SHIFT 0
  3815. #endif /* MRV_MI_MP_ENABLE */
  3816. /* Slice: path_enable:*/
  3817. /* Enables data pathes of MI according to the following table:*/
  3818. /**/
  3819. /* 0000: disabled, no data is transferred */
  3820. /* 0001: YUV data output, mainpath only (mp_enable only)*/
  3821. /* 0010: self-path only, output data format depending on other settings (sp_enable only)*/
  3822. /* 0011: YUV data output in mainpath and self-path image data active */
  3823. /* 0100: JPEG data output, mainpath only (jpeg_enable only)*/
  3824. /* 0101: not allowed */
  3825. /* 0110: JPEG data output in mainpath and self-path image data active */
  3826. /* 0111: not allowed */
  3827. /* 1000: RAW data output, mainpath only (raw_enable only)*/
  3828. /* 1001: defect pixel data on self-path, image data on mainpath */
  3829. /* 1010: defect pixel data on mainpath, image data on self-path */
  3830. /* 1011: not allowed */
  3831. /* 1100: defect pixel data on self-path, JPEG data on mainpath */
  3832. /* 1101: defect pixel data on mainpath only */
  3833. /* 1110: defect pixel data on self-path only */
  3834. /* 1111: defect pixel data on self-path, RAW data on mainpath */
  3835. #ifdef MRV_MI_PATH_ENABLE
  3836. #endif /* MRV_MI_PATH_ENABLE */
  3837. /*****************************************************************************/
  3838. /**
  3839. * register: mi_init: Control register for address init and skip function
  3840. * (0x00000004)
  3841. *
  3842. *****************************************************************************/
  3843. /* Slice: mi_cfg_upd:*/
  3844. /* Forced configuration update. Leads to an immediate update of the shadow registers.*/
  3845. /* Depending on the two init enable bits in the MI_CTRL register (init_offset_en and */
  3846. /* init_base_en) the offset counter, base address and buffer size shadow registers */
  3847. /* are also updated.*/
  3848. #ifdef MRV_MI_MI_CFG_UPD
  3849. #endif /* MRV_MI_MI_CFG_UPD */
  3850. /* Slice: mp_output_format:*/
  3851. /* Selects output format of main picture.*/
  3852. /* 1xxx: Reserved */
  3853. /* 0111: RAW10 */
  3854. /* 0110: JPEG */
  3855. /* 0101: RAW8 */
  3856. /* 0100: RAW12 */
  3857. /**/
  3858. /* 0011: YCbCr 4:4:4 */
  3859. /* 0010: YCbCr 4:2:2 */
  3860. /* 0001: YCbCr 4:2:0 */
  3861. /* 0000: YCbCr 4:0:0 */
  3862. /**/
  3863. #ifdef MRV_MI_MP_OUTPUT_FORMAT
  3864. #define MRV_MI_MP_OUTPUT_FORMAT_RAW10 7 /* 0111: RAW10 */
  3865. #define MRV_MI_MP_OUTPUT_FORMAT_JPEG 6 /* 0110: JPEG */
  3866. #define MRV_MI_MP_OUTPUT_FORMAT_RAW8 5 /* 0101: RAW8 */
  3867. #define MRV_MI_MP_OUTPUT_FORMAT_RAW12 4 /* 0100: RAW12 */
  3868. #define MRV_MI_MP_OUTPUT_FORMAT_YUV444 3 /* 0011: YCbCr 4:4:4 */
  3869. #define MRV_MI_MP_OUTPUT_FORMAT_YUV422 2 /* 0010: YCbCr 4:2:2 */
  3870. #define MRV_MI_MP_OUTPUT_FORMAT_YUV420 1 /* 0001: YCbCr 4:2:0 */
  3871. #define MRV_MI_MP_OUTPUT_FORMAT_YUV400 0 /* 0000: YCbCr 4:0:0 */
  3872. #endif /* MRV_MI_MP_OUTPUT_FORMAT */
  3873. /* Slice: mi_skip:*/
  3874. /* Skip of current or next starting main picture:*/
  3875. /* Aborts writing of main picture image data of the current frame to RAM (after the */
  3876. /* current burst transmission has been completed). Further main picture data up to */
  3877. /* the end of the current frame are discarded.*/
  3878. /**/
  3879. /* No further makroblock line interrupt (mblk_line), no wrap around interrupt for */
  3880. /* main picture (wrap_mp_y/cb/cr) and no fill level interrupt (fill_mp_y) are generated.*/
  3881. /**/
  3882. /* Skip does not affect the generation of the main path frame end interrupt (mp_frame_end).*/
  3883. /* Skip does not affect the processing of self picture and its corresponding interrupts */
  3884. /* namely the self path frame end interrupt (sp_frame_end).*/
  3885. /**/
  3886. /* The byte counter (register MI_BYTE_CNT) is not affected. It produces the correct */
  3887. /* number of JPEG or RAW data bytes at the end of the current (skipped) frame.*/
  3888. /**/
  3889. /* After a skip has been performed the offset counter for the main picture at the start */
  3890. /* of the following frame are set depending on the bit init_offset_en in register MI_CTRL:*/
  3891. /**/
  3892. /* - Skip restart mode (init_offset_en = 0)*/
  3893. /* The offset counters of the main picture are restarted at the old start values of */
  3894. /* the previous skipped frame.*/
  3895. /**/
  3896. /* - Skip init mode (init_offset_en = 1)*/
  3897. /* The offset counters of the main picture are initialized with the register contents */
  3898. /* of the offset counter init registers without any additional forced software update */
  3899. /* or automatic config update.*/
  3900. #ifdef MRV_MI_MI_SKIP
  3901. #endif /* MRV_MI_MI_SKIP */
  3902. /*****************************************************************************/
  3903. /**
  3904. * register: mi_mp_y_base_ad_init: Base address for main picture Y component,
  3905. * JPEG or raw data (0x00000008)
  3906. *
  3907. *****************************************************************************/
  3908. /* Slice: mp_y_base_ad_init:*/
  3909. /* Base address of main picture Y component ring buffer, JPEG ring buffer or raw */
  3910. /* data ring buffer.*/
  3911. /**/
  3912. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  3913. /* after a soft reset, a forced software update or an automatic config update.*/
  3914. /**/
  3915. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  3916. #ifdef MRV_MI_MP_Y_BASE_AD_INIT
  3917. #define MRV_MI_MP_Y_BASE_AD_INIT_VALID_MASK (MRV_MI_MP_Y_BASE_AD_INIT_MASK & ~0x00000007)
  3918. #endif /* MRV_MI_MP_Y_BASE_AD_INIT */
  3919. /*****************************************************************************/
  3920. /**
  3921. * register: mi_mp_y_size_init: Size of main picture Y component, JPEG or raw
  3922. * data (0x0000000c)
  3923. *
  3924. *****************************************************************************/
  3925. /* Slice: mp_y_size_init:*/
  3926. /* Size of main picture Y component ring buffer, JPEG ring buffer or raw data */
  3927. /* ring buffer.*/
  3928. /**/
  3929. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  3930. /* after a soft reset, a forced software update or an automatic config update.*/
  3931. /**/
  3932. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  3933. #ifdef MRV_MI_MP_Y_SIZE_INIT
  3934. #define MRV_MI_MP_Y_SIZE_INIT_VALID_MASK (MRV_MI_MP_Y_SIZE_INIT_MASK & ~0x00000007)
  3935. #endif /* MRV_MI_MP_Y_SIZE_INIT */
  3936. /*****************************************************************************/
  3937. /**
  3938. * register: mi_mp_y_offs_cnt_init: Offset counter init value for main picture
  3939. * Y, JPEG or raw data (0x00000010)
  3940. *
  3941. *****************************************************************************/
  3942. /* Slice: mp_y_offs_cnt_init:*/
  3943. /* Offset counter init value of main picture Y component ring buffer, JPEG ring */
  3944. /* buffer or raw data ring buffer.*/
  3945. /**/
  3946. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  3947. /* after a soft reset, a forced software update or an automatic config update.*/
  3948. /**/
  3949. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  3950. #ifdef MRV_MI_MP_Y_OFFS_CNT_INIT
  3951. #define MRV_MI_MP_Y_OFFS_CNT_INIT_VALID_MASK (MRV_MI_MP_Y_OFFS_CNT_INIT_MASK & ~0x00000007)
  3952. #endif /* MRV_MI_MP_Y_OFFS_CNT_INIT */
  3953. /*****************************************************************************/
  3954. /**
  3955. * register: mi_mp_y_offs_cnt_start: Offset counter start value for main picture
  3956. * Y, JPEG or raw data (0x00000014)
  3957. *
  3958. *****************************************************************************/
  3959. /* Slice: mp_y_offs_cnt_start:*/
  3960. /* Offset counter value which points to the start address of the previously */
  3961. /* processed picture (main picture Y component, JPEG or raw data). Updated at */
  3962. /* frame end.*/
  3963. /**/
  3964. /* Note: A soft reset resets the contents to the reset value.*/
  3965. /**/
  3966. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  3967. #ifdef MRV_MI_MP_Y_OFFS_CNT_START
  3968. #define MRV_MI_MP_Y_OFFS_CNT_START_VALID_MASK (MRV_MI_MP_Y_OFFS_CNT_START_MASK & ~0x00000007)
  3969. #endif /* MRV_MI_MP_Y_OFFS_CNT_START */
  3970. /*****************************************************************************/
  3971. /**
  3972. * register: mi_mp_y_irq_offs_init: Fill level interrupt offset value for main
  3973. * picture Y, JPEG or raw data (0x00000018)
  3974. *
  3975. *****************************************************************************/
  3976. /* Slice: mp_y_irq_offs_init:*/
  3977. /* Reaching this programmed value by the current offset counter for addressing */
  3978. /* main picture Y component, JPEG or raw data leads to generation of fill level */
  3979. /* interrupt fill_mp_y.*/
  3980. /**/
  3981. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  3982. /* after a soft reset, a forced software update or an automatic config update.*/
  3983. /**/
  3984. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  3985. #ifdef MRV_MI_MP_Y_IRQ_OFFS_INIT
  3986. #define MRV_MI_MP_Y_IRQ_OFFS_INIT_VALID_MASK (MRV_MI_MP_Y_IRQ_OFFS_INIT_MASK & ~0x00000007)
  3987. #endif /* MRV_MI_MP_Y_IRQ_OFFS_INIT */
  3988. /*****************************************************************************/
  3989. /**
  3990. * register: mi_mp_cb_base_ad_init: Base address for main picture Cb component
  3991. * ring buffer (0x0000001c)
  3992. *
  3993. *****************************************************************************/
  3994. /* Slice: mp_cb_base_ad_init:*/
  3995. /* Base address of main picture Cb component ring buffer.*/
  3996. /**/
  3997. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  3998. /* after a soft reset, a forced software update or an automatic config update.*/
  3999. /**/
  4000. /* Note: Set control bit init_base_en before updating so that a forced or */
  4001. /* automatic update can take effect.*/
  4002. /**/
  4003. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4004. #ifdef MRV_MI_MP_CB_BASE_AD_INIT
  4005. #define MRV_MI_MP_CB_BASE_AD_INIT_VALID_MASK (MRV_MI_MP_CB_BASE_AD_INIT_MASK & ~0x00000007)
  4006. #endif /* MRV_MI_MP_CB_BASE_AD_INIT */
  4007. /*****************************************************************************/
  4008. /**
  4009. * register: mi_mp_cb_size_init: Size of main picture Cb component ring buffer
  4010. * (0x00000020)
  4011. *
  4012. *****************************************************************************/
  4013. /* Slice: mp_cb_size_init:*/
  4014. /* Size of main picture Cb component ring buffer.*/
  4015. /**/
  4016. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4017. /* after a soft reset, a forced software update or an automatic config update.*/
  4018. /**/
  4019. /* Note: Set control bit init_base_en before updating so that a forced or */
  4020. /* automatic update can take effect.*/
  4021. /**/
  4022. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4023. #ifdef MRV_MI_MP_CB_SIZE_INIT
  4024. #define MRV_MI_MP_CB_SIZE_INIT_VALID_MASK (MRV_MI_MP_CB_SIZE_INIT_MASK & ~0x00000007)
  4025. #endif /* MRV_MI_MP_CB_SIZE_INIT */
  4026. /*****************************************************************************/
  4027. /**
  4028. * register: mi_mp_cb_offs_cnt_init: Offset counter init value for main picture
  4029. * Cb component ring buffer (0x00000024)
  4030. *
  4031. *****************************************************************************/
  4032. /* Slice: mp_cb_offs_cnt_init:*/
  4033. /* Offset counter init value of main picture Cb component ring buffer.*/
  4034. /**/
  4035. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4036. /* after a soft reset, a forced software update or an automatic config update.*/
  4037. /**/
  4038. /* Note: Set control bit init_base_en before updating so that a forced or automatic */
  4039. /* update can take effect. Check exceptional handling in skip modes.*/
  4040. /**/
  4041. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4042. #ifdef MRV_MI_MP_CB_OFFS_CNT_INIT
  4043. #define MRV_MI_MP_CB_OFFS_CNT_INIT_VALID_MASK (MRV_MI_MP_CB_OFFS_CNT_INIT_MASK & ~0x00000007)
  4044. #endif /* MRV_MI_MP_CB_OFFS_CNT_INIT */
  4045. /*****************************************************************************/
  4046. /**
  4047. * register: mi_mp_cb_offs_cnt_start: Offset counter start value for main
  4048. * picture Cb component ring buffer (0x00000028)
  4049. *
  4050. *****************************************************************************/
  4051. /* Slice: mp_cb_offs_cnt_start:*/
  4052. /* Offset counter value which points to the start address of the previously */
  4053. /* processed picture (main picture Cb component). Updated at frame end.*/
  4054. /**/
  4055. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4056. #ifdef MRV_MI_MP_CB_OFFS_CNT_START
  4057. #define MRV_MI_MP_CB_OFFS_CNT_START_VALID_MASK (MRV_MI_MP_CB_OFFS_CNT_START_MASK & ~0x00000007)
  4058. #endif /* MRV_MI_MP_CB_OFFS_CNT_START */
  4059. /*****************************************************************************/
  4060. /**
  4061. * register: mi_mp_cr_base_ad_init: Base address for main picture Cr component
  4062. * ring buffer (0x0000002c)
  4063. *
  4064. *****************************************************************************/
  4065. /* Slice: mp_cr_base_ad_init:*/
  4066. /* Base address of main picture Cr component ring buffer.*/
  4067. /**/
  4068. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4069. /* after a soft reset, a forced software update or an automatic config update.*/
  4070. /**/
  4071. /* Note:*/
  4072. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4073. /* update can take effect.*/
  4074. /**/
  4075. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4076. #ifdef MRV_MI_MP_CR_BASE_AD_INIT
  4077. #define MRV_MI_MP_CR_BASE_AD_INIT_VALID_MASK (MRV_MI_MP_CR_BASE_AD_INIT_MASK & ~0x00000007)
  4078. #endif /* MRV_MI_MP_CR_BASE_AD_INIT */
  4079. /*****************************************************************************/
  4080. /**
  4081. * register: mi_mp_cr_size_init: Size of main picture Cr component ring buffer
  4082. * (0x00000030)
  4083. *
  4084. *****************************************************************************/
  4085. /* Slice: mp_cr_size_init:*/
  4086. /* Size of main picture Cr component ring buffer.*/
  4087. /**/
  4088. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4089. /* after a soft reset, a forced software update or an automatic config update.*/
  4090. /**/
  4091. /* Note:*/
  4092. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4093. /* update can take effect.*/
  4094. /**/
  4095. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4096. #ifdef MRV_MI_MP_CR_SIZE_INIT
  4097. #define MRV_MI_MP_CR_SIZE_INIT_VALID_MASK (MRV_MI_MP_CR_SIZE_INIT_MASK & ~0x00000007)
  4098. #endif /* MRV_MI_MP_CR_SIZE_INIT */
  4099. /*****************************************************************************/
  4100. /**
  4101. * register: mi_mp_cr_offs_cnt_init: Offset counter init value for main
  4102. * picture Cr component ring buffer (0x00000034)
  4103. *
  4104. *****************************************************************************/
  4105. /* Slice: mp_cr_offs_cnt_init:*/
  4106. /* Offset counter init value of main picture Cr component ring buffer.*/
  4107. /**/
  4108. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4109. /* after a soft reset, a forced software update or an automatic config update.*/
  4110. /**/
  4111. /* Note:*/
  4112. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4113. /* update can take effect. Check exceptional handling in skip modes.*/
  4114. /**/
  4115. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4116. #ifdef MRV_MI_MP_CR_OFFS_CNT_INIT
  4117. #define MRV_MI_MP_CR_OFFS_CNT_INIT_VALID_MASK (MRV_MI_MP_CR_OFFS_CNT_INIT_MASK & ~0x00000007)
  4118. #endif /* MRV_MI_MP_CR_OFFS_CNT_INIT */
  4119. /*****************************************************************************/
  4120. /**
  4121. * register: mi_mp_cr_offs_cnt_start: Offset counter start value for main
  4122. * picture Cr component ring buffer (0x00000038)
  4123. *
  4124. *****************************************************************************/
  4125. /* Slice: mp_cr_offs_cnt_start:*/
  4126. /* Offset counter value which points to the start address of the previously */
  4127. /* processed picture (main picture Cr component). Updated at frame end.*/
  4128. /**/
  4129. /* Note:*/
  4130. /* - Soft reset will reset the contents to reset value.*/
  4131. /**/
  4132. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4133. #ifdef MRV_MI_MP_CR_OFFS_CNT_START
  4134. #define MRV_MI_MP_CR_OFFS_CNT_START_VALID_MASK (MRV_MI_MP_CR_OFFS_CNT_START_MASK & ~0x00000007)
  4135. #endif /* MRV_MI_MP_CR_OFFS_CNT_START */
  4136. /*****************************************************************************/
  4137. /**
  4138. * register: mi_sp_y_base_ad_init: Base address for self picture Y component
  4139. * ring buffer (0x0000003c)
  4140. *
  4141. *****************************************************************************/
  4142. /* Slice: sp_y_base_ad_init:*/
  4143. /* Base address of self picture Y component ring buffer.*/
  4144. /**/
  4145. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4146. /* after a soft reset, a forced software update or an automatic config update.*/
  4147. /**/
  4148. /* Note:*/
  4149. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4150. /* update can take effect.*/
  4151. /**/
  4152. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4153. #ifdef MRV_MI_SP_Y_BASE_AD_INIT
  4154. #define MRV_MI_SP_Y_BASE_AD_INIT_VALID_MASK (MRV_MI_SP_Y_BASE_AD_INIT_MASK & ~0x00000007)
  4155. #endif /* MRV_MI_SP_Y_BASE_AD_INIT */
  4156. /*****************************************************************************/
  4157. /**
  4158. * register: mi_sp_y_size_init: Size of self picture Y component ring buffer
  4159. * (0x00000040)
  4160. *
  4161. *****************************************************************************/
  4162. /* Slice: sp_y_size_init:*/
  4163. /* Size of self picture Y component ring buffer.*/
  4164. /**/
  4165. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4166. /* after a soft reset, a forced software update or an automatic config update.*/
  4167. /**/
  4168. /* Note: Set control bit init_base_en before updating so that a forced or */
  4169. /* automatic update can take effect.*/
  4170. /**/
  4171. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4172. #ifdef MRV_MI_SP_Y_SIZE_INIT
  4173. #define MRV_MI_SP_Y_SIZE_INIT_VALID_MASK (MRV_MI_SP_Y_SIZE_INIT_MASK & ~0x00000007)
  4174. #endif /* MRV_MI_SP_Y_SIZE_INIT */
  4175. /*****************************************************************************/
  4176. /**
  4177. * register: mi_sp_y_offs_cnt_init: Offset counter init value for self
  4178. * picture Y component ring buffer (0x00000044)
  4179. *
  4180. *****************************************************************************/
  4181. /* Slice: sp_y_offs_cnt_init:*/
  4182. /* Offset counter init value of self picture Y component ring buffer.*/
  4183. /**/
  4184. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4185. /* after a soft reset, a forced software update or an automatic config update.*/
  4186. /**/
  4187. /* Note: Set control bit init_base_en before updating so that a forced or */
  4188. /* automatic update can take effect.*/
  4189. /**/
  4190. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4191. #ifdef MRV_MI_SP_Y_OFFS_CNT_INIT
  4192. #define MRV_MI_SP_Y_OFFS_CNT_INIT_VALID_MASK (MRV_MI_SP_Y_OFFS_CNT_INIT_MASK & ~0x00000007)
  4193. #endif /* MRV_MI_SP_Y_OFFS_CNT_INIT */
  4194. /*****************************************************************************/
  4195. /**
  4196. * register: mi_sp_y_offs_cnt_start: Offset counter start value for self
  4197. * picture Y component ring buffer (0x00000048)
  4198. *
  4199. *****************************************************************************/
  4200. /* Slice: sp_y_offs_cnt_start:*/
  4201. /* Offset counter value which points to the start address of the previously */
  4202. /* processed picture (self picture Y component). Updated at frame end.*/
  4203. /**/
  4204. /* Note:*/
  4205. /* - Soft reset will reset the contents to reset value.*/
  4206. /**/
  4207. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4208. #ifdef MRV_MI_SP_Y_OFFS_CNT_START
  4209. #define MRV_MI_SP_Y_OFFS_CNT_START_VALID_MASK (MRV_MI_SP_Y_OFFS_CNT_START_MASK & ~0x00000007)
  4210. #endif /* MRV_MI_SP_Y_OFFS_CNT_START */
  4211. /*****************************************************************************/
  4212. /**
  4213. * register: mi_sp_y_llength: Line length of self picture Y component (0x0000004c)
  4214. *
  4215. *****************************************************************************/
  4216. /* Slice: sp_y_llength:*/
  4217. /* Line length of self picture Y component or RGB picture in pixel, also */
  4218. /* known as line stride.*/
  4219. /**/
  4220. /* If no line stride is used, line length must match image width.*/
  4221. /**/
  4222. /* For Y component the line length in 4:2:x planar mode must be a multiple of 8,*/
  4223. /* for all other component modes a multiple of 4 and for RGB 565 a multiple of 2.*/
  4224. /* There are no restrictions for RGB 888/666.*/
  4225. /**/
  4226. /* In planar mode the line length of the Cb and Cr component is assumed according */
  4227. /* to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4. In semi */
  4228. /* planar 4:2:x mode the line length of the Cb and Cr component is assumed the */
  4229. /* same size.*/
  4230. /**/
  4231. /* Note:*/
  4232. /* - Line length always refers to the line length of the output image. This */
  4233. /* is particularly important when rotating.*/
  4234. /**/
  4235. /* Note:*/
  4236. /* - Programmed value becomes effective immediately. So write to the register */
  4237. /* only if no picture data is sent to the self path.*/
  4238. #ifdef MRV_MI_SP_Y_LLENGTH
  4239. #define MRV_MI_SP_Y_LLENGTH_VALID_MASK (MRV_MI_SP_Y_LLENGTH_MASK & ~0x00000000)
  4240. #endif /* MRV_MI_SP_Y_LLENGTH */
  4241. /*****************************************************************************/
  4242. /**
  4243. * register: mi_sp_cb_base_ad_init: Base address for self picture Cb component
  4244. * ring buffer (0x00000050)
  4245. *
  4246. *****************************************************************************/
  4247. /* Slice: sp_cb_base_ad_init:*/
  4248. /* Base address of self picture Cb component ring buffer.*/
  4249. /**/
  4250. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4251. /* after a soft reset, a forced software update or an automatic config update.*/
  4252. /**/
  4253. /* Note: Set control bit init_base_en before updating so that a forced or */
  4254. /* automatic update can take effect.*/
  4255. /**/
  4256. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4257. #ifdef MRV_MI_SP_CB_BASE_AD_INIT
  4258. #define MRV_MI_SP_CB_BASE_AD_INIT_VALID_MASK (MRV_MI_SP_CB_BASE_AD_INIT_MASK & ~0x00000007)
  4259. #endif /* MRV_MI_SP_CB_BASE_AD_INIT */
  4260. /*****************************************************************************/
  4261. /**
  4262. * register: mi_sp_cb_size_init: Size of self picture Cb component ring buffer
  4263. * (0x00000054)
  4264. *
  4265. *****************************************************************************/
  4266. /* Slice: sp_cb_size_init:*/
  4267. /* Size of self picture Cb component ring buffer.*/
  4268. /**/
  4269. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4270. /* after a soft reset, a forced software update or an automatic config update.*/
  4271. /**/
  4272. /* Note:*/
  4273. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4274. /* update can take effect.*/
  4275. /**/
  4276. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4277. #ifdef MRV_MI_SP_CB_SIZE_INIT
  4278. #define MRV_MI_SP_CB_SIZE_INIT_VALID_MASK (MRV_MI_SP_CB_SIZE_INIT_MASK & ~0x00000007)
  4279. #endif /* MRV_MI_SP_CB_SIZE_INIT */
  4280. /*****************************************************************************/
  4281. /**
  4282. * register: mi_sp_cb_offs_cnt_init: Offset counter init value for self picture
  4283. * Cb component ring buffer (0x00000058)
  4284. *
  4285. *****************************************************************************/
  4286. /* Slice: sp_cb_offs_cnt_init:*/
  4287. /* Offset counter init value of self picture Cb component ring buffer.*/
  4288. /**/
  4289. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4290. /* after a soft reset, a forced software update or an automatic config update.*/
  4291. /**/
  4292. /* Note:*/
  4293. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4294. /* update can take effect.*/
  4295. /**/
  4296. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4297. #ifdef MRV_MI_SP_CB_OFFS_CNT_INIT
  4298. #define MRV_MI_SP_CB_OFFS_CNT_INIT_VALID_MASK (MRV_MI_SP_CB_OFFS_CNT_INIT_MASK & ~0x00000007)
  4299. #endif /* MRV_MI_SP_CB_OFFS_CNT_INIT */
  4300. /*****************************************************************************/
  4301. /**
  4302. * register: mi_sp_cb_offs_cnt_start: Offset counter start value for self
  4303. * picture Cb component ring buffer (0x0000005c)
  4304. *
  4305. *****************************************************************************/
  4306. /* Slice: sp_cb_offs_cnt_start:*/
  4307. /**/
  4308. /* Offset counter value which points to the start address of the previously */
  4309. /* processed picture (self picture Cb component). Updated at frame end.*/
  4310. /**/
  4311. /* Note:*/
  4312. /* - Soft reset will reset the contents to reset value.*/
  4313. /**/
  4314. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4315. #ifdef MRV_MI_SP_CB_OFFS_CNT_START
  4316. #define MRV_MI_SP_CB_OFFS_CNT_START_VALID_MASK (MRV_MI_SP_CB_OFFS_CNT_START_MASK & ~0x00000007)
  4317. #endif /* MRV_MI_SP_CB_OFFS_CNT_START */
  4318. /*****************************************************************************/
  4319. /**
  4320. * register: mi_sp_cr_base_ad_init: Base address for self picture Cr component
  4321. * ring buffer (0x00000060)
  4322. *
  4323. *****************************************************************************/
  4324. /* Slice: sp_cr_base_ad_init:*/
  4325. /* Base address of self picture Cr component ring buffer.*/
  4326. /**/
  4327. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4328. /* after a soft reset, a forced software update or an automatic config update.*/
  4329. /**/
  4330. /* Note:*/
  4331. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4332. /* update can take effect.*/
  4333. /**/
  4334. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4335. #ifdef MRV_MI_SP_CR_BASE_AD_INIT
  4336. #define MRV_MI_SP_CR_BASE_AD_INIT_VALID_MASK (MRV_MI_SP_CR_BASE_AD_INIT_MASK & ~0x00000007)
  4337. #endif /* MRV_MI_SP_CR_BASE_AD_INIT */
  4338. /*****************************************************************************/
  4339. /**
  4340. * register: mi_sp_cr_size_init: Size of self picture Cr component ring buffer
  4341. * (0x00000064)
  4342. *
  4343. *****************************************************************************/
  4344. /* Slice: sp_cr_size_init:*/
  4345. /* Size of self picture Cr component ring buffer.*/
  4346. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4347. /* after a soft reset, a forced software update or an automatic config update.*/
  4348. /**/
  4349. /* Note:*/
  4350. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4351. /* update can take effect.*/
  4352. /**/
  4353. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4354. #ifdef MRV_MI_SP_CR_SIZE_INIT
  4355. #define MRV_MI_SP_CR_SIZE_INIT_VALID_MASK (MRV_MI_SP_CR_SIZE_INIT_MASK & ~0x00000007)
  4356. #endif /* MRV_MI_SP_CR_SIZE_INIT */
  4357. /*****************************************************************************/
  4358. /**
  4359. * register: mi_sp_cr_offs_cnt_init: Offset counter init value for self
  4360. * picture Cr component ring buffer (0x00000068)
  4361. *
  4362. *****************************************************************************/
  4363. /* Slice: sp_cr_offs_cnt_init:*/
  4364. /* Offset counter init value of self picture Cr component ring buffer.*/
  4365. /**/
  4366. /* Programmed value becomes effective (visible in corresponding shadow register)*/
  4367. /* after a soft reset, a forced software update or an automatic config update.*/
  4368. /**/
  4369. /* Note:*/
  4370. /* - Set control bit init_base_en before updating so that a forced or automatic */
  4371. /* update can take effect.*/
  4372. /**/
  4373. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4374. #ifdef MRV_MI_SP_CR_OFFS_CNT_INIT
  4375. #define MRV_MI_SP_CR_OFFS_CNT_INIT_VALID_MASK (MRV_MI_SP_CR_OFFS_CNT_INIT_MASK & ~0x00000007)
  4376. #endif /* MRV_MI_SP_CR_OFFS_CNT_INIT */
  4377. /*****************************************************************************/
  4378. /**
  4379. * register: mi_sp_cr_offs_cnt_start: Offset counter start value for self
  4380. * picture Cr component ring buffer (0x0000006c)
  4381. *
  4382. *****************************************************************************/
  4383. /* Slice: sp_cr_offs_cnt_start:*/
  4384. /* Offset counter value which points to the start address of the previously */
  4385. /* processed picture (self picture Cr component). Updated at frame end.*/
  4386. /**/
  4387. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4388. #ifdef MRV_MI_SP_CR_OFFS_CNT_START
  4389. #define MRV_MI_SP_CR_OFFS_CNT_START_VALID_MASK (MRV_MI_SP_CR_OFFS_CNT_START_MASK & ~0x00000007)
  4390. #endif /* MRV_MI_SP_CR_OFFS_CNT_START */
  4391. /*****************************************************************************/
  4392. /**
  4393. * register: mi_byte_cnt: Counter value of JPEG or RAW data bytes (0x00000070)
  4394. *
  4395. *****************************************************************************/
  4396. /* Slice: byte_cnt:*/
  4397. /* Counter value specifies the number of JPEG or RAW data bytes of the last */
  4398. /* transmitted frame. Updated at frame end.*/
  4399. /**/
  4400. /* A soft reset will set the byte counter to zero.*/
  4401. #ifdef MRV_MI_BYTE_CNT
  4402. #endif /* MRV_MI_BYTE_CNT */
  4403. /*****************************************************************************/
  4404. /**
  4405. * register: mi_ctrl_shd: global control internal shadow register (0x00000074)
  4406. *
  4407. *****************************************************************************/
  4408. /* Slice: path_enable_out:*/
  4409. /* path_enable shadow register for module MI_OUT (former raw_enable_out,*/
  4410. /* jpeg_enable_out, sp_enable_out, mp_enable_out)*/
  4411. #ifdef MRV_MI_PATH_ENABLE_OUT
  4412. #endif /* MRV_MI_PATH_ENABLE_OUT */
  4413. /* Slice: path_enable_in:*/
  4414. /* path_enable shadow register for module MI_IN (former raw_enable_in,*/
  4415. /* jpeg_enable_in, sp_enable_in, mp_enable_in)*/
  4416. #ifdef MRV_MI_PATH_ENABLE_IN
  4417. #endif /* MRV_MI_PATH_ENABLE_IN */
  4418. /*****************************************************************************/
  4419. /**
  4420. * register: mi_mp_y_base_ad_shd: Base address shadow register for main
  4421. * picture Y component, JPEG or raw data ring buffer (0x00000078)
  4422. *
  4423. *****************************************************************************/
  4424. /* Slice: mp_y_base_ad:*/
  4425. /* Base address of main picture Y component ring buffer, JPEG ring buffer or */
  4426. /* raw data ring buffer.*/
  4427. /**/
  4428. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4429. #ifdef MRV_MI_MP_Y_BASE_AD
  4430. #define MRV_MI_MP_Y_BASE_AD_VALID_MASK (MRV_MI_MP_Y_BASE_AD_MASK & ~0x00000007)
  4431. #endif /* MRV_MI_MP_Y_BASE_AD */
  4432. /*****************************************************************************/
  4433. /**
  4434. * register: mi_mp_y_size_shd: Size shadow register of main picture Y component,
  4435. * JPEG or raw data (0x0000007c)
  4436. *
  4437. *****************************************************************************/
  4438. /* Slice: mp_y_size:*/
  4439. /* Size of main picture Y component ring buffer, JPEG ring buffer or raw data */
  4440. /* ring buffer.*/
  4441. /**/
  4442. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4443. #ifdef MRV_MI_MP_Y_SIZE
  4444. #define MRV_MI_MP_Y_SIZE_VALID_MASK (MRV_MI_MP_Y_SIZE_MASK & ~0x00000007)
  4445. #endif /* MRV_MI_MP_Y_SIZE */
  4446. /*****************************************************************************/
  4447. /**
  4448. * register: mi_mp_y_offs_cnt_shd: Current offset counter of main picture Y
  4449. * component, JPEG or raw data ring buffer (0x00000080)
  4450. *
  4451. *****************************************************************************/
  4452. /* Slice: mp_y_offs_cnt:*/
  4453. /* Current offset counter of main picture Y component, JPEG or raw data ring */
  4454. /* buffer for address generation */
  4455. /**/
  4456. /* Note:*/
  4457. /* - Soft reset will reset the contents to reset value.*/
  4458. /**/
  4459. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4460. #ifdef MRV_MI_MP_Y_OFFS_CNT
  4461. #define MRV_MI_MP_Y_OFFS_CNT_VALID_MASK (MRV_MI_MP_Y_OFFS_CNT_MASK & ~0x00000007)
  4462. #endif /* MRV_MI_MP_Y_OFFS_CNT */
  4463. /*****************************************************************************/
  4464. /**
  4465. * register: mi_mp_y_irq_offs_shd: Shadow register of fill level interrupt
  4466. * offset value for main picture Y component, JPEG or raw data
  4467. * (0x00000084)
  4468. *
  4469. *****************************************************************************/
  4470. /* Slice: mp_y_irq_offs:*/
  4471. /* Reaching this offset value by the current offset counter for addressing */
  4472. /* main picture Y component, JPEG or raw data leads to generation of fill */
  4473. /* level interrupt fill_mp_y.*/
  4474. /**/
  4475. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4476. #ifdef MRV_MI_MP_Y_IRQ_OFFS
  4477. #endif /* MRV_MI_MP_Y_IRQ_OFFS */
  4478. /*****************************************************************************/
  4479. /**
  4480. * register: mi_mp_cb_base_ad_shd: Base address shadow register for main
  4481. * picture Cb component ring buffer (0x00000088)
  4482. *
  4483. *****************************************************************************/
  4484. /* Slice: mp_cb_base_ad:*/
  4485. /* Base address of main picture Cb component ring buffer.*/
  4486. /**/
  4487. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4488. #ifdef MRV_MI_MP_CB_BASE_AD
  4489. #endif /* MRV_MI_MP_CB_BASE_AD */
  4490. /*****************************************************************************/
  4491. /**
  4492. * register: mi_mp_cb_size_shd: Size shadow register of main picture Cb
  4493. * component ring buffer (0x0000008c)
  4494. *
  4495. *****************************************************************************/
  4496. /* Slice: mp_cb_size:*/
  4497. /* Size of main picture Cb component ring buffer.*/
  4498. /**/
  4499. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4500. #ifdef MRV_MI_MP_CB_SIZE
  4501. #endif /* MRV_MI_MP_CB_SIZE */
  4502. /*****************************************************************************/
  4503. /**
  4504. * register: mi_mp_cb_offs_cnt_shd: Current offset counter of main picture Cb
  4505. * component ring buffer (0x00000090)
  4506. *
  4507. *****************************************************************************/
  4508. /* Slice: mp_cb_offs_cnt:*/
  4509. /* Current offset counter of main picture Cb component ring buffer for address */
  4510. /* generation */
  4511. /**/
  4512. /* Note:*/
  4513. /* - Soft reset will reset the contents to reset value.*/
  4514. /**/
  4515. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4516. #ifdef MRV_MI_MP_CB_OFFS_CNT
  4517. #endif /* MRV_MI_MP_CB_OFFS_CNT */
  4518. /*****************************************************************************/
  4519. /**
  4520. * register: mi_mp_cr_base_ad_shd: Base address shadow register for main
  4521. * picture Cr component ring buffer (0x00000094)
  4522. *
  4523. *****************************************************************************/
  4524. /* Slice: mp_cr_base_ad:*/
  4525. /* Base address of main picture Cr component ring buffer.*/
  4526. /**/
  4527. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4528. #ifdef MRV_MI_MP_CR_BASE_AD
  4529. #endif /* MRV_MI_MP_CR_BASE_AD */
  4530. /*****************************************************************************/
  4531. /**
  4532. * register: mi_mp_cr_size_shd: Size shadow register of main picture Cr
  4533. * component ring buffer (0x00000098)
  4534. *
  4535. *****************************************************************************/
  4536. /* Slice: mp_cr_size:*/
  4537. /* Size of main picture Cr component ring buffer.*/
  4538. /**/
  4539. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4540. #ifdef MRV_MI_MP_CR_SIZE
  4541. #endif /* MRV_MI_MP_CR_SIZE */
  4542. /*****************************************************************************/
  4543. /**
  4544. * register: mi_mp_cr_offs_cnt_shd: Current offset counter of main picture Cr
  4545. * component ring buffer (0x0000009c)
  4546. *
  4547. *****************************************************************************/
  4548. /* Slice: mp_cr_offs_cnt:*/
  4549. /* Current offset counter of main picture Cr component ring buffer for */
  4550. /* address generation */
  4551. /**/
  4552. /* Note:*/
  4553. /* - Soft reset will reset the contents to reset value.*/
  4554. /**/
  4555. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4556. #ifdef MRV_MI_MP_CR_OFFS_CNT
  4557. #endif /* MRV_MI_MP_CR_OFFS_CNT */
  4558. /*****************************************************************************/
  4559. /**
  4560. * register: mi_sp_y_base_ad_shd: Base address shadow register for self
  4561. * picture Y component ring buffer (0x000000a0)
  4562. *
  4563. *****************************************************************************/
  4564. /* Slice: sp_y_base_ad:*/
  4565. /* Base address of self picture Y component ring buffer.*/
  4566. /**/
  4567. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4568. #ifdef MRV_MI_SP_Y_BASE_AD
  4569. #endif /* MRV_MI_SP_Y_BASE_AD */
  4570. /*****************************************************************************/
  4571. /**
  4572. * register: mi_sp_y_size_shd: Size shadow register of self picture Y
  4573. * component ring buffer (0x000000a4)
  4574. *
  4575. *****************************************************************************/
  4576. /* Slice: sp_y_size:*/
  4577. /* Size of self picture Y component ring buffer.*/
  4578. /**/
  4579. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4580. #ifdef MRV_MI_SP_Y_SIZE
  4581. #endif /* MRV_MI_SP_Y_SIZE */
  4582. /*****************************************************************************/
  4583. /**
  4584. * register: mi_sp_y_offs_cnt_shd: Current offset counter of self picture Y
  4585. * component ring buffer (0x000000a8)
  4586. *
  4587. *****************************************************************************/
  4588. /* Slice: sp_y_offs_cnt:*/
  4589. /* Current offset counter of self picture Y component ring buffer for address generation */
  4590. /**/
  4591. /* Note:*/
  4592. /* - Soft reset will reset the contents to reset value.*/
  4593. /**/
  4594. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4595. #ifdef MRV_MI_SP_Y_OFFS_CNT
  4596. #endif /* MRV_MI_SP_Y_OFFS_CNT */
  4597. /*****************************************************************************/
  4598. /**
  4599. * register: mi_sp_cb_base_ad_shd: Base address shadow register for self
  4600. * picture Cb component ring buffer (0x000000b0)
  4601. *
  4602. *****************************************************************************/
  4603. /* Slice: sp_cb_base_ad:*/
  4604. /* Base address of self picture Cb component ring buffer.*/
  4605. /**/
  4606. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4607. #ifdef MRV_MI_SP_CB_BASE_AD
  4608. #endif /* MRV_MI_SP_CB_BASE_AD */
  4609. /*****************************************************************************/
  4610. /**
  4611. * register: mi_sp_cb_size_shd: Size shadow register of self picture Cb
  4612. * component ring buffer (0x000000b4)
  4613. *
  4614. *****************************************************************************/
  4615. /* Slice: sp_cb_size:*/
  4616. /* Size of self picture Cb component ring buffer.*/
  4617. /**/
  4618. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4619. #ifdef MRV_MI_SP_CB_SIZE
  4620. #endif /* MRV_MI_SP_CB_SIZE */
  4621. /*****************************************************************************/
  4622. /**
  4623. * register: mi_sp_cb_offs_cnt_shd: Current offset counter of self picture
  4624. * Cb component ring buffer (0x000000b8)
  4625. *
  4626. *****************************************************************************/
  4627. /* Slice: sp_cb_offs_cnt:*/
  4628. /* Current offset counter of self picture Cb component ring buffer for */
  4629. /* address generation */
  4630. /**/
  4631. /* Note:*/
  4632. /* - Soft reset will reset the contents to reset value.*/
  4633. /**/
  4634. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4635. #ifdef MRV_MI_SP_CB_OFFS_CNT
  4636. #endif /* MRV_MI_SP_CB_OFFS_CNT */
  4637. /*****************************************************************************/
  4638. /**
  4639. * register: mi_sp_cr_base_ad_shd: Base address shadow register for self
  4640. * picture Cr component ring buffer (0x000000bc)
  4641. *
  4642. *****************************************************************************/
  4643. /* Slice: sp_cr_base_ad:*/
  4644. /* Base address of self picture Cr component ring buffer.*/
  4645. /**/
  4646. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4647. #ifdef MRV_MI_SP_CR_BASE_AD
  4648. #endif /* MRV_MI_SP_CR_BASE_AD */
  4649. /*****************************************************************************/
  4650. /**
  4651. * register: mi_sp_cr_size_shd: Size shadow register of self picture Cr
  4652. * component ring buffer (0x000000c0)
  4653. *
  4654. *****************************************************************************/
  4655. /* Slice: sp_cr_size:*/
  4656. /* Size of self picture Cr component ring buffer.*/
  4657. /**/
  4658. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4659. #ifdef MRV_MI_SP_CR_SIZE
  4660. #endif /* MRV_MI_SP_CR_SIZE */
  4661. /*****************************************************************************/
  4662. /**
  4663. * register: mi_sp_cr_offs_cnt_shd: Current offset counter of self picture Cr
  4664. * component ring buffer (0x000000c4)
  4665. *
  4666. *****************************************************************************/
  4667. /* Slice: sp_cr_offs_cnt:*/
  4668. /* Current offset counter of self picture Cr component ring buffer for */
  4669. /* address generation */
  4670. /**/
  4671. /* Note:*/
  4672. /* - Soft reset will reset the contents to reset value.*/
  4673. /**/
  4674. /* Must be 64-bit aligned (bit 0, bit 1 and bit 2 are hard wired to "000")*/
  4675. #ifdef MRV_MI_SP_CR_OFFS_CNT
  4676. #endif /* MRV_MI_SP_CR_OFFS_CNT */
  4677. /*****************************************************************************/
  4678. /**
  4679. * register: mi_dma_y_pic_start_ad: Y component image start address (0x000000c8)
  4680. *
  4681. *****************************************************************************/
  4682. /* Slice: dma_y_pic_start_ad:*/
  4683. /* Image start address of the y component */
  4684. /**/
  4685. /* Note:*/
  4686. /* - Must be multiple of 4 in interleaved mode.*/
  4687. #ifdef MRV_MI_DMA_Y_PIC_START_AD
  4688. #endif /* MRV_MI_DMA_Y_PIC_START_AD */
  4689. /*****************************************************************************/
  4690. /**
  4691. * register: mi_dma_y_pic_width: Y component image width (0x000000cc)
  4692. *
  4693. *****************************************************************************/
  4694. /* Slice: dma_y_pic_width:*/
  4695. /* Image width of the Y component in pixel.*/
  4696. /**/
  4697. /* For YCbCr 4:2:x the image width must be a multiple of 2.*/
  4698. /**/
  4699. /* In planar mode the image width of the Cb and Cr component is assumed */
  4700. /* according to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4.*/
  4701. /**/
  4702. /* In semi planar 4:2:x mode the image width of the Cb component (which includes Cr)*/
  4703. /* is assumed the same size.*/
  4704. /**/
  4705. /* In interleave mode no Cb/Cr image width is used.*/
  4706. #ifdef MRV_MI_DMA_Y_PIC_WIDTH
  4707. #endif /* MRV_MI_DMA_Y_PIC_WIDTH */
  4708. /*****************************************************************************/
  4709. /**
  4710. * register: mi_dma_y_llength: Y component original line length (0x000000d0)
  4711. *
  4712. *****************************************************************************/
  4713. /* Slice: dma_y_llength:*/
  4714. /* Line length of the Y component of the original image in memory */
  4715. /**/
  4716. /* For an uncropped image, where lines follow each other without offset */
  4717. /* (no line stride), line length must match image width.*/
  4718. /**/
  4719. /* For Y component the line length in 4:2:x planar mode must be a multiple of 8,*/
  4720. /* for all other component modes a multiple of 4.*/
  4721. /**/
  4722. /* In planar mode the line length of the Cb and Cr component is assumed according */
  4723. /* to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4.*/
  4724. /**/
  4725. /* In semi planar 4:2:x mode the line length of the Cb component (which includes Cr)*/
  4726. /* is assumed the same size.*/
  4727. /**/
  4728. /* In interleave mode no Cb/Cr line length is used.*/
  4729. #ifdef MRV_MI_DMA_Y_LLENGTH
  4730. #endif /* MRV_MI_DMA_Y_LLENGTH */
  4731. /*****************************************************************************/
  4732. /**
  4733. * register: mi_dma_y_pic_size: Y component image size (0x000000d4)
  4734. *
  4735. *****************************************************************************/
  4736. /* Slice: dma_y_pic_size:*/
  4737. /* Image size of the Y component in pixel which has to be the Y line length */
  4738. /* multiplied by the Y image height (dma_y_llength * dma_y_pic_height).*/
  4739. /**/
  4740. /* In planar mode the image size of the Cb and Cr component is assumed according */
  4741. /* to the YCbCr format, i.e. a quarter for 4:2:0, half for 4:2:2 and the same */
  4742. /* for 4:4:4.*/
  4743. /**/
  4744. /* In semi planar mode the image size of the Cb component (which includes Cr)*/
  4745. /* is assumed half for 4:2:0 and the same size for 4:2:2.*/
  4746. /**/
  4747. /* In interleave mode no Cb/Cr image size is used.*/
  4748. #ifdef MRV_MI_DMA_Y_PIC_SIZE
  4749. #endif /* MRV_MI_DMA_Y_PIC_SIZE */
  4750. /*****************************************************************************/
  4751. /**
  4752. * register: mi_dma_cb_pic_start_ad: Cb component image start address (0x000000d8)
  4753. *
  4754. *****************************************************************************/
  4755. /* Slice: dma_cb_pic_start_ad:*/
  4756. /* Image start address of the Cb component */
  4757. /**/
  4758. /* Note:*/
  4759. /* - Must be multiple of 2 in semi-planar mode.*/
  4760. #ifdef MRV_MI_DMA_CB_PIC_START_AD
  4761. #endif /* MRV_MI_DMA_CB_PIC_START_AD */
  4762. /*****************************************************************************/
  4763. /**
  4764. * register: mi_dma_cr_pic_start_ad: Cr component image start address (0x000000e8)
  4765. *
  4766. *****************************************************************************/
  4767. /* Slice: dma_cr_pic_start_ad:*/
  4768. /* Image start address of the Cr component */
  4769. #ifdef MRV_MI_DMA_CR_PIC_START_AD
  4770. #endif /* MRV_MI_DMA_CR_PIC_START_AD */
  4771. /*****************************************************************************/
  4772. /**
  4773. * register: mi_imsc: Interrupt Mask Register (0x000000f8)
  4774. * mi_ris : Raw Interrupt Status Register (0x000000fc)
  4775. * mi_mis : Masked Interrupt Status Register (0x00000100)
  4776. * mi_icr : Interrupt Clear Register (0x00000104)
  4777. * mi_isr : Interrupt Set Register (0x00000108)
  4778. *
  4779. * ('1': interrupt active, '0': interrupt masked)
  4780. *
  4781. *****************************************************************************/
  4782. /* Slice: dma_ready:*/
  4783. /* Mask bit for dma ready interrupt */
  4784. #ifndef MRV_MI_DMA_READY
  4785. #define MRV_MI_DMA_READY_MASK 0
  4786. #endif /* MRV_MI_DMA_READY */
  4787. /* Slice: wrap_sp_cr:*/
  4788. /* Mask bit for self picture Cr address wrap interrupt */
  4789. #ifndef MRV_MI_WRAP_SP_CR
  4790. #define MRV_MI_WRAP_SP_CR_MASK 0
  4791. #endif /* MRV_MI_WRAP_SP_CR */
  4792. /* Slice: wrap_sp_cb:*/
  4793. /* Mask bit for self picture Cb address wrap interrupt */
  4794. #ifndef MRV_MI_WRAP_SP_CB
  4795. #define MRV_MI_WRAP_SP_CB_MASK 0
  4796. #endif /* MRV_MI_WRAP_SP_CB */
  4797. /* Slice: wrap_sp_y:*/
  4798. /* Mask bit for self picture Y address wrap interrupt */
  4799. #ifndef MRV_MI_WRAP_SP_Y
  4800. #define MRV_MI_WRAP_SP_Y_MASK 0
  4801. #endif /* MRV_MI_WRAP_SP_Y */
  4802. /* Slice: wrap_mp_cr:*/
  4803. /* Mask bit for main picture Cr address wrap interrupt */
  4804. #ifndef MRV_MI_WRAP_MP_CR
  4805. #define MRV_MI_WRAP_MP_CR_MASK 0
  4806. #endif /* MRV_MI_WRAP_MP_CR */
  4807. /* Slice: wrap_mp_cb:*/
  4808. /* Mask bit for main picture Cb address wrap interrupt */
  4809. #ifndef MRV_MI_WRAP_MP_CB
  4810. #define MRV_MI_WRAP_MP_CB_MASK 0
  4811. #endif /* MRV_MI_WRAP_MP_CB */
  4812. /* Slice: wrap_mp_y:*/
  4813. /* Mask bit for main picture Y address wrap interrupt */
  4814. #ifndef MRV_MI_WRAP_MP_Y
  4815. #define MRV_MI_WRAP_MP_Y_MASK 0
  4816. #endif /* MRV_MI_WRAP_MP_Y */
  4817. /* Slice: fill_mp_y:*/
  4818. /* Mask bit for fill level interrupt of main picture Y,*/
  4819. /* JPEG or raw data */
  4820. #ifndef MRV_MI_FILL_MP_Y
  4821. #define MRV_MI_FILL_MP_Y_MASK 0
  4822. #endif /* MRV_MI_FILL_MP_Y */
  4823. /* Slice: mblk_line:*/
  4824. /* Mask bit for makroblock line interrupt of main picture */
  4825. /* (16 lines of Y, 8 lines of Cb and 8 lines of Cr are written */
  4826. /* into RAM)*/
  4827. #ifndef MRV_MI_MBLK_LINE
  4828. #define MRV_MI_MBLK_LINE_MASK 0
  4829. #endif /* MRV_MI_MBLK_LINE */
  4830. /* Slice: sp_frame_end:*/
  4831. /* Mask self picture end of frame interrupt */
  4832. #ifndef MRV_MI_SP_FRAME_END
  4833. #define MRV_MI_SP_FRAME_END_MASK 0
  4834. #endif /* MRV_MI_SP_FRAME_END */
  4835. /* Slice: mp_frame_end:*/
  4836. /* Mask main picture end of frame interrupt */
  4837. #ifndef MRV_MI_MP_FRAME_END
  4838. #define MRV_MI_MP_FRAME_END_MASK 0
  4839. #endif /* MRV_MI_MP_FRAME_END */
  4840. /* combination of all interrupt lines */
  4841. #define MRV_MI_ALL_IRQS
  4842. #define MRV_MI_ALL_IRQS_MASK \
  4843. (0 \
  4844. | MRV_MI_DMA_READY_MASK \
  4845. | MRV_MI_AHB_ERROR_MASK \
  4846. | MRV_MI_WRAP_SP_CR_MASK \
  4847. | MRV_MI_WRAP_SP_CB_MASK \
  4848. | MRV_MI_WRAP_SP_Y_MASK \
  4849. | MRV_MI_WRAP_MP_CR_MASK \
  4850. | MRV_MI_WRAP_MP_CB_MASK \
  4851. | MRV_MI_WRAP_MP_Y_MASK \
  4852. | MRV_MI_FILL_MP_Y_MASK \
  4853. | MRV_MI_MBLK_LINE_MASK \
  4854. | MRV_MI_SP_FRAME_END_MASK \
  4855. | MRV_MI_DMA_FRAME_END_MASK \
  4856. | MRV_MI_MP_FRAME_END_MASK \
  4857. )
  4858. #define MRV_MI_ALL_IRQS_SHIFT 0U
  4859. /*****************************************************************************/
  4860. /**
  4861. * register: mi_status : MI Status Register (0x0000010c)
  4862. * mi_status_clr: MI Status Clear Register (0x00000110)
  4863. *
  4864. *****************************************************************************/
  4865. /* Slice: sp_cr_fifo_full:*/
  4866. /* FIFO full flag of Cr FIFO in self path asserted since last clear */
  4867. #ifndef MRV_MI_SP_CR_FIFO_FULL
  4868. #define MRV_MI_SP_CR_FIFO_FULL_MASK 0U
  4869. #endif /* MRV_MI_SP_CR_FIFO_FULL */
  4870. /* Slice: sp_cb_fifo_full:*/
  4871. /* FIFO full flag of Cb FIFO in self path asserted since last clear */
  4872. #ifndef MRV_MI_SP_CB_FIFO_FULL
  4873. #define MRV_MI_SP_CB_FIFO_FULL_MASK 0U
  4874. #endif /* MRV_MI_SP_CB_FIFO_FULL */
  4875. /* Slice: sp_y_fifo_full:*/
  4876. /* FIFO full flag of Y FIFO in self path asserted since last clear */
  4877. #ifndef MRV_MI_SP_Y_FIFO_FULL
  4878. #define MRV_MI_SP_Y_FIFO_FULL_MASK 0U
  4879. #endif /* MRV_MI_SP_Y_FIFO_FULL */
  4880. /* Slice: mp_cr_fifo_full:*/
  4881. /* FIFO full flag of Cr FIFO in main path asserted since last clear */
  4882. #ifndef MRV_MI_MP_CR_FIFO_FULL
  4883. #define MRV_MI_MP_CR_FIFO_FULL_MASK 0U
  4884. #endif /* MRV_MI_MP_CR_FIFO_FULL */
  4885. /* Slice: mp_cb_fifo_full:*/
  4886. /* FIFO full flag of Cb FIFO in main path asserted since last clear */
  4887. #ifndef MRV_MI_MP_CB_FIFO_FULL
  4888. #define MRV_MI_MP_CB_FIFO_FULL_MASK 0U
  4889. #endif /* MRV_MI_MP_CB_FIFO_FULL */
  4890. /* Slice: mp_y_fifo_full:*/
  4891. /* FIFO full flag of Y FIFO in main path asserted since last clear */
  4892. #ifndef MRV_MI_MP_Y_FIFO_FULL
  4893. #define MRV_MI_MP_Y_FIFO_FULL_MASK 0U
  4894. #endif /* MRV_MI_MP_Y_FIFO_FULL */
  4895. /* combination of all MI status lines */
  4896. #define MRV_MI_ALL_STAT
  4897. #define MRV_MI_ALL_STAT_MASK \
  4898. (0 \
  4899. | MRV_MI_SP_CR_FIFO_FULL_MASK \
  4900. | MRV_MI_SP_CB_FIFO_FULL_MASK \
  4901. | MRV_MI_SP_Y_FIFO_FULL_MASK \
  4902. | MRV_MI_MP_CR_FIFO_FULL_MASK \
  4903. | MRV_MI_MP_CB_FIFO_FULL_MASK \
  4904. | MRV_MI_MP_Y_FIFO_FULL_MASK \
  4905. )
  4906. #define MRV_MI_ALL_STAT_SHIFT 0U
  4907. /*****************************************************************************/
  4908. /**
  4909. * register: mi_sp_y_pic_width: Y component image width (0x00000114)
  4910. *
  4911. *****************************************************************************/
  4912. /* Slice: sp_y_pic_width:*/
  4913. /* Image width of the self picture Y component or RGB picture in pixel.*/
  4914. /**/
  4915. /* For YCbCr 4:2:x and RGB 565 the image width must be a multiple of 2.*/
  4916. /* If no line stride is used but flipping required, the image width must be */
  4917. /* a multiple of 8 for 4:2:x planar or 4 for 4:4:4 planar/4:2:x semi planar.*/
  4918. /**/
  4919. /* There are no restrictions for RGB 888/666.*/
  4920. /**/
  4921. /* In planar mode the image width of the Cb and Cr component is assumed according */
  4922. /* to the YCbCr format, i.e. half for 4:2:x and the same size for 4:4:4.*/
  4923. /**/
  4924. /* In semi planar 4:2:x mode the image width of the Cb component (which includes Cr)*/
  4925. /* is assumed the same size.*/
  4926. /**/
  4927. /* In interleave mode no Cb/Cr image width is used.*/
  4928. /* Note:*/
  4929. /* - Image width always refers to the picture width of the output image. This is */
  4930. /* particularly important when rotating.*/
  4931. /**/
  4932. /* Note:*/
  4933. /* - Programmed value becomes effective immediately. So write to the register */
  4934. /* only if no picture data is sent to the self path.*/
  4935. #ifdef MRV_MI_SP_Y_PIC_WIDTH
  4936. #endif /* MRV_MI_SP_Y_PIC_WIDTH */
  4937. /*****************************************************************************/
  4938. /**
  4939. * register: mi_sp_y_pic_height: Y component image height (0x00000118)
  4940. *
  4941. *****************************************************************************/
  4942. /* Slice: sp_y_pic_height:*/
  4943. /* Image height of the y component or RGB picture in pixel.*/
  4944. /**/
  4945. /* In planar and semi planar mode the image width of the cb and cr component */
  4946. /* is assumed according to the YCbCr format, i.e. half for 4:2:0 and the same */
  4947. /* for 4:2:2 and 4:4:4.*/
  4948. /**/
  4949. /* Note:*/
  4950. /* - Image height always refers to the picture height of the output image.*/
  4951. /* This is particularly important when rotating.*/
  4952. /**/
  4953. /* Note:*/
  4954. /* - Programmed value becomes effective immediately. So write to the register */
  4955. /* only if no picture data is sent to the self path.*/
  4956. #ifdef MRV_MI_SP_Y_PIC_HEIGHT
  4957. #endif /* MRV_MI_SP_Y_PIC_HEIGHT */
  4958. /*****************************************************************************/
  4959. /**
  4960. * register: mi_sp_y_pic_size: Y component image size (0x0000011c)
  4961. *
  4962. *****************************************************************************/
  4963. /* Slice: sp_y_pic_size:*/
  4964. /* Image size of the Y component or RGB picture in pixel which has to be the */
  4965. /* Y line length multiplied by the Y image height (sp_y_llength * sp_y_pic_height).*/
  4966. /**/
  4967. /* In planar mode the image size of the Cb and Cr component is assumed according */
  4968. /* to the YCbCr format, i.e. a quarter for 4:2:0, half for 4:2:2 and the same for */
  4969. /* 4:4:4.*/
  4970. /**/
  4971. /* In semi planar mode the image size of the Cb and Cr component is assumed half */
  4972. /* for 4:2:0 and the same size for 4:2:2.*/
  4973. /**/
  4974. /* Note:*/
  4975. /* - Programmed value becomes effective immediately. So write to the register only */
  4976. /* if no picture data is sent to the self path.*/
  4977. #ifdef MRV_MI_SP_Y_PIC_SIZE
  4978. #endif /* MRV_MI_SP_Y_PIC_SIZE */
  4979. /*****************************************************************************/
  4980. /**
  4981. * register: mi_dma_ctrl: DMA control register (0x00000120)
  4982. *
  4983. *****************************************************************************/
  4984. /* Slice: dma_rgb_format:*/
  4985. /* Selects RGB Bayer data of read DMA picture */
  4986. /**/
  4987. /* 00: no DMA RGB Bayer data */
  4988. /* 01: 8 bit RGB Bayer data */
  4989. /* 10: 16 bit RGB Bayer data (12 bit used)*/
  4990. /**/
  4991. /* bytes are organized MSB first and 4 lower bits of LSB remain unused:*/
  4992. /* byte_even -> bayer[11:4], byte_odd[7:4] -> bayer[3:0]*/
  4993. /**/
  4994. /* 11: reserved.*/
  4995. #ifdef MRV_MI_DMA_RGB_FORMAT
  4996. #define MRV_MI_DMA_RGB_FORMAT_NO_DATA 0
  4997. #define MRV_MI_DMA_RGB_FORMAT_8BIT_BAYER 1
  4998. #define MRV_MI_DMA_RGB_FORMAT_16BIT_BAYER 2
  4999. #endif /* MRV_MI_DMA_RGB_FORMAT */
  5000. /* Slice: dma_frame_end_disable:*/
  5001. /* Suppresses v_end so that no frame end can be detected by following */
  5002. /* instances. Note: The dma_ready interrupt is raised as usual, but the */
  5003. /* dma_frame_end interrupt will not be generated until v_end has been */
  5004. /* enabled again.*/
  5005. #ifdef MRV_MI_DMA_FRAME_END_DISABLE
  5006. #endif /* MRV_MI_DMA_FRAME_END_DISABLE */
  5007. /* Slice: dma_continuous_en:*/
  5008. /* Enables continuous mode. If set the same frame is read back over and */
  5009. /* over. A start pulse on dma_start is needed only for the first time.*/
  5010. /* To stop continuous mode reset this bit (takes effect after the next */
  5011. /* frame end) or execute a soft reset. This bit is intended to be used */
  5012. /* in conjunction with the Superimpose feature.*/
  5013. #ifdef MRV_MI_DMA_CONTINUOUS_EN
  5014. #endif /* MRV_MI_DMA_CONTINUOUS_EN */
  5015. /* Slice: dma_byte_swap:*/
  5016. /* Enables change of DMA byte order of the 32 bit input word at read port */
  5017. /* 1: byte order is mirrored but the bit order within one byte doesn’t change */
  5018. /* 0: no byte mirroring */
  5019. #ifdef MRV_MI_DMA_BYTE_SWAP
  5020. #endif /* MRV_MI_DMA_BYTE_SWAP */
  5021. /* Slice: dma_inout_format:*/
  5022. /* Selects input/output format of DMA picture.*/
  5023. /* 11: YCbCr 4:4:4 */
  5024. /* 10: YCbCr 4:2:2 */
  5025. /* 01: YCbCr 4:2:0 */
  5026. /* 00: YCbCr 4:0:0 */
  5027. #ifdef MRV_MI_DMA_INOUT_FORMAT
  5028. #define MRV_MI_DMA_INOUT_FORMAT_YUV444 3 /* 11: YCbCr 4:4:4 */
  5029. #define MRV_MI_DMA_INOUT_FORMAT_YUV422 2 /* 10: YCbCr 4:2:2 */
  5030. #define MRV_MI_DMA_INOUT_FORMAT_YUV420 1 /* 01: YCbCr 4:2:0 */
  5031. #define MRV_MI_DMA_INOUT_FORMAT_YUV400 0 /* 00: YCbCr 4:0:0 */
  5032. #endif /* MRV_MI_DMA_INOUT_FORMAT */
  5033. /* Slice: dma_read_format:*/
  5034. /* Defines how YCbCr picture data is read from memory.*/
  5035. /* 00: planar */
  5036. /* 01: semi planar, for YCbCr 4:2:x */
  5037. /* 10: interleaved (combined), for YCbCr 4:2:2 and RGB only */
  5038. /* 11: reserved */
  5039. #ifdef MRV_MI_DMA_READ_FORMAT
  5040. #define MRV_MI_DMA_READ_FORMAT_PLANAR 0 /* 00: planar */
  5041. #define MRV_MI_DMA_READ_FORMAT_SEMIPLANAR 1 /* 01: semi planar, for YCbCr 4:2:x */
  5042. #define MRV_MI_DMA_READ_FORMAT_INTERLEAVED 2 /* 10: interleaved (combined), for YCbCr 4:2:2 only */
  5043. #endif /* MRV_MI_DMA_READ_FORMAT */
  5044. /* Slice: dma_burst_len_chrom:*/
  5045. /* Burst length for Cb or Cr data affecting DMA read port.*/
  5046. /* 00: 4-beat bursts */
  5047. /* 01: 8-beat bursts */
  5048. /* 10: 16-beat bursts */
  5049. /* 11: reserved */
  5050. /* Ignored if 8- or 16-beat bursts are not supported.*/
  5051. #ifdef MRV_MI_DMA_BURST_LEN_CHROM
  5052. #define MRV_MI_DMA_BURST_LEN_CHROM_4 0 /* 0: 4-beat bursts */
  5053. #define MRV_MI_DMA_BURST_LEN_CHROM_8 1 /* 1: 8-beat bursts */
  5054. #define MRV_MI_DMA_BURST_LEN_CHROM_16 2 /* 2: 16-beat bursts */
  5055. #endif /* MRV_MI_DMA_BURST_LEN_CHROM */
  5056. /* Slice: dma_burst_len_lum:*/
  5057. /* Burst length for Y data affecting DMA read port.*/
  5058. /* 00: 4-beat bursts */
  5059. /* 01: 8-beat bursts */
  5060. /* 10: 16-beat bursts */
  5061. /* 11: reserved */
  5062. /* Ignored if 8- or 16-beat bursts are not supported.*/
  5063. #ifdef MRV_MI_DMA_BURST_LEN_LUM
  5064. #define MRV_MI_DMA_BURST_LEN_LUM_4 0 /* 0: 4-beat bursts */
  5065. #define MRV_MI_DMA_BURST_LEN_LUM_8 1 /* 1: 8-beat bursts */
  5066. #define MRV_MI_DMA_BURST_LEN_LUM_16 2 /* 2: 16-beat bursts */
  5067. #endif /* MRV_MI_DMA_BURST_LEN_LUM */
  5068. /*****************************************************************************/
  5069. /**
  5070. * register: mi_dma_start: DMA start register (0x00000124)
  5071. *
  5072. *****************************************************************************/
  5073. /* Slice: dma_start:*/
  5074. /* Enables DMA access. Additionally main or self path has to be enabled separately.*/
  5075. #ifdef MRV_MI_DMA_START
  5076. #endif /* MRV_MI_DMA_START */
  5077. /*****************************************************************************/
  5078. /**
  5079. * register: mi_dma_status: DMA status register (0x00000128)
  5080. *
  5081. *****************************************************************************/
  5082. /* Slice: dma_active:*/
  5083. /* If set DMA access is active.*/
  5084. #ifdef MRV_MI_DMA_ACTIVE
  5085. #endif /* MRV_MI_DMA_ACTIVE */
  5086. /*****************************************************************************/
  5087. /**
  5088. * register: mi_pixel_cnt: Counter value for defect pixel list (0x0000012c)
  5089. *
  5090. *****************************************************************************/
  5091. /* Slice: pix_cnt:*/
  5092. /* Counter value specifies the number of pixels of the defect pixel list */
  5093. /* generated by DPCC of the last transmitted frame. Updated at frame end.*/
  5094. /**/
  5095. /* A soft reset will set the counter to zero.*/
  5096. #ifdef MRV_MI_PIX_CNT
  5097. #endif /* MRV_MI_PIX_CNT */
  5098. #ifdef ISP_MI_HANDSHAKE_NANO
  5099. /* Nano handshake */
  5100. /*****************************************************************************/
  5101. /**
  5102. * register: isp_handshake_ctrl_0: Nano handshake functions (0x0000014C)
  5103. *
  5104. *****************************************************************************/
  5105. /*! Slice: mp_handshake_en: */
  5106. /*! Enable mp handshake function for MI MP */
  5107. #ifdef MRV_MI_MP_HANDSHK_EN
  5108. #define MRV_MI_MP_HANDSHK_EN_DISABLE 0 /* HANDSHAKE disable */
  5109. #define MRV_MI_MP_HANDSHK_EN_ENABLE 1 /* HANDSHAKE enable, active high */
  5110. #endif
  5111. /*! Slice: mp_handshk_storage_format */
  5112. /*! Define how YCbCr picture data is stored in memory */
  5113. /*! 00: Planar */
  5114. /*! 01: Semi planar, for YCbCr4:2:x */
  5115. /*! 10: Interleaved(combiled), for YCbCr 4:2:2 only or RAW format.*/
  5116. /*! 11: not support */
  5117. #ifdef MRV_MI_MP_HANDSHK_STORAGE_FORMAT
  5118. #define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_PLANAR 0 /* 00: Planar */
  5119. #define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_SEMIPLANAR 1 /* 01: Semi-Planar */
  5120. #define MRV_MI_MP_HANDSHK_STORAGE_FORMAT_INTERLEAVED 2 /* 10: Interleaved */
  5121. #endif
  5122. /*! Slice: mp_handshk_data_format */
  5123. /*! Defines the video format */
  5124. /*! 00: RAW format */
  5125. /*! 01: reserved */
  5126. /*! 10: YUV 422 */
  5127. /*! 11: YUV 420 */
  5128. #ifdef MRV_MI_MP_HANDSHK_DATA_FORMAT
  5129. #define MRV_MI_MP_HANDSHK_DATA_FORMAT_RAW 0 /* 00: raw format */
  5130. #define MRV_MI_MP_HANDSHK_DATA_FORMAT_YUV422 2 /* 10: YUV422 */
  5131. #define MRV_MI_MP_HANDSHK_DATA_FORMAT_YUV420 3 /* 11: YUV420 */
  5132. #endif
  5133. /*! Slice: mp_handshk_slice_size */
  5134. /*! Defines the slice size to generate handshake signals, minus 1 is used */
  5135. #ifdef MRV_MI_MP_HANDSHK_SLICE_SIZE
  5136. #endif
  5137. /*! Slice: mp_handshk_slice_buf_size */
  5138. /*! Defines the circular buffer size in number of defined slices per buffer, minus 1 is used */
  5139. #ifdef MRV_MI_MP_HANDSHK_SLICE_BUF_SIZE
  5140. #endif
  5141. /*! Slice: mp_handshk_ack_count */
  5142. /*! Defines the acknowledage is not received in the defined cycles, it will generate handshake interrupt.*/
  5143. #ifdef MRV_MI_MP_HANDSHK_ACK_COUNT
  5144. #endif
  5145. #endif
  5146. #ifdef ISP_MI_ALIGN_NANO
  5147. /* MI output Alignment */
  5148. /*****************************************************************************/
  5149. /**
  5150. * register: mi_output_alignment: Nano MI output alignment (0x0000015C)
  5151. *
  5152. *****************************************************************************/
  5153. /* Slice: mp_lsb_alignment:*/
  5154. /*! msb/lsb align for raw 10 and raw 12 formats control */
  5155. /*! 0: MSB aligned for RAW10 and RAW12 formats */
  5156. /*! 1: LSB aligned for RAW10 and RAW12 formats */
  5157. #ifdef MRV_MI_LSB_ALIGNMENT
  5158. #define MRV_MI_LSB_ALIGNMENT_MSB 0 /* MSB aligned for raw 10 and raw 12 formats */
  5159. #define MRV_MI_LSB_ALIGNMENT_LSB 1 /* LSB aligned for raw 10 and raw 12 formats */
  5160. #endif
  5161. #endif
  5162. #ifdef ISP_MI_BYTESWAP
  5163. /*! Slice mp_byte_swap:*/
  5164. /*! swap bytes for ISP Nano */
  5165. /*! bit 0 to swap bytes */
  5166. /*! bit 1 to swap words */
  5167. /*! bit 2 to swap dwords */
  5168. /*! 3'b001: ABCDEFGH => BADCFEHG */
  5169. /*! 3'b000: ABCDEFGH => ABCDEFGH */
  5170. /*! 3'b010: ABCDEFGH => CDABGHEF */
  5171. /*! 3'b011: ABCDEFGH => DCBAHGFE */
  5172. /*! 3'b100: ABCDEFGH => EFGHABCD */
  5173. /*! 3'b101: ABCDEFGH => FEHGBADC */
  5174. /*! 3'b110: ABCDEFGH => GHEFCDAB */
  5175. /*! 3'b111: ABCDEFGH => HGFEDCBA */
  5176. #ifdef MRV_MI_MP_BYTE_SWAP
  5177. #define MRV_MI_MP_BYTE_SWAP_NORMAL 0x0 /* normal mode */
  5178. #define MRV_MI_MP_BYTE_SWAP_BYTE 0x1 /* bit 0 to swap bytes */
  5179. #define MRV_MI_MP_BYTE_SWAP_WORD 0x2 /* bit 1 to swap words */
  5180. #define MRV_MI_MP_BYTE_SWAP_DWORD 0x4 /* bit 2 to swap dwords */
  5181. #endif
  5182. #endif
  5183. #ifdef ISP_MI_FIFO_DEPTH_NANO
  5184. /*****************************************************************************/
  5185. /**
  5186. * register: mi_mp_output_fifo_size: Nano MI fifo control (0x00000160)
  5187. *
  5188. *****************************************************************************/
  5189. /*! Slice output_fifo_depth:*/
  5190. /*! Select output FIFO depth setting */
  5191. /*! 00: FULL(2KBytes)*/
  5192. /*! 01: HALF(1KBytes)*/
  5193. /*! 10: 1/4(512Bytes)*/
  5194. /*! 11: 1/8(256Bytes)*/
  5195. #ifdef MRV_MI_OUTOUT_FIFO_DEPTH
  5196. #define MRV_MI_OUTOUT_FIFO_DEPTH_FULL 0 /* FULL(2KBytes) */
  5197. #define MRV_MI_OUTOUT_FIFO_DEPTH_HALF 1 /* HALF(1KBytes) */
  5198. #define MRV_MI_OUTOUT_FIFO_DEPTH_1_4 2 /* 1/4(512Bytes) */
  5199. #define MRV_MI_OUTOUT_FIFO_DEPTH_1_8 3 /* 1/8(256Bytes) */
  5200. #endif
  5201. #endif
  5202. /*****************************************************************************/
  5203. /* JPEG Encoder Registers */
  5204. /*****************************************************************************/
  5205. /*****************************************************************************/
  5206. /**
  5207. * register: jpe_gen_header: command to start stream header generation (0x0000)
  5208. *
  5209. *****************************************************************************/
  5210. /* Slice: gen_header:*/
  5211. /* "1" = Start command to generate stream header */
  5212. /* auto reset to zero after one clock cycle */
  5213. #ifdef MRV_JPE_GEN_HEADER
  5214. #endif /* MRV_JPE_GEN_HEADER */
  5215. /*****************************************************************************/
  5216. /**
  5217. * register: jpe_encode: Start command to start JFIF stream encoding (0x0004)
  5218. *
  5219. *****************************************************************************/
  5220. /* Slice: encode:*/
  5221. /* "1" = Start command to start JFIF stream encoding;*/
  5222. /* auto reset to zero after one clock cycle.*/
  5223. /* This bit is write-only: reading result is always zero!*/
  5224. #ifdef MRV_JPE_ENCODE
  5225. #endif /* MRV_JPE_ENCODE */
  5226. /*****************************************************************************/
  5227. /**
  5228. * register: jpe_init: Automatic configuration update (INIT) (0x0008)
  5229. *
  5230. *****************************************************************************/
  5231. /* Slice: JP_INIT:*/
  5232. /* "1" = Immediate start of JPEG encoder.*/
  5233. /**/
  5234. /* This bit has to be set after "Encode" to start the JPEG encoder. The "Encode"*/
  5235. /* command becomes active either with JP_INIT or with the input signal "CFG_UPD".*/
  5236. /* auto reset to zero after one clock cycle !!!*/
  5237. #ifdef MRV_JPE_JP_INIT
  5238. #endif /* MRV_JPE_JP_INIT */
  5239. /*****************************************************************************/
  5240. /**
  5241. * register: jpe_y_scale_en: Y value scaling control register (0x0000000c)
  5242. *
  5243. *****************************************************************************/
  5244. /* Slice: y_scale_en:*/
  5245. /* Y scale flag */
  5246. /* 1: scaling Y input from [16..235] to [0..255]*/
  5247. /* 0: no Y input scaling */
  5248. #ifdef MRV_JPE_Y_SCALE_EN
  5249. #endif /* MRV_JPE_Y_SCALE_EN */
  5250. /*****************************************************************************/
  5251. /**
  5252. * register: jpe_cbcr_scale_en: Cb/Cr value scaling control register (0x00000010)
  5253. *
  5254. *****************************************************************************/
  5255. /* Slice: cbcr_scale_en:*/
  5256. /* Cb/Cr scale flag */
  5257. /* 1: scaling Cb/Cr input from [16..240] to [0..255]*/
  5258. /* 0: no Cb/Cr input scaling */
  5259. #ifdef MRV_JPE_CBCR_SCALE_EN
  5260. #endif /* MRV_JPE_CBCR_SCALE_EN */
  5261. /*****************************************************************************/
  5262. /**
  5263. * register: jpe_table_flush: header generation debug register (0x00000014)
  5264. *
  5265. *****************************************************************************/
  5266. /* Slice: table_flush:*/
  5267. /* header generation debug control flag */
  5268. /* (controls transmission of last header bytes if the 64 bit output buffer */
  5269. /* is not completely filled)*/
  5270. /* 1: immediately transmit last header bytes */
  5271. /* 0: wait for encoded image data to fill output buffer */
  5272. #ifdef MRV_JPE_TABLE_FLUSH
  5273. #endif /* MRV_JPE_TABLE_FLUSH */
  5274. /*****************************************************************************/
  5275. /**
  5276. * register: jpe_enc_hsize: JPEG codec horizontal image size for encoding
  5277. * (0x00000018)
  5278. *
  5279. *****************************************************************************/
  5280. /* Slice: enc_hsize:*/
  5281. /* JPEG codec horizontal image size for R2B and SGEN blocks */
  5282. #ifdef MRV_JPE_ENC_HSIZE
  5283. #endif /* MRV_JPE_ENC_HSIZE */
  5284. /*****************************************************************************/
  5285. /**
  5286. * register: jpe_enc_vsize: JPEG codec vertical image size for encoding
  5287. * (0x0000001c)
  5288. *
  5289. *****************************************************************************/
  5290. /* Slice: enc_vsize:*/
  5291. /* JPEG codec vertical image size for R2B and SGEN blocks */
  5292. #ifdef MRV_JPE_ENC_VSIZE
  5293. #endif /* MRV_JPE_ENC_VSIZE */
  5294. /*****************************************************************************/
  5295. /**
  5296. * register: jpe_pic_format: JPEG picture encoding format (0x00000020)
  5297. *
  5298. *****************************************************************************/
  5299. /* Slice: enc_pic_format:*/
  5300. /* "0:0:1" = 4:2:2 format */
  5301. /* "1:x:x" = 4:0:0 format */
  5302. #ifdef MRV_JPE_ENC_PIC_FORMAT
  5303. #define MRV_JPE_ENC_PIC_FORMAT_422 1 /* "0:0:1" = 4:2:2 format */
  5304. #define MRV_JPE_ENC_PIC_FORMAT_400 4 /* "1:x:x" = 4:0:0 format */
  5305. #endif /* MRV_JPE_ENC_PIC_FORMAT */
  5306. /*****************************************************************************/
  5307. /**
  5308. * register: jpe_restart_interval: restart marker insertion register (0x0024)
  5309. *
  5310. *****************************************************************************/
  5311. /* Slice: restart_interval:*/
  5312. /* No of MCU in reset interval via host */
  5313. #ifdef MRV_JPE_RESTART_INTERVAL
  5314. #endif /* MRV_JPE_RESTART_INTERVAL */
  5315. /*****************************************************************************/
  5316. /**
  5317. * register: jpe_tq_y_select: Q- table selector 0, quant. table for Y
  5318. * component (0x00000028)
  5319. *
  5320. *****************************************************************************/
  5321. /* Slice: tq0_select:*/
  5322. /* "00" = qtable 0 */
  5323. /* "01" = qtable 1 */
  5324. /* "10" = qtable 2 */
  5325. /* "11" = qtable 3 */
  5326. #ifdef MRV_JPE_TQ0_SELECT
  5327. #endif /* MRV_JPE_TQ0_SELECT */
  5328. /*****************************************************************************/
  5329. /**
  5330. * register: jpe_tq_u_select: Q- table selector 1, quant. table for U
  5331. * component (0x0000002c)
  5332. *
  5333. *****************************************************************************/
  5334. /* Slice: tq1_select:*/
  5335. /* "00" = qtable 0 */
  5336. /* "01" = qtable 1 */
  5337. /* "10" = qtable 2 */
  5338. /* "11" = qtable 3 */
  5339. #ifdef MRV_JPE_TQ1_SELECT
  5340. #endif /* MRV_JPE_TQ1_SELECT */
  5341. /*****************************************************************************/
  5342. /**
  5343. * register: jpe_tq_v_select: Q- table selector 2, quant. table for V
  5344. * component (0x00000030)
  5345. *
  5346. *****************************************************************************/
  5347. /* Slice: tq2_select:*/
  5348. /* "00" = qtable 0 */
  5349. /* "01" = qtable 1 */
  5350. /* "10" = qtable 2 */
  5351. /* "11" = qtable 3 */
  5352. #ifdef MRV_JPE_TQ2_SELECT
  5353. #endif /* MRV_JPE_TQ2_SELECT */
  5354. #define MRV_JPE_TQ_SELECT_TAB3 3 /* "11": qtable 3 */
  5355. #define MRV_JPE_TQ_SELECT_TAB2 2 /* "10": qtable 2 */
  5356. #define MRV_JPE_TQ_SELECT_TAB1 1 /* "01": qtable 1 */
  5357. #define MRV_JPE_TQ_SELECT_TAB0 0 /* "00": qtable 0 */
  5358. /*****************************************************************************/
  5359. /**
  5360. * register: jpe_dc_table_select: Huffman table selector for DC values
  5361. * (0x00000034)
  5362. *
  5363. *****************************************************************************/
  5364. /* Slice: dc_table_select_v:*/
  5365. /* "0" = dc table 0; color component 2 (V)*/
  5366. /* "1" = dc table 1; color component 2 (V)*/
  5367. #ifdef MRV_JPE_DC_TABLE_SELECT_V
  5368. #endif /* MRV_JPE_DC_TABLE_SELECT_V */
  5369. /* Slice: dc_table_select_u:*/
  5370. /* "0" = dc table 0; color component 1 (U)*/
  5371. /* "1" = dc table 1; color component 1 (U)*/
  5372. #ifdef MRV_JPE_DC_TABLE_SELECT_U
  5373. #endif /* MRV_JPE_DC_TABLE_SELECT_U */
  5374. /* Slice: dc_table_select_y:*/
  5375. /* "0" = dc table 0; color component 0 (Y)*/
  5376. /* "1" = dc table 1; color component 0 (Y)*/
  5377. #ifdef MRV_JPE_DC_TABLE_SELECT_Y
  5378. #endif /* MRV_JPE_DC_TABLE_SELECT_Y */
  5379. /*****************************************************************************/
  5380. /**
  5381. * register: jpe_ac_table_select: Huffman table selector for AC values
  5382. * (0x00000038)
  5383. *
  5384. *****************************************************************************/
  5385. /* Slice: ac_table_select_v:*/
  5386. /* "0" = ac table 0; component 2 (V)*/
  5387. /* "1" = ac table 1; component 2 (V)*/
  5388. #ifdef MRV_JPE_AC_TABLE_SELECT_V
  5389. #endif /* MRV_JPE_AC_TABLE_SELECT_V */
  5390. /* Slice: ac_table_select_u:*/
  5391. /* "0" = ac table 0; component 1 (U)*/
  5392. /* "1" = ac table 1; component 1 (U)*/
  5393. #ifdef MRV_JPE_AC_TABLE_SELECT_U
  5394. #endif /* MRV_JPE_AC_TABLE_SELECT_U */
  5395. /* Slice: ac_table_select_y:*/
  5396. /* "0" = ac table 0; component 0 (Y)*/
  5397. /* "1" = ac table 1; component 0 (Y)*/
  5398. #ifdef MRV_JPE_AC_TABLE_SELECT_Y
  5399. #endif /* MRV_JPE_AC_TABLE_SELECT_Y */
  5400. /*****************************************************************************/
  5401. /**
  5402. * register: jpe_table_data: table programming register (0x0000003c)
  5403. *
  5404. *****************************************************************************/
  5405. /* Slice: table_wdata_h:*/
  5406. /* Table data MSB */
  5407. #ifdef MRV_JPE_TABLE_WDATA_H
  5408. #endif /* MRV_JPE_TABLE_WDATA_H */
  5409. /* Slice: table_wdata_l:*/
  5410. /* Table data LSB */
  5411. #ifdef MRV_JPE_TABLE_WDATA_L
  5412. #endif /* MRV_JPE_TABLE_WDATA_L */
  5413. /*****************************************************************************/
  5414. /**
  5415. * register: jpe_table_id: table programming select register (0x00000040)
  5416. *
  5417. *****************************************************************************/
  5418. /* Slice: table_id:*/
  5419. /* select table */
  5420. /* "0000" : Q-table 0 */
  5421. /* "0001" : Q-table 1 */
  5422. /* "0010" : Q-table 2 */
  5423. /* "0011" : Q-table 3 */
  5424. /* "0100" : VLC DC-table 0 */
  5425. /* "0101" : VLC AC-table 0 */
  5426. /* "0110" : VLC DC-table 1 */
  5427. /* "0111" : VLC AC-table 1 */
  5428. /* "1xxx" : reserved for debug */
  5429. #ifdef MRV_JPE_TABLE_ID
  5430. #define MRV_JPE_TABLE_ID_QUANT0 0 /* "0000" : Q-table 0 */
  5431. #define MRV_JPE_TABLE_ID_QUANT1 1 /* "0001" : Q-table 1 */
  5432. #define MRV_JPE_TABLE_ID_QUANT2 2 /* "0010" : Q-table 2 */
  5433. #define MRV_JPE_TABLE_ID_QUANT3 3 /* "0011" : Q-table 3 */
  5434. #define MRV_JPE_TABLE_ID_VLC_DC0 4 /* "0100" : VLC DC-table 0 */
  5435. #define MRV_JPE_TABLE_ID_VLC_AC0 5 /* "0101" : VLC AC-table 0 */
  5436. #define MRV_JPE_TABLE_ID_VLC_DC1 6 /* "0110" : VLC DC-table 1 */
  5437. #define MRV_JPE_TABLE_ID_VLC_AC1 7 /* "0111" : VLC AC-table 1 */
  5438. #endif /* MRV_JPE_TABLE_ID */
  5439. /*****************************************************************************/
  5440. /**
  5441. * register: jpe_tac0_len: Huffman AC table 0 length (0x0044)
  5442. *
  5443. *****************************************************************************/
  5444. /* Slice: tac0_len:*/
  5445. /* Huffman table length for ac0 table */
  5446. #ifdef MRV_JPE_TAC0_LEN
  5447. #endif /* MRV_JPE_TAC0_LEN */
  5448. /*****************************************************************************/
  5449. /**
  5450. * register: jpe_tdc0_len: Huffman DC table 0 length (0x00000048)
  5451. *
  5452. *****************************************************************************/
  5453. /* Slice: tdc0_len:*/
  5454. /* Huffman table length for dc0 table */
  5455. #ifdef MRV_JPE_TDC0_LEN
  5456. #endif /* MRV_JPE_TDC0_LEN */
  5457. /*****************************************************************************/
  5458. /**
  5459. * register: jpe_tac1_len: Huffman AC table 1 length (0x0000004c)
  5460. *
  5461. *****************************************************************************/
  5462. /* Slice: tac1_len:*/
  5463. /* Huffman table length for ac1 table */
  5464. #ifdef MRV_JPE_TAC1_LEN
  5465. #endif /* MRV_JPE_TAC1_LEN */
  5466. /*****************************************************************************/
  5467. /**
  5468. * register: jpe_tdc1_len: Huffman DC table 1 length (0x00000050)
  5469. *
  5470. *****************************************************************************/
  5471. /* Slice: tdc1_len:*/
  5472. /* Huffman table length for dc1 table */
  5473. #ifdef MRV_JPE_TDC1_LEN
  5474. #endif /* MRV_JPE_TDC1_LEN */
  5475. /*****************************************************************************/
  5476. /**
  5477. * register: jpe_encoder_busy: encoder status flag (0x00000058)
  5478. *
  5479. *****************************************************************************/
  5480. /* Slice: codec_busy:*/
  5481. /* Bit 0 = "1" : JPEG codec in process */
  5482. #ifdef MRV_JPE_CODEC_BUSY
  5483. #endif /* MRV_JPE_CODEC_BUSY */
  5484. /*****************************************************************************/
  5485. /**
  5486. * register: jpe_header_mode: header mode definition (0x0000005c)
  5487. *
  5488. *****************************************************************************/
  5489. /* Slice: header_mode:*/
  5490. /* "00" = no header */
  5491. /* "01" = reserved */
  5492. /* "10" = JFIF 1.02 header */
  5493. /* "11" = reserved */
  5494. #ifdef MRV_JPE_HEADER_MODE
  5495. #define MRV_JPE_HEADER_MODE_NONE 0 /* "00" = no APPn header */
  5496. #define MRV_JPE_HEADER_MODE_JFIF 2 /* "10" = JFIF header */
  5497. #endif /* MRV_JPE_HEADER_MODE */
  5498. /*****************************************************************************/
  5499. /**
  5500. * register: jpe_encode_mode: encode mode (0x00000060)
  5501. *
  5502. *****************************************************************************/
  5503. /* Slice: encode_mode:*/
  5504. /* Always "1", because this is the encoder only edition */
  5505. #ifdef MRV_JPE_ENCODE_MODE
  5506. #endif /* MRV_JPE_ENCODE_MODE */
  5507. /*****************************************************************************/
  5508. /**
  5509. * register: jpe_debug: debug information register (0x00000064)
  5510. *
  5511. *****************************************************************************/
  5512. /* Slice: deb_bad_table_access:*/
  5513. /* Debug signal only (set if an access to the TABLE_DATA or to the TABLE_ID */
  5514. /* register is performed, when the JPEG_ENCODER is busy. In this case a default */
  5515. /* PVCI Acknowledge is generated. Thus the configuration bus is not blocked)*/
  5516. #ifdef MRV_JPE_DEB_BAD_TABLE_ACCESS
  5517. #endif /* MRV_JPE_DEB_BAD_TABLE_ACCESS */
  5518. /* Slice: deb_vlc_table_busy:*/
  5519. /* Debug signal only (vlc access to huff-tables)*/
  5520. #ifdef MRV_JPE_DEB_VLC_TABLE_BUSY
  5521. #endif /* MRV_JPE_DEB_VLC_TABLE_BUSY */
  5522. /* Slice: deb_r2b_memory_full:*/
  5523. /* Debug signal only (line memory status of r2b)*/
  5524. #ifdef MRV_JPE_DEB_R2B_MEMORY_FULL
  5525. #endif /* MRV_JPE_DEB_R2B_MEMORY_FULL */
  5526. /* Slice: deb_vlc_encode_busy:*/
  5527. /* Debug signal only (vlc encode processing active)*/
  5528. #ifdef MRV_JPE_DEB_VLC_ENCODE_BUSY
  5529. #endif /* MRV_JPE_DEB_VLC_ENCODE_BUSY */
  5530. /* Slice: deb_qiq_table_acc:*/
  5531. /* Debug signal only (QIQ table access)*/
  5532. #ifdef MRV_JPE_DEB_QIQ_TABLE_ACC
  5533. #endif /* MRV_JPE_DEB_QIQ_TABLE_ACC */
  5534. /*****************************************************************************/
  5535. /**
  5536. * register: jpe_error_imr: JPEG error interrupt mask register (0x00000068)
  5537. * jpe_error_ris: JPEG error raw interrupt status register (0x0000006c)
  5538. * jpe_error_mis: JPEG error masked interrupt status register (0x00000070)
  5539. * jpe_error_icr: JPEG error interrupt set register (0x00000074)
  5540. * jpe_error_isr: JPEG error interrupt clear register (0x00000078)
  5541. *
  5542. *****************************************************************************/
  5543. /* Slice: vlc_table_err:*/
  5544. /* "1" = interrupt is activated (masked in)*/
  5545. #ifdef MRV_JPE_VLC_TABLE_ERR
  5546. #endif /* MRV_JPE_VLC_TABLE_ERR */
  5547. /* Slice: r2b_IMG_size_err:*/
  5548. /* "1" = interrupt is activated (masked in)*/
  5549. #ifdef MRV_JPE_R2B_IMG_SIZE_ERR
  5550. #endif /* MRV_JPE_R2B_IMG_SIZE_ERR */
  5551. /* Slice: DCT_ERR:*/
  5552. /* "1" = interrupt is activated (masked in)*/
  5553. #ifdef MRV_JPE_DCT_ERR
  5554. #endif /* MRV_JPE_DCT_ERR */
  5555. /* Slice: vlc_symbol_err:*/
  5556. /* "1" = interrupt is activated (masked in)*/
  5557. #ifdef MRV_JPE_VLC_SYMBOL_ERR
  5558. #endif /* MRV_JPE_VLC_SYMBOL_ERR */
  5559. /*****************************************************************************/
  5560. /**
  5561. * register: jpe_status_imr: JPEG status interrupt mask register (0x0000007c)
  5562. * jpe_status_ris: JPEG status raw interrupt status register (0x00000080)
  5563. * jpe_status_mis: JPEG status masked interrupt status register (0x00000084)
  5564. * jpe_status_icr: JPEG status interrupt clear register (0x00000088)
  5565. * jpe_status_isr: JPEG status interrupt set register (0x0000008c)
  5566. *
  5567. *****************************************************************************/
  5568. /* Slice: gen_header_done:*/
  5569. /* "1" = interrupt is activated (masked in)*/
  5570. #ifdef MRV_JPE_GEN_HEADER_DONE
  5571. #endif /* MRV_JPE_GEN_HEADER_DONE */
  5572. /* Slice: encode_done:*/
  5573. /* "1" = interrupt is activated (masked in)*/
  5574. #ifdef MRV_JPE_ENCODE_DONE
  5575. #endif /* MRV_JPE_ENCODE_DONE */
  5576. /*****************************************************************************/
  5577. /**
  5578. * register: jpe_config: JPEG configuration register (0x00000090)
  5579. *
  5580. *****************************************************************************/
  5581. /* Slice: speedview_en:*/
  5582. /* 1: speed view enabled */
  5583. /* 0: speed view disabled */
  5584. #ifdef MRV_JPE_SPEEDVIEW_EN
  5585. #define MRV_JPE_SPEEDVIEW_EN_DISABLE 0 /* "0": JPEG Stream Encoding according to JPEG standard */
  5586. #define MRV_JPE_SPEEDVIEW_EN_ENABLE 1 /* "1": SpeedView JPEG Stream Encoding enabled */
  5587. #endif /* MRV_JPE_SPEEDVIEW_EN */
  5588. /* Slice: cont_mode:*/
  5589. /* Encoder continous mode */
  5590. /* "00": encoder stops at frame end (corresponds to former behavior)*/
  5591. /* "01": encoder starts automatically to encode the next frame */
  5592. /* "10": unused */
  5593. /* "11": encoder first generates next header and then encodes automatically the next frame */
  5594. /* These settings are checked after encoding one frame. They are not auto-reset by hardware.*/
  5595. #ifdef MRV_JPE_CONT_MODE
  5596. #define MRV_JPE_CONT_MODE_STOP 0 /* "00": encoder stops at frame end (corresponds to former behavior) */
  5597. #define MRV_JPE_CONT_MODE_NEXT 1 /* "01": encoder starts automatically to encode the next frame */
  5598. #define MRV_JPE_CONT_MODE_HEADER 3 /* "11": encoder first generates next header and then encodes automatically the next frame */
  5599. #endif /* MRV_JPE_CONT_MODE */
  5600. /*****************************************************************************/
  5601. /* MIPI Registers */
  5602. /*****************************************************************************/
  5603. /*****************************************************************************/
  5604. /**
  5605. * register: mipi_ctrl: global control register (0x0000)
  5606. *
  5607. *****************************************************************************/
  5608. /* Slice: S_ENABLE_CLK */
  5609. /* 1: enable sensor clock lane (DEFAULT)*/
  5610. /* 0: disable sensor clock lane */
  5611. #ifdef MRV_MIPI_S_ENABLE_CLK
  5612. #endif /* MRV_MIPI_S_ENABLE_CLK */
  5613. /* Slice: ERR_SOT_SYNC_HS_SKIP:*/
  5614. /* 1: data within the current transmission is skipped if ErrSotSyncHS is detected (default)*/
  5615. /* 0: ErrSotSyncHS does not affect transmission */
  5616. #ifdef MRV_MIPI_ERR_SOT_SYNC_HS_SKIP
  5617. #endif /* MRV_MIPI_ERR_SOT_SYNC_HS_SKIP */
  5618. /* Slice: ERR_SOT_HS_SKIP:*/
  5619. /* 1: data within the current transmission is skipped if ErrSotHS is detected */
  5620. /* 0: ErrSotHS does not affect transmission (default)*/
  5621. #ifdef MRV_MIPI_ERR_SOT_HS_SKIP
  5622. #endif /* MRV_MIPI_ERR_SOT_HS_SKIP */
  5623. /* Slice: NUM_LANES:*/
  5624. /* 00: Lane 1 is used;*/
  5625. /* 01: Lanes 1 and 2 are used;*/
  5626. /* 10: Lanes 1...3 are used;*/
  5627. /* 11: Lanes 1...4 are used */
  5628. #ifdef MRV_MIPI_NUM_LANES
  5629. #define MRV_MIPI_NUM_LANES_1 0 /* 00: Lane 1 is used */
  5630. #define MRV_MIPI_NUM_LANES_2 1 /* 01: Lanes 1 and 2 are used */
  5631. #define MRV_MIPI_NUM_LANES_3 2 /* 10: Lanes 1...3 are used */
  5632. #define MRV_MIPI_NUM_LANES_4 3 /* 11: Lanes 1...4 are used */
  5633. #endif /* MRV_MIPI_NUM_LANES */
  5634. /* Slice: SHUTDOWN_LANE:*/
  5635. /* Shutdown Lane Module. Content of this register is directly connected to the output signal shutdown[n-1:0]*/
  5636. #ifdef MRV_MIPI_SHUTDOWN_LANE
  5637. #define MRV_MIPI_SHUTDOWN_LANE_1 1 /* 0001: shutdown lane 1 */
  5638. #define MRV_MIPI_SHUTDOWN_LANE_2 2 /* 0010: shutdown lane 1 */
  5639. #define MRV_MIPI_SHUTDOWN_LANE_3 4 /* 0100: shutdown lane 1 */
  5640. #define MRV_MIPI_SHUTDOWN_LANE_4 8 /* 1000: shutdown lane 1 */
  5641. #endif /* MRV_MIPI_SHUTDOWN_LANE */
  5642. /* Slice: FLUSH_FIFO:*/
  5643. /* writing '1' resets the write- and read pointers of the additional data fifo.*/
  5644. #ifdef MRV_MIPI_FLUSH_FIFO
  5645. #endif /* MRV_MIPI_FLUSH_FIFO */
  5646. /* Slice: OUTPUT_ENA:*/
  5647. /* 1: output to add data fifo and to output interface is enabled */
  5648. #ifdef MRV_MIPI_OUTPUT_ENA
  5649. #endif /* MRV_MIPI_OUTPUT_ENA */
  5650. /*****************************************************************************/
  5651. /**
  5652. * register: mipi_status: global status register (0x0004)
  5653. *
  5654. *****************************************************************************/
  5655. /* Slice: S_ULP_ACTIVE_NOT_CLK:*/
  5656. /* sensor clock lane is in ULP state. This register is directly connected to the synchronized input signal "s_ulpsactivenotclk"*/
  5657. #ifdef MRV_MIPI_S_ULP_ACTIVE_NOT_CLK
  5658. #endif /* MRV_MIPI_S_ULP_ACTIVE_NOT_CLK */
  5659. /* Slice: S_STOPSTATE_CLK:*/
  5660. /* sensor clock lane is in stopstate. This register is directly connected to the synchronized input signal "s_stopstateclk"*/
  5661. #ifdef MRV_MIPI_S_STOPSTATE_CLK
  5662. #endif /* MRV_MIPI_S_STOPSTATE_CLK */
  5663. /* Slice: STOPSTATE:*/
  5664. /* Lane is in stopstate. This register is directly connected to the synchronized input signal stopstate[n-1:0]*/
  5665. #ifdef MRV_MIPI_STOPSTATE
  5666. #endif /* MRV_MIPI_STOPSTATE */
  5667. /* Slice: ADD_DATA_AVAIL:*/
  5668. /* 1: additional data fifo contains data */
  5669. /* 0: additional data fifo is empty */
  5670. #ifdef MRV_MIPI_ADD_DATA_AVAIL
  5671. #endif /* MRV_MIPI_ADD_DATA_AVAIL */
  5672. /*****************************************************************************/
  5673. /**
  5674. * register: mipi_imsc: Interrupt mask (0x00000008)
  5675. *
  5676. *****************************************************************************/
  5677. /* Slice: IMSC_GEN_SHORT_PACK:*/
  5678. /* enable interrupt (1) or mask out (0)*/
  5679. #ifndef MRV_MIPI_IMSC_GEN_SHORT_PACK
  5680. #define MRV_MIPI_IMSC_GEN_SHORT_PACK_MASK 0
  5681. #endif /* MRV_MIPI_IMSC_GEN_SHORT_PACK */
  5682. /* Slice: IMSC_ADD_DATA_FILL_LEVEL:*/
  5683. /* enable interrupt (1) or mask out (0)*/
  5684. #ifndef MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL
  5685. #define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_MASK 0
  5686. #endif /* MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL */
  5687. /* Slice: IMSC_ADD_DATA_OVFLW:*/
  5688. /* enable interrupt (1) or mask out (0)*/
  5689. #ifndef MRV_MIPI_IMSC_ADD_DATA_OVFLW
  5690. #endif /* MRV_MIPI_IMSC_ADD_DATA_OVFLW */
  5691. /* Slice: IMSC_FRAME_END:*/
  5692. /* enable interrupt (1) or mask out (0)*/
  5693. #ifndef MRV_MIPI_IMSC_FRAME_END
  5694. #define MRV_MIPI_IMSC_FRAME_END_MASK 0
  5695. #endif /* MRV_MIPI_IMSC_ADD_DATA_OVFLW */
  5696. /* Slice: IMSC_ERR_CS:*/
  5697. /* enable interrupt (1) or mask out (0)*/
  5698. #ifndef MRV_MIPI_IMSC_ERR_CS
  5699. #define MRV_MIPI_IMSC_ERR_CS_MASK 0
  5700. #endif /* MRV_MIPI_IMSC_ERR_CS */
  5701. /* Slice: IMSC_ERR_ECC1:*/
  5702. /* enable interrupt (1) or mask out (0)*/
  5703. #ifndef MRV_MIPI_IMSC_ERR_ECC1
  5704. #define MRV_MIPI_IMSC_ERR_ECC1_MASK 0
  5705. #endif /* MRV_MIPI_IMSC_ERR_ECC1 */
  5706. /* Slice: IMSC_ERR_ECC2:*/
  5707. /* enable interrupt (1) or mask out (0)*/
  5708. #ifndef MRV_MIPI_IMSC_ERR_ECC2
  5709. #define MRV_MIPI_IMSC_ERR_ECC2_MASK 0
  5710. #endif /* MRV_MIPI_IMSC_ERR_ECC2 */
  5711. /* Slice: IMSC_ERR_PROTOCOL:*/
  5712. /* enable interrupt (1) or mask out (0)*/
  5713. #ifndef MRV_MIPI_IMSC_ERR_PROTOCOL
  5714. #define MRV_MIPI_IMSC_ERR_PROTOCOL_MASK 0
  5715. #endif /* MRV_MIPI_IMSC_ERR_PROTOCOL */
  5716. /* Slice: IMSC_ERR_CONTROL:*/
  5717. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5718. #ifndef MRV_MIPI_IMSC_ERR_CONTROL
  5719. #define MRV_MIPI_IMSC_ERR_CONTROL_MASK 0
  5720. #endif /* MRV_MIPI_IMSC_ERR_CONTROL */
  5721. /* Slice: IMSC_ERR_EOT_SYNC:*/
  5722. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5723. #ifndef MRV_MIPI_IMSC_ERR_EOT_SYNC
  5724. #define MRV_MIPI_IMSC_ERR_EOT_SYNC_MASK 0
  5725. #endif /* MRV_MIPI_IMSC_ERR_EOT_SYNC */
  5726. /* Slice: IMSC_ERR_SOT_SYNC:*/
  5727. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5728. #ifndef MRV_MIPI_IMSC_ERR_SOT_SYNC
  5729. #define MRV_MIPI_IMSC_ERR_SOT_SYNC_MASK 0
  5730. #endif /* MRV_MIPI_IMSC_ERR_SOT_SYNC */
  5731. /* Slice: IMSC_ERR_SOT:*/
  5732. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5733. #ifndef MRV_MIPI_IMSC_ERR_SOT
  5734. #define MRV_MIPI_IMSC_ERR_SOT_MASK 0
  5735. #endif /* MRV_MIPI_IMSC_ERR_SOT */
  5736. /* Slice: IMSC_SYNC_FIFO_OVFLW:*/
  5737. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5738. #ifndef MRV_MIPI_IMSC_SYNC_FIFO_OVFLW
  5739. #define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_MASK 0
  5740. #endif /* MRV_MIPI_IMSC_SYNC_FIFO_OVFLW */
  5741. /* combination of all interrupt lines */
  5742. #define MRV_MIPI_IMSC_ALL_IRQS
  5743. #define MRV_MIPI_IMSC_ALL_IRQS_MASK \
  5744. (MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_MASK \
  5745. | MRV_MIPI_IMSC_ADD_DATA_OVFLW_MASK \
  5746. | MRV_MIPI_IMSC_FRAME_END_MASK \
  5747. | MRV_MIPI_IMSC_ERR_CS_MASK \
  5748. | MRV_MIPI_IMSC_ERR_ECC1_MASK \
  5749. | MRV_MIPI_IMSC_ERR_ECC2_MASK \
  5750. | MRV_MIPI_IMSC_ERR_PROTOCOL_MASK \
  5751. | MRV_MIPI_IMSC_ERR_CONTROL_MASK \
  5752. | MRV_MIPI_IMSC_ERR_EOT_SYNC_MASK \
  5753. | MRV_MIPI_IMSC_ERR_SOT_SYNC_MASK \
  5754. | MRV_MIPI_IMSC_ERR_SOT_MASK \
  5755. | MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_MASK \
  5756. )
  5757. #define MRV_MIPI_IMSC_ALL_IRQS_SHIFT 0
  5758. /*****************************************************************************/
  5759. /**
  5760. * register: mipi_ris: Raw interrupt status (0x0000000c)
  5761. *
  5762. *****************************************************************************/
  5763. /* Slice: RIS_GEN_SHORT_PACK:*/
  5764. /* enable interrupt (1) or mask out (0)*/
  5765. #ifndef MRV_MIPI_RIS_GEN_SHORT_PACK
  5766. #define MRV_MIPI_RIS_GEN_SHORT_PACK_MASK 0
  5767. #endif /* MRV_MIPI_RIS_GEN_SHORT_PACK */
  5768. /* Slice: RIS_ADD_DATA_FILL_LEVEL:*/
  5769. /* enable interrupt (1) or mask out (0)*/
  5770. #ifndef MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL
  5771. #define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_MASK 0
  5772. #endif /* MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL */
  5773. /* Slice: RIS_ADD_DATA_OVFLW:*/
  5774. /* enable interrupt (1) or mask out (0)*/
  5775. #ifndef MRV_MIPI_RIS_ADD_DATA_OVFLW
  5776. #endif /* MRV_MIPI_RIS_ADD_DATA_OVFLW */
  5777. /* Slice: RIS_FRAME_END:*/
  5778. /* enable interrupt (1) or mask out (0)*/
  5779. #ifndef MRV_MIPI_RIS_FRAME_END
  5780. #define MRV_MIPI_RIS_FRAME_END_MASK 0
  5781. #endif /* MRV_MIPI_RIS_ADD_DATA_OVFLW */
  5782. /* Slice: RIS_ERR_CS:*/
  5783. /* enable interrupt (1) or mask out (0)*/
  5784. #ifndef MRV_MIPI_RIS_ERR_CS
  5785. #define MRV_MIPI_RIS_ERR_CS_MASK 0
  5786. #endif /* MRV_MIPI_RIS_ERR_CS */
  5787. /* Slice: RIS_ERR_ECC1:*/
  5788. /* enable interrupt (1) or mask out (0)*/
  5789. #ifndef MRV_MIPI_RIS_ERR_ECC1
  5790. #define MRV_MIPI_RIS_ERR_ECC1_MASK 0
  5791. #endif /* MRV_MIPI_RIS_ERR_ECC1 */
  5792. /* Slice: RIS_ERR_ECC2:*/
  5793. /* enable interrupt (1) or mask out (0)*/
  5794. #ifndef MRV_MIPI_RIS_ERR_ECC2
  5795. #define MRV_MIPI_RIS_ERR_ECC2_MASK 0
  5796. #endif /* MRV_MIPI_RIS_ERR_ECC2 */
  5797. /* Slice: RIS_ERR_PROTOCOL:*/
  5798. /* enable interrupt (1) or mask out (0)*/
  5799. #ifndef MRV_MIPI_RIS_ERR_PROTOCOL
  5800. #define MRV_MIPI_RIS_ERR_PROTOCOL_MASK 0
  5801. #endif /* MRV_MIPI_RIS_ERR_PROTOCOL */
  5802. /* Slice: RIS_ERR_CONTROL:*/
  5803. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5804. #ifndef MRV_MIPI_RIS_ERR_CONTROL
  5805. #define MRV_MIPI_RIS_ERR_CONTROL_MASK 0
  5806. #endif /* MRV_MIPI_RIS_ERR_CONTROL */
  5807. /* Slice: RIS_ERR_EOT_SYNC:*/
  5808. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5809. #ifndef MRV_MIPI_RIS_ERR_EOT_SYNC
  5810. #define MRV_MIPI_RIS_ERR_EOT_SYNC_MASK 0
  5811. #endif /* MRV_MIPI_RIS_ERR_EOT_SYNC */
  5812. /* Slice: RIS_ERR_SOT_SYNC:*/
  5813. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5814. #ifndef MRV_MIPI_RIS_ERR_SOT_SYNC
  5815. #define MRV_MIPI_RIS_ERR_SOT_SYNC_MASK 0
  5816. #endif /* MRV_MIPI_RIS_ERR_SOT_SYNC */
  5817. /* Slice: RIS_ERR_SOT:*/
  5818. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5819. #ifndef MRV_MIPI_RIS_ERR_SOT
  5820. #define MRV_MIPI_RIS_ERR_SOT_MASK 0
  5821. #endif /* MRV_MIPI_RIS_ERR_SOT */
  5822. /* Slice: RIS_SYNC_FIFO_OVFLW:*/
  5823. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5824. #ifndef MRV_MIPI_RIS_SYNC_FIFO_OVFLW
  5825. #define MRV_MIPI_RIS_SYNC_FIFO_OVFLW_MASK 0
  5826. #endif /* MRV_MIPI_RIS_SYNC_FIFO_OVFLW */
  5827. /* combination of all interrupt lines */
  5828. #define MRV_MIPI_RIS_ALL_IRQS
  5829. #define MRV_MIPI_RIS_ALL_IRQS_MASK \
  5830. (MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_MASK \
  5831. | MRV_MIPI_RIS_ADD_DATA_OVFLW_MASK \
  5832. | MRV_MIPI_RIS_FRAME_END_MASK \
  5833. | MRV_MIPI_RIS_ERR_CS_MASK \
  5834. | MRV_MIPI_RIS_ERR_ECC1_MASK \
  5835. | MRV_MIPI_RIS_ERR_ECC2_MASK \
  5836. | MRV_MIPI_RIS_ERR_PROTOCOL_MASK \
  5837. | MRV_MIPI_RIS_ERR_CONTROL_MASK \
  5838. | MRV_MIPI_RIS_ERR_EOT_SYNC_MASK \
  5839. | MRV_MIPI_RIS_ERR_SOT_SYNC_MASK \
  5840. | MRV_MIPI_RIS_ERR_SOT_MASK \
  5841. | MRV_MIPI_RIS_SYNC_FIFO_OVFLW_MASK \
  5842. )
  5843. #define MRV_MIPI_RIS_ALL_IRQS_SHIFT 0
  5844. /*****************************************************************************/
  5845. /**
  5846. * register: mipi_mis: Masked interrupt status (0x00000010)
  5847. *
  5848. *****************************************************************************/
  5849. /* Slice: MIS_GEN_SHORT_PACK:*/
  5850. /* enable interrupt (1) or mask out (0)*/
  5851. #ifndef MRV_MIPI_MIS_GEN_SHORT_PACK
  5852. #define MRV_MIPI_MIS_GEN_SHORT_PACK_MASK 0
  5853. #endif /* MRV_MIPI_MIS_GEN_SHORT_PACK */
  5854. /* Slice: MIS_ADD_DATA_FILL_LEVEL:*/
  5855. /* enable interrupt (1) or mask out (0)*/
  5856. #ifndef MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL
  5857. #define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_MASK 0
  5858. #endif /* MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL */
  5859. /* Slice: MIS_ADD_DATA_OVFLW:*/
  5860. /* enable interrupt (1) or mask out (0)*/
  5861. #ifndef MRV_MIPI_MIS_ADD_DATA_OVFLW
  5862. #endif /* MRV_MIPI_MIS_ADD_DATA_OVFLW */
  5863. /* Slice: MIS_FRAME_END:*/
  5864. /* enable interrupt (1) or mask out (0)*/
  5865. #ifndef MRV_MIPI_MIS_FRAME_END
  5866. #define MRV_MIPI_MIS_FRAME_END_MASK 0
  5867. #endif /* MRV_MIPI_MIS_ADD_DATA_OVFLW */
  5868. /* Slice: MIS_ERR_CS:*/
  5869. /* enable interrupt (1) or mask out (0)*/
  5870. #ifndef MRV_MIPI_MIS_ERR_CS
  5871. #define MRV_MIPI_MIS_ERR_CS_MASK 0
  5872. #endif /* MRV_MIPI_MIS_ERR_CS */
  5873. /* Slice: MIS_ERR_ECC1:*/
  5874. /* enable interrupt (1) or mask out (0)*/
  5875. #ifndef MRV_MIPI_MIS_ERR_ECC1
  5876. #define MRV_MIPI_MIS_ERR_ECC1_MASK 0
  5877. #endif /* MRV_MIPI_MIS_ERR_ECC1 */
  5878. /* Slice: MIS_ERR_ECC2:*/
  5879. /* enable interrupt (1) or mask out (0)*/
  5880. #ifndef MRV_MIPI_MIS_ERR_ECC2
  5881. #define MRV_MIPI_MIS_ERR_ECC2_MASK 0
  5882. #endif /* MRV_MIPI_MIS_ERR_ECC2 */
  5883. /* Slice: MIS_ERR_PROTOCOL:*/
  5884. /* enable interrupt (1) or mask out (0)*/
  5885. #ifndef MRV_MIPI_MIS_ERR_PROTOCOL
  5886. #define MRV_MIPI_MIS_ERR_PROTOCOL_MASK 0
  5887. #endif /* MRV_MIPI_MIS_ERR_PROTOCOL */
  5888. /* Slice: MIS_ERR_CONTROL:*/
  5889. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5890. #ifndef MRV_MIPI_MIS_ERR_CONTROL
  5891. #define MRV_MIPI_MIS_ERR_CONTROL_MASK 0
  5892. #endif /* MRV_MIPI_MIS_ERR_CONTROL */
  5893. /* Slice: MIS_ERR_EOT_SYNC:*/
  5894. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5895. #ifndef MRV_MIPI_MIS_ERR_EOT_SYNC
  5896. #define MRV_MIPI_MIS_ERR_EOT_SYNC_MASK 0
  5897. #endif /* MRV_MIPI_MIS_ERR_EOT_SYNC */
  5898. /* Slice: MIS_ERR_SOT_SYNC:*/
  5899. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5900. #ifndef MRV_MIPI_MIS_ERR_SOT_SYNC
  5901. #define MRV_MIPI_MIS_ERR_SOT_SYNC_MASK 0
  5902. #endif /* MRV_MIPI_MIS_ERR_SOT_SYNC */
  5903. /* Slice: MIS_ERR_SOT:*/
  5904. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5905. #ifndef MRV_MIPI_MIS_ERR_SOT
  5906. #define MRV_MIPI_MIS_ERR_SOT_MASK 0
  5907. #endif /* MRV_MIPI_MIS_ERR_SOT */
  5908. /* Slice: MIS_SYNC_FIFO_OVFLW:*/
  5909. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5910. #ifndef MRV_MIPI_MIS_SYNC_FIFO_OVFLW
  5911. #define MRV_MIPI_MIS_SYNC_FIFO_OVFLW_MASK 0
  5912. #endif /* MRV_MIPI_MIS_SYNC_FIFO_OVFLW */
  5913. /* combination of all interrupt lines */
  5914. #define MRV_MIPI_MIS_ALL_IRQS
  5915. #define MRV_MIPI_MIS_ALL_IRQS_MASK \
  5916. (MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_MASK \
  5917. | MRV_MIPI_MIS_ADD_DATA_OVFLW_MASK \
  5918. | MRV_MIPI_MIS_FRAME_END_MASK \
  5919. | MRV_MIPI_MIS_ERR_CS_MASK \
  5920. | MRV_MIPI_MIS_ERR_ECC1_MASK \
  5921. | MRV_MIPI_MIS_ERR_ECC2_MASK \
  5922. | MRV_MIPI_MIS_ERR_PROTOCOL_MASK \
  5923. | MRV_MIPI_MIS_ERR_CONTROL_MASK \
  5924. | MRV_MIPI_MIS_ERR_EOT_SYNC_MASK \
  5925. | MRV_MIPI_MIS_ERR_SOT_SYNC_MASK \
  5926. | MRV_MIPI_MIS_ERR_SOT_MASK \
  5927. | MRV_MIPI_MIS_SYNC_FIFO_OVFLW_MASK \
  5928. )
  5929. #define MRV_MIPI_MIS_ALL_IRQS_SHIFT 0
  5930. /*****************************************************************************/
  5931. /**
  5932. * register: mipi_icr: Interrupt clear register (0x00000014)
  5933. *
  5934. *****************************************************************************/
  5935. /* Slice: ICR_GEN_SHORT_PACK:*/
  5936. /* enable interrupt (1) or mask out (0)*/
  5937. #ifndef MRV_MIPI_ICR_GEN_SHORT_PACK
  5938. #define MRV_MIPI_ICR_GEN_SHORT_PACK_MASK 0
  5939. #endif /* MRV_MIPI_ICR_GEN_SHORT_PACK */
  5940. /* Slice: ICR_ADD_DATA_FILL_LEVEL:*/
  5941. /* enable interrupt (1) or mask out (0)*/
  5942. #ifndef MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL
  5943. #define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_MASK 0
  5944. #endif /* MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL */
  5945. /* Slice: ICR_ADD_DATA_OVFLW:*/
  5946. /* enable interrupt (1) or mask out (0)*/
  5947. #ifndef MRV_MIPI_ICR_ADD_DATA_OVFLW
  5948. #endif /* MRV_MIPI_ICR_ADD_DATA_OVFLW */
  5949. /* Slice: ICR_FRAME_END:*/
  5950. /* enable interrupt (1) or mask out (0)*/
  5951. #ifndef MRV_MIPI_ICR_FRAME_END
  5952. #define MRV_MIPI_ICR_FRAME_END_MASK 0
  5953. #endif /* MRV_MIPI_ICR_ADD_DATA_OVFLW */
  5954. /* Slice: ICR_ERR_CS:*/
  5955. /* enable interrupt (1) or mask out (0)*/
  5956. #ifndef MRV_MIPI_ICR_ERR_CS
  5957. #define MRV_MIPI_ICR_ERR_CS_MASK 0
  5958. #endif /* MRV_MIPI_ICR_ERR_CS */
  5959. /* Slice: ICR_ERR_ECC1:*/
  5960. /* enable interrupt (1) or mask out (0)*/
  5961. #ifndef MRV_MIPI_ICR_ERR_ECC1
  5962. #define MRV_MIPI_ICR_ERR_ECC1_MASK 0
  5963. #endif /* MRV_MIPI_ICR_ERR_ECC1 */
  5964. /* Slice: ICR_ERR_ECC2:*/
  5965. /* enable interrupt (1) or mask out (0)*/
  5966. #ifndef MRV_MIPI_ICR_ERR_ECC2
  5967. #define MRV_MIPI_ICR_ERR_ECC2_MASK 0
  5968. #endif /* MRV_MIPI_ICR_ERR_ECC2 */
  5969. /* Slice: ICR_ERR_PROTOCOL:*/
  5970. /* enable interrupt (1) or mask out (0)*/
  5971. #ifndef MRV_MIPI_ICR_ERR_PROTOCOL
  5972. #define MRV_MIPI_ICR_ERR_PROTOCOL_MASK 0
  5973. #endif /* MRV_MIPI_ICR_ERR_PROTOCOL */
  5974. /* Slice: ICR_ERR_CONTROL:*/
  5975. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5976. #ifndef MRV_MIPI_ICR_ERR_CONTROL
  5977. #define MRV_MIPI_ICR_ERR_CONTROL_MASK 0
  5978. #endif /* MRV_MIPI_ICR_ERR_CONTROL */
  5979. /* Slice: ICR_ERR_EOT_SYNC:*/
  5980. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5981. #ifndef MRV_MIPI_ICR_ERR_EOT_SYNC
  5982. #define MRV_MIPI_ICR_ERR_EOT_SYNC_MASK 0
  5983. #endif /* MRV_MIPI_ICR_ERR_EOT_SYNC */
  5984. /* Slice: ICR_ERR_SOT_SYNC:*/
  5985. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5986. #ifndef MRV_MIPI_ICR_ERR_SOT_SYNC
  5987. #define MRV_MIPI_ICR_ERR_SOT_SYNC_MASK 0
  5988. #endif /* MRV_MIPI_ICR_ERR_SOT_SYNC */
  5989. /* Slice: ICR_ERR_SOT:*/
  5990. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5991. #ifndef MRV_MIPI_ICR_ERR_SOT
  5992. #define MRV_MIPI_ICR_ERR_SOT_MASK 0
  5993. #endif /* MRV_MIPI_ICR_ERR_SOT */
  5994. /* Slice: ICR_SYNC_FIFO_OVFLW:*/
  5995. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  5996. #ifndef MRV_MIPI_ICR_SYNC_FIFO_OVFLW
  5997. #define MRV_MIPI_ICR_SYNC_FIFO_OVFLW_MASK 0
  5998. #endif /* MRV_MIPI_ICR_SYNC_FIFO_OVFLW */
  5999. /* combination of all interrupt lines */
  6000. #define MRV_MIPI_ICR_ALL_IRQS
  6001. #define MRV_MIPI_ICR_ALL_IRQS_MASK \
  6002. (MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_MASK \
  6003. | MRV_MIPI_ICR_ADD_DATA_OVFLW_MASK \
  6004. | MRV_MIPI_ICR_FRAME_END_MASK \
  6005. | MRV_MIPI_ICR_ERR_CS_MASK \
  6006. | MRV_MIPI_ICR_ERR_ECC1_MASK \
  6007. | MRV_MIPI_ICR_ERR_ECC2_MASK \
  6008. | MRV_MIPI_ICR_ERR_PROTOCOL_MASK \
  6009. | MRV_MIPI_ICR_ERR_CONTROL_MASK \
  6010. | MRV_MIPI_ICR_ERR_EOT_SYNC_MASK \
  6011. | MRV_MIPI_ICR_ERR_SOT_SYNC_MASK \
  6012. | MRV_MIPI_ICR_ERR_SOT_MASK \
  6013. | MRV_MIPI_ICR_SYNC_FIFO_OVFLW_MASK \
  6014. )
  6015. #define MRV_MIPI_ICR_ALL_IRQS_SHIFT 0
  6016. /*****************************************************************************/
  6017. /**
  6018. * register: mipi_isr: Interrupt set register (0x00000018)
  6019. *
  6020. *****************************************************************************/
  6021. /* Slice: ISR_GEN_SHORT_PACK:*/
  6022. /* enable interrupt (1) or mask out (0)*/
  6023. #ifndef MRV_MIPI_ISR_GEN_SHORT_PACK
  6024. #define MRV_MIPI_ISR_GEN_SHORT_PACK_MASK 0
  6025. #endif /* MRV_MIPI_ISR_GEN_SHORT_PACK */
  6026. /* Slice: ISR_ADD_DATA_FILL_LEVEL:*/
  6027. /* enable interrupt (1) or mask out (0)*/
  6028. #ifndef MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL
  6029. #define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_MASK 0
  6030. #endif /* MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL */
  6031. /* Slice: ISR_ADD_DATA_OVFLW:*/
  6032. /* enable interrupt (1) or mask out (0)*/
  6033. #ifndef MRV_MIPI_ISR_ADD_DATA_OVFLW
  6034. #endif /* MRV_MIPI_ISR_ADD_DATA_OVFLW */
  6035. /* Slice: ISR_FRAME_END:*/
  6036. /* enable interrupt (1) or mask out (0)*/
  6037. #ifndef MRV_MIPI_ISR_FRAME_END
  6038. #define MRV_MIPI_ISR_FRAME_END_MASK 0
  6039. #endif /* MRV_MIPI_ISR_ADD_DATA_OVFLW */
  6040. /* Slice: ISR_ERR_CS:*/
  6041. /* enable interrupt (1) or mask out (0)*/
  6042. #ifndef MRV_MIPI_ISR_ERR_CS
  6043. #define MRV_MIPI_ISR_ERR_CS_MASK 0
  6044. #endif /* MRV_MIPI_ISR_ERR_CS */
  6045. /* Slice: ISR_ERR_ECC1:*/
  6046. /* enable interrupt (1) or mask out (0)*/
  6047. #ifndef MRV_MIPI_ISR_ERR_ECC1
  6048. #define MRV_MIPI_ISR_ERR_ECC1_MASK 0
  6049. #endif /* MRV_MIPI_ISR_ERR_ECC1 */
  6050. /* Slice: ISR_ERR_ECC2:*/
  6051. /* enable interrupt (1) or mask out (0)*/
  6052. #ifndef MRV_MIPI_ISR_ERR_ECC2
  6053. #define MRV_MIPI_ISR_ERR_ECC2_MASK 0
  6054. #endif /* MRV_MIPI_ISR_ERR_ECC2 */
  6055. /* Slice: ISR_ERR_PROTOCOL:*/
  6056. /* enable interrupt (1) or mask out (0)*/
  6057. #ifndef MRV_MIPI_ISR_ERR_PROTOCOL
  6058. #define MRV_MIPI_ISR_ERR_PROTOCOL_MASK 0
  6059. #endif /* MRV_MIPI_ISR_ERR_PROTOCOL */
  6060. /* Slice: ISR_ERR_CONTROL:*/
  6061. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  6062. #ifndef MRV_MIPI_ISR_ERR_CONTROL
  6063. #define MRV_MIPI_ISR_ERR_CONTROL_MASK 0
  6064. #endif /* MRV_MIPI_ISR_ERR_CONTROL */
  6065. /* Slice: ISR_ERR_EOT_SYNC:*/
  6066. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  6067. #ifndef MRV_MIPI_ISR_ERR_EOT_SYNC
  6068. #define MRV_MIPI_ISR_ERR_EOT_SYNC_MASK 0
  6069. #endif /* MRV_MIPI_ISR_ERR_EOT_SYNC */
  6070. /* Slice: ISR_ERR_SOT_SYNC:*/
  6071. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  6072. #ifndef MRV_MIPI_ISR_ERR_SOT_SYNC
  6073. #define MRV_MIPI_ISR_ERR_SOT_SYNC_MASK 0
  6074. #endif /* MRV_MIPI_ISR_ERR_SOT_SYNC */
  6075. /* Slice: ISR_ERR_SOT:*/
  6076. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  6077. #ifndef MRV_MIPI_ISR_ERR_SOT
  6078. #define MRV_MIPI_ISR_ERR_SOT_MASK 0
  6079. #endif /* MRV_MIPI_ISR_ERR_SOT */
  6080. /* Slice: ISR_SYNC_FIFO_OVFLW:*/
  6081. /* enable interrupt (1) or mask out (0) (one bit for each lane)*/
  6082. #ifndef MRV_MIPI_ISR_SYNC_FIFO_OVFLW
  6083. #define MRV_MIPI_ISR_SYNC_FIFO_OVFLW_MASK 0
  6084. #endif /* MRV_MIPI_ISR_SYNC_FIFO_OVFLW */
  6085. /* combination of all interrupt lines */
  6086. #define MRV_MIPI_ISR_ALL_IRQS
  6087. #define MRV_MIPI_ISR_ALL_IRQS_MASK \
  6088. (MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_MASK \
  6089. | MRV_MIPI_ISR_ADD_DATA_OVFLW_MASK \
  6090. | MRV_MIPI_ISR_FRAME_END_MASK \
  6091. | MRV_MIPI_ISR_ERR_CS_MASK \
  6092. | MRV_MIPI_ISR_ERR_ECC1_MASK \
  6093. | MRV_MIPI_ISR_ERR_ECC2_MASK \
  6094. | MRV_MIPI_ISR_ERR_PROTOCOL_MASK \
  6095. | MRV_MIPI_ISR_ERR_CONTROL_MASK \
  6096. | MRV_MIPI_ISR_ERR_EOT_SYNC_MASK \
  6097. | MRV_MIPI_ISR_ERR_SOT_SYNC_MASK \
  6098. | MRV_MIPI_ISR_ERR_SOT_MASK \
  6099. | MRV_MIPI_ISR_SYNC_FIFO_OVFLW_MASK \
  6100. )
  6101. #define MRV_MIPI_ISR_ALL_IRQS_SHIFT 0
  6102. /*****************************************************************************/
  6103. /**
  6104. * register: mipi_cur_data_id: Current Data Identifier (0x0000001c)
  6105. *
  6106. *****************************************************************************/
  6107. /* Slice: VIRTUAL_CHANNEL:*/
  6108. /* virtual channel of currently received packet */
  6109. #ifdef MRV_MIPI_VIRTUAL_CHANNEL
  6110. #endif /* MRV_MIPI_VIRTUAL_CHANNEL */
  6111. /* Slice: DATA_TYPE:*/
  6112. /* data type of currently received packet */
  6113. #ifdef MRV_MIPI_DATA_TYPE
  6114. #endif /* MRV_MIPI_DATA_TYPE */
  6115. /*****************************************************************************/
  6116. /**
  6117. * register: mipi_img_data_sel: Image Data Selector (0x00000020)
  6118. *
  6119. *****************************************************************************/
  6120. /* Slice: VIRTUAL_CHANNEL_SEL:*/
  6121. /* virtual channel selector for image data output */
  6122. #ifdef MRV_MIPI_VIRTUAL_CHANNEL_SEL
  6123. #endif /* MRV_MIPI_VIRTUAL_CHANNEL_SEL */
  6124. /* Slice: DATA_TYPE_SEL:*/
  6125. /* data type selector for image data output:*/
  6126. /* 0x08...0x0F: generic short packets */
  6127. /* 0x12: embedded 8-bit data */
  6128. /* 0x18: YUV 420 8-bit */
  6129. /* 0x19: YUV 420 10-bit */
  6130. /* 0x1A: Legacy YUV 420 8-bit */
  6131. /* 0x1C: YUV 420 8-bit (CSPS)*/
  6132. /* 0x1D: YUV 420 10-bit (CSPS)*/
  6133. /* 0x1E: YUV 422 8-bit */
  6134. /* 0x1F: YUV 422 10-bit */
  6135. /* 0x20: RGB 444 */
  6136. /* 0x21: RGB 555 */
  6137. /* 0x22: RGB 565 */
  6138. /* 0x23: RGB 666 */
  6139. /* 0x24: RGB 888 */
  6140. /* 0x28: RAW 6 */
  6141. /* 0x29: RAW 7 */
  6142. /* 0x2A: RAW 8 */
  6143. /* 0x2B: RAW 10 */
  6144. /* 0x2C: RAW 12 */
  6145. /* 0x30...0x37: User Defined Byte-based data */
  6146. #ifdef MRV_MIPI_DATA_TYPE_SEL
  6147. #define MRV_MIPI_DATA_TYPE_SEL_YUV420_8BIT 24 /* 0x18 YUV 420 8-bit */
  6148. #define MRV_MIPI_DATA_TYPE_SEL_YUV420_10BIT 25 /* 0x19 YUV 420 10-bit */
  6149. #define MRV_MIPI_DATA_TYPE_SEL_YUV420_8BIT_LEGACY 26 /* 0x1A Legacy YUV 420 8-bit */
  6150. #define MRV_MIPI_DATA_TYPE_SEL_YUV420_8BIT_CSPS 28 /* 0x1C YUV 420 8-bit (CSPS) */
  6151. #define MRV_MIPI_DATA_TYPE_SEL_YUV420_10BIT_CSPS 29 /* 0x1D YUV 420 10-bit (CSPS) */
  6152. #define MRV_MIPI_DATA_TYPE_SEL_YUV422_8BIT 30 /* 0x1E YUV 422 8-bit */
  6153. #define MRV_MIPI_DATA_TYPE_SEL_YUV422_10BIT 31 /* 0x1F YUV 422 10-bit */
  6154. #define MRV_MIPI_DATA_TYPE_SEL_RGB444 32 /* 0x20 RGB 444 */
  6155. #define MRV_MIPI_DATA_TYPE_SEL_RGB555 33 /* 0x21 RGB 555 */
  6156. #define MRV_MIPI_DATA_TYPE_SEL_RGB565 34 /* 0x22 RGB 565 */
  6157. #define MRV_MIPI_DATA_TYPE_SEL_RGB666 35 /* 0x23 RGB 666 */
  6158. #define MRV_MIPI_DATA_TYPE_SEL_RGB888 36 /* 0x24 RGB 888 */
  6159. #define MRV_MIPI_DATA_TYPE_SEL_RAW6 40 /* 0x28 RAW 6 */
  6160. #define MRV_MIPI_DATA_TYPE_SEL_RAW7 41 /* 0x29 RAW 7 */
  6161. #define MRV_MIPI_DATA_TYPE_SEL_RAW8 42 /* 0x2A RAW 8 */
  6162. #define MRV_MIPI_DATA_TYPE_SEL_RAW10 43 /* 0x2B RAW 10 */
  6163. #define MRV_MIPI_DATA_TYPE_SEL_RAW12 44 /* 0x2C RAW 12 */
  6164. #define MRV_MIPI_DATA_TYPE_SEL_USER1 48 /* 0x30...0x37 User Defined Byte-based data */
  6165. #define MRV_MIPI_DATA_TYPE_SEL_USER2 49 /* 0x30...0x37 User Defined Byte-based data */
  6166. #define MRV_MIPI_DATA_TYPE_SEL_USER3 50 /* 0x30...0x37 User Defined Byte-based data */
  6167. #define MRV_MIPI_DATA_TYPE_SEL_USER4 51 /* 0x30...0x37 User Defined Byte-based data */
  6168. #define MRV_MIPI_DATA_TYPE_SEL_USER5 52 /* 0x30...0x37 User Defined Byte-based data */
  6169. #define MRV_MIPI_DATA_TYPE_SEL_USER6 53 /* 0x30...0x37 User Defined Byte-based data */
  6170. #define MRV_MIPI_DATA_TYPE_SEL_USER7 54 /* 0x30...0x37 User Defined Byte-based data */
  6171. #define MRV_MIPI_DATA_TYPE_SEL_USER8 55 /* 0x30...0x37 User Defined Byte-based data */
  6172. #endif /* MRV_MIPI_DATA_TYPE_SEL */
  6173. /*****************************************************************************/
  6174. /**
  6175. * register: mipi_add_data_sel_1: Additional Data Selector 1 (0x00000024)
  6176. *
  6177. *****************************************************************************/
  6178. /* Slice: ADD_DATA_VC_1:*/
  6179. /* virtual channel selector for additional data output */
  6180. #ifdef MRV_MIPI_ADD_DATA_VC_1
  6181. #endif /* MRV_MIPI_ADD_DATA_VC_1 */
  6182. /* Slice: ADD_DATA_TYPE_1:*/
  6183. /* data type selector for additional data output */
  6184. #ifdef MRV_MIPI_ADD_DATA_TYPE_1
  6185. #endif /* MRV_MIPI_ADD_DATA_TYPE_1 */
  6186. /*****************************************************************************/
  6187. /**
  6188. * register: mipi_add_data_sel_2: Additional Data Selector 2 (0x00000028)
  6189. *
  6190. *****************************************************************************/
  6191. /* Slice: ADD_DATA_VC_2:*/
  6192. /* virtual channel selector for additional data output */
  6193. #ifdef MRV_MIPI_ADD_DATA_VC_2
  6194. #endif /* MRV_MIPI_ADD_DATA_VC_2 */
  6195. /* Slice: ADD_DATA_TYPE_2:*/
  6196. /* data type selector for additional data output */
  6197. #ifdef MRV_MIPI_ADD_DATA_TYPE_2
  6198. #endif /* MRV_MIPI_ADD_DATA_TYPE_2 */
  6199. /*****************************************************************************/
  6200. /**
  6201. * register: mipi_add_data_sel_3: Additional Data Selector 3 (0x0000002c)
  6202. *
  6203. *****************************************************************************/
  6204. /* Slice: ADD_DATA_VC_3:*/
  6205. /* virtual channel selector for additional data output */
  6206. #ifdef MRV_MIPI_ADD_DATA_VC_3
  6207. #endif /* MRV_MIPI_ADD_DATA_VC_3 */
  6208. /* Slice: ADD_DATA_TYPE_3:*/
  6209. /* data type selector for additional data output */
  6210. #ifdef MRV_MIPI_ADD_DATA_TYPE_3
  6211. #endif /* MRV_MIPI_ADD_DATA_TYPE_3 */
  6212. /*****************************************************************************/
  6213. /**
  6214. * register: mipi_add_data_sel_4: Additional Data Selector 4 (0x00000030)
  6215. *
  6216. *****************************************************************************/
  6217. /* Slice: ADD_DATA_VC_4:*/
  6218. /* virtual channel selector for additional data output */
  6219. #ifdef MRV_MIPI_ADD_DATA_VC_4
  6220. #endif /* MRV_MIPI_ADD_DATA_VC_4 */
  6221. /* Slice: ADD_DATA_TYPE_4:*/
  6222. /* data type selector for additional data output */
  6223. #ifdef MRV_MIPI_ADD_DATA_TYPE_4
  6224. #endif /* MRV_MIPI_ADD_DATA_TYPE_4 */
  6225. /*****************************************************************************/
  6226. /**
  6227. * register: mipi_add_data_fifo: Additional Data Fifo (0x00000034)
  6228. *
  6229. *****************************************************************************/
  6230. /* Slice: ADD_DATA_FIFO:*/
  6231. /* lowest 4 bytes in additional data fifo;*/
  6232. /* reading increments fifo read pointer.*/
  6233. /* First embedded data byte will be written to bits 7:0 of 32-bit data word, second data byte written to 15:8 etc.*/
  6234. #ifdef MRV_MIPI_ADD_DATA_FIFO
  6235. #endif /* MRV_MIPI_ADD_DATA_FIFO */
  6236. /*****************************************************************************/
  6237. /**
  6238. * register: mipi_add_data_fill_level: additional data fifo fill level
  6239. * (0x00000038)
  6240. *
  6241. *****************************************************************************/
  6242. /* Slice: ADD_DATA_FILL_LEVEL:*/
  6243. /* FIFO level in dwords for triggering the FILL_LEVEL interrupt,*/
  6244. /* must be 32-bit aligned (bit 0 and bit 1 are hard wired to "00")*/
  6245. #ifdef MRV_MIPI_ADD_DATA_FILL_LEVEL
  6246. #endif /* MRV_MIPI_ADD_DATA_FILL_LEVEL */
  6247. /*****************************************************************************/
  6248. /**
  6249. * register: mipi_compressed_mode: controls processing of compressed raw data
  6250. * types (0x0000003c)
  6251. *
  6252. *****************************************************************************/
  6253. /* Slice: predictor_sel:*/
  6254. /* predictor to be used:*/
  6255. /* 0: predictor 1 */
  6256. /* 1: predictor 2 */
  6257. #ifdef MRV_MIPI_PREDICTOR_SEL
  6258. #define MRV_MIPI_PREDICTOR_SEL_1 0 /* 0: predictor 1 */
  6259. #define MRV_MIPI_PREDICTOR_SEL_2 1 /* 1: predictor 2 */
  6260. #endif /* MRV_MIPI_PREDICTOR_SEL */
  6261. /* Slice: MRV_MIPI_COMP_SCHEME:*/
  6262. /* Compressed raw data types */
  6263. /* 000: 12-8-12 */
  6264. /* 001: 12-8-12 */
  6265. /* 010: 12-8-12 */
  6266. /* 011: 10-8-10 */
  6267. /* 100: 10-7-10 */
  6268. /* 101: 10-6-10 */
  6269. #ifdef MRV_MIPI_COMP_SCHEME
  6270. #define MRV_MIPI_COMP_SCHEME_12_8_12 0 /* 000: 12-8-12 */
  6271. #define MRV_MIPI_COMP_SCHEME_12_7_12 1 /* 001: 12-8-12 */
  6272. #define MRV_MIPI_COMP_SCHEME_12_6_12 2 /* 010: 12-8-12 */
  6273. #define MRV_MIPI_COMP_SCHEME_10_8_10 3 /* 011: 10-8-10 */
  6274. #define MRV_MIPI_COMP_SCHEME_10_7_10 4 /* 100: 10-7-10 */
  6275. #define MRV_MIPI_COMP_SCHEME_10_6_10 5 /* 101: 10-6-10 */
  6276. #endif /* MRV_MIPI_COMP_SCHEME */
  6277. /* Slice: compress_en:*/
  6278. /* 1: enable compressed mode processing */
  6279. /* 0: disable compressed mode */
  6280. #ifdef MRV_MIPI_COMPRESS_EN
  6281. #endif /* MRV_MIPI_COMPRESS_EN */
  6282. /*****************************************************************************/
  6283. /* ISP Image Stabilization Registers */
  6284. /*****************************************************************************/
  6285. /*****************************************************************************/
  6286. /**
  6287. * register: isp_is_ctrl: Image Stabilization Control Register (0x00000000)
  6288. *
  6289. *****************************************************************************/
  6290. /* Slice: is_en:*/
  6291. /* 1: image stabilization switched on */
  6292. /* 0: image stabilization switched off */
  6293. #ifdef MRV_IS_IS_EN
  6294. #define MRV_IS_IS_EN_PROCESS 1
  6295. #define MRV_IS_IS_EN_BYPASS 0
  6296. #endif /* MRV_IS_IS_EN */
  6297. /*****************************************************************************/
  6298. /**
  6299. * register: isp_is_recenter: Recenter register (0x00000004)
  6300. *
  6301. *****************************************************************************/
  6302. /* Slice: is_recenter:*/
  6303. /* 000: recenter feature switched off */
  6304. /* 1..7: recentering by (cur_h/v_offs-H/V_OFFS)/2^RECENTER */
  6305. #ifdef MRV_IS_IS_RECENTER
  6306. #define MRV_IS_IS_RECENTER_MAX (MRV_IS_IS_RECENTER_MASK >> MRV_IS_IS_RECENTER_SHIFT)
  6307. #endif /* MRV_IS_IS_RECENTER */
  6308. /*****************************************************************************/
  6309. /**
  6310. * register: isp_is_h_offs: Horizontal offset of output window (0x00000008)
  6311. *
  6312. *****************************************************************************/
  6313. /* Slice: is_h_offs:*/
  6314. /* horizontal picture offset in pixel */
  6315. #ifdef MRV_IS_IS_H_OFFS
  6316. #define MRV_IS_IS_H_OFFS_MAX (MRV_IS_IS_H_OFFS_MASK >> MRV_IS_IS_H_OFFS_SHIFT)
  6317. #endif /* MRV_IS_IS_H_OFFS */
  6318. /*****************************************************************************/
  6319. /**
  6320. * register: isp_is_v_offs: Vertical offset of output window (0x0000000c)
  6321. *
  6322. *****************************************************************************/
  6323. /* Slice: is_v_offs:*/
  6324. /* vertical picture offset in lines */
  6325. #ifdef MRV_IS_IS_V_OFFS
  6326. #define MRV_IS_IS_V_OFFS_MAX (MRV_IS_IS_V_OFFS_MASK >> MRV_IS_IS_V_OFFS_SHIFT)
  6327. #endif /* MRV_IS_IS_V_OFFS */
  6328. /*****************************************************************************/
  6329. /**
  6330. * register: isp_is_h_size: Output horizontal picture size (0x00000010)
  6331. *
  6332. *****************************************************************************/
  6333. /* Slice: is_h_size:*/
  6334. /* horizontal picture size in pixel */
  6335. /* if ISP_MODE is set to */
  6336. /* 001-(ITU-R BT.656 YUV),*/
  6337. /* 010-(ITU-R BT.601 YUV),*/
  6338. /* 011-(ITU-R BT.601 Bayer RGB),*/
  6339. /* 101-(ITU-R BT.656 Bayer RGB)*/
  6340. /* only even numbers are accepted, because complete quadruples of YUYV(YCbYCr)*/
  6341. /* are needed for the following modules. If an odd size is programmed the value */
  6342. /* will be truncated to even size.*/
  6343. #ifdef MRV_IS_IS_H_SIZE
  6344. #define MRV_IS_IS_H_SIZE_MAX (MRV_IS_IS_H_SIZE_MASK >> MRV_IS_IS_H_SIZE_SHIFT)
  6345. #endif /* MRV_IS_IS_H_SIZE */
  6346. /*****************************************************************************/
  6347. /**
  6348. * register: isp_is_v_size: Output vertical picture size (0x00000014)
  6349. *
  6350. *****************************************************************************/
  6351. /* Slice: is_v_size:*/
  6352. /* vertical picture size in lines */
  6353. #ifdef MRV_IS_IS_V_SIZE
  6354. #define MRV_IS_IS_V_SIZE_MAX (MRV_IS_IS_V_SIZE_MASK >> MRV_IS_IS_V_SIZE_SHIFT)
  6355. #endif /* MRV_IS_IS_V_SIZE */
  6356. /*****************************************************************************/
  6357. /**
  6358. * register: isp_is_max_dx: Maximum Horizontal Displacement (0x00000018)
  6359. *
  6360. *****************************************************************************/
  6361. /* Slice: is_max_dx:*/
  6362. /* maximum allowed accumulated horizontal displacement in pixels */
  6363. #ifdef MRV_IS_IS_MAX_DX
  6364. #define MRV_IS_IS_MAX_DX_MAX (MRV_IS_IS_MAX_DX_MASK >> MRV_IS_IS_MAX_DX_SHIFT)
  6365. #endif /* MRV_IS_IS_MAX_DX */
  6366. /*****************************************************************************/
  6367. /**
  6368. * register: isp_is_max_dy: Maximum Vertical Displacement (0x0000001c)
  6369. *
  6370. *****************************************************************************/
  6371. /* Slice: is_max_dy:*/
  6372. /* maximum allowed accumulated vertical displacement in lines */
  6373. #ifdef MRV_IS_IS_MAX_DY
  6374. #define MRV_IS_IS_MAX_DY_MAX (MRV_IS_IS_MAX_DY_MASK >> MRV_IS_IS_MAX_DY_SHIFT)
  6375. #endif /* MRV_IS_IS_MAX_DY */
  6376. /*****************************************************************************/
  6377. /**
  6378. * register: isp_is_displace: Camera displacement (0x00000020)
  6379. *
  6380. *****************************************************************************/
  6381. /* Slice: dy:*/
  6382. /* ISP_IS will compensate for vertical camera displacement of DY lines in the next frame */
  6383. #ifdef MRV_IS_DY
  6384. #define MRV_IS_DY_MAX 0x000007FF
  6385. #define MRV_IS_DY_MIN (~MRV_IS_DY_MAX)
  6386. #endif /* MRV_IS_DY */
  6387. /* Slice: dx:*/
  6388. /* ISP_IS will compensate for horizontal camera displacement of DX pixels in the next frame */
  6389. #ifdef MRV_IS_DX
  6390. #define MRV_IS_DX_MAX 0x000007FF
  6391. #define MRV_IS_DX_MIN (~MRV_IS_DX_MAX)
  6392. #endif /* MRV_IS_DX */
  6393. /*****************************************************************************/
  6394. /**
  6395. * register: isp_is_h_offs_shd: current horizontal offset of output window
  6396. * (shadow register) (0x00000024)
  6397. *
  6398. *****************************************************************************/
  6399. /* Slice: is_h_offs_shd:*/
  6400. /* current horizonatl picture offset in lines */
  6401. #ifdef MRV_IS_IS_H_OFFS_SHD
  6402. #endif /* MRV_IS_IS_H_OFFS_SHD */
  6403. /*****************************************************************************/
  6404. /**
  6405. * register: isp_is_v_offs_shd: current vertical offset of output window
  6406. * (shadow register) (0x00000028)
  6407. *
  6408. *****************************************************************************/
  6409. /* Slice: is_v_offs_shd:*/
  6410. /* current vertical picture offset in lines */
  6411. #ifdef MRV_IS_IS_V_OFFS_SHD
  6412. #endif /* MRV_IS_IS_V_OFFS_SHD */
  6413. /*****************************************************************************/
  6414. /**
  6415. * register: isp_is_h_size_shd: current output horizontal picture size
  6416. * (shadow register) (0x0000002c)
  6417. *
  6418. *****************************************************************************/
  6419. /* Slice: isp_h_size_shd:*/
  6420. /* current horizontal picture size in pixel */
  6421. #ifdef MRV_IS_ISP_H_SIZE_SHD
  6422. #endif /* MRV_IS_ISP_H_SIZE_SHD */
  6423. /*****************************************************************************/
  6424. /**
  6425. * register: isp_is_v_size_shd: current output vertical picture size
  6426. * (shadow register) (0x00000030)
  6427. *
  6428. *****************************************************************************/
  6429. /* Slice: isp_v_size_shd:*/
  6430. /* vertical picture size in lines */
  6431. #ifdef MRV_IS_ISP_V_SIZE_SHD
  6432. #endif /* MRV_IS_ISP_V_SIZE_SHD */
  6433. /*****************************************************************************/
  6434. /* ISP Histogram Module Registers */
  6435. /*****************************************************************************/
  6436. /*****************************************************************************/
  6437. /**
  6438. * register: isp_hist_prop: Histogram properties (0x00000000)
  6439. *
  6440. *****************************************************************************/
  6441. /* Slice: stepsize:*/
  6442. /* histogram predivider, process every (stepsize)th pixel, all other pixels are skipped */
  6443. /* 0,1,2: not allowed */
  6444. /* 3: process every third input pixel */
  6445. /* 4: process every fourth input pixel */
  6446. /* ...*/
  6447. /* 7FH: process every 127th pixel */
  6448. #ifdef MRV_HIST_STEPSIZE
  6449. #define MRV_HIST_STEPSIZE_MIN 0x00000003
  6450. #define MRV_HIST_STEPSIZE_MAX 0x0000007F
  6451. #endif /* MRV_HIST_STEPSIZE */
  6452. /* Slice: hist_mode:*/
  6453. /* histogram mode, luminance is taken at ISP output before output formatter,*/
  6454. /* RGB is taken at xtalk output */
  6455. /**/
  6456. /* 7, 6: must not be used */
  6457. /* 5: Y (luminance) histogram */
  6458. /* 4: B histogram */
  6459. /* 3: G histogram */
  6460. /* 2: R histogram */
  6461. /* 1: RGB combined histogram */
  6462. /* 0: disable, no measurements */
  6463. #ifdef MRV_HIST_MODE
  6464. #define MRV_HIST_MODE_MAX 5 /* because 6 and 7 are reserved */
  6465. #define MRV_HIST_MODE_LUM 5 /* 5: Y (luminance) histogram */
  6466. #define MRV_HIST_MODE_B 4 /* 4: B histogram */
  6467. #define MRV_HIST_MODE_G 3 /* 3: G histogram */
  6468. #define MRV_HIST_MODE_R 2 /* 2: R histogram */
  6469. #define MRV_HIST_MODE_RGB 1 /* 1: RGB combined histogram */
  6470. #define MRV_HIST_MODE_NONE 0 /* 0: disable, no measurements */
  6471. #endif /* MRV_HIST_MODE */
  6472. /*****************************************************************************/
  6473. /**
  6474. * register: isp_hist_h_offs: Histogram window horizontal offset for first
  6475. * window of 25 sub-windows (0x00000004)
  6476. *
  6477. *****************************************************************************/
  6478. /* Slice: hist_h_offset:*/
  6479. /* Horizontal offset of first window in pixels.*/
  6480. #ifdef MRV_HIST_H_OFFSET
  6481. #endif /* MRV_HIST_H_OFFSET */
  6482. /*****************************************************************************/
  6483. /**
  6484. * register: isp_hist_v_offs: Histogram window vertical offset for first
  6485. * window of 25 sub-windows (0x00000008)
  6486. *
  6487. *****************************************************************************/
  6488. /* Slice: hist_v_offset:*/
  6489. /* Vertical offset of first window in pixels.*/
  6490. #ifdef MRV_HIST_V_OFFSET
  6491. #endif /* MRV_HIST_V_OFFSET */
  6492. /*****************************************************************************/
  6493. /**
  6494. * register: isp_hist_h_size: Horizontal (sub-)window size (0x0000000c)
  6495. *
  6496. *****************************************************************************/
  6497. /* Slice: hist_h_size:*/
  6498. /* Horizontal size in pixels of one sub-window, if histogram version 3 is implemented.*/
  6499. #ifdef MRV_HIST_H_SIZE
  6500. #endif /* MRV_HIST_H_SIZE */
  6501. /*****************************************************************************/
  6502. /**
  6503. * register: isp_hist_v_size: Vertical (sub-)window size (0x00000010)
  6504. *
  6505. *****************************************************************************/
  6506. /* Slice: hist_v_size:*/
  6507. /* Vertical size in lines of one sub-window, if histogram version 3 is implemented.*/
  6508. #ifdef MRV_HIST_V_SIZE
  6509. #endif /* MRV_HIST_V_SIZE */
  6510. /*****************************************************************************/
  6511. /**
  6512. * register array: isp_hist_bin: histogram measurement result bin
  6513. * (0x028 + n*0x4 (n=0..15))
  6514. *
  6515. *****************************************************************************/
  6516. /* Slice: hist_bin_n:*/
  6517. /* measured bin count as 16-bit unsigned integer value plus 4 bit fractional part */
  6518. #ifdef MRV_HIST_BIN_N
  6519. #define MRV_HIST_BIN_N_MAX (MRV_HIST_BIN_N_MASK >> MRV_HIST_BIN_N_SHIFT)
  6520. #endif /* MRV_HIST_BIN_N */
  6521. /*****************************************************************************/
  6522. /**
  6523. * register: isp_hist_weight_00to30: Weighting factor for sub-windows
  6524. * (0x00000054)
  6525. *
  6526. *****************************************************************************/
  6527. /* Slice: hist_weight_30:*/
  6528. /* weighting factor for sub-window 30 */
  6529. #ifdef MRV_HIST_WEIGHT_30
  6530. #endif /* MRV_HIST_WEIGHT_30 */
  6531. /* Slice: hist_weight_20:*/
  6532. /* weighting factor for sub-window 20 */
  6533. #ifdef MRV_HIST_WEIGHT_20
  6534. #endif /* MRV_HIST_WEIGHT_20 */
  6535. /* Slice: hist_weight_10:*/
  6536. /* weighting factor for sub-window 10 */
  6537. #ifdef MRV_HIST_WEIGHT_10
  6538. #endif /* MRV_HIST_WEIGHT_10 */
  6539. /* Slice: hist_weight_00:*/
  6540. /* weighting factor for sub-window 00 */
  6541. #ifdef MRV_HIST_WEIGHT_00
  6542. #endif /* MRV_HIST_WEIGHT_00 */
  6543. /*****************************************************************************/
  6544. /**
  6545. * register: isp_hist_weight_40to21: Weighting factor for sub-windows
  6546. * (0x00000058)
  6547. *
  6548. *****************************************************************************/
  6549. /* Slice: hist_weight_21:*/
  6550. /* weighting factor for sub-window 21 */
  6551. #ifdef MRV_HIST_WEIGHT_21
  6552. #endif /* MRV_HIST_WEIGHT_21 */
  6553. /* Slice: hist_weight_11:*/
  6554. /* weighting factor for sub-window 11 */
  6555. #ifdef MRV_HIST_WEIGHT_11
  6556. #endif /* MRV_HIST_WEIGHT_11 */
  6557. /* Slice: hist_weight_01:*/
  6558. /* weighting factor for sub-window 01 */
  6559. #ifdef MRV_HIST_WEIGHT_01
  6560. #endif /* MRV_HIST_WEIGHT_01 */
  6561. /* Slice: hist_weight_40:*/
  6562. /* weighting factor for sub-window 40 */
  6563. #ifdef MRV_HIST_WEIGHT_40
  6564. #endif /* MRV_HIST_WEIGHT_40 */
  6565. /*****************************************************************************/
  6566. /**
  6567. * register: isp_hist_weight_31to12: Weighting factor for sub-windows
  6568. * (0x0000005c)
  6569. *
  6570. *****************************************************************************/
  6571. /* Slice: hist_weight_12:*/
  6572. /* weighting factor for sub-window 12 */
  6573. #ifdef MRV_HIST_WEIGHT_12
  6574. #endif /* MRV_HIST_WEIGHT_12 */
  6575. /* Slice: hist_weight_02:*/
  6576. /* weighting factor for sub-window 02 */
  6577. #ifdef MRV_HIST_WEIGHT_02
  6578. #endif /* MRV_HIST_WEIGHT_02 */
  6579. /* Slice: hist_weight_41:*/
  6580. /* weighting factor for sub-window 41 */
  6581. #ifdef MRV_HIST_WEIGHT_41
  6582. #endif /* MRV_HIST_WEIGHT_41 */
  6583. /* Slice: hist_weight_31:*/
  6584. /* weighting factor for sub-window 31 */
  6585. #ifdef MRV_HIST_WEIGHT_31
  6586. #endif /* MRV_HIST_WEIGHT_31 */
  6587. /*****************************************************************************/
  6588. /**
  6589. * register: isp_hist_weight_22to03: Weighting factor for sub-windows
  6590. * (0x00000060)
  6591. *
  6592. *****************************************************************************/
  6593. /* Slice: hist_weight_03:*/
  6594. /* weighting factor for sub-window 03 */
  6595. #ifdef MRV_HIST_WEIGHT_03
  6596. #endif /* MRV_HIST_WEIGHT_03 */
  6597. /* Slice: hist_weight_42:*/
  6598. /* weighting factor for sub-window 42 */
  6599. #ifdef MRV_HIST_WEIGHT_42
  6600. #endif /* MRV_HIST_WEIGHT_42 */
  6601. /* Slice: hist_weight_32:*/
  6602. /* weighting factor for sub-window 32 */
  6603. #ifdef MRV_HIST_WEIGHT_32
  6604. #endif /* MRV_HIST_WEIGHT_32 */
  6605. /* Slice: hist_weight_22:*/
  6606. /* weighting factor for sub-window 22 */
  6607. #ifdef MRV_HIST_WEIGHT_22
  6608. #endif /* MRV_HIST_WEIGHT_22 */
  6609. /*****************************************************************************/
  6610. /**
  6611. * register: isp_hist_weight_13to43: Weighting factor for sub-windows
  6612. * (0x00000064)
  6613. *
  6614. *****************************************************************************/
  6615. /* Slice: hist_weight_43:*/
  6616. /* weighting factor for sub-window 43 */
  6617. #ifdef MRV_HIST_WEIGHT_43
  6618. #endif /* MRV_HIST_WEIGHT_43 */
  6619. /* Slice: hist_weight_33:*/
  6620. /* weighting factor for sub-window 33 */
  6621. #ifdef MRV_HIST_WEIGHT_33
  6622. #endif /* MRV_HIST_WEIGHT_33 */
  6623. /* Slice: hist_weight_23:*/
  6624. /* weighting factor for sub-window 23 */
  6625. #ifdef MRV_HIST_WEIGHT_23
  6626. #endif /* MRV_HIST_WEIGHT_23 */
  6627. /* Slice: hist_weight_13:*/
  6628. /* weighting factor for sub-window 13 */
  6629. #ifdef MRV_HIST_WEIGHT_13
  6630. #endif /* MRV_HIST_WEIGHT_13 */
  6631. /*****************************************************************************/
  6632. /**
  6633. * register: isp_hist_weight_04to34: Weighting factor for sub-windows
  6634. * (0x00000068)
  6635. *
  6636. *****************************************************************************/
  6637. /* Slice: hist_weight_34:*/
  6638. /* weighting factor for sub-window 34 */
  6639. #ifdef MRV_HIST_WEIGHT_34
  6640. #endif /* MRV_HIST_WEIGHT_34 */
  6641. /* Slice: hist_weight_24:*/
  6642. /* weighting factor for sub-window 24 */
  6643. #ifdef MRV_HIST_WEIGHT_24
  6644. #endif /* MRV_HIST_WEIGHT_24 */
  6645. /* Slice: hist_weight_14:*/
  6646. /* weighting factor for sub-window 14 */
  6647. #ifdef MRV_HIST_WEIGHT_14
  6648. #endif /* MRV_HIST_WEIGHT_14 */
  6649. /* Slice: hist_weight_04:*/
  6650. /* weighting factor for sub-window 04 */
  6651. #ifdef MRV_HIST_WEIGHT_04
  6652. #endif /* MRV_HIST_WEIGHT_04 */
  6653. /*****************************************************************************/
  6654. /**
  6655. * register: isp_hist_weight_44: Weighting factor for sub-windows (0x0000006c)
  6656. *
  6657. *****************************************************************************/
  6658. /* Slice: hist_weight_44:*/
  6659. /* weighting factor for sub-window 44 */
  6660. #ifdef MRV_HIST_WEIGHT_44
  6661. #endif /* MRV_HIST_WEIGHT_44 */
  6662. #define MRV_HIST_WEIGHT_MAX 0x10
  6663. /*****************************************************************************/
  6664. /* ISP Filter Module Registers */
  6665. /*****************************************************************************/
  6666. /*****************************************************************************/
  6667. /**
  6668. * register: isp_filt_mode: mode control register for the filter block
  6669. * (0x00000000)
  6670. *
  6671. *****************************************************************************/
  6672. /* Slice: stage1_select:*/
  6673. /* Green filter stage 1 select (range 0x0...0x8)*/
  6674. /* 0x0 maximum blurring */
  6675. /* 0x4 Default */
  6676. /* 0x7 minimum blurring */
  6677. /* 0x8 filter stage1 bypass */
  6678. /* For a detailed description refer to chapter "ISP Filter Programming" of user manual */
  6679. #ifdef MRV_FILT_STAGE1_SELECT
  6680. #define MRV_FILT_STAGE1_SELECT_MAX_BLUR 0U /* 0x0 maximum blurring */
  6681. #define MRV_FILT_STAGE1_SELECT_DEFAULT 4U /* 0x4 Default */
  6682. #define MRV_FILT_STAGE1_SELECT_MIN_BLUR 7U /* 0x7 minimum blurring */
  6683. #define MRV_FILT_STAGE1_SELECT_BYPASS 8U /* 0x8 filter stage1 bypass */
  6684. #endif /* MRV_FILT_STAGE1_SELECT */
  6685. /* Slice: filt_chr_h_mode:*/
  6686. /* Chroma filter horizontal mode */
  6687. /* 00 horizontal chroma filter bypass */
  6688. /* 01 horizontal chroma filter 1 static mask = [10 12 10]*/
  6689. /* 10 horizontal chroma filter 2 (dynamic blur1)*/
  6690. /* 11 horizontal chroma filter 3 (dynamic blur2) Default */
  6691. #ifdef MRV_FILT_FILT_CHR_H_MODE
  6692. #define MRV_FILT_FILT_CHR_H_MODE_BYPASS 0U /* 00 horizontal chroma filter bypass */
  6693. #define MRV_FILT_FILT_CHR_H_MODE_STATIC 1U /* 01 horizontal chroma filter 1 static mask = [10 12 10] */
  6694. #define MRV_FILT_FILT_CHR_H_MODE_DYN_1 2U /* 10 horizontal chroma filter 2 (dynamic blur1) */
  6695. #define MRV_FILT_FILT_CHR_H_MODE_DYN_2 3U /* 11 horizontal chroma filter 3 (dynamic blur2) Default */
  6696. #endif /* MRV_FILT_FILT_CHR_H_MODE */
  6697. /* Slice: filt_chr_v_mode:*/
  6698. /* Chroma filter vertical mode */
  6699. /* 00 vertical chroma filter bypass */
  6700. /* 01 vertical chroma filter 1 static [8 16 8]*/
  6701. /* 10 vertical chroma filter 2 static [10 12 10]*/
  6702. /* 11 vertical chroma filter 3 static [12 8 12] Default */
  6703. #ifdef MRV_FILT_FILT_CHR_V_MODE
  6704. #define MRV_FILT_FILT_CHR_V_MODE_BYPASS 0U /* 00 vertical chroma filter bypass */
  6705. #define MRV_FILT_FILT_CHR_V_MODE_STATIC8 1U /* 01 vertical chroma filter 1 static [8 16 8] */
  6706. #define MRV_FILT_FILT_CHR_V_MODE_STATIC10 2U /* 10 vertical chroma filter 2 static [10 12 10] */
  6707. #define MRV_FILT_FILT_CHR_V_MODE_STATIC12 3U /* 11 vertical chroma filter 3 static [12 8 12] Default */
  6708. #endif /* MRV_FILT_FILT_CHR_V_MODE */
  6709. /* Slice: filt_mode:*/
  6710. /* 0 green filter static mode (active filter factor = FILT_FAC_MID)*/
  6711. /* 1 dynamic noise reduction/sharpen Default */
  6712. #ifdef MRV_FILT_FILT_MODE
  6713. #define MRV_FILT_FILT_MODE_STATIC 0U /* 0 green filter static mode (active filter factor = FILT_FAC_MID) */
  6714. #define MRV_FILT_FILT_MODE_DYNAMIC 1U /* 1 dynamic noise reduction/sharpen Default */
  6715. #endif /* MRV_FILT_FILT_MODE */
  6716. /* Slice: filt_enable:*/
  6717. /* 1 enable filter */
  6718. /* 0 bypass filter Default */
  6719. #ifdef MRV_FILT_FILT_ENABLE
  6720. #define MRV_FILT_FILT_ENABLE_PROCESS 1U
  6721. #define MRV_FILT_FILT_ENABLE_BYPASS 0U
  6722. #endif /* MRV_FILT_FILT_ENABLE */
  6723. /*****************************************************************************/
  6724. /**
  6725. * register: isp_filt_thresh_bl0: Blurring threshold 0 (0x00000028)
  6726. *
  6727. *****************************************************************************/
  6728. /* Slice: filt_thresh_bl0:*/
  6729. /* If filt_thresh_bl1 < sum_grad < filt_thresh_bl0 then filt_fac_bl0 is selected */
  6730. #ifdef MRV_FILT_FILT_THRESH_BL0
  6731. #endif /* MRV_FILT_FILT_THRESH_BL0 */
  6732. /*****************************************************************************/
  6733. /**
  6734. * register: isp_filt_thresh_bl1: Blurring threshold 1 (0x0000002c)
  6735. *
  6736. *****************************************************************************/
  6737. /* Slice: filt_thresh_bl1:*/
  6738. /* If sum_grad < filt_thresh_bl1 then filt_fac_bl1 is selected */
  6739. #ifdef MRV_FILT_FILT_THRESH_BL1
  6740. #endif /* MRV_FILT_FILT_THRESH_BL1 */
  6741. /*****************************************************************************/
  6742. /**
  6743. * register: isp_filt_thresh_sh0: Sharpening threshold 0 (0x00000030)
  6744. *
  6745. *****************************************************************************/
  6746. /* Slice: filt_thresh_sh0:*/
  6747. /* If filt_thresh_sh0 < sum_grad < filt_thresh_sh1 then filt_thresh_sh0 is selected */
  6748. #ifdef MRV_FILT_FILT_THRESH_SH0
  6749. #endif /* MRV_FILT_FILT_THRESH_SH0 */
  6750. /*****************************************************************************/
  6751. /**
  6752. * register: isp_filt_thresh_sh1: Sharpening threshold 1 (0x00000034)
  6753. *
  6754. *****************************************************************************/
  6755. /* Slice: filt_thresh_sh1:*/
  6756. /* If filt_thresh_sh1 < sum_grad then filt_thresh_sh1 is selected */
  6757. #ifdef MRV_FILT_FILT_THRESH_SH1
  6758. #endif /* MRV_FILT_FILT_THRESH_SH1 */
  6759. /*****************************************************************************/
  6760. /**
  6761. * register: isp_filt_lum_weight: Parameters for luminance weight function
  6762. * (0x00000038)
  6763. *
  6764. *****************************************************************************/
  6765. /* Slice: lum_weight_gain:*/
  6766. /* Gain select of luminance weight function */
  6767. #ifdef MRV_FILT_LUM_WEIGHT_GAIN
  6768. #endif /* MRV_FILT_LUM_WEIGHT_GAIN */
  6769. /* Slice: lum_weight_kink:*/
  6770. /* Kink position of luminance weight function */
  6771. #ifdef MRV_FILT_LUM_WEIGHT_KINK
  6772. #endif /* MRV_FILT_LUM_WEIGHT_KINK */
  6773. /* Slice: lum_weight_min:*/
  6774. /* Minimum value of luminance weight function */
  6775. #ifdef MRV_FILT_LUM_WEIGHT_MIN
  6776. #endif /* MRV_FILT_LUM_WEIGHT_MIN */
  6777. /*****************************************************************************/
  6778. /**
  6779. * register: isp_filt_fac_sh1: filter factor sharp1 (0x0000003c)
  6780. *
  6781. *****************************************************************************/
  6782. /* Slice: filt_fac_sh1:*/
  6783. /* Filter factor for sharp1 level */
  6784. #ifdef MRV_FILT_FILT_FAC_SH1
  6785. #endif /* MRV_FILT_FILT_FAC_SH1 */
  6786. /*****************************************************************************/
  6787. /**
  6788. * register: isp_filt_fac_sh0: filter factor sharp0 (0x00000040)
  6789. *
  6790. *****************************************************************************/
  6791. /* Slice: filt_fac_sh0:*/
  6792. /* Filter factor for sharp0 level */
  6793. #ifdef MRV_FILT_FILT_FAC_SH0
  6794. #endif /* MRV_FILT_FILT_FAC_SH0 */
  6795. /*****************************************************************************/
  6796. /**
  6797. * register: isp_filt_fac_mid: filter factor middle (0x00000044)
  6798. *
  6799. *****************************************************************************/
  6800. /* Slice: filt_fac_mid:*/
  6801. /* Filter factor for mid level and for static filter mode */
  6802. #ifdef MRV_FILT_FILT_FAC_MID
  6803. #endif /* MRV_FILT_FILT_FAC_MID */
  6804. /*****************************************************************************/
  6805. /**
  6806. * register: isp_filt_fac_bl0: Parameter for blur 0 filter (0x00000048)
  6807. *
  6808. *****************************************************************************/
  6809. /* Slice: filt_fac_bl0:*/
  6810. /* Filter factor for blur 0 level */
  6811. #ifdef MRV_FILT_FILT_FAC_BL0
  6812. #endif /* MRV_FILT_FILT_FAC_BL0 */
  6813. /*****************************************************************************/
  6814. /**
  6815. * register: isp_filt_fac_bl1: Parameter for blur 1 filter (0x0000004c)
  6816. *
  6817. *****************************************************************************/
  6818. /* Slice: filt_fac_bl1:*/
  6819. /* Filter factor for blur 1 level (max blur)*/
  6820. #ifdef MRV_FILT_FILT_FAC_BL1
  6821. #endif /* MRV_FILT_FILT_FAC_BL1 */
  6822. /*****************************************************************************/
  6823. /* ISP Auto Focus Measurement Registers */
  6824. /*****************************************************************************/
  6825. /*****************************************************************************/
  6826. /**
  6827. * register: isp_afm_ctrl: This is the control register for AF measurement
  6828. * unit (0x00000000)
  6829. *
  6830. *****************************************************************************/
  6831. /* Slice: afm_en:*/
  6832. /* AF measurement enable */
  6833. /* 0: AF measurement is disabled */
  6834. /* 1: AF measurement is enabled */
  6835. /* Writing a 1 to this register starts a new measurement and resets the afm_fin (measurement finished) interrupt to 0.*/
  6836. /* As long as the afm_en is 1, the AFM unit calculates new sharpness values for each frame.*/
  6837. #ifdef MRV_AFM_AFM_EN
  6838. #define MRV_AFM_AFM_EN_ENABLE 1 /* 1: enable AF measurment */
  6839. #define MRV_AFM_AFM_EN_DISABLE 0 /* 0: processing is deactivated, bypass mode is selected */
  6840. #endif /* MRV_AFM_AFM_EN */
  6841. /*****************************************************************************/
  6842. /**
  6843. * register: isp_afm_lt_a: Top Left corner of measure window A (0x00000004)
  6844. *
  6845. *****************************************************************************/
  6846. /* Slice: a_h_l:*/
  6847. /* first pixel of window A (horizontal left row), value must be greater or equal 5 */
  6848. #ifdef MRV_AFM_A_H_L
  6849. #define MRV_AFM_A_H_L_MIN (5U)
  6850. #define MRV_AFM_A_H_L_MAX (MRV_AFM_A_H_L_MASK >> MRV_AFM_A_H_L_SHIFT)
  6851. #endif /* MRV_AFM_A_H_L */
  6852. /* Slice: a_v_t:*/
  6853. /* first line of window A (vertical top line), value must be greater or equal 2 */
  6854. #ifdef MRV_AFM_A_V_T
  6855. #define MRV_AFM_A_V_T_MIN (2U)
  6856. #define MRV_AFM_A_V_T_MAX (MRV_AFM_A_V_T_MASK >> MRV_AFM_A_V_T_SHIFT)
  6857. #endif /* MRV_AFM_A_V_T */
  6858. /*****************************************************************************/
  6859. /**
  6860. * register: isp_afm_rb_a: Bottom right corner of measure window A (0x00000008)
  6861. *
  6862. *****************************************************************************/
  6863. /* Slice: a_h_r:*/
  6864. /* last pixel of window A (horizontal right row)*/
  6865. #ifdef MRV_AFM_A_H_R
  6866. #define MRV_AFM_A_H_R_MIN (5U)
  6867. #define MRV_AFM_A_H_R_MAX (MRV_AFM_A_H_R_MASK >> MRV_AFM_A_H_R_SHIFT)
  6868. #endif /* MRV_AFM_A_H_R */
  6869. /* Slice: a_v_b:*/
  6870. /* last line of window A (vertical bottom line), value must be lower than */
  6871. /* (number of lines -2)*/
  6872. #ifdef MRV_AFM_A_V_B
  6873. #define MRV_AFM_A_V_B_MIN (2U)
  6874. #define MRV_AFM_A_V_B_MAX (MRV_AFM_A_V_B_MASK >> MRV_AFM_A_V_B_SHIFT)
  6875. #endif /* MRV_AFM_A_V_B */
  6876. /*****************************************************************************/
  6877. /**
  6878. * register: isp_afm_lt_b: Top left corner of measure window B (0x0000000c)
  6879. *
  6880. *****************************************************************************/
  6881. /* Slice: b_h_l:*/
  6882. /* first pixel of window B (horizontal left row), value must be greater or equal 5 */
  6883. #ifdef MRV_AFM_B_H_L
  6884. #define MRV_AFM_B_H_L_MIN (5U)
  6885. #define MRV_AFM_B_H_L_MAX (MRV_AFM_B_H_L_MASK >> MRV_AFM_B_H_L_SHIFT)
  6886. #endif /* MRV_AFM_B_H_L */
  6887. /* Slice: b_v_t:*/
  6888. /* first line of window B (vertical top line), value must be greater or equal 2 */
  6889. #ifdef MRV_AFM_B_V_T
  6890. #define MRV_AFM_B_V_T_MIN (2U)
  6891. #define MRV_AFM_B_V_T_MAX (MRV_AFM_B_V_T_MASK >> MRV_AFM_B_V_T_SHIFT)
  6892. #endif /* MRV_AFM_B_V_T */
  6893. /*****************************************************************************/
  6894. /**
  6895. * register: isp_afm_rb_b: Bottom right corner of measure window B (0x00000010)
  6896. *
  6897. *****************************************************************************/
  6898. /* Slice: b_h_r:*/
  6899. /* last pixel of window B (horizontal right row)*/
  6900. #ifdef MRV_AFM_B_H_R
  6901. #define MRV_AFM_B_H_R_MIN (5U)
  6902. #define MRV_AFM_B_H_R_MAX (MRV_AFM_B_H_R_MASK >> MRV_AFM_B_H_R_SHIFT)
  6903. #endif /* MRV_AFM_B_H_R */
  6904. /* Slice: b_v_b:*/
  6905. /* last line of window B (vertical bottom line), value must be lower than */
  6906. /* (number of lines -2)*/
  6907. #ifdef MRV_AFM_B_V_B
  6908. #define MRV_AFM_B_V_B_MIN (2U)
  6909. #define MRV_AFM_B_V_B_MAX (MRV_AFM_B_V_B_MASK >> MRV_AFM_B_V_B_SHIFT)
  6910. #endif /* MRV_AFM_B_V_B */
  6911. /*****************************************************************************/
  6912. /**
  6913. * register: isp_afm_lt_c: Top left corner of measure window C (0x00000014)
  6914. *
  6915. *****************************************************************************/
  6916. /* Slice: c_h_l:*/
  6917. /* first pixel of window C (horizontal left row), value must be greater or equal 5 */
  6918. #ifdef MRV_AFM_C_H_L
  6919. #define MRV_AFM_C_H_L_MIN (5U)
  6920. #define MRV_AFM_C_H_L_MAX (MRV_AFM_C_H_L_MASK >> MRV_AFM_C_H_L_SHIFT)
  6921. #endif /* MRV_AFM_C_H_L */
  6922. /* Slice: c_v_t:*/
  6923. /* first line of window C (vertical top line), value must be greater or equal 2 */
  6924. #ifdef MRV_AFM_C_V_T
  6925. #define MRV_AFM_C_V_T_MIN (2U)
  6926. #define MRV_AFM_C_V_T_MAX (MRV_AFM_C_V_T_MASK >> MRV_AFM_C_V_T_SHIFT)
  6927. #endif /* MRV_AFM_C_V_T */
  6928. /*****************************************************************************/
  6929. /**
  6930. * register: isp_afm_rb_c: Bottom right corner of measure window C (0x00000018)
  6931. *
  6932. *****************************************************************************/
  6933. /* Slice: c_h_r:*/
  6934. /* last pixel of window C (horizontal right row)*/
  6935. #ifdef MRV_AFM_C_H_R
  6936. #define MRV_AFM_C_H_R_MIN (5U)
  6937. #define MRV_AFM_C_H_R_MAX (MRV_AFM_C_H_R_MASK >> MRV_AFM_C_H_R_SHIFT)
  6938. #endif /* MRV_AFM_C_H_R */
  6939. /* Slice: c_v_b:*/
  6940. /* last line of window C (vertical bottom line), value must be lower than */
  6941. /* (number of lines -2)*/
  6942. #ifdef MRV_AFM_C_V_B
  6943. #define MRV_AFM_C_V_B_MIN (2U)
  6944. #define MRV_AFM_C_V_B_MAX (MRV_AFM_C_V_B_MASK >> MRV_AFM_C_V_B_SHIFT)
  6945. #endif /* MRV_AFM_C_V_B */
  6946. /*****************************************************************************/
  6947. /**
  6948. * register: isp_afm_thres: Threshold register (0x0000001c)
  6949. *
  6950. *****************************************************************************/
  6951. /* Slice: afm_thres:*/
  6952. /* AF measurement threshold */
  6953. /* This register defines a threshold which can be used for minimizing the */
  6954. /* influence of noise in the measurement result.*/
  6955. #ifdef MRV_AFM_AFM_THRES
  6956. #endif /* MRV_AFM_AFM_THRES */
  6957. /*****************************************************************************/
  6958. /**
  6959. * register: isp_afm_var_shift: Variable shift register (0x00000020)
  6960. *
  6961. *****************************************************************************/
  6962. /* Slice: lum_var_shift:*/
  6963. /* variable shift for luminance summation */
  6964. /* The lum_var_shift defines the number of bits for the shift operation of the */
  6965. /* value of the current pixel before summation. The shift operation is used to */
  6966. /* avoid a luminance sum overflow.*/
  6967. #ifdef MRV_AFM_LUM_VAR_SHIFT
  6968. #endif /* MRV_AFM_LUM_VAR_SHIFT */
  6969. /* Slice: afm_var_shift:*/
  6970. /* variable shift for AF measurement */
  6971. /* The afm_var_shift defines the number of bits for the shift operation at the */
  6972. /* end of the calculation chain. The shift operation is used to avoid an AF */
  6973. /* measurement sum overflow.*/
  6974. #ifdef MRV_AFM_AFM_VAR_SHIFT
  6975. #endif /* MRV_AFM_AFM_VAR_SHIFT */
  6976. /*****************************************************************************/
  6977. /**
  6978. * register: isp_afm_sum_a: Sharpness Value Status Register of Window A (0x0024)
  6979. *
  6980. *****************************************************************************/
  6981. /* Slice: afm_sum_a:*/
  6982. /* sharpness value of window A */
  6983. #ifdef MRV_AFM_AFM_SUM_A
  6984. #endif /* MRV_AFM_AFM_SUM_A */
  6985. /*****************************************************************************/
  6986. /**
  6987. * register: isp_afm_sum_b: Sharpness Value Status Register of Window B (0x0028)
  6988. *
  6989. *****************************************************************************/
  6990. /* Slice: afm_sum_b:*/
  6991. /* sharpness value of window B */
  6992. #ifdef MRV_AFM_AFM_SUM_B
  6993. #endif /* MRV_AFM_AFM_SUM_B */
  6994. /*****************************************************************************/
  6995. /**
  6996. * register: isp_afm_sum_c: Sharpness Value Status Register of Window C (0x002c)
  6997. *
  6998. *****************************************************************************/
  6999. /* Slice: afm_sum_c:*/
  7000. /* sharpness value of window C */
  7001. #ifdef MRV_AFM_AFM_SUM_C
  7002. #endif /* MRV_AFM_AFM_SUM_C */
  7003. /*****************************************************************************/
  7004. /**
  7005. * register: isp_afm_lum_a: Luminance Value Status Register of Window A (0x0030)
  7006. *
  7007. *****************************************************************************/
  7008. /* Slice: afm_lum_a:*/
  7009. /* luminance value of window A */
  7010. #ifdef MRV_AFM_AFM_LUM_A
  7011. #endif /* MRV_AFM_AFM_LUM_A */
  7012. /*****************************************************************************/
  7013. /**
  7014. * register: isp_afm_lum_b: Luminance Value Status Register of Window B (0x0034)
  7015. *
  7016. *****************************************************************************/
  7017. /* Slice: afm_lum_b:*/
  7018. /* luminance value of window B */
  7019. #ifdef MRV_AFM_AFM_LUM_B
  7020. #endif /* MRV_AFM_AFM_LUM_B */
  7021. /*****************************************************************************/
  7022. /**
  7023. * register: isp_afm_lum_c: Luminance Value Status Register of Window C (0x0038)
  7024. *
  7025. *****************************************************************************/
  7026. /* Slice: afm_lum_c:*/
  7027. /* luminance value of window C */
  7028. #ifdef MRV_AFM_AFM_LUM_C
  7029. #endif /* MRV_AFM_AFM_LUM_C */
  7030. /*****************************************************************************/
  7031. /* ISP Lens Shade Correction Registers */
  7032. /*****************************************************************************/
  7033. /*****************************************************************************/
  7034. /**
  7035. * register: isp_lsc_ctrl: Lens shade control (0x00000000)
  7036. *
  7037. *****************************************************************************/
  7038. /* Slice: lsc_en:*/
  7039. /* 0: activation request for lens shading correction */
  7040. /* 1: deactivation reqeust for lens shading correction */
  7041. /* Activation/Deactivation is object of a shadowing mechnism. The current */
  7042. /* status is visible at ISP_LSC_STATUS::lsc_enable_status */
  7043. #ifdef MRV_LSC_LSC_EN
  7044. #define MRV_LSC_LSC_EN_ENABLE 1U
  7045. #define MRV_LSC_LSC_EN_DISABLE 0U
  7046. #endif /* MRV_LSC_LSC_EN */
  7047. /*****************************************************************************/
  7048. /**
  7049. * register: isp_lsc_r_table_addr: Table RAM Address for red component (0x00000004)
  7050. *
  7051. *****************************************************************************/
  7052. /* Slice: r_ram_addr:*/
  7053. /* table address in RAM for samples of the R color component.*/
  7054. /* Will be automatically incremented by each read or write access to the table.*/
  7055. /* Valid addresses are in the range 0 to 152 for Bank0 and 153 to 305 for Bank1 */
  7056. /* (if available).*/
  7057. #ifdef MRV_LSC_R_RAM_ADDR
  7058. #define MRV_LSC_R_RAM_ADDR_MIN_BANK0 (0x00000000U)
  7059. #define MRV_LSC_R_RAM_ADDR_MAX_BANK0 (0x00000098U)
  7060. #define MRV_LSC_R_RAM_ADDR_MIN_BANK1 (0x00000099U)
  7061. #define MRV_LSC_R_RAM_ADDR_MAX_BANK1 (0x00000132U)
  7062. #endif /* MRV_LSC_R_RAM_ADDR */
  7063. /*****************************************************************************/
  7064. /**
  7065. * register: isp_lsc_gr_table_addr: Table RAM Address for green (red) component
  7066. * (0x00000008)
  7067. *
  7068. *****************************************************************************/
  7069. /* Slice: gr_ram_addr:*/
  7070. /* table address in RAM for samples of the G_R color component.*/
  7071. /* Will be automatically incremented by each read or write access to the table.*/
  7072. /* Valid addresses are in the range 0 to 152 for Bank0 and 153 to 305 for Bank1 */
  7073. /* (if available).*/
  7074. #ifdef MRV_LSC_GR_RAM_ADDR
  7075. #define MRV_LSC_GR_RAM_ADDR_MIN_BANK0 (0x00000000U)
  7076. #define MRV_LSC_GR_RAM_ADDR_MAX_BANK0 (0x00000098U)
  7077. #define MRV_LSC_GR_RAM_ADDR_MIN_BANK1 (0x00000099U)
  7078. #define MRV_LSC_GR_RAM_ADDR_MAX_BANK1 (0x00000131U)
  7079. #endif /* MRV_LSC_GR_RAM_ADDR */
  7080. /*****************************************************************************/
  7081. /**
  7082. * register: isp_lsc_b_table_addr: Table RAM Address for blue component
  7083. * (0x0000000c)
  7084. *
  7085. *****************************************************************************/
  7086. /* Slice: b_ram_addr:*/
  7087. /* table address in RAM for samples of the B color component.*/
  7088. /* Will be automatically incremented by each read or write access to the table.*/
  7089. /* Valid addresses are in the range 0 to 152 for Bank0 and 153 to 305 for Bank1 */
  7090. /* (if available).*/
  7091. #ifdef MRV_LSC_B_RAM_ADDR
  7092. #define MRV_LSC_B_RAM_ADDR_MIN_BANK0 (0x00000000U)
  7093. #define MRV_LSC_B_RAM_ADDR_MAX_BANK0 (0x00000098U)
  7094. #define MRV_LSC_B_RAM_ADDR_MIN_BANK1 (0x00000099U)
  7095. #define MRV_LSC_B_RAM_ADDR_MAX_BANK1 (0x00000132U)
  7096. #endif /* MRV_LSC_B_RAM_ADDR */
  7097. /*****************************************************************************/
  7098. /**
  7099. * register: isp_lsc_gb_table_addr: Table RAM Address for green (blue) component
  7100. * (0x00000010)
  7101. *
  7102. *****************************************************************************/
  7103. /* Slice: gb_ram_addr:*/
  7104. /* table address in RAM for samples of the G_B color component.*/
  7105. /* Will be automatically incremented by each read or write access to the table.*/
  7106. /* Valid addresses are in the range 0 to 152 for Bank0 and 153 to 305 for Bank1 */
  7107. /* (if available).*/
  7108. #ifdef MRV_LSC_GB_RAM_ADDR
  7109. #define MRV_LSC_GB_RAM_ADDR_MIN_BANK0 (0x00000000U)
  7110. #define MRV_LSC_GB_RAM_ADDR_MAX_BANK0 (0x00000098U)
  7111. #define MRV_LSC_GB_RAM_ADDR_MIN_BANK1 (0x00000099U)
  7112. #define MRV_LSC_GB_RAM_ADDR_MAX_BANK1 (0x00000132U)
  7113. #endif /* MRV_LSC_GB_RAM_ADDR */
  7114. /*****************************************************************************/
  7115. /**
  7116. * register: isp_lsc_r_table_data: Sample table red (0x00000014)
  7117. *
  7118. *****************************************************************************/
  7119. /* Slice: r_sample_1:*/
  7120. /* correction factor at sample point (fixed point number: 2 bits integer with */
  7121. /* 10-bit fractional part, range 1..3.999)*/
  7122. #ifdef MRV_LSC_R_SAMPLE_1
  7123. #endif /* MRV_LSC_R_SAMPLE_1 */
  7124. /* Slice: r_sample_0:*/
  7125. /* correction factor at sample point (fixed point number: 2 bits integer with */
  7126. /* 10-bit fractional part, range 1..3.999)*/
  7127. #ifdef MRV_LSC_R_SAMPLE_0
  7128. #endif /* MRV_LSC_R_SAMPLE_0 */
  7129. /*****************************************************************************/
  7130. /**
  7131. * register: isp_lsc_gr_table_data: Sample table green (red) (0x00000018)
  7132. *
  7133. *****************************************************************************/
  7134. /* Slice: gr_sample_1:*/
  7135. /* correction factor at sample point (fixed point number: 2 bits integer with */
  7136. /* 10-bit fractional part, range 1..3.999)*/
  7137. #ifdef MRV_LSC_GR_SAMPLE_1
  7138. #endif /* MRV_LSC_GR_SAMPLE_1 */
  7139. /* Slice: gr_sample_0:*/
  7140. /* correction factor at sample point (fixed point number: 2 bits integer with */
  7141. /* 10-bit fractional part, range 1..3.999)*/
  7142. #ifdef MRV_LSC_GR_SAMPLE_0
  7143. #endif /* MRV_LSC_GR_SAMPLE_0 */
  7144. /*****************************************************************************/
  7145. /**
  7146. * register: Register: isp_lsc_b_table_data: Sample table blue (0x0000001c)
  7147. *
  7148. *****************************************************************************/
  7149. /* Slice: b_sample_1:*/
  7150. /* correction factor at sample point (fixed point number: 2 bits integer with */
  7151. /* 10-bit fractional part, range 1..3.999)*/
  7152. #ifdef MRV_LSC_B_SAMPLE_1
  7153. #endif /* MRV_LSC_B_SAMPLE_1 */
  7154. /* Slice: b_sample_0:*/
  7155. /* correction factor at sample point (fixed point number: 2 bits integer with */
  7156. /* 10-bit fractional part, range 1..3.999)*/
  7157. #ifdef MRV_LSC_B_SAMPLE_0
  7158. #endif /* MRV_LSC_B_SAMPLE_0 */
  7159. /*****************************************************************************/
  7160. /**
  7161. * register: isp_lsc_gb_table_data: Sample table green (blue) (0x00000020)
  7162. *
  7163. *****************************************************************************/
  7164. /* Slice: gb_sample_1:*/
  7165. /* correction factor at sample point (fixed point number: 2 bits integer with */
  7166. /* 10-bit fractional part, range 1..3.999)*/
  7167. #ifdef MRV_LSC_GB_SAMPLE_1
  7168. #endif /* MRV_LSC_GB_SAMPLE_1 */
  7169. /* Slice: gb_sample_0:*/
  7170. /* correction factor at sample point (fixed point number: 2 bits integer with */
  7171. /* 10-bit fractional part, range 1..3.999)*/
  7172. #ifdef MRV_LSC_GB_SAMPLE_0
  7173. #endif /* MRV_LSC_GB_SAMPLE_0 */
  7174. /*****************************************************************************/
  7175. /**
  7176. * register: isp_lsc_xgrad_01: Gradient table x (0x00000024)
  7177. *
  7178. *****************************************************************************/
  7179. /* Slice: xgrad_1:*/
  7180. /* factor for x-gradient calculation of sector 1 */
  7181. #ifdef MRV_LSC_XGRAD_1
  7182. #endif /* MRV_LSC_XGRAD_1 */
  7183. /* Slice: xgrad_0:*/
  7184. /* factor for x-gradient calculation of sector 0 */
  7185. #ifdef MRV_LSC_XGRAD_0
  7186. #endif /* MRV_LSC_XGRAD_0 */
  7187. /*****************************************************************************/
  7188. /**
  7189. * register: isp_lsc_xgrad_23: Gradient table x (0x00000028)
  7190. *
  7191. *****************************************************************************/
  7192. /* Slice: xgrad_3:*/
  7193. /* factor for x-gradient calculation of sector 3 */
  7194. #ifdef MRV_LSC_XGRAD_3
  7195. #endif /* MRV_LSC_XGRAD_3 */
  7196. /* Slice: xgrad_2:*/
  7197. /* factor for x-gradient calculation of sector 2 */
  7198. #ifdef MRV_LSC_XGRAD_2
  7199. #endif /* MRV_LSC_XGRAD_2 */
  7200. /*****************************************************************************/
  7201. /**
  7202. * register: isp_lsc_xgrad_45: Gradient table x (0x0000002c)
  7203. *
  7204. *****************************************************************************/
  7205. /* Slice: xgrad_5:*/
  7206. /* factor for x-gradient calculation of sector 5 */
  7207. #ifdef MRV_LSC_XGRAD_5
  7208. #endif /* MRV_LSC_XGRAD_5 */
  7209. /* Slice: xgrad_4:*/
  7210. /* factor for x-gradient calculation of sector 4 */
  7211. #ifdef MRV_LSC_XGRAD_4
  7212. #endif /* MRV_LSC_XGRAD_4 */
  7213. /*****************************************************************************/
  7214. /**
  7215. * register: isp_lsc_xgrad_67: Gradient table x (0x00000030)
  7216. *
  7217. *****************************************************************************/
  7218. /* Slice: xgrad_7:*/
  7219. /* factor for x-gradient calculation of sector 7 */
  7220. #ifdef MRV_LSC_XGRAD_7
  7221. #endif /* MRV_LSC_XGRAD_7 */
  7222. /* Slice: xgrad_6:*/
  7223. /* factor for x-gradient calculation of sector 6 */
  7224. #ifdef MRV_LSC_XGRAD_6
  7225. #endif /* MRV_LSC_XGRAD_6 */
  7226. /*****************************************************************************/
  7227. /**
  7228. * register: isp_lsc_ygrad_01: Gradient table y (0x00000034)
  7229. *
  7230. *****************************************************************************/
  7231. /* Slice: ygrad_1:*/
  7232. /* factor for y-gradient calculation of sector 1 */
  7233. #ifdef MRV_LSC_YGRAD_1
  7234. #endif /* MRV_LSC_YGRAD_1 */
  7235. /* Slice: ygrad_0:*/
  7236. /* factor for y-gradient calculation of sector 0 */
  7237. #ifdef MRV_LSC_YGRAD_0
  7238. #endif /* MRV_LSC_YGRAD_0 */
  7239. /*****************************************************************************/
  7240. /**
  7241. * register: isp_lsc_ygrad_23: Gradient table y (0x00000038)
  7242. *
  7243. *****************************************************************************/
  7244. /* Slice: ygrad_3:*/
  7245. /* factor for y-gradient calculation of sector 3 */
  7246. #ifdef MRV_LSC_YGRAD_3
  7247. #endif /* MRV_LSC_YGRAD_3 */
  7248. /* Slice: ygrad_2:*/
  7249. /* factor for y-gradient calculation of sector 2 */
  7250. #ifdef MRV_LSC_YGRAD_2
  7251. #endif /* MRV_LSC_YGRAD_2 */
  7252. /*****************************************************************************/
  7253. /**
  7254. * register: isp_lsc_ygrad_45: Gradient table y (0x0000003c)
  7255. *
  7256. *****************************************************************************/
  7257. /* Slice: ygrad_5:*/
  7258. /* factor for y-gradient calculation of sector 5 */
  7259. #ifdef MRV_LSC_YGRAD_5
  7260. #endif /* MRV_LSC_YGRAD_5 */
  7261. /* Slice: ygrad_4:*/
  7262. /* factor for y-gradient calculation of sector 4 */
  7263. #ifdef MRV_LSC_YGRAD_4
  7264. #endif /* MRV_LSC_YGRAD_4 */
  7265. /*****************************************************************************/
  7266. /**
  7267. * register: isp_lsc_ygrad_67: Gradient table y (0x00000040)
  7268. *
  7269. *****************************************************************************/
  7270. /* Slice: ygrad_7:*/
  7271. /* factor for y-gradient calculation of sector 7 */
  7272. #ifdef MRV_LSC_YGRAD_7
  7273. #endif /* MRV_LSC_YGRAD_7 */
  7274. /* Slice: ygrad_6:*/
  7275. /* factor for y-gradient calculation of sector 6 */
  7276. #ifdef MRV_LSC_YGRAD_6
  7277. #endif /* MRV_LSC_YGRAD_6 */
  7278. /*****************************************************************************/
  7279. /**
  7280. * register: isp_lsc_xsize_01: Size table (0x00000044)
  7281. *
  7282. *****************************************************************************/
  7283. /* Slice: x_sect_size_1:*/
  7284. /* sector size 1 in x-direction */
  7285. #ifdef MRV_LSC_X_SECT_SIZE_1
  7286. #endif /* MRV_LSC_X_SECT_SIZE_1 */
  7287. /* Slice: x_sect_size_0:*/
  7288. /* sector size 0 in x-direction */
  7289. #ifdef MRV_LSC_X_SECT_SIZE_0
  7290. #endif /* MRV_LSC_X_SECT_SIZE_0 */
  7291. /*****************************************************************************/
  7292. /**
  7293. * register: isp_lsc_xsize_23: Size table (0x00000048)
  7294. *
  7295. *****************************************************************************/
  7296. /* Slice: x_sect_size_3:*/
  7297. /* sector size 3 in x-direction */
  7298. #ifdef MRV_LSC_X_SECT_SIZE_3
  7299. #endif /* MRV_LSC_X_SECT_SIZE_3 */
  7300. /* Slice: x_sect_size_2:*/
  7301. /* sector size 2 in x-direction */
  7302. #ifdef MRV_LSC_X_SECT_SIZE_2
  7303. #endif /* MRV_LSC_X_SECT_SIZE_2 */
  7304. /*****************************************************************************/
  7305. /**
  7306. * register: isp_lsc_xsize_45: Size table (0x0000004c)
  7307. *
  7308. *****************************************************************************/
  7309. /* Slice: x_sect_size_5:*/
  7310. /* sector size 5 in x-direction */
  7311. #ifdef MRV_LSC_X_SECT_SIZE_5
  7312. #endif /* MRV_LSC_X_SECT_SIZE_5 */
  7313. /* Slice: x_sect_size_4:*/
  7314. /* sector size 4in x-direction */
  7315. #ifdef MRV_LSC_X_SECT_SIZE_4
  7316. #endif /* MRV_LSC_X_SECT_SIZE_4 */
  7317. /*****************************************************************************/
  7318. /**
  7319. * register: isp_lsc_xsize_67: Size table (0x00000050)
  7320. *
  7321. *****************************************************************************/
  7322. /* Slice: x_sect_size_7:*/
  7323. /* sector size 7 in x-direction */
  7324. #ifdef MRV_LSC_X_SECT_SIZE_7
  7325. #endif /* MRV_LSC_X_SECT_SIZE_7 */
  7326. /* Slice: x_sect_size_6:*/
  7327. /* sector size 6 in x-direction */
  7328. #ifdef MRV_LSC_X_SECT_SIZE_6
  7329. #endif /* MRV_LSC_X_SECT_SIZE_6 */
  7330. /*****************************************************************************/
  7331. /**
  7332. * register: isp_lsc_ysize_01: Size table (0x00000054)
  7333. *
  7334. *****************************************************************************/
  7335. /* Slice: y_sect_size_1:*/
  7336. /* sector size 1 in y-direction */
  7337. #ifdef MRV_LSC_Y_SECT_SIZE_1
  7338. #endif /* MRV_LSC_Y_SECT_SIZE_1 */
  7339. /* Slice: y_sect_size_0:*/
  7340. /* sector size 0 in y-direction */
  7341. #ifdef MRV_LSC_Y_SECT_SIZE_0
  7342. #endif /* MRV_LSC_Y_SECT_SIZE_0 */
  7343. /*****************************************************************************/
  7344. /**
  7345. * register: isp_lsc_ysize_23: Size table (0x00000058)
  7346. *
  7347. *****************************************************************************/
  7348. /* Slice: y_sect_size_3:*/
  7349. /* sector size 3 in y-direction */
  7350. #ifdef MRV_LSC_Y_SECT_SIZE_3
  7351. #endif /* MRV_LSC_Y_SECT_SIZE_3 */
  7352. /* Slice: y_sect_size_2:*/
  7353. /* sector size 2 in y-direction */
  7354. #ifdef MRV_LSC_Y_SECT_SIZE_2
  7355. #endif /* MRV_LSC_Y_SECT_SIZE_2 */
  7356. /*****************************************************************************/
  7357. /**
  7358. * register: isp_lsc_ysize_45: Size table (0x0000005c)
  7359. *
  7360. *****************************************************************************/
  7361. /* Slice: y_sect_size_5:*/
  7362. /* sector size 5 in y-direction */
  7363. #ifdef MRV_LSC_Y_SECT_SIZE_5
  7364. #endif /* MRV_LSC_Y_SECT_SIZE_5 */
  7365. /* Slice: y_sect_size_4:*/
  7366. /* sector size 4 in y-direction */
  7367. #ifdef MRV_LSC_Y_SECT_SIZE_4
  7368. #endif /* MRV_LSC_Y_SECT_SIZE_4 */
  7369. /*****************************************************************************/
  7370. /**
  7371. * register: isp_lsc_ysize_67: Size table (0x00000060)
  7372. *
  7373. *****************************************************************************/
  7374. /* Slice: y_sect_size_7:*/
  7375. /* sector size 7 in y-direction */
  7376. #ifdef MRV_LSC_Y_SECT_SIZE_7
  7377. #endif /* MRV_LSC_Y_SECT_SIZE_7 */
  7378. /* Slice: y_sect_size_6:*/
  7379. /* sector size 6 in y-direction */
  7380. #ifdef MRV_LSC_Y_SECT_SIZE_6
  7381. #endif /* MRV_LSC_Y_SECT_SIZE_6 */
  7382. /*****************************************************************************/
  7383. /**
  7384. * register: isp_lsc_table_sel: Lens shade table set selection (0x00000064)
  7385. *
  7386. *****************************************************************************/
  7387. /* Slice: table_sel:*/
  7388. /* 0: next active tables set is table set 0.*/
  7389. /* 1: next active tables set is table set 1.*/
  7390. /* Table selection is object of a shadowing mechnism. The current status is */
  7391. /* visible at ISP_LSC_STATUS::active_table.*/
  7392. #ifdef MRV_LSC_TABLE_SEL
  7393. #define MRV_LSC_TABLE_SEL_BANK0 (0U)
  7394. #define MRV_LSC_TABLE_SEL_BANK1 (1U)
  7395. #endif /* MRV_LSC_TABLE_SEL */
  7396. /*****************************************************************************/
  7397. /**
  7398. * register: isp_lsc_status: Lens shade status (0x00000068)
  7399. *
  7400. *****************************************************************************/
  7401. /* Slice: active_table:*/
  7402. /* 0: currently active tables set is table set 0 */
  7403. /* 1: currently active tables set is table set 1 */
  7404. #ifdef MRV_LSC_ACTIVE_TABLE
  7405. #define MRV_LSC_ACTIVE_TABLE_BANK0 (0U)
  7406. #define MRV_LSC_ACTIVE_TABLE_BANK1 (1U)
  7407. #endif /* MRV_LSC_ACTIVE_TABLE */
  7408. /* Slice: lsc_en_status:*/
  7409. /* 0: lens shading correction is currently off */
  7410. /* 1: lens shading correction is currently on */
  7411. #ifdef MRV_LSC_LSC_EN_STATUS
  7412. #endif /* MRV_LSC_LSC_EN_STATUS */
  7413. /*****************************************************************************/
  7414. /* ISP Chromatic Aberration Correction Registers */
  7415. /*****************************************************************************/
  7416. /*****************************************************************************/
  7417. /**
  7418. * register: isp_cac_ctrl: Control register for chromatic aberration
  7419. * correction (0x00000000)
  7420. *
  7421. *****************************************************************************/
  7422. /* Slice: h_clip_mode:*/
  7423. /* Defines the maximum red/blue pixel shift in horizontal direction at pixel */
  7424. /* positions, that require a larger displacement, the maximum shift value is */
  7425. /* used instead (vector clipping)*/
  7426. /**/
  7427. /* 0: Set horizontal vector clipping to +/-4 pixel displacement (Default)*/
  7428. /* 1: Set horizontal vector clipping to +/-4 or +/-5 pixel displacement */
  7429. /* depending on pixel position inside the Bayer raster (dynamic switching */
  7430. /* between +/-4 and +/-5)*/
  7431. #ifdef MRV_CAC_H_CLIP_MODE
  7432. #define MRV_CAC_H_CLIP_MODE_FIX4 0 /* 0: Set horizontal vector clipping */
  7433. /* to +/-4 pixel displacement (Default) */
  7434. #define MRV_CAC_H_CLIP_MODE_DYN5 1 /* 1: Set horizontal vector clipping */
  7435. /* to +/-4 or +/-5 pixel displacement depending on */
  7436. /* pixel position inside the Bayer raster */
  7437. /* (dynamic switching between +/-4 and +/-5) */
  7438. #endif /* MRV_CAC_H_CLIP_MODE */
  7439. /* Slice: v_clip_mode:*/
  7440. /* Defines the maximum red/blue pixel shift in vertical direction */
  7441. /* 00: Set vertical vector clipping to +/-2 pixel ; fix filter_enable (Default)*/
  7442. /* 01: Set vertical vector clipping to +/-3 pixel; dynamic filter_enable for */
  7443. /* chroma low pass filter */
  7444. /* 10: Set vertical vector clipping +/-3 or +/-4 pixel displacement depending */
  7445. /* on pixel position inside the Bayer raster (dynamic switching between +/-3 and +/-4)*/
  7446. /* 11: reserved */
  7447. #ifdef MRV_CAC_V_CLIP_MODE
  7448. #define MRV_CAC_V_CLIP_MODE_FIX2 0 /* 00: Set vertical vector clipping to +/-2 pixel; */
  7449. /* fix filter_enable (Default) */
  7450. #define MRV_CAC_V_CLIP_MODE_FIX3 1 /* 01: Set vertical vector clipping to +/-3 pixel; */
  7451. /* dynamic filter_enable for chroma low pass filter */
  7452. #define MRV_CAC_V_CLIP_MODE_DYN4 2 /* 10: Set vertical vector clipping +/-3 or +/-4 pixel */
  7453. /* displacement depending on pixel position inside */
  7454. /* the Bayer raster (dynamic switching between +/-3 and +/-4) */
  7455. #endif /* MRV_CAC_V_CLIP_MODE */
  7456. /* Slice: cac_en:*/
  7457. /* 0: chromatic aberration correction off */
  7458. /* 1: chromatic aberration correction on */
  7459. #ifdef MRV_CAC_CAC_EN
  7460. #define MRV_CAC_CAC_EN_PROCESS 1
  7461. #define MRV_CAC_CAC_EN_BYPASS 0
  7462. #endif /* MRV_CAC_CAC_EN */
  7463. /*****************************************************************************/
  7464. /**
  7465. * register: isp_cac_count_start: Preload values for CAC pixel and line
  7466. * counter (0x00000004)
  7467. *
  7468. *****************************************************************************/
  7469. /* Slice: v_count_start:*/
  7470. /* 12 bit v_count preload value (range 4095 ... 1) of the vertical CAC line */
  7471. /* counter. Before frame start v_count has to be preloaded with */
  7472. /* (v_size/2 + v_center_offset), with v_size the image height and v_center_offset */
  7473. /* the vertical distance between image center and optical center.*/
  7474. /**/
  7475. /* After frame start the v_count decrements with every line until a value of zero */
  7476. /* is reached for the line in the optical center. Than the v_sign bit toggles and */
  7477. /* the v_counter decrements with every line until end of frame.*/
  7478. #ifdef MRV_CAC_V_COUNT_START
  7479. #define MRV_CAC_V_COUNT_START_MIN 1
  7480. #define MRV_CAC_V_COUNT_START_MAX (MRV_CAC_V_COUNT_START_MASK >> MRV_CAC_V_COUNT_START_SHIFT)
  7481. #endif /* MRV_CAC_V_COUNT_START */
  7482. /* Slice: h_count_start:*/
  7483. /* 12 bit h_count preload value (range 4095 .. 1) of the horizontal CAC pixel */
  7484. /* counter. Before line start h_count has to be preloaded with (h_size/2 + h_center_offset),*/
  7485. /* with h_size the image width and h_center_offset the horizontal distance between image */
  7486. /* center and optical center.*/
  7487. /**/
  7488. /* After line start the h_count decrements with every pixel until a value of zero is */
  7489. /* reached for the column in the optical center. Than the h_sign bit toggles and the */
  7490. /* h_counter increments with every pixel until end of line.*/
  7491. #ifdef MRV_CAC_H_COUNT_START
  7492. #define MRV_CAC_H_COUNT_START_MIN 1
  7493. #define MRV_CAC_H_COUNT_START_MAX (MRV_CAC_H_COUNT_START_MASK >> MRV_CAC_H_COUNT_START_SHIFT)
  7494. #endif /* MRV_CAC_H_COUNT_START */
  7495. /*****************************************************************************/
  7496. /**
  7497. * register: isp_cac_a: Linear Parameters for radial shift calculation (0x00000008)
  7498. *
  7499. *****************************************************************************/
  7500. /* Slice: A_Blue:*/
  7501. /* Parameter A_Blue for radial blue shift calculation, according to */
  7502. /* (A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/
  7503. /* It is a 9 bit twos complement integer with 4 fractional digits value and */
  7504. /* value range from -16 up to 15.9375.*/
  7505. #ifdef MRV_CAC_A_BLUE
  7506. #define MRV_CAC_A_BLUE_MAX (MRV_CAC_A_BLUE_MASK >> (MRV_CAC_A_BLUE_SHIFT))
  7507. #define MRV_CAC_A_BLUE_MIN 0
  7508. #endif /* MRV_CAC_A_BLUE */
  7509. /* Slice: A_Red:*/
  7510. /* Parameter A_Red for radial red shift calculation, according to */
  7511. /* (A_Red * r + B_Red * r^2 + C_Red * r^3).*/
  7512. /* It is a 9 bit twos complement integer with 4 fractional digits value and */
  7513. /* value range from -16 up to 15.9375.*/
  7514. #ifdef MRV_CAC_A_RED
  7515. #define MRV_CAC_A_RED_MAX (MRV_CAC_A_RED_MASK >> (MRV_CAC_A_RED_SHIFT))
  7516. #define MRV_CAC_A_RED_MIN 0
  7517. #endif /* MRV_CAC_A_RED */
  7518. /*****************************************************************************/
  7519. /**
  7520. * register: isp_cac_b: Square Parameters for radial shift calculation (0x0000000c)
  7521. *
  7522. *****************************************************************************/
  7523. /* Slice: B_Blue:*/
  7524. /* Parameter B_Blue for radial blue shift calculation, according to */
  7525. /* (A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/
  7526. /* It is a 9 bit twos complement integer with 4 fractional digits value and */
  7527. /* value range from -16 up to 15.9375.*/
  7528. #ifdef MRV_CAC_B_BLUE
  7529. #define MRV_CAC_B_BLUE_MAX (MRV_CAC_B_BLUE_MASK >> (MRV_CAC_B_BLUE_SHIFT))
  7530. #define MRV_CAC_B_BLUE_MIN 0
  7531. #endif /* MRV_CAC_B_BLUE */
  7532. /* Slice: B_Red:*/
  7533. /* Parameter B_Red for radial red shift calculation, according to */
  7534. /* (A_Red * r + B_Red * r^2 + C_Red * r^3).*/
  7535. /* It is a 9 bit twos complement integer with 4 fractional digits value and */
  7536. /* value range from -16 up to 15.9375.*/
  7537. #ifdef MRV_CAC_B_RED
  7538. #define MRV_CAC_B_RED_MAX (MRV_CAC_B_RED_MASK >> (MRV_CAC_B_RED_SHIFT))
  7539. #define MRV_CAC_B_RED_MIN 0
  7540. #endif /* MRV_CAC_B_RED */
  7541. /*****************************************************************************/
  7542. /**
  7543. * register: isp_cac_c: Cubical Parameters for radial shift calculation (0x00000010)
  7544. *
  7545. *****************************************************************************/
  7546. /* Slice: C_Blue:*/
  7547. /* Parameter C_Blue for radial blue shift calculation, according to */
  7548. /* (A_Blue * r + B_Blue * r^2 + C_Blue * r^3).*/
  7549. /* It is a 9 bit twos complement integer with 4 fractional digits value and */
  7550. /* value range from -16 up to 15.9375.*/
  7551. #ifdef MRV_CAC_C_BLUE
  7552. #define MRV_CAC_C_BLUE_MAX (MRV_CAC_C_BLUE_MASK >> (MRV_CAC_C_BLUE_SHIFT))
  7553. #define MRV_CAC_C_BLUE_MIN 0
  7554. #endif /* MRV_CAC_C_BLUE */
  7555. /* Slice: C_Red:*/
  7556. /* Parameter C_Red for radial red shift calculation, according to */
  7557. /* (A_Red * r + B_Red * r^2 + C_Red * r^3).*/
  7558. /* It is a 9 bit twos complement integer with 4 fractional digits value and */
  7559. /* value range from -16 up to 15.9375.*/
  7560. #ifdef MRV_CAC_C_RED
  7561. #define MRV_CAC_C_RED_MAX (MRV_CAC_C_RED_MASK >> (MRV_CAC_C_RED_SHIFT))
  7562. #define MRV_CAC_C_RED_MIN 0
  7563. #endif /* MRV_CAC_C_RED */
  7564. /*****************************************************************************/
  7565. /**
  7566. * register: isp_cac_x_norm: Normalization parameters for calculation of image
  7567. * coordinate x_d relative to optical center (0x00000014)
  7568. *
  7569. *****************************************************************************/
  7570. /* Slice: x_ns:*/
  7571. /* Horizontal normalization shift parameter x_ns (4 bit unsigned integer)*/
  7572. /* in equation x_d[7:0] = (((h_count <% 4) %> x_ns) * x_nf) >> 5 */
  7573. #ifdef MRV_CAC_X_NS
  7574. #define MRV_CAC_X_NS_MIN 0
  7575. #define MRV_CAC_X_NS_MAX (MRV_CAC_X_NS_MASK >> MRV_CAC_X_NS_SHIFT)
  7576. #endif /* MRV_CAC_X_NS */
  7577. /* Slice: x_nf:*/
  7578. /* Horizontal scaling or normalization factor x_nf (5 bit unsigned integer)*/
  7579. /* range 0 .. 31 in equation x_d[7:0] = (((h_count <% 4) %> x_ns) * x_nf) >> 5 */
  7580. #ifdef MRV_CAC_X_NF
  7581. #define MRV_CAC_X_NF_MIN 0
  7582. #define MRV_CAC_X_NF_MAX 31
  7583. #endif /* MRV_CAC_X_NF */
  7584. /*****************************************************************************/
  7585. /**
  7586. * register: isp_cac_y_norm: Normalization parameters for calculation of image
  7587. * coordinate y_d relative to optical center (0x00000018)
  7588. *
  7589. *****************************************************************************/
  7590. /* Slice: y_ns:*/
  7591. /* Vertical normalization shift parameter y_ns (4 bit unsigned integer)*/
  7592. /* in equation y_d[7:0] = (((v_count <% 4) %> y_ns) * y_nf) >> 5 */
  7593. #ifdef MRV_CAC_Y_NS
  7594. #define MRV_CAC_Y_NS_MIN 0
  7595. #define MRV_CAC_Y_NS_MAX (MRV_CAC_Y_NS_MASK >> MRV_CAC_Y_NS_SHIFT)
  7596. #endif /* MRV_CAC_Y_NS */
  7597. /* Slice: y_nf:*/
  7598. /* Vertical scaling or normalization factor y_nf (5 bit unsigned integer)*/
  7599. /* range 0 .. 31 in equation y_d[7:0] = (((v_count <% 4) %> y_ns) * y_nf) >> 5 */
  7600. #ifdef MRV_CAC_Y_NF
  7601. #define MRV_CAC_Y_NF_MIN 0
  7602. #define MRV_CAC_Y_NF_MAX 31
  7603. #endif /* MRV_CAC_Y_NF */
  7604. /*****************************************************************************/
  7605. /* ISP Exposure Measurement Registers */
  7606. /*****************************************************************************/
  7607. /*****************************************************************************/
  7608. /**
  7609. * register: isp_exp_ctrl: Exposure control (0x00000000)
  7610. *
  7611. *****************************************************************************/
  7612. /* Slice: exp_meas_mode:*/
  7613. /* '1' luminance calculation according to Y=(R+G+B) x 0.332 (85/256)*/
  7614. /* '0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B */
  7615. #ifdef MRV_AE_EXP_MEAS_MODE
  7616. #define MRV_AE_EXP_MEAS_MODE_1 1 /* '1' luminance calculation according to Y=(R+G+B) x 0.332 (85/256) */
  7617. #define MRV_AE_EXP_MEAS_MODE_0 0 /* '0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B */
  7618. #endif /* MRV_AE_EXP_MEAS_MODE */
  7619. /* Slice: autostop:*/
  7620. /* '1' stop measuring after a complete frame */
  7621. /* '0' continous measurement */
  7622. #ifdef MRV_AE_AUTOSTOP
  7623. #define MRV_AE_AUTOSTOP_STOP_MEASURING 1 /* stop measuring after a complete frame */
  7624. #define MRV_AE_AUTOSTOP_CONTINOUS_MEASURING 0 /* don't stop measurement, continoue with next frame */
  7625. #endif /* MRV_AE_AUTOSTOP */
  7626. /* Slice: exp_start:*/
  7627. /* '1' start measuring a frame. The exp block will reset this bit and halt */
  7628. /* after completing one frame, if bit "autostop" is set to '1'.*/
  7629. #ifdef MRV_AE_EXP_START
  7630. #define MRV_AE_EXP_START_PROCESS 1 /* 1: processing is activated */
  7631. #define MRV_AE_EXP_START_BYPASS 0 /* 0: processing is deactivated, bypass mode is selected */
  7632. #endif /* MRV_AE_EXP_START */
  7633. /*****************************************************************************/
  7634. /**
  7635. * register: isp_exp_h_offset: Horizontal offset for first block (0x00000004)
  7636. *
  7637. *****************************************************************************/
  7638. /* Slice: isp_exp_h_offset:*/
  7639. /* Horizontal offset of first block in pixels.*/
  7640. /* 0 <= value <= 3920 */
  7641. #ifdef MRV_AE_ISP_EXP_H_OFFSET
  7642. #define MRV_AE_ISP_EXP_H_OFFSET_MIN 0x00000000
  7643. #define MRV_AE_ISP_EXP_H_OFFSET_MAX 0x00000F50 /* 4096-176 */
  7644. #endif /* MRV_AE_ISP_EXP_H_OFFSET */
  7645. /*****************************************************************************/
  7646. /**
  7647. * register: isp_exp_v_offset: Vertical offset for first block (0x00000008)
  7648. *
  7649. *****************************************************************************/
  7650. /* Slice: isp_exp_v_offset:*/
  7651. /* Vertical offset of first block in pixels.*/
  7652. /* 0 <= value <= 1806 */
  7653. #ifdef MRV_AE_ISP_EXP_V_OFFSET
  7654. #define MRV_AE_ISP_EXP_V_OFFSET_MIN 0x00000000
  7655. #define MRV_AE_ISP_EXP_V_OFFSET_MAX 0x00000B74 /* 3072-140 */
  7656. #endif /* MRV_AE_ISP_EXP_V_OFFSET */
  7657. /*****************************************************************************/
  7658. /**
  7659. * register: isp_exp_h_size: Horizontal size of one block (0x0000000c)
  7660. *
  7661. *****************************************************************************/
  7662. /* Slice: isp_exp_h_size:*/
  7663. /* Horizontal size in pixels of one block.*/
  7664. /* 35 <= value <= 516 */
  7665. #ifdef MRV_AE_ISP_EXP_H_SIZE
  7666. #define MRV_AE_ISP_EXP_H_SIZE_MIN 0x00000023
  7667. #define MRV_AE_ISP_EXP_H_SIZE_MAX 0x00000333
  7668. #endif /* MRV_AE_ISP_EXP_H_SIZE */
  7669. /*****************************************************************************/
  7670. /**
  7671. * register: isp_exp_v_size: Vertical size of one block (0x00000010)
  7672. *
  7673. *****************************************************************************/
  7674. /* Slice: isp_exp_v_size:*/
  7675. /* Vertical size in pixels of one block.*/
  7676. /* 28 <= value <= 390 */
  7677. #ifdef MRV_AE_ISP_EXP_V_SIZE
  7678. #define MRV_AE_ISP_EXP_V_SIZE_VALID_MASK (MRV_AE_ISP_EXP_V_SIZE_MASK & ~0x00000001)
  7679. #define MRV_AE_ISP_EXP_V_SIZE_MIN 0x0000001C
  7680. #define MRV_AE_ISP_EXP_V_SIZE_MAX 0x00000266
  7681. #endif /* MRV_AE_ISP_EXP_V_SIZE */
  7682. /*****************************************************************************/
  7683. /**
  7684. * register: isp_exp_mean_00: Mean luminance value of block 00 (0x00000014)
  7685. *
  7686. *****************************************************************************/
  7687. /* Slice: isp_exp_mean_00:*/
  7688. /* Mean luminance value of block 00 (x,y)*/
  7689. #ifdef MRV_AE_ISP_EXP_MEAN_00
  7690. #endif /* MRV_AE_ISP_EXP_MEAN_00 */
  7691. /*****************************************************************************/
  7692. /**
  7693. * register: isp_exp_mean_10: Mean luminance value of block 10 (0x00000018)
  7694. *
  7695. *****************************************************************************/
  7696. /* Slice: isp_exp_mean_10:*/
  7697. /* Mean luminance value of block 10 (x,y)*/
  7698. #ifdef MRV_AE_ISP_EXP_MEAN_10
  7699. #endif /* MRV_AE_ISP_EXP_MEAN_10 */
  7700. /*****************************************************************************/
  7701. /**
  7702. * register: isp_exp_mean_20: Mean luminance value of block 20 (0x0000001c)
  7703. *
  7704. *****************************************************************************/
  7705. /* Slice: isp_exp_mean_20:*/
  7706. /* Mean luminance value of block 20 (x,y)*/
  7707. #ifdef MRV_AE_ISP_EXP_MEAN_20
  7708. #endif /* MRV_AE_ISP_EXP_MEAN_20 */
  7709. /*****************************************************************************/
  7710. /**
  7711. * register: isp_exp_mean_30: Mean luminance value of block 30 (0x00000020)
  7712. *
  7713. *****************************************************************************/
  7714. /* Slice: isp_exp_mean_30:*/
  7715. /* Mean luminance value of block 30 (x,y)*/
  7716. #ifdef MRV_AE_ISP_EXP_MEAN_30
  7717. #endif /* MRV_AE_ISP_EXP_MEAN_30 */
  7718. /*****************************************************************************/
  7719. /**
  7720. * register: isp_exp_mean_40: Mean luminance value of block 40 (0x00000024)
  7721. *
  7722. *****************************************************************************/
  7723. /* Slice: isp_exp_mean_40:*/
  7724. /* Mean luminance value of block 40 (x,y)*/
  7725. #ifdef MRV_AE_ISP_EXP_MEAN_40
  7726. #endif /* MRV_AE_ISP_EXP_MEAN_40 */
  7727. /*****************************************************************************/
  7728. /**
  7729. * register: isp_exp_mean_01: Mean luminance value of block 01 (0x00000028)
  7730. *
  7731. *****************************************************************************/
  7732. /* Slice: isp_exp_mean_01:*/
  7733. /* Mean luminance value of block 01 (x,y)*/
  7734. #ifdef MRV_AE_ISP_EXP_MEAN_01
  7735. #endif /* MRV_AE_ISP_EXP_MEAN_01 */
  7736. /*****************************************************************************/
  7737. /**
  7738. * register: isp_exp_mean_11: Mean luminance value of block 11 (0x0000002c)
  7739. *
  7740. *****************************************************************************/
  7741. /* Register: isp_exp_mean_11: Mean luminance value of block 11 (0x0000002c)*/
  7742. /* Slice: isp_exp_mean_11:*/
  7743. /* Mean luminance value of block 11 (x,y)*/
  7744. #ifdef MRV_AE_ISP_EXP_MEAN_11
  7745. #endif /* MRV_AE_ISP_EXP_MEAN_11 */
  7746. /*****************************************************************************/
  7747. /**
  7748. * register: isp_exp_mean_21: Mean luminance value of block 21 (0x00000030)
  7749. *
  7750. *****************************************************************************/
  7751. /* Slice: isp_exp_mean_21:*/
  7752. /* Mean luminance value of block 21 (x,y)*/
  7753. #ifdef MRV_AE_ISP_EXP_MEAN_21
  7754. #endif /* MRV_AE_ISP_EXP_MEAN_21 */
  7755. /*****************************************************************************/
  7756. /**
  7757. * register: isp_exp_mean_31: Mean luminance value of block 31 (0x00000034)
  7758. *
  7759. *****************************************************************************/
  7760. /* Slice: isp_exp_mean_31:*/
  7761. /* Mean luminance value of block 31 (x,y)*/
  7762. #ifdef MRV_AE_ISP_EXP_MEAN_31
  7763. #endif /* MRV_AE_ISP_EXP_MEAN_31 */
  7764. /*****************************************************************************/
  7765. /**
  7766. * register: isp_exp_mean_41: Mean luminance value of block 41 (0x00000038)
  7767. *
  7768. *****************************************************************************/
  7769. /* Slice: isp_exp_mean_41:*/
  7770. /* Mean luminance value of block 41 (x,y)*/
  7771. #ifdef MRV_AE_ISP_EXP_MEAN_41
  7772. #endif /* MRV_AE_ISP_EXP_MEAN_41 */
  7773. /*****************************************************************************/
  7774. /**
  7775. * register: isp_exp_mean_02: Mean luminance value of block 02 (0x0000003c)
  7776. *
  7777. *****************************************************************************/
  7778. /* Slice: isp_exp_mean_02:*/
  7779. /* Mean luminance value of block 02 (x,y)*/
  7780. #ifdef MRV_AE_ISP_EXP_MEAN_02
  7781. #endif /* MRV_AE_ISP_EXP_MEAN_02 */
  7782. /*****************************************************************************/
  7783. /**
  7784. * register: isp_exp_mean_12: Mean luminance value of block 12 (0x00000040)
  7785. *
  7786. *****************************************************************************/
  7787. /* Slice: isp_exp_mean_12:*/
  7788. /* Mean luminance value of block 12 (x,y)*/
  7789. #ifdef MRV_AE_ISP_EXP_MEAN_12
  7790. #endif /* MRV_AE_ISP_EXP_MEAN_12 */
  7791. /*****************************************************************************/
  7792. /**
  7793. * register: isp_exp_mean_22: Mean luminance value of block 22 (0x00000044)
  7794. *
  7795. *****************************************************************************/
  7796. /* Slice: isp_exp_mean_22:*/
  7797. /* Mean luminance value of block 22 (x,y)*/
  7798. #ifdef MRV_AE_ISP_EXP_MEAN_22
  7799. #endif /* MRV_AE_ISP_EXP_MEAN_22 */
  7800. /*****************************************************************************/
  7801. /**
  7802. * register: isp_exp_mean_32: Mean luminance value of block 32 (0x00000048)
  7803. *
  7804. *****************************************************************************/
  7805. /* Slice: isp_exp_mean_32:*/
  7806. /* Mean luminance value of block 32 (x,y)*/
  7807. #ifdef MRV_AE_ISP_EXP_MEAN_32
  7808. #endif /* MRV_AE_ISP_EXP_MEAN_32 */
  7809. /*****************************************************************************/
  7810. /**
  7811. * register: isp_exp_mean_42: Mean luminance value of block 42 (0x0000004c)
  7812. *
  7813. *****************************************************************************/
  7814. /* Slice: isp_exp_mean_42:*/
  7815. /* Mean luminance value of block 42 (x,y)*/
  7816. #ifdef MRV_AE_ISP_EXP_MEAN_42
  7817. #endif /* MRV_AE_ISP_EXP_MEAN_42 */
  7818. /*****************************************************************************/
  7819. /**
  7820. * register: isp_exp_mean_03: Mean luminance value of block 03 (0x00000050)
  7821. *
  7822. *****************************************************************************/
  7823. /* Slice: isp_exp_mean_03:*/
  7824. /* Mean luminance value of block 03 (x,y)*/
  7825. #ifdef MRV_AE_ISP_EXP_MEAN_03
  7826. #endif /* MRV_AE_ISP_EXP_MEAN_03 */
  7827. /*****************************************************************************/
  7828. /**
  7829. * register: isp_exp_mean_13: Mean luminance value of block 13 (0x00000054)
  7830. *
  7831. *****************************************************************************/
  7832. /* Slice: isp_exp_mean_13:*/
  7833. /* Mean luminance value of block 13 (x,y)*/
  7834. #ifdef MRV_AE_ISP_EXP_MEAN_13
  7835. #endif /* MRV_AE_ISP_EXP_MEAN_13 */
  7836. /*****************************************************************************/
  7837. /**
  7838. * register: isp_exp_mean_23: Mean luminance value of block 23 (0x00000058)
  7839. *
  7840. *****************************************************************************/
  7841. /* Slice: isp_exp_mean_23:*/
  7842. /* Mean luminance value of block 23 (x,y)*/
  7843. #ifdef MRV_AE_ISP_EXP_MEAN_23
  7844. #endif /* MRV_AE_ISP_EXP_MEAN_23 */
  7845. /*****************************************************************************/
  7846. /**
  7847. * register: isp_exp_mean_33: Mean luminance value of block 33 (0x0000005c)
  7848. *
  7849. *****************************************************************************/
  7850. /* Slice: isp_exp_mean_33:*/
  7851. /* Mean luminance value of block 33 (x,y)*/
  7852. #ifdef MRV_AE_ISP_EXP_MEAN_33
  7853. #endif /* MRV_AE_ISP_EXP_MEAN_33 */
  7854. /*****************************************************************************/
  7855. /**
  7856. * register: isp_exp_mean_43: Mean luminance value of block 43 (0x00000060)
  7857. *
  7858. *****************************************************************************/
  7859. /* Slice: isp_exp_mean_43:*/
  7860. /* Mean luminance value of block 43 (x,y)*/
  7861. #ifdef MRV_AE_ISP_EXP_MEAN_43
  7862. #endif /* MRV_AE_ISP_EXP_MEAN_43 */
  7863. /*****************************************************************************/
  7864. /**
  7865. * register: isp_exp_mean_04: Mean luminance value of block 04 (0x00000064)
  7866. *
  7867. *****************************************************************************/
  7868. /* Slice: isp_exp_mean_04:*/
  7869. /* Mean luminance value of block 04 (x,y)*/
  7870. #ifdef MRV_AE_ISP_EXP_MEAN_04
  7871. #endif /* MRV_AE_ISP_EXP_MEAN_04 */
  7872. /*****************************************************************************/
  7873. /**
  7874. * register: isp_exp_mean_14: Mean luminance value of block 14 (0x00000068)
  7875. *
  7876. *****************************************************************************/
  7877. /* Slice: isp_exp_mean_14:*/
  7878. /* Mean luminance value of block 14 (x,y)*/
  7879. #ifdef MRV_AE_ISP_EXP_MEAN_14
  7880. #endif /* MRV_AE_ISP_EXP_MEAN_14 */
  7881. /*****************************************************************************/
  7882. /**
  7883. * register: isp_exp_mean_24: Mean luminance value of block 24 (0x0000006c)
  7884. *
  7885. *****************************************************************************/
  7886. /* Slice: isp_exp_mean_24:*/
  7887. /* Mean luminance value of block 24 (x,y)*/
  7888. #ifdef MRV_AE_ISP_EXP_MEAN_24
  7889. #endif /* MRV_AE_ISP_EXP_MEAN_24 */
  7890. /*****************************************************************************/
  7891. /**
  7892. * register: isp_exp_mean_34: Mean luminance value of block 34 (0x00000070)
  7893. *
  7894. *****************************************************************************/
  7895. /* Slice: isp_exp_mean_34:*/
  7896. /* Mean luminance value of block 34 (x,y)*/
  7897. #ifdef MRV_AE_ISP_EXP_MEAN_34
  7898. #endif /* MRV_AE_ISP_EXP_MEAN_34 */
  7899. /*****************************************************************************/
  7900. /**
  7901. * register: isp_exp_mean_44: Mean luminance value of block 44 (0x00000074)
  7902. *
  7903. *****************************************************************************/
  7904. /* Slice: isp_exp_mean_44:*/
  7905. /* Mean luminance value of block 44 (x,y)*/
  7906. #ifdef MRV_AE_ISP_EXP_MEAN_44
  7907. #endif /* MRV_AE_ISP_EXP_MEAN_44 */
  7908. /*****************************************************************************/
  7909. /* ISP Black Level Subtraction Registers */
  7910. /*****************************************************************************/
  7911. /*****************************************************************************/
  7912. /**
  7913. * register: isp_bls_ctrl: global control register (0x00000000)
  7914. *
  7915. *****************************************************************************/
  7916. /* Slice: WINDOW_ENABLE:*/
  7917. /* 0: no measuring is performed */
  7918. /* 1: only window 1 is measured */
  7919. /* 2: only window 2 is measured */
  7920. /* 3: both windows are measured */
  7921. #ifdef MRV_BLS_WINDOW_ENABLE
  7922. #define MRV_BLS_WINDOW_ENABLE_NONE 0U /* 0: no measuring is performed */
  7923. #define MRV_BLS_WINDOW_ENABLE_WND1 1U /* 1: only window 1 is measured */
  7924. #define MRV_BLS_WINDOW_ENABLE_WND2 2U /* 2: only window 2 is measured */
  7925. #define MRV_BLS_WINDOW_ENABLE_BOTH 3U /* 3: both windows are measured */
  7926. #define MRV_BLS_WINDOW_ENABLE_WND1_MASK 0x00000004U
  7927. #define MRV_BLS_WINDOW_ENABLE_WND1_SHIFT 2U
  7928. #define MRV_BLS_WINDOW_ENABLE_WND2_MASK 0x00000008U
  7929. #define MRV_BLS_WINDOW_ENABLE_WND2_SHIFT 3U
  7930. #endif /* MRV_BLS_WINDOW_ENABLE */
  7931. /* Slice: BLS_MODE:*/
  7932. /* 1: subtract measured values */
  7933. /* 0: subtract fixed values */
  7934. #ifdef MRV_BLS_BLS_MODE
  7935. #define MRV_BLS_BLS_MODE_MEAS 1U /* 1: subtract measured values */
  7936. #define MRV_BLS_BLS_MODE_FIX 0U /* 0: subtract fixed values */
  7937. #endif /* MRV_BLS_BLS_MODE */
  7938. /* Slice: BLS_ENABLE:*/
  7939. /* 1: black level subtraction is enabled */
  7940. /* 0: bypass the black level processing */
  7941. #ifdef MRV_BLS_BLS_ENABLE
  7942. #define MRV_BLS_BLS_ENABLE_PROCESS 1U /* 1: black level subtraction is enabled */
  7943. #define MRV_BLS_BLS_ENABLE_BYPASS 0U /* 0: bypass the black level processing */
  7944. #endif /* MRV_BLS_BLS_ENABLE */
  7945. /*****************************************************************************/
  7946. /**
  7947. * register: isp_bls_samples: samples register (0x00000004)
  7948. *
  7949. *****************************************************************************/
  7950. /* Slice: BLS_SAMPLES:*/
  7951. /* This number to the power of two gives the number of measure samples for */
  7952. /* each Bayer position. Range 0x00: 2^0=1 to 0x12: 2^18=262144. This number */
  7953. /* is also the divider for the accumulator for each Bayer position.*/
  7954. /**/
  7955. /* The accumulation will be stopped, if the number of measured pixels for the */
  7956. /* current Bayer position is equal to the number of samples.*/
  7957. /**/
  7958. /* The measure windows must be positioned that way that the number of included */
  7959. /* pixels of each Bayer position included by both windows is equal or greater */
  7960. /* than the number of measure samples calculated by 2^BLS_SAMPLES !*/
  7961. /**/
  7962. /* NOTE:*/
  7963. /* - The number of pixels of one Bayer position is 1/4 of the number of all */
  7964. /* Pixels included by the measure windows.*/
  7965. #ifdef MRV_BLS_BLS_SAMPLES
  7966. #define MRV_BLS_BLS_SAMPLES_MAX (0x00000014U) /* maximum is 2^20 = 1048576 */
  7967. #endif /* MRV_BLS_BLS_SAMPLES */
  7968. /*****************************************************************************/
  7969. /**
  7970. * register: isp_bls_h1_start: window 1 horizontal start (0x00000008)
  7971. *
  7972. *****************************************************************************/
  7973. /* Slice: BLS_H1_START:*/
  7974. /* Black pixel window 1 horizontal start position */
  7975. #ifdef MRV_BLS_BLS_H1_START
  7976. #define MRV_BLS_BLS_H1_START_MAX (MRV_BLS_BLS_H1_START_MASK >> MRV_BLS_BLS_H1_START_SHIFT)
  7977. #endif /* MRV_BLS_BLS_H1_START */
  7978. /*****************************************************************************/
  7979. /**
  7980. * register: isp_bls_h1_stop: window 1 horizontal stop (0x0000000c)
  7981. *
  7982. *****************************************************************************/
  7983. /* Slice: BLS_H1_STOP:*/
  7984. /* Black pixel window 1 horizontal stop position */
  7985. #ifdef MRV_BLS_BLS_H1_STOP
  7986. #define MRV_BLS_BLS_H1_STOP_MAX (MRV_BLS_BLS_H1_STOP_MASK >> MRV_BLS_BLS_H1_STOP_SHIFT)
  7987. #endif /* MRV_BLS_BLS_H1_STOP */
  7988. /*****************************************************************************/
  7989. /**
  7990. * register: isp_bls_v1_start: window 1 vertical start (0x00000010)
  7991. *
  7992. *****************************************************************************/
  7993. /* Slice: BLS_V1_START:*/
  7994. /* Black pixel window 1 vertical start position */
  7995. #ifdef MRV_BLS_BLS_V1_START
  7996. #define MRV_BLS_BLS_V1_START_MAX (MRV_BLS_BLS_V1_START_MASK >> MRV_BLS_BLS_V1_START_SHIFT)
  7997. #endif /* MRV_BLS_BLS_V1_START */
  7998. /*****************************************************************************/
  7999. /**
  8000. * register: isp_bls_v1_stop: window 1 vertical stop (0x00000014)
  8001. *
  8002. *****************************************************************************/
  8003. /* Slice: BLS_V1_STOP:*/
  8004. /* Black pixel window 1 vertical stop position */
  8005. #ifdef MRV_BLS_BLS_V1_STOP
  8006. #define MRV_BLS_BLS_V1_STOP_MAX (MRV_BLS_BLS_V1_STOP_MASK >> MRV_BLS_BLS_V1_STOP_SHIFT)
  8007. #endif /* MRV_BLS_BLS_V1_STOP */
  8008. /*****************************************************************************/
  8009. /**
  8010. * register: isp_bls_h2_start: window 2 horizontal start (0x00000018)
  8011. *
  8012. *****************************************************************************/
  8013. /* Slice: BLS_H2_START:*/
  8014. /* Black pixel window 2 horizontal start position */
  8015. #ifdef MRV_BLS_BLS_H2_START
  8016. #define MRV_BLS_BLS_H2_START_MAX (MRV_BLS_BLS_H2_START_MASK >> MRV_BLS_BLS_H2_START_SHIFT)
  8017. #endif /* MRV_BLS_BLS_H2_START */
  8018. /*****************************************************************************/
  8019. /**
  8020. * register: isp_bls_h2_stop: window 2 horizontal stop (0x0000001c)
  8021. *
  8022. *****************************************************************************/
  8023. /* Slice: BLS_H2_STOP:*/
  8024. /* Black pixel window 2 horizontal stop position */
  8025. #ifdef MRV_BLS_BLS_H2_STOP
  8026. #define MRV_BLS_BLS_H2_STOP_MAX (MRV_BLS_BLS_H2_STOP_MASK >> MRV_BLS_BLS_H2_STOP_SHIFT)
  8027. #endif /* MRV_BLS_BLS_H2_STOP */
  8028. /*****************************************************************************/
  8029. /**
  8030. * register: isp_bls_v2_start: window 2 vertical start (0x00000020)
  8031. *
  8032. *****************************************************************************/
  8033. /* Slice: BLS_V2_START:*/
  8034. /* Black pixel window 2 vertical start position */
  8035. #ifdef MRV_BLS_BLS_V2_START
  8036. #define MRV_BLS_BLS_V2_START_MAX (MRV_BLS_BLS_V2_START_MASK >> MRV_BLS_BLS_V2_START_SHIFT)
  8037. #endif /* MRV_BLS_BLS_V2_START */
  8038. /*****************************************************************************/
  8039. /**
  8040. * register: isp_bls_v2_stop: window 2 vertical stop (0x00000024)
  8041. *
  8042. *****************************************************************************/
  8043. /* Slice: BLS_V2_STOP:*/
  8044. /* Black pixel window 2 vertical stop position */
  8045. #ifdef MRV_BLS_BLS_V2_STOP
  8046. #define MRV_BLS_BLS_V2_STOP_MAX (MRV_BLS_BLS_V2_STOP_MASK >> MRV_BLS_BLS_V2_STOP_SHIFT)
  8047. #endif /* MRV_BLS_BLS_V2_STOP */
  8048. /*****************************************************************************/
  8049. /**
  8050. * register: isp_bls_a_fixed: fixed black level A (0x00000028)
  8051. *
  8052. *****************************************************************************/
  8053. /* Slice: BLS_A_FIXED:*/
  8054. /* Fixed black level for A pixels – signed */
  8055. /* two's complement, value range from -4096 to +4095,*/
  8056. /* a positive value will be subtracted from the pixel values */
  8057. #ifdef MRV_BLS_BLS_A_FIXED
  8058. #endif /* MRV_BLS_BLS_A_FIXED */
  8059. /*****************************************************************************/
  8060. /**
  8061. * register: isp_bls_b_fixed: fixed black level B (0x0000002c)
  8062. *
  8063. *****************************************************************************/
  8064. /* Slice: BLS_B_FIXED:*/
  8065. /* Fixed black level for B pixels – signed */
  8066. /* two's complement, value range from -4096 to +4095 */
  8067. #ifdef MRV_BLS_BLS_B_FIXED
  8068. #endif /* MRV_BLS_BLS_B_FIXED */
  8069. /*****************************************************************************/
  8070. /**
  8071. * register: isp_bls_c_fixed: fixed black level C (0x00000030)
  8072. *
  8073. *****************************************************************************/
  8074. /* Slice: BLS_C_FIXED:*/
  8075. /* Fixed black level for C pixels – signed */
  8076. /* two's complement, value range from -4096 to +4095 */
  8077. #ifdef MRV_BLS_BLS_C_FIXED
  8078. #endif /* MRV_BLS_BLS_C_FIXED */
  8079. /*****************************************************************************/
  8080. /**
  8081. * register: isp_bls_d_fixed: fixed black level D (0x00000034)
  8082. *
  8083. *****************************************************************************/
  8084. /* Slice: BLS_D_FIXED:*/
  8085. /* Fixed black level for D pixels - signed */
  8086. /* two's complement, value range from -4096 to +4095 */
  8087. #ifdef MRV_BLS_BLS_D_FIXED
  8088. #endif /* MRV_BLS_BLS_D_FIXED */
  8089. /*****************************************************************************/
  8090. /**
  8091. * register: isp_bls_a_measured: measured black level A (0x00000038)
  8092. *
  8093. *****************************************************************************/
  8094. /* Slice: BLS_A_MEASURED:*/
  8095. /* Measured black level for A pixels */
  8096. #ifdef MRV_BLS_BLS_A_MEASURED
  8097. #endif /* MRV_BLS_BLS_A_MEASURED */
  8098. /*****************************************************************************/
  8099. /**
  8100. * register: isp_bls_b_measured: measured black level B (0x0000003c)
  8101. *
  8102. *****************************************************************************/
  8103. /* Slice: BLS_B_MEASURED:*/
  8104. /* Measured black level for B pixels */
  8105. #ifdef MRV_BLS_BLS_B_MEASURED
  8106. #endif /* MRV_BLS_BLS_B_MEASURED */
  8107. /*****************************************************************************/
  8108. /**
  8109. * register: isp_bls_c_measured: measured black level C (0x00000040)
  8110. *
  8111. *****************************************************************************/
  8112. /* Slice: BLS_C_MEASURED:*/
  8113. /* Measured black level for C pixels */
  8114. #ifdef MRV_BLS_BLS_C_MEASURED
  8115. #endif /* MRV_BLS_BLS_C_MEASURED */
  8116. /*****************************************************************************/
  8117. /**
  8118. * register: isp_bls_d_measured: measured black level D (0x00000044)
  8119. *
  8120. *****************************************************************************/
  8121. /* Slice: BLS_D_MEASURED:*/
  8122. /* Measured black level for D pixels */
  8123. #ifdef MRV_BLS_BLS_D_MEASURED
  8124. #endif /* MRV_BLS_BLS_D_MEASURED */
  8125. /*****************************************************************************/
  8126. /* ISP Denoising Pre-Filter Registers */
  8127. /*****************************************************************************/
  8128. /*****************************************************************************/
  8129. /**
  8130. * register: isp_dpf_mode: Mode control for Denoising Pre-Filter block
  8131. * (0x00000000)
  8132. *
  8133. *****************************************************************************/
  8134. /* Slice: USE_NF_GAIN:*/
  8135. /* 1: dpf_nf_gain's will be used */
  8136. /* 0: external AWB gains will be used *Default**/
  8137. #ifdef MRV_DPF_USE_NF_GAIN
  8138. #endif /* MRV_DPF_USE_NF_GAIN */
  8139. /* Slice: LSC_GAIN_COMP:*/
  8140. /* 1: LSC gain will be processed */
  8141. /* 0: LSC gain will not be processed *Default**/
  8142. #ifdef MRV_DPF_LSC_GAIN_COMP
  8143. #endif /* MRV_DPF_LSC_GAIN_COMP */
  8144. /* Slice: AWB_GAIN_COMP:*/
  8145. /* 1: AWB gain or internal dpf_nf_gain will be processed */
  8146. /* 0: AWB gain or internal dpf_nf_gain will not be processed *Default**/
  8147. #ifdef MRV_DPF_AWB_GAIN_COMP
  8148. #endif /* MRV_DPF_AWB_GAIN_COMP */
  8149. /* Slice: NLL_SEGMENTATION:*/
  8150. /* 1: optimized logarithmic like segmentation for Noise Level Lookup (NLL)*/
  8151. /* 0: equidistant segmentation for NLL *Default**/
  8152. #ifdef MRV_DPF_NLL_SEGMENTATION
  8153. #endif /* MRV_DPF_NLL_SEGMENTATION */
  8154. /* Slice: RB_FILTER_SIZE:*/
  8155. /* 1: Red and Blue filter kernel size of 9x9 (5x5 active) pixels */
  8156. /* 0: Wide Red and Blue filter kernel size of 13x9 (7x5 active) pixels *Default**/
  8157. #ifdef MRV_DPF_RB_FILTER_SIZE
  8158. #endif /* MRV_DPF_RB_FILTER_SIZE */
  8159. /* Slice: R_FILTER_OFF:*/
  8160. /* 1: disable filter processing for red pixels (R)*/
  8161. /* 0: filter R pixels *Default**/
  8162. #ifdef MRV_DPF_R_FILTER_OFF
  8163. #endif /* MRV_DPF_R_FILTER_OFF */
  8164. /* Slice: GR_FILTER_OFF:*/
  8165. /* 1: disable filter processing for green pixels in green/red lines (GR)*/
  8166. /* 0: filter GR pixels *Default**/
  8167. #ifdef MRV_DPF_GR_FILTER_OFF
  8168. #endif /* MRV_DPF_GR_FILTER_OFF */
  8169. /* Slice: GB_FILTER_OFF:*/
  8170. /* 1: disable filter processing for green pixels in green/blue lines (GB)*/
  8171. /* 0: filter GB pixels *Default**/
  8172. #ifdef MRV_DPF_GB_FILTER_OFF
  8173. #endif /* MRV_DPF_GB_FILTER_OFF */
  8174. /* Slice: B_FILTER_OFF:*/
  8175. /* 1: disable filter processing for blue pixels (B)*/
  8176. /* 0: filter B pixels *Default**/
  8177. #ifdef MRV_DPF_B_FILTER_OFF
  8178. #endif /* MRV_DPF_B_FILTER_OFF */
  8179. /* Slice: DPF_ENABLE:*/
  8180. /* 1: enable dpf */
  8181. /* 0: bypass dpf *Default**/
  8182. #ifdef MRV_DPF_DPF_ENABLE
  8183. #endif /* MRV_DPF_DPF_ENABLE */
  8184. /*****************************************************************************/
  8185. /**
  8186. * register: isp_dpf_strength_r: filter strength of the RED filter (0x00000004)
  8187. *
  8188. *****************************************************************************/
  8189. /* Slice: INV_WEIGHT_R:*/
  8190. /* Filter strength of the filter is determined by weight. Default is a */
  8191. /* weight of 1. A higher weight increases the filter strength. In this */
  8192. /* register the unsigned 8 bit value 64/weight is stored.*/
  8193. /**/
  8194. /* The following values show examples:*/
  8195. /* weight=0.251 -> 255, weight=0.5 -> 128,*/
  8196. /* weight=1 -> 64 *default**/
  8197. /* weight=1.25 -> 51, weight=1.5 -> 42,*/
  8198. /* weight=1.75 -> 37, weight=2 -> 32 */
  8199. #ifdef MRV_DPF_INV_WEIGHT_R
  8200. #endif /* MRV_DPF_INV_WEIGHT_R */
  8201. /*****************************************************************************/
  8202. /**
  8203. * register: isp_dpf_strength_g: filter strength of the GREEN filter (0x00000008)
  8204. *
  8205. *****************************************************************************/
  8206. /* Slice: INV_WEIGHT_G:*/
  8207. /* Filter strength of the filter is determined by weight. Default is a */
  8208. /* weight of 1. A higher weight increases the filter strength. In this */
  8209. /* register the unsigned 8 bit value 64/weight is stored.*/
  8210. /**/
  8211. /* The following values show examples:*/
  8212. /* weight=0.251 -> 255, weight=0.5 -> 128,*/
  8213. /* weight=1 -> 64 *default**/
  8214. /* weight=1.25 -> 51, weight=1.5 -> 42,*/
  8215. /* weight=1.75 -> 37, weight=2 -> 32 */
  8216. #ifdef MRV_DPF_INV_WEIGHT_G
  8217. #endif /* MRV_DPF_INV_WEIGHT_G */
  8218. /*****************************************************************************/
  8219. /**
  8220. * register: isp_dpf_strength_b: filter strength of the BLUE filter (0x0000000c)
  8221. *
  8222. *****************************************************************************/
  8223. /* Slice: INV_WEIGHT_B:*/
  8224. /* Filter strength of the filter is determined by weight. Default is a */
  8225. /* weight of 1. A higher weight increases the filter strength. In this */
  8226. /* register the unsigned 8 bit value 64/weight is stored.*/
  8227. /**/
  8228. /* The following values show examples:*/
  8229. /* weight=0.251 -> 255, weight=0.5 -> 128,*/
  8230. /* weight=1 -> 64 *default**/
  8231. /* weight=1.25 -> 51, weight=1.5 -> 42,*/
  8232. /* weight=1.75 -> 37, weight=2 -> 32 */
  8233. #ifdef MRV_DPF_INV_WEIGHT_B
  8234. #endif /* MRV_DPF_INV_WEIGHT_B */
  8235. /*****************************************************************************/
  8236. /**
  8237. * register: isp_dpf_s_weight_g_1_4: Spatial Weights green channel 1 2 3 4
  8238. * (0x00000010)
  8239. *
  8240. *****************************************************************************/
  8241. /* Slice: S_WEIGHT_G4:*/
  8242. /* Filter Coefficient green channel S_WEIGHT_G4 */
  8243. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8244. /* Default value is 16/16 (*Default*)*/
  8245. #ifdef MRV_DPF_S_WEIGHT_G4
  8246. #endif /* MRV_DPF_S_WEIGHT_G4 */
  8247. /* Slice: S_WEIGHT_G3:*/
  8248. /* Filter Coefficient green channel S_WEIGHT_G3 */
  8249. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8250. /* Default value is 16/16 (*Default*)*/
  8251. #ifdef MRV_DPF_S_WEIGHT_G3
  8252. #endif /* MRV_DPF_S_WEIGHT_G3 */
  8253. /* Slice: S_WEIGHT_G2:*/
  8254. /* Filter Coefficient green channel S_WEIGHT_G2 */
  8255. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8256. /* Default value is 16/16 (*Default*)*/
  8257. #ifdef MRV_DPF_S_WEIGHT_G2
  8258. #endif /* MRV_DPF_S_WEIGHT_G2 */
  8259. /* Slice: S_WEIGHT_G1:*/
  8260. /* Filter Coefficient green channel S_WEIGHT_G1 */
  8261. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8262. /* Default value is 16/16 (*Default*)*/
  8263. #ifdef MRV_DPF_S_WEIGHT_G1
  8264. #endif /* MRV_DPF_S_WEIGHT_G1 */
  8265. /*****************************************************************************/
  8266. /**
  8267. * register: isp_dpf_s_weight_g_5_6: Spatial Weights green channel 5 6
  8268. * (0x00000014)
  8269. *
  8270. *****************************************************************************/
  8271. /* Slice: S_WEIGHT_G6:*/
  8272. /* Filter Coefficient green channel S_WEIGHT_G6 */
  8273. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8274. /* Default value is 16/16 (*Default*)*/
  8275. #ifdef MRV_DPF_S_WEIGHT_G6
  8276. #endif /* MRV_DPF_S_WEIGHT_G6 */
  8277. /* Slice: S_WEIGHT_G5:*/
  8278. /* Filter Coefficient green channel S_WEIGHT_G5 */
  8279. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8280. /* Default value is 16/16 (*Default*)*/
  8281. #ifdef MRV_DPF_S_WEIGHT_G5
  8282. #endif /* MRV_DPF_S_WEIGHT_G5 */
  8283. /*****************************************************************************/
  8284. /**
  8285. * register: isp_dpf_s_weight_rb_1_4: Spatial Weights red/blue channels 1 2 3 4
  8286. * (0x00000018)
  8287. *
  8288. *****************************************************************************/
  8289. /* Slice: S_WEIGHT_RB4:*/
  8290. /* Filter Coefficient red/blue channels S_WEIGHT_RB4 */
  8291. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8292. /* Default value is 16/16 (*Default*)*/
  8293. #ifdef MRV_DPF_S_WEIGHT_RB4
  8294. #endif /* MRV_DPF_S_WEIGHT_RB4 */
  8295. /* Slice: S_WEIGHT_RB3:*/
  8296. /* Filter Coefficient red/blue channels S_WEIGHT_RB3 */
  8297. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8298. /* Default value is 16/16 (*Default*)*/
  8299. #ifdef MRV_DPF_S_WEIGHT_RB3
  8300. #endif /* MRV_DPF_S_WEIGHT_RB3 */
  8301. /* Slice: S_WEIGHT_RB2:*/
  8302. /* Filter Coefficient red/blue channels S_WEIGHT_RB2 */
  8303. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8304. /* Default value is 16/16 (*Default*)*/
  8305. #ifdef MRV_DPF_S_WEIGHT_RB2
  8306. #endif /* MRV_DPF_S_WEIGHT_RB2 */
  8307. /* Slice: S_WEIGHT_RB1:*/
  8308. /* Filter Coefficient red/blue channels S_WEIGHT_RB1 */
  8309. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8310. /* Default value is 16/16 (*Default*)*/
  8311. #ifdef MRV_DPF_S_WEIGHT_RB1
  8312. #endif /* MRV_DPF_S_WEIGHT_RB1 */
  8313. /*****************************************************************************/
  8314. /**
  8315. * register: isp_dpf_s_weight_rb_5_6: Spatial Weights red/blue channels 5 6
  8316. * (0x0000001c)
  8317. *
  8318. *****************************************************************************/
  8319. /* Slice: S_WEIGHT_RB6:*/
  8320. /* Filter Coefficient red/blue channels S_WEIGHT_RB6 */
  8321. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8322. /* Default value is 16/16 (*Default*)*/
  8323. #ifdef MRV_DPF_S_WEIGHT_RB6
  8324. #endif /* MRV_DPF_S_WEIGHT_RB6 */
  8325. /* Slice: S_WEIGHT_RB5:*/
  8326. /* Filter Coefficient red/blue channels S_WEIGHT_RB5 */
  8327. /* 5 bit unsigned, value range 1/16 to 16/16 */
  8328. /* Default value is 16/16 (*Default*)*/
  8329. #ifdef MRV_DPF_S_WEIGHT_RB5
  8330. #endif /* MRV_DPF_S_WEIGHT_RB5 */
  8331. /*****************************************************************************/
  8332. /**
  8333. * register array: isp_dpf_nll_coeff: Noise Level Lookup Coefficient
  8334. * (0x0040 + n*0x4 (n=0..16))
  8335. *
  8336. *****************************************************************************/
  8337. /* Slice: nll_coeff_n:*/
  8338. /* Noise Level Lookup Table Coefficient nll_coeff_n */
  8339. /* 10 bit unsigned, value range 1/1024 to 1023/1024 (*Default*)*/
  8340. #ifdef MRV_DPF_NLL_COEFF_N
  8341. #endif /* MRV_DPF_NLL_COEFF_N */
  8342. /*****************************************************************************/
  8343. /**
  8344. * register: isp_dpf_nf_gain_r: noise function gain for red pixels (0x00000064)
  8345. *
  8346. *****************************************************************************/
  8347. /* Slice: DPF_NF_GAIN_R:*/
  8348. /* Noise Function (NF) Gain that replaces the AWB gain for red pixels.*/
  8349. /* 12 bit unsigned integer format: gain=1 -> 0x100 */
  8350. #ifdef MRV_DPF_DPF_NF_GAIN_R
  8351. #endif /* MRV_DPF_DPF_NF_GAIN_R */
  8352. /*****************************************************************************/
  8353. /**
  8354. * register: isp_dpf_nf_gain_gr: noise function gain for green in red pixels
  8355. * (0x00000068)
  8356. *
  8357. *****************************************************************************/
  8358. /* Slice: DPF_NF_GAIN_GR:*/
  8359. /* Noise Function (NF) Gain that replaces the AWB gain for green pixels in a */
  8360. /* red line.*/
  8361. /* 12 bit unsigned integer format: gain=1 -> 0x100 */
  8362. #ifdef MRV_DPF_DPF_NF_GAIN_GR
  8363. #endif /* MRV_DPF_DPF_NF_GAIN_GR */
  8364. /*****************************************************************************/
  8365. /**
  8366. * register: isp_dpf_nf_gain_gb: noise function gain for green in blue pixels
  8367. * (0x0000006c)
  8368. *
  8369. *****************************************************************************/
  8370. /* Slice: DPF_NF_GAIN_GB:*/
  8371. /* Noise Function (NF) Gain that replaces the AWB gain for green pixels in a */
  8372. /* blue line.*/
  8373. /* 12 bit unsigned integer format: gain=1 -> 0x100 */
  8374. #ifdef MRV_DPF_DPF_NF_GAIN_GB
  8375. #endif /* MRV_DPF_DPF_NF_GAIN_GB */
  8376. /*****************************************************************************/
  8377. /**
  8378. * register: isp_dpf_nf_gain_b: noise function gain for blue pixels (0x00000070)
  8379. *
  8380. *****************************************************************************/
  8381. /* Slice: DPF_NF_GAIN_B:*/
  8382. /* Noise Function (NF) Gain that replaces the AWB gain for blue pixels.*/
  8383. /* 12 bit unsigned integer format: gain=1 -> 0x100 */
  8384. #ifdef MRV_DPF_DPF_NF_GAIN_B
  8385. #endif /* MRV_DPF_DPF_NF_GAIN_B */
  8386. /*****************************************************************************/
  8387. /* ISP Defect Pixel Cluster Correction Registers */
  8388. /*****************************************************************************/
  8389. /*****************************************************************************/
  8390. /**
  8391. * register: isp_dpcc_mode: mode control for DPCC block (0x0000)
  8392. *
  8393. *****************************************************************************/
  8394. /* Slice: STAGE1_ENABLE:*/
  8395. /* 1: enable stage1 *Default**/
  8396. /* 0: bypass stage1 */
  8397. #ifdef MRV_DPCC_STAGE1_ENABLE
  8398. #endif /* MRV_DPCC_STAGE1_ENABLE */
  8399. /* Slice: GRAYSCALE_MODE:*/
  8400. /* 1: enable gray scale data input from black and white sensors (without color filter array)*/
  8401. /* 0: BAYER DATA INPUT *Default**/
  8402. #ifdef MRV_DPCC_GRAYSCALE_MODE
  8403. #endif /* MRV_DPCC_GRAYSCALE_MODE */
  8404. /* Slice: ISP_DPCC_enable:*/
  8405. /* 1: enable DPCC */
  8406. /* 0: bypass DPCC *Default**/
  8407. #ifdef MRV_DPCC_ISP_DPCC_ENABLE
  8408. #endif /* MRV_DPCC_ISP_DPCC_ENABLE */
  8409. /*****************************************************************************/
  8410. /**
  8411. * register: isp_dpcc_output_mode: interpolation mode for correction unit
  8412. * (0x00000004)
  8413. *
  8414. *****************************************************************************/
  8415. /* Slice: STAGE1_RB_3x3:*/
  8416. /* 1: stage1 red/blue 9 pixel (3x3) output median */
  8417. /* 0: stage1 red/blue 4 or 5 pixel output median *Default**/
  8418. #ifdef MRV_DPCC_STAGE1_RB_3X3
  8419. #endif /* MRV_DPCC_STAGE1_RB_3X3 */
  8420. /* Slice: STAGE1_G_3x3:*/
  8421. /* 1: stage1 green 9 pixel (3x3) output median */
  8422. /* 0: stage1 green 4 or 5 pixel output median *Default**/
  8423. #ifdef MRV_DPCC_STAGE1_G_3X3
  8424. #endif /* MRV_DPCC_STAGE1_G_3X3 */
  8425. /* Slice: STAGE1_INCL_RB_CENTER:*/
  8426. /* 1: stage1 include center pixel for red/blue output median 2x2+1 */
  8427. /* *Default* 0: stage1 do not include center pixel for red/blue output median 2x2 */
  8428. #ifdef MRV_DPCC_STAGE1_INCL_RB_CENTER
  8429. #endif /* MRV_DPCC_STAGE1_INCL_RB_CENTER */
  8430. /* Slice: STAGE1_INCL_GREEN_CENTER:*/
  8431. /* 1: stage1 include center pixel for green output median 2x2+1 *Default**/
  8432. /* 0: stage1 do not include center pixel for green output median 2x2 */
  8433. #ifdef MRV_DPCC_STAGE1_INCL_GREEN_CENTER
  8434. #endif /* MRV_DPCC_STAGE1_INCL_GREEN_CENTER */
  8435. /*****************************************************************************/
  8436. /**
  8437. * register: isp_dpcc_set_use: DPCC methods set usage for detection
  8438. * (0x00000008)
  8439. *
  8440. *****************************************************************************/
  8441. /* Slice: STAGE1_USE_FIX_SET:*/
  8442. /* 1: stage1 use hard coded methods set *Default**/
  8443. /* 0: stage1 do not use hard coded methods set */
  8444. #ifdef MRV_DPCC_STAGE1_USE_FIX_SET
  8445. #endif /* MRV_DPCC_STAGE1_USE_FIX_SET */
  8446. /* Slice: STAGE1_USE_SET_3:*/
  8447. /* 1: stage1 use methods set 3 */
  8448. /* 0: stage1 do not use methods set 3 *Default**/
  8449. #ifdef MRV_DPCC_STAGE1_USE_SET_3
  8450. #endif /* MRV_DPCC_STAGE1_USE_SET_3 */
  8451. /* Slice: STAGE1_USE_SET_2:*/
  8452. /* 1: stage1 use methods set 2 */
  8453. /* 0: stage1 do not use methods set 2 *Default**/
  8454. #ifdef MRV_DPCC_STAGE1_USE_SET_2
  8455. #endif /* MRV_DPCC_STAGE1_USE_SET_2 */
  8456. /* Slice: STAGE1_USE_SET_1:*/
  8457. /* 1: stage1 use methods set 1 *Default**/
  8458. /* 0: stage1 do not use methods set 1 */
  8459. #ifdef MRV_DPCC_STAGE1_USE_SET_1
  8460. #endif /* MRV_DPCC_STAGE1_USE_SET_1 */
  8461. /*****************************************************************************/
  8462. /**
  8463. * register: isp_dpcc_methods_set_1: Methods enable bits for SET_1
  8464. * (0x0000000c)
  8465. *
  8466. *****************************************************************************/
  8467. /* Slice: RG_RED_BLUE1_ENABLE:*/
  8468. /* 1: enable Rank Gradient check for red_blue *Default**/
  8469. /* 0: bypass Rank Gradient check for red_blue */
  8470. #ifdef MRV_DPCC_RG_RED_BLUE1_ENABLE
  8471. #endif /* MRV_DPCC_RG_RED_BLUE1_ENABLE */
  8472. /* Slice: RND_RED_BLUE1_ENABLE:*/
  8473. /* 1: enable Rank Neighbor Difference check for red_blue *Default**/
  8474. /* 0: bypass Rank Neighbor Difference check for red_blue */
  8475. #ifdef MRV_DPCC_RND_RED_BLUE1_ENABLE
  8476. #endif /* MRV_DPCC_RND_RED_BLUE1_ENABLE */
  8477. /* Slice: RO_RED_BLUE1_ENABLE:*/
  8478. /* 1: enable Rank Order check for red_blue *Default**/
  8479. /* 0: bypass Rank Order check for red_blue */
  8480. #ifdef MRV_DPCC_RO_RED_BLUE1_ENABLE
  8481. #endif /* MRV_DPCC_RO_RED_BLUE1_ENABLE */
  8482. /* Slice: LC_RED_BLUE1_ENABLE:*/
  8483. /* 1: enable Line check for red_blue *Default**/
  8484. /* 0: bypass Line check for red_blue */
  8485. #ifdef MRV_DPCC_LC_RED_BLUE1_ENABLE
  8486. #endif /* MRV_DPCC_LC_RED_BLUE1_ENABLE */
  8487. /* Slice: PG_RED_BLUE1_ENABLE:*/
  8488. /* 1: enable Peak Gradient check for red_blue *Default**/
  8489. /* 0: bypass Peak Gradient check for red_blue */
  8490. #ifdef MRV_DPCC_PG_RED_BLUE1_ENABLE
  8491. #endif /* MRV_DPCC_PG_RED_BLUE1_ENABLE */
  8492. /* Slice: RG_GREEN1_ENABLE:*/
  8493. /* 1: enable Rank Gradient check for green *Default**/
  8494. /* 0: bypass Rank Gradient check for green */
  8495. #ifdef MRV_DPCC_RG_GREEN1_ENABLE
  8496. #endif /* MRV_DPCC_RG_GREEN1_ENABLE */
  8497. /* Slice: RND_GREEN1_ENABLE:*/
  8498. /* 1: enable Rank Neighbor Difference check for green *Default**/
  8499. /* 0: bypass Rank Neighbor Difference check for green */
  8500. #ifdef MRV_DPCC_RND_GREEN1_ENABLE
  8501. #endif /* MRV_DPCC_RND_GREEN1_ENABLE */
  8502. /* Slice: RO_GREEN1_ENABLE:*/
  8503. /* 1: enable Rank Order check for green *Default**/
  8504. /* 0: bypass Rank Order check for green */
  8505. #ifdef MRV_DPCC_RO_GREEN1_ENABLE
  8506. #endif /* MRV_DPCC_RO_GREEN1_ENABLE */
  8507. /* Slice: LC_GREEN1_ENABLE:*/
  8508. /* 1: enable Line check for green *Default**/
  8509. /* 0: bypass Line check for green */
  8510. #ifdef MRV_DPCC_LC_GREEN1_ENABLE
  8511. #endif /* MRV_DPCC_LC_GREEN1_ENABLE */
  8512. /* Slice: PG_GREEN1_ENABLE:*/
  8513. /* 1: enable Peak Gradient check for green *Default**/
  8514. /* 0: bypass Peak Gradient check for green */
  8515. #ifdef MRV_DPCC_PG_GREEN1_ENABLE
  8516. #endif /* MRV_DPCC_PG_GREEN1_ENABLE */
  8517. /*****************************************************************************/
  8518. /**
  8519. * register: isp_dpcc_methods_set_2: Methods enable bits for SET_2
  8520. * (0x00000010)
  8521. *
  8522. *****************************************************************************/
  8523. /* Slice: RG_RED_BLUE2_ENABLE:*/
  8524. /* 1: enable Rank Gradient check for red_blue *Default**/
  8525. /* 0: bypass Rank Gradient check for red_blue */
  8526. #ifdef MRV_DPCC_RG_RED_BLUE2_ENABLE
  8527. #endif /* MRV_DPCC_RG_RED_BLUE2_ENABLE */
  8528. /* Slice: RND_RED_BLUE2_ENABLE:*/
  8529. /* 1: enable Rank Neighbor Difference check for red_blue *Default**/
  8530. /* 0: bypass Rank Neighbor Difference check for red_blue */
  8531. #ifdef MRV_DPCC_RND_RED_BLUE2_ENABLE
  8532. #endif /* MRV_DPCC_RND_RED_BLUE2_ENABLE */
  8533. /* Slice: RO_RED_BLUE2_ENABLE:*/
  8534. /* 1: enable Rank Order check for red_blue *Default**/
  8535. /* 0: bypass Rank Order check for red_blue */
  8536. #ifdef MRV_DPCC_RO_RED_BLUE2_ENABLE
  8537. #endif /* MRV_DPCC_RO_RED_BLUE2_ENABLE */
  8538. /* Slice: LC_RED_BLUE2_ENABLE:*/
  8539. /* 1: enable Line check for red_blue *Default**/
  8540. /* 0: bypass Line check for red_blue */
  8541. #ifdef MRV_DPCC_LC_RED_BLUE2_ENABLE
  8542. #endif /* MRV_DPCC_LC_RED_BLUE2_ENABLE */
  8543. /* Slice: PG_RED_BLUE2_ENABLE:*/
  8544. /* 1: enable Peak Gradient check for red_blue *Default**/
  8545. /* 0: bypass Peak Gradient check for red_blue */
  8546. #ifdef MRV_DPCC_PG_RED_BLUE2_ENABLE
  8547. #endif /* MRV_DPCC_PG_RED_BLUE2_ENABLE */
  8548. /* Slice: RG_GREEN2_ENABLE:*/
  8549. /* 1: enable Rank Gradient check for green *Default**/
  8550. /* 0: bypass Rank Gradient check for green */
  8551. #ifdef MRV_DPCC_RG_GREEN2_ENABLE
  8552. #endif /* MRV_DPCC_RG_GREEN2_ENABLE */
  8553. /* Slice: RND_GREEN2_ENABLE:*/
  8554. /* 1: enable Rank Neighbor Difference check for green *Default**/
  8555. /* 0: bypass Rank Neighbor Difference check for green */
  8556. #ifdef MRV_DPCC_RND_GREEN2_ENABLE
  8557. #endif /* MRV_DPCC_RND_GREEN2_ENABLE */
  8558. /* Slice: RO_GREEN2_ENABLE:*/
  8559. /* 1: enable Rank Order check for green *Default**/
  8560. /* 0: bypass Rank Order check for green */
  8561. #ifdef MRV_DPCC_RO_GREEN2_ENABLE
  8562. #endif /* MRV_DPCC_RO_GREEN2_ENABLE */
  8563. /* Slice: LC_GREEN2_ENABLE:*/
  8564. /* 1: enable Line check for green *Default**/
  8565. /* 0: bypass Line check for green */
  8566. #ifdef MRV_DPCC_LC_GREEN2_ENABLE
  8567. #endif /* MRV_DPCC_LC_GREEN2_ENABLE */
  8568. /* Slice: PG_GREEN2_ENABLE:*/
  8569. /* 1: enable Peak Gradient check for green *Default**/
  8570. /* 0: bypass Peak Gradient check for green */
  8571. #ifdef MRV_DPCC_PG_GREEN2_ENABLE
  8572. #endif /* MRV_DPCC_PG_GREEN2_ENABLE */
  8573. /*****************************************************************************/
  8574. /**
  8575. * register: isp_dpcc_methods_set_3: Methods enable bits for SET_3
  8576. * (0x00000014)
  8577. *
  8578. *****************************************************************************/
  8579. /* Slice: RG_RED_BLUE3_ENABLE:*/
  8580. /* 1: enable Rank Gradient check for red_blue *Default**/
  8581. /* 0: bypass Rank Gradient check for red_blue */
  8582. #ifdef MRV_DPCC_RG_RED_BLUE3_ENABLE
  8583. #endif /* MRV_DPCC_RG_RED_BLUE3_ENABLE */
  8584. /* Slice: RND_RED_BLUE3_ENABLE:*/
  8585. /* 1: enable Rank Neighbor Difference check for red_blue *Default**/
  8586. /* 0: bypass Rank Neighbor Difference check for red_blue */
  8587. #ifdef MRV_DPCC_RND_RED_BLUE3_ENABLE
  8588. #endif /* MRV_DPCC_RND_RED_BLUE3_ENABLE */
  8589. /* Slice: RO_RED_BLUE3_ENABLE:*/
  8590. /* 1: enable Rank Order check for red_blue *Default**/
  8591. /* 0: bypass Rank Order check for red_blue */
  8592. #ifdef MRV_DPCC_RO_RED_BLUE3_ENABLE
  8593. #endif /* MRV_DPCC_RO_RED_BLUE3_ENABLE */
  8594. /* Slice: LC_RED_BLUE3_ENABLE:*/
  8595. /* 1: enable Line check for red_blue *Default**/
  8596. /* 0: bypass Line check for red_blue */
  8597. #ifdef MRV_DPCC_LC_RED_BLUE3_ENABLE
  8598. #endif /* MRV_DPCC_LC_RED_BLUE3_ENABLE */
  8599. /* Slice: PG_RED_BLUE3_ENABLE:*/
  8600. /* 1: enable Peak Gradient check for red_blue *Default**/
  8601. /* 0: bypass Peak Gradient check for red_blue */
  8602. #ifdef MRV_DPCC_PG_RED_BLUE3_ENABLE
  8603. #endif /* MRV_DPCC_PG_RED_BLUE3_ENABLE */
  8604. /* Slice: RG_GREEN3_ENABLE:*/
  8605. /* 1: enable Rank Gradient check for green *Default**/
  8606. /* 0: bypass Rank Gradient check for green */
  8607. #ifdef MRV_DPCC_RG_GREEN3_ENABLE
  8608. #endif /* MRV_DPCC_RG_GREEN3_ENABLE */
  8609. /* Slice: RND_GREEN3_ENABLE:*/
  8610. /* 1: enable Rank Neighbor Difference check for green *Default**/
  8611. /* 0: bypass Rank Neighbor Difference check for green */
  8612. #ifdef MRV_DPCC_RND_GREEN3_ENABLE
  8613. #endif /* MRV_DPCC_RND_GREEN3_ENABLE */
  8614. /* Slice: RO_GREEN3_ENABLE:*/
  8615. /* 1: enable Rank Order check for green *Default**/
  8616. /* 0: bypass Rank Order check for green */
  8617. #ifdef MRV_DPCC_RO_GREEN3_ENABLE
  8618. #endif /* MRV_DPCC_RO_GREEN3_ENABLE */
  8619. /* Slice: LC_GREEN3_ENABLE:*/
  8620. /* 1: enable Line check for green *Default**/
  8621. /* 0: bypass Line check for green */
  8622. #ifdef MRV_DPCC_LC_GREEN3_ENABLE
  8623. #endif /* MRV_DPCC_LC_GREEN3_ENABLE */
  8624. /* Slice: PG_GREEN3_ENABLE:*/
  8625. /* 1: enable Peak Gradient check for green *Default**/
  8626. /* 0: bypass Peak Gradient check for green */
  8627. #ifdef MRV_DPCC_PG_GREEN3_ENABLE
  8628. #endif /* MRV_DPCC_PG_GREEN3_ENABLE */
  8629. /*****************************************************************************/
  8630. /**
  8631. * register: isp_dpcc_line_thresh_1: Line threshold SET_1 (0x00000018)
  8632. *
  8633. *****************************************************************************/
  8634. /* Slice: LINE_THR_1_RB:*/
  8635. /* line threshold for set 1 red/blue */
  8636. #ifdef MRV_DPCC_LINE_THR_1_RB
  8637. #endif /* MRV_DPCC_LINE_THR_1_RB */
  8638. /* Slice: LINE_THR_1_G:*/
  8639. /* line threshold for set 1 green */
  8640. #ifdef MRV_DPCC_LINE_THR_1_G
  8641. #endif /* MRV_DPCC_LINE_THR_1_G */
  8642. /*****************************************************************************/
  8643. /**
  8644. * register: isp_dpcc_line_mad_fac_1: Mean Absolute Difference (MAD) factor
  8645. * for Line check set 1 (0x0000001c)
  8646. *
  8647. *****************************************************************************/
  8648. /* Slice: LINE_MAD_FAC_1_RB:*/
  8649. /* line MAD factor for set 1 red/blue */
  8650. #ifdef MRV_DPCC_LINE_MAD_FAC_1_RB
  8651. #endif /* MRV_DPCC_LINE_MAD_FAC_1_RB */
  8652. /* Slice: LINE_MAD_FAC_1_G:*/
  8653. /* line MAD factor for set 1 green */
  8654. #ifdef MRV_DPCC_LINE_MAD_FAC_1_G
  8655. #endif /* MRV_DPCC_LINE_MAD_FAC_1_G */
  8656. /*****************************************************************************/
  8657. /**
  8658. * register: isp_dpcc_pg_fac_1: Peak gradient factor for set 1 (0x00000020)
  8659. *
  8660. *****************************************************************************/
  8661. /* Slice: PG_FAC_1_RB:*/
  8662. /* Peak gradient factor for set 1 red/blue */
  8663. #ifdef MRV_DPCC_PG_FAC_1_RB
  8664. #endif /* MRV_DPCC_PG_FAC_1_RB */
  8665. /* Slice: PG_FAC_1_G:*/
  8666. /* Peak gradient factor for set 1 green */
  8667. #ifdef MRV_DPCC_PG_FAC_1_G
  8668. #endif /* MRV_DPCC_PG_FAC_1_G */
  8669. /*****************************************************************************/
  8670. /**
  8671. * register: isp_dpcc_rnd_thresh_1: Rank Neighbor Difference threshold for
  8672. * set 1 (0x00000024)
  8673. *
  8674. *****************************************************************************/
  8675. /* Slice: RND_THR_1_RB:*/
  8676. /* Rank Neighbor Difference threshold for set 1 red/blue */
  8677. #ifdef MRV_DPCC_RND_THR_1_RB
  8678. #endif /* MRV_DPCC_RND_THR_1_RB */
  8679. /* Slice: RND_THR_1_G:*/
  8680. /* Rank Neighbor Difference threshold for set 1 green */
  8681. #ifdef MRV_DPCC_RND_THR_1_G
  8682. #endif /* MRV_DPCC_RND_THR_1_G */
  8683. /*****************************************************************************/
  8684. /**
  8685. * register: isp_dpcc_rg_fac_1: Rank gradient factor for set 1 (0x00000028)
  8686. *
  8687. *****************************************************************************/
  8688. /* Slice: RG_FAC_1_RB:*/
  8689. /* Rank gradient factor for set 1 red/blue */
  8690. #ifdef MRV_DPCC_RG_FAC_1_RB
  8691. #endif /* MRV_DPCC_RG_FAC_1_RB */
  8692. /* Slice: RG_FAC_1_G:*/
  8693. /* Rank gradient factor for set 1 green */
  8694. #ifdef MRV_DPCC_RG_FAC_1_G
  8695. #endif /* MRV_DPCC_RG_FAC_1_G */
  8696. /*****************************************************************************/
  8697. /**
  8698. * register: isp_dpcc_line_thresh_2: Line threshold SET_2 (0x0000002C)
  8699. *
  8700. *****************************************************************************/
  8701. /* Slice: LINE_THR_2_RB:*/
  8702. /* line threshold for set 1 red/blue */
  8703. #ifdef MRV_DPCC_LINE_THR_2_RB
  8704. #endif /* MRV_DPCC_LINE_THR_2_RB */
  8705. /* Slice: LINE_THR_2_G:*/
  8706. /* line threshold for set 1 green */
  8707. #ifdef MRV_DPCC_LINE_THR_2_G
  8708. #endif /* MRV_DPCC_LINE_THR_2_G */
  8709. /*****************************************************************************/
  8710. /**
  8711. * register: isp_dpcc_line_mad_fac_2: Mean Absolute Difference (MAD) factor
  8712. * for Line check set 1 (0x00000030)
  8713. *
  8714. *****************************************************************************/
  8715. /* Slice: LINE_MAD_FAC_2_RB:*/
  8716. /* line MAD factor for set 1 red/blue */
  8717. #ifdef MRV_DPCC_LINE_MAD_FAC_2_RB
  8718. #endif /* MRV_DPCC_LINE_MAD_FAC_2_RB */
  8719. /* Slice: LINE_MAD_FAC_2_G:*/
  8720. /* line MAD factor for set 1 green */
  8721. #ifdef MRV_DPCC_LINE_MAD_FAC_2_G
  8722. #endif /* MRV_DPCC_LINE_MAD_FAC_2_G */
  8723. /*****************************************************************************/
  8724. /**
  8725. * register: isp_dpcc_pg_fac_2: Peak gradient factor for set 1 (0x00000034)
  8726. *
  8727. *****************************************************************************/
  8728. /* Slice: PG_FAC_2_RB:*/
  8729. /* Peak gradient factor for set 1 red/blue */
  8730. #ifdef MRV_DPCC_PG_FAC_2_RB
  8731. #endif /* MRV_DPCC_PG_FAC_2_RB */
  8732. /* Slice: PG_FAC_2_G:*/
  8733. /* Peak gradient factor for set 1 green */
  8734. #ifdef MRV_DPCC_PG_FAC_2_G
  8735. #endif /* MRV_DPCC_PG_FAC_2_G */
  8736. /*****************************************************************************/
  8737. /**
  8738. * register: isp_dpcc_rnd_thresh_2: Rank Neighbor Difference threshold for
  8739. * set 1 (0x00000038)
  8740. *
  8741. *****************************************************************************/
  8742. /* Slice: RND_THR_2_RB:*/
  8743. /* Rank Neighbor Difference threshold for set 1 red/blue */
  8744. #ifdef MRV_DPCC_RND_THR_2_RB
  8745. #endif /* MRV_DPCC_RND_THR_2_RB */
  8746. /* Slice: RND_THR_2_G:*/
  8747. /* Rank Neighbor Difference threshold for set 1 green */
  8748. #ifdef MRV_DPCC_RND_THR_2_G
  8749. #endif /* MRV_DPCC_RND_THR_2_G */
  8750. /*****************************************************************************/
  8751. /**
  8752. * register: isp_dpcc_rg_fac_2: Rank gradient factor for set 1 (0x0000003C)
  8753. *
  8754. *****************************************************************************/
  8755. /* Slice: RG_FAC_2_RB:*/
  8756. /* Rank gradient factor for set 1 red/blue */
  8757. #ifdef MRV_DPCC_RG_FAC_2_RB
  8758. #endif /* MRV_DPCC_RG_FAC_2_RB */
  8759. /* Slice: RG_FAC_2_G:*/
  8760. /* Rank gradient factor for set 1 green */
  8761. #ifdef MRV_DPCC_RG_FAC_2_G
  8762. #endif /* MRV_DPCC_RG_FAC_2_G */
  8763. /*****************************************************************************/
  8764. /**
  8765. * register: isp_dpcc_line_thresh_3: Line threshold SET_3 (0x00000040)
  8766. *
  8767. *****************************************************************************/
  8768. /* Slice: LINE_THR_3_RB:*/
  8769. /* line threshold for set 1 red/blue */
  8770. #ifdef MRV_DPCC_LINE_THR_3_RB
  8771. #endif /* MRV_DPCC_LINE_THR_3_RB */
  8772. /* Slice: LINE_THR_3_G:*/
  8773. /* line threshold for set 1 green */
  8774. #ifdef MRV_DPCC_LINE_THR_3_G
  8775. #endif /* MRV_DPCC_LINE_THR_3_G */
  8776. /*****************************************************************************/
  8777. /**
  8778. * register: isp_dpcc_line_mad_fac_3: Mean Absolute Difference (MAD) factor
  8779. * for Line check set 1 (0x00000044)
  8780. *
  8781. *****************************************************************************/
  8782. /* Slice: LINE_MAD_FAC_3_RB:*/
  8783. /* line MAD factor for set 1 red/blue */
  8784. #ifdef MRV_DPCC_LINE_MAD_FAC_3_RB
  8785. #endif /* MRV_DPCC_LINE_MAD_FAC_3_RB */
  8786. /* Slice: LINE_MAD_FAC_3_G:*/
  8787. /* line MAD factor for set 1 green */
  8788. #ifdef MRV_DPCC_LINE_MAD_FAC_3_G
  8789. #endif /* MRV_DPCC_LINE_MAD_FAC_3_G */
  8790. /*****************************************************************************/
  8791. /**
  8792. * register: isp_dpcc_pg_fac_3: Peak gradient factor for set 1 (0x00000048)
  8793. *
  8794. *****************************************************************************/
  8795. /* Slice: PG_FAC_3_RB:*/
  8796. /* Peak gradient factor for set 1 red/blue */
  8797. #ifdef MRV_DPCC_PG_FAC_3_RB
  8798. #endif /* MRV_DPCC_PG_FAC_3_RB */
  8799. /* Slice: PG_FAC_3_G:*/
  8800. /* Peak gradient factor for set 1 green */
  8801. #ifdef MRV_DPCC_PG_FAC_3_G
  8802. #endif /* MRV_DPCC_PG_FAC_3_G */
  8803. /*****************************************************************************/
  8804. /**
  8805. * register: isp_dpcc_rnd_thresh_3: Rank Neighbor Difference threshold for
  8806. * set 1 (0x0000004C)
  8807. *
  8808. *****************************************************************************/
  8809. /* Slice: RND_THR_3_RB:*/
  8810. /* Rank Neighbor Difference threshold for set 1 red/blue */
  8811. #ifdef MRV_DPCC_RND_THR_3_RB
  8812. #endif /* MRV_DPCC_RND_THR_3_RB */
  8813. /* Slice: RND_THR_3_G:*/
  8814. /* Rank Neighbor Difference threshold for set 1 green */
  8815. #ifdef MRV_DPCC_RND_THR_3_G
  8816. #endif /* MRV_DPCC_RND_THR_3_G */
  8817. /*****************************************************************************/
  8818. /**
  8819. * register: isp_dpcc_rg_fac_3: Rank gradient factor for set 1 (0x00000050)
  8820. *
  8821. *****************************************************************************/
  8822. /* Slice: RG_FAC_3_RB:*/
  8823. /* Rank gradient factor for set 1 red/blue */
  8824. #ifdef MRV_DPCC_RG_FAC_3_RB
  8825. #endif /* MRV_DPCC_RG_FAC_3_RB */
  8826. /* Slice: RG_FAC_3_G:*/
  8827. /* Rank gradient factor for set 1 green */
  8828. #ifdef MRV_DPCC_RG_FAC_3_G
  8829. #endif /* MRV_DPCC_RG_FAC_3_G */
  8830. /*****************************************************************************/
  8831. /**
  8832. * register: isp_dpcc_ro_limits: Rank Order Limits (0x00000054)
  8833. *
  8834. *****************************************************************************/
  8835. /* Slice: RO_LIM_3_RB:*/
  8836. /* Rank order limit for set 3 red/blue */
  8837. #ifdef MRV_DPCC_RO_LIM_3_RB
  8838. #endif /* MRV_DPCC_RO_LIM_3_RB */
  8839. /* Slice: RO_LIM_3_G:*/
  8840. /* Rank order limit for set 3 green */
  8841. #ifdef MRV_DPCC_RO_LIM_3_G
  8842. #endif /* MRV_DPCC_RO_LIM_3_G */
  8843. /* Slice: RO_LIM_2_RB:*/
  8844. /* Rank order limit for set 2 red/blue */
  8845. #ifdef MRV_DPCC_RO_LIM_2_RB
  8846. #endif /* MRV_DPCC_RO_LIM_2_RB */
  8847. /* Slice: RO_LIM_2_G:*/
  8848. /* Rank order limit for set 2 green */
  8849. #ifdef MRV_DPCC_RO_LIM_2_G
  8850. #endif /* MRV_DPCC_RO_LIM_2_G */
  8851. /* Slice: RO_LIM_1_RB:*/
  8852. /* Rank order limit for set 1 red/blue */
  8853. #ifdef MRV_DPCC_RO_LIM_1_RB
  8854. #endif /* MRV_DPCC_RO_LIM_1_RB */
  8855. /* Slice: RO_LIM_1_G:*/
  8856. /* Rank order limit for set 1 green */
  8857. #ifdef MRV_DPCC_RO_LIM_1_G
  8858. #endif /* MRV_DPCC_RO_LIM_1_G */
  8859. /*****************************************************************************/
  8860. /**
  8861. * register: isp_dpcc_rnd_offs: Differential Rank Offsets for Rank Neighbor
  8862. * Difference (0x00000058)
  8863. *
  8864. *****************************************************************************/
  8865. /* Slice: RND_OFFS_3_RB:*/
  8866. /* Rank Offset to Neighbor for set 3 red/blue */
  8867. #ifdef MRV_DPCC_RND_OFFS_3_RB
  8868. #endif /* MRV_DPCC_RND_OFFS_3_RB */
  8869. /* Slice: RND_OFFS_3_G:*/
  8870. /* Rank Offset to Neighbor for set 3 green */
  8871. #ifdef MRV_DPCC_RND_OFFS_3_G
  8872. #endif /* MRV_DPCC_RND_OFFS_3_G */
  8873. /* Slice: RND_OFFS_2_RB:*/
  8874. /* Rank Offset to Neighbor for set 2 red/blue */
  8875. #ifdef MRV_DPCC_RND_OFFS_2_RB
  8876. #endif /* MRV_DPCC_RND_OFFS_2_RB */
  8877. /* Slice: RND_OFFS_2_G:*/
  8878. /* Rank Offset to Neighbor for set 2 green */
  8879. #ifdef MRV_DPCC_RND_OFFS_2_G
  8880. #endif /* MRV_DPCC_RND_OFFS_2_G */
  8881. /* Slice: RND_OFFS_1_RB:*/
  8882. /* Rank Offset to Neighbor for set 1 red/blue */
  8883. #ifdef MRV_DPCC_RND_OFFS_1_RB
  8884. #endif /* MRV_DPCC_RND_OFFS_1_RB */
  8885. /* Slice: RND_OFFS_1_G:*/
  8886. /* Rank Offset to Neighbor for set 1 green */
  8887. #ifdef MRV_DPCC_RND_OFFS_1_G
  8888. #endif /* MRV_DPCC_RND_OFFS_1_G */
  8889. /*****************************************************************************/
  8890. /**
  8891. * register: isp_dpcc_bpt_ctrl: bad pixel table settings (0x0000005c)
  8892. *
  8893. *****************************************************************************/
  8894. /* Slice: BPT_RB_3x3:*/
  8895. /* 1: if BPT active red/blue 9 pixel (3x3) output median */
  8896. /* 0: if BPT active red/blue 4 or 5 pixel output median *Default**/
  8897. #ifdef MRV_DPCC_BPT_RB_3X3
  8898. #endif /* MRV_DPCC_BPT_RB_3X3 */
  8899. /* Slice: BPT_G_3x3:*/
  8900. /* 1: if BPT active green 9 pixel (3x3) output median */
  8901. /* 0: if BPT active green 4 or 5 pixel output median *Default**/
  8902. #ifdef MRV_DPCC_BPT_G_3X3
  8903. #endif /* MRV_DPCC_BPT_G_3X3 */
  8904. /* Slice: BPT_INCL_RB_CENTER:*/
  8905. /* 1: if BPT active include center pixel for red/blue output median 2x2+1 */
  8906. /* 0: if BPT active do not include center pixel for red/blue output median 2x2 *Default**/
  8907. #ifdef MRV_DPCC_BPT_INCL_RB_CENTER
  8908. #endif /* MRV_DPCC_BPT_INCL_RB_CENTER */
  8909. /* Slice: BPT_INCL_GREEN_CENTER:*/
  8910. /* 1: if BPT active include center pixel for green output median 2x2+1 */
  8911. /* 0: if BPT active do not include center pixel for green output median 2x2 *Default**/
  8912. #ifdef MRV_DPCC_BPT_INCL_GREEN_CENTER
  8913. #endif /* MRV_DPCC_BPT_INCL_GREEN_CENTER */
  8914. /* Slice: BPT_USE_FIX_SET:*/
  8915. /* 1: for BPT write use hard coded methods set */
  8916. /* 0: for BPT write do not use hard coded methods set *Default**/
  8917. #ifdef MRV_DPCC_BPT_USE_FIX_SET
  8918. #endif /* MRV_DPCC_BPT_USE_FIX_SET */
  8919. /* Slice: BPT_USE_SET_3:*/
  8920. /* 1: for BPT write use methods set 3 */
  8921. /* 0: for BPT write do not use methods set 3 *Default**/
  8922. #ifdef MRV_DPCC_BPT_USE_SET_3
  8923. #endif /* MRV_DPCC_BPT_USE_SET_3 */
  8924. /* Slice: BPT_USE_SET_2:*/
  8925. /* 1: for BPT write use methods set 2 */
  8926. /* 0: for BPT write do not use methods set 2 *Default**/
  8927. #ifdef MRV_DPCC_BPT_USE_SET_2
  8928. #endif /* MRV_DPCC_BPT_USE_SET_2 */
  8929. /* Slice: BPT_USE_SET_1:*/
  8930. /* 1: for BPT write use methods set 1 */
  8931. /* 0: for BPT write do not use methods set 1 *Default**/
  8932. #ifdef MRV_DPCC_BPT_USE_SET_1
  8933. #endif /* MRV_DPCC_BPT_USE_SET_1 */
  8934. /* Slice: bpt_cor_en:*/
  8935. /* table based correction enable */
  8936. /* 1: table based correction is enabled */
  8937. /* 0: table based correction is disabled */
  8938. #ifdef MRV_DPCC_BPT_COR_EN
  8939. #endif /* MRV_DPCC_BPT_COR_EN */
  8940. /* Slice: bpt_det_en:*/
  8941. /* Bad pixel detection write enable */
  8942. /* 1: bad pixel detection write to memory is enabled */
  8943. /* 0: bad pixel detection write to memory is disabled */
  8944. #ifdef MRV_DPCC_BPT_DET_EN
  8945. #endif /* MRV_DPCC_BPT_DET_EN */
  8946. /*****************************************************************************/
  8947. /**
  8948. * register: isp_dpcc_bpt_addr: TABLE Start Address for table-based correction
  8949. * algorithm (0x00000064)
  8950. *
  8951. *****************************************************************************/
  8952. /* Slice: bp_table_addr:*/
  8953. /* Table RAM start address for read or write operations. The address counter */
  8954. /* is incremented at each read or write access to the data register (auto-*/
  8955. /* increment mechanism).*/
  8956. #ifdef MRV_DPCC_BP_TABLE_ADDR
  8957. #endif /* MRV_DPCC_BP_TABLE_ADDR */
  8958. /*****************************************************************************/
  8959. /**
  8960. * register: isp_dpcc_bpt_data: TABLE DATA register for read and write access
  8961. * of table RAM (0x00000068)
  8962. *
  8963. *****************************************************************************/
  8964. /* Slice: bpt_v_addr:*/
  8965. /* Bad Pixel vertical address (pixel position)*/
  8966. #ifdef MRV_DPCC_BPT_V_ADDR
  8967. #endif /* MRV_DPCC_BPT_V_ADDR */
  8968. /* Slice: bpt_h_addr:*/
  8969. /* Bad Pixel horizontal address (pixel position)*/
  8970. #ifdef MRV_DPCC_BPT_H_ADDR
  8971. #endif /* MRV_DPCC_BPT_H_ADDR */
  8972. /*****************************************************************************/
  8973. /* ISP Wide Dynamic Range */
  8974. /*****************************************************************************/
  8975. /*****************************************************************************/
  8976. /**
  8977. * register: isp_wdr_ctrl: Control Bits for Wide Dynamic Range Unit (0x00000000)
  8978. *
  8979. *****************************************************************************/
  8980. /* Slice: WDR_RGB_FACTOR:*/
  8981. /* rgb_factor defines how much influence the RGBmax approach has in comparison */
  8982. /* to Y. The illumination reference Iref is calculated according to the following */
  8983. /* formula:*/
  8984. /**/
  8985. /* Iref = (WDR_RGB_FACTOR * RGBYmax_tr + (8 - WDR_RGB_FACTOR) * Y) / 8 */
  8986. /**/
  8987. /* So, rgb_factor = 0 means that the standard approach is used. Use of this */
  8988. /* factor requires that Iref has been selected, see WDR_USE_IREF.*/
  8989. /**/
  8990. /* Value range of rgb_factor: 0...8 */
  8991. #ifdef MRV_WDR_RGB_FACTOR
  8992. #endif /* MRV_WDR_RGB_FACTOR */
  8993. /* Slice: WDR_DISABLE_TRANSIENT:*/
  8994. /* 1: disable transient between Y and RGBY_max */
  8995. /* 0: calculate transient between Y and RGBY_max (for noise reduction) *Default**/
  8996. /* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/
  8997. #ifdef MRV_WDR_DISABLE_TRANSIENT
  8998. #endif /* MRV_WDR_DISABLE_TRANSIENT */
  8999. /* Slice: WDR_USE_RGB7_8:*/
  9000. /* 1: decrease RGBmax by 7/8 (for noise reduction)*/
  9001. /* 0: do not modify RGBmax *Default**/
  9002. /* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/
  9003. #ifdef MRV_WDR_USE_RGB7_8
  9004. #endif /* MRV_WDR_USE_RGB7_8 */
  9005. /* Slice: WDR_USE_Y9_8:*/
  9006. /* 1: use R G B and Y*9/8 for maximum value calculation (for noise reduction)*/
  9007. /* 0: only use R G B for maximum value calculation (RGBYmax approach) *Default**/
  9008. /* Use of this bit requires that Iref has been selected, see WDR_USE_IREF.*/
  9009. #ifdef MRV_WDR_USE_Y9_8
  9010. #endif /* MRV_WDR_USE_Y9_8 */
  9011. /* Slice: WDR_USE_IREF:*/
  9012. /* 1: use Iref (Illumination reference) instead of Y for ToneMapping and Gain calculation */
  9013. /* 0: use Y for ToneMapping and Gain calculation *Default**/
  9014. /* Iref is calculated according to the following formula:*/
  9015. /* Iref = (WDR_RGB_FACTOR * RGBmax_tr + (8 - WDR_RGB_FACTOR) * Y) / 8 */
  9016. #ifdef MRV_WDR_USE_IREF
  9017. #endif /* MRV_WDR_USE_IREF */
  9018. /* Slice: WDR_CR_MAPPING_DISABLE:*/
  9019. /* 1: disable (bypass) Chrominance Mapping */
  9020. /* 0: enable Chrominance Mapping *Default**/
  9021. /* requires that Luminance/chrominance color space has been selected */
  9022. #ifdef MRV_WDR_CR_MAPPING_DISABLE
  9023. #endif /* MRV_WDR_CR_MAPPING_DISABLE */
  9024. /* Slice: WDR_COLOR_SPACE_SELECT:*/
  9025. /* 1: R, G, B color space */
  9026. /* 0: Luminance/Chrominance color space *Default**/
  9027. #ifdef MRV_WDR_COLOR_SPACE_SELECT
  9028. #endif /* MRV_WDR_COLOR_SPACE_SELECT */
  9029. /* Slice: WDR_ENABLE:*/
  9030. /* 1: enable WDR */
  9031. /* 0: bypass WDR *Default**/
  9032. #ifdef MRV_WDR_ENABLE
  9033. #endif /* MRV_WDR_ENABLE */
  9034. /*****************************************************************************/
  9035. /**
  9036. * register: isp_wdr_tonecurve_1: Tone Curve sample points dYn definition
  9037. * (part 1) (0x00000004)
  9038. *
  9039. * isp_wdr_tonecurve_1_shd: Tone Curve sample points dYn definition
  9040. * shadow register (part 1) (0x000000a0)
  9041. *
  9042. *****************************************************************************/
  9043. /* Slice: WDR_dY8:*/
  9044. /* Tone curve sample point definition dY8 on the horizontal axis (input)*/
  9045. #ifdef MRV_WDR_DY8
  9046. #endif /* MRV_WDR_DY8 */
  9047. /* Slice: WDR_dY7:*/
  9048. /* Tone curve sample point definition dY7 on the horizontal axis (input)*/
  9049. #ifdef MRV_WDR_DY7
  9050. #endif /* MRV_WDR_DY7 */
  9051. /* Slice: WDR_dY6:*/
  9052. /* Tone curve sample point definition dY6 on the horizontal axis (input)*/
  9053. #ifdef MRV_WDR_DY6
  9054. #endif /* MRV_WDR_DY6 */
  9055. /* Slice: WDR_dY5:*/
  9056. /* Tone curve sample point definition dY5 on the horizontal axis (input)*/
  9057. #ifdef MRV_WDR_DY5
  9058. #endif /* MRV_WDR_DY5 */
  9059. /* Slice: WDR_dY4:*/
  9060. /* Tone curve sample point definition dY4 on the horizontal axis (input)*/
  9061. #ifdef MRV_WDR_DY4
  9062. #endif /* MRV_WDR_DY4 */
  9063. /* Slice: WDR_dY3:*/
  9064. /* Tone curve sample point definition dY3 on the horizontal axis (input)*/
  9065. #ifdef MRV_WDR_DY3
  9066. #endif /* MRV_WDR_DY3 */
  9067. /* Slice: WDR_dY2:*/
  9068. /* Tone curve sample point definition dY2 on the horizontal axis (input)*/
  9069. #ifdef MRV_WDR_DY2
  9070. #endif /* MRV_WDR_DY2 */
  9071. /* Slice: WDR_dY1:*/
  9072. /* Tone curve sample point definition dY1 on the horizontal axis (input)*/
  9073. #ifdef MRV_WDR_DY1
  9074. #endif /* MRV_WDR_DY1 */
  9075. /*****************************************************************************/
  9076. /**
  9077. * register: isp_wdr_tonecurve_2: Tone Curve sample points dYn definition
  9078. * (part 2) (0x00000008)
  9079. *
  9080. * isp_wdr_tonecurve_2_shd: Tone Curve sample points dYn definition
  9081. * shadow register (part 2) (0x000000a4)
  9082. *
  9083. *****************************************************************************/
  9084. /* Slice: WDR_dY16:*/
  9085. /* Tone curve sample point definition dY16 on the horizontal axis (input)*/
  9086. #ifdef MRV_WDR_DY16
  9087. #endif /* MRV_WDR_DY16 */
  9088. /* Slice: WDR_dY15:*/
  9089. /* Tone curve sample point definition dY15 on the horizontal axis (input)*/
  9090. #ifdef MRV_WDR_DY15
  9091. #endif /* MRV_WDR_DY15 */
  9092. /* Slice: WDR_dY14:*/
  9093. /* Tone curve sample point definition dY14 on the horizontal axis (input)*/
  9094. #ifdef MRV_WDR_DY14
  9095. #endif /* MRV_WDR_DY14 */
  9096. /* Slice: WDR_dY13:*/
  9097. /* Tone curve sample point definition dY13 on the horizontal axis (input)*/
  9098. #ifdef MRV_WDR_DY13
  9099. #endif /* MRV_WDR_DY13 */
  9100. /* Slice: WDR_dY12:*/
  9101. /* Tone curve sample point definition dY12 on the horizontal axis (input)*/
  9102. #ifdef MRV_WDR_DY12
  9103. #endif /* MRV_WDR_DY12 */
  9104. /* Slice: WDR_dY11:*/
  9105. /* Tone curve sample point definition dY11 on the horizontal axis (input)*/
  9106. #ifdef MRV_WDR_DY11
  9107. #endif /* MRV_WDR_DY11 */
  9108. /* Slice: WDR_dY10:*/
  9109. /* Tone curve sample point definition dY10 on the horizontal axis (input)*/
  9110. #ifdef MRV_WDR_DY10
  9111. #endif /* MRV_WDR_DY10 */
  9112. /* Slice: WDR_dY9:*/
  9113. /* Tone curve sample point definition dY9 on the horizontal axis (input)*/
  9114. #ifdef MRV_WDR_DY9
  9115. #endif /* MRV_WDR_DY9 */
  9116. /*****************************************************************************/
  9117. /**
  9118. * register: isp_wdr_tonecurve_3: Tone Curve sample points dYn definition
  9119. * (part 3) (0x0000000c)
  9120. *
  9121. * isp_wdr_tonecurve_3_shd: Tone Curve sample points dYn definition
  9122. * shadow register (part 3) (0x000000a8)
  9123. *
  9124. *****************************************************************************/
  9125. /* Slice: WDR_dY24:*/
  9126. /* Tone curve sample point definition dY24 on the horizontal axis (input)*/
  9127. #ifdef MRV_WDR_DY24
  9128. #endif /* MRV_WDR_DY24 */
  9129. /* Slice: WDR_dY23:*/
  9130. /* Tone curve sample point definition dY23 on the horizontal axis (input)*/
  9131. #ifdef MRV_WDR_DY23
  9132. #endif /* MRV_WDR_DY23 */
  9133. /* Slice: WDR_dY22:*/
  9134. /* Tone curve sample point definition dY22 on the horizontal axis (input)*/
  9135. #ifdef MRV_WDR_DY22
  9136. #endif /* MRV_WDR_DY22 */
  9137. /* Slice: WDR_dY21:*/
  9138. /* Tone curve sample point definition dY21 on the horizontal axis (input)*/
  9139. #ifdef MRV_WDR_DY21
  9140. #endif /* MRV_WDR_DY21 */
  9141. /* Slice: WDR_dY20:*/
  9142. /* Tone curve sample point definition dY20 on the horizontal axis (input)*/
  9143. #ifdef MRV_WDR_DY20
  9144. #endif /* MRV_WDR_DY20 */
  9145. /* Slice: WDR_dY19:*/
  9146. /* Tone curve sample point definition dY19 on the horizontal axis (input)*/
  9147. #ifdef MRV_WDR_DY19
  9148. #endif /* MRV_WDR_DY19 */
  9149. /* Slice: WDR_dY18:*/
  9150. /* Tone curve sample point definition dY18 on the horizontal axis (input)*/
  9151. #ifdef MRV_WDR_DY18
  9152. #endif /* MRV_WDR_DY18 */
  9153. /* Slice: WDR_dY17:*/
  9154. /* Tone curve sample point definition dY17 on the horizontal axis (input)*/
  9155. #ifdef MRV_WDR_DY17
  9156. #endif /* MRV_WDR_DY17 */
  9157. /*****************************************************************************/
  9158. /**
  9159. * register: isp_wdr_tonecurve_4: Tone Curve sample points dYn definition
  9160. * (part 4) (0x00000010)
  9161. *
  9162. * isp_wdr_tonecurve_4_shd: Tone Curve sample points dYn definition
  9163. * shadow register(part 4) (0x000000ac)
  9164. *
  9165. *****************************************************************************/
  9166. /* Slice: WDR_dY32:*/
  9167. /* Tone curve sample point definition dY32 on the horizontal axis (input)*/
  9168. #ifdef MRV_WDR_DY32
  9169. #endif /* MRV_WDR_DY32 */
  9170. /* Slice: WDR_dY31:*/
  9171. /* Tone curve sample point definition dY31 on the horizontal axis (input)*/
  9172. #ifdef MRV_WDR_DY31
  9173. #endif /* MRV_WDR_DY31 */
  9174. /* Slice: WDR_dY30:*/
  9175. /* Tone curve sample point definition dY30 on the horizontal axis (input)*/
  9176. #ifdef MRV_WDR_DY30
  9177. #endif /* MRV_WDR_DY30 */
  9178. /* Slice: WDR_dY29:*/
  9179. /* Tone curve sample point definition dY29 on the horizontal axis (input)*/
  9180. #ifdef MRV_WDR_DY29
  9181. #endif /* MRV_WDR_DY29 */
  9182. /* Slice: WDR_dY28:*/
  9183. /* Tone curve sample point definition dY28 on the horizontal axis (input)*/
  9184. #ifdef MRV_WDR_DY28
  9185. #endif /* MRV_WDR_DY28 */
  9186. /* Slice: WDR_dY27:*/
  9187. /* Tone curve sample point definition dY27 on the horizontal axis (input)*/
  9188. #ifdef MRV_WDR_DY27
  9189. #endif /* MRV_WDR_DY27 */
  9190. /* Slice: WDR_dY26:*/
  9191. /* Tone curve sample point definition dY26 on the horizontal axis (input)*/
  9192. #ifdef MRV_WDR_DY26
  9193. #endif /* MRV_WDR_DY26 */
  9194. /* Slice: WDR_dY25:*/
  9195. /* Tone curve sample point definition dY25 on the horizontal axis (input)*/
  9196. #ifdef MRV_WDR_DY25
  9197. #endif /* MRV_WDR_DY25 */
  9198. /*****************************************************************************/
  9199. /**
  9200. * register array: isp_wdr_tonecurve_ym: Tonemapping curve coefficient Ym_
  9201. * (0x0028 + n*0x4 (n=0..32))
  9202. *
  9203. *****************************************************************************/
  9204. /* Slice: tonecurve_ym_n:*/
  9205. /* Tone curve value definition y-axis (output) of WDR unit */
  9206. #ifdef MRV_WDR_TONECURVE_YM_N
  9207. #endif /* MRV_WDR_TONECURVE_YM_N */
  9208. /*****************************************************************************/
  9209. /**
  9210. * register: isp_wdr_offset: Offset values for RGB path (0x00000098)
  9211. *
  9212. *****************************************************************************/
  9213. /* Slice: LUM_OFFSET:*/
  9214. /* Luminance Offset value (a) for RGB operation mode */
  9215. /* unsigned 12 bit value */
  9216. #ifdef MRV_WDR_LUM_OFFSET
  9217. #endif /* MRV_WDR_LUM_OFFSET */
  9218. /* Slice: RGB_OFFSET:*/
  9219. /* RGB Offset value (b) for RGB operation mode */
  9220. /* unsigned 12 bit value */
  9221. #ifdef MRV_WDR_RGB_OFFSET
  9222. #endif /* MRV_WDR_RGB_OFFSET */
  9223. /*****************************************************************************/
  9224. /**
  9225. * register: isp_wdr_deltamin: DeltaMin Threshold and Strength factor (0x0000009c)
  9226. *
  9227. *****************************************************************************/
  9228. /* Slice: DMIN_STRENGTH:*/
  9229. /* strength factor for DMIN */
  9230. /* unsigned 5 bit value, range 0x00...0x10 */
  9231. #ifdef MRV_WDR_DMIN_STRENGTH
  9232. #endif /* MRV_WDR_DMIN_STRENGTH */
  9233. /* Slice: DMIN_THRESH:*/
  9234. /* Lower threshold for deltaMin value */
  9235. /* unsigned 12 bit value */
  9236. #ifdef MRV_WDR_DMIN_THRESH
  9237. #endif /* MRV_WDR_DMIN_THRESH */
  9238. /*****************************************************************************/
  9239. /**
  9240. * register array: isp_wdr_tonecurve_ym_shd: Tonemapping curve coefficient
  9241. * shadow register (0x0160 + n*0x4 (n=0..32))
  9242. *
  9243. *****************************************************************************/
  9244. /* Slice: tonecurve_ym_n_shd:*/
  9245. /* Tone curve value definition y-axis (output) of WDR unit */
  9246. /* shadow register.*/
  9247. #ifdef MRV_WDR_TONECURVE_YM_N_SHD
  9248. #endif /* MRV_WDR_TONECURVE_YM_N_SHD */
  9249. /*****************************************************************************/
  9250. /* ISP Elliptic Auto White Balance Registers */
  9251. /*****************************************************************************/
  9252. /*****************************************************************************/
  9253. /**
  9254. * register: awb_meas_mode: AWB Measure Mode (0x00000000)
  9255. *
  9256. *****************************************************************************/
  9257. /*! Register: awb_meas_mode: AWB Measure Mode (0x00000000)*/
  9258. /*! Slice: AWB_union_e5_and_e8:*/
  9259. /*! unite ellipse 5 with ellipse 8. Accu and count for ellipse 8.*/
  9260. #ifdef ISP_AWB_UNION_E5_AND_E8
  9261. #define ISP_AWB_UNION_E5_AND_E8_ON 1 /* 1: enable unite ellipse 5 with ellipse 8 */
  9262. #define ISP_AWB_UNION_E5_AND_E8_OFF 0 /* 0: disable unite ellipse 5 with ellipse 8 */
  9263. #endif /* ISP_AWB_UNION_E5_AND_E8 */
  9264. /*! Slice: AWB_union_e5_and_e7:*/
  9265. /*! unite ellipse 5 with ellipse 7. Accu and count for ellipse 7.*/
  9266. #ifdef ISP_AWB_UNION_E5_AND_E7
  9267. #define ISP_AWB_UNION_E5_AND_E7_ON 1 /* 1: enable unite ellipse 5 with ellipse 7 */
  9268. #define ISP_AWB_UNION_E5_AND_E7_OFF 0 /* 0: disable unite ellipse 5 with ellipse 7 */
  9269. #endif /* ISP_AWB_UNION_E5_AND_E7 */
  9270. /*! Slice: AWB_union_e5_and_e6:*/
  9271. /*! unite ellipse 5 with ellipse 6. Accu and count for ellipse 6.*/
  9272. #ifdef ISP_AWB_UNION_E5_AND_E6
  9273. #define ISP_AWB_UNION_E5_AND_E6_ON 1 /* 1: enable unite ellipse 5 with ellipse 6 */
  9274. #define ISP_AWB_UNION_E5_AND_E6_OFF 0 /* 0: disable unite ellipse 5 with ellipse 6 */
  9275. #endif /* ISP_AWB_UNION_E5_AND_E6 */
  9276. /*! Slice: AWB_union_e1_and_e4:*/
  9277. /*! unite ellipse 1 with ellipse 4. Accu and count for ellipse 4.*/
  9278. #ifdef ISP_AWB_UNION_E1_AND_E4
  9279. #define ISP_AWB_UNION_E1_AND_E4_ON 1 /* 1: enable unite ellipse 1 with ellipse 4 */
  9280. #define ISP_AWB_UNION_E1_AND_E4_OFF 0 /* 0: disable unite ellipse 1 with ellipse 4 */
  9281. #endif /* ISP_AWB_UNION_E1_AND_E4 */
  9282. /*! Slice: AWB_union_e1_and_e3:*/
  9283. /*! unite ellipse 1 with ellipse 3. Accu and count for ellipse 3.*/
  9284. #ifdef ISP_AWB_UNION_E1_AND_E3
  9285. #define ISP_AWB_UNION_E1_AND_E3_ON 1 /* 1: enable unite ellipse 1 with ellipse 3 */
  9286. #define ISP_AWB_UNION_E1_AND_E3_OFF 0 /* 0: disable unite ellipse 1 with ellipse 3 */
  9287. #endif /* ISP_AWB_UNION_E1_AND_E3 */
  9288. /*! Slice: AWB_union_e1_and_e2:*/
  9289. /*! unite ellipse 1 with ellipse 2. Accu and count for ellipse 2.*/
  9290. #ifdef ISP_AWB_UNION_E1_AND_E2
  9291. #define ISP_AWB_UNION_E1_AND_E2_ON 1 /* 1: enable unite ellipse 1 with ellipse 2 */
  9292. #define ISP_AWB_UNION_E1_AND_E2_OFF 0 /* 0: disable unite ellipse 1 with ellipse 2 */
  9293. #endif /* ISP_AWB_UNION_E1_AND_E2 */
  9294. /*! Slice: AWB_meas_chrom_switch:*/
  9295. /*! Accumulates Q1 and Q2 chromaticies instead of R, G, B color signals. Results are written on AWB_ACCU registers as well.*/
  9296. #ifdef ISP_AWB_MEAS_CHROM_SWITCH
  9297. #define ISP_AWB_MEAS_CHROM_SWITCH_ON 1 /* 1: accumulates Q1 and Q2 chromaticies */
  9298. #define ISP_AWB_MEAS_CHROM_SWITCH_OFF 0 /* 0: accumulates R, G, B color signals */
  9299. #endif /* ISP_AWB_MEAS_CHROM_SWITCH */
  9300. /* Slice: AWB_meas_irq_enable:*/
  9301. /* AWB measure done IRQ enable.*/
  9302. #ifdef ISP_AWB_MEAS_IRQ_ENABLE
  9303. #define ISP_AWB_MEAS_IRQ_ENABLE_ON 1 /* 1: enable measuring done irq */
  9304. #define ISP_AWB_MEAS_IRQ_ENABLE_OFF 0 /* 0: enable measuring done irq */
  9305. #endif /* ISP_AWB_MEAS_IRQ_ENABLE */
  9306. /* Slice: AWB_pre_filt_en:*/
  9307. /* median pre filter enable.*/
  9308. #ifdef ISP_AWB_PRE_FILT_EN
  9309. #define ISP_AWB_PRE_FILT_EN_ON 1 /* 1: enable median pre filter */
  9310. #define ISP_AWB_PRE_FILT_EN_OFF 0 /* 0: disable median pre filter */
  9311. #endif /* ISP_AWB_PRE_FILT_EN */
  9312. /* Slice: AWB_meas_en:*/
  9313. /* enable measure.*/
  9314. #ifdef ISP_AWB_MEAS_EN
  9315. #define ISP_AWB_MEAS_EN_ON 1 /* 1: enable measuring */
  9316. #define ISP_AWB_MEAS_EN_OFF 0 /* 0: disable measuring */
  9317. #endif /* ISP_AWB_MEAS_EN */
  9318. /*****************************************************************************/
  9319. /**
  9320. * register: awb_meas_h_offs: AWB window horizontal offset (0x00000004)
  9321. *
  9322. *****************************************************************************/
  9323. /* Slice: AWB_h_offset:*/
  9324. /* Horizontal offset in pixels.*/
  9325. #ifdef ISP_AWB_H_OFFSET
  9326. #define ISP_AWB_H_OFFSET_MIN 0U
  9327. #define ISP_AWB_H_OFFSET_MAX (ISP_AWB_H_OFFSET_MASK >> ISP_AWB_H_OFFSET_SHIFT)
  9328. #endif /* ISP_AWB_H_OFFSET */
  9329. /*****************************************************************************/
  9330. /**
  9331. * register: awb_meas_v_offs: AWB window vertical offset (0x00000008)
  9332. *
  9333. *****************************************************************************/
  9334. /* Slice: AWB_v_offset:*/
  9335. /* Vertical offset in pixels.*/
  9336. #ifdef ISP_AWB_V_OFFSET
  9337. #define ISP_AWB_V_OFFSET_MIN 0U
  9338. #define ISP_AWB_V_OFFSET_MAX (ISP_AWB_V_OFFSET_MASK >> ISP_AWB_V_OFFSET_SHIFT)
  9339. #endif /* ISP_AWB_V_OFFSET */
  9340. /*****************************************************************************/
  9341. /**
  9342. * register: awb_meas_h_size: Horizontal window size (0x0000000c)
  9343. *
  9344. *****************************************************************************/
  9345. /* Slice: AWB_h_size:*/
  9346. /* Horizontal size in pixels.*/
  9347. #ifdef ISP_AWB_H_SIZE
  9348. #define ISP_AWB_H_SIZE_MIN 0U
  9349. #define ISP_AWB_H_SIZE_MAX (ISP_AWB_H_SIZE_MASK >> ISP_AWB_H_SIZE_SHIFT)
  9350. #endif /* ISP_AWB_H_SIZE */
  9351. /*****************************************************************************/
  9352. /**
  9353. * register: awb_meas_v_size: Vertical window size (0x00000010)
  9354. *
  9355. *****************************************************************************/
  9356. /* Slice: AWB_v_size:*/
  9357. /* Vertical size.*/
  9358. #ifdef ISP_AWB_V_SIZE
  9359. #define ISP_AWB_V_SIZE_MIN 0U
  9360. #define ISP_AWB_V_SIZE_MAX (ISP_AWB_V_SIZE_MASK >> ISP_AWB_V_SIZE_SHIFT)
  9361. #endif /* ISP_AWB_V_SIZE */
  9362. /*****************************************************************************/
  9363. /**
  9364. * register: awb_meas_r_min_max: Min Max Compare Red (0x00000014)
  9365. *
  9366. *****************************************************************************/
  9367. /* Slice: r_max:*/
  9368. /* max red value */
  9369. #ifdef ISP_AWB_R_MAX
  9370. #endif /* ISP_AWB_R_MAX */
  9371. /* Slice: r_min:*/
  9372. /* min red value */
  9373. #ifdef ISP_AWB_R_MIN
  9374. #endif /* ISP_AWB_R_MIN */
  9375. /*****************************************************************************/
  9376. /**
  9377. * register: awb_meas_g_min_max: Min Max Compare Green (0x00000018)
  9378. *
  9379. *****************************************************************************/
  9380. /* Slice: g_max:*/
  9381. /* max green value */
  9382. #ifdef ISP_AWB_G_MAX
  9383. #endif /* ISP_AWB_G_MAX */
  9384. /* Slice: g_min:*/
  9385. /* min green value */
  9386. #ifdef ISP_AWB_G_MIN
  9387. #endif /* ISP_AWB_G_MIN */
  9388. /*****************************************************************************/
  9389. /**
  9390. * register: awb_meas_b_min_max: Min Max Compare Blue (0x0000001c)
  9391. *
  9392. *****************************************************************************/
  9393. /* Slice: b_max:*/
  9394. /* max blue value */
  9395. #ifdef ISP_AWB_B_MAX
  9396. #endif /* ISP_AWB_B_MAX */
  9397. /*! Slice: b_min:*/
  9398. /*! min blue value */
  9399. #ifdef ISP_AWB_B_MIN
  9400. #endif /* ISP_AWB_B_MIN */
  9401. /*****************************************************************************/
  9402. /**
  9403. * register: awb_meas_divider_min: Min Compare Divider (0x00000020)
  9404. *
  9405. *****************************************************************************/
  9406. /* Slice: div_min:*/
  9407. /* min divider value unsigned integer with 10 fractional Bits range 0 to 0.999 */
  9408. #ifdef ISP_AWB_DIV_MIN
  9409. #endif /* ISP_AWB_DIV_MIN */
  9410. /*****************************************************************************/
  9411. /**
  9412. * register: awb_meas_csc_coeff_0: Color conversion coefficient 0 (0x00000024)
  9413. *
  9414. *****************************************************************************/
  9415. /* Slice: cc_coeff_0:*/
  9416. /* coefficient 0 for color space conversion */
  9417. #ifdef ISP_AWB_CC_COEFF_0
  9418. #endif /* ISP_AWB_CC_COEFF_0 */
  9419. /*****************************************************************************/
  9420. /**
  9421. * register: awb_meas_csc_coeff_1: Color conversion coefficient 1 (0x00000028)
  9422. *
  9423. *****************************************************************************/
  9424. /* Slice: cc_coeff_1:*/
  9425. /* coefficient 1 for color space conversion */
  9426. #ifdef ISP_AWB_CC_COEFF_1
  9427. #endif /* ISP_AWB_CC_COEFF_1 */
  9428. /*****************************************************************************/
  9429. /**
  9430. * register: awb_meas_csc_coeff_2: Color conversion coefficient 2 (0x0000002c)
  9431. *
  9432. *****************************************************************************/
  9433. /* Slice: cc_coeff_2:*/
  9434. /* coefficient 2 for color space conversion */
  9435. #ifdef ISP_AWB_CC_COEFF_2
  9436. #endif /* ISP_AWB_CC_COEFF_2 */
  9437. /*****************************************************************************/
  9438. /**
  9439. * register: awb_meas_csc_coeff_3: Color conversion coefficient 3 (0x00000030)
  9440. *
  9441. *****************************************************************************/
  9442. /* Slice: cc_coeff_3:*/
  9443. /* coefficient 3 for color space conversion */
  9444. #ifdef ISP_AWB_CC_COEFF_3
  9445. #endif /* ISP_AWB_CC_COEFF_3 */
  9446. /*****************************************************************************/
  9447. /**
  9448. * register: awb_meas_csc_coeff_4: Color conversion coefficient 4 (0x00000034)
  9449. *
  9450. *****************************************************************************/
  9451. /* Slice: cc_coeff_4:*/
  9452. /* coefficient 4 for color space conversion */
  9453. #ifdef ISP_AWB_CC_COEFF_4
  9454. #endif /* ISP_AWB_CC_COEFF_4 */
  9455. /*****************************************************************************/
  9456. /**
  9457. * register: awb_meas_csc_coeff_5: Color conversion coefficient 5 (0x00000038)
  9458. *
  9459. *****************************************************************************/
  9460. /* Slice: cc_coeff_5:*/
  9461. /* coefficient 5 for color space conversion */
  9462. #ifdef ISP_AWB_CC_COEFF_5
  9463. #endif /* ISP_AWB_CC_COEFF_5 */
  9464. /*****************************************************************************/
  9465. /**
  9466. * register: awb_meas_csc_coeff_6: Color conversion coefficient 6 (0x0000003c)
  9467. *
  9468. *****************************************************************************/
  9469. /* Slice: cc_coeff_6:*/
  9470. /* coefficient 6 for color space conversion */
  9471. #ifdef ISP_AWB_CC_COEFF_6
  9472. #endif /* ISP_AWB_CC_COEFF_6 */
  9473. /*****************************************************************************/
  9474. /**
  9475. * register: awb_meas_csc_coeff_7: Color conversion coefficient 7 (0x00000040)
  9476. *
  9477. *****************************************************************************/
  9478. /* Slice: cc_coeff_7:*/
  9479. /* coefficient 7 for color space conversion */
  9480. #ifdef ISP_AWB_CC_COEFF_7
  9481. #endif /* ISP_AWB_CC_COEFF_7 */
  9482. /*****************************************************************************/
  9483. /**
  9484. * register: awb_meas_csc_coeff_8: Color conversion coefficient 8 (0x00000044)
  9485. *
  9486. *****************************************************************************/
  9487. /* Slice: cc_coeff_8:*/
  9488. /* coefficient 8 for color space conversion */
  9489. #ifdef ISP_AWB_CC_COEFF_8
  9490. #endif /* ISP_AWB_CC_COEFF_8 */
  9491. /*****************************************************************************/
  9492. /**
  9493. * register: awb_meas_ellip1_cen_x: Ellipse 1 Center X (0x00000048)
  9494. *
  9495. *****************************************************************************/
  9496. /* Slice: ellip1_cen_x:*/
  9497. /* Ellipse 1 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9498. #ifdef ISP_AWB_ELLIP1_CEN_X
  9499. #endif /* ISP_AWB_ELLIP1_CEN_X */
  9500. /*****************************************************************************/
  9501. /**
  9502. * register: awb_meas_ellip1_cen_y: Ellipse 1 Center Y (0x0000004c)
  9503. *
  9504. *****************************************************************************/
  9505. /* Slice: ellip1_cen_y:*/
  9506. /* Ellipse 1 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9507. #ifdef ISP_AWB_ELLIP1_CEN_Y
  9508. #endif /* ISP_AWB_ELLIP1_CEN_Y */
  9509. /*****************************************************************************/
  9510. /**
  9511. * register: awb_meas_ellip2_cen_x: Ellipse 2 Center X (0x00000050)
  9512. *
  9513. *****************************************************************************/
  9514. /* Slice: ellip2_cen_x:*/
  9515. /* Ellipse 2 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9516. #ifdef ISP_AWB_ELLIP2_CEN_X
  9517. #endif /* ISP_AWB_ELLIP2_CEN_X */
  9518. /*****************************************************************************/
  9519. /**
  9520. * register: awb_meas_ellip2_cen_y: Ellipse 2 Center Y (0x00000054)
  9521. *
  9522. *****************************************************************************/
  9523. /* Slice: ellip2_cen_y:*/
  9524. /* Ellipse 2 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9525. #ifdef ISP_AWB_ELLIP2_CEN_Y
  9526. #endif /* ISP_AWB_ELLIP2_CEN_Y */
  9527. /*****************************************************************************/
  9528. /**
  9529. * register: awb_meas_ellip3_cen_x: Ellipse 3 Center X (0x00000058)
  9530. *
  9531. *****************************************************************************/
  9532. /* Slice: ellip3_cen_x:*/
  9533. /* Ellipse 3 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9534. #ifdef ISP_AWB_ELLIP3_CEN_X
  9535. #endif /* ISP_AWB_ELLIP3_CEN_X */
  9536. /*****************************************************************************/
  9537. /**
  9538. * register: awb_meas_ellip3_cen_y: Ellipse 3 Center Y (0x0000005c)
  9539. *
  9540. *****************************************************************************/
  9541. /* Slice: ellip3_cen_y:*/
  9542. /* Ellipse 3 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9543. #ifdef ISP_AWB_ELLIP3_CEN_Y
  9544. #endif /* ISP_AWB_ELLIP3_CEN_Y */
  9545. /*****************************************************************************/
  9546. /**
  9547. * register: awb_meas_ellip4_cen_x: Ellipse 4 Center X (0x00000060)
  9548. *
  9549. *****************************************************************************/
  9550. /* Slice: ellip4_cen_x:*/
  9551. /* Ellipse 4 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9552. #ifdef ISP_AWB_ELLIP4_CEN_X
  9553. #endif /* ISP_AWB_ELLIP4_CEN_X */
  9554. /*****************************************************************************/
  9555. /**
  9556. * register: awb_meas_ellip4_cen_y: Ellipse 4 Center Y (0x00000064)
  9557. *
  9558. *****************************************************************************/
  9559. /* Register: awb_meas_ellip4_cen_y: Ellipse 4 Center Y (0x00000064)*/
  9560. /* Slice: ellip4_cen_y:*/
  9561. /* Ellipse 4 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9562. #ifdef ISP_AWB_ELLIP4_CEN_Y
  9563. #endif /* ISP_AWB_ELLIP4_CEN_Y */
  9564. /*****************************************************************************/
  9565. /**
  9566. * register: awb_meas_ellip5_cen_x: Ellipse 5 Center X (0x00000068)
  9567. *
  9568. *****************************************************************************/
  9569. /* Slice: ellip5_cen_x:*/
  9570. /* Ellipse 5 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9571. #ifdef ISP_AWB_ELLIP5_CEN_X
  9572. #endif /* ISP_AWB_ELLIP5_CEN_X */
  9573. /*****************************************************************************/
  9574. /**
  9575. * register: awb_meas_ellip5_cen_y: Ellipse 5 Center Y (0x0000006c)
  9576. *
  9577. *****************************************************************************/
  9578. /* Slice: ellip5_cen_y:*/
  9579. /* Ellipse 5 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9580. #ifdef ISP_AWB_ELLIP5_CEN_Y
  9581. #endif /* ISP_AWB_ELLIP5_CEN_Y */
  9582. /*****************************************************************************/
  9583. /**
  9584. * register: awb_meas_ellip6_cen_x: Ellipse 6 Center X (0x00000070)
  9585. *
  9586. *****************************************************************************/
  9587. /* Slice: ellip6_cen_x:*/
  9588. /* Ellipse 6 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9589. #ifdef ISP_AWB_ELLIP6_CEN_X
  9590. #endif /* ISP_AWB_ELLIP6_CEN_X */
  9591. /*****************************************************************************/
  9592. /**
  9593. * register: awb_meas_ellip6_cen_y: Ellipse 6 Center Y (0x00000074)
  9594. *
  9595. *****************************************************************************/
  9596. /* Slice: ellip6_cen_y:*/
  9597. /* Ellipse 6 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9598. #ifdef ISP_AWB_ELLIP6_CEN_Y
  9599. #endif /* ISP_AWB_ELLIP6_CEN_Y */
  9600. /*****************************************************************************/
  9601. /**
  9602. * register: awb_meas_ellip7_cen_x: Ellipse 7 Center X (0x00000078)
  9603. *
  9604. *****************************************************************************/
  9605. /* Slice: ellip7_cen_x:*/
  9606. /* Ellipse 7 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9607. #ifdef ISP_AWB_ELLIP7_CEN_X
  9608. #endif /* ISP_AWB_ELLIP7_CEN_X */
  9609. /*****************************************************************************/
  9610. /**
  9611. * register: awb_meas_ellip7_cen_y: Ellipse 7 Center Y (0x0000007c)
  9612. *
  9613. *****************************************************************************/
  9614. /* Slice: ellip7_cen_y:*/
  9615. /* Ellipse 7 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9616. #ifdef ISP_AWB_ELLIP7_CEN_Y
  9617. #endif /* ISP_AWB_ELLIP7_CEN_Y */
  9618. /*****************************************************************************/
  9619. /**
  9620. * register: awb_meas_ellip8_cen_x: Ellipse 8 Center X (0x00000080)
  9621. *
  9622. *****************************************************************************/
  9623. /* Slice: ellip8_cen_x:*/
  9624. /* Ellipse 8 Center X signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9625. #ifdef ISP_AWB_ELLIP8_CEN_X
  9626. #endif /* ISP_AWB_ELLIP8_CEN_X */
  9627. /*****************************************************************************/
  9628. /**
  9629. * register: awb_meas_ellip8_cen_y: Ellipse 8 Center Y (0x00000084)
  9630. *
  9631. *****************************************************************************/
  9632. /* Slice: ellip8_cen_y:*/
  9633. /* Ellipse 8 Center Y signed integer value with 9 bit fractional part, range -1 to 0.998 */
  9634. #ifdef ISP_AWB_ELLIP8_CEN_Y
  9635. #endif /* ISP_AWB_ELLIP8_CEN_Y */
  9636. /*****************************************************************************/
  9637. /**
  9638. * register: awb_meas_ellip1_a1: Ellipse 1 coefficient a1 (0x00000088)
  9639. *
  9640. *****************************************************************************/
  9641. /* Slice: ellip1_a1:*/
  9642. /* Ellipse 1 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9643. #ifdef ISP_AWB_ELLIP1_A1
  9644. #endif /* ISP_AWB_ELLIP1_A1 */
  9645. /*****************************************************************************/
  9646. /**
  9647. * register: awb_meas_ellip1_a2: Ellipse 1 coefficient a2 (0x0000008c)
  9648. *
  9649. *****************************************************************************/
  9650. /* Slice: ellip1_a2:*/
  9651. /* Ellipse 1 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9652. #ifdef ISP_AWB_ELLIP1_A2
  9653. #endif /* ISP_AWB_ELLIP1_A2 */
  9654. /*****************************************************************************/
  9655. /**
  9656. * register: awb_meas_ellip1_a3: Ellipse 1 coefficient a3 (0x00000090)
  9657. *
  9658. *****************************************************************************/
  9659. /* Slice: ellip1_a3:*/
  9660. /* Ellipse 1 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9661. #ifdef ISP_AWB_ELLIP1_A3
  9662. #endif /* ISP_AWB_ELLIP1_A3 */
  9663. /*****************************************************************************/
  9664. /**
  9665. * register: awb_meas_ellip1_a4: Ellipse 1 coefficient a4 (0x00000094)
  9666. *
  9667. *****************************************************************************/
  9668. /* Slice: ellip1_a4:*/
  9669. /* Ellipse 1 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9670. #ifdef ISP_AWB_ELLIP1_A4
  9671. #endif /* ISP_AWB_ELLIP1_A4 */
  9672. /*****************************************************************************/
  9673. /**
  9674. * register: awb_meas_ellip2_a1: Ellipse 2 coefficient a1 (0x00000098)
  9675. *
  9676. *****************************************************************************/
  9677. /* Slice: ellip2_a1:*/
  9678. /* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9679. #ifdef ISP_AWB_ELLIP2_A1
  9680. #endif /* ISP_AWB_ELLIP2_A1 */
  9681. /*****************************************************************************/
  9682. /**
  9683. * register: awb_meas_ellip2_a2: Ellipse 2 coefficient a2 (0x0000009c)
  9684. *
  9685. *****************************************************************************/
  9686. /* Slice: ellip2_a2:*/
  9687. /* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9688. #ifdef ISP_AWB_ELLIP2_A2
  9689. #endif /* ISP_AWB_ELLIP2_A2 */
  9690. /*****************************************************************************/
  9691. /**
  9692. * register: awb_meas_ellip2_a3: Ellipse 2 coefficient a3 (0x000000a0)
  9693. *
  9694. *****************************************************************************/
  9695. /* Slice: ellip2_a3:*/
  9696. /* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9697. #ifdef ISP_AWB_ELLIP2_A3
  9698. #endif /* ISP_AWB_ELLIP2_A3 */
  9699. /*****************************************************************************/
  9700. /**
  9701. * register: awb_meas_ellip2_a4: Ellipse 2 coefficient a4 (0x000000a4)
  9702. *
  9703. *****************************************************************************/
  9704. /* Slice: ellip2_a4:*/
  9705. /* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9706. #ifdef ISP_AWB_ELLIP2_A4
  9707. #endif /* ISP_AWB_ELLIP2_A4 */
  9708. /*****************************************************************************/
  9709. /**
  9710. * register: awb_meas_ellip3_a1: Ellipse 3 coefficient a1 (0x000000a8)
  9711. *
  9712. *****************************************************************************/
  9713. /* Slice: ellip3_a1:*/
  9714. /* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9715. #ifdef ISP_AWB_ELLIP3_A1
  9716. #endif /* ISP_AWB_ELLIP3_A1 */
  9717. /*****************************************************************************/
  9718. /**
  9719. * register: awb_meas_ellip3_a2: Ellipse 3 coefficient a2 (0x000000ac)
  9720. *
  9721. *****************************************************************************/
  9722. /* Slice: ellip3_a2:*/
  9723. /* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9724. #ifdef ISP_AWB_ELLIP3_A2
  9725. #endif /* ISP_AWB_ELLIP3_A2 */
  9726. /*****************************************************************************/
  9727. /**
  9728. * register: awb_meas_ellip3_a3: Ellipse 3 coefficient a3 (0x000000b0)
  9729. *
  9730. *****************************************************************************/
  9731. /* Slice: ellip3_a3:*/
  9732. /* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9733. #ifdef ISP_AWB_ELLIP3_A3
  9734. #endif /* ISP_AWB_ELLIP3_A3 */
  9735. /*****************************************************************************/
  9736. /**
  9737. * register: awb_meas_ellip3_a4: Ellipse 3 coefficient a4 (0x000000b4)
  9738. *
  9739. *****************************************************************************/
  9740. /* Slice: ellip3_a4:*/
  9741. /* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9742. #ifdef ISP_AWB_ELLIP3_A4
  9743. #endif /* ISP_AWB_ELLIP3_A4 */
  9744. /*****************************************************************************/
  9745. /**
  9746. * register: awb_meas_ellip4_a1: Ellipse 4 coefficient a1 (0x000000b8)
  9747. *
  9748. *****************************************************************************/
  9749. /* Slice: ellip4_a1:*/
  9750. /* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9751. #ifdef ISP_AWB_ELLIP4_A1
  9752. #endif /* ISP_AWB_ELLIP4_A1 */
  9753. /*****************************************************************************/
  9754. /**
  9755. * register: awb_meas_ellip4_a2: Ellipse 4 coefficient a2 (0x000000bc)
  9756. *
  9757. *****************************************************************************/
  9758. /* Slice: ellip4_a2:*/
  9759. /* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9760. #ifdef ISP_AWB_ELLIP4_A2
  9761. #endif /* ISP_AWB_ELLIP4_A2 */
  9762. /*****************************************************************************/
  9763. /**
  9764. * register: awb_meas_ellip4_a3: Ellipse 4 coefficient a3 (0x000000c0)
  9765. *
  9766. *****************************************************************************/
  9767. /* Slice: ellip4_a3:*/
  9768. /* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9769. #ifdef ISP_AWB_ELLIP4_A3
  9770. #endif /* ISP_AWB_ELLIP4_A3 */
  9771. /*****************************************************************************/
  9772. /**
  9773. * register: awb_meas_ellip4_a4: Ellipse 4 coefficient a4 (0x000000c4)
  9774. *
  9775. *****************************************************************************/
  9776. /* Slice: ellip4_a4:*/
  9777. /* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9778. #ifdef ISP_AWB_ELLIP4_A4
  9779. #endif /* ISP_AWB_ELLIP4_A4 */
  9780. /*****************************************************************************/
  9781. /**
  9782. * register: awb_meas_ellip5_a1: Ellipse 5 coefficient a1 (0x000000c8)
  9783. *
  9784. *****************************************************************************/
  9785. /* Slice: ellip5_a1:*/
  9786. /* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9787. #ifdef ISP_AWB_ELLIP5_A1
  9788. #endif /* ISP_AWB_ELLIP5_A1 */
  9789. /*****************************************************************************/
  9790. /**
  9791. * register: awb_meas_ellip5_a2: Ellipse 5 coefficient a2 (0x000000cc)
  9792. *
  9793. *****************************************************************************/
  9794. /* Slice: ellip5_a2:*/
  9795. /* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9796. #ifdef ISP_AWB_ELLIP5_A2
  9797. #endif /* ISP_AWB_ELLIP5_A2 */
  9798. /*****************************************************************************/
  9799. /**
  9800. * register: awb_meas_ellip5_a3: Ellipse 5 coefficient a3 (0x000000d0)
  9801. *
  9802. *****************************************************************************/
  9803. /* Slice: ellip5_a3:*/
  9804. /* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9805. #ifdef ISP_AWB_ELLIP5_A3
  9806. #endif /* ISP_AWB_ELLIP5_A3 */
  9807. /*****************************************************************************/
  9808. /**
  9809. * register: awb_meas_ellip5_a4: Ellipse 5 coefficient a4 (0x000000d4)
  9810. *
  9811. *****************************************************************************/
  9812. /* Slice: ellip5_a4:*/
  9813. /* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9814. #ifdef ISP_AWB_ELLIP5_A4
  9815. #endif /* ISP_AWB_ELLIP5_A4 */
  9816. /*****************************************************************************/
  9817. /**
  9818. * register: awb_meas_ellip6_a1: Ellipse 6 coefficient a1 (0x000000d8)
  9819. *
  9820. *****************************************************************************/
  9821. /* Slice: ellip6_a1:*/
  9822. /* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9823. #ifdef ISP_AWB_ELLIP6_A1
  9824. #endif /* ISP_AWB_ELLIP6_A1 */
  9825. /*****************************************************************************/
  9826. /**
  9827. * register: awb_meas_ellip6_a2: Ellipse 6 coefficient a2 (0x000000dc)
  9828. *
  9829. *****************************************************************************/
  9830. /* Slice: ellip6_a2:*/
  9831. /* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9832. #ifdef ISP_AWB_ELLIP6_A2
  9833. #endif /* ISP_AWB_ELLIP6_A2 */
  9834. /*****************************************************************************/
  9835. /**
  9836. * register: awb_meas_ellip6_a3: Ellipse 6 coefficient a3 (0x000000e0)
  9837. *
  9838. *****************************************************************************/
  9839. /* Slice: ellip6_a3:*/
  9840. /* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9841. #ifdef ISP_AWB_ELLIP6_A3
  9842. #endif /* ISP_AWB_ELLIP6_A3 */
  9843. /*****************************************************************************/
  9844. /**
  9845. * register: awb_meas_ellip6_a4: Ellipse 6 coefficient a4 (0x000000e4)
  9846. *
  9847. *****************************************************************************/
  9848. /* Slice: ellip6_a4:*/
  9849. /* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9850. #ifdef ISP_AWB_ELLIP6_A4
  9851. #endif /* ISP_AWB_ELLIP6_A4 */
  9852. /*****************************************************************************/
  9853. /**
  9854. * register: awb_meas_ellip7_a1: Ellipse 7 coefficient a1 (0x000000e8)
  9855. *
  9856. *****************************************************************************/
  9857. /* Slice: ellip7_a1:*/
  9858. /* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9859. #ifdef ISP_AWB_ELLIP7_A1
  9860. #endif /* ISP_AWB_ELLIP7_A1 */
  9861. /*****************************************************************************/
  9862. /**
  9863. * register: awb_meas_ellip7_a2: Ellipse 7 coefficient a2 (0x000000ec)
  9864. *
  9865. *****************************************************************************/
  9866. /* Slice: ellip7_a2:*/
  9867. /* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9868. #ifdef ISP_AWB_ELLIP7_A2
  9869. #endif /* ISP_AWB_ELLIP7_A2 */
  9870. /*****************************************************************************/
  9871. /**
  9872. * register: awb_meas_ellip7_a3: Ellipse 7 coefficient a3 (0x000000f0)
  9873. *
  9874. *****************************************************************************/
  9875. /* Slice: ellip7_a3:*/
  9876. /* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9877. #ifdef ISP_AWB_ELLIP7_A3
  9878. #endif /* ISP_AWB_ELLIP7_A3 */
  9879. /*****************************************************************************/
  9880. /**
  9881. * register: awb_meas_ellip7_a4: Ellipse 7 coefficient a4 (0x000000f4)
  9882. *
  9883. *****************************************************************************/
  9884. /* Slice: ellip7_a4:*/
  9885. /* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9886. #ifdef ISP_AWB_ELLIP7_A4
  9887. #endif /* ISP_AWB_ELLIP7_A4 */
  9888. /*****************************************************************************/
  9889. /**
  9890. * register: awb_meas_ellip8_a1: Ellipse 8 coefficient a1 (0x000000f8)
  9891. *
  9892. *****************************************************************************/
  9893. /* Slice: ellip8_a1:*/
  9894. /* Ellipse 2 Coefficient a1 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9895. #ifdef ISP_AWB_ELLIP8_A1
  9896. #endif /* ISP_AWB_ELLIP8_A1 */
  9897. /*****************************************************************************/
  9898. /**
  9899. * register: awb_meas_ellip8_a2: Ellipse 8 coefficient a2 (0x000000fc)
  9900. *
  9901. *****************************************************************************/
  9902. /* Slice: ellip8_a2:*/
  9903. /* Ellipse 2 Coefficient a2 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9904. #ifdef ISP_AWB_ELLIP8_A2
  9905. #endif /* ISP_AWB_ELLIP8_A2 */
  9906. /*****************************************************************************/
  9907. /**
  9908. * register: awb_meas_ellip8_a3: Ellipse 8 coefficient a3 (0x00000100)
  9909. *
  9910. *****************************************************************************/
  9911. /* Slice: ellip8_a3:*/
  9912. /* Ellipse 2 Coefficient a3 signed integer value with 8 bit fractional part, range -7.996 to 7.996 */
  9913. #ifdef ISP_AWB_ELLIP8_A3
  9914. #endif /* ISP_AWB_ELLIP8_A3 */
  9915. /*****************************************************************************/
  9916. /**
  9917. * register: awb_meas_ellip8_a4: Ellipse 8 coefficient a4 (0x00000104)
  9918. *
  9919. *****************************************************************************/
  9920. /* Slice: ellip8_a4:*/
  9921. /* Ellipse 2 Coefficient a4 signed integer value with 8 bit fractional part, range -1 to 0.996 */
  9922. #ifdef ISP_AWB_ELLIP8_A4
  9923. #endif /* ISP_AWB_ELLIP8_A4 */
  9924. /*****************************************************************************/
  9925. /**
  9926. * register: awb_meas_ellip1_rmax: Ellipse 1 r_max (0x00000108)
  9927. *
  9928. *****************************************************************************/
  9929. /* Slice: ellip1_rmax:*/
  9930. /* Ellipse 1 max radius square compare value */
  9931. #ifdef ISP_AWB_ELLIP1_RMAX
  9932. #endif /* ISP_AWB_ELLIP1_RMAX */
  9933. /*****************************************************************************/
  9934. /**
  9935. * register: awb_meas_ellip2_rmax: Ellipse 2 r_max (0x0000010c)
  9936. *
  9937. *****************************************************************************/
  9938. /* Slice: ellip2_rmax:*/
  9939. /* Ellipse 2 max radius square compare value */
  9940. #ifdef ISP_AWB_ELLIP2_RMAX
  9941. #endif /* ISP_AWB_ELLIP2_RMAX */
  9942. /*****************************************************************************/
  9943. /**
  9944. * register: awb_meas_ellip3_rmax: Ellipse 3 r_max (0x00000110)
  9945. *
  9946. *****************************************************************************/
  9947. /* Slice: ellip3_rmax:*/
  9948. /* Ellipse 3 max radius square compare value */
  9949. #ifdef ISP_AWB_ELLIP3_RMAX
  9950. #endif /* ISP_AWB_ELLIP3_RMAX */
  9951. /*****************************************************************************/
  9952. /**
  9953. * register: awb_meas_ellip4_rmax: Ellipse 4 r_max (0x00000114)
  9954. *
  9955. *****************************************************************************/
  9956. /* Slice: ellip4_rmax:*/
  9957. /* Ellipse 4 max radius square compare value */
  9958. #ifdef ISP_AWB_ELLIP4_RMAX
  9959. #endif /* ISP_AWB_ELLIP4_RMAX */
  9960. /*****************************************************************************/
  9961. /**
  9962. * register: awb_meas_ellip5_rmax: Ellipse 5 r_max (0x00000118)
  9963. *
  9964. *****************************************************************************/
  9965. /* Slice: ellip5_rmax:*/
  9966. /* Ellipse 5 max radius square compare value */
  9967. #ifdef ISP_AWB_ELLIP5_RMAX
  9968. #endif /* ISP_AWB_ELLIP5_RMAX */
  9969. /*****************************************************************************/
  9970. /**
  9971. * register: awb_meas_ellip6_rmax: Ellipse 6 r_max (0x0000011c)
  9972. *
  9973. *****************************************************************************/
  9974. /* Slice: ellip6_rmax:*/
  9975. /* Ellipse 6 max radius square compare value */
  9976. #ifdef ISP_AWB_ELLIP6_RMAX
  9977. #endif /* ISP_AWB_ELLIP6_RMAX */
  9978. /*****************************************************************************/
  9979. /**
  9980. * register: awb_meas_ellip7_rmax: Ellipse 7 r_max (0x00000120)
  9981. *
  9982. *****************************************************************************/
  9983. /* Slice: ellip7_rmax:*/
  9984. /* Ellipse 7 max radius square compare value */
  9985. #ifdef ISP_AWB_ELLIP7_RMAX
  9986. #endif /* ISP_AWB_ELLIP7_RMAX */
  9987. /*****************************************************************************/
  9988. /**
  9989. * register: awb_meas_ellip8_rmax: Ellipse 8 r_max (0x00000124)
  9990. *
  9991. *****************************************************************************/
  9992. /* Slice: ellip8_rmax:*/
  9993. /* Ellipse 8 max radius square compare value */
  9994. #ifdef ISP_AWB_ELLIP8_RMAX
  9995. #endif /* ISP_AWB_ELLIP8_RMAX */
  9996. /*****************************************************************************/
  9997. /**
  9998. * register: awb_meas_counter_1: AWB Counter 1 (0x00000128)
  9999. *
  10000. *****************************************************************************/
  10001. /* Slice: count_1:*/
  10002. /* counted Pixels of Ellipse 1 */
  10003. #ifdef ISP_AWB_COUNT_1
  10004. #endif /* ISP_AWB_COUNT_1 */
  10005. /*****************************************************************************/
  10006. /**
  10007. * register: awb_meas_counter_2: AWB Counter 2 (0x0000012c)
  10008. *
  10009. *****************************************************************************/
  10010. /* Slice: count_2:*/
  10011. /* counted Pixels of Ellipse 2 */
  10012. #ifdef ISP_AWB_COUNT_2
  10013. #endif /* ISP_AWB_COUNT_2 */
  10014. /*****************************************************************************/
  10015. /**
  10016. * register: awb_meas_counter_3: AWB Counter 3 (0x00000130)
  10017. *
  10018. *****************************************************************************/
  10019. /* Slice: count_3:*/
  10020. /* counted Pixels of Ellipse 3 */
  10021. #ifdef ISP_AWB_COUNT_3
  10022. #endif /* ISP_AWB_COUNT_3 */
  10023. /*****************************************************************************/
  10024. /**
  10025. * register: awb_meas_counter_4: AWB Counter 4 (0x00000134)
  10026. *
  10027. *****************************************************************************/
  10028. /* Slice: count_4:*/
  10029. /* counted Pixels of Ellipse 4 */
  10030. #ifdef ISP_AWB_COUNT_4
  10031. #endif /* ISP_AWB_COUNT_4 */
  10032. /*****************************************************************************/
  10033. /**
  10034. * register: awb_meas_counter_5: AWB Counter 5 (0x00000138)
  10035. *
  10036. *****************************************************************************/
  10037. /* Slice: count_5:*/
  10038. /* counted Pixels of Ellipse 5 */
  10039. #ifdef ISP_AWB_COUNT_5
  10040. #endif /* ISP_AWB_COUNT_5 */
  10041. /*****************************************************************************/
  10042. /**
  10043. * register: awb_meas_counter_6: AWB Counter 6 (0x0000013c)
  10044. *
  10045. *****************************************************************************/
  10046. /* Slice: count_6:*/
  10047. /* counted Pixels of Ellipse 6 */
  10048. #ifdef ISP_AWB_COUNT_6
  10049. #endif /* ISP_AWB_COUNT_6 */
  10050. /*****************************************************************************/
  10051. /**
  10052. * register: awb_meas_counter_7: AWB Counter 7 (0x00000140)
  10053. *
  10054. *****************************************************************************/
  10055. /* Slice: count_7:*/
  10056. /* counted Pixels of Ellipse 7 */
  10057. #ifdef ISP_AWB_COUNT_7
  10058. #endif /* ISP_AWB_COUNT_7 */
  10059. /*****************************************************************************/
  10060. /**
  10061. * register: awb_meas_counter_8: AWB Counter 8 (0x00000144)
  10062. *
  10063. *****************************************************************************/
  10064. /* Slice: count_8:*/
  10065. /* counted Pixels of Ellipse 8 */
  10066. #ifdef ISP_AWB_COUNT_8
  10067. #endif /* ISP_AWB_COUNT_8 */
  10068. /*****************************************************************************/
  10069. /**
  10070. * register array: awb_meas_accu: AWB Accu Read (0x298 + n*0x4 (n=0..23))
  10071. *
  10072. *****************************************************************************/
  10073. /* Slice: read_accu:*/
  10074. /* measured sum[34:3] of RGB values.*/
  10075. #ifdef ISP_AWB_READ_ACCU
  10076. #endif /* ISP_AWB_READ_ACCU */
  10077. #ifdef EE_CTRL_ENABLE
  10078. #define EE_CTRL_ENABLE_SET 1
  10079. #define EE_CTRL_ENABLE_CLEAR 0
  10080. #endif
  10081. /*****************************************************************************/
  10082. /**
  10083. * register array: awb_meas_accu: AWB Accu Read (0x298 + n*0x4 (n=0..23))
  10084. *
  10085. *****************************************************************************/
  10086. /* Slice: read_accu:*/
  10087. /* measured sum[34:3] of RGB values.*/
  10088. #ifdef ISP_VSM_DELTA_H
  10089. #endif /* ISP_AWB_READ_ACCU */
  10090. /*****************************************************************************/
  10091. /**
  10092. * register: isp_vsm_h_offs: VSM window horizontal offset
  10093. *
  10094. *****************************************************************************/
  10095. /* Slice: vsm_h_offset:*/
  10096. /* Horizontal offset in pixels.*/
  10097. #ifdef ISP_VSM_H_OFFSET
  10098. #define ISP_VSM_H_OFFSET_MAX (ISP_VSM_H_OFFSET_MASK >> ISP_VSM_H_OFFSET_SHIFT)
  10099. #endif /* ISP_VSM_H_OFFSET */
  10100. /*****************************************************************************/
  10101. /**
  10102. * register: isp_vsm_v_offs: VSM window vertical offset
  10103. *
  10104. *****************************************************************************/
  10105. /* Slice: vsm_v_offset:*/
  10106. /* Vertical offset in pixels.*/
  10107. #ifdef ISP_VSM_V_OFFSET
  10108. #define ISP_VSM_V_OFFSET_MAX (ISP_VSM_V_OFFSET_MASK >> ISP_VSM_V_OFFSET_SHIFT)
  10109. #endif /* ISP_VSM_V_OFFSET */
  10110. /*****************************************************************************/
  10111. /**
  10112. * register: isp_vsm_h_size: Horizontal measure window size
  10113. *
  10114. *****************************************************************************/
  10115. /* Slice: vsm_h_size:*/
  10116. /* Horizontal size in pixels..*/
  10117. #ifdef ISP_VSM_H_SIZE
  10118. /* note: do not apply shift, since bit 0 is only excluded to get even values */
  10119. #define ISP_VSM_H_SIZE_MAX ISP_VSM_H_SIZE_MASK
  10120. #endif /* ISP_VSM_H_SIZE */
  10121. /*****************************************************************************/
  10122. /**
  10123. * register: isp_vsm_v_size: Vertical measure window size
  10124. *
  10125. *****************************************************************************/
  10126. /* Slice: vsm_v_size:*/
  10127. /* Vertical size in pixels.*/
  10128. #ifdef ISP_VSM_V_SIZE
  10129. /* note: do not apply shift, since bit 0 is only excluded to get even values */
  10130. #define ISP_VSM_V_SIZE_MAX ISP_VSM_V_SIZE_MASK
  10131. #endif /* ISP_VSM_V_SIZE */
  10132. /*****************************************************************************/
  10133. /**
  10134. * register: isp_vsm_h_segments: Iteration 1 horizontal segments
  10135. *
  10136. *****************************************************************************/
  10137. /* Slice: vsm_h_segments:*/
  10138. /* number of 16 point wide segments enclosed by the first iteration sample */
  10139. /* points in horizontal direction. Range: 1 ... 128 */
  10140. #ifdef ISP_VSM_H_SEGMENTS
  10141. #define ISP_VSM_H_SEGMENTS_MIN 1
  10142. #define ISP_VSM_H_SEGMENTS_MAX 128
  10143. #endif /* ISP_VSM_H_SEGMENTS */
  10144. /*****************************************************************************/
  10145. /**
  10146. * register: isp_vsm_v_segments: Iteration 1 vertical segments
  10147. *
  10148. *****************************************************************************/
  10149. /* Slice: vsm_v_segments:*/
  10150. /* number of 16 point wide segments enclosed by the first iteration sample */
  10151. /* points in vertical direction. Range: 1 ... 128 */
  10152. /* Note: number of 1st iteration sample points = vsm_v_segments + 1.*/
  10153. /* vsm_v_segments must be equal or smaller than vsm_h_segments.*/
  10154. #ifdef ISP_VSM_V_SEGMENTS
  10155. #define ISP_VSM_V_SEGMENTS_MIN 1
  10156. #define ISP_VSM_V_SEGMENTS_MAX 128
  10157. #endif /* ISP_VSM_V_SEGMENTS */
  10158. #ifdef ISP_GCMONO
  10159. /*****************************************************************************/
  10160. /**
  10161. * register: isp_gcmono_ctrl: gcmono enable and lut table cfg
  10162. *
  10163. *****************************************************************************/
  10164. /*! Slice: mono_gc_enable */
  10165. /*! Control of gamma correction for mono sensor RAW data */
  10166. /*! 1'b0: disable GC and enter bypass mode */
  10167. /*! 1'b1: enable GC mode */
  10168. #ifdef ISP_GCMONO_SWITCH
  10169. #define ISP_GCMONO_SWITCH_DISABLE 0 /* 0: disable GC */
  10170. #define ISP_GCMONO_SWITCH_ENABLE 1 /* 1: enable GC */
  10171. #endif
  10172. /*! Slice: mono_gc_cfg_done */
  10173. /*! To notify the ISP HW the LUT configuration is done, ready to use, active high.*/
  10174. /*! Writing ZERO reset teh internal read/write pointer and also indicates that the LUT can be configured or read from CPU.*/
  10175. #ifdef ISP_GCMONO_CFG_DONE
  10176. #define ISP_GCMONO_CFG_DONE_CURVE_READY 1 /* 1: notify ISP HW LUT configuration is done */
  10177. #define ISP_GCMONO_CFG_DONE_SET_CURVE 0 /* 0: Write ZERO reset the internal pointer and can cfg LUT. */
  10178. #endif
  10179. #ifdef ISP_GCMONO_PARA_BASE
  10180. #endif
  10181. #endif
  10182. /*****************************************************************************/
  10183. /* MIV2 Registers */
  10184. /*****************************************************************************/
  10185. /*****************************************************************************/
  10186. /**
  10187. * register: miv2_mp_fmt: main path pixel format control register (0x1314)
  10188. *
  10189. *****************************************************************************/
  10190. // Slice: MP_WR_JDP_FMT
  10191. // 1: JPEG
  10192. // 0: DPCC
  10193. #ifdef MP_WR_JDP_FMT
  10194. #define MIV2_MP_WRITE_FORMAT_DPCC 0 //DPCC
  10195. #define MIV2_MP_WRITE_FORMAT_JPEG 1 //JPEG
  10196. #endif /* MP_WR_JDP_FMT */
  10197. // Slice: MP_WR_YUV_BIT:
  10198. // 1: 10bit YUV/RGB
  10199. // 0: 8bit YUV/RGB
  10200. #ifdef MP_WR_YUV_BIT
  10201. #define MIV2_MP_WRITE_FORMAT_8BIT 0 //8bit YUV/RGB
  10202. #define MIV2_MP_WRITE_FORMAT_10BIT 1 //10bit YUV/RGB
  10203. #endif /* MP_WR_YUV_BIT */
  10204. // Slice: MP_WR_YUV_FMT:
  10205. #ifdef MP_WR_YUV_FMT
  10206. #define MIV2_MP_WRITE_FORMAT_YUV420 0 // 00: YUV420
  10207. #define MIV2_MP_WRITE_FORMAT_YUV422 1 // 01: YUV422
  10208. #define MIV2_MP_WRITE_FORMAT_YUV444 2 // 10: YUV444
  10209. #endif /* MP_WR_YUV_FMT */
  10210. // Slice: MP_WR_YUV_STR:
  10211. #ifdef MP_WR_YUV_STR
  10212. #define MIV2_MP_WRITE_STRIDE_SEMIPLANAR 0 // 00: YUV/RGB SemiPlanar
  10213. #define MIV2_MP_WRITE_STRIDE_INTERLEAVE 1 // 01: YUV Interleave, RGB Raster
  10214. #define MIV2_MP_WRITE_STRIDE_PLANAR 2 // 10: YUV/RGB Planar
  10215. #endif /* MP_WR_YUV_STR */
  10216. // Slice: MP_WR_RAW_BIT:
  10217. #ifdef MP_WR_RAW_BIT
  10218. #define MIV2_MP_WRITE_FORMAT_RAW8 0 // 000: RAW8
  10219. #define MIV2_MP_WRITE_FORMAT_RAW10 1 // 001: RAW10
  10220. #define MIV2_MP_WRITE_FORMAT_RAW12 2 // 010: RAW12
  10221. #define MIV2_MP_WRITE_FORMAT_RAW14 3 // 011: RAW14
  10222. #define MIV2_MP_WRITE_FORMAT_RAW16 4 // 100: RAW16
  10223. #define MIV2_MP_WRITE_FORMAT_RAW20 5 // 101: RAW20
  10224. #endif /* MP_WR_RAW_BIT */
  10225. // Slice: MP_WR_YUV_ALIGNED
  10226. // 1: aligned
  10227. // 0: unaligned
  10228. #ifdef MP_WR_YUV_ALIGNED
  10229. #define MIV2_MP_WRITE_YUV_UNALIGNED 0 //unaligned
  10230. #define MIV2_MP_WRITE_YUV_ALIGNED 1 //aligned
  10231. #endif /* MP_WR_YUV_ALIGNED */
  10232. // Slice: MP_WR_RAW_ALIGNED:
  10233. #ifdef MP_WR_RAW_ALIGNED
  10234. #define MIV2_MP_WRITE_RAW_UNALIGNED 0 // 00: unaligned
  10235. #define MIV2_MP_WRITE_RAW_ALIGNED_MODE1 1 // 01: aligned mode1
  10236. #define MIV2_MP_WRITE_RAW_ALIGNED_MODE2 2 // 10: aligned mode2
  10237. #endif /* MP_WR_RAW_ALIGNED */
  10238. // Slice: MP_WR_YUV_NV21
  10239. // 1: Put U before V
  10240. // 0: Put V before U
  10241. #ifdef MP_WR_YUV_NV21
  10242. #define MIV2_MP_WRITE_YUV_NV21_UV 0 //Put U before V
  10243. #define MIV2_MP_WRITE_YUV_NV21_VU 1 //Put V before U
  10244. #endif /* MP_WR_YUV_NV21 */
  10245. // Slice: MP_WR_YUV_NVY:
  10246. #ifdef MP_WR_YUV_NVY
  10247. #define MIV2_MP_WRITE_YUV_NVY_YC1C2 0 // 00: Put Y first => YC1C2
  10248. #define MIV2_MP_WRITE_YUV_NVY_C1YC2 1 // 01: Put Y second => C1YC2
  10249. #define MIV2_MP_WRITE_YUV_NVY_C1C2Y 2 // 10: Put Y Third => C1C2Y
  10250. #endif /* MP_WR_YUV_NVY */
  10251. // =========================================================================================
  10252. #ifdef ISP_DEMOSAIC_DENOISE_STRENGTH
  10253. #define ISP_DEMOSAIC_DENOISE_STRENGTH_MIN 0
  10254. #define ISP_DEMOSAIC_DENOISE_STRENGTH_MAX 32
  10255. #endif
  10256. #ifdef ISP_DEMOSAIC_SHARPEN_SIZE
  10257. #define ISP_DEMOSAIC_SHARPEN_SIZE_MIN 0
  10258. #define ISP_DEMOSAIC_SHARPEN_SIZE_MAX 16
  10259. #endif
  10260. #ifdef ISP_DMSC_DEMOIRE_AREA_THR
  10261. #define ISP_DMSC_DEMOIRE_AREA_THR_MIN 0
  10262. #define ISP_DMSC_DEMOIRE_AREA_THR_MAX 32
  10263. #endif
  10264. #ifdef ISP_DMSC_DEMOIRE_SAT_SHRINK
  10265. #define ISP_DMSC_DEMOIRE_SAT_SHRINK_MIN 0
  10266. #define ISP_DMSC_DEMOIRE_SAT_SHRINK_MAX 32
  10267. #endif
  10268. #ifdef ISP_DMSC_SHARPEN_T4_SHIFT
  10269. #define ISP_DMSC_SHARPEN_SHIFT_MIN 0
  10270. #define ISP_DMSC_SHARPEN_SHIFT_MAX 11
  10271. #endif
  10272. #ifdef ISP_DMSC_SHARPEN_LINE_SHIFT1
  10273. #define ISP_DMSC_SHARPEN_LINE_SHIFT1_MIN 0
  10274. #define ISP_DMSC_SHARPEN_LINE_SHIFT1_MAX 10
  10275. #endif
  10276. #ifdef ISP_DMSC_HF_FILT_00
  10277. #define ISP_DMSC_HF_FILT_MIN 0
  10278. #define ISP_DMSC_HF_FILT_MAX 34
  10279. #endif
  10280. #ifdef ISP_DMSC_CBCR_MODE
  10281. #define ISP_DMSC_CBCR_MODE_MIN 0
  10282. #define ISP_DMSC_CBCR_MODE_MAX 3
  10283. #endif
  10284. #ifdef ISP_DMSC_DEPURPLE_SAT_SHRINK
  10285. #define ISP_DMSC_DEPURPLE_SAT_SHRINK_MIN 0
  10286. #define ISP_DMSC_DEPURPLE_SAT_SHRINK_MAX 8
  10287. #endif
  10288. #ifdef ISP_DMSC_X_NF
  10289. #define ISP_DMSC_X_NF_MIN 0
  10290. #define ISP_DMSC_X_NF_MAX 31
  10291. #endif
  10292. #ifdef ISP_DMSC_X_NS
  10293. #define ISP_DMSC_X_NS_MIN 0
  10294. #define ISP_DMSC_X_NS_MAX 15
  10295. #endif
  10296. #ifdef ISP_DMSC_Y_NF
  10297. #define ISP_DMSC_Y_NF_MIN 0
  10298. #define ISP_DMSC_Y_NF_MAX 31
  10299. #endif
  10300. #ifdef ISP_DMSC_Y_NS
  10301. #define ISP_DMSC_Y_NS_MIN 0
  10302. #define ISP_DMSC_Y_NS_MAX 15
  10303. #endif
  10304. /* =========================================================================================*/
  10305. /*! returns the value of slice \a name from register or variable \a reg
  10306. * \note "parameter" \a reg could be a hardware register or a (32bit) variable, but not a pointer! \n
  10307. * each slice (specified as "parameter" \a name) requires two \#defines: \n
  10308. * - <tt>\<name\>_MASK </tt>: defines the mask to use on register side
  10309. * - <tt>\<name\>_SHIFT </tt>: defines the shift value to use (left on write, right on read)
  10310. */
  10311. #define REG_GET_SLICE(reg, name) \
  10312. (((reg) & (name##_MASK)) >> (name##_SHIFT))
  10313. /* =========================================================================================*/
  10314. /*! writes the value \a value into slice \a name of register or variable \a reg
  10315. * \note "parameter" \a reg could be a hardware register or a (32bit) variable, but not a pointer! \n
  10316. * each slice (specified as "parameter" \a name) requires two \#defines: \n
  10317. * - <tt>\<name\>_MASK </tt>: defines the mask to use on register side
  10318. * - <tt>\<name\>_SHIFT </tt>: defines the shift value to use (left on write, right on read)
  10319. */
  10320. #define REG_SET_SLICE(reg, name, value) \
  10321. { \
  10322. ((reg) = (((reg) & ~(name##_MASK)) | (((value) << (name##_SHIFT)) & (name##_MASK))));\
  10323. }
  10324. #endif /* __MRV_ALL_BITS_H__ */