isp_tdnr3.c 24 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. #ifdef __KERNEL__
  54. #include <linux/io.h>
  55. #include <linux/module.h>
  56. #endif
  57. #include "isp_ioctl.h"
  58. #include "mrv_all_bits.h"
  59. #include "isp_types.h"
  60. #ifdef ISP_3DNR_V3
  61. extern MrvAllRegister_t *all_regs;
  62. int isp_tdnr_cfg_gamma(struct isp_ic_dev *dev)
  63. {
  64. //write to regs
  65. struct isp_tdnr_context *tdnr = &dev->tdnr;
  66. u32 regVal;
  67. u8 bit_width;
  68. u8 i;
  69. u16 val_a, val_b;
  70. //const u8 tdnrRegGap = 8;
  71. bit_width = 12;
  72. //pr_info("enter %s\n", __func__);
  73. for (i = 0; i < DENOISE3D_GAMMA_BIN - 3; i += 5)
  74. {
  75. val_a = tdnr->curve.preGamma_y[i + 2] >> 6; val_b = tdnr->curve.preGamma_y[i + 2] & 0x3f;
  76. regVal = (val_a << 24) | ((tdnr->curve.preGamma_y[i + 1] & 0xfff) << bit_width) | (tdnr->curve.preGamma_y[i] & 0xfff);
  77. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_pregamma_y_0) + (i / 5) *8 , regVal);
  78. regVal = (val_b << 24) | ((tdnr->curve.preGamma_y[i + 4] & 0xfff) << bit_width) | (tdnr->curve.preGamma_y[i + 3] & 0xfff);
  79. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_pregamma_y_1) + (i / 5 ) *8, regVal);
  80. }
  81. val_a = tdnr->curve.preGamma_y[i + 2] >> 6; val_b = tdnr->curve.preGamma_y[i + 2] & 0x3f;
  82. regVal = (val_a << 24) | ((tdnr->curve.preGamma_y[i + 1] & 0xfff) << bit_width) | (tdnr->curve.preGamma_y[i] & 0xfff);
  83. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_pregamma_y_12), regVal);
  84. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_pregamma_y_13), val_b);
  85. i = 0;
  86. for (i = 0; i < DENOISE3D_GAMMA_BIN - 3; i += 5)
  87. {
  88. val_a = tdnr->curve.invGamma_y[i + 2] >> 6; val_b = tdnr->curve.invGamma_y[i + 2] & 0x3f;
  89. regVal = (val_a << 24) | ((tdnr->curve.invGamma_y[i + 1] & 0xfff) << bit_width) | (tdnr->curve.invGamma_y[i] & 0xfff);
  90. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_invgamma_y_0) + (i / 5) *8 , regVal);
  91. regVal = (val_b << 24) | ((tdnr->curve.invGamma_y[i + 4] & 0xfff) << bit_width) | (tdnr->curve.invGamma_y[i + 3] & 0xfff);
  92. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_invgamma_y_1) + (i / 5) *8 , regVal);
  93. }
  94. val_a = tdnr->curve.invGamma_y[i + 2] >> 6; val_b = tdnr->curve.invGamma_y[i + 2] & 0x3f;
  95. regVal = (val_a << 24) | ((tdnr->curve.invGamma_y[i + 1] & 0xfff) << bit_width) | (tdnr->curve.invGamma_y[i] & 0xfff);
  96. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_invgamma_y_12), regVal);
  97. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_invgamma_y_13), val_b);
  98. return 0;
  99. }
  100. int isp_s_tdnr(struct isp_ic_dev *dev)
  101. {
  102. u32 isp_denoise3d2_ctrl;
  103. struct isp_tdnr_context *tdnr = &dev->tdnr;
  104. u32 regVal = 0;
  105. /* spacial */
  106. u32 strength = tdnr->strength;
  107. //pr_info("enter %s\n", __func__);
  108. strength = MIN(MAX(strength, 0), 128);
  109. isp_denoise3d2_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  110. #if 0
  111. if (!tdnr->enable) {
  112. REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_ENABLE, 0);
  113. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), isp_denoise3d2_ctrl);
  114. return 0;
  115. }
  116. #endif
  117. #if 1
  118. if (dev->tdnr.enable_tnr) {
  119. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), strength);
  120. } else {
  121. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), 0);
  122. if (dev->tdnr.frames == 2)
  123. return 0 ;
  124. }
  125. #endif
  126. //isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), strength);
  127. regVal = 0;
  128. REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_LEVEL, tdnr->noise_level);
  129. REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_MEAN, tdnr->noise_mean);
  130. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_noise), regVal);
  131. regVal = 0;
  132. REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_LEVEL, tdnr->noise_threshold);
  133. REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_MEAN, tdnr->motion_mean);
  134. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_motion), regVal);
  135. regVal = 0;
  136. REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_RANGE_H, tdnr->range_h);
  137. REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_RANGE_V, tdnr->range_v);
  138. REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_DILATE_RANGE_H, tdnr->dilate_range_h);
  139. REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_DILATE_RANGE_V, tdnr->dilate_range_v);
  140. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_range), regVal);
  141. regVal = 0;
  142. REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_INV, tdnr->motion_inv_factor);
  143. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_motion_inv), regVal);
  144. regVal = 0;
  145. REG_SET_SLICE(regVal, DENOISE3D_V20_THR_UPDATE, tdnr->update_factor);
  146. REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_THR_UPDATE, tdnr->motion_update_factor);
  147. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_update), regVal);
  148. regVal = 0;
  149. REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_PRE_WEIGHT, tdnr->pre_motion_weight);
  150. REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_SLOPE, tdnr->motion_slope);
  151. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_tnr), regVal);
  152. regVal = 0;
  153. REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_CONV_SHIFT, tdnr->motion_converage_shift);
  154. REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_CONV_MAX, tdnr->motion_converage_max);
  155. REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_VAL_SHIFT_BIT, tdnr->tnr_val_shift_bit);
  156. REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_DIFF_NORM_SHIFT_BIT, tdnr->tnr_diff_shift_bit);
  157. REG_SET_SLICE(regVal, DENOISE3D_V20_SAD_WEIGHT, tdnr->sad_weight);
  158. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_shift), regVal);
  159. regVal = 0;
  160. REG_SET_SLICE(regVal, DENOISE3D_V20_PIXEL_VAL_SHIFT, tdnr->luma_pixel_val_shift);
  161. REG_SET_SLICE(regVal, DENOISE3D_V20_PIXEL_SLOP, tdnr->luma_pixel_slope);
  162. REG_SET_SLICE(regVal, DENOISE3D_V20_PIXEL_SLOP_SHIFT_BIT, tdnr->luma_pixel_slope_shift);
  163. REG_SET_SLICE(regVal, DENOISE3D_V20_PIXEL_SLOP_MIN, tdnr->luma_pixel_slope_min);
  164. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_luma), regVal);
  165. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_dummy_hblank), 0x63);
  166. REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_INVGAMMA_EN, tdnr->enable_inv_gamma);
  167. REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_PREGAMMA_EN, tdnr->enable_pre_gamma);
  168. REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_ERODE_EN, tdnr->enable_motion_erosion);
  169. REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_MOTION_CONV_EN, tdnr->enable_motion_converage);
  170. REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_INV_DGAIN_EN, 0);
  171. REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_INV_AWB_GAIN_EN, 1);
  172. REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_COMP_LUMA_EN, 0);
  173. REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_MOTION_DILATE_ENABLE, tdnr->enable_motion_dilation);
  174. REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_NLM_ENABLE, dev->tdnr.enable_2dnr);
  175. //REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_NLM_ENABLE, 1);
  176. REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_TNR_ENABLE, dev->tdnr.enable_tnr);
  177. if (!dev->tdnr.enable_tnr) {
  178. REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_REF_RESET, 1);
  179. }
  180. REG_SET_SLICE(isp_denoise3d2_ctrl, DENOISE3D_V20_ENABLE, 1);
  181. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), isp_denoise3d2_ctrl);
  182. return 0;
  183. }
  184. int isp_tdnr_set_strength(struct isp_ic_dev *dev)
  185. {
  186. u32 isp_denoise3d2_strength;
  187. struct isp_tdnr_context *tdnr = &dev->tdnr;
  188. //pr_info("enter %s\n", __func__);
  189. isp_denoise3d2_strength = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_strength));
  190. REG_SET_SLICE(isp_denoise3d2_strength, DENOISE3D_V20_TNR_STRENGTH, tdnr->strength);
  191. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), isp_denoise3d2_strength);
  192. return 0;
  193. }
  194. int isp_tdnr_set_motion(struct isp_ic_dev *dev)
  195. {
  196. struct isp_tdnr_context *tdnr = &dev->tdnr;
  197. u32 isp_denoise3d2_motion_inv;
  198. pr_info("enter %s\n", __func__);
  199. isp_denoise3d2_motion_inv = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_motion_inv));
  200. REG_SET_SLICE(isp_denoise3d2_motion_inv, DENOISE3D_V20_MOTION_INV, tdnr->motion_inv_factor);
  201. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_motion_inv), isp_denoise3d2_motion_inv);
  202. return 0;
  203. }
  204. int isp_tdnr_enable(struct isp_ic_dev *dev)
  205. {
  206. u32 regVal = 0;
  207. u32 strength = dev->tdnr.strength;
  208. pr_info("enter %s\n", __func__);
  209. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  210. REG_SET_SLICE(regVal, DENOISE3D_V20_ENABLE, 1);
  211. // REG_SET_SLICE(regVal, DENOISE3D_V20_REF_RESET, 1);
  212. REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_ENABLE, 1);
  213. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal);
  214. strength = MIN(MAX(strength, 0), 128);
  215. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), strength); //clear strength
  216. dev->tdnr.enable = true;
  217. return 0;
  218. }
  219. int isp_tdnr_disable(struct isp_ic_dev *dev)
  220. {
  221. u32 regVal = 0;
  222. pr_info("enter %s\n", __func__);
  223. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  224. // REG_SET_SLICE(regVal, DENOISE3D_V20_ENABLE, 0);
  225. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal);
  226. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_strength), 0); //clear strength
  227. dev->tdnr.enable = false;
  228. return 0;
  229. }
  230. int isp_tdnr_enable_tdnr(struct isp_ic_dev *dev)
  231. {
  232. u32 regVal = 0;
  233. pr_info("enter %s\n", __func__);
  234. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  235. REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_ENABLE, 1);
  236. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal);
  237. dev->tdnr.enable_tnr= true;
  238. return 0;
  239. }
  240. int isp_tdnr_disable_tdnr(struct isp_ic_dev *dev)
  241. {
  242. u32 regVal = 0;
  243. pr_info("enter %s\n", __func__);
  244. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  245. REG_SET_SLICE(regVal, DENOISE3D_V20_TNR_ENABLE, 0);
  246. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal);
  247. dev->tdnr.enable = false;
  248. return 0;
  249. }
  250. int isp_tdnr_enable_2dnr(struct isp_ic_dev *dev)
  251. {
  252. //u32 regVal = 0;
  253. pr_info("enter %s\n", __func__);
  254. /*regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  255. REG_SET_SLICE(regVal, DENOISE3D_V20_NLM_ENABLE, 1);
  256. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal);*/
  257. dev->tdnr.enable_tnr= true;
  258. return 0;
  259. }
  260. int isp_tdnr_disable_2dnr(struct isp_ic_dev *dev)
  261. {
  262. //u32 regVal = 0;
  263. pr_info("enter %s\n", __func__);
  264. /*regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  265. REG_SET_SLICE(regVal, DENOISE3D_V20_NLM_ENABLE, 0);
  266. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl), regVal);*/
  267. dev->tdnr.enable = false;
  268. return 0;
  269. }
  270. int isp_tdnr_g_stats(struct isp_ic_dev *dev, struct isp_tdnr_stats *stats)
  271. {
  272. //pr_info("enter %s\n", __func__);
  273. if (!dev || !stats) {
  274. return -EINVAL;
  275. }
  276. stats->bg_sum = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_bg_val_sum));
  277. stats->motion_sum = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_mo_val_sum));
  278. stats->bg_pixel_cnt = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_bg_cnt));
  279. stats->motion_pixel_cnt = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_mo_cnt));
  280. stats->frame_avg = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_frame_avg));
  281. return 0;
  282. }
  283. int isp_tdnr_u_noise(struct isp_ic_dev *dev)
  284. {
  285. u32 regVal = 0;
  286. struct isp_tdnr_context *tdnr = &dev->tdnr;
  287. pr_info("enter %s\n", __func__);
  288. regVal = 0;
  289. REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_LEVEL, tdnr->noise_level);
  290. REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_MEAN, tdnr->noise_mean);
  291. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_noise), regVal);
  292. regVal = 0;
  293. REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_LEVEL, tdnr->noise_threshold);
  294. REG_SET_SLICE(regVal, DENOISE3D_V20_NOISE_MEAN, tdnr->motion_mean);
  295. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_motion), regVal);
  296. return 0;
  297. }
  298. int isp_tdnr_u_thr(struct isp_ic_dev *dev)
  299. {
  300. u32 regVal = 0;
  301. struct isp_tdnr_context *tdnr = &dev->tdnr;
  302. pr_info("enter %s\n", __func__);
  303. regVal = 0;
  304. REG_SET_SLICE(regVal, DENOISE3D_V20_THR_UPDATE, tdnr->update_factor);
  305. REG_SET_SLICE(regVal, DENOISE3D_V20_MOTION_THR_UPDATE, tdnr->motion_update_factor);
  306. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_update), regVal);
  307. return 0;
  308. }
  309. int isp_tdnr_s_buf(struct isp_ic_dev *dev)
  310. {
  311. struct isp_tdnr_buffer* buf = &dev->tdnr.buf;
  312. u32 in_width, in_height;
  313. u32 size, lval;
  314. u32 miv2_sp2_bus_id ;
  315. u32 miv2_sp2_fmt;
  316. u32 miv2_imsc2;
  317. u32 miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl));
  318. u32 miv2_imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc));
  319. u32 miv2_sp2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_sp2_ctrl));
  320. u32 isp_mi_sp2_raw2_ctrl = isp_read_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl));
  321. pr_info("enter %s\n", __func__);
  322. /*
  323. ENABLE MIV2 SP2 RAW1 RAW2 WRITE/READ
  324. */
  325. REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_PATH_ENABLE, 1);
  326. REG_SET_SLICE(miv2_ctrl, SP2_RAW_PATH_ENABLE, 1);
  327. miv2_ctrl |= 0x00100000; // sp2_raw2_path_enable
  328. isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl);
  329. in_width = isp_read_reg(dev, REG_ADDR(isp_out_h_size));
  330. in_height = isp_read_reg(dev, REG_ADDR(isp_out_v_size));
  331. lval = (in_width * 12 + 127)/ 128;
  332. lval <<= 4;
  333. size = in_height * lval; //raw12 unaligned
  334. //write reference frame config
  335. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_base_ad_init), buf->pa_refer);
  336. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_size_init), size);
  337. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_offs_cnt_init), 0);
  338. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_llength), lval);
  339. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_width), in_width);
  340. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_height), in_height);
  341. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_size), size);
  342. isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_start_ad), buf->pa_refer);
  343. isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_width), in_width);
  344. isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_llength), lval);
  345. isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_lval), lval);
  346. isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_size), size);
  347. in_width /= 2;
  348. in_height /= 2;
  349. lval = (in_width); // RAW8 output
  350. size = in_height * lval;
  351. pr_info("%s 0x%08x\n", __func__, REG_ADDR(isp_mi_sp2_raw2_base_ad_init));
  352. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_base_ad_init), buf->pa_motion);
  353. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_size_init), size);
  354. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_offs_cnt_init), 0);
  355. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_llength), lval);
  356. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_pic_width), in_width);
  357. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_pic_height), in_height);
  358. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_pic_size), size);
  359. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_start_ad), buf->pa_motion);
  360. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_width), in_width);
  361. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_llength), lval);
  362. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_lval), lval); // align to 128
  363. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_size), size);
  364. #if 0
  365. isp_write_reg(dev, 0x5620, buf->pa_motion);
  366. isp_write_reg(dev, 0x5624, size);
  367. isp_write_reg(dev, 0x5628, 0);
  368. isp_write_reg(dev, 0x562c, lval);
  369. isp_write_reg(dev, 0x5630, in_width);
  370. isp_write_reg(dev, 0x5634, in_height);
  371. isp_write_reg(dev, 0x5638, size);
  372. isp_write_reg(dev, 0x5660, buf->pa_motion);
  373. isp_write_reg(dev, 0x5664, in_width);
  374. isp_write_reg(dev, 0x5668, lval);
  375. isp_write_reg(dev, 0x5680, lval); // align to 128
  376. isp_write_reg(dev, 0x566c, size);
  377. #endif
  378. miv2_sp2_bus_id = isp_read_reg(dev, REG_ADDR(miv2_sp2_bus_id));
  379. REG_SET_SLICE(miv2_sp2_bus_id, SP2_WR_ID_EN, 1);
  380. REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_ID_EN, 1);
  381. REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_BURST_LEN, 2); //sp2 rd burst lenghth 16
  382. REG_SET_SLICE(miv2_sp2_bus_id, SP2_BUS_SW_EN, 1);
  383. isp_write_reg(dev, REG_ADDR(miv2_sp2_bus_id), miv2_sp2_bus_id);
  384. miv2_sp2_fmt = isp_read_reg(dev, REG_ADDR(miv2_sp2_fmt));
  385. REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_BIT, 2); //raw12
  386. REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_ALIGNED, 0); //unaligned
  387. REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_BIT, 2); //raw12
  388. REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_ALIGNED, 0); //unaligned
  389. isp_write_reg(dev, REG_ADDR(miv2_sp2_fmt), miv2_sp2_fmt);
  390. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_fmt), 0);
  391. REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_CFG_UPDATE, 1);
  392. //REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_AUTO_UPDATE, 1);
  393. REG_SET_SLICE(miv2_sp2_ctrl, SP2_MI_CFG_UPD, 1);
  394. REG_SET_SLICE(miv2_sp2_ctrl, SP2_AUTO_UPDATE, 1);
  395. miv2_sp2_ctrl |= (SP2_INIT_BASE_EN_MASK | SP2_INIT_OFFSET_EN_MASK);
  396. //miv2_sp2_ctrl |= 0x2fa;
  397. isp_write_reg(dev, REG_ADDR(miv2_sp2_ctrl), miv2_sp2_ctrl);
  398. isp_mi_sp2_raw2_ctrl |= 0x23a;
  399. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl), isp_mi_sp2_raw2_ctrl);
  400. miv2_imsc |= SP2_RAW_FRAME_END_MASK|SP2_DMA_RAW_READY_MASK;
  401. isp_write_reg(dev, REG_ADDR(miv2_imsc), miv2_imsc);
  402. miv2_imsc2 = isp_read_reg(dev, REG_ADDR(miv2_imsc2));
  403. miv2_imsc2 |= SP2_RAW2_FRAME_END_MASK | SP2_RAW2_DMA_READY_MASK; //0x41000
  404. isp_write_reg(dev, REG_ADDR(miv2_imsc2), miv2_imsc2);
  405. isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), 0x480);
  406. // isp_write_reg(dev, 0x00000730, 0x00001edf);
  407. //isp_write_reg(dev, 0x000014ec, 0x04b30000);
  408. //isp_write_reg(dev, 0x000014f0, 0x0807e521);
  409. return 0;
  410. }
  411. int isp_r_tdnr_refer(struct isp_ic_dev *dev)
  412. {
  413. struct isp_tdnr_buffer* buf = &dev->tdnr.buf;
  414. u32 miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl));
  415. u32 miv2_imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc));
  416. u32 miv2_sp2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_sp2_ctrl));
  417. u32 isp_mi_sp2_raw2_ctrl = isp_read_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl));
  418. pr_info("enter %s\n", __func__);
  419. isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_start_ad), buf->pa_refer);
  420. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_start_ad), buf->pa_motion);
  421. REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_CFG_UPDATE, 1);
  422. REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_AUTO_UPDATE, 1);
  423. REG_SET_SLICE(miv2_sp2_ctrl, SP2_MI_CFG_UPD, 1);
  424. miv2_sp2_ctrl |= (SP2_INIT_BASE_EN_MASK | SP2_INIT_OFFSET_EN_MASK);
  425. miv2_sp2_ctrl |= 0xf0;
  426. isp_write_reg(dev, REG_ADDR(miv2_sp2_ctrl), miv2_sp2_ctrl);
  427. isp_mi_sp2_raw2_ctrl |= 0x238;
  428. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl), isp_mi_sp2_raw2_ctrl);
  429. REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_PATH_ENABLE, 1);
  430. REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_START_CON, 1);
  431. REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_START, 1);
  432. REG_SET_SLICE(miv2_ctrl, SP2_RAW2_RDMA_START, 1);
  433. REG_SET_SLICE(miv2_ctrl, SP2_RAW2_RDMA_START_CON, 1);
  434. isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl);
  435. miv2_imsc |= SP2_DMA_RAW_READY_MASK;
  436. isp_write_reg(dev, REG_ADDR(miv2_imsc), miv2_imsc);
  437. return 0;
  438. }
  439. int isp_r_tdnr_motion(struct isp_ic_dev *dev)
  440. {
  441. struct isp_tdnr_buffer* buf = &dev->tdnr.buf;
  442. u32 miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl));
  443. u32 isp_mi_sp2_raw2_ctrl = isp_read_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl));
  444. pr_info("enter %s\n", __func__);
  445. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_dma_raw2_pic_start_ad), buf->pa_motion);
  446. REG_SET_SLICE(miv2_ctrl, SP2_RAW2_RDMA_START, 1);
  447. REG_SET_SLICE(miv2_ctrl, SP2_RAW2_RDMA_START_CON, 1);
  448. isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl);
  449. isp_mi_sp2_raw2_ctrl |= 0x238;
  450. isp_write_reg(dev, REG_ADDR(isp_mi_sp2_raw2_ctrl), isp_mi_sp2_raw2_ctrl);
  451. return 0;
  452. }
  453. int isp_tdnr_s_2dnr(struct isp_ic_dev *dev)
  454. {
  455. #ifndef ISP_2DNR_V5
  456. pr_info("unsupported function: %s\n", __func__);
  457. return -EINVAL;
  458. #else
  459. struct isp_2dnr_context *dnr2 = &dev->dnr2;
  460. u32 isp_denoise2d_control =
  461. isp_read_reg(dev, REG_ADDR(isp_denoise2d_control));
  462. u32 value, addr, strength;
  463. u32 isp_ctrl;
  464. int i;
  465. if (!dnr2->enable) {
  466. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  467. REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 0);
  468. if((value & DENOISE3D_V20_TNR_ENABLE_MASK) == 0)
  469. REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 0);
  470. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl),
  471. value);
  472. return 0;
  473. }
  474. strength = isp_read_reg(dev, REG_ADDR(isp_denoise2d_strength));
  475. REG_SET_SLICE(strength, ISP_2DNR_PRGAMMA_STRENGTH, 1);
  476. REG_SET_SLICE(strength, ISP_2DNR_STRENGTH, 0xff);
  477. isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength), strength);
  478. pr_debug("%s: write strength addr =0x%08x value = 0x%08x \n", __func__, REG_ADDR(isp_denoise2d_strength), strength);
  479. addr = REG_ADDR(isp_denoise2d_sigma_y[0]);
  480. for (i = 0; i < 60; i += 5) {
  481. value = 0;
  482. REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i]);
  483. REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 1]);
  484. REG_SET_SLICE(value, ISP_2DNR_SIGMAY2A,
  485. dnr2->sigma[i + 2] >> 6);
  486. isp_write_reg(dev, addr, value);
  487. value = 0;
  488. addr += 4;
  489. REG_SET_SLICE(value, ISP_2DNR_SIGMAY2B,
  490. dnr2->sigma[i + 2] & 0x3f);
  491. REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i + 3]);
  492. REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 4]);
  493. isp_write_reg(dev, addr, value);
  494. addr += 4;
  495. }
  496. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  497. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  498. REG_SET_SLICE(isp_denoise2d_control, ISP_2DNR_ENABLE, 1);
  499. isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr), dnr2->sigma_sqr);
  500. isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr_shd),
  501. dnr2->sigma_sqr);
  502. isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor),
  503. dnr2->weight);
  504. isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor_shd),
  505. dnr2->weight);
  506. /* refer to HW spec for HBLANK */
  507. //isp_write_reg(dev, REG_ADDR(isp_denoise2d_dummy_hblank), 0);
  508. isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength_shd), strength);
  509. isp_write_reg(dev, REG_ADDR(isp_denoise2d_control_shd),
  510. isp_denoise2d_control);
  511. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_blending));
  512. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_OFFSET, dnr2->str_off);
  513. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_MAX, dnr2->str_max);
  514. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_SLOPE, dnr2->str_slope);
  515. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_blending), value);
  516. pr_debug("%s:write blending addr = 0x%08x, value = 0x%08x \n", __func__, REG_ADDR(isp_denoise3d2_blending), value);
  517. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  518. REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 1);
  519. REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 1);
  520. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl),
  521. value);
  522. pr_debug("%s:write isp_denoise3d2_ctrl addr = 0x%08x, value = 0x%08x \n", __func__, REG_ADDR(isp_denoise3d2_ctrl), value);
  523. pr_debug("exit %s\n", __func__);
  524. return 0;
  525. #endif
  526. }
  527. #endif