isp_rgbir.c 15 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. #ifdef __KERNEL__
  54. #include <linux/io.h>
  55. #include <linux/module.h>
  56. #endif
  57. #include "mrv_all_bits.h"
  58. #include "isp_ioctl.h"
  59. #include "isp_types.h"
  60. extern MrvAllRegister_t *all_regs;
  61. enum {
  62. ISP_RGBIR_OUT_BAT_RGGB = 0,
  63. ISP_RGBIR_OUT_BAT_GRBG,
  64. ISP_RGBIR_OUT_BAT_GBRG,
  65. ISP_RGBIR_OUT_BAT_BGGR
  66. };
  67. enum {
  68. ISP_RGBIR_BAT_BGGIR = 0,
  69. ISP_RGBIR_BAT_GRIRG,
  70. ISP_RGBIR_BAT_RGGIR,
  71. ISP_RGBIR_BAT_GBIRG,
  72. ISP_RGBIR_BAT_GIRRG,
  73. ISP_RGBIR_BAT_IRGGB,
  74. ISP_RGBIR_BAT_GIRBG,
  75. ISP_RGBIR_BAT_IRGGR,
  76. ISP_RGBIR_BAT_RGIRB,
  77. ISP_RGBIR_BAT_GRBIR,
  78. ISP_RGBIR_BAT_IRBRG,
  79. ISP_RGBIR_BAT_BIRGR,
  80. ISP_RGBIR_BAT_BGIRR,
  81. ISP_RGBIR_BAT_GBRIR,
  82. ISP_RGBIR_BAT_IRRBG,
  83. ISP_RGBIR_BAT_RIRGB,
  84. };
  85. int isp_rgbir_s_bls(struct isp_ic_dev *dev)
  86. {
  87. #ifndef ISP_RGBIR
  88. isp_err("unsupported function %s", __func__);
  89. return -1;
  90. #else
  91. struct isp_rgbir_context rgbir = *(&dev->rgbir);
  92. struct isp_rgbir_bls_context* bls = &rgbir.bls;
  93. isp_info("enter %s\n", __func__);
  94. isp_write_reg(dev, REG_ADDR(isp_pre_filt_bls_a), bls->a);
  95. isp_write_reg(dev, REG_ADDR(isp_pre_filt_bls_b), bls->b);
  96. isp_write_reg(dev, REG_ADDR(isp_pre_filt_bls_c), bls->c);
  97. isp_write_reg(dev, REG_ADDR(isp_pre_filt_bls_d), bls->d);
  98. return 0;
  99. #endif
  100. }
  101. int isp_rgbir_s_gain(struct isp_ic_dev *dev)
  102. {
  103. #ifndef ISP_RGBIR
  104. isp_err("unsupported function %s", __func__);
  105. return -1;
  106. #else
  107. struct isp_rgbir_context rgbir = *(&dev->rgbir);
  108. struct isp_rgbir_rgb_gain_context* rgb_gain = &rgbir.rgb_gain;
  109. isp_info("enter %s\n", __func__);
  110. isp_write_reg(dev, REG_ADDR(isp_pre_filt_gain_r), rgb_gain->r);
  111. isp_write_reg(dev, REG_ADDR(isp_pre_filt_gain_g), rgb_gain->g);
  112. isp_write_reg(dev, REG_ADDR(isp_pre_filt_gain_b), rgb_gain->b);
  113. return 0;
  114. #endif
  115. }
  116. int isp_rgbir_s_dpcc(struct isp_ic_dev *dev)
  117. {
  118. #ifndef ISP_RGBIR
  119. isp_err("unsupported function %s", __func__);
  120. return -1;
  121. #else
  122. struct isp_rgbir_dpcc_context *dpcc = &dev->rgbir.dpcc;
  123. int i;
  124. u32 isp_pre_filt_dpc_th_r;
  125. isp_info("enter %s\n", __func__);
  126. for (i = 0; i < 4; i++) {
  127. isp_pre_filt_dpc_th_r = isp_read_reg(dev, REG_ADDR(isp_pre_filt_dpc_th_r) + i * ISP_REG_GAP);
  128. REG_SET_SLICE(isp_pre_filt_dpc_th_r, ISP_PRE_FILT_DPC_TH_MED_R, dpcc->median_thr[i]);
  129. REG_SET_SLICE(isp_pre_filt_dpc_th_r, ISP_PRE_FILT_DPC_TH_AVG_R, dpcc->avg_thr[i]);
  130. isp_write_reg(dev, REG_ADDR(isp_pre_filt_dpc_th_r) + i * ISP_REG_GAP, isp_pre_filt_dpc_th_r);
  131. }
  132. return 0;
  133. #endif
  134. }
  135. int isp_rgbir_s_cc_matrix(struct isp_ic_dev *dev)
  136. {
  137. #ifndef ISP_RGBIR
  138. isp_err("unsupported function %s", __func__);
  139. return -1;
  140. #else
  141. struct isp_rgbir_cc_context *cc = &dev->rgbir.cc; //cc color correct
  142. int i;
  143. const u8 reg_gap = 8;
  144. u32 isp_pre_filt_cc_00_01;
  145. isp_info("enter %s\n", __func__);
  146. for (i = 0; i < 3; i++) {
  147. isp_pre_filt_cc_00_01 = isp_read_reg(dev, REG_ADDR(isp_pre_filt_cc_00_01) + i * reg_gap);
  148. REG_SET_SLICE(isp_pre_filt_cc_00_01, ISP_PRE_FILT_CC_00, (u32)(cc->mtx[i][0] ));
  149. REG_SET_SLICE(isp_pre_filt_cc_00_01, ISP_PRE_FILT_CC_01, (u32)(cc->mtx[i][1] ));
  150. isp_write_reg(dev, REG_ADDR(isp_pre_filt_cc_00_01) + i * reg_gap, isp_pre_filt_cc_00_01);
  151. isp_pre_filt_cc_00_01 = isp_read_reg(dev, REG_ADDR(isp_pre_filt_cc_00_01) + i * reg_gap + ISP_REG_GAP);
  152. REG_SET_SLICE(isp_pre_filt_cc_00_01, ISP_PRE_FILT_CC_02, (u32)(cc->mtx[i][2] ));
  153. REG_SET_SLICE(isp_pre_filt_cc_00_01, ISP_PRE_FILT_CC_03, (u32)(cc->mtx[i][3] ));
  154. isp_write_reg(dev, REG_ADDR(isp_pre_filt_cc_00_01) + (i * reg_gap) + ISP_REG_GAP, isp_pre_filt_cc_00_01);
  155. }
  156. return 0;
  157. #endif
  158. }
  159. int isp_rgbir_s_des(struct isp_ic_dev *dev) //de-saturation
  160. {
  161. #ifndef ISP_RGBIR
  162. isp_err("unsupported function %s", __func__);
  163. return -1;
  164. #else
  165. struct isp_rgbir_des_context *des = &dev->rgbir.des; //cc color correct
  166. int i;
  167. u32 isp_pre_filt_ir_des_pd1; // isp_pre_filt_ir_des_px1, isp_pre_filt_ir_des_py1;
  168. u32 isp_pre_filt_l_des_pd1; // isp_pre_filt_l_des_px1, isp_pre_filt_l_des_py1;
  169. isp_info("enter %s\n", __func__);
  170. //register value
  171. for (i = 0 ; i < 4; i++) {
  172. isp_pre_filt_ir_des_pd1 = isp_read_reg(dev, REG_ADDR(isp_pre_filt_ir_des_pd1) + i * ISP_REG_GAP);
  173. if (i != 3) {
  174. isp_pre_filt_ir_des_pd1 = des->ir_pd[i *4] | des->ir_pd[i *4 + 1] << 8 | des->ir_pd[i * 4 + 2] << 16 |\
  175. des->ir_pd[i*4 + 3] << 24;
  176. } else {
  177. isp_pre_filt_ir_des_pd1 = des->ir_pd[i *4] | des->ir_pd[i *4 + 1] << 8 | des->ir_pd[i*4 + 2] << 16;
  178. }
  179. isp_write_reg(dev, REG_ADDR(isp_pre_filt_ir_des_pd1) + i * ISP_REG_GAP, isp_pre_filt_ir_des_pd1);
  180. }
  181. isp_write_reg(dev, REG_ADDR(isp_pre_filt_ir_des_px1), (des->ir_px1 & 0xffff));
  182. for (i = 0; i < 8; i++)
  183. {
  184. isp_write_reg(dev, REG_ADDR(isp_pre_filt_ir_des_py1) + i * ISP_REG_GAP, des->ir_py[i]);
  185. }
  186. for (i = 0 ; i < 4; i++) {
  187. isp_pre_filt_l_des_pd1 = isp_read_reg(dev, REG_ADDR(isp_pre_filt_l_des_pd1) + i * ISP_REG_GAP);
  188. if (i != 3) {
  189. isp_pre_filt_l_des_pd1 = des->l_pd[i *4] | des->l_pd[i*4 + 1] << 8 | des->l_pd[i*4 + 2] << 16 |\
  190. des->l_pd[i*4 + 3] << 24;
  191. } else {
  192. isp_pre_filt_l_des_pd1 = des->l_pd[i *4] | des->l_pd[i*4 + 1] << 8 | des->l_pd[i*4+2] << 16;
  193. }
  194. isp_write_reg(dev, REG_ADDR(isp_pre_filt_l_des_pd1) + i * ISP_REG_GAP, isp_pre_filt_l_des_pd1);
  195. }
  196. isp_write_reg(dev, REG_ADDR(isp_pre_filt_l_des_px1), (des->l_px1 & 0xffff));
  197. for ( i = 0; i < 8; i++)
  198. {
  199. isp_write_reg(dev, REG_ADDR(isp_pre_filt_l_des_py1) + i * 4, des->l_py[i]);
  200. }
  201. return 0;
  202. #endif
  203. }
  204. int isp_rgbir_s_sharpen(struct isp_ic_dev *dev)
  205. {
  206. #ifndef ISP_RGBIR
  207. isp_err("unsupported function %s", __func__);
  208. return -1;
  209. #else
  210. struct isp_rgbir_sharpen_context *sharpen = &dev->rgbir.sharpen;
  211. u8 sharpl = sharpen->sharpen_lvl;
  212. u32 isp_pre_filt_lum_weight; // isp_pre_filt_thresh_sh0, isp_pre_filt_thresh_sh1;
  213. // u32 isp_pre_filt_thresh_bl0, isp_pre_filt_thresh_bl1;
  214. // u32 isp_pre_filt_fac_sh0, isp_pre_filt_fac_sh1, isp_pre_filt_fac_mid;
  215. // u32 isp_pre_filt_fac_bl0, isp_pre_filt_fac_bl1;
  216. const unsigned int sharplevel[5][11] = {
  217. { 0x4, 0x08, 0x0C, 0x10, 0x16, 0x1B, 0x20, 0x26, 0x2C, 0x30, 0x3F },
  218. { 0x4, 0x07, 0x0A, 0x0C, 0x10, 0x14, 0x1A, 0x1E, 0x24, 0x2A, 0x30 },
  219. { 0x4, 0x06, 0x08, 0x0A, 0x0C, 0x10, 0x13, 0x17, 0x1D, 0x22, 0x28 },
  220. { 0x2, 0x02, 0x04, 0x06, 0x08, 0x0A, 0x0C, 0x10, 0x15, 0x1A, 0x24 },
  221. { 0x0, 0x00, 0x00, 0x02, 0x04, 0x04, 0x06, 0x08, 0x0D, 0x14, 0x20 } };
  222. isp_info("enter %s\n", __func__);
  223. //filter factor sharp
  224. isp_pre_filt_lum_weight = isp_read_reg(dev, REG_ADDR(isp_pre_filt_lum_weight));
  225. REG_SET_SLICE(isp_pre_filt_lum_weight, LUM_WEIGHT_GAIN, sharpen->lum_weight_gain);
  226. REG_SET_SLICE(isp_pre_filt_lum_weight, LUM_WEIGHT_KINK, sharpen->lum_weight_kink);
  227. REG_SET_SLICE(isp_pre_filt_lum_weight, LUM_WEIGHT_MIN, sharpen->lum_weight_min);
  228. isp_write_reg(dev, REG_ADDR(isp_pre_filt_lum_weight), isp_pre_filt_lum_weight);
  229. isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_mid), sharpen->middle);
  230. isp_write_reg(dev, REG_ADDR(isp_pre_filt_thresh_sh0), sharpen->thresh_sh0);
  231. isp_write_reg(dev, REG_ADDR(isp_pre_filt_thresh_sh1), sharpen->thresh_sh1);
  232. isp_write_reg(dev, REG_ADDR(isp_pre_filt_thresh_bl0), sharpen->thresh_bl0);
  233. isp_write_reg(dev, REG_ADDR(isp_pre_filt_thresh_bl1), sharpen->thresh_bl1);
  234. isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_sh1), (unsigned int)(sharplevel[0][sharpl]));
  235. isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_sh0), (unsigned int)(sharplevel[1][sharpl]));
  236. isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_mid), (unsigned int)(sharplevel[2][sharpl]));
  237. isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_bl0), (unsigned int)(sharplevel[3][sharpl]));
  238. isp_write_reg(dev, REG_ADDR(isp_pre_filt_fac_bl1), (unsigned int)(sharplevel[4][sharpl]));
  239. return 0;
  240. #endif
  241. }
  242. int isp_rgbir_s_ir_dnr(struct isp_ic_dev *dev)
  243. {
  244. #ifndef ISP_RGBIR
  245. isp_err("unsupported function %s", __func__);
  246. return -1;
  247. #else
  248. struct isp_rgbir_ir_dnr_context* ir_dnr = &dev->rgbir.ir_dnr;
  249. //u16 imgwidth, imgheight;
  250. u32 ir_denoise_reg_03;
  251. u32 ir_denoise_reg_45;
  252. ir_denoise_reg_03 = (ir_dnr->winweight[0] | (ir_dnr->winweight[1] << 8) | (ir_dnr->winweight[2] << 16) | (ir_dnr->winweight[3] << 24));
  253. ir_denoise_reg_45 = (ir_dnr->winweight[4] | (ir_dnr->winweight[5] << 8));
  254. isp_write_reg(dev, REG_ADDR(isp_pre_filt_ir_denoise_sw_03), (unsigned int)(ir_denoise_reg_03));
  255. isp_write_reg(dev, REG_ADDR(isp_pre_filt_ir_denoise_sw_45), ((unsigned int)(ir_denoise_reg_45) & 0xffff));
  256. //imgwidth = isp_read_reg(dev, REG_ADDR(isp_out_h_size));
  257. //imgheight = isp_read_reg(dev, REG_ADDR(isp_out_v_size));
  258. isp_write_reg(dev, REG_ADDR(isp_pre_filt_h_size), ir_dnr->width& 0x7fff);
  259. isp_write_reg(dev, REG_ADDR(isp_pre_filt_v_size), ir_dnr->height & 0x3fff);
  260. return 0;
  261. #endif
  262. }
  263. int isp_rgbir_hw_init(struct isp_ic_dev *dev)
  264. {
  265. #ifndef ISP_RGBIR
  266. isp_err("unsupported function %s", __func__);
  267. return -1;
  268. #else
  269. u32 isp_pre_filt_ctrl;
  270. struct isp_rgbir_context *rgbir = &dev->rgbir;
  271. isp_info("enter %s\n", __func__);
  272. isp_rgbir_s_cc_matrix(dev);
  273. isp_rgbir_s_bls(dev);
  274. isp_rgbir_s_dpcc(dev);
  275. isp_rgbir_s_des(dev);
  276. isp_rgbir_s_gain(dev);
  277. isp_rgbir_s_ir_dnr(dev);
  278. isp_rgbir_s_sharpen(dev);
  279. isp_pre_filt_ctrl = isp_read_reg(dev, REG_ADDR(isp_pre_filt_ctrl));//pre filt ctrl
  280. REG_SET_SLICE(isp_pre_filt_ctrl , ISP_PRE_FILT_ENABLE, rgbir->prefilt_enable);
  281. REG_SET_SLICE(isp_pre_filt_ctrl , GREEN_FILT_MODE, rgbir->green_filt_mode);
  282. REG_SET_SLICE(isp_pre_filt_ctrl , GREEN_FILT_ENABLE, rgbir->green_filt_enable);
  283. REG_SET_SLICE(isp_pre_filt_ctrl , RGBIR_BAYER_PATTERN, rgbir->rgbirPattern );
  284. REG_SET_SLICE(isp_pre_filt_ctrl , OUT_RGB_BAYER_PATTERN, rgbir->out_rgb_pattern);
  285. REG_SET_SLICE(isp_pre_filt_ctrl , STAGE1_SELECT, rgbir->green_filt_stage1_select);
  286. REG_SET_SLICE(isp_pre_filt_ctrl , DEMOSAIC_THRESHOLD, rgbir->demosaic_threshold);
  287. REG_SET_SLICE(isp_pre_filt_ctrl , PART_ONE_ENABLE, rgbir->part1_enable);
  288. REG_SET_SLICE(isp_pre_filt_ctrl , PART_TWO_ENABLE,rgbir->part2_enable);
  289. isp_write_reg(dev, REG_ADDR(isp_pre_filt_ctrl), (unsigned int)(isp_pre_filt_ctrl));//pre filt ctrl
  290. return 0;
  291. #endif
  292. }
  293. int isp_enable_rgbir(struct isp_ic_dev *dev)
  294. {
  295. #ifndef ISP_RGBIR
  296. isp_err("unsupported function %s", __func__);
  297. return -1;
  298. #else
  299. struct isp_rgbir_context *rgbir = &dev->rgbir;
  300. u32 isp_pre_filt_ctrl;
  301. isp_info("enter %s\n", __func__);
  302. isp_pre_filt_ctrl = isp_read_reg(dev, REG_ADDR(isp_pre_filt_ctrl));//pre filt ctrl
  303. REG_SET_SLICE(isp_pre_filt_ctrl , ISP_PRE_FILT_ENABLE, rgbir->prefilt_enable);
  304. isp_write_reg(dev, REG_ADDR(isp_pre_filt_ctrl), isp_pre_filt_ctrl);//pre filt ctrl
  305. return 0;
  306. #endif
  307. }
  308. int isp_rgbir_out_ir_raw(struct isp_ic_dev *dev)
  309. {
  310. #ifndef ISP_RGBIR
  311. isp_err("unsupported function %s", __func__);
  312. return -1;
  313. #else
  314. struct isp_rgbir_context *rgbir = &dev->rgbir;
  315. u32 isp_ctrl;
  316. isp_info("enter %s\n", __func__);
  317. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));//isp ctrl
  318. REG_SET_SLICE(isp_ctrl , ISP_IR_RAW_OUT, rgbir->enable_ir_raw_out);
  319. REG_SET_SLICE(isp_ctrl , MRV_ISP_ISP_MODE, MRV_ISP_ISP_MODE_RGB); //there need to config rgb mode.
  320. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);//isp_ctrl
  321. return 0;
  322. #endif
  323. }
  324. int isp_s_rgbir(struct isp_ic_dev *dev)
  325. {
  326. #ifndef ISP_WDR_V4
  327. pr_err("unsupported function: %s", __func__);
  328. return -EINVAL;
  329. #else
  330. struct isp_rgbir_context *rgbir = &dev->rgbir;
  331. u32 isp_pre_filt_ctrl;
  332. isp_info("enter %s\n", __func__);
  333. isp_rgbir_s_cc_matrix(dev);
  334. isp_rgbir_s_bls(dev);
  335. isp_rgbir_s_dpcc(dev);
  336. isp_rgbir_s_des(dev);
  337. isp_rgbir_s_gain(dev);
  338. isp_rgbir_s_ir_dnr(dev);
  339. isp_rgbir_s_sharpen(dev);
  340. isp_pre_filt_ctrl = isp_read_reg(dev, REG_ADDR(isp_pre_filt_ctrl));//pre filt ctrl
  341. REG_SET_SLICE(isp_pre_filt_ctrl , ISP_PRE_FILT_ENABLE, rgbir->prefilt_enable);
  342. REG_SET_SLICE(isp_pre_filt_ctrl , GREEN_FILT_MODE, rgbir->green_filt_mode);
  343. REG_SET_SLICE(isp_pre_filt_ctrl , GREEN_FILT_ENABLE, rgbir->green_filt_enable);
  344. REG_SET_SLICE(isp_pre_filt_ctrl , RGBIR_BAYER_PATTERN, rgbir->rgbirPattern );
  345. REG_SET_SLICE(isp_pre_filt_ctrl , OUT_RGB_BAYER_PATTERN, rgbir->out_rgb_pattern);
  346. REG_SET_SLICE(isp_pre_filt_ctrl , STAGE1_SELECT, rgbir->green_filt_stage1_select);
  347. REG_SET_SLICE(isp_pre_filt_ctrl , DEMOSAIC_THRESHOLD, rgbir->demosaic_threshold);
  348. REG_SET_SLICE(isp_pre_filt_ctrl , PART_ONE_ENABLE, rgbir->part1_enable);
  349. REG_SET_SLICE(isp_pre_filt_ctrl , PART_TWO_ENABLE,rgbir->part2_enable);
  350. isp_write_reg(dev, REG_ADDR(isp_pre_filt_ctrl), (unsigned int)(isp_pre_filt_ctrl));//pre filt ctrl
  351. return 0;
  352. #endif
  353. }