isp_isr.c 7.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279
  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. #ifdef ENABLE_IRQ
  54. #include "isp_ioctl.h"
  55. #include "isp_types.h"
  56. #include "mrv_all_bits.h"
  57. #include "video/vvbuf.h"
  58. extern MrvAllRegister_t *all_regs;
  59. #ifdef CONFIG_VIDEOBUF2_DMA_CONTIG
  60. static int config_dma_buf(struct isp_mi_data_path_context *path,
  61. dma_addr_t dma, struct isp_buffer_context *buf)
  62. {
  63. u32 size = path->out_width * path->out_height;
  64. buf->addr_y = dma;
  65. switch (path->out_mode) {
  66. case IC_MI_DATAMODE_YUV444:
  67. case IC_MI_DATAMODE_YUV422:
  68. case IC_MI_DATAMODE_YUV420:
  69. if (path->data_layout == IC_MI_DATASTORAGE_PLANAR) {
  70. buf->size_y = size + ISP_BUF_GAP;
  71. buf->addr_cb = buf->addr_y + size;
  72. buf->size_cb = size + ISP_BUF_GAP;
  73. buf->addr_cr = buf->addr_cb + size;
  74. buf->size_cr = size + ISP_BUF_GAP;
  75. } else if (path->data_layout ==
  76. IC_MI_DATASTORAGE_SEMIPLANAR) {
  77. buf->size_y = size + ISP_BUF_GAP;
  78. buf->addr_cb = buf->addr_y + size;
  79. if (path->out_mode == IC_MI_DATAMODE_YUV420)
  80. buf->size_cb = (size >> 1) + ISP_BUF_GAP;
  81. else
  82. buf->size_cb = size + ISP_BUF_GAP;
  83. } else if (path->data_layout ==
  84. IC_MI_DATASTORAGE_INTERLEAVED) {
  85. buf->size_y = (size << 1) + ISP_BUF_GAP;
  86. } else
  87. return -1;
  88. break;
  89. case IC_MI_DATAMODE_RAW8:
  90. buf->size_y = size + ISP_BUF_GAP;
  91. break;
  92. case IC_MI_DATAMODE_RAW10:
  93. case IC_MI_DATAMODE_RAW12:
  94. buf->size_y = (size << 1) + ISP_BUF_GAP;
  95. break;
  96. default:
  97. pr_err("unsupported out mode:%d\n", path->out_mode);
  98. return -1;
  99. }
  100. #ifdef ISP_MP_34BIT
  101. buf->addr_y >>= 2;
  102. buf->addr_cb >>= 2;
  103. buf->addr_cr >>= 2;
  104. #endif
  105. return 0;
  106. }
  107. #endif
  108. static int update_dma_buffer(struct isp_ic_dev *dev)
  109. {
  110. #ifdef CONFIG_VIDEOBUF2_DMA_CONTIG
  111. struct isp_mi_context *mi = &dev->mi;
  112. struct vb2_dc_buf *buf = NULL;
  113. struct isp_buffer_context dmabuf;
  114. int i,dequeued;
  115. for (i = 0; i < MI_PATH_NUM; ++i) {
  116. if (!mi->path[i].enable)
  117. continue;
  118. if (dev->mi_buf[i]) {
  119. vvbuf_ready(dev->bctx, dev->mi_buf[i]->pad,
  120. dev->mi_buf[i]);
  121. dev->mi_buf[i] = NULL;
  122. }
  123. if (dev->state && !(*dev->state & STATE_DRIVER_STARTED))
  124. continue;
  125. dequeued = 1;
  126. buf = vvbuf_try_dqbuf(dev->bctx);
  127. if (!buf) {
  128. buf = dev->mi_buf_shd[i];
  129. if (!buf)
  130. return -ENOMEM;
  131. dev->mi_buf_shd[i] = NULL;
  132. dequeued = 0;
  133. } else if (dev->mi_buf_shd[i]) {
  134. dev->mi_buf[i] = dev->mi_buf_shd[i];
  135. dev->mi_buf_shd[i] = NULL;
  136. }
  137. memset(&dmabuf, 0, sizeof(dmabuf));
  138. dmabuf.path = i;
  139. if (config_dma_buf(&mi->path[i], buf->dma, &dmabuf))
  140. continue;
  141. isp_set_buffer(dev, &dmabuf);
  142. dev->mi_buf_shd[i] = buf;
  143. if (dequeued)
  144. vvbuf_try_dqbuf_done(dev->bctx, buf);
  145. }
  146. #endif
  147. return 0;
  148. }
  149. int clean_dma_buffer(struct isp_ic_dev *dev)
  150. {
  151. #ifdef CONFIG_VIDEOBUF2_DMA_CONTIG
  152. int i;
  153. if (!dev->free)
  154. return 0;
  155. dev->free(dev, NULL);
  156. for (i = 0; i < MI_PATH_NUM; ++i) {
  157. if (dev->mi_buf[i]) {
  158. dev->free(dev, dev->mi_buf[i]);
  159. dev->mi_buf[i] = NULL;
  160. }
  161. if (dev->mi_buf_shd[i]) {
  162. dev->free(dev, dev->mi_buf_shd[i]);
  163. dev->mi_buf_shd[i] = NULL;
  164. }
  165. }
  166. #endif
  167. return 0;
  168. }
  169. void isp_clear_interrupts(struct isp_ic_dev *dev)
  170. {
  171. u32 isp_mis, mi_mis;
  172. isp_mis = isp_read_reg(dev, REG_ADDR(isp_mis));
  173. isp_write_reg(dev, REG_ADDR(isp_icr), isp_mis);
  174. #ifdef ISP_MIV1
  175. mi_mis = isp_read_reg(dev, REG_ADDR(mi_mis));
  176. isp_write_reg(dev, REG_ADDR(mi_icr), mi_mis);
  177. #elif defined(ISP_MIV2)
  178. mi_mis = isp_read_reg(dev, REG_ADDR(miv2_mis));
  179. isp_write_reg(dev, REG_ADDR(miv2_icr), mi_mis);
  180. #else
  181. mi_mis = 0;
  182. #endif
  183. }
  184. irqreturn_t isp_hw_isr(int irq, void *data)
  185. {
  186. struct isp_ic_dev *dev = (struct isp_ic_dev *)data;
  187. static const u32 frameendmask = MRV_MI_MP_FRAME_END_MASK |
  188. #ifdef ISP_MI_BP
  189. MRV_MI_BP_FRAME_END_MASK |
  190. #endif
  191. MRV_MI_SP_FRAME_END_MASK;
  192. static const u32 errormask = MRV_MI_WRAP_MP_Y_MASK |
  193. MRV_MI_WRAP_MP_CB_MASK |
  194. MRV_MI_WRAP_MP_CR_MASK |
  195. #ifdef ISP_MI_BP
  196. MRV_MI_BP_WRAP_R_MASK |
  197. MRV_MI_BP_WRAP_GR_MASK |
  198. MRV_MI_BP_WRAP_GB_MASK |
  199. MRV_MI_BP_WRAP_B_MASK |
  200. #endif
  201. MRV_MI_WRAP_SP_Y_MASK |
  202. MRV_MI_WRAP_SP_CB_MASK |
  203. MRV_MI_WRAP_SP_CR_MASK |
  204. MRV_MI_FILL_MP_Y_MASK;
  205. static const u32 fifofullmask = MRV_MI_MP_Y_FIFO_FULL_MASK |
  206. MRV_MI_MP_CB_FIFO_FULL_MASK |
  207. MRV_MI_MP_CR_FIFO_FULL_MASK |
  208. MRV_MI_SP_Y_FIFO_FULL_MASK |
  209. MRV_MI_SP_CB_FIFO_FULL_MASK |
  210. MRV_MI_SP_CR_FIFO_FULL_MASK;
  211. u32 isp_mis, mi_mis, mi_status;
  212. struct isp_irq_data irq_data;
  213. int rc = 0;
  214. if (!dev)
  215. return IRQ_HANDLED;
  216. isp_mis = isp_read_reg(dev, REG_ADDR(isp_mis));
  217. isp_write_reg(dev, REG_ADDR(isp_icr), isp_mis);
  218. #ifdef ISP_MIV1
  219. mi_mis = isp_read_reg(dev, REG_ADDR(mi_mis));
  220. isp_write_reg(dev, REG_ADDR(mi_icr), mi_mis);
  221. #elif defined(ISP_MIV2)
  222. mi_mis = isp_read_reg(dev, REG_ADDR(miv2_mis));
  223. isp_write_reg(dev, REG_ADDR(miv2_icr), mi_mis);
  224. #else
  225. mi_mis = 0;
  226. #endif
  227. mi_status = isp_read_reg(dev, REG_ADDR(mi_status));
  228. if (mi_status & fifofullmask) {
  229. isp_write_reg(dev, REG_ADDR(mi_status), mi_status);
  230. pr_debug("MI FIFO full: 0x%x\n", mi_status);
  231. }
  232. if (mi_mis & errormask)
  233. pr_debug("MI mis error: 0x%x\n", mi_mis);
  234. if (mi_mis & frameendmask)
  235. rc = update_dma_buffer(dev);
  236. if (isp_mis) {
  237. if(isp_mis & MRV_ISP_MIS_FRAME_MASK) {
  238. if (dev->isp_update_flag & ISP_FLT_UPDATE) {
  239. isp_s_flt(dev);
  240. dev->isp_update_flag &= (~ISP_FLT_UPDATE);
  241. }
  242. if (dev->gamma_out.changed) {
  243. isp_s_gamma_out(dev);
  244. }
  245. }
  246. memset(&irq_data, 0, sizeof(irq_data));
  247. irq_data.val = isp_mis;
  248. if (dev->post_event)
  249. dev->post_event(dev, &irq_data, sizeof(irq_data));
  250. }
  251. return IRQ_HANDLED;
  252. }
  253. #endif