isp_ioctl.c 116 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. /* process public and sample isp command. for complex modules, need new files.*/
  54. #include "mrv_all_bits.h"
  55. #include "isp_ioctl.h"
  56. #include "isp_types.h"
  57. #include "isp_wdr.h"
  58. #include <linux/dma-mapping.h>
  59. #include <linux/dma-buf.h>
  60. #ifdef __KERNEL__
  61. #include <linux/regmap.h>
  62. #include <linux/of_reserved_mem.h>
  63. #endif
  64. #ifdef CONFIG_VSI_ISP_DEBUG
  65. #define isp_info(fmt, ...) pr_info(fmt, ##__VA_ARGS__)
  66. #define isp_debug(fmt, ...) pr_debug(fmt, ##__VA_ARGS__)
  67. #define isp_err(fmt, ...) pr_err(fmt, ##__VA_ARGS__)
  68. #else
  69. #define isp_info(fmt, ...)
  70. #define isp_debug(fmt, ...)
  71. #define isp_err(fmt, ...) pr_err(fmt, ##__VA_ARGS__)
  72. #endif
  73. volatile MrvAllRegister_t *all_regs = NULL;
  74. #ifndef __KERNEL__
  75. #define ISP_REG_SIZE 0x10000
  76. static HalHandle_t hal_handle;
  77. void isp_ic_set_hal(HalHandle_t hal)
  78. {
  79. hal_handle = hal;
  80. }
  81. void isp_write_reg(struct isp_ic_dev *dev, u32 offset, u32 val)
  82. {
  83. //pr_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);
  84. if (offset >= ISP_REG_SIZE)
  85. return;
  86. HalWriteReg(hal_handle, offset, val);
  87. }
  88. u32 isp_read_reg(struct isp_ic_dev *dev, u32 offset)
  89. {
  90. if (offset >= ISP_REG_SIZE)
  91. return 0;
  92. return HalReadReg(hal_handle, offset);
  93. }
  94. long isp_copy_data(void *dst, void *src, int size)
  95. {
  96. if (dst != src)
  97. memcpy(dst, src, size);
  98. return 0;
  99. }
  100. #else
  101. void isp_write_reg(struct isp_ic_dev *dev, u32 offset, u32 val)
  102. {
  103. // isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);
  104. if (offset >= ISP_REG_SIZE)
  105. return;
  106. __raw_writel(val, dev->base + offset);
  107. /*isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);*/
  108. }
  109. u32 isp_read_reg(struct isp_ic_dev *dev, u32 offset)
  110. {
  111. u32 val = 0;
  112. if (offset >= ISP_REG_SIZE)
  113. return 0;
  114. val = __raw_readl(dev->base + offset);
  115. /*isp_info("%s addr 0x%08x val 0x%08x\n", __func__, offset, val);*/
  116. return val;
  117. }
  118. #endif
  119. int isp_reset(struct isp_ic_dev *dev)
  120. {
  121. isp_info("enter %s\n", __func__);
  122. isp_write_reg(dev, REG_ADDR(vi_ircl), 0xFFFFFFBF);
  123. #ifdef __KERNEL__
  124. mdelay(2);
  125. #endif
  126. isp_write_reg(dev, REG_ADDR(vi_ircl), 0x0);
  127. /*clear mis array*/
  128. isp_write_reg(dev, REG_ADDR(isp_ctrl), 0x0); //clear isp_ctrl disable_isp_clk
  129. isp_info("exit %s\n", __func__);
  130. return 0;
  131. }
  132. int isp_enable_tpg(struct isp_ic_dev *dev)
  133. {
  134. u32 addr, isp_tpg_ctrl;
  135. isp_info("enter %s\n", __func__);
  136. addr = REG_ADDR(isp_tpg_ctrl);
  137. isp_tpg_ctrl = isp_read_reg(dev, addr);
  138. //REG_SET_SLICE(isp_tpg_ctrl, TPG_FRAME_NUM, 1);//set tpg frame num
  139. REG_SET_SLICE(isp_tpg_ctrl, TPG_ENABLE, 1);
  140. isp_write_reg(dev, addr, isp_tpg_ctrl);
  141. isp_info("exit %s\n", __func__);
  142. return 0;
  143. }
  144. int isp_disable_tpg(struct isp_ic_dev *dev)
  145. {
  146. u32 addr, isp_tpg_ctrl;
  147. isp_info("enter %s\n", __func__);
  148. addr = REG_ADDR(isp_tpg_ctrl);
  149. isp_tpg_ctrl = isp_read_reg(dev, addr);
  150. REG_SET_SLICE(isp_tpg_ctrl, TPG_ENABLE, 0);
  151. isp_write_reg(dev, addr, isp_tpg_ctrl);
  152. isp_info("exit %s\n", __func__);
  153. return 0;
  154. }
  155. int isp_enable_bls(struct isp_ic_dev *dev)
  156. {
  157. #ifndef ISP_BLS
  158. //isp_err("unsupported function %s", __func__);
  159. return -1;
  160. #else
  161. u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl));
  162. isp_info("enter %s\n", __func__);
  163. REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_ENABLE,
  164. MRV_BLS_BLS_ENABLE_PROCESS);
  165. isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl);
  166. isp_info("exit %s\n", __func__);
  167. return 0;
  168. #endif
  169. }
  170. int isp_disable_bls(struct isp_ic_dev *dev)
  171. {
  172. #ifndef ISP_BLS
  173. //isp_err("unsupported function %s", __func__);
  174. return -1;
  175. #else
  176. u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl));
  177. isp_info("enter %s\n", __func__);
  178. REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_ENABLE,
  179. MRV_BLS_BLS_ENABLE_BYPASS);
  180. isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl);
  181. isp_info("exit %s\n", __func__);
  182. return 0;
  183. #endif
  184. }
  185. int isp_enable(struct isp_ic_dev *dev)
  186. {
  187. u32 isp_ctrl, isp_imsc;
  188. isp_info("enter %s\n", __func__);
  189. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  190. isp_imsc |= (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK);
  191. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  192. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  193. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 1);
  194. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  195. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 1);
  196. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  197. /*Set lsc tbl after isp enable*/
  198. if (dev->update_lsc_tbl) {
  199. isp_s_lsc_tbl(dev);
  200. dev->update_lsc_tbl = false;
  201. }
  202. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1);
  203. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  204. isp_info("exit %s\n", __func__);
  205. return 0;
  206. }
  207. int isp_disable(struct isp_ic_dev *dev)
  208. {
  209. u32 isp_ctrl;
  210. /* #ifndef ENABLE_IRQ
  211. u32 isp_imsc;
  212. #endif*/
  213. isp_info("enter %s\n", __func__);
  214. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  215. /* #ifndef ENABLE_IRQ
  216. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  217. isp_imsc |= (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK);
  218. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  219. #endif*/
  220. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 0);
  221. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  222. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 0);
  223. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  224. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  225. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  226. isp_write_reg(dev, REG_ADDR(isp_isr), MRV_ISP_ISR_ISP_OFF_MASK);
  227. isp_info("exit %s\n", __func__);
  228. return 0;
  229. }
  230. bool is_isp_enable(struct isp_ic_dev *dev)
  231. {
  232. // isp_info("enter %s\n", __func__);
  233. return isp_read_reg(dev, REG_ADDR(isp_ctrl)) & 0x01;
  234. }
  235. int isp_enable_lsc(struct isp_ic_dev *dev)
  236. {
  237. u32 isp_lsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_lsc_ctrl));
  238. isp_info("enter %s\n", __func__);
  239. REG_SET_SLICE(isp_lsc_ctrl, MRV_LSC_LSC_EN, 1U);
  240. isp_write_reg(dev, REG_ADDR(isp_lsc_ctrl), isp_lsc_ctrl);
  241. {
  242. uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  243. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  244. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  245. }
  246. isp_info("exit %s\n", __func__);
  247. return 0;
  248. }
  249. int isp_disable_lsc(struct isp_ic_dev *dev)
  250. {
  251. u32 isp_lsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_lsc_ctrl));
  252. isp_info("enter %s\n", __func__);
  253. REG_SET_SLICE(isp_lsc_ctrl, MRV_LSC_LSC_EN, 0U);
  254. isp_write_reg(dev, REG_ADDR(isp_lsc_ctrl), isp_lsc_ctrl);
  255. {
  256. uint32_t isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  257. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  258. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  259. }
  260. isp_info("exit %s\n", __func__);
  261. return 0;
  262. }
  263. #if defined(__KERNEL__) && defined(ISP8000NANO_V1802)
  264. static int isp_gpr_input_control(struct isp_ic_dev *dev)
  265. {
  266. struct isp_context isp_ctx = *(&dev->ctx);
  267. unsigned int fmt_offset = 3;
  268. unsigned int isp_dewarp_control_val;
  269. if (dev->mix_gpr == NULL)
  270. return -ENOMEM;
  271. if (dev->id == 0)
  272. fmt_offset = 3;
  273. else
  274. fmt_offset = 13;
  275. regmap_read(dev->mix_gpr, 0x138, &isp_dewarp_control_val);
  276. if (isp_dewarp_control_val == 0)
  277. isp_dewarp_control_val = 0x8d8360;
  278. switch (isp_ctx.input_selection) {
  279. case MRV_ISP_INPUT_SELECTION_12EXT:
  280. isp_dewarp_control_val &= ~(0x3f << fmt_offset);
  281. isp_dewarp_control_val |= (0x2c << fmt_offset);
  282. break;
  283. case MRV_ISP_INPUT_SELECTION_10ZERO:
  284. case MRV_ISP_INPUT_SELECTION_10MSB:
  285. isp_dewarp_control_val &= ~(0x3f << fmt_offset);
  286. isp_dewarp_control_val |= (0x2b << fmt_offset);
  287. break;
  288. case MRV_ISP_INPUT_SELECTION_8ZERO:
  289. case MRV_ISP_INPUT_SELECTION_8MSB:
  290. isp_dewarp_control_val &= ~(0x3f << fmt_offset);
  291. isp_dewarp_control_val |= (0x2a << fmt_offset);
  292. break;
  293. default:
  294. return 0;
  295. }
  296. regmap_write(dev->mix_gpr, 0x138, isp_dewarp_control_val);
  297. return 0;
  298. }
  299. #endif
  300. int isp_s_input(struct isp_ic_dev *dev)
  301. {
  302. struct isp_context isp_ctx = *(&dev->ctx);
  303. u32 isp_ctrl, isp_acq_prop, isp_demosaic;
  304. #ifdef ISP_HDR_STITCH
  305. u32 isp_stitching_ctrl;
  306. #endif //ISP_HDR_STITCH
  307. isp_info("enter %s\n", __func__);
  308. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  309. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_MODE, isp_ctx.mode);
  310. isp_acq_prop = isp_read_reg(dev, REG_ADDR(isp_acq_prop));
  311. REG_SET_SLICE(isp_acq_prop, MRV_ISP_SAMPLE_EDGE, isp_ctx.sample_edge);
  312. REG_SET_SLICE(isp_acq_prop, MRV_ISP_HSYNC_POL,
  313. isp_ctx.hSyncLowPolarity);
  314. REG_SET_SLICE(isp_acq_prop, MRV_ISP_VSYNC_POL,
  315. isp_ctx.vSyncLowPolarity);
  316. REG_SET_SLICE(isp_acq_prop, MRV_ISP_BAYER_PAT, isp_ctx.bayer_pattern);
  317. REG_SET_SLICE(isp_acq_prop, MRV_ISP_CONV_422, isp_ctx.sub_sampling);
  318. REG_SET_SLICE(isp_acq_prop, MRV_ISP_CCIR_SEQ, isp_ctx.seq_ccir);
  319. REG_SET_SLICE(isp_acq_prop, MRV_ISP_FIELD_SELECTION,
  320. isp_ctx.field_selection);
  321. REG_SET_SLICE(isp_acq_prop, MRV_ISP_INPUT_SELECTION,
  322. isp_ctx.input_selection);
  323. REG_SET_SLICE(isp_acq_prop, MRV_ISP_LATENCY_FIFO_SELECTION,
  324. isp_ctx.latency_fifo);
  325. isp_write_reg(dev, REG_ADDR(isp_acq_prop), isp_acq_prop);
  326. isp_write_reg(dev, REG_ADDR(isp_acq_h_offs), isp_ctx.acqWindow.x);
  327. isp_write_reg(dev, REG_ADDR(isp_acq_v_offs), isp_ctx.acqWindow.y);
  328. isp_write_reg(dev, REG_ADDR(isp_acq_h_size), isp_ctx.acqWindow.width);
  329. isp_write_reg(dev, REG_ADDR(isp_acq_v_size), isp_ctx.acqWindow.height);
  330. #ifdef ISP_MI_HDR
  331. isp_write_reg(dev, REG_ADDR(isp_hdr_interval), 0x113);
  332. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_h_blank), 0x200);
  333. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_v_blank), 0x30);
  334. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_h_size), isp_ctx.acqWindow.width);
  335. isp_write_reg(dev, REG_ADDR(isp_hdr_ret_v_size), isp_ctx.acqWindow.height);
  336. #endif
  337. isp_write_reg(dev, REG_ADDR(isp_out_h_offs),
  338. (isp_ctx.ofWindow.x & MRV_ISP_ISP_OUT_H_OFFS_MASK));
  339. isp_write_reg(dev, REG_ADDR(isp_out_v_offs),
  340. (isp_ctx.ofWindow.y & MRV_ISP_ISP_OUT_V_OFFS_MASK));
  341. isp_write_reg(dev, REG_ADDR(isp_out_h_size),
  342. (isp_ctx.ofWindow.width & MRV_ISP_ISP_OUT_H_SIZE_MASK));
  343. isp_write_reg(dev, REG_ADDR(isp_out_v_size),
  344. (isp_ctx.ofWindow.height & MRV_ISP_ISP_OUT_V_SIZE_MASK));
  345. isp_write_reg(dev, REG_ADDR(isp_is_h_offs),
  346. (isp_ctx.isWindow.x & MRV_IS_IS_H_OFFS_MASK));
  347. isp_write_reg(dev, REG_ADDR(isp_is_v_offs),
  348. (isp_ctx.isWindow.y & MRV_IS_IS_V_OFFS_MASK));
  349. isp_write_reg(dev, REG_ADDR(isp_is_h_size),
  350. (isp_ctx.isWindow.width & MRV_IS_IS_H_SIZE_MASK));
  351. isp_write_reg(dev, REG_ADDR(isp_is_v_size),
  352. (isp_ctx.isWindow.height & MRV_IS_IS_V_SIZE_MASK));
  353. isp_demosaic = isp_read_reg(dev, REG_ADDR(isp_demosaic));
  354. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_BYPASS,
  355. isp_ctx.bypass_mode);
  356. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_TH,
  357. isp_ctx.demosaic_threshold);
  358. isp_write_reg(dev, REG_ADDR(isp_demosaic), isp_demosaic);
  359. #ifdef ISP_HDR_STITCH
  360. isp_write_reg(dev, REG_ADDR(isp_stitching_frame_width), isp_ctx.acqWindow.width);
  361. isp_write_reg(dev, REG_ADDR(isp_stitching_frame_height), isp_ctx.acqWindow.height);
  362. isp_write_reg(dev, REG_ADDR(isp_stitching_hdr_mode), isp_ctx.stitching_mode);
  363. isp_stitching_ctrl = isp_read_reg(dev, REG_ADDR(isp_stitching_ctrl));
  364. REG_SET_SLICE(isp_stitching_ctrl, STITCHING_BAYER_PATTERN, isp_ctx.bayer_pattern);
  365. isp_write_reg(dev, REG_ADDR(isp_stitching_ctrl), isp_stitching_ctrl);
  366. #endif
  367. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  368. #if defined(__KERNEL__) && defined(ISP8000NANO_V1802)
  369. isp_gpr_input_control(dev);
  370. #endif
  371. return 0;
  372. }
  373. int isp_s_digital_gain(struct isp_ic_dev *dev)
  374. {
  375. struct isp_digital_gain_cxt dgain = *(&dev->dgain);
  376. u32 isp_dgain_rb = isp_read_reg(dev, REG_ADDR(isp_dgain_rb));
  377. u32 isp_dgain_g = isp_read_reg(dev, REG_ADDR(isp_dgain_g));
  378. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  379. if (!dgain.enable) {
  380. isp_err("%s, Disable isp digital gain", __func__);
  381. REG_SET_SLICE(isp_ctrl, MRV_ISP_DIGITAL_GAIN_EN, 0U);
  382. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  383. return 0;
  384. }
  385. //isp_info("enter %s\n", __func__);
  386. REG_SET_SLICE(isp_dgain_rb, ISP_DIGITAL_GAIN_R, dgain.gain_r);
  387. REG_SET_SLICE(isp_dgain_rb, ISP_DIGITAL_GAIN_B, dgain.gain_b);
  388. REG_SET_SLICE(isp_dgain_g, ISP_DIGITAL_GAIN_GR, dgain.gain_gr);
  389. REG_SET_SLICE(isp_dgain_g, ISP_DIGITAL_GAIN_GB, dgain.gain_gb);
  390. REG_SET_SLICE(isp_ctrl, MRV_ISP_DIGITAL_GAIN_EN, 1U);
  391. isp_write_reg(dev, REG_ADDR(isp_dgain_rb), isp_dgain_rb);
  392. isp_write_reg(dev, REG_ADDR(isp_dgain_g), isp_dgain_g);
  393. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  394. //isp_info("exit %s\n", __func__);
  395. return 0;
  396. }
  397. int isp_s_demosaic(struct isp_ic_dev *dev)
  398. {
  399. struct isp_context isp_ctx = *(&dev->ctx);
  400. u32 isp_demosaic;
  401. isp_info("enter %s\n", __func__);
  402. isp_demosaic = isp_read_reg(dev, REG_ADDR(isp_demosaic));
  403. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_BYPASS,
  404. isp_ctx.bypass_mode);
  405. REG_SET_SLICE(isp_demosaic, MRV_ISP_DEMOSAIC_TH,
  406. isp_ctx.demosaic_threshold);
  407. isp_write_reg(dev, REG_ADDR(isp_demosaic), isp_demosaic);
  408. isp_info("exit %s\n", __func__);
  409. return 0;;
  410. }
  411. int isp_s_tpg(struct isp_ic_dev *dev)
  412. {
  413. struct isp_tpg_context tpg = *(&dev->tpg);
  414. u32 addr, regVal;
  415. isp_info("enter %s\n", __func__);
  416. addr = REG_ADDR(isp_tpg_ctrl);
  417. regVal = isp_read_reg(dev, addr);
  418. REG_SET_SLICE(regVal, TPG_IMG_NUM, tpg.image_type);
  419. REG_SET_SLICE(regVal, TPG_CFA_PAT, tpg.bayer_pattern);
  420. REG_SET_SLICE(regVal, TPG_COLOR_DEPTH, tpg.color_depth);
  421. REG_SET_SLICE(regVal, TPG_RESOLUTION, tpg.resolution);
  422. REG_SET_SLICE(regVal, TPG_FRAME_NUM, tpg.frame_num);
  423. isp_write_reg(dev, addr, regVal);
  424. regVal = 0;
  425. REG_SET_SLICE(regVal, TPG_PIX_GAP_IN, tpg.pixleGap);
  426. REG_SET_SLICE(regVal, TPG_LINE_GAP_IN, tpg.lineGap);
  427. isp_write_reg(dev, REG_ADDR(isp_tpg_gap_in), regVal);
  428. regVal = 0;
  429. REG_SET_SLICE(regVal, TPG_PIX_GAP_STD_IN, tpg.gapStandard);
  430. isp_write_reg(dev, REG_ADDR(isp_tpg_gap_std_in), regVal);
  431. regVal = 0;
  432. REG_SET_SLICE(regVal, TPG_RANDOM_SEED, tpg.randomSeed);
  433. isp_write_reg(dev, REG_ADDR(isp_tpg_random_seed), regVal);
  434. REG_SET_SLICE(regVal, TPG_HTOTAL_IN, tpg.user_mode_h.total);
  435. REG_SET_SLICE(regVal, TPG_VTOTAL_IN, tpg.user_mode_v.total);
  436. isp_write_reg(dev, REG_ADDR(isp_tpg_total_in), regVal);
  437. regVal = 0;
  438. REG_SET_SLICE(regVal, TPG_HACT_IN, tpg.user_mode_h.act);
  439. REG_SET_SLICE(regVal, TPG_VACT_IN, tpg.user_mode_v.act);
  440. isp_write_reg(dev, REG_ADDR(isp_tpg_act_in), regVal);
  441. regVal = 0;
  442. REG_SET_SLICE(regVal, TPG_FP_H_IN, tpg.user_mode_h.fp);
  443. REG_SET_SLICE(regVal, TPG_FP_V_IN, tpg.user_mode_v.fp);
  444. isp_write_reg(dev, REG_ADDR(isp_tpg_fp_in), regVal);
  445. regVal = 0;
  446. REG_SET_SLICE(regVal, TPG_BP_H_IN, tpg.user_mode_h.bp);
  447. REG_SET_SLICE(regVal, TPG_BP_V_IN, tpg.user_mode_v.bp);
  448. isp_write_reg(dev, REG_ADDR(isp_tpg_bp_in), regVal);
  449. regVal = 0;
  450. REG_SET_SLICE(regVal, TPG_HS_W_IN, tpg.user_mode_h.sync);
  451. REG_SET_SLICE(regVal, TPG_VS_W_IN, tpg.user_mode_v.sync);
  452. isp_write_reg(dev, REG_ADDR(isp_tpg_w_in), regVal);
  453. isp_info("exit %s\n", __func__);
  454. return 0;
  455. }
  456. int isp_s_mcm_wr(struct isp_ic_dev *dev)
  457. {
  458. struct isp_mcm_context *mcm = &dev->mcm;
  459. u32 mcm_ctrl;
  460. u32 mcm_hsync_preample_ext;
  461. u32 mcm_size, mcm_rd_fmt;
  462. int i;
  463. isp_info("enter %s\n", __func__);
  464. mcm_ctrl = isp_read_reg(dev, REG_ADDR(mcm_ctrl));
  465. mcm_rd_fmt = isp_read_reg(dev, REG_ADDR(mcm_rd_cfg));
  466. mcm_hsync_preample_ext = isp_read_reg(dev, REG_ADDR(mcm_hsync_preample_ext));
  467. REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_SWITCH, mcm->bypass_switch);
  468. REG_SET_SLICE(mcm_ctrl, MCM_WR0_FMT, mcm->wr_fmt[MCM_INDEX_WR0]);
  469. REG_SET_SLICE(mcm_ctrl, MCM_WR1_FMT, mcm->wr_fmt[MCM_INDEX_WR1]);
  470. REG_SET_SLICE(mcm_ctrl, MCM_G2_WR0_FMT, mcm->wr_fmt[MCM_INDEX_G2_WR0]);
  471. REG_SET_SLICE(mcm_ctrl, MCM_G2_WR1_FMT, mcm->wr_fmt[MCM_INDEX_G2_WR1]);
  472. REG_SET_SLICE(mcm_ctrl, MCM_SENSOR_MEM_BYPASS, mcm->sensor_mem_bypass);
  473. REG_SET_SLICE(mcm_rd_fmt, MCM_RD_FMT, mcm->rd_fmt);
  474. REG_SET_SLICE(mcm_hsync_preample_ext, MCM_HSYNC_PREAMPLE_EXT, mcm->hsync_rpeample_ext);
  475. for (i = MCM_INDEX_WR0 ; i < MCM_INDEX_WR_MAX; i++){
  476. REG_SET_SLICE(mcm_size, MCM_HEIGHT0, mcm->height[i]);
  477. REG_SET_SLICE(mcm_size, MCM_WIDTH0, mcm->width[i]);
  478. isp_write_reg(dev, REG_ADDR(mcm_size0) + i *4, mcm_size);
  479. }
  480. isp_write_reg(dev, REG_ADDR(mcm_hsync_preample_ext), mcm_hsync_preample_ext);
  481. isp_write_reg(dev, REG_ADDR(mcm_rd_cfg), mcm_rd_fmt);
  482. isp_write_reg(dev, REG_ADDR(mcm_ctrl), mcm_ctrl);
  483. isp_info("exit %s\n", __func__);
  484. return 0;
  485. }
  486. int isp_bypass_mcm(struct isp_ic_dev *dev)
  487. {
  488. struct isp_mcm_context *mcm = &dev->mcm;
  489. u32 mcm_ctrl;
  490. u32 mcm_retiming0;
  491. u32 mcm_retiming1;
  492. u32 mcm_wr_retiming0;
  493. u32 mcm_wr_retiming1;
  494. isp_info("enter %s\n", __func__);
  495. mcm_ctrl = isp_read_reg(dev, REG_ADDR(mcm_ctrl));
  496. mcm_retiming0 = isp_read_reg(dev, REG_ADDR(mcm_retiming0));
  497. mcm_retiming1 = isp_read_reg(dev, REG_ADDR(mcm_retiming1));
  498. mcm_wr_retiming0 = isp_read_reg(dev, REG_ADDR(mcm_wr_retiming0));
  499. mcm_wr_retiming1 = isp_read_reg(dev, REG_ADDR(mcm_wr_retiming1));
  500. if (mcm->bypass_enable) {
  501. REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_EN, 1);
  502. } else {
  503. REG_SET_SLICE(mcm_ctrl, MCM_BYPASS_EN, 0);
  504. }
  505. REG_SET_SLICE(mcm_retiming0, MCM_VSYNC_DURATION, mcm->vsync_duration);
  506. REG_SET_SLICE(mcm_retiming0, MCM_VSYNC_BLANK, mcm->vsync_blank);
  507. REG_SET_SLICE(mcm_retiming1, MCM_HSYNC_PREAMPLE, mcm->hsync_preample);
  508. REG_SET_SLICE(mcm_retiming1, MCM_HSYNC_BLANK, mcm->hsync_blank);
  509. REG_SET_SLICE(mcm_wr_retiming0, MCM_VSYNC_DURATION, mcm->vsync_duration);
  510. REG_SET_SLICE(mcm_wr_retiming0, MCM_VSYNC_BLANK, mcm->vsync_blank);
  511. REG_SET_SLICE(mcm_wr_retiming1, MCM_HSYNC_PREAMPLE, mcm->hsync_preample);
  512. REG_SET_SLICE(mcm_wr_retiming1, MCM_HSYNC_BLANK, mcm->hsync_blank);
  513. isp_write_reg(dev, REG_ADDR(mcm_ctrl), mcm_ctrl);
  514. isp_write_reg(dev, REG_ADDR(mcm_retiming0), mcm_retiming0); // 0x01042801);//
  515. isp_write_reg(dev, REG_ADDR(mcm_retiming1), mcm_retiming1); //0x00008478); //
  516. isp_write_reg(dev, REG_ADDR(mcm_wr_retiming0), mcm_wr_retiming0); //0x01042801); //
  517. isp_write_reg(dev, REG_ADDR(mcm_wr_retiming1), mcm_wr_retiming1); //0x000084ec);//
  518. isp_info("exit %s\n", __func__);
  519. return 0;
  520. }
  521. int isp_s_mux(struct isp_ic_dev *dev)
  522. {
  523. struct isp_mux_context mux = *(&dev->mux);
  524. u32 vi_dpcl;
  525. isp_info("enter %s\n", __func__);
  526. vi_dpcl = isp_read_reg(dev, REG_ADDR(vi_dpcl));
  527. REG_SET_SLICE(vi_dpcl, MRV_VI_MP_MUX, mux.mp_mux);
  528. REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_SPMUX, mux.sp_mux);
  529. REG_SET_SLICE(vi_dpcl, MRV_VI_CHAN_MODE, mux.chan_mode);
  530. REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_IEMUX, mux.ie_mux);
  531. REG_SET_SLICE(vi_dpcl, MRV_VI_DMA_SWITCH, mux.dma_read_switch);
  532. REG_SET_SLICE(vi_dpcl, MRV_IF_SELECT, mux.if_select);
  533. isp_write_reg(dev, REG_ADDR(vi_dpcl), vi_dpcl);
  534. isp_info("exit %s\n", __func__);
  535. return 0;
  536. }
  537. int isp_s_bls(struct isp_ic_dev *dev)
  538. {
  539. #ifndef ISP_BLS
  540. //isp_err("unsupported function %s", __func__);
  541. return -1;
  542. #else
  543. struct isp_bls_context bls = *(&dev->bls);
  544. u32 isp_bls_ctrl = isp_read_reg(dev, REG_ADDR(isp_bls_ctrl));
  545. isp_info("enter %s\n", __func__);
  546. REG_SET_SLICE(isp_bls_ctrl, MRV_BLS_BLS_MODE, bls.mode);
  547. isp_write_reg(dev, REG_ADDR(isp_bls_ctrl), isp_bls_ctrl);
  548. isp_write_reg(dev, REG_ADDR(isp_bls_a_fixed), bls.a);
  549. isp_write_reg(dev, REG_ADDR(isp_bls_b_fixed), bls.b);
  550. isp_write_reg(dev, REG_ADDR(isp_bls_c_fixed), bls.c);
  551. isp_write_reg(dev, REG_ADDR(isp_bls_d_fixed), bls.d);
  552. return 0;
  553. #endif
  554. }
  555. int isp_enable_awb(struct isp_ic_dev *dev)
  556. {
  557. u32 isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop));
  558. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  559. isp_info("enter %s\n", __func__);
  560. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MODE, MRV_ISP_AWB_MODE_MEAS);
  561. isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop);
  562. isp_write_reg(dev, REG_ADDR(isp_imsc),
  563. isp_imsc | MRV_ISP_IMSC_AWB_DONE_MASK);
  564. isp_info("exit %s\n", __func__);
  565. return 0;
  566. }
  567. int isp_disable_awb(struct isp_ic_dev *dev)
  568. {
  569. u32 isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop));
  570. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  571. isp_info("enter %s\n", __func__);
  572. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MODE, MRV_ISP_AWB_MODE_NOMEAS);
  573. isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop);
  574. isp_write_reg(dev, REG_ADDR(isp_imsc),
  575. isp_imsc & ~MRV_ISP_IMSC_AWB_DONE_MASK);
  576. isp_info("exit %s\n", __func__);
  577. return 0;
  578. }
  579. int isp_s_awb(struct isp_ic_dev *dev)
  580. {
  581. struct isp_awb_context awb = *(&dev->awb);
  582. u32 gain_data = 0;
  583. u32 isp_awb_thresh = 0;
  584. u32 isp_awb_ref = 0;
  585. u32 isp_awb_prop = 0;
  586. /* isp_info("enter %s\n", __func__); */
  587. isp_awb_prop = isp_read_reg(dev, REG_ADDR(isp_awb_prop));
  588. if (awb.mode == MRV_ISP_AWB_MEAS_MODE_YCBCR) {
  589. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MEAS_MODE,
  590. MRV_ISP_AWB_MEAS_MODE_YCBCR);
  591. if (awb.max_y == 0) {
  592. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN,
  593. MRV_ISP_AWB_MAX_EN_DISABLE);
  594. } else {
  595. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN,
  596. MRV_ISP_AWB_MAX_EN_ENABLE);
  597. }
  598. } else if (awb.mode == MRV_ISP_AWB_MEAS_MODE_RGB) {
  599. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MAX_EN,
  600. MRV_ISP_AWB_MAX_EN_DISABLE);
  601. REG_SET_SLICE(isp_awb_prop, MRV_ISP_AWB_MEAS_MODE,
  602. MRV_ISP_AWB_MEAS_MODE_RGB);
  603. }
  604. isp_write_reg(dev, REG_ADDR(isp_awb_prop), isp_awb_prop);
  605. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MAX_Y, awb.max_y);
  606. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MIN_Y__MAX_G,
  607. awb.min_y_max_g);
  608. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MAX_CSUM, awb.max_c_sum);
  609. REG_SET_SLICE(isp_awb_thresh, MRV_ISP_AWB_MIN_C, awb.min_c);
  610. isp_write_reg(dev, REG_ADDR(isp_awb_thresh), isp_awb_thresh);
  611. REG_SET_SLICE(isp_awb_ref, MRV_ISP_AWB_REF_CR__MAX_R, awb.refcr_max_r);
  612. REG_SET_SLICE(isp_awb_ref, MRV_ISP_AWB_REF_CB__MAX_B, awb.refcb_max_b);
  613. isp_write_reg(dev, REG_ADDR(isp_awb_ref), isp_awb_ref);
  614. isp_write_reg(dev, REG_ADDR(isp_awb_frames), 0);
  615. isp_write_reg(dev, REG_ADDR(isp_awb_h_offs),
  616. (MRV_ISP_AWB_H_OFFS_MASK & awb.window.x));
  617. isp_write_reg(dev, REG_ADDR(isp_awb_v_offs),
  618. (MRV_ISP_AWB_V_OFFS_MASK & awb.window.y));
  619. isp_write_reg(dev, REG_ADDR(isp_awb_h_size),
  620. (MRV_ISP_AWB_H_SIZE_MASK & awb.window.width));
  621. isp_write_reg(dev, REG_ADDR(isp_awb_v_size),
  622. (MRV_ISP_AWB_V_SIZE_MASK & awb.window.height));
  623. gain_data = 0UL;
  624. #ifdef ISP_AWB_0410 //This is Gain value component 4 bit int part and 10 bit fractional part
  625. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_R, awb.gain_r << 2);
  626. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_B, awb.gain_b << 2) ;
  627. #else //This is Gain value component 2 bit int part and 8 bit fractional part
  628. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_R, awb.gain_r);
  629. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_B, awb.gain_b);
  630. #endif
  631. isp_write_reg(dev, REG_ADDR(isp_awb_gain_rb), gain_data);
  632. gain_data = 0UL;
  633. #ifdef ISP_AWB_0410 //This is Gain value component 4 bit int part and 10 bit fractional part
  634. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GR, awb.gain_gr << 2);
  635. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GB, awb.gain_gb << 2);
  636. #else //This is Gain value component 2 bit int part and 8 bit fractional part
  637. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GR, awb.gain_gr);
  638. REG_SET_SLICE(gain_data, MRV_ISP_AWB_GAIN_GB, awb.gain_gb);
  639. #endif
  640. isp_write_reg(dev, REG_ADDR(isp_awb_gain_g), gain_data);
  641. return 0;
  642. }
  643. int isp_s_is(struct isp_ic_dev *dev)
  644. {
  645. struct isp_is_context is = *(&dev->is);
  646. u32 isp_is_ctrl;
  647. u32 isp_is_displace;
  648. u32 isp_ctrl;
  649. isp_info("enter %s\n", __func__);
  650. isp_is_ctrl = isp_read_reg(dev, REG_ADDR(isp_is_ctrl));
  651. if (!is.enable) {
  652. REG_SET_SLICE(isp_is_ctrl, MRV_IS_IS_EN, 0);
  653. isp_write_reg(dev, REG_ADDR(isp_is_ctrl), isp_is_ctrl);
  654. return 0;
  655. }
  656. REG_SET_SLICE(isp_is_ctrl, MRV_IS_IS_EN, 1);
  657. isp_write_reg(dev, REG_ADDR(isp_is_h_offs), is.window.x);
  658. isp_write_reg(dev, REG_ADDR(isp_is_v_offs), is.window.y);
  659. isp_write_reg(dev, REG_ADDR(isp_is_h_size), is.window.width);
  660. isp_write_reg(dev, REG_ADDR(isp_is_v_size), is.window.height);
  661. isp_write_reg(dev, REG_ADDR(isp_is_recenter),
  662. is.recenter & MRV_IS_IS_RECENTER_MASK);
  663. isp_write_reg(dev, REG_ADDR(isp_is_max_dx), is.max_dx);
  664. isp_write_reg(dev, REG_ADDR(isp_is_max_dy), is.max_dy);
  665. isp_is_displace = isp_read_reg(dev, REG_ADDR(isp_is_displace));
  666. REG_SET_SLICE(isp_is_displace, MRV_IS_DX, is.displace_x);
  667. REG_SET_SLICE(isp_is_displace, MRV_IS_DY, is.displace_y);
  668. isp_write_reg(dev, REG_ADDR(isp_is_displace), isp_is_displace);
  669. isp_write_reg(dev, REG_ADDR(isp_is_ctrl), isp_is_ctrl);
  670. if (is.update) {
  671. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  672. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  673. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  674. is.update = false;
  675. }
  676. isp_info("exit %s\n", __func__);
  677. return 0;
  678. }
  679. int isp_s_raw_is(struct isp_ic_dev *dev)
  680. {
  681. #ifndef ISP_RAWIS
  682. //isp_err("unsupported funciton: %s\n", __func__);
  683. return -EINVAL;
  684. #else
  685. struct isp_is_context rawis = *(&dev->rawis);
  686. u32 isp_raw_is_ctrl;
  687. u32 isp_raw_is_displace;
  688. // u32 isp_ctrl;
  689. isp_info("enter %s\n", __func__);
  690. isp_raw_is_ctrl = isp_read_reg(dev, REG_ADDR(isp_raw_is_ctrl));
  691. if (!rawis.enable) {
  692. isp_write_reg(dev, REG_ADDR(isp_raw_is_h_size),
  693. rawis.window.width);
  694. isp_write_reg(dev, REG_ADDR(isp_raw_is_v_size),
  695. rawis.window.height);
  696. REG_SET_SLICE(isp_raw_is_ctrl, MRV_ISP_RAW_IS_EN, 0);
  697. isp_write_reg(dev, REG_ADDR(isp_raw_is_ctrl), isp_raw_is_ctrl);
  698. return 0;
  699. }
  700. REG_SET_SLICE(isp_raw_is_ctrl, MRV_ISP_RAW_IS_EN, 1);
  701. isp_write_reg(dev, REG_ADDR(isp_raw_is_h_offs), rawis.window.x);
  702. isp_write_reg(dev, REG_ADDR(isp_raw_is_v_offs), rawis.window.y);
  703. isp_write_reg(dev, REG_ADDR(isp_raw_is_h_size), rawis.window.width);
  704. isp_write_reg(dev, REG_ADDR(isp_raw_is_v_size), rawis.window.height);
  705. isp_write_reg(dev, REG_ADDR(isp_raw_is_recenter),
  706. rawis.recenter & MRV_IS_IS_RECENTER_MASK);
  707. isp_write_reg(dev, REG_ADDR(isp_raw_is_max_dx), rawis.max_dx);
  708. isp_write_reg(dev, REG_ADDR(isp_raw_is_max_dy), rawis.max_dy);
  709. isp_raw_is_displace = isp_read_reg(dev, REG_ADDR(isp_raw_is_displace));
  710. REG_SET_SLICE(isp_raw_is_displace, MRV_ISP_RAW_IS_DX, rawis.displace_x);
  711. REG_SET_SLICE(isp_raw_is_displace, MRV_ISP_RAW_IS_DY, rawis.displace_y);
  712. isp_write_reg(dev, REG_ADDR(isp_raw_is_displace), isp_raw_is_displace);
  713. isp_write_reg(dev, REG_ADDR(isp_raw_is_ctrl), isp_raw_is_ctrl);
  714. /*dont update the configuration at the sub module function*/
  715. #if 0
  716. if (rawis.update) {
  717. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  718. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1);
  719. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  720. rawis.update = false;
  721. }
  722. #endif
  723. return 0;
  724. #endif
  725. }
  726. int isp_s_cnr(struct isp_ic_dev *dev)
  727. {
  728. struct isp_cnr_context *cnr = &dev->cnr;
  729. u32 isp_ctrl;
  730. isp_info("enter %s\n", __func__);
  731. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  732. if (!cnr->enable) {
  733. REG_SET_SLICE(isp_ctrl, MRV_ISP_CNR_EN, 0);
  734. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  735. return 0;
  736. }
  737. REG_SET_SLICE(isp_ctrl, MRV_ISP_CNR_EN, 1);
  738. isp_write_reg(dev, REG_ADDR(isp_cnr_linesize), cnr->line_width);
  739. isp_write_reg(dev, REG_ADDR(isp_cnr_threshold_c1), cnr->threshold_1);
  740. isp_write_reg(dev, REG_ADDR(isp_cnr_threshold_c2), cnr->threshold_2);
  741. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  742. isp_info("exit %s\n", __func__);
  743. return 0;
  744. }
  745. void isp_test_bt(struct isp_ic_dev *dev)
  746. {
  747. isp_write_reg(dev, 0x00000010, 0x00019f7b);
  748. isp_write_reg(dev, 0x00000014, 0x00020000);
  749. isp_write_reg(dev, 0x00001200, 0x00000000);
  750. isp_write_reg(dev, 0x00001204, 0x01e00280);
  751. isp_write_reg(dev, 0x00001208, 0x01e00280);
  752. isp_write_reg(dev, 0x00001308, 0x6ce60608);
  753. isp_write_reg(dev, 0x00001314, 0x000008c4);
  754. isp_write_reg(dev, 0x00001318, 0x00000001);
  755. isp_write_reg(dev, 0x0000131c, 0x03a2013b);
  756. isp_write_reg(dev, 0x00001320, 0x00000000);
  757. isp_write_reg(dev, 0x00001324, 0xc0000000);
  758. isp_write_reg(dev, 0x00001328, 0x0004B000);
  759. isp_write_reg(dev, 0x0000132c, 0x00000000);
  760. isp_write_reg(dev, 0x00001330, 0x00000280);
  761. isp_write_reg(dev, 0x00001334, 0x00000280);
  762. isp_write_reg(dev, 0x00001338, 0x000001e0);
  763. isp_write_reg(dev, 0x0000133c, 0x0004B000);
  764. isp_write_reg(dev, 0x00001340, 0xc0040000);
  765. isp_write_reg(dev, 0x00001344, 0x0004B000);
  766. isp_write_reg(dev, 0x000016c0, 0x07ffffff);
  767. isp_write_reg(dev, 0x000005bc, 0x00000003);
  768. isp_write_reg(dev, 0x000016c4, 0x052c4e39);
  769. isp_write_reg(dev, 0x00000404, 0x00d00018);
  770. isp_write_reg(dev, 0x00000410, 0x00000280);
  771. isp_write_reg(dev, 0x00000414, 0x000001e0);
  772. isp_write_reg(dev, 0x00000538, 0x01000100);
  773. isp_write_reg(dev, 0x0000053c, 0x02270220);
  774. isp_write_reg(dev, 0x0000059c, 0x00000280);
  775. isp_write_reg(dev, 0x000005a0, 0x000001e0);
  776. isp_write_reg(dev, 0x00002310, 0x00000280);
  777. isp_write_reg(dev, 0x00002314, 0x000001e0);
  778. isp_write_reg(dev, 0x0000295c, 0x00000070);
  779. isp_write_reg(dev, 0x00003e00, 0x040128be);
  780. isp_write_reg(dev, 0x00003e04, 0x00000000);
  781. isp_write_reg(dev, 0x00003e08, 0x00001f08);
  782. isp_write_reg(dev, 0x00003e0c, 0x200003ff);
  783. isp_write_reg(dev, 0x00003e10, 0x0c968628);
  784. isp_write_reg(dev, 0x00003e14, 0x00008008);
  785. isp_write_reg(dev, 0x00003e18, 0x007d07d0);
  786. isp_write_reg(dev, 0x00003e1c, 0x301a3012);
  787. isp_write_reg(dev, 0x00003e20, 0x04010000);
  788. isp_write_reg(dev, 0x00003e24, 0x22018000);
  789. isp_write_reg(dev, 0x00003e28, 0x00020000);
  790. isp_write_reg(dev, 0x00003e2c, 0x0210210a);
  791. isp_write_reg(dev, 0x00003e30, 0x00102102);
  792. isp_write_reg(dev, 0x00003e34, 0x0000388c);
  793. isp_write_reg(dev, 0x00003e38, 0x00000000);
  794. isp_write_reg(dev, 0x00003e3c, 0x00000000);
  795. isp_write_reg(dev, 0x00003e40, 0x00000000);
  796. isp_write_reg(dev, 0x00003e44, 0x00000001);
  797. isp_write_reg(dev, 0x00003e48, 0x10001000);
  798. isp_write_reg(dev, 0x00003e4c, 0x00000000);
  799. isp_write_reg(dev, 0x00003e50, 0x00000000);
  800. isp_write_reg(dev, 0x00003e54, 0x00000000);
  801. isp_write_reg(dev, 0x00003e58, 0x00080010);
  802. isp_write_reg(dev, 0x00003e5c, 0x00080010);
  803. isp_write_reg(dev, 0x00003e60, 0x01300280);
  804. isp_write_reg(dev, 0x00000018, 0x00001000);
  805. isp_write_reg(dev, 0x00001200, 0x00000001); //why
  806. isp_write_reg(dev, 0x00000418, 0x00000001);
  807. isp_write_reg(dev, 0x00000400, 0x80100686);
  808. isp_write_reg(dev, 0x00000400, 0x80100097);
  809. isp_write_reg(dev, 0x00001300, 0x00000001);
  810. isp_write_reg(dev, 0x00001310, 0x00000038);
  811. isp_write_reg(dev, 0x000014e4, 0x00000238);
  812. isp_write_reg(dev, 0x00001600, 0x0000005c);
  813. isp_write_reg(dev, 0x00000704, 0x00c00222);
  814. isp_write_reg(dev, 0x00000708, 0x00a001e0);
  815. isp_write_reg(dev, 0x0000070c, 0x000a4023);
  816. isp_write_reg(dev, 0x00000710, 0x000a401e);
  817. isp_write_reg(dev, 0x00000714, 0x000b8001);
  818. isp_write_reg(dev, 0x00000718, 0x003540a0);
  819. isp_write_reg(dev, 0x0000071c, 0x00000050);
  820. isp_write_reg(dev, 0x00000720, 0x3aca095b);
  821. isp_write_reg(dev, 0x00000700, 0x00000c42);
  822. isp_info("end %s\n", __func__);
  823. }
  824. int isp_start_stream(struct isp_ic_dev *dev, u32 numFrames)
  825. {
  826. u32 isp_imsc, isp_ctrl;
  827. isp_info("enter %s\n", __func__);
  828. #ifdef ISP_PDAF
  829. isp_write_reg(dev, 0x5d00, 0x1);
  830. #endif
  831. isp_write_reg(dev, REG_ADDR(isp_sh_ctrl), 0x10);
  832. isp_write_reg(dev, REG_ADDR(isp_acq_nr_frames),
  833. (MRV_ISP_ACQ_NR_FRAMES_MASK & numFrames));
  834. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  835. isp_imsc |=
  836. (MRV_ISP_IMSC_ISP_OFF_MASK | MRV_ISP_IMSC_FRAME_MASK |
  837. MRV_ISP_IMSC_FRAME_IN_MASK | MRV_ISP_IMSC_PIC_SIZE_ERR_MASK | MRV_ISP_IMSC_FLASH_ON_MASK);
  838. /* isp_imsc |= (MRV_ISP_IMSC_FRAME_MASK | MRV_ISP_IMSC_DATA_LOSS_MASK | MRV_ISP_IMSC_FRAME_IN_MASK); */
  839. isp_write_reg(dev, REG_ADDR(isp_icr), 0xFFFFFFFF);
  840. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  841. isp_write_reg(dev, 0x00001320, 1);
  842. isp_write_reg(dev, 0x00001610, 1);
  843. #if 0/*add by shenwuyi for live sensor*/
  844. isp_write_reg(dev, 0x00000c68, 10);/*fream_rete_ctrl*/
  845. isp_write_reg(dev, 0x00002200, 0x00000000); //disable lsc
  846. isp_write_reg(dev, 0x000005bc, 0x00000001); //irq_enable
  847. isp_write_reg(dev, 0x00000538, 0x01000100); //awb_gain_gr
  848. isp_write_reg(dev, 0x0000053c, 0x02270220); //awb_gain_gc
  849. #endif
  850. /*isp_test_bt(dev);*/
  851. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  852. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_INFORM_ENABLE, 1);
  853. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_ENABLE, 1);
  854. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  855. /*Set lsc tbl after isp enable*/
  856. if (dev->update_lsc_tbl) {
  857. isp_s_lsc_tbl(dev);
  858. dev->update_lsc_tbl = false;
  859. }
  860. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  861. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CFG_UPD, 1);
  862. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  863. isp_info("exit %s\n", __func__);
  864. return 0;
  865. }
  866. int isp_stop_stream(struct isp_ic_dev *dev)
  867. {
  868. isp_info("enter %s\n", __func__);
  869. isp_write_reg(dev, REG_ADDR(isp_imsc), 0);
  870. isp_disable(dev);
  871. isp_info("exit %s\n", __func__);
  872. return 0;
  873. }
  874. int isp_s_cc(struct isp_ic_dev *dev)
  875. {
  876. struct isp_cc_context *cc = &dev->cc;
  877. u32 isp_ctrl, addr;
  878. int i;
  879. isp_info("enter %s\n", __func__);
  880. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  881. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CSM_Y_RANGE, cc->conv_range_y_full);
  882. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_CSM_C_RANGE, cc->conv_range_c_full);
  883. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  884. if (cc->update_curve) {
  885. addr = REG_ADDR(isp_cc_coeff_0);
  886. for (i = 0; i < 9; i++) {
  887. isp_write_reg(dev, addr + i * 4,
  888. MRV_ISP_CC_COEFF_0_MASK & cc->lCoeff[i]);
  889. }
  890. }
  891. isp_info("exit %s\n", __func__);
  892. return 0;
  893. }
  894. int isp_s_xtalk(struct isp_ic_dev *dev)
  895. {
  896. struct isp_xtalk_context xtalk = *(&dev->xtalk);
  897. int i;
  898. /* isp_info("enter %s\n", __func__); */
  899. for (i = 0; i < 9; i++) {
  900. #ifdef ISP_CTM_0507 // Coefficient for cross talk matrix.Use bit 11,Values are 12-bit signed fixed-point numbers with 5 bit integer and 7 bit fractional part, ranging from -16 (0x800) to +15.992 (0x7FF).
  901. isp_write_reg(dev, REG_ADDR(cross_talk_coef_block_arr[i]),
  902. MRV_ISP_CT_COEFF_MASK & (xtalk.lCoeff[i] << 1));
  903. #else // Coefficient for cross talk matrix.Values are 11-bit signed fixed-point numbers with 4 bit integer and 7 bit fractional part, ranging from -8 (0x400) to +7.992 (0x3FF).
  904. isp_write_reg(dev, REG_ADDR(cross_talk_coef_block_arr[i]),
  905. MRV_ISP_CT_COEFF_MASK & xtalk.lCoeff[i]);
  906. #endif
  907. }
  908. isp_write_reg(dev, REG_ADDR(isp_ct_offset_r),
  909. (MRV_ISP_CT_OFFSET_R_MASK & xtalk.r));
  910. isp_write_reg(dev, REG_ADDR(isp_ct_offset_g),
  911. (MRV_ISP_CT_OFFSET_G_MASK & xtalk.g));
  912. isp_write_reg(dev, REG_ADDR(isp_ct_offset_b),
  913. (MRV_ISP_CT_OFFSET_B_MASK & xtalk.b));
  914. return 0;
  915. }
  916. int isp_enable_wb(struct isp_ic_dev *dev, bool bEnable)
  917. {
  918. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  919. isp_info("enter %s\n", __func__);
  920. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_AWB_ENABLE, bEnable);
  921. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  922. isp_info("exit %s\n", __func__);
  923. return 0;
  924. }
  925. int isp_enable_gamma_out(struct isp_ic_dev *dev, bool bEnable)
  926. {
  927. u32 isp_ctrl;
  928. struct isp_gamma_out_context *gamma = &dev->gamma_out;
  929. isp_info("enter %s\n", __func__);
  930. gamma->enableGamma = bEnable;
  931. if(gamma->changed || !is_isp_enable(dev))
  932. {
  933. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  934. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_OUT_ENABLE, bEnable);
  935. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  936. gamma->changed = false;
  937. } else {
  938. gamma->changed = true;
  939. }
  940. isp_info("exit %s\n", __func__);
  941. return 0;
  942. }
  943. int isp_s_gamma_out(struct isp_ic_dev *dev)
  944. {
  945. u32 isp_gamma_out_mode;
  946. int i;
  947. u32 isp_ctrl;
  948. struct isp_gamma_out_context *gamma = &dev->gamma_out;
  949. if(gamma->changed || !is_isp_enable(dev)) {
  950. isp_gamma_out_mode = isp_read_reg(dev, REG_ADDR(isp_gamma_out_mode));
  951. REG_SET_SLICE(isp_gamma_out_mode, MRV_ISP_EQU_SEGM, gamma->mode);
  952. isp_write_reg(dev, REG_ADDR(isp_gamma_out_mode), isp_gamma_out_mode);
  953. for (i = 0; i < 17; i++) {
  954. isp_write_reg(dev, REG_ADDR(gamma_out_y_block_arr[i]),
  955. MRV_ISP_ISP_GAMMA_OUT_Y_MASK & gamma->curve[i]);
  956. }
  957. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  958. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_OUT_ENABLE, gamma->enableGamma);
  959. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  960. gamma->changed = false;
  961. } else {
  962. gamma->changed = true;
  963. }
  964. return 0;
  965. }
  966. int isp_s_lsc_tbl(struct isp_ic_dev *dev)
  967. {
  968. int i, n;
  969. u32 isp_ctrl;
  970. u32 sram_addr;
  971. u32 isp_lsc_status;
  972. struct isp_lsc_context *lsc = (&dev->lsc);
  973. //isp_debug("enter %s\n", __func__);
  974. /*need to set tbl after isp_ctrl enable In ISP8000NANO_V1802*/
  975. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  976. /* Enable isp to enable ram clock for write correct table to ram. */
  977. if (!(isp_ctrl & 0x01)) {
  978. dev->update_lsc_tbl = true;
  979. return 0;
  980. }
  981. isp_lsc_status = isp_read_reg(dev, REG_ADDR(isp_lsc_status));
  982. sram_addr = (isp_lsc_status & 0x2U) ? 0U : 153U;
  983. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_addr), sram_addr);
  984. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_addr), sram_addr);
  985. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_addr), sram_addr);
  986. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_addr), sram_addr);
  987. #ifdef ISP_LSC_V2
  988. for (n = 0; n < ((CAMERIC_MAX_LSC_SECTORS + 1) * (CAMERIC_MAX_LSC_SECTORS + 1)); n += CAMERIC_MAX_LSC_SECTORS + 1) {
  989. for (i = 0; i < (CAMERIC_MAX_LSC_SECTORS); i += 2) {
  990. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), (lsc->r[n + i] & 0xFFF) | ((lsc->r[n + i + 1] & 0xFFF) << 12) | ((lsc->r[n + i] >> 12) << 24) | ((lsc->r[n + i + 1] >> 12) << 28));
  991. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), (lsc->gr[n + i] & 0xFFF) | ((lsc->gr[n + i + 1] & 0xFFF) << 12) | ((lsc->gr[n + i] >> 12) << 24) | ((lsc->gr[n + i + 1] >> 12) << 28));
  992. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), (lsc->gb[n + i] & 0xFFF) | ((lsc->gb[n + i + 1] & 0xFFF) << 12) | ((lsc->gb[n + i] >> 12) << 24) | ((lsc->gb[n + i + 1] >> 12) << 28));
  993. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), (lsc->b[n + i] & 0xFFF) | ((lsc->b[n + i + 1] & 0xFFF) << 12) | ((lsc->b[n + i] >> 12) << 24) | ((lsc->b[n + i + 1] >> 12) << 28));
  994. }
  995. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data), (lsc->r[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->r[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  996. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data), (lsc->gr[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->gr[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  997. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data), (lsc->gb[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->gb[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  998. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data), (lsc->b[n + CAMERIC_MAX_LSC_SECTORS] & 0xFFF) | ((lsc->b[n + CAMERIC_MAX_LSC_SECTORS] >> 12) << 24));
  999. }
  1000. #else
  1001. for (n = 0;
  1002. n <
  1003. ((CAMERIC_MAX_LSC_SECTORS + 1) * (CAMERIC_MAX_LSC_SECTORS + 1));
  1004. n += CAMERIC_MAX_LSC_SECTORS + 1) {
  1005. /* 17 sectors with 2 values in one DWORD = 9 DWORDs (8 steps + 1 outside loop) */
  1006. for (i = 0; i < (CAMERIC_MAX_LSC_SECTORS); i += 2) {
  1007. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data),
  1008. lsc->r[n +
  1009. i] | (lsc->r[n + i + 1] << 12));
  1010. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data),
  1011. lsc->gr[n +
  1012. i] | (lsc->gr[n + i + 1] << 12));
  1013. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data),
  1014. lsc->gb[n +
  1015. i] | (lsc->gb[n + i + 1] << 12));
  1016. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data),
  1017. lsc->b[n +
  1018. i] | (lsc->b[n + i + 1] << 12));
  1019. }
  1020. isp_write_reg(dev, REG_ADDR(isp_lsc_r_table_data),
  1021. lsc->r[n + CAMERIC_MAX_LSC_SECTORS]);
  1022. isp_write_reg(dev, REG_ADDR(isp_lsc_gr_table_data),
  1023. lsc->gr[n + CAMERIC_MAX_LSC_SECTORS]);
  1024. isp_write_reg(dev, REG_ADDR(isp_lsc_gb_table_data),
  1025. lsc->gb[n + CAMERIC_MAX_LSC_SECTORS]);
  1026. isp_write_reg(dev, REG_ADDR(isp_lsc_b_table_data),
  1027. lsc->b[n + CAMERIC_MAX_LSC_SECTORS]);
  1028. }
  1029. #endif
  1030. isp_write_reg(dev, REG_ADDR(isp_lsc_table_sel),
  1031. (isp_lsc_status & 0x2U) ? 0U : 1U);
  1032. //isp_info("exit %s\n", __func__);
  1033. return 0;
  1034. }
  1035. int isp_s_lsc_sec(struct isp_ic_dev *dev)
  1036. {
  1037. int i;
  1038. struct isp_lsc_context *lsc = (&dev->lsc);
  1039. /* isp_info("enter %s\n", __func__); */
  1040. for (i = 0; i < CAEMRIC_GRAD_TBL_SIZE; i += 2) {
  1041. isp_write_reg(dev, REG_ADDR(isp_lsc_xsize_01) + i * 2,
  1042. (lsc->x_size[i] & MRV_LSC_Y_SECT_SIZE_0_MASK) |
  1043. ((lsc->x_size[i + 1]
  1044. << MRV_LSC_X_SECT_SIZE_1_SHIFT)
  1045. & MRV_LSC_X_SECT_SIZE_1_MASK));
  1046. isp_write_reg(dev, REG_ADDR(isp_lsc_ysize_01) + i * 2,
  1047. (lsc->y_size[i] & MRV_LSC_Y_SECT_SIZE_0_MASK) |
  1048. ((lsc->y_size[i + 1]
  1049. << MRV_LSC_Y_SECT_SIZE_1_SHIFT)
  1050. & MRV_LSC_Y_SECT_SIZE_1_MASK));
  1051. isp_write_reg(dev, REG_ADDR(isp_lsc_xgrad_01) + i * 2,
  1052. (lsc->x_grad[i] & MRV_LSC_XGRAD_0_MASK) |
  1053. ((lsc->x_grad[i + 1]
  1054. << MRV_LSC_XGRAD_1_SHIFT)
  1055. & MRV_LSC_XGRAD_1_MASK));
  1056. isp_write_reg(dev, REG_ADDR(isp_lsc_ygrad_01) + i * 2,
  1057. (lsc->y_grad[i] & MRV_LSC_YGRAD_0_MASK) |
  1058. ((lsc->y_grad[i + 1]
  1059. << MRV_LSC_YGRAD_1_SHIFT)
  1060. & MRV_LSC_YGRAD_1_MASK));
  1061. }
  1062. return 0;
  1063. }
  1064. int isp_ioc_read_mis(struct isp_ic_dev *dev, void __user *args)
  1065. {
  1066. isp_mis_list_t* pCList = &dev->circle_list;
  1067. isp_mis_t mis_data;
  1068. u32 ary[2];
  1069. int ret = -1;
  1070. ret = isp_irq_read_circle_queue(&mis_data, pCList);
  1071. if (ret < 0) {
  1072. /*isp_info("%s can not dequeue mis data\n", __func__);*/
  1073. return ret;
  1074. }
  1075. /*isp_info("%s irq src %d val 0x%08x\n", __func__, mis_data.irq_src, mis_data.val);*/
  1076. ary[0] = mis_data.irq_src;
  1077. ary[1] = mis_data.val;
  1078. viv_check_retval(copy_to_user(args, ary, sizeof( ary)));
  1079. return 0;
  1080. }
  1081. static int isp_ioc_read_reg(struct isp_ic_dev *dev, void __user * args)
  1082. {
  1083. struct isp_reg_t reg;
  1084. viv_check_retval(copy_from_user(&reg, args, sizeof(reg)));
  1085. reg.val = isp_read_reg(dev, reg.offset);
  1086. viv_check_retval(copy_to_user(args, &reg, sizeof(reg)));
  1087. return 0;
  1088. }
  1089. static int isp_ioc_write_reg(struct isp_ic_dev *dev, void __user *args)
  1090. {
  1091. struct isp_reg_t reg;
  1092. viv_check_retval((copy_from_user(&reg, args, sizeof(reg))));
  1093. isp_write_reg(dev, reg.offset, reg.val);
  1094. return 0;
  1095. }
  1096. int isp_ioc_disable_isp_off(struct isp_ic_dev *dev, void __user *args)
  1097. {
  1098. u32 isp_imsc;
  1099. isp_info("enter %s\n", __func__);
  1100. isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1101. isp_imsc &= ~MRV_ISP_IMSC_ISP_OFF_MASK;
  1102. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  1103. isp_info("exit %s\n", __func__);
  1104. return 0;
  1105. }
  1106. int isp_g_awbmean(struct isp_ic_dev *dev, struct isp_awb_mean *mean)
  1107. {
  1108. u32 reg = isp_read_reg(dev, REG_ADDR(isp_awb_mean));
  1109. /* isp_info("enter %s\n", __func__); */
  1110. mean->g = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_Y__G);
  1111. mean->b = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_CB__B);
  1112. mean->r = REG_GET_SLICE(reg, MRV_ISP_AWB_MEAN_CR__R);
  1113. mean->no_white_count = isp_read_reg(dev, REG_ADDR(isp_awb_white_cnt));
  1114. return 0;
  1115. }
  1116. int isp_s_ee(struct isp_ic_dev *dev)
  1117. {
  1118. #ifndef ISP_EE
  1119. //isp_err("unsupported function: %s\n", __func__);
  1120. return -EINVAL;
  1121. #else
  1122. struct isp_ee_context *ee = &dev->ee;
  1123. u32 isp_ee_ctrl = isp_read_reg(dev, REG_ADDR(isp_ee_ctrl));
  1124. u32 gain = 0;
  1125. //isp_info("enter %s\n", __func__);
  1126. if (!ee->enable) {
  1127. isp_write_reg(dev, REG_ADDR(isp_ee_ctrl),
  1128. isp_ee_ctrl & ~EE_CTRL_ENABLE_MASK);
  1129. return 0;
  1130. }
  1131. REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_INPUT_SEL, ee->input_sel);
  1132. REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_SOURCE_STRENGTH, ee->src_strength);
  1133. REG_SET_SLICE(isp_ee_ctrl, EE_CTRL_STRENGTH, ee->strength);
  1134. REG_SET_SLICE(gain, EE_UV_GAIN, ee->uv_gain);
  1135. REG_SET_SLICE(gain, EE_EDGE_GAIN, ee->edge_gain);
  1136. isp_write_reg(dev, REG_ADDR(isp_ee_y_gain), ee->y_gain);
  1137. isp_write_reg(dev, REG_ADDR(isp_ee_uv_gain), gain);
  1138. isp_write_reg(dev, REG_ADDR(isp_ee_ctrl),
  1139. isp_ee_ctrl | EE_CTRL_ENABLE_MASK);
  1140. //isp_info("exit %s\n", __func__);
  1141. return 0;
  1142. #endif
  1143. }
  1144. int isp_s_exp(struct isp_ic_dev *dev)
  1145. {
  1146. struct isp_exp_context *exp = &dev->exp;
  1147. u32 isp_exp_ctrl = isp_read_reg(dev, REG_ADDR(isp_exp_ctrl));
  1148. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1149. isp_info("enter %s\n", __func__);
  1150. if (!exp->enable) {
  1151. REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_START, 0);
  1152. isp_write_reg(dev, REG_ADDR(isp_exp_ctrl), isp_exp_ctrl);
  1153. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1154. isp_imsc & ~MRV_ISP_IMSC_EXP_END_MASK);
  1155. return 0;
  1156. }
  1157. isp_write_reg(dev, REG_ADDR(isp_exp_h_offset),
  1158. (MRV_AE_ISP_EXP_H_OFFSET_MASK & exp->window.x));
  1159. isp_write_reg(dev, REG_ADDR(isp_exp_v_offset),
  1160. (MRV_AE_ISP_EXP_V_OFFSET_MASK & exp->window.y));
  1161. isp_write_reg(dev, REG_ADDR(isp_exp_h_size),
  1162. (MRV_AE_ISP_EXP_H_SIZE_MASK & exp->window.width));
  1163. isp_write_reg(dev, REG_ADDR(isp_exp_v_size),
  1164. (MRV_AE_ISP_EXP_V_SIZE_MASK & exp->window.height));
  1165. #ifdef ISP_AE_SHADOW
  1166. isp_write_reg(dev, REG_ADDR(isp_exp_h_offset_shd),
  1167. (MRV_AE_ISP_EXP_H_OFFSET_MASK & exp->window.x));
  1168. isp_write_reg(dev, REG_ADDR(isp_exp_v_offset_shd),
  1169. (MRV_AE_ISP_EXP_V_OFFSET_MASK & exp->window.y));
  1170. isp_write_reg(dev, REG_ADDR(isp_exp_h_size_shd),
  1171. (MRV_AE_ISP_EXP_H_SIZE_MASK & exp->window.width));
  1172. isp_write_reg(dev, REG_ADDR(isp_exp_v_size_shd),
  1173. (MRV_AE_ISP_EXP_V_SIZE_MASK & exp->window.height));
  1174. #endif
  1175. REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_MEAS_MODE, exp->mode);
  1176. REG_SET_SLICE(isp_exp_ctrl, MRV_AE_EXP_START, 1);
  1177. isp_write_reg(dev, REG_ADDR(isp_exp_ctrl), isp_exp_ctrl);
  1178. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1179. isp_imsc | MRV_ISP_IMSC_EXP_END_MASK);
  1180. isp_info("exit %s\n", __func__);
  1181. return 0;
  1182. }
  1183. int isp_s_hdrexp(struct isp_ic_dev *dev)
  1184. {
  1185. struct isp_exp_context *hdrexp = &dev->hdrexp;
  1186. u32 isp_hdr_exp_conf = isp_read_reg(dev, REG_ADDR(isp_hdr_exp_conf));
  1187. u32 isp_stitching_imsc = isp_read_reg(dev, REG_ADDR(isp_stitching_imsc));
  1188. pr_info("enter %s\n", __func__);
  1189. if (!dev->hdrexp.enable) {
  1190. pr_info("%s, hdr disabled\n",__func__);
  1191. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_START, 0);
  1192. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_conf), isp_hdr_exp_conf);
  1193. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc & ~0x38);
  1194. return 0;
  1195. }
  1196. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_h_offset),
  1197. (MRV_ISP_HDR_EXP_H_OFFSET_MASK & hdrexp->window.x));
  1198. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_v_offset),
  1199. (MRV_ISP_HDR_EXP_V_OFFSET_MASK & hdrexp->window.y));
  1200. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_h_size),
  1201. (MRV_ISP_HDR_EXP_H_SIZE_MASK & hdrexp->window.width));
  1202. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_v_size),
  1203. (MRV_ISP_HDR_EXP_V_SIZE_MASK & hdrexp->window.height));
  1204. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_MEAS_MODE, hdrexp->mode);
  1205. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_SRC_SEL, 1); //hardware only support 1
  1206. REG_SET_SLICE(isp_hdr_exp_conf, MRV_HDR_EXP_START, 1);
  1207. isp_write_reg(dev, REG_ADDR(isp_hdr_exp_conf), isp_hdr_exp_conf);
  1208. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc | 0x38);
  1209. return 0;
  1210. }
  1211. int isp_g_expmean(struct isp_ic_dev *dev, u8 *mean)
  1212. {
  1213. int i = 0;
  1214. /* isp_info("enter %s\n", __func__); */
  1215. if (!dev || !mean)
  1216. return -EINVAL;
  1217. for (; i < 25; i++) {
  1218. mean[i] = isp_read_reg(dev, REG_ADDR(isp_exp_mean_00) + i * 4);
  1219. }
  1220. return 0;
  1221. }
  1222. int isp_g_hdrexpmean(struct isp_ic_dev *dev, u8 * mean)
  1223. {
  1224. int i = 0;
  1225. pr_info("enter %s\n", __func__);
  1226. if (!dev || !mean)
  1227. return -EINVAL;
  1228. for (; i < 75; i++) {
  1229. mean[i] = isp_read_reg(dev, REG_ADDR(isp_hdr_exp_statistics[i]));
  1230. }
  1231. return 0;
  1232. }
  1233. #ifdef ISP_HIST256
  1234. #define HIST_BIN_TOTAL 256
  1235. #else
  1236. #define HIST_BIN_TOTAL 16
  1237. #endif
  1238. int isp_s_hist(struct isp_ic_dev *dev)
  1239. {
  1240. struct isp_hist_context *hist = &dev->hist;
  1241. #ifdef ISP_HIST256
  1242. u32 isp_hist256_prop = isp_read_reg(dev, REG_ADDR(isp_hist256_prop));
  1243. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1244. int i;
  1245. if (!hist->enable) {
  1246. REG_SET_SLICE(isp_hist256_prop, MRV_HIST_MODE,
  1247. MRV_HIST_MODE_NONE);
  1248. isp_write_reg(dev, REG_ADDR(isp_hist256_prop),
  1249. isp_hist256_prop);
  1250. //isp_write_reg(dev, REG_ADDR(isp_imsc),
  1251. // isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1252. return 0;
  1253. }
  1254. isp_write_reg(dev, REG_ADDR(isp_hist256_h_offs),
  1255. (MRV_HIST_H_OFFSET_MASK & hist->window.x));
  1256. isp_write_reg(dev, REG_ADDR(isp_hist256_v_offs),
  1257. (MRV_HIST_V_OFFSET_MASK & hist->window.y));
  1258. isp_write_reg(dev, REG_ADDR(isp_hist256_h_size),
  1259. (MRV_HIST_H_SIZE_MASK & hist->window.width));
  1260. isp_write_reg(dev, REG_ADDR(isp_hist256_v_size),
  1261. (MRV_HIST_V_SIZE_MASK & hist->window.height));
  1262. for (i = 0; i < 24; i += 4) {
  1263. isp_write_reg(dev, REG_ADDR(isp_hist256_weight_00to30) + i,
  1264. hist->weight[i +
  1265. 0] | (hist->weight[i +
  1266. 1] << 8) |
  1267. (hist->weight[i + 2] << 16) | (hist->weight[i +
  1268. 3] <<
  1269. 24));
  1270. }
  1271. isp_write_reg(dev, REG_ADDR(isp_hist256_weight_44), hist->weight[24]);
  1272. REG_SET_SLICE(isp_hist256_prop, MRV_HIST_STEPSIZE, hist->step_size);
  1273. REG_SET_SLICE(isp_hist256_prop, MRV_HIST_MODE, hist->mode);
  1274. isp_write_reg(dev, REG_ADDR(isp_hist256_prop), isp_hist256_prop);
  1275. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1276. isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1277. #else
  1278. u32 isp_hist_prop = isp_read_reg(dev, REG_ADDR(isp_hist_prop));
  1279. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1280. int i;
  1281. isp_info("enter %s\n", __func__);
  1282. if (!hist->enable) {
  1283. REG_SET_SLICE(isp_hist_prop, MRV_HIST_MODE, MRV_HIST_MODE_NONE);
  1284. isp_write_reg(dev, REG_ADDR(isp_hist_prop), isp_hist_prop);
  1285. //isp_write_reg(dev, REG_ADDR(isp_imsc),
  1286. // isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1287. return 0;
  1288. }
  1289. isp_write_reg(dev, REG_ADDR(isp_hist_h_offs),
  1290. (MRV_HIST_H_OFFSET_MASK & hist->window.x));
  1291. isp_write_reg(dev, REG_ADDR(isp_hist_v_offs),
  1292. (MRV_HIST_V_OFFSET_MASK & hist->window.y));
  1293. isp_write_reg(dev, REG_ADDR(isp_hist_h_size),
  1294. (MRV_HIST_H_SIZE_MASK & hist->window.width));
  1295. isp_write_reg(dev, REG_ADDR(isp_hist_v_size),
  1296. (MRV_HIST_V_SIZE_MASK & hist->window.height));
  1297. for (i = 0; i < 24; i += 4) {
  1298. isp_write_reg(dev, REG_ADDR(isp_hist_weight_00to30) + i,
  1299. hist->weight[i + 0] |
  1300. (hist->weight[i + 1] << 8) |
  1301. (hist->weight[i + 2] << 16) |
  1302. (hist->weight[i + 3] << 24));
  1303. }
  1304. isp_write_reg(dev, REG_ADDR(isp_hist_weight_44), hist->weight[24]);
  1305. REG_SET_SLICE(isp_hist_prop, MRV_HIST_STEPSIZE, hist->step_size);
  1306. REG_SET_SLICE(isp_hist_prop, MRV_HIST_MODE, hist->mode);
  1307. isp_write_reg(dev, REG_ADDR(isp_hist_prop), isp_hist_prop);
  1308. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1309. isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1310. isp_info("exit %s\n", __func__);
  1311. #endif
  1312. return 0;
  1313. }
  1314. int isp_s_hdrhist(struct isp_ic_dev *dev)
  1315. {
  1316. struct isp_hist_context *hdrhist = &dev->hdrhist;
  1317. u32 isp_hdr_hist_prop = isp_read_reg(dev, REG_ADDR(isp_hdr_hist_prop));
  1318. u32 isp_stitching_imsc = isp_read_reg(dev, REG_ADDR(isp_stitching_imsc));
  1319. pr_info("enter %s\n", __func__);
  1320. if (!dev->hdrhist.enable) {
  1321. pr_info("%s, hdr disable\n", __func__);
  1322. REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_MODE, MRV_HIST_MODE_NONE);
  1323. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_prop), isp_hdr_hist_prop);
  1324. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc),
  1325. isp_stitching_imsc & ~0x1c0);
  1326. return 0;
  1327. }
  1328. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_h_offs),
  1329. (MRV_HIST_H_OFFSET_MASK & hdrhist->window.x));
  1330. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_v_offs),
  1331. (MRV_HIST_V_OFFSET_MASK & hdrhist->window.y));
  1332. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_h_size),
  1333. (MRV_HIST_H_SIZE_MASK & hdrhist->window.width));
  1334. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_v_size),
  1335. (MRV_HIST_V_SIZE_MASK & hdrhist->window.height));
  1336. REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_STEPSIZE, hdrhist->step_size);
  1337. REG_SET_SLICE(isp_hdr_hist_prop, MRV_HIST_MODE, hdrhist->mode);
  1338. isp_write_reg(dev, REG_ADDR(isp_hdr_hist_prop), isp_hdr_hist_prop);
  1339. isp_write_reg(dev, REG_ADDR(isp_stitching_imsc), isp_stitching_imsc | 0x1c0);
  1340. return 0;
  1341. }
  1342. int isp_g_histmean(struct isp_ic_dev *dev, u32 *mean)
  1343. {
  1344. int i = 0;
  1345. /* isp_info("enter %s\n", __func__); */
  1346. if (!dev || !mean)
  1347. return -EINVAL;
  1348. #ifdef ISP_HIST256
  1349. for (; i < HIST_BIN_TOTAL; i++) {
  1350. mean[i] = isp_read_reg(dev, REG_ADDR(isp_hist256_bin_n));
  1351. }
  1352. #else
  1353. for (; i < HIST_BIN_TOTAL; i++) {
  1354. mean[i] = isp_read_reg(dev,
  1355. REG_ADDR(histogram_measurement_result_arr[i]));
  1356. }
  1357. #endif
  1358. return 0;
  1359. }
  1360. int isp_g_hdrhistmean(struct isp_ic_dev *dev, u32 * mean)
  1361. {
  1362. int i = 0;
  1363. pr_info("enter %s\n", __func__);
  1364. if (!dev || !mean)
  1365. return -EINVAL;
  1366. // size is fixed 48 now, contain 3 channels
  1367. for (; i < 48; i++) {
  1368. mean[i] = isp_read_reg(dev, REG_ADDR(isp_hdr_hist_statistics[i]));
  1369. }
  1370. return 0;
  1371. }
  1372. int isp_s_hist64(struct isp_ic_dev *dev)
  1373. {
  1374. #ifndef ISP_HIST64
  1375. //pr_err("Not supported hist64 module\n");
  1376. return -1;
  1377. #else
  1378. struct isp_hist64_context *hist64 = &dev->hist64;
  1379. u32 isp64_hist_prop = isp_read_reg(dev, REG_ADDR(isp64_hist_prop));
  1380. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1381. u32 isp64_hist_subsampling = isp_read_reg(dev, REG_ADDR(isp64_hist_subsampling));
  1382. u32 isp64_hist_sample_range = isp_read_reg(dev, REG_ADDR(isp64_hist_sample_range));
  1383. u32 isp64_hist_coeff_r = 0, isp64_hist_coeff_g = 0, isp64_hist_coeff_b = 0;
  1384. int i;
  1385. if (!hist64->enable) {
  1386. REG_SET_SLICE(isp64_hist_prop, MRV_HIST_MODE,
  1387. MRV_HIST_MODE_NONE);
  1388. isp_write_reg(dev, REG_ADDR(isp64_hist_prop),
  1389. isp64_hist_prop);
  1390. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1391. isp_imsc & ~MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1392. //isp_write_reg(dev, REG_ADDR(isp64_hist_ctrl),
  1393. /// hist64->enable & ~MRV_HIST_UPDATE_ENABLE_MASK);
  1394. return 0;
  1395. }
  1396. isp_write_reg(dev, REG_ADDR(isp64_hist_h_offs),
  1397. (MRV_HIST_H_OFFSET_MASK & hist64->window.x));
  1398. isp_write_reg(dev, REG_ADDR(isp64_hist_v_offs),
  1399. (MRV_HIST_V_OFFSET_MASK & hist64->window.y));
  1400. isp_write_reg(dev, REG_ADDR(isp64_hist_h_size),
  1401. (MRV_HIST_H_SIZE_MASK & hist64->window.width));
  1402. isp_write_reg(dev, REG_ADDR(isp64_hist_v_size),
  1403. (MRV_HIST_V_SIZE_MASK & hist64->window.height));
  1404. for (i = 0; i < 24; i += 4) {
  1405. isp_write_reg(dev, REG_ADDR(isp64_hist_weight_00to30) + i,
  1406. hist64->weight[i +
  1407. 0] | (hist64->weight[i +
  1408. 1] << 8) |
  1409. (hist64->weight[i + 2] << 16) | (hist64->weight[i +
  1410. 3] <<
  1411. 24));
  1412. }
  1413. isp_write_reg(dev, REG_ADDR(isp64_hist_weight_44), hist64->weight[24]);
  1414. REG_SET_SLICE(isp64_hist_prop, MRV_HIST_CHANNEL_SELECT, hist64->channel);
  1415. REG_SET_SLICE(isp64_hist_prop, MRV_HIST_MODE, hist64->mode);
  1416. REG_SET_SLICE(isp64_hist_subsampling, MRV_HIST_V_STEPSIZE, hist64->vStepSize);
  1417. REG_SET_SLICE(isp64_hist_subsampling, MRV_HIST_H_STEP_INC, hist64->hStepInc);
  1418. REG_SET_SLICE(isp64_hist_sample_range, MRV_HIST_SAMPLE_OFFSET, hist64->sample_offset);
  1419. REG_SET_SLICE(isp64_hist_sample_range, MRV_HIST_SAMPLE_SHIFT, hist64->sample_shift);
  1420. REG_SET_SLICE(isp64_hist_coeff_r, MRV_HIST_COEFF_R, hist64->r_coeff);
  1421. REG_SET_SLICE(isp64_hist_coeff_g, MRV_HIST_COEFF_G, hist64->g_coeff);
  1422. REG_SET_SLICE(isp64_hist_coeff_b, MRV_HIST_COEFF_B, hist64->b_coeff);
  1423. isp_write_reg(dev, REG_ADDR(isp64_hist_subsampling), isp64_hist_subsampling);
  1424. isp_write_reg(dev, REG_ADDR(isp64_hist_sample_range), isp64_hist_sample_range);
  1425. isp_write_reg(dev, REG_ADDR(isp64_hist_prop), isp64_hist_prop);
  1426. isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_r), isp64_hist_coeff_r);
  1427. isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_g), isp64_hist_coeff_g);
  1428. isp_write_reg(dev, REG_ADDR(isp64_hist_coeff_b), isp64_hist_coeff_b);
  1429. isp_write_reg(dev, REG_ADDR(isp64_hist_ctrl),
  1430. hist64->enable);
  1431. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1432. isp_imsc | MRV_ISP_IMSC_HIST_MEASURE_RDY_MASK);
  1433. return 0;
  1434. #endif
  1435. }
  1436. #define HIST64_BIN_TOTAL 32
  1437. int isp_g_hist64mean(struct isp_ic_dev *dev, u32 *mean)
  1438. {
  1439. #ifndef ISP_HIST64
  1440. //pr_err("Not supported hist64 module\n");
  1441. return -1;
  1442. #else
  1443. int i = 0;
  1444. isp_info("enter %s\n", __func__);
  1445. if (!dev || !mean)
  1446. return -EINVAL;
  1447. for (; i < HIST64_BIN_TOTAL; i++) {
  1448. mean[i] = isp_read_reg(dev,
  1449. REG_ADDR(isp64_histogram_measurement_result_arr[i]));
  1450. }
  1451. isp_info("exit %s\n", __func__);
  1452. return 0;
  1453. #endif
  1454. }
  1455. int isp_g_hist64_vstart_status(struct isp_ic_dev *dev, u32 *status)
  1456. {
  1457. #ifndef ISP_HIST64
  1458. //pr_err("Not supported hist64 module\n");
  1459. return -1;
  1460. #else
  1461. /* isp_info("enter %s\n", __func__); */
  1462. if (!dev || !status)
  1463. return -EINVAL;
  1464. *status = isp_read_reg(dev, REG_ADDR(isp64_hist_vstart_status));
  1465. return 0;
  1466. #endif
  1467. }
  1468. int isp_update_hist64(struct isp_ic_dev *dev)
  1469. {
  1470. #ifndef ISP_HIST64
  1471. //pr_err("Not supported hist64\n");
  1472. return -1;
  1473. #else
  1474. struct isp_hist64_context* hist64 =&dev->hist64;
  1475. isp_write_reg(dev, REG_ADDR(isp64_hist_forced_upd_start_line),hist64->forced_upd_start_line);
  1476. isp_write_reg(dev, REG_ADDR(isp64_hist_forced_update), hist64->forced_upd);
  1477. return 0;
  1478. #endif
  1479. }
  1480. int isp_s_ge(struct isp_ic_dev *dev)
  1481. {
  1482. #ifndef ISP_GREENEQUILIBRATE
  1483. //isp_err("unsupported function %s\n", __func__);
  1484. return -1;
  1485. #else
  1486. struct isp_ge_context *ge = &dev->ge;
  1487. u32 green_equilibrate_ctrl =
  1488. isp_read_reg(dev, REG_ADDR(green_equilibrate_ctrl));
  1489. u32 green_equilibrate_hcnt_dummy = 0;
  1490. isp_info("enter %s\n", __func__);
  1491. if (!ge->enable) {
  1492. REG_SET_SLICE(green_equilibrate_ctrl,
  1493. ISP_GREEN_EQUILIBTATE_ENABLE, 0);
  1494. isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl),
  1495. green_equilibrate_ctrl);
  1496. return 0;
  1497. }
  1498. REG_SET_SLICE(green_equilibrate_ctrl, ISP_GREEN_EQUILIBTATE_TH,
  1499. ge->threshold);
  1500. REG_SET_SLICE(green_equilibrate_ctrl, ISP_GREEN_EQUILIBTATE_ENABLE, 1);
  1501. REG_SET_SLICE(green_equilibrate_hcnt_dummy,
  1502. ISP_GREEN_EQUILIBTATE_HCNT_DUMMY, ge->h_dummy);
  1503. isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl),
  1504. green_equilibrate_ctrl);
  1505. isp_write_reg(dev, REG_ADDR(green_equilibrate_hcnt_dummy),
  1506. green_equilibrate_hcnt_dummy);
  1507. isp_write_reg(dev, REG_ADDR(green_equilibrate_ctrl_shd),
  1508. green_equilibrate_ctrl);
  1509. isp_info("exit %s\n", __func__);
  1510. return 0;
  1511. #endif
  1512. }
  1513. int isp_s_ca(struct isp_ic_dev *dev)
  1514. {
  1515. #ifndef ISP_CA
  1516. //isp_err("unsupported function %s\n", __func__);
  1517. return -1;
  1518. #else
  1519. struct isp_ca_context *ca = &dev->ca;
  1520. u32 isp_curve_ctrl = isp_read_reg(dev, REG_ADDR(isp_curve_ctrl));
  1521. // u32 isp_curve_lut_x_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_x_addr));
  1522. // u32 isp_curve_lut_luma_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_luma_addr));
  1523. // u32 isp_curve_lut_chroma_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_chroma_addr));
  1524. // u32 isp_curve_lut_shift_addr = isp_read_reg(dev, REG_ADDR(isp_curve_lut_shift_addr));
  1525. int i = 0;
  1526. /*isp_info("enter %s\n", __func__);*/
  1527. if (!ca->enable) {
  1528. REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_ENABLE, 0);
  1529. isp_write_reg(dev, REG_ADDR(isp_curve_ctrl), isp_curve_ctrl);
  1530. return 0;
  1531. }
  1532. isp_write_reg(dev, REG_ADDR(isp_curve_lut_x_addr), 0);
  1533. isp_write_reg(dev, REG_ADDR(isp_curve_lut_luma_addr), 0);
  1534. isp_write_reg(dev, REG_ADDR(isp_curve_lut_chroma_addr), 0);
  1535. isp_write_reg(dev, REG_ADDR(isp_curve_lut_shift_addr), 0);
  1536. for (i = 0; i < CA_CURVE_DATA_TABLE_LEN; i++) {
  1537. isp_write_reg(dev, REG_ADDR(isp_curve_lut_x_write_data),
  1538. dev->ca.lut_x[i]);
  1539. isp_write_reg(dev, REG_ADDR(isp_curve_lut_luma_write_data),
  1540. dev->ca.lut_luma[i]);
  1541. isp_write_reg(dev, REG_ADDR(isp_curve_lut_chroma_write_data),
  1542. dev->ca.lut_chroma[i]);
  1543. isp_write_reg(dev, REG_ADDR(isp_curve_lut_shift_write_data),
  1544. dev->ca.lut_shift[i]);
  1545. }
  1546. REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_MODE, dev->ca.mode);
  1547. REG_SET_SLICE(isp_curve_ctrl, ISP_CURVE_ENABLE, 1);
  1548. isp_write_reg(dev, REG_ADDR(isp_curve_ctrl), isp_curve_ctrl);
  1549. /*isp_info("exit %s\n", __func__);*/
  1550. return 0;
  1551. #endif
  1552. }
  1553. int isp_s_dpcc(struct isp_ic_dev *dev)
  1554. {
  1555. struct isp_dpcc_context *dpcc = &dev->dpcc;
  1556. const u32 reg_gap = 20;
  1557. int i;
  1558. u32 isp_dpcc_mode = isp_read_reg(dev, REG_ADDR(isp_dpcc_mode));
  1559. isp_info("enter %s\n", __func__);
  1560. if (!dpcc->enable) {
  1561. REG_SET_SLICE(isp_dpcc_mode, MRV_DPCC_ISP_DPCC_ENABLE, 0);
  1562. } else {
  1563. REG_SET_SLICE(isp_dpcc_mode, MRV_DPCC_ISP_DPCC_ENABLE, 1);
  1564. }
  1565. isp_write_reg(dev, REG_ADDR(isp_dpcc_mode), dpcc->mode);
  1566. isp_write_reg(dev, REG_ADDR(isp_dpcc_output_mode), dpcc->outmode);
  1567. isp_write_reg(dev, REG_ADDR(isp_dpcc_set_use), dpcc->set_use);
  1568. for (i = 0; i < 3; i++) {
  1569. isp_write_reg(dev, REG_ADDR(isp_dpcc_methods_set_1) + i * 4,
  1570. 0x1FFF & dpcc->methods_set[i]);
  1571. isp_write_reg(dev,
  1572. REG_ADDR(isp_dpcc_line_thresh_1) + i * reg_gap,
  1573. 0xFFFF & dpcc->params[i].line_thresh);
  1574. isp_write_reg(dev,
  1575. REG_ADDR(isp_dpcc_line_mad_fac_1) + i * reg_gap,
  1576. 0x3F3F & dpcc->params[i].line_mad_fac);
  1577. isp_write_reg(dev, REG_ADDR(isp_dpcc_pg_fac_1) + i * reg_gap,
  1578. 0x3F3F & dpcc->params[i].pg_fac);
  1579. isp_write_reg(dev,
  1580. REG_ADDR(isp_dpcc_rnd_thresh_1) + i * reg_gap,
  1581. 0xFFFF & dpcc->params[i].rnd_thresh);
  1582. isp_write_reg(dev, REG_ADDR(isp_dpcc_rg_fac_1) + i * reg_gap,
  1583. 0x3F3F & dpcc->params[i].rg_fac);
  1584. }
  1585. isp_write_reg(dev, REG_ADDR(isp_dpcc_ro_limits), dpcc->ro_limits);
  1586. isp_write_reg(dev, REG_ADDR(isp_dpcc_rnd_offs), dpcc->rnd_offs);
  1587. isp_write_reg(dev, REG_ADDR(isp_dpcc_mode), isp_dpcc_mode);
  1588. isp_info("exit %s\n", __func__);
  1589. return 0;
  1590. }
  1591. int isp_s_flt(struct isp_ic_dev *dev)
  1592. {
  1593. struct flt_denoise_type {
  1594. u32 thresh_sh0;
  1595. u32 thresh_sh1;
  1596. u32 thresh_bl0;
  1597. u32 thresh_bl1;
  1598. u32 stage_select;
  1599. u32 vmode;
  1600. u32 hmode;
  1601. };
  1602. struct flt_sharpen_type {
  1603. u32 fac_sh0;
  1604. u32 fac_sh1;
  1605. u32 fac_mid;
  1606. u32 fac_bl0;
  1607. u32 fac_bl1;
  1608. };
  1609. static struct flt_denoise_type denoise_tbl[] = {
  1610. {0, 0, 0, 0, 6, MRV_FILT_FILT_CHR_V_MODE_STATIC8,
  1611. MRV_FILT_FILT_CHR_H_MODE_BYPASS},
  1612. {18, 33, 8, 2, 6, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1613. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1614. {26, 44, 13, 5, 4, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1615. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1616. {36, 51, 23, 10, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1617. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1618. {41, 67, 26, 15, 3, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1619. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1620. {75, 10, 50, 20, 3, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1621. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1622. {90, 120, 60, 26, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1623. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1624. {120, 150, 80, 51, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1625. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1626. {170, 200, 140, 100, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1627. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1628. {250, 300, 180, 150, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1629. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1630. {1023, 1023, 1023, 1023, 2, MRV_FILT_FILT_CHR_V_MODE_STATIC12,
  1631. MRV_FILT_FILT_CHR_H_MODE_DYN_2},
  1632. {1023, 1023, 1023, 1023, 0, MRV_FILT_FILT_CHR_V_MODE_BYPASS,
  1633. MRV_FILT_FILT_CHR_H_MODE_BYPASS},
  1634. };
  1635. static struct flt_sharpen_type sharpen_tbl[] = {
  1636. {0x4, 0x4, 0x4, 0x2, 0x0},
  1637. {0x7, 0x8, 0x6, 0x2, 0x0},
  1638. {0xA, 0xC, 0x8, 0x4, 0x0},
  1639. {0xC, 0x10, 0xA, 0x6, 0x2},
  1640. {0x16, 0x16, 0xC, 0x8, 0x4},
  1641. {0x14, 0x1B, 0x10, 0xA, 0x4},
  1642. {0x1A, 0x20, 0x13, 0xC, 0x6},
  1643. {0x1E, 0x26, 0x17, 0x10, 0x8},
  1644. {0x24, 0x2C, 0x1D, 0x15, 0x0D},
  1645. {0x2A, 0x30, 0x22, 0x1A, 0x14},
  1646. {0x30, 0x3F, 0x28, 0x24, 0x20},
  1647. };
  1648. // isp_info("enter %s\n", __func__);
  1649. if(dev->flt.changed || !is_isp_enable(dev))
  1650. {
  1651. struct isp_flt_context *flt = &dev->flt;
  1652. u32 isp_flt_mode = isp_read_reg(dev, REG_ADDR(isp_filt_mode));
  1653. if (!flt->enable) {
  1654. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_ENABLE, 0);
  1655. isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode);
  1656. return 0;
  1657. }
  1658. if (flt->denoise >= 0) {
  1659. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_sh0),
  1660. denoise_tbl[flt->denoise].thresh_sh0);
  1661. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_sh1),
  1662. denoise_tbl[flt->denoise].thresh_sh1);
  1663. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_bl0),
  1664. denoise_tbl[flt->denoise].thresh_bl0);
  1665. isp_write_reg(dev, REG_ADDR(isp_filt_thresh_bl1),
  1666. denoise_tbl[flt->denoise].thresh_bl1);
  1667. REG_SET_SLICE(isp_flt_mode, MRV_FILT_STAGE1_SELECT,
  1668. denoise_tbl[flt->denoise].stage_select);
  1669. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_CHR_V_MODE,
  1670. denoise_tbl[flt->denoise].vmode);
  1671. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_CHR_H_MODE,
  1672. denoise_tbl[flt->denoise].hmode);
  1673. }
  1674. if (flt->sharpen >= 0) {
  1675. isp_write_reg(dev, REG_ADDR(isp_filt_fac_sh0),
  1676. sharpen_tbl[flt->sharpen].fac_sh0);
  1677. isp_write_reg(dev, REG_ADDR(isp_filt_fac_sh1),
  1678. sharpen_tbl[flt->sharpen].fac_sh1);
  1679. isp_write_reg(dev, REG_ADDR(isp_filt_fac_mid),
  1680. sharpen_tbl[flt->sharpen].fac_mid);
  1681. isp_write_reg(dev, REG_ADDR(isp_filt_fac_bl0),
  1682. sharpen_tbl[flt->sharpen].fac_bl0);
  1683. isp_write_reg(dev, REG_ADDR(isp_filt_fac_bl1),
  1684. sharpen_tbl[flt->sharpen].fac_bl1);
  1685. }
  1686. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_MODE,
  1687. MRV_FILT_FILT_MODE_DYNAMIC);
  1688. isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode);
  1689. REG_SET_SLICE(isp_flt_mode, MRV_FILT_FILT_ENABLE, 1);
  1690. isp_write_reg(dev, REG_ADDR(isp_filt_mode), isp_flt_mode);
  1691. isp_write_reg(dev, REG_ADDR(isp_filt_lum_weight), 0x00032040);
  1692. dev->flt.changed = false;
  1693. } else {
  1694. dev->flt.changed = true;
  1695. }
  1696. isp_info("exit %s\n", __func__);
  1697. return 0;
  1698. }
  1699. int isp_s_cac(struct isp_ic_dev *dev)
  1700. {
  1701. struct isp_cac_context *cac = &dev->cac;
  1702. u32 val = 0;
  1703. u32 isp_cac_ctrl = isp_read_reg(dev, REG_ADDR(isp_cac_ctrl));
  1704. isp_info("enter %s\n", __func__);
  1705. if (!cac->enable) {
  1706. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_CAC_EN, 0);
  1707. isp_write_reg(dev, REG_ADDR(isp_cac_ctrl), isp_cac_ctrl);
  1708. return 0;
  1709. }
  1710. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_H_CLIP_MODE, cac->hmode);
  1711. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_V_CLIP_MODE, cac->vmode);
  1712. isp_write_reg(dev, REG_ADDR(isp_cac_count_start),
  1713. cac->hstart | (cac->vstart << 16));
  1714. isp_write_reg(dev, REG_ADDR(isp_cac_a), cac->ar | (cac->ab << 16));
  1715. isp_write_reg(dev, REG_ADDR(isp_cac_b), cac->br | (cac->bb << 16));
  1716. isp_write_reg(dev, REG_ADDR(isp_cac_c), cac->cr | (cac->cb << 16));
  1717. REG_SET_SLICE(val, MRV_CAC_X_NS, cac->xns);
  1718. REG_SET_SLICE(val, MRV_CAC_X_NF, cac->xnf);
  1719. isp_write_reg(dev, REG_ADDR(isp_cac_x_norm), val);
  1720. val = 0;
  1721. REG_SET_SLICE(val, MRV_CAC_Y_NS, cac->yns);
  1722. REG_SET_SLICE(val, MRV_CAC_Y_NF, cac->ynf);
  1723. isp_write_reg(dev, REG_ADDR(isp_cac_y_norm), val);
  1724. REG_SET_SLICE(isp_cac_ctrl, MRV_CAC_CAC_EN, 1);
  1725. isp_write_reg(dev, REG_ADDR(isp_cac_ctrl), isp_cac_ctrl);
  1726. isp_info("exit %s\n", __func__);
  1727. return 0;
  1728. }
  1729. int isp_s_deg(struct isp_ic_dev *dev)
  1730. {
  1731. struct isp_deg_context *deg = &dev->deg;
  1732. int i;
  1733. u32 isp_gamma_dx_lo = 0;
  1734. u32 isp_gamma_dx_hi = 0;
  1735. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  1736. isp_info("enter %s\n", __func__);
  1737. if (!deg->enable) {
  1738. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_IN_ENABLE, 0);
  1739. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  1740. return 0;
  1741. }
  1742. for (i = 0; i < 8; i++) {
  1743. isp_gamma_dx_lo |= deg->segment[i] << (i * 4);
  1744. isp_gamma_dx_hi |= deg->segment[i + 8] << (i * 4);
  1745. }
  1746. isp_write_reg(dev, REG_ADDR(isp_gamma_dx_lo), isp_gamma_dx_lo);
  1747. isp_write_reg(dev, REG_ADDR(isp_gamma_dx_hi), isp_gamma_dx_hi);
  1748. for (i = 0; i < 17; i++) {
  1749. isp_write_reg(dev, REG_ADDR(degamma_r_y_block_arr[i]),
  1750. deg->r[i]);
  1751. isp_write_reg(dev, REG_ADDR(degamma_g_y_block_arr[i]),
  1752. deg->g[i]);
  1753. isp_write_reg(dev, REG_ADDR(degamma_b_y_block_arr[i]),
  1754. deg->b[i]);
  1755. }
  1756. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GAMMA_IN_ENABLE, 1);
  1757. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  1758. isp_info("exit %s\n", __func__);
  1759. return 0;
  1760. }
  1761. static u32 get_eff_coeff(int decimal)
  1762. {
  1763. u32 value = 0;
  1764. if (decimal <= -6)
  1765. value = 15;
  1766. else if (decimal <= -3)
  1767. value = 14;
  1768. else if (decimal == -2)
  1769. value = 13;
  1770. else if (decimal == -1)
  1771. value = 12;
  1772. else if (decimal == 0)
  1773. value = 0;
  1774. else if (decimal == 1)
  1775. value = 8;
  1776. else if (decimal == 2)
  1777. value = 9;
  1778. else if (decimal < 6)
  1779. value = 10;
  1780. else
  1781. value = 11;
  1782. return value;
  1783. }
  1784. int isp_s_ie(struct isp_ic_dev *dev)
  1785. {
  1786. struct isp_ie_context *ie = &dev->ie;
  1787. u32 img_eff_ctrl = isp_read_reg(dev, REG_ADDR(img_eff_ctrl));
  1788. u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl));
  1789. u32 vi_ircl = isp_read_reg(dev, REG_ADDR(vi_ircl));
  1790. u32 img_eff_tint = isp_read_reg(dev, REG_ADDR(img_eff_tint));
  1791. u32 img_eff_color_sel = isp_read_reg(dev, REG_ADDR(img_eff_color_sel));
  1792. u32 mat[9];
  1793. u32 sharpen = 0;
  1794. int i;
  1795. isp_info("enter %s\n", __func__);
  1796. REG_SET_SLICE(vi_ircl, MRV_VI_IE_SOFT_RST, 1);
  1797. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  1798. if (!ie->enable) {
  1799. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_CFG_UPD,
  1800. MRV_IMGEFF_CFG_UPD_UPDATE);
  1801. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_BYPASS_MODE,
  1802. MRV_IMGEFF_BYPASS_MODE_BYPASS);
  1803. REG_SET_SLICE(vi_iccl, MRV_VI_IE_CLK_ENABLE, 0);
  1804. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  1805. isp_write_reg(dev, REG_ADDR(img_eff_ctrl), img_eff_ctrl);
  1806. return 0;
  1807. }
  1808. REG_SET_SLICE(vi_ircl, MRV_VI_IE_SOFT_RST, 0);
  1809. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  1810. REG_SET_SLICE(vi_iccl, MRV_VI_IE_CLK_ENABLE, 1);
  1811. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  1812. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_EFFECT_MODE, ie->mode);
  1813. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_FULL_RANGE, ie->full_range);
  1814. for (i = 0; i < 9; i++)
  1815. mat[i] = get_eff_coeff(ie->m[i]);
  1816. if (ie->mode == MRV_IMGEFF_EFFECT_MODE_SEPIA) {
  1817. img_eff_tint = isp_read_reg(dev, REG_ADDR(img_eff_tint));
  1818. REG_SET_SLICE(img_eff_tint, MRV_IMGEFF_INCR_CR, ie->tint_cr);
  1819. REG_SET_SLICE(img_eff_tint, MRV_IMGEFF_INCR_CB, ie->tint_cb);
  1820. isp_write_reg(dev, REG_ADDR(img_eff_tint), img_eff_tint);
  1821. } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_COLOR_SEL) {
  1822. REG_SET_SLICE(img_eff_color_sel, MRV_IMGEFF_COLOR_SELECTION,
  1823. ie->color_sel);
  1824. REG_SET_SLICE(img_eff_color_sel, MRV_IMGEFF_COLOR_THRESHOLD,
  1825. ie->color_thresh);
  1826. isp_write_reg(dev, REG_ADDR(img_eff_color_sel),
  1827. img_eff_color_sel);
  1828. } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_EMBOSS) {
  1829. isp_write_reg(dev, REG_ADDR(img_eff_mat_1),
  1830. mat[0] | (mat[1] << 4) | (mat[2] << 8) | (mat[3]
  1831. << 12));
  1832. isp_write_reg(dev, REG_ADDR(img_eff_mat_2),
  1833. mat[4] | (mat[5] << 4) | (mat[6] << 8) | (mat[7]
  1834. << 12));
  1835. isp_write_reg(dev, REG_ADDR(img_eff_mat_3), mat[8]);
  1836. } else if (ie->mode == MRV_IMGEFF_EFFECT_MODE_SKETCH ||
  1837. ie->mode == MRV_IMGEFF_EFFECT_MODE_SHARPEN) {
  1838. isp_write_reg(dev, REG_ADDR(img_eff_mat_3),
  1839. (mat[0] << 4) | (mat[1] << 8) | (mat[2] << 12));
  1840. isp_write_reg(dev, REG_ADDR(img_eff_mat_4),
  1841. mat[3] | (mat[4] << 4) | (mat[5] << 8) | (mat[6]
  1842. << 12));
  1843. isp_write_reg(dev, REG_ADDR(img_eff_mat_5),
  1844. mat[7] | (mat[8] << 4));
  1845. REG_SET_SLICE(sharpen, MRV_IMGEFF_SHARP_FACTOR,
  1846. ie->sharpen_factor);
  1847. REG_SET_SLICE(sharpen, MRV_IMGEFF_CORING_THR,
  1848. ie->sharpen_thresh);
  1849. isp_write_reg(dev, REG_ADDR(img_eff_sharpen), sharpen);
  1850. }
  1851. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_CFG_UPD,
  1852. MRV_IMGEFF_CFG_UPD_UPDATE);
  1853. REG_SET_SLICE(img_eff_ctrl, MRV_IMGEFF_BYPASS_MODE,
  1854. MRV_IMGEFF_BYPASS_MODE_PROCESS);
  1855. isp_write_reg(dev, REG_ADDR(img_eff_ctrl), img_eff_ctrl);
  1856. isp_info("exit %s\n", __func__);
  1857. return 0;
  1858. }
  1859. int isp_s_vsm(struct isp_ic_dev *dev)
  1860. {
  1861. struct isp_vsm_context *vsm = &dev->vsm;
  1862. u32 isp_vsm_mode = isp_read_reg(dev, REG_ADDR(isp_vsm_mode));
  1863. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1864. isp_info("enter %s\n", __func__);
  1865. if (!vsm->enable) {
  1866. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_EN, 0);
  1867. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_IRQ_ENABLE, 0);
  1868. isp_write_reg(dev, REG_ADDR(isp_vsm_mode), isp_vsm_mode);
  1869. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1870. isp_imsc & ~MRV_ISP_IMSC_VSM_END_MASK);
  1871. return 0;
  1872. }
  1873. isp_write_reg(dev, REG_ADDR(isp_vsm_h_offs), vsm->window.x);
  1874. isp_write_reg(dev, REG_ADDR(isp_vsm_v_offs), vsm->window.y);
  1875. isp_write_reg(dev, REG_ADDR(isp_vsm_h_size),
  1876. vsm->window.width & 0xFFFFE);
  1877. isp_write_reg(dev, REG_ADDR(isp_vsm_v_size),
  1878. vsm->window.height & 0xFFFFE);
  1879. isp_write_reg(dev, REG_ADDR(isp_vsm_h_segments), vsm->h_seg);
  1880. isp_write_reg(dev, REG_ADDR(isp_vsm_v_segments), vsm->v_seg);
  1881. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_EN, 1);
  1882. REG_SET_SLICE(isp_vsm_mode, ISP_VSM_MEAS_IRQ_ENABLE, 1);
  1883. isp_write_reg(dev, REG_ADDR(isp_vsm_mode), isp_vsm_mode);
  1884. isp_write_reg(dev, REG_ADDR(isp_imsc),
  1885. isp_imsc | MRV_ISP_IMSC_VSM_END_MASK);
  1886. isp_info("exit %s\n", __func__);
  1887. return 0;
  1888. }
  1889. int isp_g_vsm(struct isp_ic_dev *dev, struct isp_vsm_result *vsm)
  1890. {
  1891. isp_info("enter %s\n", __func__);
  1892. vsm->x = isp_read_reg(dev, REG_ADDR(isp_vsm_delta_h));
  1893. vsm->y = isp_read_reg(dev, REG_ADDR(isp_vsm_delta_v));
  1894. isp_info("exit %s\n", __func__);
  1895. return 0;
  1896. }
  1897. #if 0
  1898. u32 get_afm_shift(u32 count, u32 thresh)
  1899. {
  1900. u32 grad = count;
  1901. u32 shift = 0;
  1902. while (grad > (thresh)) {
  1903. ++shift;
  1904. grad >>= 1;
  1905. }
  1906. return shift;
  1907. }
  1908. #endif
  1909. int isp_s_afm(struct isp_ic_dev *dev)
  1910. {
  1911. struct isp_afm_context *afm = &dev->afm;
  1912. u32 mask =
  1913. (MRV_ISP_IMSC_AFM_FIN_MASK | MRV_ISP_IMSC_AFM_LUM_OF_MASK |
  1914. MRV_ISP_IMSC_AFM_SUM_OF_MASK);
  1915. u32 shift = 0;
  1916. int i;
  1917. u32 isp_afm_ctrl = isp_read_reg(dev, REG_ADDR(isp_afm_ctrl));
  1918. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  1919. isp_info("enter %s\n", __func__);
  1920. if (!afm->enable) {
  1921. REG_SET_SLICE(isp_afm_ctrl, MRV_AFM_AFM_EN, 0);
  1922. isp_imsc &= ~mask;
  1923. isp_write_reg(dev, REG_ADDR(isp_afm_ctrl), isp_afm_ctrl);
  1924. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  1925. return 0;
  1926. }
  1927. for (i = 0; i < 3; i++) {
  1928. isp_write_reg(dev, REG_ADDR(isp_afm_lt_a) + i * 8,
  1929. (afm->window[i].x << 16) | afm->window[i].y);
  1930. isp_write_reg(dev, REG_ADDR(isp_afm_rb_a) + i * 8,
  1931. ((afm->window[i].x + afm->window[i].width -
  1932. 1) << 16) | ((afm->window[i].y +
  1933. afm->window[i].height - 1)));
  1934. }
  1935. REG_SET_SLICE(shift, MRV_AFM_LUM_VAR_SHIFT, afm->lum_shift);
  1936. REG_SET_SLICE(shift, MRV_AFM_AFM_VAR_SHIFT, afm->afm_shift);
  1937. isp_write_reg(dev, REG_ADDR(isp_afm_var_shift), shift);
  1938. isp_write_reg(dev, REG_ADDR(isp_afm_thres), afm->thresh);
  1939. REG_SET_SLICE(isp_afm_ctrl, MRV_AFM_AFM_EN, 1);
  1940. isp_imsc |= mask;
  1941. isp_write_reg(dev, REG_ADDR(isp_afm_ctrl), isp_afm_ctrl);
  1942. isp_write_reg(dev, REG_ADDR(isp_imsc), isp_imsc);
  1943. isp_info("exit %s\n", __func__);
  1944. return 0;
  1945. }
  1946. int isp_g_afm(struct isp_ic_dev *dev, struct isp_afm_result *afm)
  1947. {
  1948. isp_debug("enter %s\n", __func__);
  1949. afm->sum_a = isp_read_reg(dev, REG_ADDR(isp_afm_sum_a));
  1950. afm->sum_b = isp_read_reg(dev, REG_ADDR(isp_afm_sum_b));
  1951. afm->sum_c = isp_read_reg(dev, REG_ADDR(isp_afm_sum_c));
  1952. afm->lum_a = isp_read_reg(dev, REG_ADDR(isp_afm_lum_a));
  1953. afm->lum_b = isp_read_reg(dev, REG_ADDR(isp_afm_lum_b));
  1954. afm->lum_c = isp_read_reg(dev, REG_ADDR(isp_afm_lum_c));
  1955. isp_debug("exit %s\n", __func__);
  1956. return 0;
  1957. }
  1958. int isp_s_exp2_inputsel(struct isp_ic_dev *dev)
  1959. {
  1960. #ifndef ISP_AEV2
  1961. pr_err("unsupported function: %s\n", __func__);
  1962. return -EINVAL;
  1963. #else
  1964. struct isp_exp2_context *exp2 = &dev->exp2;
  1965. u32 isp_expv2_ctrl = isp_read_reg(dev, REG_ADDR(isp_expv2_ctrl));
  1966. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_INPUT_SELECT, exp2->input_select);
  1967. isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl);
  1968. return 0;
  1969. #endif
  1970. }
  1971. int isp_s_exp2_sizeratio(struct isp_ic_dev *dev, u32 h_size)
  1972. {
  1973. #ifndef ISP_AEV2
  1974. pr_err("unsupported function: %s\n", __func__);
  1975. return -EINVAL;
  1976. #else
  1977. u32 size_inv;
  1978. size_inv = isp_read_reg(dev, REG_ADDR(isp_expv2_size_invert));
  1979. REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_H, h_size);
  1980. isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert), size_inv);
  1981. return 0;
  1982. #endif
  1983. }
  1984. int isp_s_exp2(struct isp_ic_dev *dev)
  1985. {
  1986. #ifndef ISP_AEV2
  1987. //isp_err("unsupported function: %s\n", __func__);
  1988. return -EINVAL;
  1989. #else
  1990. u32 miv2_ctrl, miv2_mp_fmt, miv2_mp_bus_id, miv2_mp_ctrl, miv2_ctrl_shd;
  1991. struct isp_exp2_context *exp2 = &dev->exp2;
  1992. u32 isp_expv2_ctrl = isp_read_reg(dev, REG_ADDR(isp_expv2_ctrl));
  1993. u32 grid_w, grid_h;
  1994. u32 size, offset, size_inv, weight;
  1995. isp_info("enter %s\n", __func__);
  1996. grid_w = ((exp2->window.width - 1) >> 6) << 1;
  1997. grid_h = ((exp2->window.height - 1) >> 6) << 1;
  1998. if (!exp2->enable) {
  1999. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_ENABLE, 0);
  2000. isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl);
  2001. return 0;
  2002. }
  2003. size = 0;
  2004. REG_SET_SLICE(size, MRV_AE_ISP_EXPV2_SIZE_H, grid_w);
  2005. REG_SET_SLICE(size, MRV_AE_ISP_EXPV2_SIZE_V, grid_h);
  2006. offset = 0;
  2007. REG_SET_SLICE(offset, MRV_AE_ISP_EXPV2_OFFSET_H, exp2->window.x);
  2008. REG_SET_SLICE(offset, MRV_AE_ISP_EXPV2_OFFSET_V, exp2->window.y);
  2009. size_inv = 0;
  2010. REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_H, (65536 + grid_w/2) / grid_w);
  2011. REG_SET_SLICE(size_inv, MRV_AE_ISP_EXPV2_SIZE_INVERT_V, (65536 + grid_h/2) / grid_h);
  2012. weight = 0;
  2013. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_R, exp2->r)
  2014. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_GR, exp2->gr)
  2015. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_GB, exp2->gb)
  2016. REG_SET_SLICE(weight, MRV_AE_ISP_EXPV2_PIX_WEIGHT_B, exp2->b)
  2017. isp_write_reg(dev, REG_ADDR(isp_expv2_offset), offset);
  2018. isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert), size_inv);
  2019. isp_write_reg(dev, REG_ADDR(isp_expv2_size), size);
  2020. #ifdef ISP_AE_SHADOW
  2021. isp_write_reg(dev, REG_ADDR(isp_expv2_offset_shd), offset);
  2022. isp_write_reg(dev, REG_ADDR(isp_expv2_size_invert_shd), size_inv);
  2023. isp_write_reg(dev, REG_ADDR(isp_expv2_size_shd), size);
  2024. #endif
  2025. isp_write_reg(dev, REG_ADDR(isp_expv2_pixel_weight), weight);
  2026. miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl));
  2027. REG_SET_SLICE(miv2_ctrl, MP_JDP_PATH_ENABLE, 1);
  2028. isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl);
  2029. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_base_ad_init), dev->exp2.pa);
  2030. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_size_init), AEV2_DMA_SIZE);
  2031. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_offs_cnt_init), 0);
  2032. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_llength), AEV2_DMA_SIZE);
  2033. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_width), 1024);
  2034. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_height), 1);
  2035. isp_write_reg(dev, REG_ADDR(miv2_mp_jdp_pic_size), AEV2_DMA_SIZE);
  2036. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_ENABLE, 1);
  2037. REG_SET_SLICE(isp_expv2_ctrl, MRV_AE_ISP_EXPV2_INPUT_SELECT, exp2->input_select);
  2038. isp_write_reg(dev, REG_ADDR(isp_expv2_ctrl), isp_expv2_ctrl);
  2039. miv2_ctrl_shd = isp_read_reg(dev, REG_ADDR(miv2_ctrl_shd));
  2040. if (!(miv2_ctrl_shd && MP_YCBCR_PATH_ENABLE_MASK) && !(miv2_ctrl_shd && MP_RAW_PATH_ENABLE_MASK)) {
  2041. miv2_mp_fmt = isp_read_reg(dev, REG_ADDR(miv2_mp_fmt));
  2042. #ifdef ISP_AEV2_V2
  2043. REG_SET_SLICE(miv2_mp_fmt, MP_WR_JDP_DP_BIT, 1);
  2044. #endif
  2045. REG_SET_SLICE(miv2_mp_fmt, MP_WR_JDP_FMT, 0);
  2046. isp_write_reg(dev, REG_ADDR(miv2_mp_fmt), miv2_mp_fmt);
  2047. miv2_mp_bus_id = isp_read_reg(dev, REG_ADDR(miv2_mp_bus_id));
  2048. REG_SET_SLICE(miv2_mp_bus_id, MP_BUS_SW_EN, 1);
  2049. REG_SET_SLICE(miv2_mp_bus_id, MP_WR_ID_EN, 1);
  2050. isp_write_reg(dev, REG_ADDR(miv2_mp_bus_id), miv2_mp_bus_id);
  2051. miv2_mp_ctrl = isp_read_reg(dev, REG_ADDR(miv2_mp_ctrl));
  2052. REG_SET_SLICE(miv2_mp_ctrl, MP_AUTO_UPDATE, 1);
  2053. REG_SET_SLICE(miv2_mp_ctrl, MP_INIT_BASE_EN, 1);
  2054. REG_SET_SLICE(miv2_mp_ctrl, MP_INIT_OFFSET_EN, 1);
  2055. isp_write_reg(dev, REG_ADDR(miv2_mp_ctrl), miv2_mp_ctrl);
  2056. }
  2057. isp_info("exit %s\n", __func__);
  2058. return 0;
  2059. #endif
  2060. }
  2061. int isp_s_2dnr(struct isp_ic_dev *dev)
  2062. {
  2063. #ifndef ISP_2DNR
  2064. //isp_err("unsupported function: %s\n", __func__);
  2065. return -EINVAL;
  2066. #else
  2067. struct isp_2dnr_context *dnr2 = &dev->dnr2;
  2068. u32 isp_denoise2d_control =
  2069. isp_read_reg(dev, REG_ADDR(isp_denoise2d_control));
  2070. u32 value, addr, strength;
  2071. u32 isp_ctrl;
  2072. int i;
  2073. /*isp_info("enter %s\n", __func__);*/
  2074. if (!dnr2->enable) {
  2075. #ifndef ISP_2DNR_V4
  2076. REG_SET_SLICE(isp_denoise2d_control, ISP_2DNR_ENABLE, 0);
  2077. isp_write_reg(dev, REG_ADDR(isp_denoise2d_control),
  2078. isp_denoise2d_control);
  2079. #else
  2080. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  2081. REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 0);
  2082. if((value & DENOISE3D_V20_TNR_ENABLE_MASK) == 0)
  2083. REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 0);
  2084. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl),
  2085. value);
  2086. #endif
  2087. return 0;
  2088. }
  2089. strength = isp_read_reg(dev, REG_ADDR(isp_denoise2d_strength));
  2090. REG_SET_SLICE(strength, ISP_2DNR_PRGAMMA_STRENGTH, dnr2->pre_gamma);
  2091. REG_SET_SLICE(strength, ISP_2DNR_STRENGTH, dnr2->strength);
  2092. isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength), strength);
  2093. addr = REG_ADDR(isp_denoise2d_sigma_y[0]);
  2094. for (i = 0; i < 60; i += 5) {
  2095. value = 0;
  2096. REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i]);
  2097. REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 1]);
  2098. REG_SET_SLICE(value, ISP_2DNR_SIGMAY2A,
  2099. dnr2->sigma[i + 2] >> 6);
  2100. isp_write_reg(dev, addr, value);
  2101. value = 0;
  2102. addr += 4;
  2103. REG_SET_SLICE(value, ISP_2DNR_SIGMAY2B,
  2104. dnr2->sigma[i + 2] & 0x3f);
  2105. REG_SET_SLICE(value, ISP_2DNR_SIGMAY0, dnr2->sigma[i + 3]);
  2106. REG_SET_SLICE(value, ISP_2DNR_SIGMAY1, dnr2->sigma[i + 4]);
  2107. isp_write_reg(dev, addr, value);
  2108. addr += 4;
  2109. }
  2110. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  2111. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  2112. REG_SET_SLICE(isp_denoise2d_control, ISP_2DNR_ENABLE, 1);
  2113. #if defined(ISP_2DNR_V2) || defined(ISP_2DNR_V4)
  2114. isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr), dnr2->sigma_sqr);
  2115. isp_write_reg(dev, REG_ADDR(isp_denoise2d_sigma_sqr_shd),
  2116. dnr2->sigma_sqr);
  2117. isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor),
  2118. dnr2->weight);
  2119. isp_write_reg(dev, REG_ADDR(isp_denoise2d_weight_mul_factor_shd),
  2120. dnr2->weight);
  2121. /* refer to HW spec for HBLANK */
  2122. //isp_write_reg(dev, REG_ADDR(isp_denoise2d_dummy_hblank), 0);
  2123. isp_write_reg(dev, REG_ADDR(isp_denoise2d_strength_shd), strength);
  2124. isp_write_reg(dev, REG_ADDR(isp_denoise2d_control_shd),
  2125. isp_denoise2d_control);
  2126. #endif
  2127. #ifndef ISP_2DNR_V4
  2128. isp_write_reg(dev, REG_ADDR(isp_denoise2d_control),
  2129. isp_denoise2d_control);
  2130. #else
  2131. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_blending));
  2132. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_OFFSET, dnr2->str_off);
  2133. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_MAX, dnr2->str_max);
  2134. REG_SET_SLICE(value, DENOISE3D_V20_NLM_STRENGTH_SLOPE, dnr2->str_slope);
  2135. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_blending), value);
  2136. value = isp_read_reg(dev, REG_ADDR(isp_denoise3d2_ctrl));
  2137. REG_SET_SLICE(value, DENOISE3D_V20_NLM_ENABLE, 1);
  2138. REG_SET_SLICE(value, DENOISE3D_V20_ENABLE, 1);
  2139. isp_write_reg(dev, REG_ADDR(isp_denoise3d2_ctrl),
  2140. value);
  2141. #endif
  2142. /*isp_info("exit %s\n", __func__);*/
  2143. return 0;
  2144. #endif
  2145. }
  2146. int isp_s_simp(struct isp_ic_dev *dev)
  2147. {
  2148. struct isp_simp_context *simp = &dev->simp;
  2149. u32 vi_ircl = isp_read_reg(dev, REG_ADDR(vi_ircl));
  2150. u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl));
  2151. u32 super_imp_ctrl = isp_read_reg(dev, REG_ADDR(super_imp_ctrl));
  2152. isp_info("enter %s\n", __func__);
  2153. REG_SET_SLICE(vi_ircl, MRV_VI_SIMP_SOFT_RST, 1);
  2154. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2155. if (!simp->enable) {
  2156. REG_SET_SLICE(vi_iccl, MRV_VI_SIMP_CLK_ENABLE, 0);
  2157. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  2158. return 0;
  2159. }
  2160. REG_SET_SLICE(vi_ircl, MRV_VI_SIMP_SOFT_RST, 0);
  2161. isp_write_reg(dev, REG_ADDR(super_imp_offset_x), simp->x);
  2162. isp_write_reg(dev, REG_ADDR(super_imp_offset_y), simp->y);
  2163. isp_write_reg(dev, REG_ADDR(super_imp_color_y), simp->r);
  2164. isp_write_reg(dev, REG_ADDR(super_imp_color_cb), simp->g);
  2165. isp_write_reg(dev, REG_ADDR(super_imp_color_cr), simp->b);
  2166. REG_SET_SLICE(super_imp_ctrl, MRV_SI_TRANSPARENCY_MODE,
  2167. simp->transparency_mode);
  2168. REG_SET_SLICE(super_imp_ctrl, MRV_SI_REF_IMAGE, simp->ref_image);
  2169. isp_write_reg(dev, REG_ADDR(super_imp_ctrl), super_imp_ctrl);
  2170. isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2171. REG_SET_SLICE(vi_iccl, MRV_VI_SIMP_CLK_ENABLE, 1);
  2172. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  2173. isp_info("exit %s\n", __func__);
  2174. return 0;
  2175. }
  2176. int isp_s_cproc(struct isp_ic_dev *dev)
  2177. {
  2178. struct isp_cproc_context *cproc = &dev->cproc;
  2179. u32 vi_iccl = isp_read_reg(dev, REG_ADDR(vi_iccl));
  2180. u32 cproc_ctrl = isp_read_reg(dev, REG_ADDR(cproc_ctrl));
  2181. //REG_SET_SLICE(vi_ircl, MRV_VI_CP_SOFT_RST, 1);
  2182. //isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2183. //if there is no shd register. should update cporc register in isp frame end irq.
  2184. #ifndef ISP_CPROC_SHD
  2185. if(dev->cproc.changed || !is_isp_enable(dev))
  2186. {
  2187. #endif
  2188. /*isp_info("enter %s %d\n", __func__, cproc->enable);*/
  2189. if (!cproc->enable) {
  2190. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_ENABLE, 0);
  2191. /* REG_SET_SLICE(vi_iccl, MRV_VI_CP_CLK_ENABLE, 0); */
  2192. /* isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl); */
  2193. isp_write_reg(dev, REG_ADDR(cproc_ctrl), cproc_ctrl);
  2194. return 0;
  2195. }
  2196. //REG_SET_SLICE(vi_ircl, MRV_VI_CP_SOFT_RST, 0);
  2197. //isp_write_reg(dev, REG_ADDR(vi_ircl), vi_ircl);
  2198. isp_write_reg(dev, REG_ADDR(cproc_contrast), cproc->contrast);
  2199. isp_write_reg(dev, REG_ADDR(cproc_brightness), cproc->brightness);
  2200. isp_write_reg(dev, REG_ADDR(cproc_saturation), cproc->saturation);
  2201. isp_write_reg(dev, REG_ADDR(cproc_hue), cproc->hue);
  2202. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_ENABLE, 1);
  2203. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_C_OUT_RANGE,
  2204. cproc->c_out_full);
  2205. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_Y_OUT_RANGE,
  2206. cproc->y_out_full);
  2207. REG_SET_SLICE(cproc_ctrl, MRV_CPROC_CPROC_Y_IN_RANGE, cproc->y_in_full);
  2208. REG_SET_SLICE(vi_iccl, MRV_VI_CP_CLK_ENABLE, 1);
  2209. isp_write_reg(dev, REG_ADDR(vi_iccl), vi_iccl);
  2210. isp_write_reg(dev, REG_ADDR(cproc_ctrl), cproc_ctrl);
  2211. #ifndef ISP_CPROC_SHD
  2212. dev->cproc.changed = false;
  2213. } else {
  2214. dev->cproc.changed = true;
  2215. }
  2216. #endif
  2217. /*isp_info("exit %s\n", __func__);*/
  2218. return 0;
  2219. }
  2220. int isp_s_elawb(struct isp_ic_dev *dev)
  2221. {
  2222. struct isp_elawb_context *elawb = &dev->elawb;
  2223. u32 awb_meas_mode = isp_read_reg(dev, REG_ADDR(awb_meas_mode));
  2224. u32 isp_imsc = isp_read_reg(dev, REG_ADDR(isp_imsc));
  2225. u32 id = elawb->id;
  2226. u32 data;
  2227. if (!elawb->enable) {
  2228. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_IRQ_ENABLE, 0);
  2229. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_EN, 0);
  2230. isp_write_reg(dev, REG_ADDR(awb_meas_mode), awb_meas_mode);
  2231. isp_write_reg(dev, REG_ADDR(isp_imsc),
  2232. isp_imsc & ~MRV_ISP_IMSC_AWB_DONE_MASK);
  2233. return 0;
  2234. }
  2235. isp_write_reg(dev, REG_ADDR(awb_meas_h_offs), elawb->window.x);
  2236. isp_write_reg(dev, REG_ADDR(awb_meas_v_offs), elawb->window.y);
  2237. isp_write_reg(dev, REG_ADDR(awb_meas_h_size), elawb->window.width);
  2238. isp_write_reg(dev, REG_ADDR(awb_meas_v_size), elawb->window.height);
  2239. if (id > 0 && id < 9) {
  2240. isp_write_reg(dev, REG_ADDR(awb_meas_center[id - 1].x),
  2241. elawb->info[id - 1].x);
  2242. isp_write_reg(dev, REG_ADDR(awb_meas_center[id - 1].y),
  2243. elawb->info[id - 1].y);
  2244. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a1),
  2245. elawb->info[id - 1].a1);
  2246. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a2),
  2247. elawb->info[id - 1].a2);
  2248. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a3),
  2249. elawb->info[id - 1].a3);
  2250. isp_write_reg(dev, REG_ADDR(awb_meas_axis[id - 1].a4),
  2251. elawb->info[id - 1].a4);
  2252. isp_write_reg(dev, REG_ADDR(awb_meas_rmax[id - 1]),
  2253. elawb->info[id - 1].r_max_sqr);
  2254. }
  2255. data = 0;
  2256. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_R, elawb->r);
  2257. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_B, elawb->b);
  2258. isp_write_reg(dev, REG_ADDR(isp_awb_gain_rb), data);
  2259. data = 0;
  2260. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_GR, elawb->gr);
  2261. REG_SET_SLICE(data, MRV_ISP_AWB_GAIN_GB, elawb->gb);
  2262. isp_write_reg(dev, REG_ADDR(isp_awb_gain_g), data);
  2263. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_IRQ_ENABLE, 1);
  2264. REG_SET_SLICE(awb_meas_mode, ISP_AWB_MEAS_EN, 1);
  2265. isp_write_reg(dev, REG_ADDR(awb_meas_mode), awb_meas_mode);
  2266. isp_write_reg(dev, REG_ADDR(isp_imsc),
  2267. isp_imsc | MRV_ISP_IMSC_AWB_DONE_MASK);
  2268. return 0;
  2269. }
  2270. int isp_ioc_qcap(struct isp_ic_dev *dev, void __user *args)
  2271. {
  2272. /* use public VIDIOC_QUERYCAP to query the type of v4l-subdevs. */
  2273. #ifdef __KERNEL__
  2274. #ifndef USE_FPGA
  2275. struct v4l2_capability *cap = (struct v4l2_capability *)args;
  2276. strcpy((char *)cap->driver, "viv_isp_subdev");
  2277. cap->bus_info[0] = (__u8)dev->id;//isp channel id
  2278. #else
  2279. struct v4l2_capability cap;
  2280. strcpy((char *)cap.driver, "viv_isp_subdev");
  2281. cap.bus_info[0] = (__u8)dev->id;//isp channel id
  2282. isp_info("enter %s viv_isp_subdev\n", __func__);
  2283. viv_check_retval(copy_to_user
  2284. ((struct v4l2_capability *)args, &cap, sizeof(cap)));
  2285. #endif
  2286. #endif
  2287. return 0;
  2288. }
  2289. int isp_ioc_g_status(struct isp_ic_dev *dev, void __user *args)
  2290. {
  2291. u32 val = 0;
  2292. /* val = isp_read_reg(REG_ADDR(isp_feature_version)); */
  2293. viv_check_retval(copy_to_user(args, &val, sizeof(val)));
  2294. return 0;
  2295. }
  2296. static u32 getScaleFactor(u32 src, u32 dst)
  2297. {
  2298. if (dst > src) {
  2299. return ((65536 * (src - 1)) / (dst - 1));
  2300. } else if (dst < src) {
  2301. return ((65536 * (dst - 1)) / (src - 1)) + 1;
  2302. }
  2303. return 65536;
  2304. }
  2305. int isp_set_scaling(int id, struct isp_ic_dev *dev, bool stabilization, bool crop)
  2306. {
  2307. u32 addr, ctrl;
  2308. u32 iw, ih, ow, oh;
  2309. u32 inputWidth, inputHeight, outputWidth, outputHeight;
  2310. u32 scale_hy, scale_hcb, scale_hcr, scale_vy, scale_vc;
  2311. struct isp_mi_data_path_context *path = &dev->mi.path[id];
  2312. if (crop) { //enabled crop.Do not need to scaler.
  2313. isp_info("%s:The crop enabled ,So does not need to do scaler.\n", __func__);
  2314. return 0;
  2315. }
  2316. if (id == IC_MI_PATH_MAIN) { /* mp */
  2317. addr = REG_ADDR(mrsz_ctrl);
  2318. } else if (id == IC_MI_PATH_SELF) { /* sp */
  2319. addr = REG_ADDR(srsz_ctrl);
  2320. } else if (id == IC_MI_PATH_SELF2) { /* sp2 */
  2321. addr = REG_ADDR(srsz2_ctrl);
  2322. } else {
  2323. return -EFAULT;
  2324. }
  2325. inputWidth = path->in_width;
  2326. inputHeight = path->in_height;
  2327. outputWidth = path->out_width;
  2328. outputHeight = path->out_height;
  2329. if (stabilization) { /* enabled image stabilization. */
  2330. inputWidth = isp_read_reg(dev, REG_ADDR(isp_is_h_size));
  2331. inputHeight = isp_read_reg(dev, REG_ADDR(isp_is_v_size));
  2332. }
  2333. ctrl = isp_read_reg(dev, addr);
  2334. iw = inputWidth / 2;
  2335. ih = inputHeight;
  2336. ow = outputWidth / 2;
  2337. oh = outputHeight;
  2338. switch (path->in_mode) {
  2339. case IC_MI_DATAMODE_YUV422:
  2340. oh = outputHeight;
  2341. break;
  2342. case IC_MI_DATAMODE_YUV420:
  2343. oh = outputHeight / 2; /* scale cbcr */
  2344. break;
  2345. case IC_MI_DATAMODE_YUV444:
  2346. oh = outputHeight;
  2347. break;
  2348. case IC_MI_DATAMODE_RGB888:
  2349. oh = outputHeight;
  2350. break;
  2351. default:
  2352. return -EFAULT;
  2353. }
  2354. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_ENABLE,
  2355. inputWidth != outputWidth);
  2356. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_ENABLE,
  2357. inputHeight != outputHeight);
  2358. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HY_UP, inputWidth < outputWidth);
  2359. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VY_UP, inputHeight < outputHeight);
  2360. scale_hy = getScaleFactor(inputWidth, outputWidth);
  2361. scale_vy = getScaleFactor(inputHeight, outputHeight);
  2362. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_ENABLE, iw != ow);
  2363. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_ENABLE, ih != oh);
  2364. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_HC_UP, iw < ow);
  2365. REG_SET_SLICE(ctrl, MRV_MRSZ_SCALE_VC_UP, ih < oh);
  2366. scale_hcr = getScaleFactor(iw, ow);
  2367. scale_hcb = getScaleFactor(iw, ow);
  2368. scale_vc = getScaleFactor(ih, oh);
  2369. /*Need to update immediately*/
  2370. REG_SET_SLICE(ctrl, MRV_MRSZ_CFG_UPD, 1);
  2371. if (id == IC_MI_PATH_MAIN) {
  2372. isp_write_reg(dev, REG_ADDR(mrsz_scale_vc), scale_vc);
  2373. isp_write_reg(dev, REG_ADDR(mrsz_scale_vy), scale_vy);
  2374. isp_write_reg(dev, REG_ADDR(mrsz_scale_hcr), scale_hcr);
  2375. isp_write_reg(dev, REG_ADDR(mrsz_scale_hcb), scale_hcb);
  2376. isp_write_reg(dev, REG_ADDR(mrsz_scale_hy), scale_hy);
  2377. isp_write_reg(dev, REG_ADDR(mrsz_ctrl), ctrl);
  2378. } else if (id == IC_MI_PATH_SELF) {
  2379. isp_write_reg(dev, REG_ADDR(srsz_scale_vc), scale_vc);
  2380. isp_write_reg(dev, REG_ADDR(srsz_scale_vy), scale_vy);
  2381. isp_write_reg(dev, REG_ADDR(srsz_scale_hcr), scale_hcr);
  2382. isp_write_reg(dev, REG_ADDR(srsz_scale_hcb), scale_hcb);
  2383. isp_write_reg(dev, REG_ADDR(srsz_scale_hy), scale_hy);
  2384. isp_write_reg(dev, REG_ADDR(srsz_ctrl), ctrl);
  2385. } else if (id == IC_MI_PATH_SELF2) {
  2386. isp_write_reg(dev, REG_ADDR(srsz2_scale_vc), scale_vc);
  2387. isp_write_reg(dev, REG_ADDR(srsz2_scale_vy), scale_vy);
  2388. isp_write_reg(dev, REG_ADDR(srsz2_scale_hcr), scale_hcr);
  2389. isp_write_reg(dev, REG_ADDR(srsz2_scale_hcb), scale_hcb);
  2390. isp_write_reg(dev, REG_ADDR(srsz2_scale_hy), scale_hy);
  2391. isp_write_reg(dev, REG_ADDR(srsz2_ctrl), ctrl);
  2392. }
  2393. return 0;
  2394. }
  2395. typedef struct isp_crop_reg_s {
  2396. u32 crop_ctrl_addr;
  2397. u32 crop_x_dir_addr;
  2398. u32 crop_y_dir_addr;
  2399. } isp_crop_reg_t;
  2400. int isp_set_crop(struct isp_ic_dev *dev)
  2401. {
  2402. long ret = 0;
  2403. u32 crop_ctrl, crop_x_dir, crop_y_dir;
  2404. u8 i;
  2405. isp_crop_reg_t crop_reg[ISP_MI_PATH_SP2_BP + 1] = {
  2406. {
  2407. REG_ADDR(mrsz_ctrl),
  2408. REG_ADDR(mrsz_phase_crop_x),
  2409. REG_ADDR(mrsz_phase_crop_y)
  2410. },
  2411. {
  2412. REG_ADDR(srsz_ctrl),
  2413. REG_ADDR(srsz_phase_crop_x),
  2414. REG_ADDR(srsz_phase_crop_y)
  2415. },
  2416. {
  2417. REG_ADDR(srsz2_ctrl),
  2418. REG_ADDR(srsz2_phase_crop_x),
  2419. REG_ADDR(srsz2_phase_crop_y)
  2420. }
  2421. };
  2422. struct isp_crop_context *crop = dev->crop;
  2423. for ( i = 0; i <= ISP_MI_PATH_SP2_BP; i++) {
  2424. crop_ctrl = isp_read_reg(dev, crop_reg[i].crop_ctrl_addr);
  2425. crop_x_dir = isp_read_reg(dev, crop_reg[i].crop_x_dir_addr);
  2426. crop_y_dir = isp_read_reg(dev, crop_reg[i].crop_y_dir_addr);
  2427. if (!crop[i].enabled) {
  2428. #ifndef ISP8000NANO_BASE
  2429. REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CROP_ENABLE, 0);
  2430. #endif
  2431. isp_write_reg(dev, crop_reg[i].crop_ctrl_addr, crop_ctrl);
  2432. continue;
  2433. }
  2434. REG_SET_SLICE(crop_x_dir, MRV_MRSZ_PHASE_H_START, crop[i].window.x);
  2435. REG_SET_SLICE(crop_y_dir, MRV_MRSZ_PHASE_V_START, crop[i].window.y);
  2436. REG_SET_SLICE(crop_x_dir, MRV_MRSZ_PHASE_H_END, crop[i].window.width + crop[i].window.x - 1); //x_end = x + width -1
  2437. REG_SET_SLICE(crop_y_dir, MRV_MRSZ_PHASE_V_END, crop[i].window.height + crop[i].window.y - 1); //y_end = y + height -1
  2438. #ifndef ISP8000NANO_BASE
  2439. REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CROP_ENABLE, 1);
  2440. /*Need to update immediately*/
  2441. REG_SET_SLICE(crop_ctrl, MRV_MRSZ_CFG_UPD, 1);
  2442. #endif
  2443. isp_write_reg(dev, crop_reg[i].crop_x_dir_addr, crop_x_dir);
  2444. isp_write_reg(dev, crop_reg[i].crop_y_dir_addr, crop_y_dir);
  2445. isp_write_reg(dev, crop_reg[i].crop_ctrl_addr, crop_ctrl);
  2446. }
  2447. return ret;
  2448. }
  2449. int isp_ioc_g_feature(struct isp_ic_dev *dev, void __user *args)
  2450. {
  2451. u32 val = 0;
  2452. #ifdef ISP_EE
  2453. val |= ISP_EE_SUPPORT;
  2454. #endif
  2455. #ifdef ISP_WDR3
  2456. val |= ISP_WDR3_SUPPORT;
  2457. #endif
  2458. #ifdef ISP_2DNR
  2459. val |= ISP_2DNR_SUPPORT;
  2460. #endif
  2461. #ifdef ISP_3DNR
  2462. val |= ISP_3DNR_SUPPORT;
  2463. #endif
  2464. #ifdef ISP_WDR_V3
  2465. val |= ISP_WDR3_SUPPORT;
  2466. #endif
  2467. #ifdef ISP_MIV2
  2468. val |= ISP_MIV2_SUPPORT;
  2469. #endif
  2470. #ifdef ISP_AEV2
  2471. val |= ISP_AEV2_SUPPORT;
  2472. #endif
  2473. #ifdef ISP_HDR_STITCH
  2474. val |= ISP_HDR_STITCH_SUPPORT;
  2475. #endif
  2476. viv_check_retval(copy_to_user(args, &val, sizeof(val)));
  2477. return 0;
  2478. }
  2479. int isp_ioc_g_feature_veresion(struct isp_ic_dev *dev, void __user *args)
  2480. {
  2481. u32 val = 0;
  2482. /* val = isp_read_reg(REG_ADDR(isp_feature_version)); */
  2483. viv_check_retval(copy_to_user(args, &val, sizeof(val)));
  2484. return 0;
  2485. }
  2486. static long isp_get_extmem(struct isp_ic_dev *dev, void __user *args)
  2487. {
  2488. #define UT_USED_SIZE 0x01000000
  2489. long ret = 0;
  2490. struct isp_extmem_info ext_mem;
  2491. dev->ut_addr = dma_alloc_coherent(dev->device, UT_USED_SIZE, &dev->ut_phy_addr, GFP_KERNEL);
  2492. if (dev->ut_addr != NULL) {
  2493. ext_mem.addr = dev->ut_phy_addr;
  2494. ext_mem.size = UT_USED_SIZE;
  2495. } else {
  2496. return -1;
  2497. }
  2498. ret = copy_to_user(args, &ext_mem, sizeof(struct isp_extmem_info));
  2499. return ret;
  2500. }
  2501. long isp_priv_ioctl(struct isp_ic_dev *dev, unsigned int cmd, void __user *args)
  2502. {
  2503. int ret = -1;
  2504. if (!dev) {
  2505. return ret;
  2506. }
  2507. /*pr_info("[%s:%d]cmd 0x%08x\n", __func__, __LINE__, cmd);*/
  2508. switch (cmd) {
  2509. case ISPIOC_RESET:
  2510. if((ret = isp_mi_stop(dev)) != 0 )
  2511. {
  2512. pr_err("[%s:%d]stop mi error before resetting!\n", __func__, __LINE__);
  2513. break;
  2514. }
  2515. if((ret = isp_stop_stream(dev)) != 0)
  2516. {
  2517. pr_err("[%s:%d]stop isp stream before resetting!\n", __func__, __LINE__);
  2518. break;
  2519. }
  2520. ret = isp_reset(dev);
  2521. break;
  2522. case ISPIOC_WRITE_REG:
  2523. ret = isp_ioc_write_reg(dev, args);
  2524. break;
  2525. case ISPIOC_READ_REG:
  2526. ret = isp_ioc_read_reg(dev, args);
  2527. break;
  2528. case ISPIOC_GET_MIS:
  2529. ret = isp_ioc_read_mis(dev, args);
  2530. break;
  2531. case ISPIOC_ENABLE_TPG:
  2532. ret = isp_enable_tpg(dev);
  2533. break;
  2534. case ISPIOC_DISABLE_TPG:
  2535. ret = isp_disable_tpg(dev);
  2536. break;
  2537. case ISPIOC_ENABLE_BLS:
  2538. ret = isp_enable_bls(dev);
  2539. break;
  2540. case ISPIOC_DISABLE_BLS:
  2541. ret = isp_disable_bls(dev);
  2542. break;
  2543. case ISPIOC_START_DMA_READ:
  2544. ret = isp_ioc_start_dma_read(dev, args);
  2545. break;
  2546. case ISPIOC_CFG_DMA:
  2547. ret = isp_ioc_cfg_dma(dev, args);
  2548. break;
  2549. case ISPIOC_MI_STOP:
  2550. ret = isp_mi_stop(dev);
  2551. break;
  2552. case ISPIOC_DISABLE_ISP_OFF:
  2553. ret = isp_ioc_disable_isp_off(dev, args);
  2554. break;
  2555. case ISPIOC_ISP_STOP:
  2556. ret = isp_stop_stream(dev);
  2557. if(!ret) {
  2558. dev->streaming = false;
  2559. }
  2560. break;
  2561. case ISPIOC_ENABLE:
  2562. ret = isp_enable(dev);
  2563. break;
  2564. case ISPIOC_DISABLE:
  2565. ret = isp_disable(dev);
  2566. break;
  2567. case ISPIOC_ISP_STATUS:{
  2568. bool enable = is_isp_enable(dev);
  2569. viv_check_retval(copy_to_user
  2570. (args, &enable, sizeof(bool)));
  2571. ret = 0;
  2572. break;
  2573. }
  2574. case ISPIOC_ENABLE_LSC:
  2575. ret = isp_enable_lsc(dev);
  2576. break;
  2577. case ISPIOC_DISABLE_LSC:
  2578. ret = isp_disable_lsc(dev);
  2579. break;
  2580. case ISPIOC_S_DIGITAL_GAIN:
  2581. viv_check_retval(copy_from_user
  2582. (&dev->dgain, args, sizeof(dev->dgain)));
  2583. ret = isp_s_digital_gain(dev);
  2584. break;
  2585. #ifdef ISP_DEMOSAIC2
  2586. case ISPIOC_S_DMSC_INTP:
  2587. viv_check_retval(copy_from_user
  2588. (&dev->demosaic.intp, args,
  2589. sizeof(dev->demosaic.intp)));
  2590. ret = isp_set_dmsc_intp(dev);
  2591. break;
  2592. case ISPIOC_S_DMSC_DMOI:
  2593. viv_check_retval(copy_from_user
  2594. (&dev->demosaic.demoire, args,
  2595. sizeof(dev->demosaic.demoire)));
  2596. ret = isp_set_dmsc_dmoi(dev);
  2597. break;
  2598. case ISPIOC_S_DMSC_SKIN:
  2599. viv_check_retval(copy_from_user
  2600. (&dev->demosaic.skin, args,
  2601. sizeof(dev->demosaic.skin)));
  2602. ret = isp_set_dmsc_skin(dev);
  2603. break;
  2604. case ISPIOC_S_DMSC_SHAP:
  2605. viv_check_retval(copy_from_user
  2606. (&dev->demosaic.sharpen, args,
  2607. sizeof(dev->demosaic.sharpen)));
  2608. ret = isp_set_dmsc_sharpen(dev);
  2609. break;
  2610. case ISPIOC_S_DMSC_SHAP_LINE:
  2611. viv_check_retval(copy_from_user
  2612. (&dev->demosaic.sharpenLine, args,
  2613. sizeof(dev->demosaic.sharpenLine)));
  2614. ret = isp_set_dmsc_sharpen_line(dev);
  2615. break;
  2616. case ISPIOC_S_DMSC_CAC:
  2617. viv_check_retval(copy_from_user
  2618. (&dev->cac, args, sizeof(dev->cac)));
  2619. ret = isp_set_dmsc_cac(dev);
  2620. break;
  2621. case ISPIOC_S_DMSC_DEPURPLE:
  2622. viv_check_retval(copy_from_user
  2623. (&dev->demosaic.depurple, args,
  2624. sizeof(dev->demosaic.depurple)));
  2625. ret = isp_set_dmsc_depurple(dev);
  2626. break;
  2627. case ISPIOC_S_DMSC_GFILTER:
  2628. viv_check_retval(copy_from_user
  2629. (&dev->demosaic.gFilter, args,
  2630. sizeof(dev->demosaic.gFilter)));
  2631. ret = isp_set_dmsc_gfilter(dev);
  2632. break;
  2633. case ISPIOC_S_DMSC:
  2634. viv_check_retval(copy_from_user
  2635. (&dev->demosaic, args, sizeof(dev->demosaic)));
  2636. ret = isp_s_dmsc(dev);
  2637. break;
  2638. #endif
  2639. case ISPIOC_ENABLE_AWB:
  2640. ret = isp_enable_awb(dev);
  2641. break;
  2642. case ISPIOC_DISABLE_AWB:
  2643. ret = isp_disable_awb(dev);
  2644. break;
  2645. case ISPIOC_ENABLE_WB:
  2646. ret = isp_enable_wb(dev, 1);
  2647. break;
  2648. case ISPIOC_DISABLE_WB:
  2649. ret = isp_enable_wb(dev, 0);
  2650. break;
  2651. case ISPIOC_ENABLE_GAMMA_OUT:
  2652. ret = isp_enable_gamma_out(dev, 1);
  2653. break;
  2654. case ISPIOC_DISABLE_GAMMA_OUT:
  2655. ret = isp_enable_gamma_out(dev, 0);
  2656. break;
  2657. #if defined(ISP_3DNR) || defined(ISP_3DNR_V2_V1)
  2658. case ISPIOC_R_3DNR:
  2659. viv_check_retval(copy_from_user
  2660. (&dev->dnr3, args, sizeof(dev->dnr3)));
  2661. ret = isp_r_3dnr(dev);
  2662. break;
  2663. #endif
  2664. case ISPIOC_S_IS:
  2665. viv_check_retval(copy_from_user
  2666. (&dev->is, args, sizeof(dev->is)));
  2667. ret = isp_s_is(dev);
  2668. break;
  2669. case ISPIOC_S_RAW_IS:
  2670. viv_check_retval(copy_from_user
  2671. (&dev->rawis, args, sizeof(dev->rawis)));
  2672. ret = isp_s_raw_is(dev);
  2673. break;
  2674. case ISPIOC_S_CC:
  2675. viv_check_retval(copy_from_user
  2676. (&dev->cc, args, sizeof(dev->cc)));
  2677. ret = isp_s_cc(dev);
  2678. break;
  2679. case ISPIOC_S_EE:
  2680. viv_check_retval(copy_from_user
  2681. (&dev->ee, args, sizeof(dev->ee)));
  2682. ret = isp_s_ee(dev);
  2683. break;
  2684. case ISPIOC_S_IE:
  2685. viv_check_retval(copy_from_user
  2686. (&dev->ie, args, sizeof(dev->ie)));
  2687. ret = isp_s_ie(dev);
  2688. break;
  2689. case ISPIOC_S_TPG:
  2690. viv_check_retval(copy_from_user
  2691. (&dev->tpg, args, sizeof(dev->tpg)));
  2692. ret = isp_s_tpg(dev);
  2693. break;
  2694. case ISPIOC_S_BLS:
  2695. viv_check_retval(copy_from_user
  2696. (&dev->bls, args, sizeof(dev->bls)));
  2697. ret = isp_s_bls(dev);
  2698. break;
  2699. case ISPIOC_BYPASS_MCM:
  2700. viv_check_retval(copy_from_user
  2701. (&dev->mcm, args, sizeof(dev->mcm)));
  2702. ret = isp_bypass_mcm(dev);
  2703. break;
  2704. case ISPIOC_S_MCM_WR:
  2705. viv_check_retval(copy_from_user
  2706. (&dev->mcm, args, sizeof(dev->mcm)));
  2707. ret = isp_s_mcm_wr(dev);
  2708. break;
  2709. case ISPIOC_S_MUX:
  2710. viv_check_retval(copy_from_user
  2711. (&dev->mux, args, sizeof(dev->mux)));
  2712. ret = isp_s_mux(dev);
  2713. break;
  2714. case ISPIOC_S_AWB:
  2715. viv_check_retval(copy_from_user
  2716. (&dev->awb, args, sizeof(dev->awb)));
  2717. ret = isp_s_awb(dev);
  2718. break;
  2719. case ISPIOC_S_LSC_TBL:
  2720. viv_check_retval(copy_from_user
  2721. (&dev->lsc, args, sizeof(dev->lsc)));
  2722. ret = isp_s_lsc_tbl(dev);
  2723. break;
  2724. case ISPIOC_S_LSC_SEC:
  2725. viv_check_retval(copy_from_user
  2726. (&dev->lsc, args, sizeof(dev->lsc)));
  2727. ret = isp_s_lsc_sec(dev);
  2728. break;
  2729. case ISPIOC_S_DPF:
  2730. viv_check_retval(copy_from_user
  2731. (&dev->dpf, args, sizeof(dev->dpf)));
  2732. ret = isp_s_dpf(dev);
  2733. break;
  2734. case ISPIOC_S_EXP:
  2735. viv_check_retval(copy_from_user
  2736. (&dev->exp, args, sizeof(dev->exp)));
  2737. ret = isp_s_exp(dev);
  2738. break;
  2739. case ISPIOC_S_HDREXP:
  2740. viv_check_retval(copy_from_user
  2741. (&dev->hdrexp, args, sizeof(dev->hdrexp)));
  2742. ret = isp_s_hdrexp(dev);
  2743. break;
  2744. case ISPIOC_S_CNR:
  2745. viv_check_retval(copy_from_user
  2746. (&dev->cnr, args, sizeof(dev->cnr)));
  2747. ret = isp_s_cnr(dev);
  2748. break;
  2749. case ISPIOC_S_FLT:
  2750. {
  2751. viv_check_retval(copy_from_user
  2752. (&dev->flt, args, sizeof(dev->flt)));
  2753. ret = isp_s_flt(dev);
  2754. break;
  2755. }
  2756. case ISPIOC_S_CAC:
  2757. viv_check_retval(copy_from_user
  2758. (&dev->cac, args, sizeof(dev->cac)));
  2759. ret = isp_s_cac(dev);
  2760. break;
  2761. case ISPIOC_S_DEG:
  2762. viv_check_retval(copy_from_user
  2763. (&dev->deg, args, sizeof(dev->deg)));
  2764. ret = isp_s_deg(dev);
  2765. break;
  2766. case ISPIOC_S_VSM:
  2767. viv_check_retval(copy_from_user
  2768. (&dev->vsm, args, sizeof(dev->vsm)));
  2769. ret = isp_s_vsm(dev);
  2770. break;
  2771. case ISPIOC_S_AFM:
  2772. viv_check_retval(copy_from_user
  2773. (&dev->afm, args, sizeof(dev->afm)));
  2774. ret = isp_s_afm(dev);
  2775. break;
  2776. case ISPIOC_S_HDR:
  2777. viv_check_retval(copy_from_user
  2778. (&dev->hdr, args, sizeof(dev->hdr)));
  2779. ret = isp_s_hdr(dev);
  2780. break;
  2781. case ISPIOC_ENABLE_HDR:
  2782. viv_check_retval(copy_from_user
  2783. (&dev->hdr, args, sizeof(dev->hdr)));
  2784. ret = isp_enable_hdr(dev);
  2785. break;
  2786. case ISPIOC_DISABLE_HDR:
  2787. viv_check_retval(copy_from_user
  2788. (&dev->hdr, args, sizeof(dev->hdr)));
  2789. ret = isp_disable_hdr(dev);
  2790. break;
  2791. case ISPIOC_S_HIST:
  2792. viv_check_retval(copy_from_user
  2793. (&dev->hist, args, sizeof(dev->hist)));
  2794. ret = isp_s_hist(dev);
  2795. break;
  2796. case ISPIOC_S_HDRHIST:
  2797. viv_check_retval(copy_from_user
  2798. (&dev->hdrhist, args, sizeof(dev->hdrhist)));
  2799. ret = isp_s_hdrhist(dev);
  2800. break;
  2801. #ifdef ISP_HIST64
  2802. case ISPIOC_S_HIST64:
  2803. viv_check_retval(copy_from_user
  2804. (&dev->hist64, args, sizeof(dev->hist64)));
  2805. ret = isp_s_hist64(dev);
  2806. break;
  2807. case ISPIOC_U_HIST64:
  2808. viv_check_retval(copy_from_user
  2809. (&dev->hist64, args, sizeof(dev->hist64)));
  2810. ret = isp_update_hist64(dev);
  2811. break;
  2812. #endif
  2813. case ISPIOC_S_DPCC:
  2814. viv_check_retval(copy_from_user
  2815. (&dev->dpcc, args, sizeof(dev->dpcc)));
  2816. ret = isp_s_dpcc(dev);
  2817. break;
  2818. case ISPIOC_ENABLE_WDR3:
  2819. ret = isp_enable_wdr3(dev);
  2820. break;
  2821. case ISPIOC_DISABLE_WDR3:
  2822. ret = isp_disable_wdr3(dev);
  2823. break;
  2824. case ISPIOC_U_WDR3:
  2825. viv_check_retval(copy_from_user
  2826. (&dev->wdr3, args, sizeof(dev->wdr3)));
  2827. ret = isp_u_wdr3(dev);
  2828. break;
  2829. case ISPIOC_S_WDR3:
  2830. viv_check_retval(copy_from_user
  2831. (&dev->wdr3, args, sizeof(dev->wdr3)));
  2832. ret = isp_s_wdr3(dev);
  2833. break;
  2834. #ifdef ISP_WDR_V4
  2835. case ISPIOC_ENABLE_WDR4:
  2836. ret = isp_enable_wdr4(dev);
  2837. break;
  2838. case ISPIOC_DISABLE_WDR4:
  2839. ret = isp_disable_wdr4(dev);
  2840. break;
  2841. case ISPIOC_U_WDR4:
  2842. viv_check_retval(copy_from_user
  2843. (&dev->wdr4, args, sizeof(dev->wdr4)));
  2844. ret = isp_u_wdr4(dev);
  2845. break;
  2846. case ISPIOC_S_WDR4:
  2847. viv_check_retval(copy_from_user
  2848. (&dev->wdr4, args, sizeof(dev->wdr4)));
  2849. ret = isp_s_wdr4(dev);
  2850. break;
  2851. #endif
  2852. case ISPIOC_S_EXP2:
  2853. viv_check_retval(copy_from_user
  2854. (&dev->exp2, args, sizeof(dev->exp2)));
  2855. ret = isp_s_exp2(dev);
  2856. break;
  2857. case ISPIOC_S_EXP2_INPUTSEL:
  2858. viv_check_retval(copy_from_user
  2859. (&dev->exp2.input_select, args,
  2860. sizeof(dev->exp2.input_select)));
  2861. ret = isp_s_exp2_inputsel(dev);
  2862. break;
  2863. case ISPIOC_S_EXP2_SIZERATIO: {
  2864. u32 ratio;
  2865. viv_check_retval(copy_from_user(&ratio, args, sizeof(ratio)));
  2866. ret = isp_s_exp2_sizeratio(dev, ratio);
  2867. break;
  2868. }
  2869. case ISPIOC_S_2DNR:
  2870. viv_check_retval(copy_from_user
  2871. (&dev->dnr2, args, sizeof(dev->dnr2)));
  2872. #ifdef ISP_2DNR_V5
  2873. ret = isp_tdnr_s_2dnr(dev);
  2874. #else
  2875. ret = isp_s_2dnr(dev);
  2876. #endif
  2877. break;
  2878. case ISPIOC_S_SIMP:
  2879. viv_check_retval(copy_from_user
  2880. (&dev->simp, args, sizeof(dev->simp)));
  2881. ret = isp_s_simp(dev);
  2882. break;
  2883. case ISPIOC_S_COMP:
  2884. viv_check_retval(copy_from_user
  2885. (&dev->comp, args, sizeof(dev->comp)));
  2886. ret = isp_s_comp(dev);
  2887. break;
  2888. case ISPIOC_S_CPROC:
  2889. viv_check_retval(copy_from_user
  2890. (&dev->cproc, args, sizeof(dev->cproc)));
  2891. ret = isp_s_cproc(dev);
  2892. break;
  2893. case ISPIOC_S_XTALK:
  2894. viv_check_retval(copy_from_user
  2895. (&dev->xtalk, args, sizeof(dev->xtalk)));
  2896. ret = isp_s_xtalk(dev);
  2897. break;
  2898. case ISPIOC_S_ELAWB:
  2899. viv_check_retval(copy_from_user
  2900. (&dev->elawb, args, sizeof(dev->elawb)));
  2901. ret = isp_s_elawb(dev);
  2902. break;
  2903. case ISPIOC_S_INPUT:
  2904. viv_check_retval(copy_from_user
  2905. (&dev->ctx, args, sizeof(dev->ctx)));
  2906. ret = isp_s_input(dev);
  2907. break;
  2908. case ISPIOC_S_DEMOSAIC:
  2909. viv_check_retval(copy_from_user
  2910. (&dev->ctx, args, sizeof(dev->ctx)));
  2911. ret = isp_s_demosaic(dev);
  2912. break;
  2913. case ISPIOC_MI_START:
  2914. viv_check_retval(copy_from_user
  2915. (&dev->mi, args, sizeof(dev->mi)));
  2916. ret = isp_mi_start(dev);
  2917. break;
  2918. case ISPIOC_S_HDR_WB:
  2919. viv_check_retval(copy_from_user
  2920. (&dev->hdr, args, sizeof(dev->hdr)));
  2921. ret = isp_s_hdr_wb(dev);
  2922. break;
  2923. case ISPIOC_S_HDR_BLS:
  2924. viv_check_retval(copy_from_user
  2925. (&dev->hdr, args, sizeof(dev->hdr)));
  2926. ret = isp_s_hdr_bls(dev);
  2927. break;
  2928. case ISPIOC_S_HDR_DIGITAL_GAIN:
  2929. viv_check_retval(copy_from_user
  2930. (&dev->hdr, args, sizeof(dev->hdr)));
  2931. // ret = isp_s_hdr_digal_gain(dev);
  2932. break;
  2933. case ISPIOC_S_GAMMA_OUT:{
  2934. viv_check_retval(copy_from_user
  2935. (&dev->gamma_out, args,
  2936. sizeof(dev->gamma_out)));
  2937. ret = isp_s_gamma_out(dev);
  2938. break;
  2939. }
  2940. case ISPIOC_SET_BUFFER:{
  2941. struct isp_buffer_context buf;
  2942. viv_check_retval(copy_from_user
  2943. (&buf, args, sizeof(buf)));
  2944. #if defined(__KERNEL__) && defined(ENABLE_IRQ)
  2945. if (dev->alloc)
  2946. ret = dev->alloc(dev, &buf);
  2947. #else
  2948. ret = isp_set_buffer(dev, &buf);
  2949. #endif
  2950. break;
  2951. }
  2952. case ISPIOC_SET_BP_BUFFER:{
  2953. struct isp_bp_buffer_context buf;
  2954. viv_check_retval(copy_from_user
  2955. (&buf, args, sizeof(buf)));
  2956. ret = isp_set_bp_buffer(dev, &buf);
  2957. break;
  2958. }
  2959. case ISPIOC_START_CAPTURE:{
  2960. u32 num;
  2961. viv_check_retval(copy_from_user
  2962. (&num, args, sizeof(num)));
  2963. ret = isp_start_stream(dev, num);
  2964. if(!ret) {
  2965. dev->streaming = true;
  2966. }
  2967. break;
  2968. }
  2969. #if defined(ISP_3DNR_V2) || defined(ISP_3DNR_V2_V1)
  2970. case ISPIOC_S_3DNR_CMP: {
  2971. viv_check_retval(
  2972. copy_from_user(&dev->dnr3.compress, args, sizeof(dev->dnr3.compress)));
  2973. ret = isp_s_3dnr_cmp(dev);
  2974. break;
  2975. }
  2976. #endif
  2977. #if defined(ISP_3DNR) || defined(ISP_3DNR_V2)
  2978. case ISPIOC_U_3DNR:{
  2979. struct isp_3dnr_update param;
  2980. viv_check_retval(copy_from_user
  2981. (&param, args, sizeof(param)));
  2982. ret = isp_u_3dnr(dev, &param);
  2983. break;
  2984. }
  2985. case ISPIOC_S_3DNR:
  2986. viv_check_retval(copy_from_user
  2987. (&dev->dnr3, args, sizeof(dev->dnr3)));
  2988. ret = isp_s_3dnr(dev);
  2989. break;
  2990. case ISPIOC_U_3DNR_STRENGTH: {
  2991. viv_check_retval(
  2992. copy_from_user(&dev->dnr3, args, sizeof(dev->dnr3)));
  2993. ret = isp_u_3dnr_strength(dev);
  2994. break;
  2995. }
  2996. case ISPIOC_S_3DNR_MOT:{
  2997. viv_check_retval(copy_from_user
  2998. (&dev->dnr3, args, sizeof(dev->dnr3)));
  2999. ret = isp_s_3dnr_motion(dev);
  3000. break;
  3001. }
  3002. case ISPIOC_S_3DNR_DLT:{
  3003. viv_check_retval(copy_from_user
  3004. (&dev->dnr3, args, sizeof(dev->dnr3)));
  3005. ret = isp_s_3dnr_delta(dev);
  3006. break;
  3007. }
  3008. case ISPIOC_G_3DNR:{
  3009. u32 avg;
  3010. ret = isp_g_3dnr(dev, &avg);
  3011. viv_check_retval(copy_to_user(args, &avg, sizeof(avg)));
  3012. break;
  3013. }
  3014. #endif
  3015. case ISPIOC_G_AWBMEAN:{
  3016. struct isp_awb_mean mean;
  3017. ret = isp_g_awbmean(dev, &mean);
  3018. viv_check_retval(copy_to_user
  3019. (args, &mean, sizeof(mean)));
  3020. break;
  3021. }
  3022. case ISPIOC_G_EXPMEAN:{
  3023. u8 mean[25];
  3024. ret = isp_g_expmean(dev, mean);
  3025. viv_check_retval(copy_to_user
  3026. (args, mean, sizeof(mean)));
  3027. break;
  3028. }
  3029. case ISPIOC_G_HDREXPMEAN:{
  3030. u8 mean[75];
  3031. ret = isp_g_hdrexpmean(dev, mean);
  3032. viv_check_retval(copy_to_user
  3033. (args, mean, sizeof(mean)));
  3034. break;
  3035. }
  3036. case ISPIOC_G_HISTMEAN:{
  3037. u32 mean[HIST_BIN_TOTAL];
  3038. ret = isp_g_histmean(dev, mean);
  3039. viv_check_retval(copy_to_user
  3040. (args, mean, sizeof(mean)));
  3041. break;
  3042. }
  3043. case ISPIOC_G_HDRHISTMEAN:{
  3044. u32 mean[48];
  3045. ret = isp_g_hdrhistmean(dev, mean);
  3046. viv_check_retval(copy_to_user
  3047. (args, mean, sizeof(mean)));
  3048. break;
  3049. }
  3050. #ifdef ISP_HIST64
  3051. case ISPIOC_G_HIST64MEAN:{
  3052. u32 mean[HIST64_BIN_TOTAL];
  3053. ret = isp_g_hist64mean(dev, mean);
  3054. viv_check_retval(copy_to_user
  3055. (args, mean, sizeof(mean)));
  3056. break;
  3057. }
  3058. case ISPIOC_G_HIST64VSTART_STATUS:{
  3059. u32 status = 0;
  3060. ret = isp_g_hist64_vstart_status(dev, &status);
  3061. viv_check_retval(copy_to_user
  3062. (args, &status, sizeof(status)));
  3063. break;
  3064. }
  3065. #endif
  3066. case ISPIOC_G_VSM:{
  3067. struct isp_vsm_result vsm;
  3068. ret = isp_g_vsm(dev, &vsm);
  3069. viv_check_retval(copy_to_user(args, &vsm, sizeof(vsm)));
  3070. break;
  3071. }
  3072. case ISPIOC_G_AFM:{
  3073. struct isp_afm_result afm;
  3074. ret = isp_g_afm(dev, &afm);
  3075. viv_check_retval(copy_to_user(args, &afm, sizeof(afm)));
  3076. break;
  3077. }
  3078. case ISPIOC_G_STATUS:
  3079. ret = isp_ioc_g_status(dev, args);
  3080. break;
  3081. case ISPIOC_G_FEATURE:
  3082. ret = isp_ioc_g_feature(dev, args);
  3083. break;
  3084. case ISPIOC_G_FEATURE_VERSION:
  3085. ret = isp_ioc_g_feature_veresion(dev, args);
  3086. break;
  3087. case ISPIOC_WDR_CONFIG:
  3088. viv_check_retval(copy_from_user
  3089. (&dev->wdr, args, sizeof(dev->wdr)));
  3090. ret = isp_s_wdr(dev);
  3091. break;
  3092. case ISPIOC_S_WDR_CURVE:
  3093. viv_check_retval(copy_from_user
  3094. (&dev->wdr, args, sizeof(dev->wdr)));
  3095. ret = isp_s_wdr_curve(dev);
  3096. break;
  3097. case ISPIOC_ENABLE_GCMONO:
  3098. viv_check_retval(copy_from_user
  3099. (&dev->gcmono.mode, args, sizeof(u32)));
  3100. ret = isp_enable_gcmono(dev);
  3101. break;
  3102. case ISPIOC_DISABLE_GCMONO:
  3103. ret = isp_disable_gcmono(dev);
  3104. break;
  3105. case ISPIOC_S_GCMONO:{
  3106. struct isp_gcmono_data *data;
  3107. #ifdef __KERNEL__
  3108. data = (struct isp_gcmono_data *)
  3109. kmalloc(sizeof(struct isp_gcmono_data), GFP_KERNEL);
  3110. #else
  3111. data = (struct isp_gcmono_data *)
  3112. malloc(sizeof(struct isp_gcmono_data));
  3113. #endif
  3114. if (data == NULL) {
  3115. isp_err("%s, malloc mem for rgb gamma failed.", __func__);
  3116. ret = -1;
  3117. } else {
  3118. viv_check_retval(copy_from_user
  3119. (data, args,
  3120. sizeof(struct
  3121. isp_gcmono_data)));
  3122. ret = isp_s_gcmono(dev, data);
  3123. #ifdef __KERNEL__
  3124. kfree(data);
  3125. #else
  3126. free(data);
  3127. #endif
  3128. }
  3129. break;
  3130. }
  3131. case ISPIOC_ENABLE_RGBGAMMA:
  3132. ret = isp_enable_rgbgamma(dev);
  3133. break;
  3134. case ISPIOC_DISABLE_RGBGAMMA:
  3135. ret = isp_disable_rgbgamma(dev);
  3136. break;
  3137. case ISPIOC_S_RGBGAMMA:{
  3138. struct isp_rgbgamma_data *data;
  3139. #ifdef __KERNEL__
  3140. data = (struct isp_rgbgamma_data *)
  3141. kmalloc(sizeof(struct isp_rgbgamma_data),
  3142. GFP_KERNEL);
  3143. #else
  3144. data = (struct isp_rgbgamma_data *)
  3145. malloc(sizeof(struct isp_rgbgamma_data));
  3146. #endif
  3147. if (data == NULL) {
  3148. isp_err("%s, malloc mem for rgb gamma failed.", __func__);
  3149. ret = -1;
  3150. } else {
  3151. viv_check_retval(copy_from_user
  3152. (data, args,
  3153. sizeof(struct
  3154. isp_rgbgamma_data)));
  3155. ret = isp_s_rgbgamma(dev, data);
  3156. #ifdef __KERNEL__
  3157. kfree(data);
  3158. #else
  3159. free(data);
  3160. #endif
  3161. }
  3162. break;
  3163. }
  3164. case ISPIOC_S_GREENEQUILIBRATE:
  3165. viv_check_retval(copy_from_user
  3166. (&dev->ge, args, sizeof(dev->ge)));
  3167. ret = isp_s_ge(dev);
  3168. break;
  3169. case ISPIOC_S_COLOR_ADJUST:
  3170. viv_check_retval(copy_from_user
  3171. (&dev->ca, args, sizeof(dev->ca)));
  3172. ret = isp_s_ca(dev);
  3173. break;
  3174. #ifdef __KERNEL__
  3175. case VIDIOC_QUERYCAP:
  3176. ret = isp_ioc_qcap(dev, args);
  3177. break;
  3178. #endif
  3179. case ISPIOC_G_QUERY_EXTMEM:
  3180. ret = isp_get_extmem(dev, args);
  3181. break;
  3182. case ISPIOC_ENABLE_RGBIR:
  3183. viv_check_retval(copy_from_user
  3184. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3185. ret = isp_enable_rgbir(dev);
  3186. break;
  3187. case ISPIOC_S_RGBIR:
  3188. viv_check_retval(copy_from_user
  3189. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3190. ret = isp_s_rgbir(dev);
  3191. break;
  3192. case ISPIOC_RGBIR_HW_INIT:
  3193. viv_check_retval(copy_from_user
  3194. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3195. ret = isp_rgbir_hw_init(dev);
  3196. break;
  3197. case ISPIOC_RGBIR_S_IR_DNR:
  3198. viv_check_retval(copy_from_user
  3199. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3200. ret = isp_rgbir_s_ir_dnr(dev);
  3201. break;
  3202. case ISPIOC_RGBIR_S_SHARPEN:
  3203. viv_check_retval(copy_from_user
  3204. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3205. ret = isp_rgbir_s_sharpen(dev);
  3206. break;
  3207. case ISPIOC_RGBIR_S_DES:
  3208. viv_check_retval(copy_from_user
  3209. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3210. ret = isp_rgbir_s_des(dev);
  3211. break;
  3212. case ISPIOC_RGBIR_S_CC_MATRIX:
  3213. viv_check_retval(copy_from_user
  3214. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3215. ret = isp_rgbir_s_cc_matrix(dev);
  3216. break;
  3217. case ISPIOC_RGBIR_S_DPCC:
  3218. viv_check_retval(copy_from_user
  3219. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3220. ret = isp_rgbir_s_dpcc(dev);
  3221. break;
  3222. case ISPIOC_RGBIR_S_GAIN:
  3223. viv_check_retval(copy_from_user
  3224. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3225. ret = isp_rgbir_s_gain(dev);
  3226. break;
  3227. case ISPIOC_RGBIR_S_BLS:
  3228. viv_check_retval(copy_from_user
  3229. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3230. ret = isp_rgbir_s_bls(dev);
  3231. break;
  3232. case ISPIOC_RGBIR_S_IR_RAW_OUT:
  3233. viv_check_retval(copy_from_user
  3234. (&dev->rgbir, args, sizeof(dev->rgbir)));
  3235. ret = isp_rgbir_out_ir_raw(dev);
  3236. break;
  3237. case ISPIOC_S_CROP:
  3238. viv_check_retval(copy_from_user
  3239. (&dev->crop, args, sizeof(struct isp_crop_context) * 3));
  3240. ret = isp_set_crop(dev);
  3241. break;
  3242. #ifdef ISP_3DNR_V3
  3243. case ISPIOC_S_TDNR:
  3244. viv_check_retval(copy_from_user
  3245. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3246. ret = isp_s_tdnr(dev);
  3247. break;
  3248. case ISPIOC_TDNR_ENABLE:
  3249. ret = isp_tdnr_enable(dev);
  3250. break;
  3251. case ISPIOC_TDNR_DISABLE:
  3252. ret = isp_tdnr_disable(dev);
  3253. break;
  3254. case ISPIOC_TDNR_ENABLE_TDNR:
  3255. ret = isp_tdnr_enable_tdnr(dev);
  3256. break;
  3257. case ISPIOC_TDNR_DISABLE_TDNR:
  3258. ret = isp_tdnr_disable_tdnr(dev);
  3259. break;
  3260. case ISPIOC_TDNR_ENABLE_2DNR:
  3261. ret = isp_tdnr_enable_2dnr(dev);
  3262. break;
  3263. case ISPIOC_TDNR_DISABLE_2DNR:
  3264. ret = isp_tdnr_disable_2dnr(dev);
  3265. break;
  3266. case ISPIOC_S_TDNR_CURVE:
  3267. viv_check_retval(copy_from_user
  3268. (&dev->tdnr.curve, args, sizeof(dev->tdnr.curve)));
  3269. ret = isp_tdnr_cfg_gamma(dev);
  3270. break;
  3271. case ISPIOC_G_TDNR: {
  3272. struct isp_tdnr_stats stats;
  3273. ret = isp_tdnr_g_stats(dev, &stats);
  3274. viv_check_retval(copy_to_user(args, &stats, sizeof(stats)));
  3275. }
  3276. break;
  3277. case ISPIOC_S_TDNR_STRENGTH:
  3278. viv_check_retval(copy_from_user
  3279. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3280. ret = isp_tdnr_set_strength(dev);
  3281. break;
  3282. case ISPIOC_U_TDNR_NOISE:
  3283. viv_check_retval(copy_from_user
  3284. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3285. ret = isp_tdnr_u_noise(dev);
  3286. break;
  3287. case ISPIOC_U_TDNR_THR:
  3288. viv_check_retval(copy_from_user
  3289. (&dev->tdnr, args, sizeof(dev->tdnr)));
  3290. ret = isp_tdnr_u_thr(dev);
  3291. break;
  3292. case ISPIOC_R_TDNR_REFER:
  3293. ret = isp_r_tdnr_refer(dev);
  3294. break;
  3295. case ISPIOC_R_TDNR_MOTION:
  3296. ret = isp_r_tdnr_motion(dev);
  3297. break;
  3298. case ISPIOC_S_TDNR_BUF:
  3299. viv_check_retval(copy_from_user
  3300. (&dev->tdnr.buf, args, sizeof(dev->tdnr.buf)));
  3301. ret = isp_tdnr_s_buf(dev);
  3302. break;
  3303. #endif
  3304. #ifdef ISP_MI_PP_WRITE
  3305. case ISPIOC_GET_PPW_LINE_CNT:
  3306. {
  3307. u16 ppw_pic_cnt;
  3308. ret = isp_get_ppw_pic_cnt(dev, &ppw_pic_cnt);
  3309. viv_check_retval(copy_to_user
  3310. (args, &ppw_pic_cnt, sizeof(ppw_pic_cnt)));
  3311. break;
  3312. }
  3313. case ISPIOC_SET_PPW_LINE_NUM:
  3314. {
  3315. viv_check_retval(copy_from_user
  3316. (&dev->pp_write, args, sizeof(dev->pp_write)));
  3317. ret = isp_set_ppw_line_num(dev);
  3318. break;
  3319. }
  3320. #endif
  3321. #ifdef ISP_MI_PP_READ
  3322. case ISPIOC_CFG_DMA_LINE_ENTRY:
  3323. viv_check_retval(copy_from_user
  3324. (&dev->pp_dma_line_entry, args, sizeof(dev->pp_dma_line_entry)));
  3325. ret = isp_cfg_pp_dma_line_entry(dev);
  3326. break;
  3327. #endif
  3328. case ISPIOC_GET_FRAME_MASK_INFO_ADDR: {
  3329. unsigned long addr;
  3330. addr = dev->frame_mark_info_addr;
  3331. pr_info("ISPIOC_GET_FRAME_MASK_INFO_ADDR %lx\n", addr);
  3332. viv_check_retval(copy_to_user(args, &addr, sizeof(addr)));
  3333. ret = 0;
  3334. }
  3335. break;
  3336. default:
  3337. isp_err("unsupported command %d", cmd);
  3338. break;
  3339. }
  3340. if (cmd != ISPIOC_WRITE_REG) //frame end isp update shd registers.
  3341. ISP_GEN_CFG_UPDATE(dev);
  3342. return ret;
  3343. }