isp_hdr.c 9.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259
  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. #ifdef __KERNEL__
  54. #include <linux/io.h>
  55. #include <linux/module.h>
  56. #endif
  57. #include "mrv_all_bits.h"
  58. #include "isp_ioctl.h"
  59. #include "isp_types.h"
  60. extern MrvAllRegister_t *all_regs;
  61. int isp_s_hdr(struct isp_ic_dev *dev)
  62. {
  63. struct isp_hdr_context *hdr = &dev->hdr;
  64. u32 isp_stitching_ctrl =
  65. isp_read_reg(dev, REG_ADDR(isp_stitching_ctrl));
  66. u32 val;
  67. int i;
  68. pr_info("enter %s\n", __func__);
  69. val = 0;
  70. #if 0
  71. REG_SET_SLICE(val, STITCHING_FRAME_WIDTH, hdr->width);
  72. isp_write_reg(dev, REG_ADDR(isp_stitching_frame_width), val);
  73. val = 0;
  74. REG_SET_SLICE(val, STITCHING_FRAME_HEIGHT, hdr->height);
  75. isp_write_reg(dev, REG_ADDR(isp_stitching_frame_height), val);
  76. val = 0;
  77. REG_SET_SLICE(val, STITCHING_L_BIT_DEPTH, hdr->l_bit_dep);
  78. REG_SET_SLICE(val, STITCHING_S_BIT_DEPTH, hdr->s_bit_dep);
  79. REG_SET_SLICE(val, STITCHING_VS_BIT_DEPTH, hdr->vs_bit_dep);
  80. REG_SET_SLICE(val, STITCHING_LS_BIT_DEPTH, hdr->ls_bit_dep);
  81. isp_write_reg(dev, REG_ADDR(isp_stitching_exposure_bit), val);
  82. val = 0;
  83. REG_SET_SLICE(val, STITCHING_COLOR_WEIGHT_0, hdr->weight0);
  84. REG_SET_SLICE(val, STITCHING_COLOR_WEIGHT_1, hdr->weight1);
  85. REG_SET_SLICE(val, STITCHING_COLOR_WEIGHT_2, hdr->weight2);
  86. isp_write_reg(dev, REG_ADDR(isp_stitching_color_weight), val);
  87. val = 0;
  88. REG_SET_SLICE(val, STITCHING_TRANS_RANGE_START_LINEAR,
  89. hdr->start_linear);
  90. REG_SET_SLICE(val, STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_LINEAR,
  91. hdr->norm_factor_mul_linear);
  92. isp_write_reg(dev, REG_ADDR(isp_stitching_trans_range_linear), val);
  93. val = 0;
  94. REG_SET_SLICE(val, STITCHING_TRANS_RANGE_START_NONLINEAR,
  95. hdr->start_nonlinear);
  96. REG_SET_SLICE(val, STITCHING_TRANS_RANGE_NORM_FACTOR_MUL_NONLINEAR,
  97. hdr->norm_factor_mul_nonlinear);
  98. isp_write_reg(dev, REG_ADDR(isp_stitching_trans_range_nonlinear), val);
  99. val = 0;
  100. REG_SET_SLICE(val, STITCHING_DUMMY_HBLANK, hdr->dummy_hblank);
  101. REG_SET_SLICE(val, STITCHING_OUT_HBLANK, hdr->out_hblank);
  102. isp_write_reg(dev, REG_ADDR(isp_stitching_out_hblank), val);
  103. val = 0;
  104. REG_SET_SLICE(val, STITCHING_OUT_VBLANK, hdr->out_vblank);
  105. isp_write_reg(dev, REG_ADDR(isp_stitching_out_vblank), val);
  106. val = 0;
  107. REG_SET_SLICE(val, STITCHING_LONG_EXPOSURE_TIME, hdr->long_exp);
  108. isp_write_reg(dev, REG_ADDR(isp_stitching_long_exposure), val);
  109. val = 0;
  110. REG_SET_SLICE(val, STITCHING_SHORT_EXPOSURE_TIME, hdr->short_exp);
  111. isp_write_reg(dev, REG_ADDR(isp_stitching_short_exposure), val);
  112. val = 0;
  113. REG_SET_SLICE(val, STITCHING_VERY_SHORT_EXPOSURE_TIME,
  114. hdr->very_short_exp);
  115. isp_write_reg(dev, REG_ADDR(isp_stitching_very_short_exposure), val);
  116. val = 0;
  117. REG_SET_SLICE(val, STITCHING_LONG_EXPOSURE_TIME, hdr->long_exp);
  118. isp_write_reg(dev, REG_ADDR(isp_stitching_long_exposure), val);
  119. #endif
  120. val = 0;
  121. REG_SET_SLICE(val, STITCHING_RATIO_LONG_SHORT_1, hdr->ls1);
  122. REG_SET_SLICE(val, STITCHING_RATIO_LONG_SHORT_0, hdr->ls0);
  123. isp_write_reg(dev, REG_ADDR(isp_stitching_ratio_ls), val);
  124. val = 0;
  125. REG_SET_SLICE(val, STITCHING_RATIO_VERYSHORT_SHORT_1, hdr->vs1);
  126. REG_SET_SLICE(val, STITCHING_RATIO_VERYSHORT_SHORT_0, hdr->vs0);
  127. isp_write_reg(dev, REG_ADDR(isp_stitching_ratio_vs), val);
  128. val = 0;
  129. REG_SET_SLICE(val, STITCHING_SHORT_EXTEND_BIT, hdr->ext_bit);
  130. REG_SET_SLICE(val, STITCHING_VERYSHORT_VALID_THRESH, hdr->valid_thresh);
  131. REG_SET_SLICE(val, STITCHING_VERYSHORT_OFFSET_VAL, hdr->offset_val);
  132. isp_write_reg(dev, REG_ADDR(isp_stitching_sat_level), val);
  133. for (i = 0; i < 5; i++) {
  134. val = 0;
  135. REG_SET_SLICE(val, STITCHING_COMPRESS_LUT_2,
  136. hdr->compress_lut[i * 3 + 2]);
  137. REG_SET_SLICE(val, STITCHING_COMPRESS_LUT_1,
  138. hdr->compress_lut[i * 3 + 1]);
  139. REG_SET_SLICE(val, STITCHING_COMPRESS_LUT_0,
  140. hdr->compress_lut[i * 3]);
  141. isp_write_reg(dev,
  142. REG_ADDR(isp_stitching_compress_lut_0) + i * 4,
  143. val);
  144. }
  145. val = 0;
  146. REG_SET_SLICE(val, STITCHING_LONG_SAT_THRESH, hdr->sat_thresh);
  147. REG_SET_SLICE(val, STITCHING_LONG_SAT_COMBINE_WEIGHT,
  148. hdr->combine_weight);
  149. isp_write_reg(dev, REG_ADDR(isp_stitching_long_sat_params), val);
  150. REG_SET_SLICE(isp_stitching_ctrl, STITCHING_COMBINE_ENABLE_BIT, 1);
  151. REG_SET_SLICE(isp_stitching_ctrl, STITCHING_CFG_UPD, 1);
  152. REG_SET_SLICE(isp_stitching_ctrl, STITCHING_COMBINATION_MODE, 1);
  153. isp_write_reg(dev, REG_ADDR(isp_stitching_ctrl), 0x4c0221);
  154. return 0;
  155. }
  156. int isp_s_hdr_wb(struct isp_ic_dev *dev)
  157. {
  158. struct isp_hdr_context *hdr = &dev->hdr;
  159. u32 val = 0;
  160. u32 isp_stitching_ctrl =
  161. isp_read_reg(dev, REG_ADDR(isp_stitching_ctrl));
  162. pr_info("enter %s\n", __func__);
  163. REG_SET_SLICE(val, STITCHING_EXP0_AWB_GAIN_GR, hdr->gr);
  164. REG_SET_SLICE(val, STITCHING_EXP0_AWB_GAIN_GB, hdr->gb);
  165. isp_write_reg(dev, REG_ADDR(isp_stitching_exp0_awb_gain_g), val);
  166. isp_write_reg(dev, REG_ADDR(isp_stitching_exp1_awb_gain_g), val);
  167. isp_write_reg(dev, REG_ADDR(isp_stitching_exp2_awb_gain_g), val);
  168. val = 0;
  169. REG_SET_SLICE(val, STITCHING_EXP0_AWB_GAIN_R, hdr->r);
  170. REG_SET_SLICE(val, STITCHING_EXP0_AWB_GAIN_B, hdr->b);
  171. isp_write_reg(dev, REG_ADDR(isp_stitching_exp0_awb_gain_rb), val);
  172. isp_write_reg(dev, REG_ADDR(isp_stitching_exp1_awb_gain_rb), val);
  173. isp_write_reg(dev, REG_ADDR(isp_stitching_exp2_awb_gain_rb), val);
  174. REG_SET_SLICE(isp_stitching_ctrl, STITCHING_CFG_UPD, 1);
  175. isp_write_reg(dev, REG_ADDR(isp_stitching_ctrl), 0x4c0221);
  176. return 0;
  177. }
  178. int isp_s_hdr_bls(struct isp_ic_dev *dev)
  179. {
  180. struct isp_hdr_context *hdr = &dev->hdr;
  181. u32 isp_stitching_ctrl =
  182. isp_read_reg(dev, REG_ADDR(isp_stitching_ctrl));
  183. u32 val = 0;
  184. int i;
  185. pr_info("enter %s\n", __func__);
  186. for (i = 0; i < 12; i++) {
  187. val = 0;
  188. REG_SET_SLICE(val, STITCHING_BLS_EXP_0_A, hdr->bls[i % 4]);
  189. isp_write_reg(dev, REG_ADDR(isp_stitching_bls_exp_0_a) + i * 4,
  190. val);
  191. }
  192. REG_SET_SLICE(isp_stitching_ctrl, STITCHING_CFG_UPD, 1);
  193. isp_write_reg(dev, REG_ADDR(isp_stitching_ctrl), 0x4c0221);
  194. return 0;
  195. }
  196. int isp_enable_hdr(struct isp_ic_dev *dev)
  197. {
  198. u32 addr, isp_stitching_ctrl;
  199. u32 dpcl;
  200. int val = 0;
  201. pr_info("enter %s\n", __func__);
  202. addr = REG_ADDR(isp_stitching_ctrl);
  203. isp_stitching_ctrl = isp_read_reg(dev, addr);
  204. REG_SET_SLICE(val, STITCHING_FRAME_WIDTH, dev->ctx.acqWindow.width);
  205. isp_write_reg(dev, REG_ADDR(isp_stitching_frame_width), val);
  206. val = 0;
  207. REG_SET_SLICE(val, STITCHING_FRAME_HEIGHT, dev->ctx.acqWindow.height);
  208. isp_write_reg(dev, REG_ADDR(isp_stitching_frame_height), val);
  209. REG_SET_SLICE(isp_stitching_ctrl, STITCHING_COMBINE_ENABLE_BIT, 0);
  210. isp_write_reg(dev, addr, isp_stitching_ctrl);
  211. dpcl = isp_read_reg(dev, REG_ADDR(vi_dpcl));
  212. REG_SET_SLICE(dpcl, MRV_IF_SELECT, MRV_IF_SELECT_HDR);
  213. isp_write_reg(dev, REG_ADDR(vi_dpcl), dpcl);
  214. dev->mux.if_select = MRV_IF_SELECT_HDR;
  215. return 0;
  216. }
  217. int isp_disable_hdr(struct isp_ic_dev *dev)
  218. {
  219. u32 addr, isp_stitching_ctrl = 0;
  220. pr_info("enter %s\n", __func__);
  221. addr = REG_ADDR(isp_stitching_ctrl);
  222. isp_stitching_ctrl = isp_read_reg(dev, addr);
  223. REG_SET_SLICE(isp_stitching_ctrl, STITCHING_COMBINE_ENABLE_BIT, 1);
  224. isp_write_reg(dev, addr, isp_stitching_ctrl);
  225. return 0;
  226. }