isp_dpf.c 7.4 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. #ifdef __KERNEL__
  54. #include <linux/io.h>
  55. #include <linux/module.h>
  56. #else
  57. #endif
  58. #include "mrv_all_bits.h"
  59. #include "isp_ioctl.h"
  60. #include "isp_types.h"
  61. extern MrvAllRegister_t *all_regs;
  62. int isp_s_dpf(struct isp_ic_dev *dev)
  63. {
  64. struct isp_dpf_context *dpf = &dev->dpf;
  65. u32 value;
  66. int i = 0;
  67. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  68. u32 isp_dpf_mode = isp_read_reg(dev, REG_ADDR(isp_dpf_mode));
  69. //pr_info("enter %s\n", __func__);
  70. if (!dpf->enable) {
  71. isp_write_reg(dev, REG_ADDR(isp_dpf_mode),
  72. isp_dpf_mode & ~MRV_DPF_DPF_ENABLE_MASK);
  73. return 0;
  74. }
  75. isp_dpf_mode &=
  76. (MRV_DPF_DPF_ENABLE_MASK | MRV_DPF_NLL_SEGMENTATION_MASK);
  77. switch (dpf->gain_usage) {
  78. case IC_DPF_GAIN_USAGE_DISABLED:
  79. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 0);
  80. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 0);
  81. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 0);
  82. break;
  83. case IC_DPF_GAIN_USAGE_NF_GAINS:
  84. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 1);
  85. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 0);
  86. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 1);
  87. break;
  88. case IC_DPF_GAIN_USAGE_LSC_GAINS:
  89. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 0);
  90. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 1);
  91. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 0);
  92. break;
  93. case IC_DPF_GAIN_USAGE_NF_LSC_GAINS:
  94. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 1);
  95. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 1);
  96. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 1);
  97. break;
  98. case IC_DPF_GAIN_USAGE_AWB_GAINS:
  99. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 0);
  100. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 0);
  101. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 1);
  102. break;
  103. case IC_DPF_GAIN_USAGE_AWB_LSC_GAINS:
  104. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_USE_NF_GAIN, 0);
  105. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_LSC_GAIN_COMP, 1);
  106. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_AWB_GAIN_COMP, 1);
  107. break;
  108. default:
  109. /*pr_err("%s: unsupported gain usage\n", __func__);*/
  110. break;
  111. }
  112. switch (dpf->filter_type) {
  113. case IC_DPF_RB_FILTERSIZE_13x9:
  114. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_RB_FILTER_SIZE, 0U);
  115. break;
  116. case IC_DPF_RB_FILTERSIZE_9x9:
  117. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_RB_FILTER_SIZE, 1U);
  118. break;
  119. default:
  120. /*pr_err
  121. ("%s: unsupported filter kernel size for red/blue pixel\n",
  122. __func__);*/
  123. break;
  124. }
  125. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_R_FILTER_OFF, dpf->filter_r_off);
  126. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_GR_FILTER_OFF, dpf->filter_gr_off);
  127. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_GB_FILTER_OFF, dpf->filter_gb_off);
  128. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_B_FILTER_OFF, dpf->filter_b_off);
  129. value = 0;
  130. REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G1, dpf->weight_g[0]);
  131. REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G2, dpf->weight_g[1]);
  132. REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G3, dpf->weight_g[2]);
  133. REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G4, dpf->weight_g[3]);
  134. isp_write_reg(dev, REG_ADDR(isp_dpf_s_weight_g_1_4), value);
  135. value = 0;
  136. REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G5, dpf->weight_g[4]);
  137. REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_G6, dpf->weight_g[5]);
  138. isp_write_reg(dev, REG_ADDR(isp_dpf_s_weight_g_5_6), value);
  139. value = 0;
  140. REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB1, dpf->weight_rb[0]);
  141. REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB2, dpf->weight_rb[1]);
  142. REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB3, dpf->weight_rb[2]);
  143. REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB4, dpf->weight_rb[3]);
  144. isp_write_reg(dev, REG_ADDR(isp_dpf_s_weight_rb_1_4), value);
  145. value = 0;
  146. REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB5, dpf->weight_rb[4]);
  147. REG_SET_SLICE(value, MRV_DPF_S_WEIGHT_RB6, dpf->weight_rb[5]);
  148. isp_write_reg(dev, REG_ADDR(isp_dpf_s_weight_rb_5_6), value);
  149. isp_write_reg(dev, REG_ADDR(isp_dpf_nf_gain_r), dpf->nf_gain_r);
  150. isp_write_reg(dev, REG_ADDR(isp_dpf_nf_gain_gr), dpf->nf_gain_gr);
  151. isp_write_reg(dev, REG_ADDR(isp_dpf_nf_gain_gb), dpf->nf_gain_gb);
  152. isp_write_reg(dev, REG_ADDR(isp_dpf_nf_gain_b), dpf->nf_gain_b);
  153. isp_write_reg(dev, REG_ADDR(isp_dpf_strength_r),
  154. (MRV_DPF_INV_WEIGHT_R_MASK & dpf->strength_r));
  155. isp_write_reg(dev, REG_ADDR(isp_dpf_strength_g),
  156. (MRV_DPF_INV_WEIGHT_G_MASK & dpf->strength_g));
  157. isp_write_reg(dev, REG_ADDR(isp_dpf_strength_b),
  158. (MRV_DPF_INV_WEIGHT_B_MASK & dpf->strength_b));
  159. for (i = 0; i < 17; i++) {
  160. if (dpf->denoise_talbe[i] <= MRV_DPF_NLL_COEFF_N_MASK) {
  161. isp_write_reg(dev,
  162. REG_ADDR(nlf_lookup_table_block_arr[i]),
  163. dpf->denoise_talbe[i]);
  164. }
  165. }
  166. switch (dpf->x_scale) {
  167. case IC_NLL_SCALE_LINEAR:
  168. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_NLL_SEGMENTATION, 0);
  169. break;
  170. case IC_NLL_SCALE_LOGARITHMIC:
  171. REG_SET_SLICE(isp_dpf_mode, MRV_DPF_NLL_SEGMENTATION, 1);
  172. break;
  173. default:
  174. break;
  175. }
  176. isp_write_reg(dev, REG_ADDR(isp_dpf_mode), isp_dpf_mode);
  177. isp_write_reg(dev, REG_ADDR(isp_dpf_mode),
  178. isp_dpf_mode | MRV_DPF_DPF_ENABLE_MASK);
  179. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  180. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  181. return 0;
  182. }