isp_dmsc2.c 16 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. #ifdef __KERNEL__
  54. #include <linux/io.h>
  55. #include <linux/module.h>
  56. #endif
  57. #include "mrv_all_bits.h"
  58. #include "isp_ioctl.h"
  59. #include "isp_types.h"
  60. extern MrvAllRegister_t *all_regs;
  61. #ifdef ISP_DEMOSAIC2
  62. int isp_enable_dmsc(struct isp_ic_dev *dev)
  63. {
  64. u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  65. u32 isp_dmsc_size_ctrl =
  66. isp_read_reg(dev, REG_ADDR(isp_dmsc_size_ctrl));
  67. pr_info("enter %s\n", __func__);
  68. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_BYPASS, 0U);
  69. REG_SET_SLICE(isp_dmsc_size_ctrl, ISP_DMSC_IMAGE_H_SIZE,
  70. isp_read_reg(dev, REG_ADDR(isp_acq_h_size)));
  71. REG_SET_SLICE(isp_dmsc_size_ctrl, ISP_DMSC_IMAGE_H_BLANK, 0x039c);
  72. isp_write_reg(dev, REG_ADDR(isp_dmsc_size_ctrl), isp_dmsc_size_ctrl);
  73. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  74. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl_shd), isp_dmsc_ctrl);
  75. return 0;
  76. }
  77. int isp_disable_dmsc(struct isp_ic_dev *dev)
  78. {
  79. u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  80. isp_dmsc_ctrl = 0; //clear fpga default bit 3 and 13 to keep the same value with cmodel.
  81. pr_info("enter %s\n", __func__);
  82. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_BYPASS, 1U);
  83. /*clear the reg default val to keep weith cmodel */
  84. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_fact), 0);
  85. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_clip), 0);
  86. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_filt2), 0);
  87. isp_write_reg(dev, REG_ADDR(isp_dmsc_dpul_ctrl), 0);
  88. isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cb), 0);
  89. //isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_a), 0);
  90. //isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_c), 0);
  91. isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_ctrl), 0);
  92. isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_thr), 0);
  93. isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cr), 0);
  94. isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_y), 0);
  95. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  96. return 0;
  97. }
  98. int isp_set_dmsc_intp(struct isp_ic_dev *dev)
  99. {
  100. u32 isp_dmsc_intp_thr = isp_read_reg(dev, REG_ADDR(isp_dmsc_intp_thr));
  101. pr_info("enter %s\n", __func__);
  102. REG_SET_SLICE(isp_dmsc_intp_thr, ISP_DMSC_INTERPLATION_DIR_THR_MAX,
  103. dev->demosaic.intp.intp_dir_thr_max);
  104. REG_SET_SLICE(isp_dmsc_intp_thr, ISP_DMSC_INTERPLATION_DIR_THR_MIN,
  105. dev->demosaic.intp.intp_dir_thr_min);
  106. isp_write_reg(dev, REG_ADDR(isp_dmsc_intp_thr), isp_dmsc_intp_thr);
  107. return 0;
  108. }
  109. int isp_set_dmsc_dmoi(struct isp_ic_dev *dev)
  110. {
  111. struct isp_dmoi_context *pDemoire = &dev->demosaic.demoire;
  112. u32 isp_dmsc_dmoi_ctrl =
  113. isp_read_reg(dev, REG_ADDR(isp_dmsc_dmoi_ctrl));
  114. u32 isp_dmsc_dmoi_thr = isp_read_reg(dev, REG_ADDR(isp_dmsc_dmoi_thr));
  115. u32 isp_dmsc_dmoi_patn_thr =
  116. isp_read_reg(dev, REG_ADDR(isp_dmsc_dmoi_patn_thr));
  117. u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  118. pr_info("enter %s\n", __func__);
  119. if (!pDemoire->enable) {
  120. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEMOIRE_ENABLE, 0U);
  121. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  122. return 0;
  123. }
  124. REG_SET_SLICE(isp_dmsc_dmoi_ctrl, ISP_DMSC_DEMOIRE_AREA_THR,
  125. pDemoire->demoire_area_thr);
  126. REG_SET_SLICE(isp_dmsc_dmoi_ctrl, ISP_DMSC_DEMOIRE_SAT_SHRINK,
  127. pDemoire->demoire_sat_shrink);
  128. REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_R2,
  129. pDemoire->demoire_r2);
  130. REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_R1,
  131. pDemoire->demoire_r1);
  132. REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_T2_SHIFT,
  133. pDemoire->demoire_t2_shift);
  134. REG_SET_SLICE(isp_dmsc_dmoi_thr, ISP_DMSC_DEMOIRE_T1,
  135. pDemoire->demoire_t1);
  136. REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_R2,
  137. pDemoire->demoire_edge_r2);
  138. REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_R1,
  139. pDemoire->demoire_edge_r1);
  140. REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_T2_SHIFT,
  141. pDemoire->demoire_edge_t2_shift);
  142. REG_SET_SLICE(isp_dmsc_dmoi_patn_thr, ISP_DMSC_DEMOIRE_EDGE_T1,
  143. pDemoire->demoire_edge_t1);
  144. isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_ctrl), isp_dmsc_dmoi_ctrl);
  145. isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_thr), isp_dmsc_dmoi_thr);
  146. isp_write_reg(dev, REG_ADDR(isp_dmsc_dmoi_patn_thr),
  147. isp_dmsc_dmoi_patn_thr);
  148. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEMOIRE_ENABLE, 1U);
  149. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  150. return 0;
  151. }
  152. int isp_set_dmsc_sharpen(struct isp_ic_dev *dev)
  153. {
  154. struct isp_shap_context *pSharpen = &dev->demosaic.sharpen;
  155. u32 isp_dmsc_shap_fact =
  156. isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_fact));
  157. u32 isp_dmsc_shap_clip =
  158. isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_clip));
  159. u32 isp_dmsc_shap_thr = isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_thr));
  160. u32 isp_dmsc_shap_ratio =
  161. isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_ratio));
  162. u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  163. pr_info("enter %s\n", __func__);
  164. if (!pSharpen->enable) {
  165. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_ENBALE, 0);
  166. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  167. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl_shd), isp_dmsc_ctrl);
  168. return 0;
  169. }
  170. REG_SET_SLICE(isp_dmsc_shap_fact, ISP_DMSC_SHARPEN_FACTOR_BLACK,
  171. pSharpen->sharpen_factor_black);
  172. REG_SET_SLICE(isp_dmsc_shap_fact, ISP_DMSC_SHARPEN_FACTOR_WHITE,
  173. pSharpen->sharpen_factor_white);
  174. REG_SET_SLICE(isp_dmsc_shap_clip, ISP_DMSC_SHARPEN_CLIP_BLACK,
  175. pSharpen->sharpen_clip_black);
  176. REG_SET_SLICE(isp_dmsc_shap_clip, ISP_DMSC_SHARPEN_CLIP_WHITE,
  177. pSharpen->sharpen_clip_white);
  178. REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T4_SHIFT,
  179. pSharpen->sharpen_t4_shift);
  180. REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T3,
  181. pSharpen->sharpen_t3);
  182. REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T2_SHIFT,
  183. pSharpen->sharpen_t2_shift);
  184. REG_SET_SLICE(isp_dmsc_shap_thr, ISP_DMSC_SHARPEN_T1,
  185. pSharpen->sharpen_t1);
  186. REG_SET_SLICE(isp_dmsc_shap_ratio, ISP_DMSC_SHARPEN_R3,
  187. pSharpen->sharpen_r3);
  188. REG_SET_SLICE(isp_dmsc_shap_ratio, ISP_DMSC_SHARPEN_R2,
  189. pSharpen->sharpen_r2);
  190. REG_SET_SLICE(isp_dmsc_shap_ratio, ISP_DMSC_SHARPEN_R1,
  191. pSharpen->sharpen_r1);
  192. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_fact), isp_dmsc_shap_fact);
  193. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_clip), isp_dmsc_shap_clip);
  194. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_thr), isp_dmsc_shap_thr);
  195. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_ratio), isp_dmsc_shap_ratio);
  196. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_ENBALE, 1);
  197. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  198. return 0;
  199. }
  200. int isp_set_dmsc_gfilter(struct isp_ic_dev *dev)
  201. {
  202. struct isp_gfilter_context *pgfilter = &dev->demosaic.gFilter;
  203. u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  204. u32 isp_dmsc_shap_filt1 =
  205. isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_filt1));
  206. u32 isp_dmsc_shap_filt2 =
  207. isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_filt2));
  208. pr_info("enter %s\n", __func__);
  209. REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_00,
  210. pgfilter->hf_filt_00);
  211. REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_01,
  212. pgfilter->hf_filt_01);
  213. REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_02,
  214. pgfilter->hf_filt_02);
  215. REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_10,
  216. pgfilter->hf_filt_10);
  217. REG_SET_SLICE(isp_dmsc_shap_filt1, ISP_DMSC_HF_FILT_11,
  218. pgfilter->hf_filt_11);
  219. REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_12,
  220. pgfilter->hf_filt_12);
  221. REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_20,
  222. pgfilter->hf_filt_20);
  223. REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_21,
  224. pgfilter->hf_filt_21);
  225. REG_SET_SLICE(isp_dmsc_shap_filt2, ISP_DMSC_HF_FILT_22,
  226. pgfilter->hf_filt_22);
  227. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_filt1), isp_dmsc_shap_filt1);
  228. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_filt2), isp_dmsc_shap_filt2);
  229. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_SIZE, pgfilter->sharpen_size);
  230. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  231. return 0;
  232. }
  233. int isp_set_dmsc_sharpen_line(struct isp_ic_dev *dev)
  234. {
  235. struct isp_shap_line_context *sharpenLine = &dev->demosaic.sharpenLine;
  236. u32 isp_dmsc_shap_line_ctrl =
  237. isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_line_ctrl));
  238. u32 isp_dmsc_shap_line_ratio =
  239. isp_read_reg(dev, REG_ADDR(isp_dmsc_shap_line_ratio));
  240. u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  241. pr_info("enter %s\n", __func__);
  242. if (!sharpenLine->enable) {
  243. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_LINE_ENABLE, 0);
  244. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  245. return 0;
  246. }
  247. REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_SHIFT2,
  248. sharpenLine->sharpen_line_shift2);
  249. REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_SHIFT1,
  250. sharpenLine->sharpen_line_shift1);
  251. REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_T1,
  252. sharpenLine->sharpen_line_t1);
  253. REG_SET_SLICE(isp_dmsc_shap_line_ctrl, ISP_DMSC_SHARPEN_LINE_STRENGTH,
  254. sharpenLine->sharpen_line_strength);
  255. REG_SET_SLICE(isp_dmsc_shap_line_ratio, ISP_DMSC_SHARPEN_LINE_R2,
  256. sharpenLine->sharpen_line_r2);
  257. REG_SET_SLICE(isp_dmsc_shap_line_ratio, ISP_DMSC_SHARPEN_LINE_R1,
  258. sharpenLine->sharpen_line_r1);
  259. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_line_ctrl),
  260. isp_dmsc_shap_line_ctrl);
  261. isp_write_reg(dev, REG_ADDR(isp_dmsc_shap_line_ratio),
  262. isp_dmsc_shap_line_ratio);
  263. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SHARPEN_LINE_ENABLE, 1);
  264. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  265. return 0;
  266. }
  267. int isp_set_dmsc_cac(struct isp_ic_dev *dev)
  268. {
  269. struct isp_cac_context *cac = &dev->cac;
  270. u32 val = 0;
  271. u32 isp_dmsc_cac_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_cac_ctrl));
  272. pr_info("enter %s\n", __func__);
  273. if (!cac->enable) {
  274. REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_CAC_EN, 0);
  275. isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_ctrl),
  276. isp_dmsc_cac_ctrl);
  277. return 0;
  278. }
  279. REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_H_CLIP_MODE, cac->hmode);
  280. REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_V_CLIP_MODE, cac->vmode);
  281. isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_count_start),
  282. cac->hstart | (cac->vstart << 16));
  283. isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_a), cac->ar | (cac->ab << 16));
  284. isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_b), cac->br | (cac->bb << 16));
  285. isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_c), cac->cr | (cac->cb << 16));
  286. REG_SET_SLICE(val, MRV_CAC_X_NS, cac->xns);
  287. REG_SET_SLICE(val, MRV_CAC_X_NF, cac->xnf);
  288. isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_x_norm), val);
  289. val = 0;
  290. REG_SET_SLICE(val, MRV_CAC_Y_NS, cac->yns);
  291. REG_SET_SLICE(val, MRV_CAC_Y_NF, cac->ynf);
  292. isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_y_norm), val);
  293. REG_SET_SLICE(isp_dmsc_cac_ctrl, MRV_CAC_CAC_EN, 1);
  294. isp_write_reg(dev, REG_ADDR(isp_dmsc_cac_ctrl), isp_dmsc_cac_ctrl);
  295. return 0;
  296. }
  297. int isp_set_dmsc_depurple(struct isp_ic_dev *dev)
  298. {
  299. struct isp_depurple_context *depurple = &dev->demosaic.depurple;
  300. u32 isp_dmsc_dpul_ctrl =
  301. isp_read_reg(dev, REG_ADDR(isp_dmsc_dpul_ctrl));
  302. u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  303. pr_info("enter %s\n", __func__);
  304. if (!depurple->enable) {
  305. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEPURPLE_ENABLE, 0U);
  306. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  307. return 0;
  308. }
  309. REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_RED_SAT, depurple->red_sat);
  310. REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_BLUE_SAT, depurple->blue_sat);
  311. REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_SAT_SHRINK,
  312. depurple->depurple_sat_shrink);
  313. REG_SET_SLICE(isp_dmsc_dpul_ctrl, ISP_DMSC_DEPURPLE_THR,
  314. depurple->depurple_thr);
  315. isp_write_reg(dev, REG_ADDR(isp_dmsc_dpul_ctrl), isp_dmsc_dpul_ctrl);
  316. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DEPURPLE_ENABLE, 1U);
  317. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  318. return 0;
  319. }
  320. int isp_set_dmsc_skin(struct isp_ic_dev *dev)
  321. {
  322. struct isp_skin_context *skin = &dev->demosaic.skin;
  323. u32 isp_dmsc_skin_thr_cb =
  324. isp_read_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cb));
  325. u32 isp_dmsc_skin_thr_cr =
  326. isp_read_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cr));
  327. u32 isp_dmsc_skin_thr_y =
  328. isp_read_reg(dev, REG_ADDR(isp_dmsc_skin_thr_y));
  329. u32 isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  330. pr_info("enter %s\n", __func__);
  331. if (!skin->enable) {
  332. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SKIN_ENABLE, 0U);
  333. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  334. return 0;
  335. }
  336. REG_SET_SLICE(isp_dmsc_skin_thr_cb, ISP_DMSC_SKIN_CB_THR_MAX_2047,
  337. skin->cb_thr_max_2047);
  338. REG_SET_SLICE(isp_dmsc_skin_thr_cb, ISP_DMSC_SKIN_CB_THR_MIN_2047,
  339. skin->cb_thr_min_2047);
  340. REG_SET_SLICE(isp_dmsc_skin_thr_cr, ISP_DMSC_SKIN_CR_THR_MAX_2047,
  341. skin->cr_thr_max_2047);
  342. REG_SET_SLICE(isp_dmsc_skin_thr_cr, ISP_DMSC_SKIN_CR_THR_MIN_2047,
  343. skin->cr_thr_min_2047);
  344. REG_SET_SLICE(isp_dmsc_skin_thr_y, ISP_DMSC_SKIN_Y_THR_MAX,
  345. skin->y_thr_max_2047);
  346. REG_SET_SLICE(isp_dmsc_skin_thr_y, ISP_DMSC_SKIN_Y_THR_MIN,
  347. skin->y_thr_min_2047);
  348. isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cb),
  349. isp_dmsc_skin_thr_cb);
  350. isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_cr),
  351. isp_dmsc_skin_thr_cr);
  352. isp_write_reg(dev, REG_ADDR(isp_dmsc_skin_thr_y), isp_dmsc_skin_thr_y);
  353. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_SKIN_ENABLE, 1U);
  354. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  355. return 0;
  356. }
  357. int isp_s_dmsc(struct isp_ic_dev *dev)
  358. {
  359. u32 isp_dmsc_ctrl;
  360. /*Clear the cmodel register default value to match the fpga default value */
  361. isp_disable_dmsc(dev);
  362. isp_dmsc_ctrl = isp_read_reg(dev, REG_ADDR(isp_dmsc_ctrl));
  363. pr_info("enter %s\n", __func__);
  364. if (!dev->demosaic.enable) {
  365. isp_disable_dmsc(dev);
  366. return 0;
  367. }
  368. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_THR,
  369. dev->demosaic.demosaic_thr);
  370. REG_SET_SLICE(isp_dmsc_ctrl, ISP_DEMOSAIC_DENOISE_STRENGTH,
  371. dev->demosaic.denoise_stren);
  372. isp_write_reg(dev, REG_ADDR(isp_dmsc_ctrl), isp_dmsc_ctrl);
  373. isp_set_dmsc_intp(dev);
  374. isp_set_dmsc_dmoi(dev);
  375. isp_set_dmsc_skin(dev);
  376. isp_enable_dmsc(dev);
  377. isp_set_dmsc_depurple(dev);
  378. isp_set_dmsc_sharpen_line(dev);
  379. isp_set_dmsc_sharpen(dev);
  380. isp_set_dmsc_gfilter(dev);
  381. return 0;
  382. }
  383. #endif