isp_3dnr2.c 15 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. #ifdef __KERNEL__
  54. #include <linux/io.h>
  55. #include <linux/module.h>
  56. #endif
  57. #include "mrv_all_bits.h"
  58. #include "isp_ioctl.h"
  59. #include "isp_types.h"
  60. #ifdef ISP_3DNR_V2
  61. extern MrvAllRegister_t *all_regs;
  62. static void dnr3_hw_init(struct isp_ic_dev *dev)
  63. {
  64. struct isp_3dnr_context *dnr3 = &dev->dnr3;
  65. u32 regVal = 0;
  66. int i, pos;
  67. /* spacial */
  68. u32 update_spacial = 900;
  69. u32 strength_curve_spacial = 64;
  70. u32 thr_edge_v_inv = 1024;
  71. u32 thr_edge_h_inv = 1024;
  72. u32 thr_range_s_inv = 1024;
  73. /* temperal */
  74. u32 update_temperal = 1020;
  75. u32 strength_curve_temperal = 64;
  76. u32 range_t_h = 1;
  77. u32 range_t_v = 1;
  78. u32 thr_range_t_inv = 1024;
  79. u32 thr_motion_inv = 1024;
  80. u32 range_d = 1;
  81. u32 thr_delta_h_inv = 1023;
  82. u32 thr_delta_v_inv = 1023;
  83. u32 thr_delta_t_inv = 1023;
  84. u32 strength = dnr3->strength;
  85. strength = MIN(MAX(strength, 0), 128);
  86. if (dnr3->init) { //for 3dnr init
  87. u32 isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl));
  88. REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_READ_REF_EN, 1);
  89. REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_WRITE_REF_EN, 1);
  90. REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_HORIZONTAL_EN,
  91. dnr3->enable_h);
  92. REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_VERTICAL_EN,
  93. dnr3->enable_v);
  94. REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_TEMPERAL_EN,
  95. dnr3->enable_temperal);
  96. REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_DILATE_EN,
  97. dnr3->enable_dilate);
  98. REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, dnr3->enable);
  99. isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl);
  100. }
  101. regVal = 0;
  102. REG_SET_SLICE(regVal, DENOISE3D_STRENGTH_CURVE_SPACIAL,
  103. strength_curve_spacial);
  104. REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_H_INV, thr_edge_h_inv);
  105. isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_h), regVal);
  106. regVal = 0;
  107. REG_SET_SLICE(regVal, DENOISE3D_STRENGTH_CURVE_TEMPERAL,
  108. strength_curve_temperal);
  109. REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_V_INV, thr_edge_v_inv);
  110. isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_v), regVal);
  111. regVal = 0;
  112. REG_SET_SLICE(regVal, DENOISE3D_RANGE_S_INV, thr_range_s_inv);
  113. isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_s), regVal);
  114. regVal = 0;
  115. REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_H, range_t_h);
  116. REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_V, range_t_v);
  117. REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_INV, thr_range_t_inv);
  118. isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_t), regVal);
  119. regVal = 0;
  120. REG_SET_SLICE(regVal, DENOISE3D_RANGE_D, range_d);
  121. REG_SET_SLICE(regVal, DENOISE3D_MOTION_INV, thr_motion_inv);
  122. isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), regVal);
  123. regVal = 0;
  124. REG_SET_SLICE(regVal, DENOISE3D_DELTA_H_INV, thr_delta_h_inv);
  125. REG_SET_SLICE(regVal, DENOISE3D_DELTA_V_INV, thr_delta_v_inv);
  126. REG_SET_SLICE(regVal, DENOISE3D_DELTA_T_INV, thr_delta_t_inv);
  127. isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), regVal);
  128. /* spacial */
  129. for (i = 0; i < 6; i++) {
  130. regVal = 0;
  131. pos = i * 3;
  132. if (i < 5) {
  133. REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE0,
  134. dnr3->spacial_curve[pos + 0]);
  135. REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE1,
  136. dnr3->spacial_curve[pos + 1]);
  137. REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE2,
  138. dnr3->spacial_curve[pos + 2]);
  139. } else {
  140. REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE1,
  141. dnr3->spacial_curve[pos + 0]);
  142. REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE2,
  143. dnr3->spacial_curve[pos + 1]);
  144. }
  145. isp_write_reg(dev, REG_ADDR(isp_denoise3d_curve_s[i]), regVal);
  146. regVal = 0;
  147. if (i < 5) {
  148. REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE0,
  149. dnr3->temperal_curve[pos + 0]);
  150. REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE1,
  151. dnr3->temperal_curve[pos + 1]);
  152. REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE2,
  153. dnr3->temperal_curve[pos + 2]);
  154. } else {
  155. REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE1,
  156. dnr3->temperal_curve[pos + 0]);
  157. REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE2,
  158. dnr3->temperal_curve[pos + 1]);
  159. }
  160. isp_write_reg(dev, REG_ADDR(isp_denoise3d_curve_t[i]), regVal);
  161. }
  162. regVal = 0;
  163. REG_SET_SLICE(regVal, DENOISE3D_UPDATE_SPACIAL, update_spacial);
  164. REG_SET_SLICE(regVal, DENOISE3D_UPDATE_TEMPERAL, update_temperal);
  165. isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), regVal);
  166. }
  167. int isp_s_3dnr_cmp(struct isp_ic_dev *dev) {
  168. struct isp_3dnr_compress_context *compress = &dev->dnr3.compress;
  169. u32 isp_denoise3d_weight1 = 0; // isp_read_reg(dev, REG_ADDR(isp_denoise3d_weight1));
  170. u32 isp_denoise3d_weight2 = 0; // isp_read_reg(dev, REG_ADDR(isp_denoise3d_weight2));
  171. int i = 0;
  172. for (i = 0; i < 4; i++) {
  173. isp_denoise3d_weight1 |= (compress->weight_down[i] & DENOISE3D_WEIGHT_MASK) << (3 - i) * 4;
  174. }
  175. REG_SET_SLICE(isp_denoise3d_weight1, DENOISE3D_WEIGHT_UP_Y0, compress->weight_up_y[0]);
  176. REG_SET_SLICE(isp_denoise3d_weight1, DENOISE3D_WEIGHT_UP_Y1, compress->weight_up_y[1]);
  177. for (i = 0; i < 8; i++) {
  178. isp_denoise3d_weight2 |= (compress->weight_up[i] & DENOISE3D_WEIGHT_MASK) << (7 - i) * 4;
  179. }
  180. isp_write_reg(dev, REG_ADDR(isp_denoise3d_weight1), isp_denoise3d_weight1);
  181. isp_write_reg(dev, REG_ADDR(isp_denoise3d_weight2), isp_denoise3d_weight2);
  182. return 0;
  183. }
  184. int isp_s_3dnr(struct isp_ic_dev *dev)
  185. {
  186. struct isp_3dnr_context *dnr3 = &dev->dnr3;
  187. u32 isp_denoise3d_strength, isp_denoise3d_motion, isp_denoise3d_delta_inv;
  188. u32 isp_denoise3d_ctrl;
  189. pr_info("enter %s\n", __func__);
  190. if (dnr3->update_bin) {
  191. dnr3_hw_init(dev);
  192. }
  193. isp_denoise3d_strength = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength));
  194. if (!dnr3->enable) {
  195. REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, 0);
  196. } else {
  197. REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, dnr3->strength);
  198. }
  199. isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength),
  200. isp_denoise3d_strength);
  201. isp_denoise3d_motion =
  202. isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion));
  203. REG_SET_SLICE(isp_denoise3d_motion, DENOISE3D_MOTION_INV, dnr3->motion_factor);
  204. isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion),
  205. isp_denoise3d_motion);
  206. isp_denoise3d_delta_inv =
  207. isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv));
  208. REG_SET_SLICE(isp_denoise3d_delta_inv, DENOISE3D_DELTA_T_INV, dnr3->delta_factor);
  209. isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv),
  210. isp_denoise3d_delta_inv);
  211. isp_write_reg(dev, REG_ADDR(isp_denoise3d_dummy_hblank), 0x80);
  212. isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl));
  213. if (dnr3->enable) {
  214. isp_s_3dnr_cmp(dev);
  215. REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, 1);
  216. }
  217. isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl);
  218. return 0;
  219. }
  220. int isp_s_3dnr_motion(struct isp_ic_dev *dev)
  221. {
  222. struct isp_3dnr_context *dnr3 = &dev->dnr3;
  223. u32 isp_denoise3d_motion;
  224. u32 isp_ctrl;
  225. isp_denoise3d_motion =
  226. isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion));
  227. REG_SET_SLICE(isp_denoise3d_motion, DENOISE3D_MOTION_INV, dnr3->motion_factor);
  228. isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion),
  229. isp_denoise3d_motion);
  230. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  231. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  232. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  233. return 0;
  234. }
  235. int isp_s_3dnr_delta(struct isp_ic_dev *dev)
  236. {
  237. struct isp_3dnr_context *dnr3 = &dev->dnr3;
  238. u32 isp_denoise3d_delta_inv;
  239. u32 isp_ctrl;
  240. isp_denoise3d_delta_inv =
  241. isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv));
  242. REG_SET_SLICE(isp_denoise3d_delta_inv, DENOISE3D_DELTA_T_INV, dnr3->delta_factor);
  243. isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv),
  244. isp_denoise3d_delta_inv);
  245. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  246. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  247. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  248. return 0;
  249. }
  250. int isp_u_3dnr(struct isp_ic_dev *dev, struct isp_3dnr_update *dnr3_update)
  251. {
  252. u32 regVal = 0;
  253. pr_info("enter %s\n", __func__);
  254. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength));
  255. REG_SET_SLICE(regVal, DENOISE3D_STRENGTH, dev->dnr3.strength);
  256. isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), regVal);
  257. regVal = 0;
  258. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_edge_h));
  259. REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_H_INV,
  260. dnr3_update->thr_edge_h_inv);
  261. isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_h), regVal);
  262. regVal = 0;
  263. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_edge_v));
  264. REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_V_INV,
  265. dnr3_update->thr_edge_v_inv);
  266. isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_v), regVal);
  267. regVal = 0;
  268. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_range_s));
  269. REG_SET_SLICE(regVal, DENOISE3D_RANGE_S_INV,
  270. dnr3_update->thr_range_s_inv);
  271. isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_s), regVal);
  272. regVal = 0;
  273. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_range_t));
  274. REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_H, dnr3_update->range_t_h);
  275. REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_V, dnr3_update->range_t_v);
  276. REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_INV,
  277. dnr3_update->thr_range_t_inv);
  278. isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_t), regVal);
  279. regVal = 0;
  280. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion));
  281. REG_SET_SLICE(regVal, DENOISE3D_RANGE_D, dnr3_update->range_d);
  282. REG_SET_SLICE(regVal, DENOISE3D_MOTION_INV,
  283. dnr3_update->thr_motion_inv);
  284. isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), regVal);
  285. regVal = 0;
  286. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv));
  287. REG_SET_SLICE(regVal, DENOISE3D_DELTA_H_INV,
  288. dnr3_update->thr_delta_h_inv);
  289. REG_SET_SLICE(regVal, DENOISE3D_DELTA_V_INV,
  290. dnr3_update->thr_delta_v_inv);
  291. REG_SET_SLICE(regVal, DENOISE3D_DELTA_T_INV,
  292. dnr3_update->thr_delta_t_inv);
  293. isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), regVal);
  294. return 0;
  295. }
  296. int isp_g_3dnr(struct isp_ic_dev *dev, u32 * avg)
  297. {
  298. if (!dev || !avg) {
  299. return -EINVAL;
  300. }
  301. *avg = isp_read_reg(dev, REG_ADDR(isp_denoise3d_average));
  302. return 0;
  303. }
  304. int isp_u_3dnr_strength(struct isp_ic_dev *dev)
  305. {
  306. uint32_t isp_denoise3d_strength;
  307. isp_denoise3d_strength = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength));
  308. REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, dev->dnr3.strength);
  309. isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), isp_denoise3d_strength);
  310. return 0;
  311. }
  312. int isp_r_3dnr(struct isp_ic_dev *dev)
  313. {
  314. #ifndef ISP_3DNR_V2_V1
  315. return -1;
  316. #else
  317. u32 in_width, in_height;
  318. u32 size, lval;
  319. u32 miv2_sp2_bus_id;
  320. u32 miv2_sp2_fmt;
  321. u32 miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl));
  322. u32 miv2_imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc));
  323. u32 miv2_sp2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_sp2_ctrl));
  324. //SP2_RAW_PATH_ENABLE is shadow bit, need set SP2_MI_CFG_UPD to update to shadow.
  325. //So here config before set SP2_MI_CFG_UPD
  326. REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_PATH_ENABLE, 1);
  327. REG_SET_SLICE(miv2_ctrl, SP2_RAW_PATH_ENABLE, 1);
  328. isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl);
  329. in_width = isp_read_reg(dev, REG_ADDR(isp_out_h_size));
  330. in_height = isp_read_reg(dev, REG_ADDR(isp_out_v_size));
  331. lval = (in_width * 12 + 127)/ 128;
  332. lval <<= 4;
  333. size = in_height * lval; //raw12 unaligned
  334. //write reference frame config
  335. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_base_ad_init), dev->dnr3.pa);
  336. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_size_init), size);
  337. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_offs_cnt_init), 0);
  338. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_llength), lval);
  339. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_width), in_width);
  340. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_height), in_height);
  341. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_size), size);
  342. miv2_sp2_bus_id = isp_read_reg(dev, REG_ADDR(miv2_sp2_bus_id));
  343. REG_SET_SLICE(miv2_sp2_bus_id, SP2_WR_ID_EN, 1);
  344. REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_ID_EN, 1);
  345. REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_BURST_LEN, 2); //sp2 rd burst lenghth 16
  346. REG_SET_SLICE(miv2_sp2_bus_id, SP2_BUS_SW_EN, 1);
  347. isp_write_reg(dev, REG_ADDR(miv2_sp2_bus_id), miv2_sp2_bus_id);
  348. miv2_sp2_fmt = isp_read_reg(dev, REG_ADDR(miv2_sp2_fmt));
  349. REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_BIT, 2); //raw12
  350. REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_ALIGNED, 0); //unaligned
  351. REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_BIT, 2); //raw12
  352. REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_ALIGNED, 0); //unaligned
  353. isp_write_reg(dev, REG_ADDR(miv2_sp2_fmt), miv2_sp2_fmt);
  354. //read reference frame config
  355. isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_start_ad), dev->dnr3.pa);
  356. isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_width), in_width);
  357. isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_llength), lval);
  358. isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_lval), lval);
  359. isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_size), size);
  360. REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_CFG_UPDATE, 1);
  361. REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_AUTO_UPDATE, 1);
  362. REG_SET_SLICE(miv2_sp2_ctrl, SP2_MI_CFG_UPD, 1);
  363. /* we successfully programmed a buffer to marvin, so we need
  364. * to enable updateing of base and offset registers */
  365. miv2_sp2_ctrl |= (SP2_INIT_BASE_EN_MASK | SP2_INIT_OFFSET_EN_MASK);
  366. isp_write_reg(dev, REG_ADDR(miv2_sp2_ctrl), miv2_sp2_ctrl);
  367. miv2_imsc |= SP2_DMA_RAW_READY_MASK;
  368. isp_write_reg(dev, REG_ADDR(miv2_imsc), miv2_imsc);
  369. return 0;
  370. #endif
  371. }
  372. #endif