isp_3dnr.c 16 KB

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  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. #ifdef __KERNEL__
  54. #include <linux/io.h>
  55. #include <linux/module.h>
  56. #endif
  57. #include "isp_ioctl.h"
  58. #include "mrv_all_bits.h"
  59. #include "isp_types.h"
  60. #ifdef ISP_3DNR
  61. extern MrvAllRegister_t *all_regs;
  62. static void dnr3_hw_init(struct isp_ic_dev *dev)
  63. {
  64. struct isp_3dnr_context *dnr3 = &dev->dnr3;
  65. u32 regVal = 0;
  66. int i, pos;
  67. /* spacial */
  68. u32 update_spacial = 900;
  69. u32 strength_curve_spacial = 64;
  70. u32 thr_edge_v_inv = 1024;
  71. u32 thr_edge_h_inv = 1024;
  72. u32 thr_range_s_inv = 1024;
  73. /* temperal */
  74. u32 update_temperal = 1020;
  75. u32 strength_curve_temperal = 64;
  76. u32 range_t_h = 2;
  77. u32 range_t_v = 2;
  78. u32 thr_range_t_inv = 41943;
  79. u32 thr_motion_inv = 1024;
  80. u32 range_d = 1;
  81. u32 thr_delta_h_inv = 1023;
  82. u32 thr_delta_v_inv = 1023;
  83. u32 thr_delta_t_inv = 1023;
  84. u32 strength = dnr3->strength;
  85. strength = MIN(MAX(strength, 0), 128);
  86. if (dnr3->init) { //for 3dnr init
  87. u32 isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl));
  88. REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_HORIZONTAL_EN,
  89. dnr3->enable_h);
  90. REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_VERTICAL_EN,
  91. dnr3->enable_v);
  92. REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_TEMPERAL_EN,
  93. dnr3->enable_temperal);
  94. REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_DILATE_EN,
  95. dnr3->enable_dilate);
  96. REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, dnr3->enable);
  97. isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl);
  98. }
  99. regVal = 0;
  100. REG_SET_SLICE(regVal, DENOISE3D_STRENGTH_CURVE_SPACIAL,
  101. strength_curve_spacial);
  102. REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_H_INV, thr_edge_h_inv);
  103. isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_h), regVal);
  104. regVal = 0;
  105. REG_SET_SLICE(regVal, DENOISE3D_STRENGTH_CURVE_TEMPERAL,
  106. strength_curve_temperal);
  107. REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_V_INV, thr_edge_v_inv);
  108. isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_v), regVal);
  109. regVal = 0;
  110. REG_SET_SLICE(regVal, DENOISE3D_RANGE_S_INV, thr_range_s_inv);
  111. isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_s), regVal);
  112. regVal = 0;
  113. REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_H, range_t_h);
  114. REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_V, range_t_v);
  115. REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_INV, thr_range_t_inv);
  116. isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_t), regVal);
  117. regVal = 0;
  118. REG_SET_SLICE(regVal, DENOISE3D_RANGE_D, range_d);
  119. REG_SET_SLICE(regVal, DENOISE3D_MOTION_INV, thr_motion_inv);
  120. isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), regVal);
  121. regVal = 0;
  122. REG_SET_SLICE(regVal, DENOISE3D_DELTA_H_INV, thr_delta_h_inv);
  123. REG_SET_SLICE(regVal, DENOISE3D_DELTA_V_INV, thr_delta_v_inv);
  124. REG_SET_SLICE(regVal, DENOISE3D_DELTA_T_INV, thr_delta_t_inv);
  125. isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), regVal);
  126. /* spacial */
  127. for (i = 0; i < 6; i++) {
  128. regVal = 0;
  129. pos = i * 3;
  130. if (i < 5) {
  131. REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE0,
  132. dnr3->spacial_curve[pos + 0]);
  133. REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE1,
  134. dnr3->spacial_curve[pos + 1]);
  135. REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE2,
  136. dnr3->spacial_curve[pos + 2]);
  137. } else {
  138. REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE1,
  139. dnr3->spacial_curve[pos + 0]);
  140. REG_SET_SLICE(regVal, DENOISE3D_SPACIAL_CURVE2,
  141. dnr3->spacial_curve[pos + 1]);
  142. }
  143. isp_write_reg(dev, REG_ADDR(isp_denoise3d_curve_s[i]), regVal);
  144. regVal = 0;
  145. if (i < 5) {
  146. REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE0,
  147. dnr3->temperal_curve[pos + 0]);
  148. REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE1,
  149. dnr3->temperal_curve[pos + 1]);
  150. REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE2,
  151. dnr3->temperal_curve[pos + 2]);
  152. } else {
  153. REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE1,
  154. dnr3->temperal_curve[pos + 0]);
  155. REG_SET_SLICE(regVal, DENOISE3D_TEMPERAL_CURVE2,
  156. dnr3->temperal_curve[pos + 1]);
  157. }
  158. isp_write_reg(dev, REG_ADDR(isp_denoise3d_curve_t[i]), regVal);
  159. }
  160. regVal = 0;
  161. REG_SET_SLICE(regVal, DENOISE3D_UPDATE_SPACIAL, update_spacial);
  162. REG_SET_SLICE(regVal, DENOISE3D_UPDATE_TEMPERAL, update_temperal);
  163. isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), regVal);
  164. isp_write_reg(dev, REG_ADDR(isp_denoise3d_dummy_hblank), 0x80);
  165. }
  166. int isp_u_3dnr_strength(struct isp_ic_dev *dev)
  167. {
  168. #ifndef ISP_3DNR
  169. //pr_err("Not supported 3dnr\n");
  170. return -1;
  171. #else
  172. struct isp_3dnr_context *dnr3 = &dev->dnr3;
  173. u32 isp_ctrl;
  174. u32 isp_denoise3d_strength;
  175. isp_denoise3d_strength = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength));
  176. REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, dnr3->strength);
  177. isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), isp_denoise3d_strength);
  178. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  179. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  180. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  181. return 0;
  182. #endif
  183. }
  184. int isp_s_3dnr(struct isp_ic_dev *dev)
  185. {
  186. #ifndef ISP_3DNR
  187. //pr_err("Not supported 3dnr\n");
  188. return -1;
  189. #else
  190. u32 isp_denoise3d_ctrl;
  191. struct isp_3dnr_context *dnr3 = &dev->dnr3;
  192. u32 isp_denoise3d_strength, isp_denoise3d_motion, isp_denoise3d_delta_inv;
  193. pr_info("enter %s\n", __func__);
  194. if (dnr3->update_bin) {
  195. dnr3_hw_init(dev);
  196. }
  197. isp_denoise3d_motion =
  198. isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion));
  199. REG_SET_SLICE(isp_denoise3d_motion, DENOISE3D_MOTION_INV, dnr3->motion_factor);
  200. isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion),
  201. isp_denoise3d_motion);
  202. isp_denoise3d_delta_inv =
  203. isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv));
  204. REG_SET_SLICE(isp_denoise3d_delta_inv, DENOISE3D_DELTA_T_INV, dnr3->delta_factor);
  205. isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv),
  206. isp_denoise3d_delta_inv);
  207. isp_denoise3d_strength = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength));
  208. #ifndef NR200
  209. if (!dnr3->enable) {
  210. REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, 0);
  211. } else {
  212. REG_SET_SLICE(isp_denoise3d_strength, DENOISE3D_STRENGTH, dnr3->strength);
  213. isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl));
  214. REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, dnr3->enable);
  215. isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl);
  216. }
  217. isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), isp_denoise3d_strength);
  218. #else
  219. isp_denoise3d_ctrl = isp_read_reg(dev, REG_ADDR(isp_denoise3d_ctrl));
  220. REG_SET_SLICE(isp_denoise3d_ctrl, DENOISE3D_ENABLE, dnr3->enable);
  221. isp_write_reg(dev, REG_ADDR(isp_denoise3d_ctrl), isp_denoise3d_ctrl);
  222. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  223. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  224. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  225. #endif
  226. return 0;
  227. #endif
  228. }
  229. int isp_s_3dnr_motion(struct isp_ic_dev *dev)
  230. {
  231. #ifndef ISP_3DNR
  232. pr_err("Not supported 3dnr\n");
  233. return -1;
  234. #else
  235. struct isp_3dnr_context *dnr3 = &dev->dnr3;
  236. u32 isp_denoise3d_motion;
  237. u32 isp_ctrl;
  238. isp_denoise3d_motion =
  239. isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion));
  240. REG_SET_SLICE(isp_denoise3d_motion, DENOISE3D_MOTION_INV, dnr3->motion_factor);
  241. isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion),
  242. isp_denoise3d_motion);
  243. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  244. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  245. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  246. #endif
  247. return 0;
  248. }
  249. int isp_s_3dnr_delta(struct isp_ic_dev *dev)
  250. {
  251. #ifndef ISP_3DNR
  252. pr_err("Not supported 3dnr\n");
  253. return -1;
  254. #else
  255. struct isp_3dnr_context *dnr3 = &dev->dnr3;
  256. u32 isp_denoise3d_delta_inv;
  257. u32 isp_ctrl;
  258. isp_denoise3d_delta_inv =
  259. isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv));
  260. REG_SET_SLICE(isp_denoise3d_delta_inv, DENOISE3D_DELTA_T_INV, dnr3->delta_factor);
  261. isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv),
  262. isp_denoise3d_delta_inv);
  263. isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  264. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  265. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  266. #endif
  267. return 0;
  268. }
  269. int isp_u_3dnr(struct isp_ic_dev *dev, struct isp_3dnr_update *dnr3_update)
  270. {
  271. #ifndef ISP_3DNR
  272. pr_err("unsupported function: %s", __func__);
  273. return -EINVAL;
  274. #else
  275. u32 regVal = 0;
  276. pr_info("enter %s\n", __func__);
  277. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_strength));
  278. REG_SET_SLICE(regVal, DENOISE3D_STRENGTH, dev->dnr3.strength);
  279. isp_write_reg(dev, REG_ADDR(isp_denoise3d_strength), regVal);
  280. regVal = 0;
  281. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_edge_h));
  282. REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_H_INV,
  283. dnr3_update->thr_edge_h_inv);
  284. isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_h), regVal);
  285. regVal = 0;
  286. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_edge_v));
  287. REG_SET_SLICE(regVal, DENOISE3D_THR_EDGE_V_INV,
  288. dnr3_update->thr_edge_v_inv);
  289. isp_write_reg(dev, REG_ADDR(isp_denoise3d_edge_v), regVal);
  290. regVal = 0;
  291. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_range_s));
  292. REG_SET_SLICE(regVal, DENOISE3D_RANGE_S_INV,
  293. dnr3_update->thr_range_s_inv);
  294. isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_s), regVal);
  295. regVal = 0;
  296. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_range_t));
  297. REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_H, dnr3_update->range_t_h);
  298. REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_V, dnr3_update->range_t_v);
  299. REG_SET_SLICE(regVal, DENOISE3D_RANGE_T_INV,
  300. dnr3_update->thr_range_t_inv);
  301. isp_write_reg(dev, REG_ADDR(isp_denoise3d_range_t), regVal);
  302. regVal = 0;
  303. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_motion));
  304. REG_SET_SLICE(regVal, DENOISE3D_RANGE_D, dnr3_update->range_d);
  305. REG_SET_SLICE(regVal, DENOISE3D_MOTION_INV,
  306. dnr3_update->thr_motion_inv);
  307. isp_write_reg(dev, REG_ADDR(isp_denoise3d_motion), regVal);
  308. regVal = 0;
  309. regVal = isp_read_reg(dev, REG_ADDR(isp_denoise3d_delta_inv));
  310. REG_SET_SLICE(regVal, DENOISE3D_DELTA_H_INV,
  311. dnr3_update->thr_delta_h_inv);
  312. REG_SET_SLICE(regVal, DENOISE3D_DELTA_V_INV,
  313. dnr3_update->thr_delta_v_inv);
  314. REG_SET_SLICE(regVal, DENOISE3D_DELTA_T_INV,
  315. dnr3_update->thr_delta_t_inv);
  316. isp_write_reg(dev, REG_ADDR(isp_denoise3d_delta_inv), regVal);
  317. #ifdef NR200
  318. u32 isp_ctrl = isp_read_reg(dev, REG_ADDR(isp_ctrl));
  319. REG_SET_SLICE(isp_ctrl, MRV_ISP_ISP_GEN_CFG_UPD, 1);
  320. isp_write_reg(dev, REG_ADDR(isp_ctrl), isp_ctrl);
  321. #endif
  322. return 0;
  323. #endif
  324. }
  325. int isp_g_3dnr(struct isp_ic_dev *dev, u32 * avg)
  326. {
  327. if (!dev || !avg) {
  328. return -EINVAL;
  329. }
  330. *avg = isp_read_reg(dev, REG_ADDR(isp_denoise3d_average));
  331. return 0;
  332. }
  333. int isp_r_3dnr(struct isp_ic_dev *dev)
  334. {
  335. #ifndef ISP_3DNR
  336. return -1;
  337. #else
  338. u32 in_width, in_height;
  339. u32 size, lval;
  340. u32 miv2_sp2_bus_id;
  341. u32 miv2_sp2_fmt;
  342. u32 miv2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_ctrl));
  343. u32 miv2_imsc = isp_read_reg(dev, REG_ADDR(miv2_imsc));
  344. u32 miv2_sp2_ctrl = isp_read_reg(dev, REG_ADDR(miv2_sp2_ctrl));
  345. //SP2_RAW_PATH_ENABLE is shadow bit, need set SP2_MI_CFG_UPD to update to shadow.
  346. //So here config before set SP2_MI_CFG_UPD
  347. REG_SET_SLICE(miv2_ctrl, SP2_RAW_RDMA_PATH_ENABLE, 1);
  348. REG_SET_SLICE(miv2_ctrl, SP2_RAW_PATH_ENABLE, 1);
  349. isp_write_reg(dev, REG_ADDR(miv2_ctrl), miv2_ctrl);
  350. #ifndef NR200
  351. in_width = isp_read_reg(dev, REG_ADDR(isp_acq_h_size));
  352. in_height = isp_read_reg(dev, REG_ADDR(isp_acq_v_size));
  353. #else
  354. in_width = isp_read_reg(dev, REG_ADDR(isp_out_h_size));
  355. in_height = isp_read_reg(dev, REG_ADDR(isp_out_v_size));
  356. #endif
  357. lval = (in_width * 12 + 127)/ 128;
  358. lval <<= 4;
  359. size = in_height * lval; //raw12 unaligned
  360. //write reference frame config
  361. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_base_ad_init), dev->dnr3.pa);
  362. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_size_init), size);
  363. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_offs_cnt_init), 0);
  364. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_llength), lval);
  365. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_width), in_width);
  366. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_height), in_height);
  367. isp_write_reg(dev, REG_ADDR(miv2_sp2_raw_pic_size), size);
  368. miv2_sp2_bus_id = isp_read_reg(dev, REG_ADDR(miv2_sp2_bus_id));
  369. REG_SET_SLICE(miv2_sp2_bus_id, SP2_WR_ID_EN, 1);
  370. REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_ID_EN, 1);
  371. REG_SET_SLICE(miv2_sp2_bus_id, SP2_RD_BURST_LEN, 2); //sp2 rd burst lenghth 16
  372. REG_SET_SLICE(miv2_sp2_bus_id, SP2_BUS_SW_EN, 1);
  373. isp_write_reg(dev, REG_ADDR(miv2_sp2_bus_id), miv2_sp2_bus_id);
  374. miv2_sp2_fmt = isp_read_reg(dev, REG_ADDR(miv2_sp2_fmt));
  375. REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_BIT, 2); //raw12
  376. REG_SET_SLICE(miv2_sp2_fmt, SP2_WR_RAW_ALIGNED, 0); //unaligned
  377. REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_BIT, 2); //raw12
  378. REG_SET_SLICE(miv2_sp2_fmt, SP2_RD_RAW_ALIGNED, 0); //unaligned
  379. isp_write_reg(dev, REG_ADDR(miv2_sp2_fmt), miv2_sp2_fmt);
  380. //read reference frame config
  381. isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_start_ad), dev->dnr3.pa);
  382. isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_width), in_width);
  383. isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_llength), lval);
  384. isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_lval), lval);
  385. isp_write_reg(dev, REG_ADDR(miv2_sp2_dma_raw_pic_size), size);
  386. REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_CFG_UPDATE, 1);
  387. REG_SET_SLICE(miv2_sp2_ctrl, SP2_RD_RAW_AUTO_UPDATE, 1);
  388. REG_SET_SLICE(miv2_sp2_ctrl, SP2_MI_CFG_UPD, 1);
  389. /* we successfully programmed a buffer to marvin, so we need
  390. * to enable updateing of base and offset registers */
  391. miv2_sp2_ctrl |= (SP2_INIT_BASE_EN_MASK | SP2_INIT_OFFSET_EN_MASK);
  392. isp_write_reg(dev, REG_ADDR(miv2_sp2_ctrl), miv2_sp2_ctrl);
  393. miv2_imsc |= SP2_DMA_RAW_READY_MASK;
  394. isp_write_reg(dev, REG_ADDR(miv2_imsc), miv2_imsc);
  395. return 0;
  396. #endif
  397. }
  398. #endif