dwe_isr.c 5.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183
  1. /****************************************************************************
  2. *
  3. * The MIT License (MIT)
  4. *
  5. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the "Software"),
  9. * to deal in the Software without restriction, including without limitation
  10. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11. * and/or sell copies of the Software, and to permit persons to whom the
  12. * Software is furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  20. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. *****************************************************************************
  26. *
  27. * The GPL License (GPL)
  28. *
  29. * Copyright (c) 2020 VeriSilicon Holdings Co., Ltd.
  30. *
  31. * This program is free software; you can redistribute it and/or
  32. * modify it under the terms of the GNU General Public License
  33. * as published by the Free Software Foundation; either version 2
  34. * of the License, or (at your option) any later version.
  35. *
  36. * This program is distributed in the hope that it will be useful,
  37. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  39. * GNU General Public License for more details.
  40. *
  41. * You should have received a copy of the GNU General Public License
  42. * along with this program;
  43. *
  44. *****************************************************************************
  45. *
  46. * Note: This software is released under dual MIT and GPL licenses. A
  47. * recipient may use this file under the terms of either the MIT license or
  48. * GPL License. If you wish to use only one license not the other, you can
  49. * indicate your decision by deleting one of the above license notices in your
  50. * version of this file.
  51. *
  52. *****************************************************************************/
  53. #ifdef __KERNEL__
  54. # include "dwe_driver.h"
  55. # include "video/vvbuf.h"
  56. #endif
  57. #include "dwe_ioctl.h"
  58. #include "dwe_regs.h"
  59. #if defined(__KERNEL__) && defined(ENABLE_IRQ)
  60. static int update_dma_buffer(struct dwe_ic_dev *dev)
  61. {
  62. int no_dist_map_err, overflow_err;
  63. int which;
  64. u32 dewarp_ctrl;
  65. dwe_enable_bus(dev, 0);
  66. if (dev->dst)
  67. return -EBUSY;
  68. if (dev->src) {
  69. vvbuf_ready(dev->sink_bctx, dev->src->pad, dev->src);
  70. dev->src = NULL;
  71. }
  72. dev->src = vvbuf_try_dqbuf(dev->sink_bctx);
  73. if (!dev->src) {
  74. dev->error |= BUF_ERR_UNDERFLOW;
  75. return -ENOMEM;
  76. }
  77. dev->error &= ~BUF_ERR_UNDERFLOW;
  78. if (!dev->get_index) {
  79. dev->error |= BUF_ERR_WRONGSTATE;
  80. dev->src = NULL;
  81. return -ENXIO;
  82. }
  83. dev->index = dev->get_index(dev, dev->src);
  84. if (dev->index < 0 || dev->index >= MAX_DWE_NUM) {
  85. dev->error |= BUF_ERR_WRONGSTATE;
  86. dev->src = NULL;
  87. return -ENXIO;
  88. }
  89. dev->error &= ~BUF_ERR_WRONGSTATE;
  90. if (!(*dev->state[dev->index] & STATE_DRIVER_STARTED)) {
  91. vvbuf_try_dqbuf_done(dev->sink_bctx, dev->src);
  92. vvbuf_ready(dev->sink_bctx, dev->src->pad, dev->src);
  93. dev->error |= BUF_ERR_UNDERFLOW;
  94. dev->src = NULL;
  95. return 0;
  96. }
  97. no_dist_map_err = BUF_ERR_NO_DIST_MAP0 << dev->index;
  98. if (!dev->dist_map[dev->index]) {
  99. dev->error |= no_dist_map_err;
  100. dev->src = NULL;
  101. return -ENOMEM;
  102. }
  103. dev->error &= ~no_dist_map_err;
  104. overflow_err = BUF_ERR_OVERFLOW0 << dev->index;
  105. dev->dst = vvbuf_try_dqbuf(dev->src_bctx[dev->index]);
  106. if (!dev->dst) {
  107. if (!(*dev->state[dev->index] & STATE_STREAM_STARTED)) {
  108. vvbuf_try_dqbuf_done(dev->sink_bctx, dev->src);
  109. vvbuf_ready(dev->sink_bctx, dev->src->pad, dev->src);
  110. }
  111. dev->error |= overflow_err;
  112. dev->src = NULL;
  113. return -ENOMEM;
  114. }
  115. dev->error &= ~overflow_err;
  116. vvbuf_try_dqbuf_done(dev->sink_bctx, dev->src);
  117. vvbuf_try_dqbuf_done(dev->src_bctx[dev->index], dev->dst);
  118. which = dev->which[dev->index];
  119. dwe_s_params(dev, &dev->info[dev->index][which]);
  120. dwe_set_buffer(dev, &dev->info[dev->index][which], dev->dst->dma);
  121. dwe_set_lut(dev, dev->dist_map[dev->index][which]);
  122. dwe_start_dma_read(dev, &dev->info[dev->index][which], dev->src->dma);
  123. dewarp_ctrl = dwe_read_reg(dev, DEWARP_CTRL);
  124. dwe_write_reg(dev, DEWARP_CTRL, dewarp_ctrl | 2);
  125. dwe_write_reg(dev, DEWARP_CTRL, dewarp_ctrl);
  126. dwe_write_reg(dev, INTERRUPT_STATUS, INT_MSK_STATUS_MASK);
  127. dwe_enable_bus(dev, 1);
  128. return 0;
  129. }
  130. int dwe_on_buf_update(struct dwe_ic_dev *dev)
  131. {
  132. int rc = 0;
  133. unsigned long flags;
  134. if (dev) {
  135. spin_lock_irqsave(&dev->irqlock, flags);
  136. if (dev->error)
  137. rc = update_dma_buffer(dev);
  138. spin_unlock_irqrestore(&dev->irqlock, flags);
  139. }
  140. return rc;
  141. }
  142. void dwe_clear_interrupts(struct dwe_ic_dev *dev)
  143. {
  144. u32 status;
  145. u32 clr;
  146. status = dwe_read_reg(dev, INTERRUPT_STATUS);
  147. clr = (status & 0xFF) << 24;
  148. dwe_write_reg(dev, INTERRUPT_STATUS, clr);
  149. }
  150. irqreturn_t dwe_hw_isr(int irq, void *data)
  151. {
  152. struct dwe_ic_dev *dev = (struct dwe_ic_dev *)data;
  153. u32 status;
  154. u32 clr;
  155. unsigned long flags;
  156. if (!dev)
  157. return IRQ_HANDLED;
  158. status = dwe_read_reg(dev, INTERRUPT_STATUS);
  159. if (status & INT_FRAME_DONE) {
  160. clr = (status & 0xFF) << 24;
  161. dwe_write_reg(dev, INTERRUPT_STATUS, clr);
  162. spin_lock_irqsave(&dev->irqlock, flags);
  163. if (dev->dst) {
  164. vvbuf_ready(dev->src_bctx[dev->index],
  165. dev->dst->pad, dev->dst);
  166. dev->dst = NULL;
  167. }
  168. update_dma_buffer(dev);
  169. spin_unlock_irqrestore(&dev->irqlock, flags);
  170. }
  171. return IRQ_HANDLED;
  172. }
  173. #endif